mthca_cq.c revision ed23a72778f3dbd465e55b06fe31629e7e1dd2f3
1/* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006 Cisco Systems, Inc. All rights reserved. 5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 * 36 * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $ 37 */ 38 39#include <linux/hardirq.h> 40 41#include <asm/io.h> 42 43#include <rdma/ib_pack.h> 44 45#include "mthca_dev.h" 46#include "mthca_cmd.h" 47#include "mthca_memfree.h" 48 49enum { 50 MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE 51}; 52 53enum { 54 MTHCA_CQ_ENTRY_SIZE = 0x20 55}; 56 57enum { 58 MTHCA_ATOMIC_BYTE_LEN = 8 59}; 60 61/* 62 * Must be packed because start is 64 bits but only aligned to 32 bits. 63 */ 64struct mthca_cq_context { 65 __be32 flags; 66 __be64 start; 67 __be32 logsize_usrpage; 68 __be32 error_eqn; /* Tavor only */ 69 __be32 comp_eqn; 70 __be32 pd; 71 __be32 lkey; 72 __be32 last_notified_index; 73 __be32 solicit_producer_index; 74 __be32 consumer_index; 75 __be32 producer_index; 76 __be32 cqn; 77 __be32 ci_db; /* Arbel only */ 78 __be32 state_db; /* Arbel only */ 79 u32 reserved; 80} __attribute__((packed)); 81 82#define MTHCA_CQ_STATUS_OK ( 0 << 28) 83#define MTHCA_CQ_STATUS_OVERFLOW ( 9 << 28) 84#define MTHCA_CQ_STATUS_WRITE_FAIL (10 << 28) 85#define MTHCA_CQ_FLAG_TR ( 1 << 18) 86#define MTHCA_CQ_FLAG_OI ( 1 << 17) 87#define MTHCA_CQ_STATE_DISARMED ( 0 << 8) 88#define MTHCA_CQ_STATE_ARMED ( 1 << 8) 89#define MTHCA_CQ_STATE_ARMED_SOL ( 4 << 8) 90#define MTHCA_EQ_STATE_FIRED (10 << 8) 91 92enum { 93 MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe 94}; 95 96enum { 97 SYNDROME_LOCAL_LENGTH_ERR = 0x01, 98 SYNDROME_LOCAL_QP_OP_ERR = 0x02, 99 SYNDROME_LOCAL_EEC_OP_ERR = 0x03, 100 SYNDROME_LOCAL_PROT_ERR = 0x04, 101 SYNDROME_WR_FLUSH_ERR = 0x05, 102 SYNDROME_MW_BIND_ERR = 0x06, 103 SYNDROME_BAD_RESP_ERR = 0x10, 104 SYNDROME_LOCAL_ACCESS_ERR = 0x11, 105 SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12, 106 SYNDROME_REMOTE_ACCESS_ERR = 0x13, 107 SYNDROME_REMOTE_OP_ERR = 0x14, 108 SYNDROME_RETRY_EXC_ERR = 0x15, 109 SYNDROME_RNR_RETRY_EXC_ERR = 0x16, 110 SYNDROME_LOCAL_RDD_VIOL_ERR = 0x20, 111 SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21, 112 SYNDROME_REMOTE_ABORTED_ERR = 0x22, 113 SYNDROME_INVAL_EECN_ERR = 0x23, 114 SYNDROME_INVAL_EEC_STATE_ERR = 0x24 115}; 116 117struct mthca_cqe { 118 __be32 my_qpn; 119 __be32 my_ee; 120 __be32 rqpn; 121 __be16 sl_g_mlpath; 122 __be16 rlid; 123 __be32 imm_etype_pkey_eec; 124 __be32 byte_cnt; 125 __be32 wqe; 126 u8 opcode; 127 u8 is_send; 128 u8 reserved; 129 u8 owner; 130}; 131 132struct mthca_err_cqe { 133 __be32 my_qpn; 134 u32 reserved1[3]; 135 u8 syndrome; 136 u8 vendor_err; 137 __be16 db_cnt; 138 u32 reserved2; 139 __be32 wqe; 140 u8 opcode; 141 u8 reserved3[2]; 142 u8 owner; 143}; 144 145#define MTHCA_CQ_ENTRY_OWNER_SW (0 << 7) 146#define MTHCA_CQ_ENTRY_OWNER_HW (1 << 7) 147 148#define MTHCA_TAVOR_CQ_DB_INC_CI (1 << 24) 149#define MTHCA_TAVOR_CQ_DB_REQ_NOT (2 << 24) 150#define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL (3 << 24) 151#define MTHCA_TAVOR_CQ_DB_SET_CI (4 << 24) 152#define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24) 153 154#define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL (1 << 24) 155#define MTHCA_ARBEL_CQ_DB_REQ_NOT (2 << 24) 156#define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24) 157 158static inline struct mthca_cqe *get_cqe_from_buf(struct mthca_cq_buf *buf, 159 int entry) 160{ 161 if (buf->is_direct) 162 return buf->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE); 163 else 164 return buf->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf 165 + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE; 166} 167 168static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry) 169{ 170 return get_cqe_from_buf(&cq->buf, entry); 171} 172 173static inline struct mthca_cqe *cqe_sw(struct mthca_cqe *cqe) 174{ 175 return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe; 176} 177 178static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq) 179{ 180 return cqe_sw(get_cqe(cq, cq->cons_index & cq->ibcq.cqe)); 181} 182 183static inline void set_cqe_hw(struct mthca_cqe *cqe) 184{ 185 cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW; 186} 187 188static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr) 189{ 190 __be32 *cqe = cqe_ptr; 191 192 (void) cqe; /* avoid warning if mthca_dbg compiled away... */ 193 mthca_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n", 194 be32_to_cpu(cqe[0]), be32_to_cpu(cqe[1]), be32_to_cpu(cqe[2]), 195 be32_to_cpu(cqe[3]), be32_to_cpu(cqe[4]), be32_to_cpu(cqe[5]), 196 be32_to_cpu(cqe[6]), be32_to_cpu(cqe[7])); 197} 198 199/* 200 * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index 201 * should be correct before calling update_cons_index(). 202 */ 203static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq, 204 int incr) 205{ 206 __be32 doorbell[2]; 207 208 if (mthca_is_memfree(dev)) { 209 *cq->set_ci_db = cpu_to_be32(cq->cons_index); 210 wmb(); 211 } else { 212 doorbell[0] = cpu_to_be32(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn); 213 doorbell[1] = cpu_to_be32(incr - 1); 214 215 mthca_write64(doorbell, 216 dev->kar + MTHCA_CQ_DOORBELL, 217 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 218 /* 219 * Make sure doorbells don't leak out of CQ spinlock 220 * and reach the HCA out of order: 221 */ 222 mmiowb(); 223 } 224} 225 226void mthca_cq_completion(struct mthca_dev *dev, u32 cqn) 227{ 228 struct mthca_cq *cq; 229 230 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1)); 231 232 if (!cq) { 233 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn); 234 return; 235 } 236 237 ++cq->arm_sn; 238 239 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 240} 241 242void mthca_cq_event(struct mthca_dev *dev, u32 cqn, 243 enum ib_event_type event_type) 244{ 245 struct mthca_cq *cq; 246 struct ib_event event; 247 248 spin_lock(&dev->cq_table.lock); 249 250 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1)); 251 if (cq) 252 ++cq->refcount; 253 254 spin_unlock(&dev->cq_table.lock); 255 256 if (!cq) { 257 mthca_warn(dev, "Async event for bogus CQ %08x\n", cqn); 258 return; 259 } 260 261 event.device = &dev->ib_dev; 262 event.event = event_type; 263 event.element.cq = &cq->ibcq; 264 if (cq->ibcq.event_handler) 265 cq->ibcq.event_handler(&event, cq->ibcq.cq_context); 266 267 spin_lock(&dev->cq_table.lock); 268 if (!--cq->refcount) 269 wake_up(&cq->wait); 270 spin_unlock(&dev->cq_table.lock); 271} 272 273static inline int is_recv_cqe(struct mthca_cqe *cqe) 274{ 275 if ((cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) == 276 MTHCA_ERROR_CQE_OPCODE_MASK) 277 return !(cqe->opcode & 0x01); 278 else 279 return !(cqe->is_send & 0x80); 280} 281 282void mthca_cq_clean(struct mthca_dev *dev, struct mthca_cq *cq, u32 qpn, 283 struct mthca_srq *srq) 284{ 285 struct mthca_cqe *cqe; 286 u32 prod_index; 287 int nfreed = 0; 288 289 spin_lock_irq(&cq->lock); 290 291 /* 292 * First we need to find the current producer index, so we 293 * know where to start cleaning from. It doesn't matter if HW 294 * adds new entries after this loop -- the QP we're worried 295 * about is already in RESET, so the new entries won't come 296 * from our QP and therefore don't need to be checked. 297 */ 298 for (prod_index = cq->cons_index; 299 cqe_sw(get_cqe(cq, prod_index & cq->ibcq.cqe)); 300 ++prod_index) 301 if (prod_index == cq->cons_index + cq->ibcq.cqe) 302 break; 303 304 if (0) 305 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n", 306 qpn, cq->cqn, cq->cons_index, prod_index); 307 308 /* 309 * Now sweep backwards through the CQ, removing CQ entries 310 * that match our QP by copying older entries on top of them. 311 */ 312 while ((int) --prod_index - (int) cq->cons_index >= 0) { 313 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 314 if (cqe->my_qpn == cpu_to_be32(qpn)) { 315 if (srq && is_recv_cqe(cqe)) 316 mthca_free_srq_wqe(srq, be32_to_cpu(cqe->wqe)); 317 ++nfreed; 318 } else if (nfreed) 319 memcpy(get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe), 320 cqe, MTHCA_CQ_ENTRY_SIZE); 321 } 322 323 if (nfreed) { 324 wmb(); 325 cq->cons_index += nfreed; 326 update_cons_index(dev, cq, nfreed); 327 } 328 329 spin_unlock_irq(&cq->lock); 330} 331 332void mthca_cq_resize_copy_cqes(struct mthca_cq *cq) 333{ 334 int i; 335 336 /* 337 * In Tavor mode, the hardware keeps the consumer and producer 338 * indices mod the CQ size. Since we might be making the CQ 339 * bigger, we need to deal with the case where the producer 340 * index wrapped around before the CQ was resized. 341 */ 342 if (!mthca_is_memfree(to_mdev(cq->ibcq.device)) && 343 cq->ibcq.cqe < cq->resize_buf->cqe) { 344 cq->cons_index &= cq->ibcq.cqe; 345 if (cqe_sw(get_cqe(cq, cq->ibcq.cqe))) 346 cq->cons_index -= cq->ibcq.cqe + 1; 347 } 348 349 for (i = cq->cons_index; cqe_sw(get_cqe(cq, i & cq->ibcq.cqe)); ++i) 350 memcpy(get_cqe_from_buf(&cq->resize_buf->buf, 351 i & cq->resize_buf->cqe), 352 get_cqe(cq, i & cq->ibcq.cqe), MTHCA_CQ_ENTRY_SIZE); 353} 354 355int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent) 356{ 357 int ret; 358 int i; 359 360 ret = mthca_buf_alloc(dev, nent * MTHCA_CQ_ENTRY_SIZE, 361 MTHCA_MAX_DIRECT_CQ_SIZE, 362 &buf->queue, &buf->is_direct, 363 &dev->driver_pd, 1, &buf->mr); 364 if (ret) 365 return ret; 366 367 for (i = 0; i < nent; ++i) 368 set_cqe_hw(get_cqe_from_buf(buf, i)); 369 370 return 0; 371} 372 373void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe) 374{ 375 mthca_buf_free(dev, (cqe + 1) * MTHCA_CQ_ENTRY_SIZE, &buf->queue, 376 buf->is_direct, &buf->mr); 377} 378 379static void handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq, 380 struct mthca_qp *qp, int wqe_index, int is_send, 381 struct mthca_err_cqe *cqe, 382 struct ib_wc *entry, int *free_cqe) 383{ 384 int dbd; 385 __be32 new_wqe; 386 387 if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) { 388 mthca_dbg(dev, "local QP operation err " 389 "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n", 390 be32_to_cpu(cqe->my_qpn), be32_to_cpu(cqe->wqe), 391 cq->cqn, cq->cons_index); 392 dump_cqe(dev, cqe); 393 } 394 395 /* 396 * For completions in error, only work request ID, status, vendor error 397 * (and freed resource count for RD) have to be set. 398 */ 399 switch (cqe->syndrome) { 400 case SYNDROME_LOCAL_LENGTH_ERR: 401 entry->status = IB_WC_LOC_LEN_ERR; 402 break; 403 case SYNDROME_LOCAL_QP_OP_ERR: 404 entry->status = IB_WC_LOC_QP_OP_ERR; 405 break; 406 case SYNDROME_LOCAL_EEC_OP_ERR: 407 entry->status = IB_WC_LOC_EEC_OP_ERR; 408 break; 409 case SYNDROME_LOCAL_PROT_ERR: 410 entry->status = IB_WC_LOC_PROT_ERR; 411 break; 412 case SYNDROME_WR_FLUSH_ERR: 413 entry->status = IB_WC_WR_FLUSH_ERR; 414 break; 415 case SYNDROME_MW_BIND_ERR: 416 entry->status = IB_WC_MW_BIND_ERR; 417 break; 418 case SYNDROME_BAD_RESP_ERR: 419 entry->status = IB_WC_BAD_RESP_ERR; 420 break; 421 case SYNDROME_LOCAL_ACCESS_ERR: 422 entry->status = IB_WC_LOC_ACCESS_ERR; 423 break; 424 case SYNDROME_REMOTE_INVAL_REQ_ERR: 425 entry->status = IB_WC_REM_INV_REQ_ERR; 426 break; 427 case SYNDROME_REMOTE_ACCESS_ERR: 428 entry->status = IB_WC_REM_ACCESS_ERR; 429 break; 430 case SYNDROME_REMOTE_OP_ERR: 431 entry->status = IB_WC_REM_OP_ERR; 432 break; 433 case SYNDROME_RETRY_EXC_ERR: 434 entry->status = IB_WC_RETRY_EXC_ERR; 435 break; 436 case SYNDROME_RNR_RETRY_EXC_ERR: 437 entry->status = IB_WC_RNR_RETRY_EXC_ERR; 438 break; 439 case SYNDROME_LOCAL_RDD_VIOL_ERR: 440 entry->status = IB_WC_LOC_RDD_VIOL_ERR; 441 break; 442 case SYNDROME_REMOTE_INVAL_RD_REQ_ERR: 443 entry->status = IB_WC_REM_INV_RD_REQ_ERR; 444 break; 445 case SYNDROME_REMOTE_ABORTED_ERR: 446 entry->status = IB_WC_REM_ABORT_ERR; 447 break; 448 case SYNDROME_INVAL_EECN_ERR: 449 entry->status = IB_WC_INV_EECN_ERR; 450 break; 451 case SYNDROME_INVAL_EEC_STATE_ERR: 452 entry->status = IB_WC_INV_EEC_STATE_ERR; 453 break; 454 default: 455 entry->status = IB_WC_GENERAL_ERR; 456 break; 457 } 458 459 entry->vendor_err = cqe->vendor_err; 460 461 /* 462 * Mem-free HCAs always generate one CQE per WQE, even in the 463 * error case, so we don't have to check the doorbell count, etc. 464 */ 465 if (mthca_is_memfree(dev)) 466 return; 467 468 mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe); 469 470 /* 471 * If we're at the end of the WQE chain, or we've used up our 472 * doorbell count, free the CQE. Otherwise just update it for 473 * the next poll operation. 474 */ 475 if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd)) 476 return; 477 478 cqe->db_cnt = cpu_to_be16(be16_to_cpu(cqe->db_cnt) - dbd); 479 cqe->wqe = new_wqe; 480 cqe->syndrome = SYNDROME_WR_FLUSH_ERR; 481 482 *free_cqe = 0; 483} 484 485static inline int mthca_poll_one(struct mthca_dev *dev, 486 struct mthca_cq *cq, 487 struct mthca_qp **cur_qp, 488 int *freed, 489 struct ib_wc *entry) 490{ 491 struct mthca_wq *wq; 492 struct mthca_cqe *cqe; 493 int wqe_index; 494 int is_error; 495 int is_send; 496 int free_cqe = 1; 497 int err = 0; 498 499 cqe = next_cqe_sw(cq); 500 if (!cqe) 501 return -EAGAIN; 502 503 /* 504 * Make sure we read CQ entry contents after we've checked the 505 * ownership bit. 506 */ 507 rmb(); 508 509 if (0) { 510 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n", 511 cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn), 512 be32_to_cpu(cqe->wqe)); 513 dump_cqe(dev, cqe); 514 } 515 516 is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) == 517 MTHCA_ERROR_CQE_OPCODE_MASK; 518 is_send = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80; 519 520 if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) { 521 /* 522 * We do not have to take the QP table lock here, 523 * because CQs will be locked while QPs are removed 524 * from the table. 525 */ 526 *cur_qp = mthca_array_get(&dev->qp_table.qp, 527 be32_to_cpu(cqe->my_qpn) & 528 (dev->limits.num_qps - 1)); 529 if (!*cur_qp) { 530 mthca_warn(dev, "CQ entry for unknown QP %06x\n", 531 be32_to_cpu(cqe->my_qpn) & 0xffffff); 532 err = -EINVAL; 533 goto out; 534 } 535 } 536 537 entry->qp = &(*cur_qp)->ibqp; 538 539 if (is_send) { 540 wq = &(*cur_qp)->sq; 541 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset) 542 >> wq->wqe_shift); 543 entry->wr_id = (*cur_qp)->wrid[wqe_index + 544 (*cur_qp)->rq.max]; 545 } else if ((*cur_qp)->ibqp.srq) { 546 struct mthca_srq *srq = to_msrq((*cur_qp)->ibqp.srq); 547 u32 wqe = be32_to_cpu(cqe->wqe); 548 wq = NULL; 549 wqe_index = wqe >> srq->wqe_shift; 550 entry->wr_id = srq->wrid[wqe_index]; 551 mthca_free_srq_wqe(srq, wqe); 552 } else { 553 s32 wqe; 554 wq = &(*cur_qp)->rq; 555 wqe = be32_to_cpu(cqe->wqe); 556 wqe_index = wqe >> wq->wqe_shift; 557 /* 558 * WQE addr == base - 1 might be reported in receive completion 559 * with error instead of (rq size - 1) by Sinai FW 1.0.800 and 560 * Arbel FW 5.1.400. This bug should be fixed in later FW revs. 561 */ 562 if (unlikely(wqe_index < 0)) 563 wqe_index = wq->max - 1; 564 entry->wr_id = (*cur_qp)->wrid[wqe_index]; 565 } 566 567 if (wq) { 568 if (wq->last_comp < wqe_index) 569 wq->tail += wqe_index - wq->last_comp; 570 else 571 wq->tail += wqe_index + wq->max - wq->last_comp; 572 573 wq->last_comp = wqe_index; 574 } 575 576 if (is_error) { 577 handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send, 578 (struct mthca_err_cqe *) cqe, 579 entry, &free_cqe); 580 goto out; 581 } 582 583 if (is_send) { 584 entry->wc_flags = 0; 585 switch (cqe->opcode) { 586 case MTHCA_OPCODE_RDMA_WRITE: 587 entry->opcode = IB_WC_RDMA_WRITE; 588 break; 589 case MTHCA_OPCODE_RDMA_WRITE_IMM: 590 entry->opcode = IB_WC_RDMA_WRITE; 591 entry->wc_flags |= IB_WC_WITH_IMM; 592 break; 593 case MTHCA_OPCODE_SEND: 594 entry->opcode = IB_WC_SEND; 595 break; 596 case MTHCA_OPCODE_SEND_IMM: 597 entry->opcode = IB_WC_SEND; 598 entry->wc_flags |= IB_WC_WITH_IMM; 599 break; 600 case MTHCA_OPCODE_RDMA_READ: 601 entry->opcode = IB_WC_RDMA_READ; 602 entry->byte_len = be32_to_cpu(cqe->byte_cnt); 603 break; 604 case MTHCA_OPCODE_ATOMIC_CS: 605 entry->opcode = IB_WC_COMP_SWAP; 606 entry->byte_len = MTHCA_ATOMIC_BYTE_LEN; 607 break; 608 case MTHCA_OPCODE_ATOMIC_FA: 609 entry->opcode = IB_WC_FETCH_ADD; 610 entry->byte_len = MTHCA_ATOMIC_BYTE_LEN; 611 break; 612 case MTHCA_OPCODE_BIND_MW: 613 entry->opcode = IB_WC_BIND_MW; 614 break; 615 default: 616 entry->opcode = MTHCA_OPCODE_INVALID; 617 break; 618 } 619 } else { 620 entry->byte_len = be32_to_cpu(cqe->byte_cnt); 621 switch (cqe->opcode & 0x1f) { 622 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE: 623 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE: 624 entry->wc_flags = IB_WC_WITH_IMM; 625 entry->imm_data = cqe->imm_etype_pkey_eec; 626 entry->opcode = IB_WC_RECV; 627 break; 628 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE: 629 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE: 630 entry->wc_flags = IB_WC_WITH_IMM; 631 entry->imm_data = cqe->imm_etype_pkey_eec; 632 entry->opcode = IB_WC_RECV_RDMA_WITH_IMM; 633 break; 634 default: 635 entry->wc_flags = 0; 636 entry->opcode = IB_WC_RECV; 637 break; 638 } 639 entry->slid = be16_to_cpu(cqe->rlid); 640 entry->sl = be16_to_cpu(cqe->sl_g_mlpath) >> 12; 641 entry->src_qp = be32_to_cpu(cqe->rqpn) & 0xffffff; 642 entry->dlid_path_bits = be16_to_cpu(cqe->sl_g_mlpath) & 0x7f; 643 entry->pkey_index = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16; 644 entry->wc_flags |= be16_to_cpu(cqe->sl_g_mlpath) & 0x80 ? 645 IB_WC_GRH : 0; 646 } 647 648 entry->status = IB_WC_SUCCESS; 649 650 out: 651 if (likely(free_cqe)) { 652 set_cqe_hw(cqe); 653 ++(*freed); 654 ++cq->cons_index; 655 } 656 657 return err; 658} 659 660int mthca_poll_cq(struct ib_cq *ibcq, int num_entries, 661 struct ib_wc *entry) 662{ 663 struct mthca_dev *dev = to_mdev(ibcq->device); 664 struct mthca_cq *cq = to_mcq(ibcq); 665 struct mthca_qp *qp = NULL; 666 unsigned long flags; 667 int err = 0; 668 int freed = 0; 669 int npolled; 670 671 spin_lock_irqsave(&cq->lock, flags); 672 673 npolled = 0; 674repoll: 675 while (npolled < num_entries) { 676 err = mthca_poll_one(dev, cq, &qp, 677 &freed, entry + npolled); 678 if (err) 679 break; 680 ++npolled; 681 } 682 683 if (freed) { 684 wmb(); 685 update_cons_index(dev, cq, freed); 686 } 687 688 /* 689 * If a CQ resize is in progress and we discovered that the 690 * old buffer is empty, then peek in the new buffer, and if 691 * it's not empty, switch to the new buffer and continue 692 * polling there. 693 */ 694 if (unlikely(err == -EAGAIN && cq->resize_buf && 695 cq->resize_buf->state == CQ_RESIZE_READY)) { 696 /* 697 * In Tavor mode, the hardware keeps the producer 698 * index modulo the CQ size. Since we might be making 699 * the CQ bigger, we need to mask our consumer index 700 * using the size of the old CQ buffer before looking 701 * in the new CQ buffer. 702 */ 703 if (!mthca_is_memfree(dev)) 704 cq->cons_index &= cq->ibcq.cqe; 705 706 if (cqe_sw(get_cqe_from_buf(&cq->resize_buf->buf, 707 cq->cons_index & cq->resize_buf->cqe))) { 708 struct mthca_cq_buf tbuf; 709 int tcqe; 710 711 tbuf = cq->buf; 712 tcqe = cq->ibcq.cqe; 713 cq->buf = cq->resize_buf->buf; 714 cq->ibcq.cqe = cq->resize_buf->cqe; 715 716 cq->resize_buf->buf = tbuf; 717 cq->resize_buf->cqe = tcqe; 718 cq->resize_buf->state = CQ_RESIZE_SWAPPED; 719 720 goto repoll; 721 } 722 } 723 724 spin_unlock_irqrestore(&cq->lock, flags); 725 726 return err == 0 || err == -EAGAIN ? npolled : err; 727} 728 729int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags) 730{ 731 __be32 doorbell[2]; 732 733 doorbell[0] = cpu_to_be32(((flags & IB_CQ_SOLICITED_MASK) == 734 IB_CQ_SOLICITED ? 735 MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL : 736 MTHCA_TAVOR_CQ_DB_REQ_NOT) | 737 to_mcq(cq)->cqn); 738 doorbell[1] = (__force __be32) 0xffffffff; 739 740 mthca_write64(doorbell, 741 to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL, 742 MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock)); 743 744 return 0; 745} 746 747int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 748{ 749 struct mthca_cq *cq = to_mcq(ibcq); 750 __be32 doorbell[2]; 751 u32 sn; 752 __be32 ci; 753 754 sn = cq->arm_sn & 3; 755 ci = cpu_to_be32(cq->cons_index); 756 757 doorbell[0] = ci; 758 doorbell[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) | 759 ((flags & IB_CQ_SOLICITED_MASK) == 760 IB_CQ_SOLICITED ? 1 : 2)); 761 762 mthca_write_db_rec(doorbell, cq->arm_db); 763 764 /* 765 * Make sure that the doorbell record in host memory is 766 * written before ringing the doorbell via PCI MMIO. 767 */ 768 wmb(); 769 770 doorbell[0] = cpu_to_be32((sn << 28) | 771 ((flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 772 MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL : 773 MTHCA_ARBEL_CQ_DB_REQ_NOT) | 774 cq->cqn); 775 doorbell[1] = ci; 776 777 mthca_write64(doorbell, 778 to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL, 779 MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock)); 780 781 return 0; 782} 783 784int mthca_init_cq(struct mthca_dev *dev, int nent, 785 struct mthca_ucontext *ctx, u32 pdn, 786 struct mthca_cq *cq) 787{ 788 struct mthca_mailbox *mailbox; 789 struct mthca_cq_context *cq_context; 790 int err = -ENOMEM; 791 u8 status; 792 793 cq->ibcq.cqe = nent - 1; 794 cq->is_kernel = !ctx; 795 796 cq->cqn = mthca_alloc(&dev->cq_table.alloc); 797 if (cq->cqn == -1) 798 return -ENOMEM; 799 800 if (mthca_is_memfree(dev)) { 801 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn); 802 if (err) 803 goto err_out; 804 805 if (cq->is_kernel) { 806 cq->arm_sn = 1; 807 808 err = -ENOMEM; 809 810 cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, 811 cq->cqn, &cq->set_ci_db); 812 if (cq->set_ci_db_index < 0) 813 goto err_out_icm; 814 815 cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM, 816 cq->cqn, &cq->arm_db); 817 if (cq->arm_db_index < 0) 818 goto err_out_ci; 819 } 820 } 821 822 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 823 if (IS_ERR(mailbox)) 824 goto err_out_arm; 825 826 cq_context = mailbox->buf; 827 828 if (cq->is_kernel) { 829 err = mthca_alloc_cq_buf(dev, &cq->buf, nent); 830 if (err) 831 goto err_out_mailbox; 832 } 833 834 spin_lock_init(&cq->lock); 835 cq->refcount = 1; 836 init_waitqueue_head(&cq->wait); 837 mutex_init(&cq->mutex); 838 839 memset(cq_context, 0, sizeof *cq_context); 840 cq_context->flags = cpu_to_be32(MTHCA_CQ_STATUS_OK | 841 MTHCA_CQ_STATE_DISARMED | 842 MTHCA_CQ_FLAG_TR); 843 cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24); 844 if (ctx) 845 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index); 846 else 847 cq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index); 848 cq_context->error_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn); 849 cq_context->comp_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn); 850 cq_context->pd = cpu_to_be32(pdn); 851 cq_context->lkey = cpu_to_be32(cq->buf.mr.ibmr.lkey); 852 cq_context->cqn = cpu_to_be32(cq->cqn); 853 854 if (mthca_is_memfree(dev)) { 855 cq_context->ci_db = cpu_to_be32(cq->set_ci_db_index); 856 cq_context->state_db = cpu_to_be32(cq->arm_db_index); 857 } 858 859 err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status); 860 if (err) { 861 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err); 862 goto err_out_free_mr; 863 } 864 865 if (status) { 866 mthca_warn(dev, "SW2HW_CQ returned status 0x%02x\n", 867 status); 868 err = -EINVAL; 869 goto err_out_free_mr; 870 } 871 872 spin_lock_irq(&dev->cq_table.lock); 873 if (mthca_array_set(&dev->cq_table.cq, 874 cq->cqn & (dev->limits.num_cqs - 1), 875 cq)) { 876 spin_unlock_irq(&dev->cq_table.lock); 877 goto err_out_free_mr; 878 } 879 spin_unlock_irq(&dev->cq_table.lock); 880 881 cq->cons_index = 0; 882 883 mthca_free_mailbox(dev, mailbox); 884 885 return 0; 886 887err_out_free_mr: 888 if (cq->is_kernel) 889 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 890 891err_out_mailbox: 892 mthca_free_mailbox(dev, mailbox); 893 894err_out_arm: 895 if (cq->is_kernel && mthca_is_memfree(dev)) 896 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index); 897 898err_out_ci: 899 if (cq->is_kernel && mthca_is_memfree(dev)) 900 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index); 901 902err_out_icm: 903 mthca_table_put(dev, dev->cq_table.table, cq->cqn); 904 905err_out: 906 mthca_free(&dev->cq_table.alloc, cq->cqn); 907 908 return err; 909} 910 911static inline int get_cq_refcount(struct mthca_dev *dev, struct mthca_cq *cq) 912{ 913 int c; 914 915 spin_lock_irq(&dev->cq_table.lock); 916 c = cq->refcount; 917 spin_unlock_irq(&dev->cq_table.lock); 918 919 return c; 920} 921 922void mthca_free_cq(struct mthca_dev *dev, 923 struct mthca_cq *cq) 924{ 925 struct mthca_mailbox *mailbox; 926 int err; 927 u8 status; 928 929 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 930 if (IS_ERR(mailbox)) { 931 mthca_warn(dev, "No memory for mailbox to free CQ.\n"); 932 return; 933 } 934 935 err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status); 936 if (err) 937 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err); 938 else if (status) 939 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status); 940 941 if (0) { 942 __be32 *ctx = mailbox->buf; 943 int j; 944 945 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n", 946 cq->cqn, cq->cons_index, 947 cq->is_kernel ? !!next_cqe_sw(cq) : 0); 948 for (j = 0; j < 16; ++j) 949 printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j])); 950 } 951 952 spin_lock_irq(&dev->cq_table.lock); 953 mthca_array_clear(&dev->cq_table.cq, 954 cq->cqn & (dev->limits.num_cqs - 1)); 955 --cq->refcount; 956 spin_unlock_irq(&dev->cq_table.lock); 957 958 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) 959 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector); 960 else 961 synchronize_irq(dev->pdev->irq); 962 963 wait_event(cq->wait, !get_cq_refcount(dev, cq)); 964 965 if (cq->is_kernel) { 966 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 967 if (mthca_is_memfree(dev)) { 968 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index); 969 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index); 970 } 971 } 972 973 mthca_table_put(dev, dev->cq_table.table, cq->cqn); 974 mthca_free(&dev->cq_table.alloc, cq->cqn); 975 mthca_free_mailbox(dev, mailbox); 976} 977 978int mthca_init_cq_table(struct mthca_dev *dev) 979{ 980 int err; 981 982 spin_lock_init(&dev->cq_table.lock); 983 984 err = mthca_alloc_init(&dev->cq_table.alloc, 985 dev->limits.num_cqs, 986 (1 << 24) - 1, 987 dev->limits.reserved_cqs); 988 if (err) 989 return err; 990 991 err = mthca_array_init(&dev->cq_table.cq, 992 dev->limits.num_cqs); 993 if (err) 994 mthca_alloc_cleanup(&dev->cq_table.alloc); 995 996 return err; 997} 998 999void mthca_cleanup_cq_table(struct mthca_dev *dev) 1000{ 1001 mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs); 1002 mthca_alloc_cleanup(&dev->cq_table.alloc); 1003} 1004