11700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* 21700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * specific defines for CCD's HFC 2BDS0 PCI chips 31700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * 41700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * Author Werner Cornelius (werner@isdn4linux.de) 51700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * 61700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * Copyright 1999 by Werner Cornelius (werner@isdn4linux.de) 71700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * 81700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * This program is free software; you can redistribute it and/or modify 91700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * it under the terms of the GNU General Public License as published by 101700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * the Free Software Foundation; either version 2, or (at your option) 111700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * any later version. 121700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * 131700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * This program is distributed in the hope that it will be useful, 141700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * but WITHOUT ANY WARRANTY; without even the implied warranty of 151700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 161700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * GNU General Public License for more details. 171700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * 181700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * You should have received a copy of the GNU General Public License 191700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * along with this program; if not, write to the Free Software 201700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 211700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * 221700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil */ 231700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 241700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* 251700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * thresholds for transparent B-channel mode 261700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil * change mask and threshold simultaneously 271700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil */ 281700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_BTRANS_THRESHOLD 128 298dd2f36f317569665e454268a2677cfba3e848f1Andreas Eversberg#define HFCPCI_FILLEMPTY 64 301700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_BTRANS_THRESMASK 0x00 311700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 321700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* defines for PCI config */ 331700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define PCI_ENA_MEMIO 0x02 341700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define PCI_ENA_MASTER 0x04 351700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 361700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* GCI/IOM bus monitor registers */ 371700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HCFPCI_C_I 0x08 381700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_TRxR 0x0C 391700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_MON1_D 0x28 401700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_MON2_D 0x2C 411700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 421700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* GCI/IOM bus timeslot registers */ 431700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_B1_SSL 0x80 441700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_B2_SSL 0x84 451700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_AUX1_SSL 0x88 461700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_AUX2_SSL 0x8C 471700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_B1_RSL 0x90 481700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_B2_RSL 0x94 491700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_AUX1_RSL 0x98 501700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_AUX2_RSL 0x9C 511700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 521700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* GCI/IOM bus data registers */ 531700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_B1_D 0xA0 541700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_B2_D 0xA4 551700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_AUX1_D 0xA8 561700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_AUX2_D 0xAC 571700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 581700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* GCI/IOM bus configuration registers */ 591700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_MST_EMOD 0xB4 601700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_MST_MODE 0xB8 61475be4d85a274d0961593db41cf85689db1d583cJoe Perches#define HFCPCI_CONNECT 0xBC 621700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 631700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 641700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* Interrupt and status registers */ 651700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_FIFO_EN 0x44 661700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_TRM 0x48 671700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_B_MODE 0x4C 681700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_CHIP_ID 0x58 691700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_CIRM 0x60 701700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_CTMT 0x64 711700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_INT_M1 0x68 721700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_INT_M2 0x6C 731700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_INT_S1 0x78 741700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_INT_S2 0x7C 751700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_STATUS 0x70 761700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 771700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* S/T section registers */ 781700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_STATES 0xC0 791700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_SCTRL 0xC4 801700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_SCTRL_E 0xC8 811700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_SCTRL_R 0xCC 821700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_SQ 0xD0 831700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_CLKDEL 0xDC 841700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_B1_REC 0xF0 851700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_B1_SEND 0xF0 861700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_B2_REC 0xF4 871700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_B2_SEND 0xF4 881700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_D_REC 0xF8 891700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_D_SEND 0xF8 901700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_E_REC 0xFC 911700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 921700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 931700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* bits in status register (READ) */ 941700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_PCI_PROC 0x02 951700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_NBUSY 0x04 961700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_TIMER_ELAP 0x10 971700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_STATINT 0x20 981700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_FRAMEINT 0x40 991700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_ANYINT 0x80 1001700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 1011700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* bits in CTMT (Write) */ 1021700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_CLTIMER 0x80 1031700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_TIM3_125 0x04 1041700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_TIM25 0x10 1051700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_TIM50 0x14 1061700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_TIM400 0x18 1071700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_TIM800 0x1C 1081700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_AUTO_TIMER 0x20 1091700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_TRANSB2 0x02 1101700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_TRANSB1 0x01 1111700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 1121700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* bits in CIRM (Write) */ 1131700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_AUX_MSK 0x07 1141700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_RESET 0x08 1151700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_B1_REV 0x40 1161700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_B2_REV 0x80 1171700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 1181700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* bits in INT_M1 and INT_S1 */ 1191700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_INTS_B1TRANS 0x01 1201700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_INTS_B2TRANS 0x02 1211700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_INTS_DTRANS 0x04 1221700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_INTS_B1REC 0x08 1231700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_INTS_B2REC 0x10 1241700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_INTS_DREC 0x20 1251700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_INTS_L1STATE 0x40 1261700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_INTS_TIMER 0x80 1271700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 1281700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* bits in INT_M2 */ 1291700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_PROC_TRANS 0x01 1301700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_GCI_I_CHG 0x02 1311700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_GCI_MON_REC 0x04 1321700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_IRQ_ENABLE 0x08 1331700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_PMESEL 0x80 1341700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 1351700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* bits in STATES */ 1361700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_STATE_MSK 0x0F 1371700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_LOAD_STATE 0x10 1381700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_ACTIVATE 0x20 1391700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_DO_ACTION 0x40 1401700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_NT_G2_G3 0x80 1411700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 1421700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* bits in HFCD_MST_MODE */ 1431700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_MASTER 0x01 1441700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_SLAVE 0x00 1451700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_F0IO_POSITIV 0x02 1461700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_F0_NEGATIV 0x04 1471700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_F0_2C4 0x08 1481700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* remaining bits are for codecs control */ 1491700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 1501700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* bits in HFCD_SCTRL */ 1511700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define SCTRL_B1_ENA 0x01 1521700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define SCTRL_B2_ENA 0x02 1531700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define SCTRL_MODE_TE 0x00 1541700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define SCTRL_MODE_NT 0x04 1551700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define SCTRL_LOW_PRIO 0x08 1561700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define SCTRL_SQ_ENA 0x10 1571700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define SCTRL_TEST 0x20 1581700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define SCTRL_NONE_CAP 0x40 1591700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define SCTRL_PWR_DOWN 0x80 1601700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 1611700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* bits in SCTRL_E */ 1621700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_AUTO_AWAKE 0x01 1631700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_DBIT_1 0x04 1641700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_IGNORE_COL 0x08 1651700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_CHG_B1_B2 0x80 1661700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 1671700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* bits in FIFO_EN register */ 1681700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_FIFOEN_B1 0x03 1691700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_FIFOEN_B2 0x0C 1701700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_FIFOEN_DTX 0x10 1711700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_FIFOEN_B1TX 0x01 1721700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_FIFOEN_B1RX 0x02 1731700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_FIFOEN_B2TX 0x04 1741700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define HFCPCI_FIFOEN_B2RX 0x08 1751700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 1761700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 1771700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil/* definitions of fifo memory area */ 1781700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define MAX_D_FRAMES 15 1791700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define MAX_B_FRAMES 31 1801700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define B_SUB_VAL 0x200 1811700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define B_FIFO_SIZE (0x2000 - B_SUB_VAL) 1821700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define D_FIFO_SIZE 512 1831700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil#define D_FREG_MASK 0xF 1841700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 1851700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keilstruct zt { 186f11d32dfaa0753cfab7b2e5052923e8784a3c141Harvey Harrison __le16 z1; /* Z1 pointer 16 Bit */ 187f11d32dfaa0753cfab7b2e5052923e8784a3c141Harvey Harrison __le16 z2; /* Z2 pointer 16 Bit */ 1881700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil}; 1891700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 1901700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keilstruct dfifo { 1911700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil u_char data[D_FIFO_SIZE]; /* FIFO data space */ 192475be4d85a274d0961593db41cf85689db1d583cJoe Perches u_char fill1[0x20A0 - D_FIFO_SIZE]; /* reserved, do not use */ 1931700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil u_char f1, f2; /* f pointers */ 194475be4d85a274d0961593db41cf85689db1d583cJoe Perches u_char fill2[0x20C0 - 0x20A2]; /* reserved, do not use */ 1951700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil /* mask index with D_FREG_MASK for access */ 196475be4d85a274d0961593db41cf85689db1d583cJoe Perches struct zt za[MAX_D_FRAMES + 1]; 197475be4d85a274d0961593db41cf85689db1d583cJoe Perches u_char fill3[0x4000 - 0x2100]; /* align 16K */ 1981700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil}; 1991700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 2001700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keilstruct bzfifo { 201475be4d85a274d0961593db41cf85689db1d583cJoe Perches struct zt za[MAX_B_FRAMES + 1]; /* only range 0x0..0x1F allowed */ 2021700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil u_char f1, f2; /* f pointers */ 203475be4d85a274d0961593db41cf85689db1d583cJoe Perches u_char fill[0x2100 - 0x2082]; /* alignment */ 2041700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil}; 2051700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 2061700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 2071700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keilunion fifo_area { 2081700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil struct { 2091700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil struct dfifo d_tx; /* D-send channel */ 2101700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil struct dfifo d_rx; /* D-receive channel */ 2111700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil } d_chan; 2121700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil struct { 2131700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil u_char fill1[0x200]; 2141700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil u_char txdat_b1[B_FIFO_SIZE]; 2151700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil struct bzfifo txbz_b1; 2161700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil struct bzfifo txbz_b2; 2171700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil u_char txdat_b2[B_FIFO_SIZE]; 2181700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil u_char fill2[D_FIFO_SIZE]; 2191700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil u_char rxdat_b1[B_FIFO_SIZE]; 2201700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil struct bzfifo rxbz_b1; 2211700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil struct bzfifo rxbz_b2; 2221700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil u_char rxdat_b2[B_FIFO_SIZE]; 2231700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil } b_chans; 2241700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil u_char fill[32768]; 2251700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil}; 2261700fe1a10dc0eaac0ef60a8093eaeafa9bff9aeKarsten Keil 227475be4d85a274d0961593db41cf85689db1d583cJoe Perches#define Write_hfc(a, b, c) (writeb(c, (a->hw.pci_io) + b)) 228475be4d85a274d0961593db41cf85689db1d583cJoe Perches#define Read_hfc(a, b) (readb((a->hw.pci_io) + b)) 229