it913x-fe.c revision ed942c507465287777a5342f83af1638ba05a6ac
1/* 2 * Driver for it913x-fe Frontend 3 * 4 * with support for on chip it9137 integral tuner 5 * 6 * Copyright (C) 2011 Malcolm Priestley (tvboxspy@gmail.com) 7 * IT9137 Copyright (C) ITE Tech Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= 23 */ 24 25#include <linux/module.h> 26#include <linux/init.h> 27#include <linux/slab.h> 28#include <linux/types.h> 29 30#include "dvb_frontend.h" 31#include "it913x-fe.h" 32#include "it913x-fe-priv.h" 33 34static int it913x_debug; 35 36module_param_named(debug, it913x_debug, int, 0644); 37MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able))."); 38 39#define dprintk(level, args...) do { \ 40 if (level & it913x_debug) \ 41 printk(KERN_DEBUG "it913x-fe: " args); \ 42} while (0) 43 44#define deb_info(args...) dprintk(0x01, args) 45#define debug_data_snipet(level, name, p) \ 46 dprintk(level, name" (%02x%02x%02x%02x%02x%02x%02x%02x)", \ 47 *p, *(p+1), *(p+2), *(p+3), *(p+4), \ 48 *(p+5), *(p+6), *(p+7)); 49#define info(format, arg...) \ 50 printk(KERN_INFO "it913x-fe: " format "\n" , ## arg) 51 52struct it913x_fe_state { 53 struct dvb_frontend frontend; 54 struct i2c_adapter *i2c_adap; 55 struct ite_config *config; 56 u8 i2c_addr; 57 u32 frequency; 58 fe_modulation_t constellation; 59 fe_transmit_mode_t transmission_mode; 60 u32 crystalFrequency; 61 u32 adcFrequency; 62 u8 tuner_type; 63 struct adctable *table; 64 fe_status_t it913x_status; 65 u16 tun_xtal; 66 u8 tun_fdiv; 67 u8 tun_clk_mode; 68 u32 tun_fn_min; 69}; 70 71static int it913x_read_reg(struct it913x_fe_state *state, 72 u32 reg, u8 *data, u8 count) 73{ 74 int ret; 75 u8 pro = PRO_DMOD; /* All reads from demodulator */ 76 u8 b[4]; 77 struct i2c_msg msg[2] = { 78 { .addr = state->i2c_addr + (pro << 1), .flags = 0, 79 .buf = b, .len = sizeof(b) }, 80 { .addr = state->i2c_addr + (pro << 1), .flags = I2C_M_RD, 81 .buf = data, .len = count } 82 }; 83 b[0] = (u8) reg >> 24; 84 b[1] = (u8)(reg >> 16) & 0xff; 85 b[2] = (u8)(reg >> 8) & 0xff; 86 b[3] = (u8) reg & 0xff; 87 88 ret = i2c_transfer(state->i2c_adap, msg, 2); 89 90 return ret; 91} 92 93static int it913x_read_reg_u8(struct it913x_fe_state *state, u32 reg) 94{ 95 int ret; 96 u8 b[1]; 97 ret = it913x_read_reg(state, reg, &b[0], sizeof(b)); 98 return (ret < 0) ? -ENODEV : b[0]; 99} 100 101static int it913x_write(struct it913x_fe_state *state, 102 u8 pro, u32 reg, u8 buf[], u8 count) 103{ 104 u8 b[256]; 105 struct i2c_msg msg[1] = { 106 { .addr = state->i2c_addr + (pro << 1), .flags = 0, 107 .buf = b, .len = count + 4 } 108 }; 109 int ret; 110 111 b[0] = (u8) reg >> 24; 112 b[1] = (u8)(reg >> 16) & 0xff; 113 b[2] = (u8)(reg >> 8) & 0xff; 114 b[3] = (u8) reg & 0xff; 115 memcpy(&b[4], buf, count); 116 117 ret = i2c_transfer(state->i2c_adap, msg, 1); 118 119 if (ret < 0) 120 return -EIO; 121 122 return 0; 123} 124 125static int it913x_write_reg(struct it913x_fe_state *state, 126 u8 pro, u32 reg, u32 data) 127{ 128 int ret; 129 u8 b[4]; 130 u8 s; 131 132 b[0] = data >> 24; 133 b[1] = (data >> 16) & 0xff; 134 b[2] = (data >> 8) & 0xff; 135 b[3] = data & 0xff; 136 /* expand write as needed */ 137 if (data < 0x100) 138 s = 3; 139 else if (data < 0x1000) 140 s = 2; 141 else if (data < 0x100000) 142 s = 1; 143 else 144 s = 0; 145 146 ret = it913x_write(state, pro, reg, &b[s], sizeof(b) - s); 147 148 return ret; 149} 150 151static int it913x_fe_script_loader(struct it913x_fe_state *state, 152 struct it913xset *loadscript) 153{ 154 int ret, i; 155 if (loadscript == NULL) 156 return -EINVAL; 157 158 for (i = 0; i < 1000; ++i) { 159 if (loadscript[i].pro == 0xff) 160 break; 161 ret = it913x_write(state, loadscript[i].pro, 162 loadscript[i].address, 163 loadscript[i].reg, loadscript[i].count); 164 if (ret < 0) 165 return -ENODEV; 166 } 167 return 0; 168} 169 170static int it913x_init_tuner(struct it913x_fe_state *state) 171{ 172 int ret, i, reg; 173 u8 val, nv_val; 174 u8 nv[] = {48, 32, 24, 16, 12, 8, 6, 4, 2}; 175 u8 b[2]; 176 177 reg = it913x_read_reg_u8(state, 0xec86); 178 switch (reg) { 179 case 0: 180 state->tun_clk_mode = reg; 181 state->tun_xtal = 2000; 182 state->tun_fdiv = 3; 183 val = 16; 184 break; 185 case -ENODEV: 186 return -ENODEV; 187 case 1: 188 default: 189 state->tun_clk_mode = reg; 190 state->tun_xtal = 640; 191 state->tun_fdiv = 1; 192 val = 6; 193 break; 194 } 195 196 reg = it913x_read_reg_u8(state, 0xed03); 197 198 if (reg < 0) 199 return -ENODEV; 200 else if (reg < sizeof(nv)) 201 nv_val = nv[reg]; 202 else 203 nv_val = 2; 204 205 for (i = 0; i < 50; i++) { 206 ret = it913x_read_reg(state, 0xed23, &b[0], sizeof(b)); 207 reg = (b[1] << 8) + b[0]; 208 if (reg > 0) 209 break; 210 if (ret < 0) 211 return -ENODEV; 212 udelay(2000); 213 } 214 state->tun_fn_min = state->tun_xtal * reg; 215 state->tun_fn_min /= (state->tun_fdiv * nv_val); 216 deb_info("Tuner fn_min %d", state->tun_fn_min); 217 218 if (state->config->chip_ver > 1) 219 msleep(50); 220 else { 221 for (i = 0; i < 50; i++) { 222 reg = it913x_read_reg_u8(state, 0xec82); 223 if (reg > 0) 224 break; 225 if (reg < 0) 226 return -ENODEV; 227 udelay(2000); 228 } 229 } 230 231 return it913x_write_reg(state, PRO_DMOD, 0xed81, val); 232} 233 234static int it9137_set_tuner(struct it913x_fe_state *state, 235 enum fe_bandwidth bandwidth, u32 frequency_m) 236{ 237 struct it913xset *set_tuner = set_it9137_template; 238 int ret, reg; 239 u32 frequency = frequency_m / 1000; 240 u32 freq, temp_f, tmp; 241 u16 iqik_m_cal; 242 u16 n_div; 243 u8 n; 244 u8 l_band; 245 u8 lna_band; 246 u8 bw; 247 248 deb_info("Tuner Frequency %d Bandwidth %d", frequency, bandwidth); 249 250 if (frequency >= 51000 && frequency <= 440000) { 251 l_band = 0; 252 lna_band = 0; 253 } else if (frequency > 440000 && frequency <= 484000) { 254 l_band = 1; 255 lna_band = 1; 256 } else if (frequency > 484000 && frequency <= 533000) { 257 l_band = 1; 258 lna_band = 2; 259 } else if (frequency > 533000 && frequency <= 587000) { 260 l_band = 1; 261 lna_band = 3; 262 } else if (frequency > 587000 && frequency <= 645000) { 263 l_band = 1; 264 lna_band = 4; 265 } else if (frequency > 645000 && frequency <= 710000) { 266 l_band = 1; 267 lna_band = 5; 268 } else if (frequency > 710000 && frequency <= 782000) { 269 l_band = 1; 270 lna_band = 6; 271 } else if (frequency > 782000 && frequency <= 860000) { 272 l_band = 1; 273 lna_band = 7; 274 } else if (frequency > 1450000 && frequency <= 1492000) { 275 l_band = 1; 276 lna_band = 0; 277 } else if (frequency > 1660000 && frequency <= 1685000) { 278 l_band = 1; 279 lna_band = 1; 280 } else 281 return -EINVAL; 282 set_tuner[0].reg[0] = lna_band; 283 284 if (bandwidth == BANDWIDTH_5_MHZ) 285 bw = 0; 286 else if (bandwidth == BANDWIDTH_6_MHZ) 287 bw = 2; 288 else if (bandwidth == BANDWIDTH_7_MHZ) 289 bw = 4; 290 else if (bandwidth == BANDWIDTH_8_MHZ) 291 bw = 6; 292 else 293 bw = 6; 294 295 set_tuner[1].reg[0] = bw; 296 set_tuner[2].reg[0] = 0xa0 | (l_band << 3); 297 298 if (frequency > 53000 && frequency <= 74000) { 299 n_div = 48; 300 n = 0; 301 } else if (frequency > 74000 && frequency <= 111000) { 302 n_div = 32; 303 n = 1; 304 } else if (frequency > 111000 && frequency <= 148000) { 305 n_div = 24; 306 n = 2; 307 } else if (frequency > 148000 && frequency <= 222000) { 308 n_div = 16; 309 n = 3; 310 } else if (frequency > 222000 && frequency <= 296000) { 311 n_div = 12; 312 n = 4; 313 } else if (frequency > 296000 && frequency <= 445000) { 314 n_div = 8; 315 n = 5; 316 } else if (frequency > 445000 && frequency <= state->tun_fn_min) { 317 n_div = 6; 318 n = 6; 319 } else if (frequency > state->tun_fn_min && frequency <= 950000) { 320 n_div = 4; 321 n = 7; 322 } else if (frequency > 1450000 && frequency <= 1680000) { 323 n_div = 2; 324 n = 0; 325 } else 326 return -EINVAL; 327 328 reg = it913x_read_reg_u8(state, 0xed81); 329 iqik_m_cal = (u16)reg * n_div; 330 331 if (reg < 0x20) { 332 if (state->tun_clk_mode == 0) 333 iqik_m_cal = (iqik_m_cal * 9) >> 5; 334 else 335 iqik_m_cal >>= 1; 336 } else { 337 iqik_m_cal = 0x40 - iqik_m_cal; 338 if (state->tun_clk_mode == 0) 339 iqik_m_cal = ~((iqik_m_cal * 9) >> 5); 340 else 341 iqik_m_cal = ~(iqik_m_cal >> 1); 342 } 343 344 temp_f = frequency * (u32)n_div * (u32)state->tun_fdiv; 345 freq = temp_f / state->tun_xtal; 346 tmp = freq * state->tun_xtal; 347 348 if ((temp_f - tmp) >= (state->tun_xtal >> 1)) 349 freq++; 350 351 freq += (u32) n << 13; 352 /* Frequency OMEGA_IQIK_M_CAL_MID*/ 353 temp_f = freq + (u32)iqik_m_cal; 354 355 set_tuner[3].reg[0] = temp_f & 0xff; 356 set_tuner[4].reg[0] = (temp_f >> 8) & 0xff; 357 358 deb_info("High Frequency = %04x", temp_f); 359 360 /* Lower frequency */ 361 set_tuner[5].reg[0] = freq & 0xff; 362 set_tuner[6].reg[0] = (freq >> 8) & 0xff; 363 364 deb_info("low Frequency = %04x", freq); 365 366 ret = it913x_fe_script_loader(state, set_tuner); 367 368 return (ret < 0) ? -ENODEV : 0; 369} 370 371static int it913x_fe_select_bw(struct it913x_fe_state *state, 372 enum fe_bandwidth bandwidth, u32 adcFrequency) 373{ 374 int ret, i; 375 u8 buffer[256]; 376 u32 coeff[8]; 377 u16 bfsfcw_fftinx_ratio; 378 u16 fftinx_bfsfcw_ratio; 379 u8 count; 380 u8 bw; 381 u8 adcmultiplier; 382 383 deb_info("Bandwidth %d Adc %d", bandwidth, adcFrequency); 384 385 if (bandwidth == BANDWIDTH_5_MHZ) 386 bw = 3; 387 else if (bandwidth == BANDWIDTH_6_MHZ) 388 bw = 0; 389 else if (bandwidth == BANDWIDTH_7_MHZ) 390 bw = 1; 391 else if (bandwidth == BANDWIDTH_8_MHZ) 392 bw = 2; 393 else 394 bw = 2; 395 396 ret = it913x_write_reg(state, PRO_DMOD, REG_BW, bw); 397 398 if (state->table == NULL) 399 return -EINVAL; 400 401 /* In write order */ 402 coeff[0] = state->table[bw].coeff_1_2048; 403 coeff[1] = state->table[bw].coeff_2_2k; 404 coeff[2] = state->table[bw].coeff_1_8191; 405 coeff[3] = state->table[bw].coeff_1_8192; 406 coeff[4] = state->table[bw].coeff_1_8193; 407 coeff[5] = state->table[bw].coeff_2_8k; 408 coeff[6] = state->table[bw].coeff_1_4096; 409 coeff[7] = state->table[bw].coeff_2_4k; 410 bfsfcw_fftinx_ratio = state->table[bw].bfsfcw_fftinx_ratio; 411 fftinx_bfsfcw_ratio = state->table[bw].fftinx_bfsfcw_ratio; 412 413 /* ADC multiplier */ 414 ret = it913x_read_reg_u8(state, ADC_X_2); 415 if (ret < 0) 416 return -EINVAL; 417 418 adcmultiplier = ret; 419 420 count = 0; 421 422 /* Build Buffer for COEFF Registers */ 423 for (i = 0; i < 8; i++) { 424 if (adcmultiplier == 1) 425 coeff[i] /= 2; 426 buffer[count++] = (coeff[i] >> 24) & 0x3; 427 buffer[count++] = (coeff[i] >> 16) & 0xff; 428 buffer[count++] = (coeff[i] >> 8) & 0xff; 429 buffer[count++] = coeff[i] & 0xff; 430 } 431 432 /* bfsfcw_fftinx_ratio register 0x21-0x22 */ 433 buffer[count++] = bfsfcw_fftinx_ratio & 0xff; 434 buffer[count++] = (bfsfcw_fftinx_ratio >> 8) & 0xff; 435 /* fftinx_bfsfcw_ratio register 0x23-0x24 */ 436 buffer[count++] = fftinx_bfsfcw_ratio & 0xff; 437 buffer[count++] = (fftinx_bfsfcw_ratio >> 8) & 0xff; 438 /* start at COEFF_1_2048 and write through to fftinx_bfsfcw_ratio*/ 439 ret = it913x_write(state, PRO_DMOD, COEFF_1_2048, buffer, count); 440 441 for (i = 0; i < 42; i += 8) 442 debug_data_snipet(0x1, "Buffer", &buffer[i]); 443 444 return ret; 445} 446 447 448 449static int it913x_fe_read_status(struct dvb_frontend *fe, fe_status_t *status) 450{ 451 struct it913x_fe_state *state = fe->demodulator_priv; 452 int ret, i; 453 fe_status_t old_status = state->it913x_status; 454 *status = 0; 455 456 if (state->it913x_status == 0) { 457 ret = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS); 458 if (ret == 0x1) { 459 *status |= FE_HAS_SIGNAL; 460 for (i = 0; i < 40; i++) { 461 ret = it913x_read_reg_u8(state, MP2IF_SYNC_LK); 462 if (ret == 0x1) 463 break; 464 msleep(25); 465 } 466 if (ret == 0x1) 467 *status |= FE_HAS_CARRIER 468 | FE_HAS_VITERBI 469 | FE_HAS_SYNC; 470 state->it913x_status = *status; 471 } 472 } 473 474 if (state->it913x_status & FE_HAS_SYNC) { 475 ret = it913x_read_reg_u8(state, TPSD_LOCK); 476 if (ret == 0x1) 477 *status |= FE_HAS_LOCK 478 | state->it913x_status; 479 else 480 state->it913x_status = 0; 481 if (old_status != state->it913x_status) 482 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, ret); 483 } 484 485 return 0; 486} 487 488static int it913x_fe_read_signal_strength(struct dvb_frontend *fe, 489 u16 *strength) 490{ 491 struct it913x_fe_state *state = fe->demodulator_priv; 492 int ret = it913x_read_reg_u8(state, SIGNAL_LEVEL); 493 /*SIGNAL_LEVEL always returns 100%! so using FE_HAS_SIGNAL as switch*/ 494 if (state->it913x_status & FE_HAS_SIGNAL) 495 ret = (ret * 0xff) / 0x64; 496 else 497 ret = 0x0; 498 ret |= ret << 0x8; 499 *strength = ret; 500 return 0; 501} 502 503static int it913x_fe_read_snr(struct dvb_frontend *fe, u16 *snr) 504{ 505 struct it913x_fe_state *state = fe->demodulator_priv; 506 int ret; 507 u8 reg[3]; 508 u32 snr_val, snr_min, snr_max; 509 u32 temp; 510 511 ret = it913x_read_reg(state, 0x2c, reg, sizeof(reg)); 512 513 snr_val = (u32)(reg[2] << 16) | (reg[1] < 8) | reg[0]; 514 515 ret |= it913x_read_reg(state, 0xf78b, reg, 1); 516 if (reg[0]) 517 snr_val /= reg[0]; 518 519 if (state->transmission_mode == TRANSMISSION_MODE_2K) 520 snr_val *= 4; 521 else if (state->transmission_mode == TRANSMISSION_MODE_4K) 522 snr_val *= 2; 523 524 if (state->constellation == QPSK) { 525 snr_min = 0xb4711; 526 snr_max = 0x191451; 527 } else if (state->constellation == QAM_16) { 528 snr_min = 0x4f0d5; 529 snr_max = 0xc7925; 530 } else if (state->constellation == QAM_64) { 531 snr_min = 0x256d0; 532 snr_max = 0x626be; 533 } else 534 return -EINVAL; 535 536 if (snr_val < snr_min) 537 *snr = 0; 538 else if (snr_val < snr_max) { 539 temp = (snr_val - snr_min) >> 5; 540 temp *= 0xffff; 541 temp /= (snr_max - snr_min) >> 5; 542 *snr = (u16)temp; 543 } else 544 *snr = 0xffff; 545 546 return (ret < 0) ? -ENODEV : 0; 547} 548 549static int it913x_fe_read_ber(struct dvb_frontend *fe, u32 *ber) 550{ 551 *ber = 0; 552 return 0; 553} 554 555static int it913x_fe_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 556{ 557 *ucblocks = 0; 558 return 0; 559} 560 561static int it913x_fe_get_frontend(struct dvb_frontend *fe, 562 struct dvb_frontend_parameters *p) 563{ 564 struct it913x_fe_state *state = fe->demodulator_priv; 565 int ret; 566 u8 reg[8]; 567 568 ret = it913x_read_reg(state, REG_TPSD_TX_MODE, reg, sizeof(reg)); 569 570 if (reg[3] < 3) 571 p->u.ofdm.constellation = fe_con[reg[3]]; 572 573 state->constellation = p->u.ofdm.constellation; 574 575 if (reg[0] < 3) 576 p->u.ofdm.transmission_mode = fe_mode[reg[0]]; 577 578 state->transmission_mode = p->u.ofdm.transmission_mode; 579 580 if (reg[1] < 4) 581 p->u.ofdm.guard_interval = fe_gi[reg[1]]; 582 583 if (reg[2] < 4) 584 p->u.ofdm.hierarchy_information = fe_hi[reg[2]]; 585 586 p->u.ofdm.code_rate_HP = (reg[6] < 6) ? fe_code[reg[6]] : FEC_NONE; 587 p->u.ofdm.code_rate_LP = (reg[7] < 6) ? fe_code[reg[7]] : FEC_NONE; 588 589 return 0; 590} 591 592static int it913x_fe_set_frontend(struct dvb_frontend *fe, 593 struct dvb_frontend_parameters *p) 594{ 595 struct it913x_fe_state *state = fe->demodulator_priv; 596 int ret, i; 597 u8 empty_ch, last_ch; 598 599 state->it913x_status = 0; 600 601 /* Set bw*/ 602 ret = it913x_fe_select_bw(state, p->u.ofdm.bandwidth, 603 state->adcFrequency); 604 605 /* Training Mode Off */ 606 ret = it913x_write_reg(state, PRO_LINK, TRAINING_MODE, 0x0); 607 608 /* Clear Empty Channel */ 609 ret = it913x_write_reg(state, PRO_DMOD, EMPTY_CHANNEL_STATUS, 0x0); 610 611 /* Clear bits */ 612 ret = it913x_write_reg(state, PRO_DMOD, MP2IF_SYNC_LK, 0x0); 613 /* LED on */ 614 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1); 615 /* Select Band*/ 616 if ((p->frequency >= 51000000) && (p->frequency <= 230000000)) 617 i = 0; 618 else if ((p->frequency >= 350000000) && (p->frequency <= 900000000)) 619 i = 1; 620 else if ((p->frequency >= 1450000000) && (p->frequency <= 1680000000)) 621 i = 2; 622 else 623 return -EOPNOTSUPP; 624 625 ret = it913x_write_reg(state, PRO_DMOD, FREE_BAND, i); 626 627 deb_info("Frontend Set Tuner Type %02x", state->tuner_type); 628 switch (state->tuner_type) { 629 case IT9135_38: 630 case IT9135_51: 631 case IT9135_52: 632 case IT9135_60: 633 case IT9135_61: 634 case IT9135_62: 635 ret = it9137_set_tuner(state, 636 p->u.ofdm.bandwidth, p->frequency); 637 break; 638 default: 639 if (fe->ops.tuner_ops.set_params) { 640 fe->ops.tuner_ops.set_params(fe, p); 641 if (fe->ops.i2c_gate_ctrl) 642 fe->ops.i2c_gate_ctrl(fe, 0); 643 } 644 break; 645 } 646 /* LED off */ 647 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0); 648 /* Trigger ofsm */ 649 ret = it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0); 650 last_ch = 2; 651 for (i = 0; i < 40; ++i) { 652 empty_ch = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS); 653 if (last_ch == 1 && empty_ch == 1) 654 break; 655 if (last_ch == 2 && empty_ch == 2) 656 return 0; 657 last_ch = empty_ch; 658 msleep(25); 659 } 660 for (i = 0; i < 40; ++i) { 661 if (it913x_read_reg_u8(state, D_TPSD_LOCK) == 1) 662 break; 663 msleep(25); 664 } 665 666 state->frequency = p->frequency; 667 return 0; 668} 669 670static int it913x_fe_suspend(struct it913x_fe_state *state) 671{ 672 int ret, i; 673 u8 b; 674 675 ret = it913x_write_reg(state, PRO_DMOD, SUSPEND_FLAG, 0x1); 676 677 ret |= it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0); 678 679 for (i = 0; i < 128; i++) { 680 ret = it913x_read_reg(state, SUSPEND_FLAG, &b, 1); 681 if (ret < 0) 682 return -ENODEV; 683 if (b == 0) 684 break; 685 686 } 687 688 ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x8); 689 /* Turn LED off */ 690 ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0); 691 692 ret |= it913x_fe_script_loader(state, it9137_tuner_off); 693 694 return (ret < 0) ? -ENODEV : 0; 695} 696 697/* Power sequence */ 698/* Power Up Tuner on -> Frontend suspend off -> Tuner clk on */ 699/* Power Down Frontend suspend on -> Tuner clk off -> Tuner off */ 700 701static int it913x_fe_sleep(struct dvb_frontend *fe) 702{ 703 struct it913x_fe_state *state = fe->demodulator_priv; 704 return it913x_fe_suspend(state); 705} 706 707static u32 compute_div(u32 a, u32 b, u32 x) 708{ 709 u32 res = 0; 710 u32 c = 0; 711 u32 i = 0; 712 713 if (a > b) { 714 c = a / b; 715 a = a - c * b; 716 } 717 718 for (i = 0; i < x; i++) { 719 if (a >= b) { 720 res += 1; 721 a -= b; 722 } 723 a <<= 1; 724 res <<= 1; 725 } 726 727 res = (c << x) + res; 728 729 return res; 730} 731 732static int it913x_fe_start(struct it913x_fe_state *state) 733{ 734 struct it913xset *set_lna; 735 struct it913xset *set_mode; 736 int ret; 737 u8 adf = (state->config->adf & 0xf); 738 u32 adc, xtal; 739 u8 b[4]; 740 741 if (state->config->chip_ver == 1) 742 ret = it913x_init_tuner(state); 743 744 info("ADF table value :%02x", adf); 745 746 if (adf < 10) { 747 state->crystalFrequency = fe_clockTable[adf].xtal ; 748 state->table = fe_clockTable[adf].table; 749 state->adcFrequency = state->table->adcFrequency; 750 751 adc = compute_div(state->adcFrequency, 1000000ul, 19ul); 752 xtal = compute_div(state->crystalFrequency, 1000000ul, 19ul); 753 754 } else 755 return -EINVAL; 756 757 /* Set LED indicator on GPIOH3 */ 758 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_EN, 0x1); 759 ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_ON, 0x1); 760 ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1); 761 762 ret |= it913x_write_reg(state, PRO_LINK, 0xf641, state->tuner_type); 763 ret |= it913x_write_reg(state, PRO_DMOD, 0xf5ca, 0x01); 764 ret |= it913x_write_reg(state, PRO_DMOD, 0xf715, 0x01); 765 766 b[0] = xtal & 0xff; 767 b[1] = (xtal >> 8) & 0xff; 768 b[2] = (xtal >> 16) & 0xff; 769 b[3] = (xtal >> 24); 770 ret |= it913x_write(state, PRO_DMOD, XTAL_CLK, b , 4); 771 772 b[0] = adc & 0xff; 773 b[1] = (adc >> 8) & 0xff; 774 b[2] = (adc >> 16) & 0xff; 775 ret |= it913x_write(state, PRO_DMOD, ADC_FREQ, b, 3); 776 777 info("Crystal Frequency :%d Adc Frequency :%d", 778 state->crystalFrequency, state->adcFrequency); 779 deb_info("Xtal value :%04x Adc value :%04x", xtal, adc); 780 781 if (ret < 0) 782 return -ENODEV; 783 784 /* v1 or v2 tuner script */ 785 if (state->config->chip_ver > 1) 786 ret = it913x_fe_script_loader(state, it9135_v2); 787 else 788 ret = it913x_fe_script_loader(state, it9135_v1); 789 if (ret < 0) 790 return ret; 791 792 /* LNA Scripts */ 793 switch (state->tuner_type) { 794 case IT9135_51: 795 set_lna = it9135_51; 796 break; 797 case IT9135_52: 798 set_lna = it9135_52; 799 break; 800 case IT9135_60: 801 set_lna = it9135_60; 802 break; 803 case IT9135_61: 804 set_lna = it9135_61; 805 break; 806 case IT9135_62: 807 set_lna = it9135_62; 808 break; 809 case IT9135_38: 810 default: 811 set_lna = it9135_38; 812 } 813 info("Tuner LNA type :%02x", state->tuner_type); 814 815 ret = it913x_fe_script_loader(state, set_lna); 816 if (ret < 0) 817 return ret; 818 819 if (state->config->chip_ver == 2) { 820 ret = it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x1); 821 ret |= it913x_write_reg(state, PRO_LINK, PADODPU, 0x0); 822 ret |= it913x_write_reg(state, PRO_LINK, AGC_O_D, 0x0); 823 ret |= it913x_init_tuner(state); 824 } 825 if (ret < 0) 826 return -ENODEV; 827 828 /* Always solo frontend */ 829 set_mode = set_solo_fe; 830 ret |= it913x_fe_script_loader(state, set_mode); 831 832 ret |= it913x_fe_suspend(state); 833 return (ret < 0) ? -ENODEV : 0; 834} 835 836static int it913x_fe_init(struct dvb_frontend *fe) 837{ 838 struct it913x_fe_state *state = fe->demodulator_priv; 839 int ret = 0; 840 /* Power Up Tuner - common all versions */ 841 ret = it913x_write_reg(state, PRO_DMOD, 0xec40, 0x1); 842 843 ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x0); 844 845 ret |= it913x_fe_script_loader(state, init_1); 846 847 ret |= it913x_write_reg(state, PRO_DMOD, 0xfba8, 0x0); 848 849 return (ret < 0) ? -ENODEV : 0; 850} 851 852static void it913x_fe_release(struct dvb_frontend *fe) 853{ 854 struct it913x_fe_state *state = fe->demodulator_priv; 855 kfree(state); 856} 857 858static struct dvb_frontend_ops it913x_fe_ofdm_ops; 859 860struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap, 861 u8 i2c_addr, struct ite_config *config) 862{ 863 struct it913x_fe_state *state = NULL; 864 int ret; 865 866 /* allocate memory for the internal state */ 867 state = kzalloc(sizeof(struct it913x_fe_state), GFP_KERNEL); 868 if (state == NULL) 869 return NULL; 870 if (config == NULL) 871 goto error; 872 873 state->i2c_adap = i2c_adap; 874 state->i2c_addr = i2c_addr; 875 state->config = config; 876 877 switch (state->config->tuner_id_0) { 878 case IT9135_51: 879 case IT9135_52: 880 case IT9135_60: 881 case IT9135_61: 882 case IT9135_62: 883 state->tuner_type = state->config->tuner_id_0; 884 break; 885 default: 886 case IT9135_38: 887 state->tuner_type = IT9135_38; 888 } 889 890 ret = it913x_fe_start(state); 891 if (ret < 0) 892 goto error; 893 894 895 /* create dvb_frontend */ 896 memcpy(&state->frontend.ops, &it913x_fe_ofdm_ops, 897 sizeof(struct dvb_frontend_ops)); 898 state->frontend.demodulator_priv = state; 899 900 return &state->frontend; 901error: 902 kfree(state); 903 return NULL; 904} 905EXPORT_SYMBOL(it913x_fe_attach); 906 907static struct dvb_frontend_ops it913x_fe_ofdm_ops = { 908 909 .info = { 910 .name = "it913x-fe DVB-T", 911 .type = FE_OFDM, 912 .frequency_min = 51000000, 913 .frequency_max = 1680000000, 914 .frequency_stepsize = 62500, 915 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 916 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | 917 FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO | 918 FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 919 FE_CAN_TRANSMISSION_MODE_AUTO | 920 FE_CAN_GUARD_INTERVAL_AUTO | 921 FE_CAN_HIERARCHY_AUTO, 922 }, 923 924 .release = it913x_fe_release, 925 926 .init = it913x_fe_init, 927 .sleep = it913x_fe_sleep, 928 929 .set_frontend = it913x_fe_set_frontend, 930 .get_frontend = it913x_fe_get_frontend, 931 932 .read_status = it913x_fe_read_status, 933 .read_signal_strength = it913x_fe_read_signal_strength, 934 .read_snr = it913x_fe_read_snr, 935 .read_ber = it913x_fe_read_ber, 936 .read_ucblocks = it913x_fe_read_ucblocks, 937}; 938 939MODULE_DESCRIPTION("it913x Frontend and it9137 tuner"); 940MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com"); 941MODULE_VERSION("1.10"); 942MODULE_LICENSE("GPL"); 943