stv0900_core.c revision 62bdbb735c0415c2ffdddc2269a860a76f7f716a
1/* 2 * stv0900_core.c 3 * 4 * Driver for ST STV0900 satellite demodulator IC. 5 * 6 * Copyright (C) ST Microelectronics. 7 * Copyright (C) 2009 NetUP Inc. 8 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 */ 25 26#include <linux/kernel.h> 27#include <linux/module.h> 28#include <linux/string.h> 29#include <linux/slab.h> 30#include <linux/i2c.h> 31 32#include "stv0900.h" 33#include "stv0900_reg.h" 34#include "stv0900_priv.h" 35#include "stv0900_init.h" 36 37int stvdebug = 1; 38module_param_named(debug, stvdebug, int, 0644); 39 40/* internal params node */ 41struct stv0900_inode { 42 /* pointer for internal params, one for each pair of demods */ 43 struct stv0900_internal *internal; 44 struct stv0900_inode *next_inode; 45}; 46 47/* first internal params */ 48static struct stv0900_inode *stv0900_first_inode; 49 50/* find chip by i2c adapter and i2c address */ 51static struct stv0900_inode *find_inode(struct i2c_adapter *i2c_adap, 52 u8 i2c_addr) 53{ 54 struct stv0900_inode *temp_chip = stv0900_first_inode; 55 56 if (temp_chip != NULL) { 57 /* 58 Search of the last stv0900 chip or 59 find it by i2c adapter and i2c address */ 60 while ((temp_chip != NULL) && 61 ((temp_chip->internal->i2c_adap != i2c_adap) || 62 (temp_chip->internal->i2c_addr != i2c_addr))) 63 64 temp_chip = temp_chip->next_inode; 65 66 } 67 68 return temp_chip; 69} 70 71/* deallocating chip */ 72static void remove_inode(struct stv0900_internal *internal) 73{ 74 struct stv0900_inode *prev_node = stv0900_first_inode; 75 struct stv0900_inode *del_node = find_inode(internal->i2c_adap, 76 internal->i2c_addr); 77 78 if (del_node != NULL) { 79 if (del_node == stv0900_first_inode) { 80 stv0900_first_inode = del_node->next_inode; 81 } else { 82 while (prev_node->next_inode != del_node) 83 prev_node = prev_node->next_inode; 84 85 if (del_node->next_inode == NULL) 86 prev_node->next_inode = NULL; 87 else 88 prev_node->next_inode = 89 prev_node->next_inode->next_inode; 90 } 91 92 kfree(del_node); 93 } 94} 95 96/* allocating new chip */ 97static struct stv0900_inode *append_internal(struct stv0900_internal *internal) 98{ 99 struct stv0900_inode *new_node = stv0900_first_inode; 100 101 if (new_node == NULL) { 102 new_node = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL); 103 stv0900_first_inode = new_node; 104 } else { 105 while (new_node->next_inode != NULL) 106 new_node = new_node->next_inode; 107 108 new_node->next_inode = kmalloc(sizeof(struct stv0900_inode), 109 GFP_KERNEL); 110 if (new_node->next_inode != NULL) 111 new_node = new_node->next_inode; 112 else 113 new_node = NULL; 114 } 115 116 if (new_node != NULL) { 117 new_node->internal = internal; 118 new_node->next_inode = NULL; 119 } 120 121 return new_node; 122} 123 124s32 ge2comp(s32 a, s32 width) 125{ 126 if (width == 32) 127 return a; 128 else 129 return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a; 130} 131 132void stv0900_write_reg(struct stv0900_internal *intp, u16 reg_addr, 133 u8 reg_data) 134{ 135 u8 data[3]; 136 int ret; 137 struct i2c_msg i2cmsg = { 138 .addr = intp->i2c_addr, 139 .flags = 0, 140 .len = 3, 141 .buf = data, 142 }; 143 144 data[0] = MSB(reg_addr); 145 data[1] = LSB(reg_addr); 146 data[2] = reg_data; 147 148 ret = i2c_transfer(intp->i2c_adap, &i2cmsg, 1); 149 if (ret != 1) 150 dprintk("%s: i2c error %d\n", __func__, ret); 151} 152 153u8 stv0900_read_reg(struct stv0900_internal *intp, u16 reg) 154{ 155 int ret; 156 u8 b0[] = { MSB(reg), LSB(reg) }; 157 u8 buf = 0; 158 struct i2c_msg msg[] = { 159 { 160 .addr = intp->i2c_addr, 161 .flags = 0, 162 .buf = b0, 163 .len = 2, 164 }, { 165 .addr = intp->i2c_addr, 166 .flags = I2C_M_RD, 167 .buf = &buf, 168 .len = 1, 169 }, 170 }; 171 172 ret = i2c_transfer(intp->i2c_adap, msg, 2); 173 if (ret != 2) 174 dprintk("%s: i2c error %d, reg[0x%02x]\n", 175 __func__, ret, reg); 176 177 return buf; 178} 179 180static void extract_mask_pos(u32 label, u8 *mask, u8 *pos) 181{ 182 u8 position = 0, i = 0; 183 184 (*mask) = label & 0xff; 185 186 while ((position == 0) && (i < 8)) { 187 position = ((*mask) >> i) & 0x01; 188 i++; 189 } 190 191 (*pos) = (i - 1); 192} 193 194void stv0900_write_bits(struct stv0900_internal *intp, u32 label, u8 val) 195{ 196 u8 reg, mask, pos; 197 198 reg = stv0900_read_reg(intp, (label >> 16) & 0xffff); 199 extract_mask_pos(label, &mask, &pos); 200 201 val = mask & (val << pos); 202 203 reg = (reg & (~mask)) | val; 204 stv0900_write_reg(intp, (label >> 16) & 0xffff, reg); 205 206} 207 208u8 stv0900_get_bits(struct stv0900_internal *intp, u32 label) 209{ 210 u8 val = 0xff; 211 u8 mask, pos; 212 213 extract_mask_pos(label, &mask, &pos); 214 215 val = stv0900_read_reg(intp, label >> 16); 216 val = (val & mask) >> pos; 217 218 return val; 219} 220 221static enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *intp) 222{ 223 s32 i; 224 225 if (intp == NULL) 226 return STV0900_INVALID_HANDLE; 227 228 intp->chip_id = stv0900_read_reg(intp, R0900_MID); 229 230 if (intp->errs != STV0900_NO_ERROR) 231 return intp->errs; 232 233 /*Startup sequence*/ 234 stv0900_write_reg(intp, R0900_P1_DMDISTATE, 0x5c); 235 stv0900_write_reg(intp, R0900_P2_DMDISTATE, 0x5c); 236 msleep(3); 237 stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x6c); 238 stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x6f); 239 stv0900_write_reg(intp, R0900_P1_I2CRPT, 0x20); 240 stv0900_write_reg(intp, R0900_P2_I2CRPT, 0x20); 241 stv0900_write_reg(intp, R0900_NCOARSE, 0x13); 242 msleep(3); 243 stv0900_write_reg(intp, R0900_I2CCFG, 0x08); 244 245 switch (intp->clkmode) { 246 case 0: 247 case 2: 248 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 249 | intp->clkmode); 250 break; 251 default: 252 /* preserve SELOSCI bit */ 253 i = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL); 254 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | i); 255 break; 256 } 257 258 msleep(3); 259 for (i = 0; i < 181; i++) 260 stv0900_write_reg(intp, STV0900_InitVal[i][0], 261 STV0900_InitVal[i][1]); 262 263 if (stv0900_read_reg(intp, R0900_MID) >= 0x20) { 264 stv0900_write_reg(intp, R0900_TSGENERAL, 0x0c); 265 for (i = 0; i < 32; i++) 266 stv0900_write_reg(intp, STV0900_Cut20_AddOnVal[i][0], 267 STV0900_Cut20_AddOnVal[i][1]); 268 } 269 270 stv0900_write_reg(intp, R0900_P1_FSPYCFG, 0x6c); 271 stv0900_write_reg(intp, R0900_P2_FSPYCFG, 0x6c); 272 273 stv0900_write_reg(intp, R0900_P1_PDELCTRL2, 0x01); 274 stv0900_write_reg(intp, R0900_P2_PDELCTRL2, 0x21); 275 276 stv0900_write_reg(intp, R0900_P1_PDELCTRL3, 0x20); 277 stv0900_write_reg(intp, R0900_P2_PDELCTRL3, 0x20); 278 279 stv0900_write_reg(intp, R0900_TSTRES0, 0x80); 280 stv0900_write_reg(intp, R0900_TSTRES0, 0x00); 281 282 return STV0900_NO_ERROR; 283} 284 285static u32 stv0900_get_mclk_freq(struct stv0900_internal *intp, u32 ext_clk) 286{ 287 u32 mclk = 90000000, div = 0, ad_div = 0; 288 289 div = stv0900_get_bits(intp, F0900_M_DIV); 290 ad_div = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6); 291 292 mclk = (div + 1) * ext_clk / ad_div; 293 294 dprintk("%s: Calculated Mclk = %d\n", __func__, mclk); 295 296 return mclk; 297} 298 299static enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *intp, u32 mclk) 300{ 301 u32 m_div, clk_sel; 302 303 dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk, 304 intp->quartz); 305 306 if (intp == NULL) 307 return STV0900_INVALID_HANDLE; 308 309 if (intp->errs) 310 return STV0900_I2C_ERROR; 311 312 clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6); 313 m_div = ((clk_sel * mclk) / intp->quartz) - 1; 314 stv0900_write_bits(intp, F0900_M_DIV, m_div); 315 intp->mclk = stv0900_get_mclk_freq(intp, 316 intp->quartz); 317 318 /*Set the DiseqC frequency to 22KHz */ 319 /* 320 Formula: 321 DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg) 322 DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg) 323 */ 324 m_div = intp->mclk / 704000; 325 stv0900_write_reg(intp, R0900_P1_F22TX, m_div); 326 stv0900_write_reg(intp, R0900_P1_F22RX, m_div); 327 328 stv0900_write_reg(intp, R0900_P2_F22TX, m_div); 329 stv0900_write_reg(intp, R0900_P2_F22RX, m_div); 330 331 if ((intp->errs)) 332 return STV0900_I2C_ERROR; 333 334 return STV0900_NO_ERROR; 335} 336 337static u32 stv0900_get_err_count(struct stv0900_internal *intp, int cntr, 338 enum fe_stv0900_demod_num demod) 339{ 340 u32 lsb, msb, hsb, err_val; 341 342 switch (cntr) { 343 case 0: 344 default: 345 hsb = stv0900_get_bits(intp, ERR_CNT12); 346 msb = stv0900_get_bits(intp, ERR_CNT11); 347 lsb = stv0900_get_bits(intp, ERR_CNT10); 348 break; 349 case 1: 350 hsb = stv0900_get_bits(intp, ERR_CNT22); 351 msb = stv0900_get_bits(intp, ERR_CNT21); 352 lsb = stv0900_get_bits(intp, ERR_CNT20); 353 break; 354 } 355 356 err_val = (hsb << 16) + (msb << 8) + (lsb); 357 358 return err_val; 359} 360 361static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 362{ 363 struct stv0900_state *state = fe->demodulator_priv; 364 struct stv0900_internal *intp = state->internal; 365 enum fe_stv0900_demod_num demod = state->demod; 366 367 stv0900_write_bits(intp, I2CT_ON, enable); 368 369 return 0; 370} 371 372static void stv0900_set_ts_parallel_serial(struct stv0900_internal *intp, 373 enum fe_stv0900_clock_type path1_ts, 374 enum fe_stv0900_clock_type path2_ts) 375{ 376 377 dprintk("%s\n", __func__); 378 379 if (intp->chip_id >= 0x20) { 380 switch (path1_ts) { 381 case STV0900_PARALLEL_PUNCT_CLOCK: 382 case STV0900_DVBCI_CLOCK: 383 switch (path2_ts) { 384 case STV0900_SERIAL_PUNCT_CLOCK: 385 case STV0900_SERIAL_CONT_CLOCK: 386 default: 387 stv0900_write_reg(intp, R0900_TSGENERAL, 388 0x00); 389 break; 390 case STV0900_PARALLEL_PUNCT_CLOCK: 391 case STV0900_DVBCI_CLOCK: 392 stv0900_write_reg(intp, R0900_TSGENERAL, 393 0x06); 394 stv0900_write_bits(intp, 395 F0900_P1_TSFIFO_MANSPEED, 3); 396 stv0900_write_bits(intp, 397 F0900_P2_TSFIFO_MANSPEED, 0); 398 stv0900_write_reg(intp, 399 R0900_P1_TSSPEED, 0x14); 400 stv0900_write_reg(intp, 401 R0900_P2_TSSPEED, 0x28); 402 break; 403 } 404 break; 405 case STV0900_SERIAL_PUNCT_CLOCK: 406 case STV0900_SERIAL_CONT_CLOCK: 407 default: 408 switch (path2_ts) { 409 case STV0900_SERIAL_PUNCT_CLOCK: 410 case STV0900_SERIAL_CONT_CLOCK: 411 default: 412 stv0900_write_reg(intp, 413 R0900_TSGENERAL, 0x0C); 414 break; 415 case STV0900_PARALLEL_PUNCT_CLOCK: 416 case STV0900_DVBCI_CLOCK: 417 stv0900_write_reg(intp, 418 R0900_TSGENERAL, 0x0A); 419 dprintk("%s: 0x0a\n", __func__); 420 break; 421 } 422 break; 423 } 424 } else { 425 switch (path1_ts) { 426 case STV0900_PARALLEL_PUNCT_CLOCK: 427 case STV0900_DVBCI_CLOCK: 428 switch (path2_ts) { 429 case STV0900_SERIAL_PUNCT_CLOCK: 430 case STV0900_SERIAL_CONT_CLOCK: 431 default: 432 stv0900_write_reg(intp, R0900_TSGENERAL1X, 433 0x10); 434 break; 435 case STV0900_PARALLEL_PUNCT_CLOCK: 436 case STV0900_DVBCI_CLOCK: 437 stv0900_write_reg(intp, R0900_TSGENERAL1X, 438 0x16); 439 stv0900_write_bits(intp, 440 F0900_P1_TSFIFO_MANSPEED, 3); 441 stv0900_write_bits(intp, 442 F0900_P2_TSFIFO_MANSPEED, 0); 443 stv0900_write_reg(intp, R0900_P1_TSSPEED, 444 0x14); 445 stv0900_write_reg(intp, R0900_P2_TSSPEED, 446 0x28); 447 break; 448 } 449 450 break; 451 case STV0900_SERIAL_PUNCT_CLOCK: 452 case STV0900_SERIAL_CONT_CLOCK: 453 default: 454 switch (path2_ts) { 455 case STV0900_SERIAL_PUNCT_CLOCK: 456 case STV0900_SERIAL_CONT_CLOCK: 457 default: 458 stv0900_write_reg(intp, R0900_TSGENERAL1X, 459 0x14); 460 break; 461 case STV0900_PARALLEL_PUNCT_CLOCK: 462 case STV0900_DVBCI_CLOCK: 463 stv0900_write_reg(intp, R0900_TSGENERAL1X, 464 0x12); 465 dprintk("%s: 0x12\n", __func__); 466 break; 467 } 468 469 break; 470 } 471 } 472 473 switch (path1_ts) { 474 case STV0900_PARALLEL_PUNCT_CLOCK: 475 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00); 476 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00); 477 break; 478 case STV0900_DVBCI_CLOCK: 479 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00); 480 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01); 481 break; 482 case STV0900_SERIAL_PUNCT_CLOCK: 483 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01); 484 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00); 485 break; 486 case STV0900_SERIAL_CONT_CLOCK: 487 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01); 488 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01); 489 break; 490 default: 491 break; 492 } 493 494 switch (path2_ts) { 495 case STV0900_PARALLEL_PUNCT_CLOCK: 496 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00); 497 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00); 498 break; 499 case STV0900_DVBCI_CLOCK: 500 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00); 501 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01); 502 break; 503 case STV0900_SERIAL_PUNCT_CLOCK: 504 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01); 505 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00); 506 break; 507 case STV0900_SERIAL_CONT_CLOCK: 508 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01); 509 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01); 510 break; 511 default: 512 break; 513 } 514 515 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1); 516 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0); 517 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1); 518 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0); 519} 520 521void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency, 522 u32 bandwidth) 523{ 524 struct dvb_frontend_ops *frontend_ops = NULL; 525 struct dvb_tuner_ops *tuner_ops = NULL; 526 527 if (&fe->ops) 528 frontend_ops = &fe->ops; 529 530 if (&frontend_ops->tuner_ops) 531 tuner_ops = &frontend_ops->tuner_ops; 532 533 if (tuner_ops->set_frequency) { 534 if ((tuner_ops->set_frequency(fe, frequency)) < 0) 535 dprintk("%s: Invalid parameter\n", __func__); 536 else 537 dprintk("%s: Frequency=%d\n", __func__, frequency); 538 539 } 540 541 if (tuner_ops->set_bandwidth) { 542 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0) 543 dprintk("%s: Invalid parameter\n", __func__); 544 else 545 dprintk("%s: Bandwidth=%d\n", __func__, bandwidth); 546 547 } 548} 549 550void stv0900_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth) 551{ 552 struct dvb_frontend_ops *frontend_ops = NULL; 553 struct dvb_tuner_ops *tuner_ops = NULL; 554 555 if (&fe->ops) 556 frontend_ops = &fe->ops; 557 558 if (&frontend_ops->tuner_ops) 559 tuner_ops = &frontend_ops->tuner_ops; 560 561 if (tuner_ops->set_bandwidth) { 562 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0) 563 dprintk("%s: Invalid parameter\n", __func__); 564 else 565 dprintk("%s: Bandwidth=%d\n", __func__, bandwidth); 566 567 } 568} 569 570u32 stv0900_get_freq_auto(struct stv0900_internal *intp, int demod) 571{ 572 u32 freq, round; 573 /* Formulat : 574 Tuner_Frequency(MHz) = Regs / 64 575 Tuner_granularity(MHz) = Regs / 2048 576 real_Tuner_Frequency = Tuner_Frequency(MHz) - Tuner_granularity(MHz) 577 */ 578 freq = (stv0900_get_bits(intp, TUN_RFFREQ2) << 10) + 579 (stv0900_get_bits(intp, TUN_RFFREQ1) << 2) + 580 stv0900_get_bits(intp, TUN_RFFREQ0); 581 582 freq = (freq * 1000) / 64; 583 584 round = (stv0900_get_bits(intp, TUN_RFRESTE1) >> 2) + 585 stv0900_get_bits(intp, TUN_RFRESTE0); 586 587 round = (round * 1000) / 2048; 588 589 return freq + round; 590} 591 592void stv0900_set_tuner_auto(struct stv0900_internal *intp, u32 Frequency, 593 u32 Bandwidth, int demod) 594{ 595 u32 tunerFrequency; 596 /* Formulat: 597 Tuner_frequency_reg= Frequency(MHz)*64 598 */ 599 tunerFrequency = (Frequency * 64) / 1000; 600 601 stv0900_write_bits(intp, TUN_RFFREQ2, (tunerFrequency >> 10)); 602 stv0900_write_bits(intp, TUN_RFFREQ1, (tunerFrequency >> 2) & 0xff); 603 stv0900_write_bits(intp, TUN_RFFREQ0, (tunerFrequency & 0x03)); 604 /* Low Pass Filter = BW /2 (MHz)*/ 605 stv0900_write_bits(intp, TUN_BW, Bandwidth / 2000000); 606 /* Tuner Write trig */ 607 stv0900_write_reg(intp, TNRLD, 1); 608} 609 610static s32 stv0900_get_rf_level(struct stv0900_internal *intp, 611 const struct stv0900_table *lookup, 612 enum fe_stv0900_demod_num demod) 613{ 614 s32 agc_gain = 0, 615 imin, 616 imax, 617 i, 618 rf_lvl = 0; 619 620 dprintk("%s\n", __func__); 621 622 if ((lookup == NULL) || (lookup->size <= 0)) 623 return 0; 624 625 agc_gain = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1), 626 stv0900_get_bits(intp, AGCIQ_VALUE0)); 627 628 imin = 0; 629 imax = lookup->size - 1; 630 if (INRANGE(lookup->table[imin].regval, agc_gain, 631 lookup->table[imax].regval)) { 632 while ((imax - imin) > 1) { 633 i = (imax + imin) >> 1; 634 635 if (INRANGE(lookup->table[imin].regval, 636 agc_gain, 637 lookup->table[i].regval)) 638 imax = i; 639 else 640 imin = i; 641 } 642 643 rf_lvl = (s32)agc_gain - lookup->table[imin].regval; 644 rf_lvl *= (lookup->table[imax].realval - 645 lookup->table[imin].realval); 646 rf_lvl /= (lookup->table[imax].regval - 647 lookup->table[imin].regval); 648 rf_lvl += lookup->table[imin].realval; 649 } else if (agc_gain > lookup->table[0].regval) 650 rf_lvl = 5; 651 else if (agc_gain < lookup->table[lookup->size-1].regval) 652 rf_lvl = -100; 653 654 dprintk("%s: RFLevel = %d\n", __func__, rf_lvl); 655 656 return rf_lvl; 657} 658 659static int stv0900_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 660{ 661 struct stv0900_state *state = fe->demodulator_priv; 662 struct stv0900_internal *internal = state->internal; 663 s32 rflevel = stv0900_get_rf_level(internal, &stv0900_rf, 664 state->demod); 665 666 rflevel = (rflevel + 100) * (65535 / 70); 667 if (rflevel < 0) 668 rflevel = 0; 669 670 if (rflevel > 65535) 671 rflevel = 65535; 672 673 *strength = rflevel; 674 675 return 0; 676} 677 678static s32 stv0900_carr_get_quality(struct dvb_frontend *fe, 679 const struct stv0900_table *lookup) 680{ 681 struct stv0900_state *state = fe->demodulator_priv; 682 struct stv0900_internal *intp = state->internal; 683 enum fe_stv0900_demod_num demod = state->demod; 684 685 s32 c_n = -100, 686 regval, 687 imin, 688 imax, 689 i, 690 noise_field1, 691 noise_field0; 692 693 dprintk("%s\n", __func__); 694 695 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) { 696 noise_field1 = NOSPLHT_NORMED1; 697 noise_field0 = NOSPLHT_NORMED0; 698 } else { 699 noise_field1 = NOSDATAT_NORMED1; 700 noise_field0 = NOSDATAT_NORMED0; 701 } 702 703 if (stv0900_get_bits(intp, LOCK_DEFINITIF)) { 704 if ((lookup != NULL) && lookup->size) { 705 regval = 0; 706 msleep(5); 707 for (i = 0; i < 16; i++) { 708 regval += MAKEWORD(stv0900_get_bits(intp, 709 noise_field1), 710 stv0900_get_bits(intp, 711 noise_field0)); 712 msleep(1); 713 } 714 715 regval /= 16; 716 imin = 0; 717 imax = lookup->size - 1; 718 if (INRANGE(lookup->table[imin].regval, 719 regval, 720 lookup->table[imax].regval)) { 721 while ((imax - imin) > 1) { 722 i = (imax + imin) >> 1; 723 if (INRANGE(lookup->table[imin].regval, 724 regval, 725 lookup->table[i].regval)) 726 imax = i; 727 else 728 imin = i; 729 } 730 731 c_n = ((regval - lookup->table[imin].regval) 732 * (lookup->table[imax].realval 733 - lookup->table[imin].realval) 734 / (lookup->table[imax].regval 735 - lookup->table[imin].regval)) 736 + lookup->table[imin].realval; 737 } else if (regval < lookup->table[imin].regval) 738 c_n = 1000; 739 } 740 } 741 742 return c_n; 743} 744 745static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks) 746{ 747 struct stv0900_state *state = fe->demodulator_priv; 748 struct stv0900_internal *intp = state->internal; 749 enum fe_stv0900_demod_num demod = state->demod; 750 u8 err_val1, err_val0; 751 u32 header_err_val = 0; 752 753 *ucblocks = 0x0; 754 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) { 755 /* DVB-S2 delineator errors count */ 756 757 /* retreiving number for errnous headers */ 758 err_val1 = stv0900_read_reg(intp, BBFCRCKO1); 759 err_val0 = stv0900_read_reg(intp, BBFCRCKO0); 760 header_err_val = (err_val1 << 8) | err_val0; 761 762 /* retreiving number for errnous packets */ 763 err_val1 = stv0900_read_reg(intp, UPCRCKO1); 764 err_val0 = stv0900_read_reg(intp, UPCRCKO0); 765 *ucblocks = (err_val1 << 8) | err_val0; 766 *ucblocks += header_err_val; 767 } 768 769 return 0; 770} 771 772static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr) 773{ 774 s32 snrlcl = stv0900_carr_get_quality(fe, 775 (const struct stv0900_table *)&stv0900_s2_cn); 776 snrlcl = (snrlcl + 30) * 384; 777 if (snrlcl < 0) 778 snrlcl = 0; 779 780 if (snrlcl > 65535) 781 snrlcl = 65535; 782 783 *snr = snrlcl; 784 785 return 0; 786} 787 788static u32 stv0900_get_ber(struct stv0900_internal *intp, 789 enum fe_stv0900_demod_num demod) 790{ 791 u32 ber = 10000000, i; 792 s32 demod_state; 793 794 demod_state = stv0900_get_bits(intp, HEADER_MODE); 795 796 switch (demod_state) { 797 case STV0900_SEARCH: 798 case STV0900_PLH_DETECTED: 799 default: 800 ber = 10000000; 801 break; 802 case STV0900_DVBS_FOUND: 803 ber = 0; 804 for (i = 0; i < 5; i++) { 805 msleep(5); 806 ber += stv0900_get_err_count(intp, 0, demod); 807 } 808 809 ber /= 5; 810 if (stv0900_get_bits(intp, PRFVIT)) { 811 ber *= 9766; 812 ber = ber >> 13; 813 } 814 815 break; 816 case STV0900_DVBS2_FOUND: 817 ber = 0; 818 for (i = 0; i < 5; i++) { 819 msleep(5); 820 ber += stv0900_get_err_count(intp, 0, demod); 821 } 822 823 ber /= 5; 824 if (stv0900_get_bits(intp, PKTDELIN_LOCK)) { 825 ber *= 9766; 826 ber = ber >> 13; 827 } 828 829 break; 830 } 831 832 return ber; 833} 834 835static int stv0900_read_ber(struct dvb_frontend *fe, u32 *ber) 836{ 837 struct stv0900_state *state = fe->demodulator_priv; 838 struct stv0900_internal *internal = state->internal; 839 840 *ber = stv0900_get_ber(internal, state->demod); 841 842 return 0; 843} 844 845int stv0900_get_demod_lock(struct stv0900_internal *intp, 846 enum fe_stv0900_demod_num demod, s32 time_out) 847{ 848 s32 timer = 0, 849 lock = 0; 850 851 enum fe_stv0900_search_state dmd_state; 852 853 while ((timer < time_out) && (lock == 0)) { 854 dmd_state = stv0900_get_bits(intp, HEADER_MODE); 855 dprintk("Demod State = %d\n", dmd_state); 856 switch (dmd_state) { 857 case STV0900_SEARCH: 858 case STV0900_PLH_DETECTED: 859 default: 860 lock = 0; 861 break; 862 case STV0900_DVBS2_FOUND: 863 case STV0900_DVBS_FOUND: 864 lock = stv0900_get_bits(intp, LOCK_DEFINITIF); 865 break; 866 } 867 868 if (lock == 0) 869 msleep(10); 870 871 timer += 10; 872 } 873 874 if (lock) 875 dprintk("DEMOD LOCK OK\n"); 876 else 877 dprintk("DEMOD LOCK FAIL\n"); 878 879 return lock; 880} 881 882void stv0900_stop_all_s2_modcod(struct stv0900_internal *intp, 883 enum fe_stv0900_demod_num demod) 884{ 885 s32 regflist, 886 i; 887 888 dprintk("%s\n", __func__); 889 890 regflist = MODCODLST0; 891 892 for (i = 0; i < 16; i++) 893 stv0900_write_reg(intp, regflist + i, 0xff); 894} 895 896void stv0900_activate_s2_modcod(struct stv0900_internal *intp, 897 enum fe_stv0900_demod_num demod) 898{ 899 u32 matype, 900 mod_code, 901 fmod, 902 reg_index, 903 field_index; 904 905 dprintk("%s\n", __func__); 906 907 if (intp->chip_id <= 0x11) { 908 msleep(5); 909 910 mod_code = stv0900_read_reg(intp, PLHMODCOD); 911 matype = mod_code & 0x3; 912 mod_code = (mod_code & 0x7f) >> 2; 913 914 reg_index = MODCODLSTF - mod_code / 2; 915 field_index = mod_code % 2; 916 917 switch (matype) { 918 case 0: 919 default: 920 fmod = 14; 921 break; 922 case 1: 923 fmod = 13; 924 break; 925 case 2: 926 fmod = 11; 927 break; 928 case 3: 929 fmod = 7; 930 break; 931 } 932 933 if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910)) 934 && (matype <= 1)) { 935 if (field_index == 0) 936 stv0900_write_reg(intp, reg_index, 937 0xf0 | fmod); 938 else 939 stv0900_write_reg(intp, reg_index, 940 (fmod << 4) | 0xf); 941 } 942 943 } else if (intp->chip_id >= 0x12) { 944 for (reg_index = 0; reg_index < 7; reg_index++) 945 stv0900_write_reg(intp, MODCODLST0 + reg_index, 0xff); 946 947 stv0900_write_reg(intp, MODCODLSTE, 0xff); 948 stv0900_write_reg(intp, MODCODLSTF, 0xcf); 949 for (reg_index = 0; reg_index < 8; reg_index++) 950 stv0900_write_reg(intp, MODCODLST7 + reg_index, 0xcc); 951 952 953 } 954} 955 956void stv0900_activate_s2_modcod_single(struct stv0900_internal *intp, 957 enum fe_stv0900_demod_num demod) 958{ 959 u32 reg_index; 960 961 dprintk("%s\n", __func__); 962 963 stv0900_write_reg(intp, MODCODLST0, 0xff); 964 stv0900_write_reg(intp, MODCODLST1, 0xf0); 965 stv0900_write_reg(intp, MODCODLSTF, 0x0f); 966 for (reg_index = 0; reg_index < 13; reg_index++) 967 stv0900_write_reg(intp, MODCODLST2 + reg_index, 0); 968 969} 970 971static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe) 972{ 973 return DVBFE_ALGO_CUSTOM; 974} 975 976static int stb0900_set_property(struct dvb_frontend *fe, 977 struct dtv_property *tvp) 978{ 979 dprintk("%s(..)\n", __func__); 980 981 return 0; 982} 983 984static int stb0900_get_property(struct dvb_frontend *fe, 985 struct dtv_property *tvp) 986{ 987 dprintk("%s(..)\n", __func__); 988 989 return 0; 990} 991 992void stv0900_start_search(struct stv0900_internal *intp, 993 enum fe_stv0900_demod_num demod) 994{ 995 u32 freq; 996 s16 freq_s16 ; 997 998 stv0900_write_bits(intp, DEMOD_MODE, 0x1f); 999 if (intp->chip_id == 0x10) 1000 stv0900_write_reg(intp, CORRELEXP, 0xaa); 1001 1002 if (intp->chip_id < 0x20) 1003 stv0900_write_reg(intp, CARHDR, 0x55); 1004 1005 if (intp->chip_id <= 0x20) { 1006 if (intp->symbol_rate[0] <= 5000000) { 1007 stv0900_write_reg(intp, CARCFG, 0x44); 1008 stv0900_write_reg(intp, CFRUP1, 0x0f); 1009 stv0900_write_reg(intp, CFRUP0, 0xff); 1010 stv0900_write_reg(intp, CFRLOW1, 0xf0); 1011 stv0900_write_reg(intp, CFRLOW0, 0x00); 1012 stv0900_write_reg(intp, RTCS2, 0x68); 1013 } else { 1014 stv0900_write_reg(intp, CARCFG, 0xc4); 1015 stv0900_write_reg(intp, RTCS2, 0x44); 1016 } 1017 1018 } else { /*cut 3.0 above*/ 1019 if (intp->symbol_rate[demod] <= 5000000) 1020 stv0900_write_reg(intp, RTCS2, 0x68); 1021 else 1022 stv0900_write_reg(intp, RTCS2, 0x44); 1023 1024 stv0900_write_reg(intp, CARCFG, 0x46); 1025 if (intp->srch_algo[demod] == STV0900_WARM_START) { 1026 freq = 1000 << 16; 1027 freq /= (intp->mclk / 1000); 1028 freq_s16 = (s16)freq; 1029 } else { 1030 freq = (intp->srch_range[demod] / 2000); 1031 if (intp->symbol_rate[demod] <= 5000000) 1032 freq += 80; 1033 else 1034 freq += 600; 1035 1036 freq = freq << 16; 1037 freq /= (intp->mclk / 1000); 1038 freq_s16 = (s16)freq; 1039 } 1040 1041 stv0900_write_bits(intp, CFR_UP1, MSB(freq_s16)); 1042 stv0900_write_bits(intp, CFR_UP0, LSB(freq_s16)); 1043 freq_s16 *= (-1); 1044 stv0900_write_bits(intp, CFR_LOW1, MSB(freq_s16)); 1045 stv0900_write_bits(intp, CFR_LOW0, LSB(freq_s16)); 1046 } 1047 1048 stv0900_write_reg(intp, CFRINIT1, 0); 1049 stv0900_write_reg(intp, CFRINIT0, 0); 1050 1051 if (intp->chip_id >= 0x20) { 1052 stv0900_write_reg(intp, EQUALCFG, 0x41); 1053 stv0900_write_reg(intp, FFECFG, 0x41); 1054 1055 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) || 1056 (intp->srch_standard[demod] == STV0900_SEARCH_DSS) || 1057 (intp->srch_standard[demod] == STV0900_AUTO_SEARCH)) { 1058 stv0900_write_reg(intp, VITSCALE, 1059 0x82); 1060 stv0900_write_reg(intp, VAVSRVIT, 0x0); 1061 } 1062 } 1063 1064 stv0900_write_reg(intp, SFRSTEP, 0x00); 1065 stv0900_write_reg(intp, TMGTHRISE, 0xe0); 1066 stv0900_write_reg(intp, TMGTHFALL, 0xc0); 1067 stv0900_write_bits(intp, SCAN_ENABLE, 0); 1068 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); 1069 stv0900_write_bits(intp, S1S2_SEQUENTIAL, 0); 1070 stv0900_write_reg(intp, RTC, 0x88); 1071 if (intp->chip_id >= 0x20) { 1072 if (intp->symbol_rate[demod] < 2000000) { 1073 if (intp->chip_id <= 0x20) 1074 stv0900_write_reg(intp, CARFREQ, 0x39); 1075 else /*cut 3.0*/ 1076 stv0900_write_reg(intp, CARFREQ, 0x89); 1077 1078 stv0900_write_reg(intp, CARHDR, 0x40); 1079 } else if (intp->symbol_rate[demod] < 10000000) { 1080 stv0900_write_reg(intp, CARFREQ, 0x4c); 1081 stv0900_write_reg(intp, CARHDR, 0x20); 1082 } else { 1083 stv0900_write_reg(intp, CARFREQ, 0x4b); 1084 stv0900_write_reg(intp, CARHDR, 0x20); 1085 } 1086 1087 } else { 1088 if (intp->symbol_rate[demod] < 10000000) 1089 stv0900_write_reg(intp, CARFREQ, 0xef); 1090 else 1091 stv0900_write_reg(intp, CARFREQ, 0xed); 1092 } 1093 1094 switch (intp->srch_algo[demod]) { 1095 case STV0900_WARM_START: 1096 stv0900_write_reg(intp, DMDISTATE, 0x1f); 1097 stv0900_write_reg(intp, DMDISTATE, 0x18); 1098 break; 1099 case STV0900_COLD_START: 1100 stv0900_write_reg(intp, DMDISTATE, 0x1f); 1101 stv0900_write_reg(intp, DMDISTATE, 0x15); 1102 break; 1103 default: 1104 break; 1105 } 1106} 1107 1108u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode, 1109 s32 pilot, u8 chip_id) 1110{ 1111 u8 aclc_value = 0x29; 1112 s32 i; 1113 const struct stv0900_car_loop_optim *cls2, *cllqs2, *cllas2; 1114 1115 dprintk("%s\n", __func__); 1116 1117 if (chip_id <= 0x12) { 1118 cls2 = FE_STV0900_S2CarLoop; 1119 cllqs2 = FE_STV0900_S2LowQPCarLoopCut30; 1120 cllas2 = FE_STV0900_S2APSKCarLoopCut30; 1121 } else if (chip_id == 0x20) { 1122 cls2 = FE_STV0900_S2CarLoopCut20; 1123 cllqs2 = FE_STV0900_S2LowQPCarLoopCut20; 1124 cllas2 = FE_STV0900_S2APSKCarLoopCut20; 1125 } else { 1126 cls2 = FE_STV0900_S2CarLoopCut30; 1127 cllqs2 = FE_STV0900_S2LowQPCarLoopCut30; 1128 cllas2 = FE_STV0900_S2APSKCarLoopCut30; 1129 } 1130 1131 if (modcode < STV0900_QPSK_12) { 1132 i = 0; 1133 while ((i < 3) && (modcode != cllqs2[i].modcode)) 1134 i++; 1135 1136 if (i >= 3) 1137 i = 2; 1138 } else { 1139 i = 0; 1140 while ((i < 14) && (modcode != cls2[i].modcode)) 1141 i++; 1142 1143 if (i >= 14) { 1144 i = 0; 1145 while ((i < 11) && (modcode != cllas2[i].modcode)) 1146 i++; 1147 1148 if (i >= 11) 1149 i = 10; 1150 } 1151 } 1152 1153 if (modcode <= STV0900_QPSK_25) { 1154 if (pilot) { 1155 if (srate <= 3000000) 1156 aclc_value = cllqs2[i].car_loop_pilots_on_2; 1157 else if (srate <= 7000000) 1158 aclc_value = cllqs2[i].car_loop_pilots_on_5; 1159 else if (srate <= 15000000) 1160 aclc_value = cllqs2[i].car_loop_pilots_on_10; 1161 else if (srate <= 25000000) 1162 aclc_value = cllqs2[i].car_loop_pilots_on_20; 1163 else 1164 aclc_value = cllqs2[i].car_loop_pilots_on_30; 1165 } else { 1166 if (srate <= 3000000) 1167 aclc_value = cllqs2[i].car_loop_pilots_off_2; 1168 else if (srate <= 7000000) 1169 aclc_value = cllqs2[i].car_loop_pilots_off_5; 1170 else if (srate <= 15000000) 1171 aclc_value = cllqs2[i].car_loop_pilots_off_10; 1172 else if (srate <= 25000000) 1173 aclc_value = cllqs2[i].car_loop_pilots_off_20; 1174 else 1175 aclc_value = cllqs2[i].car_loop_pilots_off_30; 1176 } 1177 1178 } else if (modcode <= STV0900_8PSK_910) { 1179 if (pilot) { 1180 if (srate <= 3000000) 1181 aclc_value = cls2[i].car_loop_pilots_on_2; 1182 else if (srate <= 7000000) 1183 aclc_value = cls2[i].car_loop_pilots_on_5; 1184 else if (srate <= 15000000) 1185 aclc_value = cls2[i].car_loop_pilots_on_10; 1186 else if (srate <= 25000000) 1187 aclc_value = cls2[i].car_loop_pilots_on_20; 1188 else 1189 aclc_value = cls2[i].car_loop_pilots_on_30; 1190 } else { 1191 if (srate <= 3000000) 1192 aclc_value = cls2[i].car_loop_pilots_off_2; 1193 else if (srate <= 7000000) 1194 aclc_value = cls2[i].car_loop_pilots_off_5; 1195 else if (srate <= 15000000) 1196 aclc_value = cls2[i].car_loop_pilots_off_10; 1197 else if (srate <= 25000000) 1198 aclc_value = cls2[i].car_loop_pilots_off_20; 1199 else 1200 aclc_value = cls2[i].car_loop_pilots_off_30; 1201 } 1202 1203 } else { 1204 if (srate <= 3000000) 1205 aclc_value = cllas2[i].car_loop_pilots_on_2; 1206 else if (srate <= 7000000) 1207 aclc_value = cllas2[i].car_loop_pilots_on_5; 1208 else if (srate <= 15000000) 1209 aclc_value = cllas2[i].car_loop_pilots_on_10; 1210 else if (srate <= 25000000) 1211 aclc_value = cllas2[i].car_loop_pilots_on_20; 1212 else 1213 aclc_value = cllas2[i].car_loop_pilots_on_30; 1214 } 1215 1216 return aclc_value; 1217} 1218 1219u8 stv0900_get_optim_short_carr_loop(s32 srate, 1220 enum fe_stv0900_modulation modulation, 1221 u8 chip_id) 1222{ 1223 const struct stv0900_short_frames_car_loop_optim *s2scl; 1224 const struct stv0900_short_frames_car_loop_optim_vs_mod *s2sclc30; 1225 s32 mod_index = 0; 1226 u8 aclc_value = 0x0b; 1227 1228 dprintk("%s\n", __func__); 1229 1230 s2scl = FE_STV0900_S2ShortCarLoop; 1231 s2sclc30 = FE_STV0900_S2ShortCarLoopCut30; 1232 1233 switch (modulation) { 1234 case STV0900_QPSK: 1235 default: 1236 mod_index = 0; 1237 break; 1238 case STV0900_8PSK: 1239 mod_index = 1; 1240 break; 1241 case STV0900_16APSK: 1242 mod_index = 2; 1243 break; 1244 case STV0900_32APSK: 1245 mod_index = 3; 1246 break; 1247 } 1248 1249 if (chip_id >= 0x30) { 1250 if (srate <= 3000000) 1251 aclc_value = s2sclc30[mod_index].car_loop_2; 1252 else if (srate <= 7000000) 1253 aclc_value = s2sclc30[mod_index].car_loop_5; 1254 else if (srate <= 15000000) 1255 aclc_value = s2sclc30[mod_index].car_loop_10; 1256 else if (srate <= 25000000) 1257 aclc_value = s2sclc30[mod_index].car_loop_20; 1258 else 1259 aclc_value = s2sclc30[mod_index].car_loop_30; 1260 1261 } else if (chip_id >= 0x20) { 1262 if (srate <= 3000000) 1263 aclc_value = s2scl[mod_index].car_loop_cut20_2; 1264 else if (srate <= 7000000) 1265 aclc_value = s2scl[mod_index].car_loop_cut20_5; 1266 else if (srate <= 15000000) 1267 aclc_value = s2scl[mod_index].car_loop_cut20_10; 1268 else if (srate <= 25000000) 1269 aclc_value = s2scl[mod_index].car_loop_cut20_20; 1270 else 1271 aclc_value = s2scl[mod_index].car_loop_cut20_30; 1272 1273 } else { 1274 if (srate <= 3000000) 1275 aclc_value = s2scl[mod_index].car_loop_cut12_2; 1276 else if (srate <= 7000000) 1277 aclc_value = s2scl[mod_index].car_loop_cut12_5; 1278 else if (srate <= 15000000) 1279 aclc_value = s2scl[mod_index].car_loop_cut12_10; 1280 else if (srate <= 25000000) 1281 aclc_value = s2scl[mod_index].car_loop_cut12_20; 1282 else 1283 aclc_value = s2scl[mod_index].car_loop_cut12_30; 1284 1285 } 1286 1287 return aclc_value; 1288} 1289 1290static 1291enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *intp, 1292 enum fe_stv0900_demod_mode LDPC_Mode, 1293 enum fe_stv0900_demod_num demod) 1294{ 1295 enum fe_stv0900_error error = STV0900_NO_ERROR; 1296 s32 reg_ind; 1297 1298 dprintk("%s\n", __func__); 1299 1300 switch (LDPC_Mode) { 1301 case STV0900_DUAL: 1302 default: 1303 if ((intp->demod_mode != STV0900_DUAL) 1304 || (stv0900_get_bits(intp, F0900_DDEMOD) != 1)) { 1305 stv0900_write_reg(intp, R0900_GENCFG, 0x1d); 1306 1307 intp->demod_mode = STV0900_DUAL; 1308 1309 stv0900_write_bits(intp, F0900_FRESFEC, 1); 1310 stv0900_write_bits(intp, F0900_FRESFEC, 0); 1311 1312 for (reg_ind = 0; reg_ind < 7; reg_ind++) 1313 stv0900_write_reg(intp, 1314 R0900_P1_MODCODLST0 + reg_ind, 1315 0xff); 1316 for (reg_ind = 0; reg_ind < 8; reg_ind++) 1317 stv0900_write_reg(intp, 1318 R0900_P1_MODCODLST7 + reg_ind, 1319 0xcc); 1320 1321 stv0900_write_reg(intp, R0900_P1_MODCODLSTE, 0xff); 1322 stv0900_write_reg(intp, R0900_P1_MODCODLSTF, 0xcf); 1323 1324 for (reg_ind = 0; reg_ind < 7; reg_ind++) 1325 stv0900_write_reg(intp, 1326 R0900_P2_MODCODLST0 + reg_ind, 1327 0xff); 1328 for (reg_ind = 0; reg_ind < 8; reg_ind++) 1329 stv0900_write_reg(intp, 1330 R0900_P2_MODCODLST7 + reg_ind, 1331 0xcc); 1332 1333 stv0900_write_reg(intp, R0900_P2_MODCODLSTE, 0xff); 1334 stv0900_write_reg(intp, R0900_P2_MODCODLSTF, 0xcf); 1335 } 1336 1337 break; 1338 case STV0900_SINGLE: 1339 if (demod == STV0900_DEMOD_2) { 1340 stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_1); 1341 stv0900_activate_s2_modcod_single(intp, 1342 STV0900_DEMOD_2); 1343 stv0900_write_reg(intp, R0900_GENCFG, 0x06); 1344 } else { 1345 stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_2); 1346 stv0900_activate_s2_modcod_single(intp, 1347 STV0900_DEMOD_1); 1348 stv0900_write_reg(intp, R0900_GENCFG, 0x04); 1349 } 1350 1351 intp->demod_mode = STV0900_SINGLE; 1352 1353 stv0900_write_bits(intp, F0900_FRESFEC, 1); 1354 stv0900_write_bits(intp, F0900_FRESFEC, 0); 1355 stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 1); 1356 stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 0); 1357 stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 1); 1358 stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 0); 1359 break; 1360 } 1361 1362 return error; 1363} 1364 1365static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe, 1366 struct stv0900_init_params *p_init) 1367{ 1368 struct stv0900_state *state = fe->demodulator_priv; 1369 enum fe_stv0900_error error = STV0900_NO_ERROR; 1370 enum fe_stv0900_error demodError = STV0900_NO_ERROR; 1371 struct stv0900_internal *intp = NULL; 1372 int selosci, i; 1373 1374 struct stv0900_inode *temp_int = find_inode(state->i2c_adap, 1375 state->config->demod_address); 1376 1377 dprintk("%s\n", __func__); 1378 1379 if ((temp_int != NULL) && (p_init->demod_mode == STV0900_DUAL)) { 1380 state->internal = temp_int->internal; 1381 (state->internal->dmds_used)++; 1382 dprintk("%s: Find Internal Structure!\n", __func__); 1383 return STV0900_NO_ERROR; 1384 } else { 1385 state->internal = kmalloc(sizeof(struct stv0900_internal), 1386 GFP_KERNEL); 1387 if (state->internal == NULL) 1388 return STV0900_INVALID_HANDLE; 1389 temp_int = append_internal(state->internal); 1390 if (temp_int == NULL) { 1391 kfree(state->internal); 1392 state->internal = NULL; 1393 return STV0900_INVALID_HANDLE; 1394 } 1395 state->internal->dmds_used = 1; 1396 state->internal->i2c_adap = state->i2c_adap; 1397 state->internal->i2c_addr = state->config->demod_address; 1398 state->internal->clkmode = state->config->clkmode; 1399 state->internal->errs = STV0900_NO_ERROR; 1400 dprintk("%s: Create New Internal Structure!\n", __func__); 1401 } 1402 1403 if (state->internal == NULL) { 1404 error = STV0900_INVALID_HANDLE; 1405 return error; 1406 } 1407 1408 demodError = stv0900_initialize(state->internal); 1409 if (demodError == STV0900_NO_ERROR) { 1410 error = STV0900_NO_ERROR; 1411 } else { 1412 if (demodError == STV0900_INVALID_HANDLE) 1413 error = STV0900_INVALID_HANDLE; 1414 else 1415 error = STV0900_I2C_ERROR; 1416 1417 return error; 1418 } 1419 1420 intp = state->internal; 1421 1422 intp->demod_mode = p_init->demod_mode; 1423 stv0900_st_dvbs2_single(intp, intp->demod_mode, STV0900_DEMOD_1); 1424 intp->chip_id = stv0900_read_reg(intp, R0900_MID); 1425 intp->rolloff = p_init->rolloff; 1426 intp->quartz = p_init->dmd_ref_clk; 1427 1428 stv0900_write_bits(intp, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff); 1429 stv0900_write_bits(intp, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff); 1430 1431 intp->ts_config = p_init->ts_config; 1432 if (intp->ts_config == NULL) 1433 stv0900_set_ts_parallel_serial(intp, 1434 p_init->path1_ts_clock, 1435 p_init->path2_ts_clock); 1436 else { 1437 for (i = 0; intp->ts_config[i].addr != 0xffff; i++) 1438 stv0900_write_reg(intp, 1439 intp->ts_config[i].addr, 1440 intp->ts_config[i].val); 1441 1442 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1); 1443 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0); 1444 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1); 1445 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0); 1446 } 1447 1448 intp->tuner_type[0] = p_init->tuner1_type; 1449 intp->tuner_type[1] = p_init->tuner2_type; 1450 /* tuner init */ 1451 switch (p_init->tuner1_type) { 1452 case 3: /*FE_AUTO_STB6100:*/ 1453 stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x3c); 1454 stv0900_write_reg(intp, R0900_P1_TNRCFG2, 0x86); 1455 stv0900_write_reg(intp, R0900_P1_TNRCFG3, 0x18); 1456 stv0900_write_reg(intp, R0900_P1_TNRXTAL, 27); /* 27MHz */ 1457 stv0900_write_reg(intp, R0900_P1_TNRSTEPS, 0x05); 1458 stv0900_write_reg(intp, R0900_P1_TNRGAIN, 0x17); 1459 stv0900_write_reg(intp, R0900_P1_TNRADJ, 0x1f); 1460 stv0900_write_reg(intp, R0900_P1_TNRCTL2, 0x0); 1461 stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 3); 1462 break; 1463 /* case FE_SW_TUNER: */ 1464 default: 1465 stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 6); 1466 break; 1467 } 1468 1469 stv0900_write_bits(intp, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress); 1470 switch (p_init->tuner1_adc) { 1471 case 1: 1472 stv0900_write_reg(intp, R0900_TSTTNR1, 0x26); 1473 break; 1474 default: 1475 break; 1476 } 1477 1478 stv0900_write_reg(intp, R0900_P1_TNRLD, 1); /* hw tuner */ 1479 1480 /* tuner init */ 1481 switch (p_init->tuner2_type) { 1482 case 3: /*FE_AUTO_STB6100:*/ 1483 stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x3c); 1484 stv0900_write_reg(intp, R0900_P2_TNRCFG2, 0x86); 1485 stv0900_write_reg(intp, R0900_P2_TNRCFG3, 0x18); 1486 stv0900_write_reg(intp, R0900_P2_TNRXTAL, 27); /* 27MHz */ 1487 stv0900_write_reg(intp, R0900_P2_TNRSTEPS, 0x05); 1488 stv0900_write_reg(intp, R0900_P2_TNRGAIN, 0x17); 1489 stv0900_write_reg(intp, R0900_P2_TNRADJ, 0x1f); 1490 stv0900_write_reg(intp, R0900_P2_TNRCTL2, 0x0); 1491 stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 3); 1492 break; 1493 /* case FE_SW_TUNER: */ 1494 default: 1495 stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 6); 1496 break; 1497 } 1498 1499 stv0900_write_bits(intp, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress); 1500 switch (p_init->tuner2_adc) { 1501 case 1: 1502 stv0900_write_reg(intp, R0900_TSTTNR3, 0x26); 1503 break; 1504 default: 1505 break; 1506 } 1507 1508 stv0900_write_reg(intp, R0900_P2_TNRLD, 1); /* hw tuner */ 1509 1510 stv0900_write_bits(intp, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inv); 1511 stv0900_write_bits(intp, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inv); 1512 stv0900_set_mclk(intp, 135000000); 1513 msleep(3); 1514 1515 switch (intp->clkmode) { 1516 case 0: 1517 case 2: 1518 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | intp->clkmode); 1519 break; 1520 default: 1521 selosci = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL); 1522 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | selosci); 1523 break; 1524 } 1525 msleep(3); 1526 1527 intp->mclk = stv0900_get_mclk_freq(intp, intp->quartz); 1528 if (intp->errs) 1529 error = STV0900_I2C_ERROR; 1530 1531 return error; 1532} 1533 1534static int stv0900_status(struct stv0900_internal *intp, 1535 enum fe_stv0900_demod_num demod) 1536{ 1537 enum fe_stv0900_search_state demod_state; 1538 int locked = FALSE; 1539 u8 tsbitrate0_val, tsbitrate1_val; 1540 s32 bitrate; 1541 1542 demod_state = stv0900_get_bits(intp, HEADER_MODE); 1543 switch (demod_state) { 1544 case STV0900_SEARCH: 1545 case STV0900_PLH_DETECTED: 1546 default: 1547 locked = FALSE; 1548 break; 1549 case STV0900_DVBS2_FOUND: 1550 locked = stv0900_get_bits(intp, LOCK_DEFINITIF) && 1551 stv0900_get_bits(intp, PKTDELIN_LOCK) && 1552 stv0900_get_bits(intp, TSFIFO_LINEOK); 1553 break; 1554 case STV0900_DVBS_FOUND: 1555 locked = stv0900_get_bits(intp, LOCK_DEFINITIF) && 1556 stv0900_get_bits(intp, LOCKEDVIT) && 1557 stv0900_get_bits(intp, TSFIFO_LINEOK); 1558 break; 1559 } 1560 1561 dprintk("%s: locked = %d\n", __func__, locked); 1562 1563 if (stvdebug) { 1564 /* Print TS bitrate */ 1565 tsbitrate0_val = stv0900_read_reg(intp, TSBITRATE0); 1566 tsbitrate1_val = stv0900_read_reg(intp, TSBITRATE1); 1567 /* Formula Bit rate = Mclk * px_tsfifo_bitrate / 16384 */ 1568 bitrate = (stv0900_get_mclk_freq(intp, intp->quartz)/1000000) 1569 * (tsbitrate1_val << 8 | tsbitrate0_val); 1570 bitrate /= 16384; 1571 dprintk("TS bitrate = %d Mbit/sec \n", bitrate); 1572 }; 1573 1574 return locked; 1575} 1576 1577static enum dvbfe_search stv0900_search(struct dvb_frontend *fe, 1578 struct dvb_frontend_parameters *params) 1579{ 1580 struct stv0900_state *state = fe->demodulator_priv; 1581 struct stv0900_internal *intp = state->internal; 1582 enum fe_stv0900_demod_num demod = state->demod; 1583 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1584 1585 struct stv0900_search_params p_search; 1586 struct stv0900_signal_info p_result; 1587 1588 enum fe_stv0900_error error = STV0900_NO_ERROR; 1589 1590 dprintk("%s: ", __func__); 1591 1592 if (!(INRANGE(100000, c->symbol_rate, 70000000))) 1593 return DVBFE_ALGO_SEARCH_FAILED; 1594 1595 if (state->config->set_ts_params) 1596 state->config->set_ts_params(fe, 0); 1597 1598 p_result.locked = FALSE; 1599 p_search.path = demod; 1600 p_search.frequency = c->frequency; 1601 p_search.symbol_rate = c->symbol_rate; 1602 p_search.search_range = 10000000; 1603 p_search.fec = STV0900_FEC_UNKNOWN; 1604 p_search.standard = STV0900_AUTO_SEARCH; 1605 p_search.iq_inversion = STV0900_IQ_AUTO; 1606 p_search.search_algo = STV0900_BLIND_SEARCH; 1607 1608 intp->srch_standard[demod] = p_search.standard; 1609 intp->symbol_rate[demod] = p_search.symbol_rate; 1610 intp->srch_range[demod] = p_search.search_range; 1611 intp->freq[demod] = p_search.frequency; 1612 intp->srch_algo[demod] = p_search.search_algo; 1613 intp->srch_iq_inv[demod] = p_search.iq_inversion; 1614 intp->fec[demod] = p_search.fec; 1615 if ((stv0900_algo(fe) == STV0900_RANGEOK) && 1616 (intp->errs == STV0900_NO_ERROR)) { 1617 p_result.locked = intp->result[demod].locked; 1618 p_result.standard = intp->result[demod].standard; 1619 p_result.frequency = intp->result[demod].frequency; 1620 p_result.symbol_rate = intp->result[demod].symbol_rate; 1621 p_result.fec = intp->result[demod].fec; 1622 p_result.modcode = intp->result[demod].modcode; 1623 p_result.pilot = intp->result[demod].pilot; 1624 p_result.frame_len = intp->result[demod].frame_len; 1625 p_result.spectrum = intp->result[demod].spectrum; 1626 p_result.rolloff = intp->result[demod].rolloff; 1627 p_result.modulation = intp->result[demod].modulation; 1628 } else { 1629 p_result.locked = FALSE; 1630 switch (intp->err[demod]) { 1631 case STV0900_I2C_ERROR: 1632 error = STV0900_I2C_ERROR; 1633 break; 1634 case STV0900_NO_ERROR: 1635 default: 1636 error = STV0900_SEARCH_FAILED; 1637 break; 1638 } 1639 } 1640 1641 if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) { 1642 dprintk("Search Success\n"); 1643 return DVBFE_ALGO_SEARCH_SUCCESS; 1644 } else { 1645 dprintk("Search Fail\n"); 1646 return DVBFE_ALGO_SEARCH_FAILED; 1647 } 1648 1649} 1650 1651static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status) 1652{ 1653 struct stv0900_state *state = fe->demodulator_priv; 1654 1655 dprintk("%s: ", __func__); 1656 1657 if ((stv0900_status(state->internal, state->demod)) == TRUE) { 1658 dprintk("DEMOD LOCK OK\n"); 1659 *status = FE_HAS_CARRIER 1660 | FE_HAS_VITERBI 1661 | FE_HAS_SYNC 1662 | FE_HAS_LOCK; 1663 } else 1664 dprintk("DEMOD LOCK FAIL\n"); 1665 1666 return 0; 1667} 1668 1669static int stv0900_track(struct dvb_frontend *fe, 1670 struct dvb_frontend_parameters *p) 1671{ 1672 return 0; 1673} 1674 1675static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts) 1676{ 1677 1678 struct stv0900_state *state = fe->demodulator_priv; 1679 struct stv0900_internal *intp = state->internal; 1680 enum fe_stv0900_demod_num demod = state->demod; 1681 1682 if (stop_ts == TRUE) 1683 stv0900_write_bits(intp, RST_HWARE, 1); 1684 else 1685 stv0900_write_bits(intp, RST_HWARE, 0); 1686 1687 return 0; 1688} 1689 1690static int stv0900_diseqc_init(struct dvb_frontend *fe) 1691{ 1692 struct stv0900_state *state = fe->demodulator_priv; 1693 struct stv0900_internal *intp = state->internal; 1694 enum fe_stv0900_demod_num demod = state->demod; 1695 1696 stv0900_write_bits(intp, DISTX_MODE, state->config->diseqc_mode); 1697 stv0900_write_bits(intp, DISEQC_RESET, 1); 1698 stv0900_write_bits(intp, DISEQC_RESET, 0); 1699 1700 return 0; 1701} 1702 1703static int stv0900_init(struct dvb_frontend *fe) 1704{ 1705 dprintk("%s\n", __func__); 1706 1707 stv0900_stop_ts(fe, 1); 1708 stv0900_diseqc_init(fe); 1709 1710 return 0; 1711} 1712 1713static int stv0900_diseqc_send(struct stv0900_internal *intp , u8 *data, 1714 u32 NbData, enum fe_stv0900_demod_num demod) 1715{ 1716 s32 i = 0; 1717 1718 stv0900_write_bits(intp, DIS_PRECHARGE, 1); 1719 while (i < NbData) { 1720 while (stv0900_get_bits(intp, FIFO_FULL)) 1721 ;/* checkpatch complains */ 1722 stv0900_write_reg(intp, DISTXDATA, data[i]); 1723 i++; 1724 } 1725 1726 stv0900_write_bits(intp, DIS_PRECHARGE, 0); 1727 i = 0; 1728 while ((stv0900_get_bits(intp, TX_IDLE) != 1) && (i < 10)) { 1729 msleep(10); 1730 i++; 1731 } 1732 1733 return 0; 1734} 1735 1736static int stv0900_send_master_cmd(struct dvb_frontend *fe, 1737 struct dvb_diseqc_master_cmd *cmd) 1738{ 1739 struct stv0900_state *state = fe->demodulator_priv; 1740 1741 return stv0900_diseqc_send(state->internal, 1742 cmd->msg, 1743 cmd->msg_len, 1744 state->demod); 1745} 1746 1747static int stv0900_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst) 1748{ 1749 struct stv0900_state *state = fe->demodulator_priv; 1750 struct stv0900_internal *intp = state->internal; 1751 enum fe_stv0900_demod_num demod = state->demod; 1752 u8 data; 1753 1754 1755 switch (burst) { 1756 case SEC_MINI_A: 1757 stv0900_write_bits(intp, DISTX_MODE, 3);/* Unmodulated */ 1758 data = 0x00; 1759 stv0900_diseqc_send(intp, &data, 1, state->demod); 1760 break; 1761 case SEC_MINI_B: 1762 stv0900_write_bits(intp, DISTX_MODE, 2);/* Modulated */ 1763 data = 0xff; 1764 stv0900_diseqc_send(intp, &data, 1, state->demod); 1765 break; 1766 } 1767 1768 return 0; 1769} 1770 1771static int stv0900_recv_slave_reply(struct dvb_frontend *fe, 1772 struct dvb_diseqc_slave_reply *reply) 1773{ 1774 struct stv0900_state *state = fe->demodulator_priv; 1775 struct stv0900_internal *intp = state->internal; 1776 enum fe_stv0900_demod_num demod = state->demod; 1777 s32 i = 0; 1778 1779 reply->msg_len = 0; 1780 1781 while ((stv0900_get_bits(intp, RX_END) != 1) && (i < 10)) { 1782 msleep(10); 1783 i++; 1784 } 1785 1786 if (stv0900_get_bits(intp, RX_END)) { 1787 reply->msg_len = stv0900_get_bits(intp, FIFO_BYTENBR); 1788 1789 for (i = 0; i < reply->msg_len; i++) 1790 reply->msg[i] = stv0900_read_reg(intp, DISRXDATA); 1791 } 1792 1793 return 0; 1794} 1795 1796static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t toneoff) 1797{ 1798 struct stv0900_state *state = fe->demodulator_priv; 1799 struct stv0900_internal *intp = state->internal; 1800 enum fe_stv0900_demod_num demod = state->demod; 1801 1802 dprintk("%s: %s\n", __func__, ((toneoff == 0) ? "On" : "Off")); 1803 1804 switch (toneoff) { 1805 case SEC_TONE_ON: 1806 /*Set the DiseqC mode to 22Khz _continues_ tone*/ 1807 stv0900_write_bits(intp, DISTX_MODE, 0); 1808 stv0900_write_bits(intp, DISEQC_RESET, 1); 1809 /*release DiseqC reset to enable the 22KHz tone*/ 1810 stv0900_write_bits(intp, DISEQC_RESET, 0); 1811 break; 1812 case SEC_TONE_OFF: 1813 /*return diseqc mode to config->diseqc_mode. 1814 Usually it's without _continues_ tone */ 1815 stv0900_write_bits(intp, DISTX_MODE, 1816 state->config->diseqc_mode); 1817 /*maintain the DiseqC reset to disable the 22KHz tone*/ 1818 stv0900_write_bits(intp, DISEQC_RESET, 1); 1819 stv0900_write_bits(intp, DISEQC_RESET, 0); 1820 break; 1821 default: 1822 return -EINVAL; 1823 } 1824 1825 return 0; 1826} 1827 1828static void stv0900_release(struct dvb_frontend *fe) 1829{ 1830 struct stv0900_state *state = fe->demodulator_priv; 1831 1832 dprintk("%s\n", __func__); 1833 1834 if ((--(state->internal->dmds_used)) <= 0) { 1835 1836 dprintk("%s: Actually removing\n", __func__); 1837 1838 remove_inode(state->internal); 1839 kfree(state->internal); 1840 } 1841 1842 kfree(state); 1843} 1844 1845static struct dvb_frontend_ops stv0900_ops = { 1846 1847 .info = { 1848 .name = "STV0900 frontend", 1849 .type = FE_QPSK, 1850 .frequency_min = 950000, 1851 .frequency_max = 2150000, 1852 .frequency_stepsize = 125, 1853 .frequency_tolerance = 0, 1854 .symbol_rate_min = 1000000, 1855 .symbol_rate_max = 45000000, 1856 .symbol_rate_tolerance = 500, 1857 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | 1858 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | 1859 FE_CAN_FEC_7_8 | FE_CAN_QPSK | 1860 FE_CAN_2G_MODULATION | 1861 FE_CAN_FEC_AUTO 1862 }, 1863 .release = stv0900_release, 1864 .init = stv0900_init, 1865 .get_frontend_algo = stv0900_frontend_algo, 1866 .i2c_gate_ctrl = stv0900_i2c_gate_ctrl, 1867 .diseqc_send_master_cmd = stv0900_send_master_cmd, 1868 .diseqc_send_burst = stv0900_send_burst, 1869 .diseqc_recv_slave_reply = stv0900_recv_slave_reply, 1870 .set_tone = stv0900_set_tone, 1871 .set_property = stb0900_set_property, 1872 .get_property = stb0900_get_property, 1873 .search = stv0900_search, 1874 .track = stv0900_track, 1875 .read_status = stv0900_read_status, 1876 .read_ber = stv0900_read_ber, 1877 .read_signal_strength = stv0900_read_signal_strength, 1878 .read_snr = stv0900_read_snr, 1879 .read_ucblocks = stv0900_read_ucblocks, 1880}; 1881 1882struct dvb_frontend *stv0900_attach(const struct stv0900_config *config, 1883 struct i2c_adapter *i2c, 1884 int demod) 1885{ 1886 struct stv0900_state *state = NULL; 1887 struct stv0900_init_params init_params; 1888 enum fe_stv0900_error err_stv0900; 1889 1890 state = kzalloc(sizeof(struct stv0900_state), GFP_KERNEL); 1891 if (state == NULL) 1892 goto error; 1893 1894 state->demod = demod; 1895 state->config = config; 1896 state->i2c_adap = i2c; 1897 1898 memcpy(&state->frontend.ops, &stv0900_ops, 1899 sizeof(struct dvb_frontend_ops)); 1900 state->frontend.demodulator_priv = state; 1901 1902 switch (demod) { 1903 case 0: 1904 case 1: 1905 init_params.dmd_ref_clk = config->xtal; 1906 init_params.demod_mode = config->demod_mode; 1907 init_params.rolloff = STV0900_35; 1908 init_params.path1_ts_clock = config->path1_mode; 1909 init_params.tun1_maddress = config->tun1_maddress; 1910 init_params.tun1_iq_inv = STV0900_IQ_NORMAL; 1911 init_params.tuner1_adc = config->tun1_adc; 1912 init_params.tuner1_type = config->tun1_type; 1913 init_params.path2_ts_clock = config->path2_mode; 1914 init_params.ts_config = config->ts_config_regs; 1915 init_params.tun2_maddress = config->tun2_maddress; 1916 init_params.tuner2_adc = config->tun2_adc; 1917 init_params.tuner2_type = config->tun2_type; 1918 init_params.tun2_iq_inv = STV0900_IQ_SWAPPED; 1919 1920 err_stv0900 = stv0900_init_internal(&state->frontend, 1921 &init_params); 1922 1923 if (err_stv0900) 1924 goto error; 1925 1926 break; 1927 default: 1928 goto error; 1929 break; 1930 } 1931 1932 dprintk("%s: Attaching STV0900 demodulator(%d) \n", __func__, demod); 1933 return &state->frontend; 1934 1935error: 1936 dprintk("%s: Failed to attach STV0900 demodulator(%d) \n", 1937 __func__, demod); 1938 kfree(state); 1939 return NULL; 1940} 1941EXPORT_SYMBOL(stv0900_attach); 1942 1943MODULE_PARM_DESC(debug, "Set debug"); 1944 1945MODULE_AUTHOR("Igor M. Liplianin"); 1946MODULE_DESCRIPTION("ST STV0900 frontend"); 1947MODULE_LICENSE("GPL"); 1948