cx18-mailbox.c revision 18b5dc2ed7f0ede825dd1f93fefc7a61aba866e3
1/* 2 * cx18 mailbox functions 3 * 4 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 19 * 02111-1307 USA 20 */ 21 22#include <stdarg.h> 23 24#include "cx18-driver.h" 25#include "cx18-io.h" 26#include "cx18-scb.h" 27#include "cx18-irq.h" 28#include "cx18-mailbox.h" 29#include "cx18-queue.h" 30#include "cx18-streams.h" 31 32static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" }; 33 34#define API_FAST (1 << 2) /* Short timeout */ 35#define API_SLOW (1 << 3) /* Additional 300ms timeout */ 36 37struct cx18_api_info { 38 u32 cmd; 39 u8 flags; /* Flags, see above */ 40 u8 rpu; /* Processing unit */ 41 const char *name; /* The name of the command */ 42}; 43 44#define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x } 45 46static const struct cx18_api_info api_info[] = { 47 /* MPEG encoder API */ 48 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0), 49 API_ENTRY(CPU, CX18_EPU_DEBUG, 0), 50 API_ENTRY(CPU, CX18_CREATE_TASK, 0), 51 API_ENTRY(CPU, CX18_DESTROY_TASK, 0), 52 API_ENTRY(CPU, CX18_CPU_CAPTURE_START, API_SLOW), 53 API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP, API_SLOW), 54 API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE, 0), 55 API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME, 0), 56 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0), 57 API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 0), 58 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN, 0), 59 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE, 0), 60 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION, 0), 61 API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM, 0), 62 API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 0), 63 API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING, 0), 64 API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE, 0), 65 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS, 0), 66 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE, 0), 67 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE, 0), 68 API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS, 0), 69 API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM, API_SLOW), 70 API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO, 0), 71 API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT, 0), 72 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID, 0), 73 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID, 0), 74 API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE, 0), 75 API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE, 0), 76 API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION, 0), 77 API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO, 0), 78 API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME, 0), 79 API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM, 0), 80 API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER, 0), 81 API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS, 0), 82 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0), 83 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST), 84 API_ENTRY(CPU, CX18_APU_RESETAI, API_FAST), 85 API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, API_SLOW), 86 API_ENTRY(0, 0, 0), 87}; 88 89static const struct cx18_api_info *find_api_info(u32 cmd) 90{ 91 int i; 92 93 for (i = 0; api_info[i].cmd; i++) 94 if (api_info[i].cmd == cmd) 95 return &api_info[i]; 96 return NULL; 97} 98 99static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name) 100{ 101 char argstr[MAX_MB_ARGUMENTS*11+1]; 102 char *p; 103 int i; 104 105 if (!(cx18_debug & CX18_DBGFLG_API)) 106 return; 107 108 for (i = 0, p = argstr; i < MAX_MB_ARGUMENTS; i++, p += 11) { 109 /* kernel snprintf() appends '\0' always */ 110 snprintf(p, 12, " %#010x", mb->args[i]); 111 } 112 CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s" 113 "\n", name, mb->request, mb->ack, mb->cmd, mb->error, argstr); 114} 115 116 117/* 118 * Functions that run in a work_queue work handling context 119 */ 120 121static void epu_dma_done(struct cx18 *cx, struct cx18_epu_work_order *order) 122{ 123 u32 handle, mdl_ack_count; 124 struct cx18_mailbox *mb; 125 struct cx18_mdl_ack *mdl_ack; 126 struct cx18_stream *s; 127 struct cx18_buffer *buf; 128 int i; 129 130 mb = &order->mb; 131 handle = mb->args[0]; 132 s = cx18_handle_to_stream(cx, handle); 133 134 if (s == NULL) { 135 CX18_WARN("Got DMA done notification for unknown/inactive" 136 " handle %d\n", handle); 137 return; 138 } 139 140 mdl_ack_count = mb->args[2]; 141 mdl_ack = order->mdl_ack; 142 for (i = 0; i < mdl_ack_count; i++, mdl_ack++) { 143 buf = cx18_queue_get_buf(s, mdl_ack->id, mdl_ack->data_used); 144 CX18_DEBUG_HI_DMA("DMA DONE for %s (buffer %d)\n", s->name, 145 mdl_ack->id); 146 if (buf == NULL) { 147 CX18_WARN("Could not find buf %d for stream %s\n", 148 mdl_ack->id, s->name); 149 continue; 150 } 151 152 cx18_buf_sync_for_cpu(s, buf); 153 if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) { 154 CX18_DEBUG_HI_DMA("TS recv bytesused = %d\n", 155 buf->bytesused); 156 157 dvb_dmx_swfilter(&s->dvb.demux, buf->buf, 158 buf->bytesused); 159 160 cx18_buf_sync_for_device(s, buf); 161 162 if (s->handle != CX18_INVALID_TASK_HANDLE && 163 test_bit(CX18_F_S_STREAMING, &s->s_flags)) 164 cx18_vapi(cx, 165 CX18_CPU_DE_SET_MDL, 5, s->handle, 166 (void __iomem *) 167 &cx->scb->cpu_mdl[buf->id] - cx->enc_mem, 168 1, buf->id, s->buf_size); 169 } else 170 set_bit(CX18_F_B_NEED_BUF_SWAP, &buf->b_flags); 171 } 172 wake_up(&cx->dma_waitq); 173 if (s->id != -1) 174 wake_up(&s->waitq); 175} 176 177static void epu_debug(struct cx18 *cx, struct cx18_epu_work_order *order) 178{ 179 char *p; 180 char *str = order->str; 181 182 CX18_DEBUG_INFO("%x %s\n", order->mb.args[0], str); 183 p = strchr(str, '.'); 184 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str) 185 CX18_INFO("FW version: %s\n", p - 1); 186} 187 188static void epu_cmd(struct cx18 *cx, struct cx18_epu_work_order *order) 189{ 190 switch (order->rpu) { 191 case CPU: 192 { 193 switch (order->mb.cmd) { 194 case CX18_EPU_DMA_DONE: 195 epu_dma_done(cx, order); 196 break; 197 case CX18_EPU_DEBUG: 198 epu_debug(cx, order); 199 break; 200 default: 201 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n", 202 order->mb.cmd); 203 break; 204 } 205 break; 206 } 207 case APU: 208 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n", 209 order->mb.cmd); 210 break; 211 default: 212 break; 213 } 214} 215 216static 217void free_epu_work_order(struct cx18 *cx, struct cx18_epu_work_order *order) 218{ 219 atomic_set(&order->pending, 0); 220} 221 222void cx18_epu_work_handler(struct work_struct *work) 223{ 224 struct cx18_epu_work_order *order = 225 container_of(work, struct cx18_epu_work_order, work); 226 struct cx18 *cx = order->cx; 227 epu_cmd(cx, order); 228 free_epu_work_order(cx, order); 229} 230 231 232/* 233 * Functions that run in an interrupt handling context 234 */ 235 236static void mb_ack_irq(struct cx18 *cx, const struct cx18_epu_work_order *order) 237{ 238 struct cx18_mailbox __iomem *ack_mb; 239 u32 ack_irq, req; 240 241 switch (order->rpu) { 242 case APU: 243 ack_irq = IRQ_EPU_TO_APU_ACK; 244 ack_mb = &cx->scb->apu2epu_mb; 245 break; 246 case CPU: 247 ack_irq = IRQ_EPU_TO_CPU_ACK; 248 ack_mb = &cx->scb->cpu2epu_mb; 249 break; 250 default: 251 CX18_WARN("Unhandled RPU (%d) for command %x ack\n", 252 order->rpu, order->mb.cmd); 253 return; 254 } 255 256 req = order->mb.request; 257 /* Don't ack if the RPU has gotten impatient and timed us out */ 258 if (req != cx18_readl(cx, &ack_mb->request) || 259 req == cx18_readl(cx, &ack_mb->ack)) 260 return; 261 cx18_writel(cx, req, &ack_mb->ack); 262 cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq); 263 return; 264} 265 266static int epu_dma_done_irq(struct cx18 *cx, struct cx18_epu_work_order *order, 267 int stale) 268{ 269 u32 handle, mdl_ack_offset, mdl_ack_count; 270 struct cx18_mailbox *mb; 271 272 mb = &order->mb; 273 handle = mb->args[0]; 274 mdl_ack_offset = mb->args[1]; 275 mdl_ack_count = mb->args[2]; 276 277 if (handle == CX18_INVALID_TASK_HANDLE || 278 mdl_ack_count == 0 || mdl_ack_count > CX18_MAX_MDL_ACKS) { 279 if (!stale) 280 mb_ack_irq(cx, order); 281 return -1; 282 } 283 284 cx18_memcpy_fromio(cx, order->mdl_ack, cx->enc_mem + mdl_ack_offset, 285 sizeof(struct cx18_mdl_ack) * mdl_ack_count); 286 if (!stale) 287 mb_ack_irq(cx, order); 288 return 1; 289} 290 291static 292int epu_debug_irq(struct cx18 *cx, struct cx18_epu_work_order *order, int stale) 293{ 294 u32 str_offset; 295 char *str = order->str; 296 297 str[0] = '\0'; 298 str_offset = order->mb.args[1]; 299 if (str_offset) { 300 cx18_setup_page(cx, str_offset); 301 cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252); 302 str[252] = '\0'; 303 cx18_setup_page(cx, SCB_OFFSET); 304 } 305 306 if (!stale) 307 mb_ack_irq(cx, order); 308 309 return str_offset ? 1 : 0; 310} 311 312static inline 313int epu_cmd_irq(struct cx18 *cx, struct cx18_epu_work_order *order, int stale) 314{ 315 int ret = -1; 316 317 switch (order->rpu) { 318 case CPU: 319 { 320 switch (order->mb.cmd) { 321 case CX18_EPU_DMA_DONE: 322 ret = epu_dma_done_irq(cx, order, stale); 323 break; 324 case CX18_EPU_DEBUG: 325 ret = epu_debug_irq(cx, order, stale); 326 break; 327 default: 328 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n", 329 order->mb.cmd); 330 break; 331 } 332 break; 333 } 334 case APU: 335 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n", 336 order->mb.cmd); 337 break; 338 default: 339 break; 340 } 341 return ret; 342} 343 344static inline 345struct cx18_epu_work_order *alloc_epu_work_order_irq(struct cx18 *cx) 346{ 347 int i; 348 struct cx18_epu_work_order *order = NULL; 349 350 for (i = 0; i < CX18_MAX_EPU_WORK_ORDERS; i++) { 351 /* 352 * We only need "pending" atomic to inspect its contents, 353 * and need not do a check and set because: 354 * 1. Any work handler thread only clears "pending" and only 355 * on one, particular work order at a time, per handler thread. 356 * 2. "pending" is only set here, and we're serialized because 357 * we're called in an IRQ handler context. 358 */ 359 if (atomic_read(&cx->epu_work_order[i].pending) == 0) { 360 order = &cx->epu_work_order[i]; 361 atomic_set(&order->pending, 1); 362 break; 363 } 364 } 365 return order; 366} 367 368void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu) 369{ 370 struct cx18_mailbox __iomem *mb; 371 struct cx18_mailbox *order_mb; 372 struct cx18_epu_work_order *order; 373 int stale = 0; 374 int submit; 375 376 switch (rpu) { 377 case CPU: 378 mb = &cx->scb->cpu2epu_mb; 379 break; 380 case APU: 381 mb = &cx->scb->apu2epu_mb; 382 break; 383 default: 384 return; 385 } 386 387 order = alloc_epu_work_order_irq(cx); 388 if (order == NULL) { 389 CX18_WARN("Unable to find blank work order form to schedule " 390 "incoming mailbox command processing\n"); 391 return; 392 } 393 394 order->rpu = rpu; 395 order_mb = &order->mb; 396 cx18_memcpy_fromio(cx, order_mb, mb, sizeof(struct cx18_mailbox)); 397 398 if (order_mb->request == order_mb->ack) { 399 CX18_WARN("Possibly falling behind: %s self-ack'ed our incoming" 400 " %s to EPU mailbox (sequence no. %u)\n", 401 rpu_str[rpu], rpu_str[rpu], order_mb->request); 402 dump_mb(cx, order_mb, "incoming"); 403 stale = 1; 404 } 405 406 /* 407 * Individual EPU command processing is responsible for ack-ing 408 * a non-stale mailbox as soon as possible 409 */ 410 submit = epu_cmd_irq(cx, order, stale); 411 if (submit > 0) { 412 queue_work(cx18_work_queue, &order->work); 413 } 414} 415 416 417/* 418 * Functions called from a non-interrupt, non work_queue context 419 */ 420 421static void cx18_api_log_ack_delay(struct cx18 *cx, int msecs) 422{ 423 if (msecs > CX18_MAX_MB_ACK_DELAY) 424 msecs = CX18_MAX_MB_ACK_DELAY; 425 atomic_inc(&cx->mbox_stats.mb_ack_delay[msecs]); 426} 427 428static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[]) 429{ 430 const struct cx18_api_info *info = find_api_info(cmd); 431 u32 state, irq, req, ack, err; 432 struct cx18_mailbox __iomem *mb; 433 u32 __iomem *xpu_state; 434 wait_queue_head_t *waitq; 435 struct mutex *mb_lock; 436 long int timeout, ret; 437 int i; 438 439 if (info == NULL) { 440 CX18_WARN("unknown cmd %x\n", cmd); 441 return -EINVAL; 442 } 443 444 if (cmd == CX18_CPU_DE_SET_MDL) 445 CX18_DEBUG_HI_API("%s\n", info->name); 446 else 447 CX18_DEBUG_API("%s\n", info->name); 448 449 switch (info->rpu) { 450 case APU: 451 waitq = &cx->mb_apu_waitq; 452 mb_lock = &cx->epu2apu_mb_lock; 453 irq = IRQ_EPU_TO_APU; 454 mb = &cx->scb->epu2apu_mb; 455 xpu_state = &cx->scb->apu_state; 456 break; 457 case CPU: 458 waitq = &cx->mb_cpu_waitq; 459 mb_lock = &cx->epu2cpu_mb_lock; 460 irq = IRQ_EPU_TO_CPU; 461 mb = &cx->scb->epu2cpu_mb; 462 xpu_state = &cx->scb->cpu_state; 463 break; 464 default: 465 CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu); 466 return -EINVAL; 467 } 468 469 mutex_lock(mb_lock); 470 /* 471 * Wait for an in-use mailbox to complete 472 * 473 * If the XPU is responding with Ack's, the mailbox shouldn't be in 474 * a busy state, since we serialize access to it on our end. 475 * 476 * If the wait for ack after sending a previous command was interrupted 477 * by a signal, we may get here and find a busy mailbox. After waiting, 478 * mark it "not busy" from our end, if the XPU hasn't ack'ed it still. 479 */ 480 state = cx18_readl(cx, xpu_state); 481 req = cx18_readl(cx, &mb->request); 482 timeout = msecs_to_jiffies(20); /* 1 field at 50 Hz vertical refresh */ 483 ret = wait_event_timeout(*waitq, 484 (ack = cx18_readl(cx, &mb->ack)) == req, 485 timeout); 486 if (req != ack) { 487 /* waited long enough, make the mbox "not busy" from our end */ 488 cx18_writel(cx, req, &mb->ack); 489 CX18_ERR("mbox was found stuck busy when setting up for %s; " 490 "clearing busy and trying to proceed\n", info->name); 491 } else if (ret != timeout) 492 CX18_DEBUG_API("waited %u usecs for busy mbox to be acked\n", 493 jiffies_to_usecs(timeout-ret)); 494 495 /* Build the outgoing mailbox */ 496 req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1; 497 498 cx18_writel(cx, cmd, &mb->cmd); 499 for (i = 0; i < args; i++) 500 cx18_writel(cx, data[i], &mb->args[i]); 501 cx18_writel(cx, 0, &mb->error); 502 cx18_writel(cx, req, &mb->request); 503 cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */ 504 505 /* 506 * Notify the XPU and wait for it to send an Ack back 507 * 21 ms = ~ 0.5 frames at a frame rate of 24 fps 508 * 42 ms = ~ 1 frame at a frame rate of 24 fps 509 */ 510 timeout = msecs_to_jiffies((info->flags & API_FAST) ? 21 : 42); 511 512 CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n", 513 irq, info->name); 514 cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq); 515 516 ret = wait_event_timeout( 517 *waitq, 518 cx18_readl(cx, &mb->ack) == cx18_readl(cx, &mb->request), 519 timeout); 520 if (ret == 0) { 521 /* Timed out */ 522 mutex_unlock(mb_lock); 523 i = jiffies_to_msecs(timeout); 524 cx18_api_log_ack_delay(cx, i); 525 CX18_WARN("sending %s timed out waiting %d msecs for RPU " 526 "acknowledgement\n", info->name, i); 527 return -EINVAL; 528 } else if (ret < 0) { 529 /* Interrupted */ 530 mutex_unlock(mb_lock); 531 CX18_WARN("sending %s was interrupted waiting for RPU" 532 "acknowledgement\n", info->name); 533 return -EINTR; 534 } 535 536 i = jiffies_to_msecs(timeout-ret); 537 cx18_api_log_ack_delay(cx, i); 538 if (ret != timeout) 539 CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n", 540 i, info->name); 541 542 /* Collect data returned by the XPU */ 543 for (i = 0; i < MAX_MB_ARGUMENTS; i++) 544 data[i] = cx18_readl(cx, &mb->args[i]); 545 err = cx18_readl(cx, &mb->error); 546 mutex_unlock(mb_lock); 547 548 /* 549 * Wait for XPU to perform extra actions for the caller in some cases. 550 * e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all buffers 551 * back in a burst shortly thereafter 552 */ 553 if (info->flags & API_SLOW) 554 cx18_msleep_timeout(300, 0); 555 556 if (err) 557 CX18_DEBUG_API("mailbox error %08x for command %s\n", err, 558 info->name); 559 return err ? -EIO : 0; 560} 561 562int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[]) 563{ 564 return cx18_api_call(cx, cmd, args, data); 565} 566 567static int cx18_set_filter_param(struct cx18_stream *s) 568{ 569 struct cx18 *cx = s->cx; 570 u32 mode; 571 int ret; 572 573 mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0); 574 ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4, 575 s->handle, 1, mode, cx->spatial_strength); 576 mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0); 577 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4, 578 s->handle, 0, mode, cx->temporal_strength); 579 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4, 580 s->handle, 2, cx->filter_mode >> 2, 0); 581 return ret; 582} 583 584int cx18_api_func(void *priv, u32 cmd, int in, int out, 585 u32 data[CX2341X_MBOX_MAX_DATA]) 586{ 587 struct cx18 *cx = priv; 588 struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_MPG]; 589 590 switch (cmd) { 591 case CX2341X_ENC_SET_OUTPUT_PORT: 592 return 0; 593 case CX2341X_ENC_SET_FRAME_RATE: 594 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6, 595 s->handle, 0, 0, 0, 0, data[0]); 596 case CX2341X_ENC_SET_FRAME_SIZE: 597 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3, 598 s->handle, data[1], data[0]); 599 case CX2341X_ENC_SET_STREAM_TYPE: 600 return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2, 601 s->handle, data[0]); 602 case CX2341X_ENC_SET_ASPECT_RATIO: 603 return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2, 604 s->handle, data[0]); 605 606 case CX2341X_ENC_SET_GOP_PROPERTIES: 607 return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3, 608 s->handle, data[0], data[1]); 609 case CX2341X_ENC_SET_GOP_CLOSURE: 610 return 0; 611 case CX2341X_ENC_SET_AUDIO_PROPERTIES: 612 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2, 613 s->handle, data[0]); 614 case CX2341X_ENC_MUTE_AUDIO: 615 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2, 616 s->handle, data[0]); 617 case CX2341X_ENC_SET_BIT_RATE: 618 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5, 619 s->handle, data[0], data[1], data[2], data[3]); 620 case CX2341X_ENC_MUTE_VIDEO: 621 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2, 622 s->handle, data[0]); 623 case CX2341X_ENC_SET_FRAME_DROP_RATE: 624 return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2, 625 s->handle, data[0]); 626 case CX2341X_ENC_MISC: 627 return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4, 628 s->handle, data[0], data[1], data[2]); 629 case CX2341X_ENC_SET_DNR_FILTER_MODE: 630 cx->filter_mode = (data[0] & 3) | (data[1] << 2); 631 return cx18_set_filter_param(s); 632 case CX2341X_ENC_SET_DNR_FILTER_PROPS: 633 cx->spatial_strength = data[0]; 634 cx->temporal_strength = data[1]; 635 return cx18_set_filter_param(s); 636 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE: 637 return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3, 638 s->handle, data[0], data[1]); 639 case CX2341X_ENC_SET_CORING_LEVELS: 640 return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5, 641 s->handle, data[0], data[1], data[2], data[3]); 642 } 643 CX18_WARN("Unknown cmd %x\n", cmd); 644 return 0; 645} 646 647int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS], 648 u32 cmd, int args, ...) 649{ 650 va_list ap; 651 int i; 652 653 va_start(ap, args); 654 for (i = 0; i < args; i++) 655 data[i] = va_arg(ap, u32); 656 va_end(ap); 657 return cx18_api(cx, cmd, args, data); 658} 659 660int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...) 661{ 662 u32 data[MAX_MB_ARGUMENTS]; 663 va_list ap; 664 int i; 665 666 if (cx == NULL) { 667 CX18_ERR("cx == NULL (cmd=%x)\n", cmd); 668 return 0; 669 } 670 if (args > MAX_MB_ARGUMENTS) { 671 CX18_ERR("args too big (cmd=%x)\n", cmd); 672 args = MAX_MB_ARGUMENTS; 673 } 674 va_start(ap, args); 675 for (i = 0; i < args; i++) 676 data[i] = va_arg(ap, u32); 677 va_end(ap); 678 return cx18_api(cx, cmd, args, data); 679} 680