cx18-mailbox.c revision d6c7e5f8faad080e75bace5c4f2265e3513e3510
1/* 2 * cx18 mailbox functions 3 * 4 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 19 * 02111-1307 USA 20 */ 21 22#include <stdarg.h> 23 24#include "cx18-driver.h" 25#include "cx18-io.h" 26#include "cx18-scb.h" 27#include "cx18-irq.h" 28#include "cx18-mailbox.h" 29#include "cx18-queue.h" 30#include "cx18-streams.h" 31 32static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" }; 33 34#define API_FAST (1 << 2) /* Short timeout */ 35#define API_SLOW (1 << 3) /* Additional 300ms timeout */ 36 37struct cx18_api_info { 38 u32 cmd; 39 u8 flags; /* Flags, see above */ 40 u8 rpu; /* Processing unit */ 41 const char *name; /* The name of the command */ 42}; 43 44#define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x } 45 46static const struct cx18_api_info api_info[] = { 47 /* MPEG encoder API */ 48 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0), 49 API_ENTRY(CPU, CX18_EPU_DEBUG, 0), 50 API_ENTRY(CPU, CX18_CREATE_TASK, 0), 51 API_ENTRY(CPU, CX18_DESTROY_TASK, 0), 52 API_ENTRY(CPU, CX18_CPU_CAPTURE_START, API_SLOW), 53 API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP, API_SLOW), 54 API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE, 0), 55 API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME, 0), 56 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0), 57 API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 0), 58 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN, 0), 59 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE, 0), 60 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION, 0), 61 API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM, 0), 62 API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 0), 63 API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING, 0), 64 API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE, 0), 65 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS, 0), 66 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE, 0), 67 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE, 0), 68 API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS, 0), 69 API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM, API_SLOW), 70 API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO, 0), 71 API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT, 0), 72 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID, 0), 73 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID, 0), 74 API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE, 0), 75 API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE, 0), 76 API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION, 0), 77 API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO, 0), 78 API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME, 0), 79 API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM, 0), 80 API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER, 0), 81 API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS, 0), 82 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0), 83 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST), 84 API_ENTRY(CPU, CX18_APU_RESETAI, API_FAST), 85 API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, API_SLOW), 86 API_ENTRY(0, 0, 0), 87}; 88 89static const struct cx18_api_info *find_api_info(u32 cmd) 90{ 91 int i; 92 93 for (i = 0; api_info[i].cmd; i++) 94 if (api_info[i].cmd == cmd) 95 return &api_info[i]; 96 return NULL; 97} 98 99static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name) 100{ 101 char argstr[MAX_MB_ARGUMENTS*11+1]; 102 char *p; 103 int i; 104 105 if (!(cx18_debug & CX18_DBGFLG_API)) 106 return; 107 108 for (i = 0, p = argstr; i < MAX_MB_ARGUMENTS; i++, p += 11) { 109 /* kernel snprintf() appends '\0' always */ 110 snprintf(p, 12, " %#010x", mb->args[i]); 111 } 112 CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s" 113 "\n", name, mb->request, mb->ack, mb->cmd, mb->error, argstr); 114} 115 116 117/* 118 * Functions that run in a work_queue work handling context 119 */ 120 121static void epu_dma_done(struct cx18 *cx, struct cx18_epu_work_order *order) 122{ 123 u32 handle, mdl_ack_count; 124 struct cx18_mailbox *mb; 125 struct cx18_mdl_ack *mdl_ack; 126 struct cx18_stream *s; 127 struct cx18_buffer *buf; 128 int i; 129 130 mb = &order->mb; 131 handle = mb->args[0]; 132 s = cx18_handle_to_stream(cx, handle); 133 134 if (s == NULL) { 135 CX18_WARN("Got DMA done notification for unknown/inactive" 136 " handle %d\n", handle); 137 return; 138 } 139 140 mdl_ack_count = mb->args[2]; 141 mdl_ack = order->mdl_ack; 142 for (i = 0; i < mdl_ack_count; i++, mdl_ack++) { 143 buf = cx18_queue_get_buf(s, mdl_ack->id, mdl_ack->data_used); 144 CX18_DEBUG_HI_DMA("DMA DONE for %s (buffer %d)\n", s->name, 145 mdl_ack->id); 146 if (buf == NULL) { 147 CX18_WARN("Could not find buf %d for stream %s\n", 148 mdl_ack->id, s->name); 149 continue; 150 } 151 152 cx18_buf_sync_for_cpu(s, buf); 153 if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) { 154 CX18_DEBUG_HI_DMA("TS recv bytesused = %d\n", 155 buf->bytesused); 156 157 dvb_dmx_swfilter(&s->dvb.demux, buf->buf, 158 buf->bytesused); 159 160 cx18_buf_sync_for_device(s, buf); 161 162 if (s->handle != CX18_INVALID_TASK_HANDLE && 163 test_bit(CX18_F_S_STREAMING, &s->s_flags)) 164 cx18_vapi(cx, 165 CX18_CPU_DE_SET_MDL, 5, s->handle, 166 (void __iomem *) 167 &cx->scb->cpu_mdl[buf->id] - cx->enc_mem, 168 1, buf->id, s->buf_size); 169 } else 170 set_bit(CX18_F_B_NEED_BUF_SWAP, &buf->b_flags); 171 } 172 wake_up(&cx->dma_waitq); 173 if (s->id != -1) 174 wake_up(&s->waitq); 175} 176 177static void epu_debug(struct cx18 *cx, struct cx18_epu_work_order *order) 178{ 179 char *p; 180 char *str = order->str; 181 182 CX18_DEBUG_INFO("%x %s\n", order->mb.args[0], str); 183 p = strchr(str, '.'); 184 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str) 185 CX18_INFO("FW version: %s\n", p - 1); 186} 187 188static void epu_cmd(struct cx18 *cx, struct cx18_epu_work_order *order) 189{ 190 switch (order->rpu) { 191 case CPU: 192 { 193 switch (order->mb.cmd) { 194 case CX18_EPU_DMA_DONE: 195 epu_dma_done(cx, order); 196 break; 197 case CX18_EPU_DEBUG: 198 epu_debug(cx, order); 199 break; 200 default: 201 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n", 202 order->mb.cmd); 203 break; 204 } 205 break; 206 } 207 case APU: 208 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n", 209 order->mb.cmd); 210 break; 211 default: 212 break; 213 } 214} 215 216static 217void free_epu_work_order(struct cx18 *cx, struct cx18_epu_work_order *order) 218{ 219 atomic_set(&order->pending, 0); 220} 221 222void cx18_epu_work_handler(struct work_struct *work) 223{ 224 struct cx18_epu_work_order *order = 225 container_of(work, struct cx18_epu_work_order, work); 226 struct cx18 *cx = order->cx; 227 epu_cmd(cx, order); 228 free_epu_work_order(cx, order); 229} 230 231 232/* 233 * Functions that run in an interrupt handling context 234 */ 235 236static void mb_ack_irq(struct cx18 *cx, struct cx18_epu_work_order *order) 237{ 238 struct cx18_mailbox __iomem *ack_mb; 239 u32 ack_irq, req; 240 241 switch (order->rpu) { 242 case APU: 243 ack_irq = IRQ_EPU_TO_APU_ACK; 244 ack_mb = &cx->scb->apu2epu_mb; 245 break; 246 case CPU: 247 ack_irq = IRQ_EPU_TO_CPU_ACK; 248 ack_mb = &cx->scb->cpu2epu_mb; 249 break; 250 default: 251 CX18_WARN("Unhandled RPU (%d) for command %x ack\n", 252 order->rpu, order->mb.cmd); 253 return; 254 } 255 256 req = order->mb.request; 257 /* Don't ack if the RPU has gotten impatient and timed us out */ 258 if (req != cx18_readl(cx, &ack_mb->request) || 259 req == cx18_readl(cx, &ack_mb->ack)) { 260 CX18_WARN("Possibly falling behind: %s self-ack'ed our incoming" 261 " %s to EPU mailbox (sequence no. %u) while " 262 "processing\n", 263 rpu_str[order->rpu], rpu_str[order->rpu], req); 264 order->flags |= CX18_F_EWO_MB_STALE_WHILE_PROC; 265 return; 266 } 267 cx18_writel(cx, req, &ack_mb->ack); 268 cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq); 269 return; 270} 271 272static int epu_dma_done_irq(struct cx18 *cx, struct cx18_epu_work_order *order) 273{ 274 u32 handle, mdl_ack_offset, mdl_ack_count; 275 struct cx18_mailbox *mb; 276 277 mb = &order->mb; 278 handle = mb->args[0]; 279 mdl_ack_offset = mb->args[1]; 280 mdl_ack_count = mb->args[2]; 281 282 if (handle == CX18_INVALID_TASK_HANDLE || 283 mdl_ack_count == 0 || mdl_ack_count > CX18_MAX_MDL_ACKS) { 284 if ((order->flags & CX18_F_EWO_MB_STALE) == 0) 285 mb_ack_irq(cx, order); 286 return -1; 287 } 288 289 cx18_memcpy_fromio(cx, order->mdl_ack, cx->enc_mem + mdl_ack_offset, 290 sizeof(struct cx18_mdl_ack) * mdl_ack_count); 291 292 if ((order->flags & CX18_F_EWO_MB_STALE) == 0) 293 mb_ack_irq(cx, order); 294 return 1; 295} 296 297static 298int epu_debug_irq(struct cx18 *cx, struct cx18_epu_work_order *order) 299{ 300 u32 str_offset; 301 char *str = order->str; 302 303 str[0] = '\0'; 304 str_offset = order->mb.args[1]; 305 if (str_offset) { 306 cx18_setup_page(cx, str_offset); 307 cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252); 308 str[252] = '\0'; 309 cx18_setup_page(cx, SCB_OFFSET); 310 } 311 312 if ((order->flags & CX18_F_EWO_MB_STALE) == 0) 313 mb_ack_irq(cx, order); 314 315 return str_offset ? 1 : 0; 316} 317 318static inline 319int epu_cmd_irq(struct cx18 *cx, struct cx18_epu_work_order *order) 320{ 321 int ret = -1; 322 323 switch (order->rpu) { 324 case CPU: 325 { 326 switch (order->mb.cmd) { 327 case CX18_EPU_DMA_DONE: 328 ret = epu_dma_done_irq(cx, order); 329 break; 330 case CX18_EPU_DEBUG: 331 ret = epu_debug_irq(cx, order); 332 break; 333 default: 334 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n", 335 order->mb.cmd); 336 break; 337 } 338 break; 339 } 340 case APU: 341 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n", 342 order->mb.cmd); 343 break; 344 default: 345 break; 346 } 347 return ret; 348} 349 350static inline 351struct cx18_epu_work_order *alloc_epu_work_order_irq(struct cx18 *cx) 352{ 353 int i; 354 struct cx18_epu_work_order *order = NULL; 355 356 for (i = 0; i < CX18_MAX_EPU_WORK_ORDERS; i++) { 357 /* 358 * We only need "pending" atomic to inspect its contents, 359 * and need not do a check and set because: 360 * 1. Any work handler thread only clears "pending" and only 361 * on one, particular work order at a time, per handler thread. 362 * 2. "pending" is only set here, and we're serialized because 363 * we're called in an IRQ handler context. 364 */ 365 if (atomic_read(&cx->epu_work_order[i].pending) == 0) { 366 order = &cx->epu_work_order[i]; 367 atomic_set(&order->pending, 1); 368 break; 369 } 370 } 371 return order; 372} 373 374void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu) 375{ 376 struct cx18_mailbox __iomem *mb; 377 struct cx18_mailbox *order_mb; 378 struct cx18_epu_work_order *order; 379 int submit; 380 381 switch (rpu) { 382 case CPU: 383 mb = &cx->scb->cpu2epu_mb; 384 break; 385 case APU: 386 mb = &cx->scb->apu2epu_mb; 387 break; 388 default: 389 return; 390 } 391 392 order = alloc_epu_work_order_irq(cx); 393 if (order == NULL) { 394 CX18_WARN("Unable to find blank work order form to schedule " 395 "incoming mailbox command processing\n"); 396 return; 397 } 398 399 order->flags = 0; 400 order->rpu = rpu; 401 order_mb = &order->mb; 402 403 /* mb->cmd and mb->args[0] through mb->args[2] */ 404 cx18_memcpy_fromio(cx, &order_mb->cmd, &mb->cmd, 4 * sizeof(u32)); 405 /* mb->request and mb->ack. N.B. we want to read mb->ack last */ 406 cx18_memcpy_fromio(cx, &order_mb->request, &mb->request, 407 2 * sizeof(u32)); 408 409 if (order_mb->request == order_mb->ack) { 410 CX18_WARN("Possibly falling behind: %s self-ack'ed our incoming" 411 " %s to EPU mailbox (sequence no. %u)\n", 412 rpu_str[rpu], rpu_str[rpu], order_mb->request); 413 dump_mb(cx, order_mb, "incoming"); 414 order->flags = CX18_F_EWO_MB_STALE_UPON_RECEIPT; 415 } 416 417 /* 418 * Individual EPU command processing is responsible for ack-ing 419 * a non-stale mailbox as soon as possible 420 */ 421 submit = epu_cmd_irq(cx, order); 422 if (submit > 0) { 423 queue_work(cx18_work_queue, &order->work); 424 } 425} 426 427 428/* 429 * Functions called from a non-interrupt, non work_queue context 430 */ 431 432static void cx18_api_log_ack_delay(struct cx18 *cx, int msecs) 433{ 434 if (msecs > CX18_MAX_MB_ACK_DELAY) 435 msecs = CX18_MAX_MB_ACK_DELAY; 436 atomic_inc(&cx->mbox_stats.mb_ack_delay[msecs]); 437} 438 439static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[]) 440{ 441 const struct cx18_api_info *info = find_api_info(cmd); 442 u32 state, irq, req, ack, err; 443 struct cx18_mailbox __iomem *mb; 444 u32 __iomem *xpu_state; 445 wait_queue_head_t *waitq; 446 struct mutex *mb_lock; 447 long int timeout, ret; 448 int i; 449 450 if (info == NULL) { 451 CX18_WARN("unknown cmd %x\n", cmd); 452 return -EINVAL; 453 } 454 455 if (cmd == CX18_CPU_DE_SET_MDL) 456 CX18_DEBUG_HI_API("%s\n", info->name); 457 else 458 CX18_DEBUG_API("%s\n", info->name); 459 460 switch (info->rpu) { 461 case APU: 462 waitq = &cx->mb_apu_waitq; 463 mb_lock = &cx->epu2apu_mb_lock; 464 irq = IRQ_EPU_TO_APU; 465 mb = &cx->scb->epu2apu_mb; 466 xpu_state = &cx->scb->apu_state; 467 break; 468 case CPU: 469 waitq = &cx->mb_cpu_waitq; 470 mb_lock = &cx->epu2cpu_mb_lock; 471 irq = IRQ_EPU_TO_CPU; 472 mb = &cx->scb->epu2cpu_mb; 473 xpu_state = &cx->scb->cpu_state; 474 break; 475 default: 476 CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu); 477 return -EINVAL; 478 } 479 480 mutex_lock(mb_lock); 481 /* 482 * Wait for an in-use mailbox to complete 483 * 484 * If the XPU is responding with Ack's, the mailbox shouldn't be in 485 * a busy state, since we serialize access to it on our end. 486 * 487 * If the wait for ack after sending a previous command was interrupted 488 * by a signal, we may get here and find a busy mailbox. After waiting, 489 * mark it "not busy" from our end, if the XPU hasn't ack'ed it still. 490 */ 491 state = cx18_readl(cx, xpu_state); 492 req = cx18_readl(cx, &mb->request); 493 timeout = msecs_to_jiffies(20); /* 1 field at 50 Hz vertical refresh */ 494 ret = wait_event_timeout(*waitq, 495 (ack = cx18_readl(cx, &mb->ack)) == req, 496 timeout); 497 if (req != ack) { 498 /* waited long enough, make the mbox "not busy" from our end */ 499 cx18_writel(cx, req, &mb->ack); 500 CX18_ERR("mbox was found stuck busy when setting up for %s; " 501 "clearing busy and trying to proceed\n", info->name); 502 } else if (ret != timeout) 503 CX18_DEBUG_API("waited %u usecs for busy mbox to be acked\n", 504 jiffies_to_usecs(timeout-ret)); 505 506 /* Build the outgoing mailbox */ 507 req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1; 508 509 cx18_writel(cx, cmd, &mb->cmd); 510 for (i = 0; i < args; i++) 511 cx18_writel(cx, data[i], &mb->args[i]); 512 cx18_writel(cx, 0, &mb->error); 513 cx18_writel(cx, req, &mb->request); 514 cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */ 515 516 /* 517 * Notify the XPU and wait for it to send an Ack back 518 * 21 ms = ~ 0.5 frames at a frame rate of 24 fps 519 * 42 ms = ~ 1 frame at a frame rate of 24 fps 520 */ 521 timeout = msecs_to_jiffies((info->flags & API_FAST) ? 21 : 42); 522 523 CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n", 524 irq, info->name); 525 cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq); 526 527 ret = wait_event_timeout( 528 *waitq, 529 cx18_readl(cx, &mb->ack) == cx18_readl(cx, &mb->request), 530 timeout); 531 if (ret == 0) { 532 /* Timed out */ 533 mutex_unlock(mb_lock); 534 i = jiffies_to_msecs(timeout); 535 cx18_api_log_ack_delay(cx, i); 536 CX18_WARN("sending %s timed out waiting %d msecs for RPU " 537 "acknowledgement\n", info->name, i); 538 return -EINVAL; 539 } else if (ret < 0) { 540 /* Interrupted */ 541 mutex_unlock(mb_lock); 542 CX18_WARN("sending %s was interrupted waiting for RPU" 543 "acknowledgement\n", info->name); 544 return -EINTR; 545 } 546 547 i = jiffies_to_msecs(timeout-ret); 548 cx18_api_log_ack_delay(cx, i); 549 if (ret != timeout) 550 CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n", 551 i, info->name); 552 553 /* Collect data returned by the XPU */ 554 for (i = 0; i < MAX_MB_ARGUMENTS; i++) 555 data[i] = cx18_readl(cx, &mb->args[i]); 556 err = cx18_readl(cx, &mb->error); 557 mutex_unlock(mb_lock); 558 559 /* 560 * Wait for XPU to perform extra actions for the caller in some cases. 561 * e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all buffers 562 * back in a burst shortly thereafter 563 */ 564 if (info->flags & API_SLOW) 565 cx18_msleep_timeout(300, 0); 566 567 if (err) 568 CX18_DEBUG_API("mailbox error %08x for command %s\n", err, 569 info->name); 570 return err ? -EIO : 0; 571} 572 573int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[]) 574{ 575 return cx18_api_call(cx, cmd, args, data); 576} 577 578static int cx18_set_filter_param(struct cx18_stream *s) 579{ 580 struct cx18 *cx = s->cx; 581 u32 mode; 582 int ret; 583 584 mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0); 585 ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4, 586 s->handle, 1, mode, cx->spatial_strength); 587 mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0); 588 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4, 589 s->handle, 0, mode, cx->temporal_strength); 590 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4, 591 s->handle, 2, cx->filter_mode >> 2, 0); 592 return ret; 593} 594 595int cx18_api_func(void *priv, u32 cmd, int in, int out, 596 u32 data[CX2341X_MBOX_MAX_DATA]) 597{ 598 struct cx18 *cx = priv; 599 struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_MPG]; 600 601 switch (cmd) { 602 case CX2341X_ENC_SET_OUTPUT_PORT: 603 return 0; 604 case CX2341X_ENC_SET_FRAME_RATE: 605 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6, 606 s->handle, 0, 0, 0, 0, data[0]); 607 case CX2341X_ENC_SET_FRAME_SIZE: 608 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3, 609 s->handle, data[1], data[0]); 610 case CX2341X_ENC_SET_STREAM_TYPE: 611 return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2, 612 s->handle, data[0]); 613 case CX2341X_ENC_SET_ASPECT_RATIO: 614 return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2, 615 s->handle, data[0]); 616 617 case CX2341X_ENC_SET_GOP_PROPERTIES: 618 return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3, 619 s->handle, data[0], data[1]); 620 case CX2341X_ENC_SET_GOP_CLOSURE: 621 return 0; 622 case CX2341X_ENC_SET_AUDIO_PROPERTIES: 623 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2, 624 s->handle, data[0]); 625 case CX2341X_ENC_MUTE_AUDIO: 626 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2, 627 s->handle, data[0]); 628 case CX2341X_ENC_SET_BIT_RATE: 629 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5, 630 s->handle, data[0], data[1], data[2], data[3]); 631 case CX2341X_ENC_MUTE_VIDEO: 632 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2, 633 s->handle, data[0]); 634 case CX2341X_ENC_SET_FRAME_DROP_RATE: 635 return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2, 636 s->handle, data[0]); 637 case CX2341X_ENC_MISC: 638 return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4, 639 s->handle, data[0], data[1], data[2]); 640 case CX2341X_ENC_SET_DNR_FILTER_MODE: 641 cx->filter_mode = (data[0] & 3) | (data[1] << 2); 642 return cx18_set_filter_param(s); 643 case CX2341X_ENC_SET_DNR_FILTER_PROPS: 644 cx->spatial_strength = data[0]; 645 cx->temporal_strength = data[1]; 646 return cx18_set_filter_param(s); 647 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE: 648 return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3, 649 s->handle, data[0], data[1]); 650 case CX2341X_ENC_SET_CORING_LEVELS: 651 return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5, 652 s->handle, data[0], data[1], data[2], data[3]); 653 } 654 CX18_WARN("Unknown cmd %x\n", cmd); 655 return 0; 656} 657 658int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS], 659 u32 cmd, int args, ...) 660{ 661 va_list ap; 662 int i; 663 664 va_start(ap, args); 665 for (i = 0; i < args; i++) 666 data[i] = va_arg(ap, u32); 667 va_end(ap); 668 return cx18_api(cx, cmd, args, data); 669} 670 671int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...) 672{ 673 u32 data[MAX_MB_ARGUMENTS]; 674 va_list ap; 675 int i; 676 677 if (cx == NULL) { 678 CX18_ERR("cx == NULL (cmd=%x)\n", cmd); 679 return 0; 680 } 681 if (args > MAX_MB_ARGUMENTS) { 682 CX18_ERR("args too big (cmd=%x)\n", cmd); 683 args = MAX_MB_ARGUMENTS; 684 } 685 va_start(ap, args); 686 for (i = 0; i < args; i++) 687 data[i] = va_arg(ap, u32); 688 va_end(ap); 689 return cx18_api(cx, cmd, args, data); 690} 691