cx23885-dvb.c revision b179bc4579f67c6f1df524c48b28cacf0c7a1b91
1/* 2 * Driver for the Conexant CX23885 PCIe bridge 3 * 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22#include <linux/module.h> 23#include <linux/init.h> 24#include <linux/device.h> 25#include <linux/fs.h> 26#include <linux/kthread.h> 27#include <linux/file.h> 28#include <linux/suspend.h> 29 30#include "cx23885.h" 31#include <media/v4l2-common.h> 32 33#include "dvb_ca_en50221.h" 34#include "s5h1409.h" 35#include "s5h1411.h" 36#include "mt2131.h" 37#include "tda8290.h" 38#include "tda18271.h" 39#include "lgdt330x.h" 40#include "xc5000.h" 41#include "tda10048.h" 42#include "tuner-xc2028.h" 43#include "tuner-simple.h" 44#include "dib7000p.h" 45#include "dibx000_common.h" 46#include "zl10353.h" 47#include "stv0900.h" 48#include "stv0900_reg.h" 49#include "stv6110.h" 50#include "lnbh24.h" 51#include "cx24116.h" 52#include "cimax2.h" 53#include "lgs8gxx.h" 54#include "netup-eeprom.h" 55#include "netup-init.h" 56#include "lgdt3305.h" 57 58static unsigned int debug; 59 60#define dprintk(level, fmt, arg...)\ 61 do { if (debug >= level)\ 62 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\ 63 } while (0) 64 65/* ------------------------------------------------------------------ */ 66 67static unsigned int alt_tuner; 68module_param(alt_tuner, int, 0644); 69MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration"); 70 71DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); 72 73/* ------------------------------------------------------------------ */ 74 75static int dvb_buf_setup(struct videobuf_queue *q, 76 unsigned int *count, unsigned int *size) 77{ 78 struct cx23885_tsport *port = q->priv_data; 79 80 port->ts_packet_size = 188 * 4; 81 port->ts_packet_count = 32; 82 83 *size = port->ts_packet_size * port->ts_packet_count; 84 *count = 32; 85 return 0; 86} 87 88static int dvb_buf_prepare(struct videobuf_queue *q, 89 struct videobuf_buffer *vb, enum v4l2_field field) 90{ 91 struct cx23885_tsport *port = q->priv_data; 92 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field); 93} 94 95static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb) 96{ 97 struct cx23885_tsport *port = q->priv_data; 98 cx23885_buf_queue(port, (struct cx23885_buffer *)vb); 99} 100 101static void dvb_buf_release(struct videobuf_queue *q, 102 struct videobuf_buffer *vb) 103{ 104 cx23885_free_buffer(q, (struct cx23885_buffer *)vb); 105} 106 107static struct videobuf_queue_ops dvb_qops = { 108 .buf_setup = dvb_buf_setup, 109 .buf_prepare = dvb_buf_prepare, 110 .buf_queue = dvb_buf_queue, 111 .buf_release = dvb_buf_release, 112}; 113 114static struct s5h1409_config hauppauge_generic_config = { 115 .demod_address = 0x32 >> 1, 116 .output_mode = S5H1409_SERIAL_OUTPUT, 117 .gpio = S5H1409_GPIO_ON, 118 .qam_if = 44000, 119 .inversion = S5H1409_INVERSION_OFF, 120 .status_mode = S5H1409_DEMODLOCKING, 121 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 122}; 123 124static struct tda10048_config hauppauge_hvr1200_config = { 125 .demod_address = 0x10 >> 1, 126 .output_mode = TDA10048_SERIAL_OUTPUT, 127 .fwbulkwritelen = TDA10048_BULKWRITE_200, 128 .inversion = TDA10048_INVERSION_ON, 129 .dtv6_if_freq_khz = TDA10048_IF_3300, 130 .dtv7_if_freq_khz = TDA10048_IF_3800, 131 .dtv8_if_freq_khz = TDA10048_IF_4300, 132 .clk_freq_khz = TDA10048_CLK_16000, 133}; 134 135static struct tda10048_config hauppauge_hvr1210_config = { 136 .demod_address = 0x10 >> 1, 137 .output_mode = TDA10048_SERIAL_OUTPUT, 138 .fwbulkwritelen = TDA10048_BULKWRITE_200, 139 .inversion = TDA10048_INVERSION_ON, 140 .dtv6_if_freq_khz = TDA10048_IF_3300, 141 .dtv7_if_freq_khz = TDA10048_IF_3500, 142 .dtv8_if_freq_khz = TDA10048_IF_4000, 143 .clk_freq_khz = TDA10048_CLK_16000, 144}; 145 146static struct s5h1409_config hauppauge_ezqam_config = { 147 .demod_address = 0x32 >> 1, 148 .output_mode = S5H1409_SERIAL_OUTPUT, 149 .gpio = S5H1409_GPIO_OFF, 150 .qam_if = 4000, 151 .inversion = S5H1409_INVERSION_ON, 152 .status_mode = S5H1409_DEMODLOCKING, 153 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 154}; 155 156static struct s5h1409_config hauppauge_hvr1800lp_config = { 157 .demod_address = 0x32 >> 1, 158 .output_mode = S5H1409_SERIAL_OUTPUT, 159 .gpio = S5H1409_GPIO_OFF, 160 .qam_if = 44000, 161 .inversion = S5H1409_INVERSION_OFF, 162 .status_mode = S5H1409_DEMODLOCKING, 163 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 164}; 165 166static struct s5h1409_config hauppauge_hvr1500_config = { 167 .demod_address = 0x32 >> 1, 168 .output_mode = S5H1409_SERIAL_OUTPUT, 169 .gpio = S5H1409_GPIO_OFF, 170 .inversion = S5H1409_INVERSION_OFF, 171 .status_mode = S5H1409_DEMODLOCKING, 172 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 173}; 174 175static struct mt2131_config hauppauge_generic_tunerconfig = { 176 0x61 177}; 178 179static struct lgdt330x_config fusionhdtv_5_express = { 180 .demod_address = 0x0e, 181 .demod_chip = LGDT3303, 182 .serial_mpeg = 0x40, 183}; 184 185static struct s5h1409_config hauppauge_hvr1500q_config = { 186 .demod_address = 0x32 >> 1, 187 .output_mode = S5H1409_SERIAL_OUTPUT, 188 .gpio = S5H1409_GPIO_ON, 189 .qam_if = 44000, 190 .inversion = S5H1409_INVERSION_OFF, 191 .status_mode = S5H1409_DEMODLOCKING, 192 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 193}; 194 195static struct s5h1409_config dvico_s5h1409_config = { 196 .demod_address = 0x32 >> 1, 197 .output_mode = S5H1409_SERIAL_OUTPUT, 198 .gpio = S5H1409_GPIO_ON, 199 .qam_if = 44000, 200 .inversion = S5H1409_INVERSION_OFF, 201 .status_mode = S5H1409_DEMODLOCKING, 202 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 203}; 204 205static struct s5h1411_config dvico_s5h1411_config = { 206 .output_mode = S5H1411_SERIAL_OUTPUT, 207 .gpio = S5H1411_GPIO_ON, 208 .qam_if = S5H1411_IF_44000, 209 .vsb_if = S5H1411_IF_44000, 210 .inversion = S5H1411_INVERSION_OFF, 211 .status_mode = S5H1411_DEMODLOCKING, 212 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 213}; 214 215static struct s5h1411_config hcw_s5h1411_config = { 216 .output_mode = S5H1411_SERIAL_OUTPUT, 217 .gpio = S5H1411_GPIO_OFF, 218 .vsb_if = S5H1411_IF_44000, 219 .qam_if = S5H1411_IF_4000, 220 .inversion = S5H1411_INVERSION_ON, 221 .status_mode = S5H1411_DEMODLOCKING, 222 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 223}; 224 225static struct xc5000_config hauppauge_hvr1500q_tunerconfig = { 226 .i2c_address = 0x61, 227 .if_khz = 5380, 228}; 229 230static struct xc5000_config dvico_xc5000_tunerconfig = { 231 .i2c_address = 0x64, 232 .if_khz = 5380, 233}; 234 235static struct tda829x_config tda829x_no_probe = { 236 .probe_tuner = TDA829X_DONT_PROBE, 237}; 238 239static struct tda18271_std_map hauppauge_tda18271_std_map = { 240 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3, 241 .if_lvl = 6, .rfagc_top = 0x37 }, 242 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0, 243 .if_lvl = 6, .rfagc_top = 0x37 }, 244}; 245 246static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = { 247 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4, 248 .if_lvl = 1, .rfagc_top = 0x37, }, 249 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5, 250 .if_lvl = 1, .rfagc_top = 0x37, }, 251 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6, 252 .if_lvl = 1, .rfagc_top = 0x37, }, 253}; 254 255static struct tda18271_config hauppauge_tda18271_config = { 256 .std_map = &hauppauge_tda18271_std_map, 257 .gate = TDA18271_GATE_ANALOG, 258}; 259 260static struct tda18271_config hauppauge_hvr1200_tuner_config = { 261 .std_map = &hauppauge_hvr1200_tda18271_std_map, 262 .gate = TDA18271_GATE_ANALOG, 263}; 264 265static struct tda18271_config hauppauge_hvr1210_tuner_config = { 266 .gate = TDA18271_GATE_DIGITAL, 267}; 268 269static struct tda18271_std_map hauppauge_hvr127x_std_map = { 270 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4, 271 .if_lvl = 1, .rfagc_top = 0x58 }, 272 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5, 273 .if_lvl = 1, .rfagc_top = 0x58 }, 274}; 275 276static struct tda18271_config hauppauge_hvr127x_config = { 277 .std_map = &hauppauge_hvr127x_std_map, 278}; 279 280static struct lgdt3305_config hauppauge_lgdt3305_config = { 281 .i2c_addr = 0x0e, 282 .mpeg_mode = LGDT3305_MPEG_SERIAL, 283 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE, 284 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH, 285 .deny_i2c_rptr = 1, 286 .spectral_inversion = 1, 287 .qam_if_khz = 4000, 288 .vsb_if_khz = 3250, 289}; 290 291static struct dibx000_agc_config xc3028_agc_config = { 292 BAND_VHF | BAND_UHF, /* band_caps */ 293 294 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0, 295 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, 296 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, 297 * P_agc_nb_est=2, P_agc_write=0 298 */ 299 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | 300 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */ 301 302 712, /* inv_gain */ 303 21, /* time_stabiliz */ 304 305 0, /* alpha_level */ 306 118, /* thlock */ 307 308 0, /* wbd_inv */ 309 2867, /* wbd_ref */ 310 0, /* wbd_sel */ 311 2, /* wbd_alpha */ 312 313 0, /* agc1_max */ 314 0, /* agc1_min */ 315 39718, /* agc2_max */ 316 9930, /* agc2_min */ 317 0, /* agc1_pt1 */ 318 0, /* agc1_pt2 */ 319 0, /* agc1_pt3 */ 320 0, /* agc1_slope1 */ 321 0, /* agc1_slope2 */ 322 0, /* agc2_pt1 */ 323 128, /* agc2_pt2 */ 324 29, /* agc2_slope1 */ 325 29, /* agc2_slope2 */ 326 327 17, /* alpha_mant */ 328 27, /* alpha_exp */ 329 23, /* beta_mant */ 330 51, /* beta_exp */ 331 332 1, /* perform_agc_softsplit */ 333}; 334 335/* PLL Configuration for COFDM BW_MHz = 8.000000 336 * With external clock = 30.000000 */ 337static struct dibx000_bandwidth_config xc3028_bw_config = { 338 60000, /* internal */ 339 30000, /* sampling */ 340 1, /* pll_cfg: prediv */ 341 8, /* pll_cfg: ratio */ 342 3, /* pll_cfg: range */ 343 1, /* pll_cfg: reset */ 344 0, /* pll_cfg: bypass */ 345 0, /* misc: refdiv */ 346 0, /* misc: bypclk_div */ 347 1, /* misc: IO_CLK_en_core */ 348 1, /* misc: ADClkSrc */ 349 0, /* misc: modulo */ 350 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */ 351 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */ 352 20452225, /* timf */ 353 30000000 /* xtal_hz */ 354}; 355 356static struct dib7000p_config hauppauge_hvr1400_dib7000_config = { 357 .output_mpeg2_in_188_bytes = 1, 358 .hostbus_diversity = 1, 359 .tuner_is_baseband = 0, 360 .update_lna = NULL, 361 362 .agc_config_count = 1, 363 .agc = &xc3028_agc_config, 364 .bw = &xc3028_bw_config, 365 366 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS, 367 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES, 368 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS, 369 370 .pwm_freq_div = 0, 371 .agc_control = NULL, 372 .spur_protect = 0, 373 374 .output_mode = OUTMODE_MPEG2_SERIAL, 375}; 376 377static struct zl10353_config dvico_fusionhdtv_xc3028 = { 378 .demod_address = 0x0f, 379 .if2 = 45600, 380 .no_tuner = 1, 381 .disable_i2c_gate_ctrl = 1, 382}; 383 384static struct stv0900_reg stv0900_ts_regs[] = { 385 { R0900_TSGENERAL, 0x00 }, 386 { R0900_P1_TSSPEED, 0x40 }, 387 { R0900_P2_TSSPEED, 0x40 }, 388 { R0900_P1_TSCFGM, 0xc0 }, 389 { R0900_P2_TSCFGM, 0xc0 }, 390 { R0900_P1_TSCFGH, 0xe0 }, 391 { R0900_P2_TSCFGH, 0xe0 }, 392 { R0900_P1_TSCFGL, 0x20 }, 393 { R0900_P2_TSCFGL, 0x20 }, 394 { 0xffff, 0xff }, /* terminate */ 395}; 396 397static struct stv0900_config netup_stv0900_config = { 398 .demod_address = 0x68, 399 .xtal = 27000000, 400 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */ 401 .diseqc_mode = 2,/* 2/3 PWM */ 402 .ts_config_regs = stv0900_ts_regs, 403 .tun1_maddress = 0,/* 0x60 */ 404 .tun2_maddress = 3,/* 0x63 */ 405 .tun1_adc = 1,/* 1 Vpp */ 406 .tun2_adc = 1,/* 1 Vpp */ 407}; 408 409static struct stv6110_config netup_stv6110_tunerconfig_a = { 410 .i2c_address = 0x60, 411 .mclk = 27000000, 412 .iq_wiring = 0, 413}; 414 415static struct stv6110_config netup_stv6110_tunerconfig_b = { 416 .i2c_address = 0x63, 417 .mclk = 27000000, 418 .iq_wiring = 1, 419}; 420 421static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) 422{ 423 struct cx23885_tsport *port = fe->dvb->priv; 424 struct cx23885_dev *dev = port->dev; 425 426 if (voltage == SEC_VOLTAGE_18) 427 cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */ 428 else if (voltage == SEC_VOLTAGE_13) 429 cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */ 430 else 431 cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */ 432 return 0; 433} 434 435static struct cx24116_config tbs_cx24116_config = { 436 .demod_address = 0x05, 437}; 438 439static struct cx24116_config tevii_cx24116_config = { 440 .demod_address = 0x55, 441}; 442 443static struct cx24116_config dvbworld_cx24116_config = { 444 .demod_address = 0x05, 445}; 446 447static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = { 448 .prod = LGS8GXX_PROD_LGS8GL5, 449 .demod_address = 0x19, 450 .serial_ts = 0, 451 .ts_clk_pol = 1, 452 .ts_clk_gated = 1, 453 .if_clk_freq = 30400, /* 30.4 MHz */ 454 .if_freq = 5380, /* 5.38 MHz */ 455 .if_neg_center = 1, 456 .ext_adc = 0, 457 .adc_signed = 0, 458 .if_neg_edge = 0, 459}; 460 461static struct xc5000_config mygica_x8506_xc5000_config = { 462 .i2c_address = 0x61, 463 .if_khz = 5380, 464}; 465 466static int cx23885_dvb_set_frontend(struct dvb_frontend *fe, 467 struct dvb_frontend_parameters *param) 468{ 469 struct cx23885_tsport *port = fe->dvb->priv; 470 struct cx23885_dev *dev = port->dev; 471 472 switch (dev->board) { 473 case CX23885_BOARD_HAUPPAUGE_HVR1275: 474 switch (param->u.vsb.modulation) { 475 case VSB_8: 476 cx23885_gpio_clear(dev, GPIO_5); 477 break; 478 case QAM_64: 479 case QAM_256: 480 default: 481 cx23885_gpio_set(dev, GPIO_5); 482 break; 483 } 484 break; 485 } 486 return (port->set_frontend_save) ? 487 port->set_frontend_save(fe, param) : -ENODEV; 488} 489 490static int dvb_register(struct cx23885_tsport *port) 491{ 492 struct cx23885_dev *dev = port->dev; 493 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL; 494 struct videobuf_dvb_frontend *fe0; 495 int ret; 496 497 /* Get the first frontend */ 498 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1); 499 if (!fe0) 500 return -EINVAL; 501 502 /* init struct videobuf_dvb */ 503 fe0->dvb.name = dev->name; 504 505 /* init frontend */ 506 switch (dev->board) { 507 case CX23885_BOARD_HAUPPAUGE_HVR1250: 508 i2c_bus = &dev->i2c_bus[0]; 509 fe0->dvb.frontend = dvb_attach(s5h1409_attach, 510 &hauppauge_generic_config, 511 &i2c_bus->i2c_adap); 512 if (fe0->dvb.frontend != NULL) { 513 dvb_attach(mt2131_attach, fe0->dvb.frontend, 514 &i2c_bus->i2c_adap, 515 &hauppauge_generic_tunerconfig, 0); 516 } 517 break; 518 case CX23885_BOARD_HAUPPAUGE_HVR1270: 519 case CX23885_BOARD_HAUPPAUGE_HVR1275: 520 i2c_bus = &dev->i2c_bus[0]; 521 fe0->dvb.frontend = dvb_attach(lgdt3305_attach, 522 &hauppauge_lgdt3305_config, 523 &i2c_bus->i2c_adap); 524 if (fe0->dvb.frontend != NULL) { 525 dvb_attach(tda18271_attach, fe0->dvb.frontend, 526 0x60, &dev->i2c_bus[1].i2c_adap, 527 &hauppauge_hvr127x_config); 528 } 529 530 /* FIXME: temporary hack */ 531 /* define bridge override to set_frontend */ 532 port->set_frontend_save = fe0->dvb.frontend->ops.set_frontend; 533 fe0->dvb.frontend->ops.set_frontend = cx23885_dvb_set_frontend; 534 535 break; 536 case CX23885_BOARD_HAUPPAUGE_HVR1255: 537 i2c_bus = &dev->i2c_bus[0]; 538 fe0->dvb.frontend = dvb_attach(s5h1411_attach, 539 &hcw_s5h1411_config, 540 &i2c_bus->i2c_adap); 541 if (fe0->dvb.frontend != NULL) { 542 dvb_attach(tda18271_attach, fe0->dvb.frontend, 543 0x60, &dev->i2c_bus[1].i2c_adap, 544 &hauppauge_tda18271_config); 545 } 546 break; 547 case CX23885_BOARD_HAUPPAUGE_HVR1800: 548 i2c_bus = &dev->i2c_bus[0]; 549 switch (alt_tuner) { 550 case 1: 551 fe0->dvb.frontend = 552 dvb_attach(s5h1409_attach, 553 &hauppauge_ezqam_config, 554 &i2c_bus->i2c_adap); 555 if (fe0->dvb.frontend != NULL) { 556 dvb_attach(tda829x_attach, fe0->dvb.frontend, 557 &dev->i2c_bus[1].i2c_adap, 0x42, 558 &tda829x_no_probe); 559 dvb_attach(tda18271_attach, fe0->dvb.frontend, 560 0x60, &dev->i2c_bus[1].i2c_adap, 561 &hauppauge_tda18271_config); 562 } 563 break; 564 case 0: 565 default: 566 fe0->dvb.frontend = 567 dvb_attach(s5h1409_attach, 568 &hauppauge_generic_config, 569 &i2c_bus->i2c_adap); 570 if (fe0->dvb.frontend != NULL) 571 dvb_attach(mt2131_attach, fe0->dvb.frontend, 572 &i2c_bus->i2c_adap, 573 &hauppauge_generic_tunerconfig, 0); 574 break; 575 } 576 break; 577 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 578 i2c_bus = &dev->i2c_bus[0]; 579 fe0->dvb.frontend = dvb_attach(s5h1409_attach, 580 &hauppauge_hvr1800lp_config, 581 &i2c_bus->i2c_adap); 582 if (fe0->dvb.frontend != NULL) { 583 dvb_attach(mt2131_attach, fe0->dvb.frontend, 584 &i2c_bus->i2c_adap, 585 &hauppauge_generic_tunerconfig, 0); 586 } 587 break; 588 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP: 589 i2c_bus = &dev->i2c_bus[0]; 590 fe0->dvb.frontend = dvb_attach(lgdt330x_attach, 591 &fusionhdtv_5_express, 592 &i2c_bus->i2c_adap); 593 if (fe0->dvb.frontend != NULL) { 594 dvb_attach(simple_tuner_attach, fe0->dvb.frontend, 595 &i2c_bus->i2c_adap, 0x61, 596 TUNER_LG_TDVS_H06XF); 597 } 598 break; 599 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 600 i2c_bus = &dev->i2c_bus[1]; 601 fe0->dvb.frontend = dvb_attach(s5h1409_attach, 602 &hauppauge_hvr1500q_config, 603 &dev->i2c_bus[0].i2c_adap); 604 if (fe0->dvb.frontend != NULL) 605 dvb_attach(xc5000_attach, fe0->dvb.frontend, 606 &i2c_bus->i2c_adap, 607 &hauppauge_hvr1500q_tunerconfig); 608 break; 609 case CX23885_BOARD_HAUPPAUGE_HVR1500: 610 i2c_bus = &dev->i2c_bus[1]; 611 fe0->dvb.frontend = dvb_attach(s5h1409_attach, 612 &hauppauge_hvr1500_config, 613 &dev->i2c_bus[0].i2c_adap); 614 if (fe0->dvb.frontend != NULL) { 615 struct dvb_frontend *fe; 616 struct xc2028_config cfg = { 617 .i2c_adap = &i2c_bus->i2c_adap, 618 .i2c_addr = 0x61, 619 }; 620 static struct xc2028_ctrl ctl = { 621 .fname = XC2028_DEFAULT_FIRMWARE, 622 .max_len = 64, 623 .demod = XC3028_FE_OREN538, 624 }; 625 626 fe = dvb_attach(xc2028_attach, 627 fe0->dvb.frontend, &cfg); 628 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) 629 fe->ops.tuner_ops.set_config(fe, &ctl); 630 } 631 break; 632 case CX23885_BOARD_HAUPPAUGE_HVR1200: 633 case CX23885_BOARD_HAUPPAUGE_HVR1700: 634 i2c_bus = &dev->i2c_bus[0]; 635 fe0->dvb.frontend = dvb_attach(tda10048_attach, 636 &hauppauge_hvr1200_config, 637 &i2c_bus->i2c_adap); 638 if (fe0->dvb.frontend != NULL) { 639 dvb_attach(tda829x_attach, fe0->dvb.frontend, 640 &dev->i2c_bus[1].i2c_adap, 0x42, 641 &tda829x_no_probe); 642 dvb_attach(tda18271_attach, fe0->dvb.frontend, 643 0x60, &dev->i2c_bus[1].i2c_adap, 644 &hauppauge_hvr1200_tuner_config); 645 } 646 break; 647 case CX23885_BOARD_HAUPPAUGE_HVR1210: 648 i2c_bus = &dev->i2c_bus[0]; 649 fe0->dvb.frontend = dvb_attach(tda10048_attach, 650 &hauppauge_hvr1210_config, 651 &i2c_bus->i2c_adap); 652 if (fe0->dvb.frontend != NULL) { 653 dvb_attach(tda18271_attach, fe0->dvb.frontend, 654 0x60, &dev->i2c_bus[1].i2c_adap, 655 &hauppauge_hvr1210_tuner_config); 656 } 657 break; 658 case CX23885_BOARD_HAUPPAUGE_HVR1400: 659 i2c_bus = &dev->i2c_bus[0]; 660 fe0->dvb.frontend = dvb_attach(dib7000p_attach, 661 &i2c_bus->i2c_adap, 662 0x12, &hauppauge_hvr1400_dib7000_config); 663 if (fe0->dvb.frontend != NULL) { 664 struct dvb_frontend *fe; 665 struct xc2028_config cfg = { 666 .i2c_adap = &dev->i2c_bus[1].i2c_adap, 667 .i2c_addr = 0x64, 668 }; 669 static struct xc2028_ctrl ctl = { 670 .fname = XC3028L_DEFAULT_FIRMWARE, 671 .max_len = 64, 672 .demod = 5000, 673 /* This is true for all demods with 674 v36 firmware? */ 675 .type = XC2028_D2633, 676 }; 677 678 fe = dvb_attach(xc2028_attach, 679 fe0->dvb.frontend, &cfg); 680 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) 681 fe->ops.tuner_ops.set_config(fe, &ctl); 682 } 683 break; 684 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 685 i2c_bus = &dev->i2c_bus[port->nr - 1]; 686 687 fe0->dvb.frontend = dvb_attach(s5h1409_attach, 688 &dvico_s5h1409_config, 689 &i2c_bus->i2c_adap); 690 if (fe0->dvb.frontend == NULL) 691 fe0->dvb.frontend = dvb_attach(s5h1411_attach, 692 &dvico_s5h1411_config, 693 &i2c_bus->i2c_adap); 694 if (fe0->dvb.frontend != NULL) 695 dvb_attach(xc5000_attach, fe0->dvb.frontend, 696 &i2c_bus->i2c_adap, 697 &dvico_xc5000_tunerconfig); 698 break; 699 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: { 700 i2c_bus = &dev->i2c_bus[port->nr - 1]; 701 702 fe0->dvb.frontend = dvb_attach(zl10353_attach, 703 &dvico_fusionhdtv_xc3028, 704 &i2c_bus->i2c_adap); 705 if (fe0->dvb.frontend != NULL) { 706 struct dvb_frontend *fe; 707 struct xc2028_config cfg = { 708 .i2c_adap = &i2c_bus->i2c_adap, 709 .i2c_addr = 0x61, 710 }; 711 static struct xc2028_ctrl ctl = { 712 .fname = XC2028_DEFAULT_FIRMWARE, 713 .max_len = 64, 714 .demod = XC3028_FE_ZARLINK456, 715 }; 716 717 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, 718 &cfg); 719 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) 720 fe->ops.tuner_ops.set_config(fe, &ctl); 721 } 722 break; 723 } 724 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 725 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 726 i2c_bus = &dev->i2c_bus[0]; 727 728 fe0->dvb.frontend = dvb_attach(zl10353_attach, 729 &dvico_fusionhdtv_xc3028, 730 &i2c_bus->i2c_adap); 731 if (fe0->dvb.frontend != NULL) { 732 struct dvb_frontend *fe; 733 struct xc2028_config cfg = { 734 .i2c_adap = &dev->i2c_bus[1].i2c_adap, 735 .i2c_addr = 0x61, 736 }; 737 static struct xc2028_ctrl ctl = { 738 .fname = XC2028_DEFAULT_FIRMWARE, 739 .max_len = 64, 740 .demod = XC3028_FE_ZARLINK456, 741 }; 742 743 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, 744 &cfg); 745 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) 746 fe->ops.tuner_ops.set_config(fe, &ctl); 747 } 748 break; 749 case CX23885_BOARD_TBS_6920: 750 i2c_bus = &dev->i2c_bus[0]; 751 752 fe0->dvb.frontend = dvb_attach(cx24116_attach, 753 &tbs_cx24116_config, 754 &i2c_bus->i2c_adap); 755 if (fe0->dvb.frontend != NULL) 756 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage; 757 758 break; 759 case CX23885_BOARD_TEVII_S470: 760 i2c_bus = &dev->i2c_bus[1]; 761 762 fe0->dvb.frontend = dvb_attach(cx24116_attach, 763 &tevii_cx24116_config, 764 &i2c_bus->i2c_adap); 765 if (fe0->dvb.frontend != NULL) 766 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage; 767 768 break; 769 case CX23885_BOARD_DVBWORLD_2005: 770 i2c_bus = &dev->i2c_bus[1]; 771 772 fe0->dvb.frontend = dvb_attach(cx24116_attach, 773 &dvbworld_cx24116_config, 774 &i2c_bus->i2c_adap); 775 break; 776 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 777 i2c_bus = &dev->i2c_bus[0]; 778 switch (port->nr) { 779 /* port B */ 780 case 1: 781 fe0->dvb.frontend = dvb_attach(stv0900_attach, 782 &netup_stv0900_config, 783 &i2c_bus->i2c_adap, 0); 784 if (fe0->dvb.frontend != NULL) { 785 if (dvb_attach(stv6110_attach, 786 fe0->dvb.frontend, 787 &netup_stv6110_tunerconfig_a, 788 &i2c_bus->i2c_adap)) { 789 if (!dvb_attach(lnbh24_attach, 790 fe0->dvb.frontend, 791 &i2c_bus->i2c_adap, 792 LNBH24_PCL, 793 LNBH24_TTX, 0x09)) 794 printk(KERN_ERR 795 "No LNBH24 found!\n"); 796 797 } 798 } 799 break; 800 /* port C */ 801 case 2: 802 fe0->dvb.frontend = dvb_attach(stv0900_attach, 803 &netup_stv0900_config, 804 &i2c_bus->i2c_adap, 1); 805 if (fe0->dvb.frontend != NULL) { 806 if (dvb_attach(stv6110_attach, 807 fe0->dvb.frontend, 808 &netup_stv6110_tunerconfig_b, 809 &i2c_bus->i2c_adap)) { 810 if (!dvb_attach(lnbh24_attach, 811 fe0->dvb.frontend, 812 &i2c_bus->i2c_adap, 813 LNBH24_PCL, 814 LNBH24_TTX, 0x0a)) 815 printk(KERN_ERR 816 "No LNBH24 found!\n"); 817 818 } 819 } 820 break; 821 } 822 break; 823 case CX23885_BOARD_MYGICA_X8506: 824 i2c_bus = &dev->i2c_bus[0]; 825 i2c_bus2 = &dev->i2c_bus[1]; 826 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach, 827 &mygica_x8506_lgs8gl5_config, 828 &i2c_bus->i2c_adap); 829 if (fe0->dvb.frontend != NULL) { 830 dvb_attach(xc5000_attach, 831 fe0->dvb.frontend, 832 &i2c_bus2->i2c_adap, 833 &mygica_x8506_xc5000_config); 834 } 835 break; 836 default: 837 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card " 838 " isn't supported yet\n", 839 dev->name); 840 break; 841 } 842 if (NULL == fe0->dvb.frontend) { 843 printk(KERN_ERR "%s: frontend initialization failed\n", 844 dev->name); 845 return -1; 846 } 847 /* define general-purpose callback pointer */ 848 fe0->dvb.frontend->callback = cx23885_tuner_callback; 849 850 /* Put the analog decoder in standby to keep it quiet */ 851 call_all(dev, tuner, s_standby); 852 853 if (fe0->dvb.frontend->ops.analog_ops.standby) 854 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend); 855 856 /* register everything */ 857 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port, 858 &dev->pci->dev, adapter_nr, 0); 859 860 /* init CI & MAC */ 861 switch (dev->board) { 862 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: { 863 static struct netup_card_info cinfo; 864 865 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo); 866 memcpy(port->frontends.adapter.proposed_mac, 867 cinfo.port[port->nr - 1].mac, 6); 868 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=" 869 "%02X:%02X:%02X:%02X:%02X:%02X\n", 870 port->nr, 871 port->frontends.adapter.proposed_mac[0], 872 port->frontends.adapter.proposed_mac[1], 873 port->frontends.adapter.proposed_mac[2], 874 port->frontends.adapter.proposed_mac[3], 875 port->frontends.adapter.proposed_mac[4], 876 port->frontends.adapter.proposed_mac[5]); 877 878 netup_ci_init(port); 879 break; 880 } 881 } 882 883 return ret; 884} 885 886int cx23885_dvb_register(struct cx23885_tsport *port) 887{ 888 889 struct videobuf_dvb_frontend *fe0; 890 struct cx23885_dev *dev = port->dev; 891 int err, i; 892 893 /* Here we need to allocate the correct number of frontends, 894 * as reflected in the cards struct. The reality is that currrently 895 * no cx23885 boards support this - yet. But, if we don't modify this 896 * code then the second frontend would never be allocated (later) 897 * and fail with error before the attach in dvb_register(). 898 * Without these changes we risk an OOPS later. The changes here 899 * are for safety, and should provide a good foundation for the 900 * future addition of any multi-frontend cx23885 based boards. 901 */ 902 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__, 903 port->num_frontends); 904 905 for (i = 1; i <= port->num_frontends; i++) { 906 if (videobuf_dvb_alloc_frontend( 907 &port->frontends, i) == NULL) { 908 printk(KERN_ERR "%s() failed to alloc\n", __func__); 909 return -ENOMEM; 910 } 911 912 fe0 = videobuf_dvb_get_frontend(&port->frontends, i); 913 if (!fe0) 914 err = -EINVAL; 915 916 dprintk(1, "%s\n", __func__); 917 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n", 918 dev->board, 919 dev->name, 920 dev->pci_bus, 921 dev->pci_slot); 922 923 err = -ENODEV; 924 925 /* dvb stuff */ 926 /* We have to init the queue for each frontend on a port. */ 927 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name); 928 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops, 929 &dev->pci->dev, &port->slock, 930 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP, 931 sizeof(struct cx23885_buffer), port); 932 } 933 err = dvb_register(port); 934 if (err != 0) 935 printk(KERN_ERR "%s() dvb_register failed err = %d\n", 936 __func__, err); 937 938 return err; 939} 940 941int cx23885_dvb_unregister(struct cx23885_tsport *port) 942{ 943 struct videobuf_dvb_frontend *fe0; 944 945 /* FIXME: in an error condition where the we have 946 * an expected number of frontends (attach problem) 947 * then this might not clean up correctly, if 1 948 * is invalid. 949 * This comment only applies to future boards IF they 950 * implement MFE support. 951 */ 952 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1); 953 if (fe0->dvb.frontend) 954 videobuf_dvb_unregister_bus(&port->frontends); 955 956 switch (port->dev->board) { 957 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 958 netup_ci_exit(port); 959 break; 960 } 961 962 return 0; 963} 964 965