mx2_camera.c revision 64dc3c1a906467d90c24913b0b38dd13d9378f4f
1/* 2 * V4L2 Driver for i.MX27/i.MX25 camera host 3 * 4 * Copyright (C) 2008, Sascha Hauer, Pengutronix 5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/init.h> 14#include <linux/module.h> 15#include <linux/io.h> 16#include <linux/delay.h> 17#include <linux/slab.h> 18#include <linux/dma-mapping.h> 19#include <linux/errno.h> 20#include <linux/fs.h> 21#include <linux/interrupt.h> 22#include <linux/kernel.h> 23#include <linux/mm.h> 24#include <linux/moduleparam.h> 25#include <linux/time.h> 26#include <linux/device.h> 27#include <linux/platform_device.h> 28#include <linux/mutex.h> 29#include <linux/clk.h> 30 31#include <media/v4l2-common.h> 32#include <media/v4l2-dev.h> 33#include <media/videobuf-core.h> 34#include <media/videobuf-dma-contig.h> 35#include <media/soc_camera.h> 36#include <media/soc_mediabus.h> 37 38#include <linux/videodev2.h> 39 40#include <mach/mx2_cam.h> 41#ifdef CONFIG_MACH_MX27 42#include <mach/dma-mx1-mx2.h> 43#endif 44#include <mach/hardware.h> 45 46#include <asm/dma.h> 47 48#define MX2_CAM_DRV_NAME "mx2-camera" 49#define MX2_CAM_VERSION "0.0.6" 50#define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera" 51 52/* reset values */ 53#define CSICR1_RESET_VAL 0x40000800 54#define CSICR2_RESET_VAL 0x0 55#define CSICR3_RESET_VAL 0x0 56 57/* csi control reg 1 */ 58#define CSICR1_SWAP16_EN (1 << 31) 59#define CSICR1_EXT_VSYNC (1 << 30) 60#define CSICR1_EOF_INTEN (1 << 29) 61#define CSICR1_PRP_IF_EN (1 << 28) 62#define CSICR1_CCIR_MODE (1 << 27) 63#define CSICR1_COF_INTEN (1 << 26) 64#define CSICR1_SF_OR_INTEN (1 << 25) 65#define CSICR1_RF_OR_INTEN (1 << 24) 66#define CSICR1_STATFF_LEVEL (3 << 22) 67#define CSICR1_STATFF_INTEN (1 << 21) 68#define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */ 69#define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */ 70#define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */ 71#define CSICR1_RXFF_INTEN (1 << 18) 72#define CSICR1_SOF_POL (1 << 17) 73#define CSICR1_SOF_INTEN (1 << 16) 74#define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12) 75#define CSICR1_HSYNC_POL (1 << 11) 76#define CSICR1_CCIR_EN (1 << 10) 77#define CSICR1_MCLKEN (1 << 9) 78#define CSICR1_FCC (1 << 8) 79#define CSICR1_PACK_DIR (1 << 7) 80#define CSICR1_CLR_STATFIFO (1 << 6) 81#define CSICR1_CLR_RXFIFO (1 << 5) 82#define CSICR1_GCLK_MODE (1 << 4) 83#define CSICR1_INV_DATA (1 << 3) 84#define CSICR1_INV_PCLK (1 << 2) 85#define CSICR1_REDGE (1 << 1) 86 87#define SHIFT_STATFF_LEVEL 22 88#define SHIFT_RXFF_LEVEL 19 89#define SHIFT_MCLKDIV 12 90 91/* control reg 3 */ 92#define CSICR3_FRMCNT (0xFFFF << 16) 93#define CSICR3_FRMCNT_RST (1 << 15) 94#define CSICR3_DMA_REFLASH_RFF (1 << 14) 95#define CSICR3_DMA_REFLASH_SFF (1 << 13) 96#define CSICR3_DMA_REQ_EN_RFF (1 << 12) 97#define CSICR3_DMA_REQ_EN_SFF (1 << 11) 98#define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */ 99#define CSICR3_CSI_SUP (1 << 3) 100#define CSICR3_ZERO_PACK_EN (1 << 2) 101#define CSICR3_ECC_INT_EN (1 << 1) 102#define CSICR3_ECC_AUTO_EN (1 << 0) 103 104#define SHIFT_FRMCNT 16 105 106/* csi status reg */ 107#define CSISR_SFF_OR_INT (1 << 25) 108#define CSISR_RFF_OR_INT (1 << 24) 109#define CSISR_STATFF_INT (1 << 21) 110#define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */ 111#define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */ 112#define CSISR_RXFF_INT (1 << 18) 113#define CSISR_EOF_INT (1 << 17) 114#define CSISR_SOF_INT (1 << 16) 115#define CSISR_F2_INT (1 << 15) 116#define CSISR_F1_INT (1 << 14) 117#define CSISR_COF_INT (1 << 13) 118#define CSISR_ECC_INT (1 << 1) 119#define CSISR_DRDY (1 << 0) 120 121#define CSICR1 0x00 122#define CSICR2 0x04 123#define CSISR (cpu_is_mx27() ? 0x08 : 0x18) 124#define CSISTATFIFO 0x0c 125#define CSIRFIFO 0x10 126#define CSIRXCNT 0x14 127#define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08) 128#define CSIDMASA_STATFIFO 0x20 129#define CSIDMATA_STATFIFO 0x24 130#define CSIDMASA_FB1 0x28 131#define CSIDMASA_FB2 0x2c 132#define CSIFBUF_PARA 0x30 133#define CSIIMAG_PARA 0x34 134 135/* EMMA PrP */ 136#define PRP_CNTL 0x00 137#define PRP_INTR_CNTL 0x04 138#define PRP_INTRSTATUS 0x08 139#define PRP_SOURCE_Y_PTR 0x0c 140#define PRP_SOURCE_CB_PTR 0x10 141#define PRP_SOURCE_CR_PTR 0x14 142#define PRP_DEST_RGB1_PTR 0x18 143#define PRP_DEST_RGB2_PTR 0x1c 144#define PRP_DEST_Y_PTR 0x20 145#define PRP_DEST_CB_PTR 0x24 146#define PRP_DEST_CR_PTR 0x28 147#define PRP_SRC_FRAME_SIZE 0x2c 148#define PRP_DEST_CH1_LINE_STRIDE 0x30 149#define PRP_SRC_PIXEL_FORMAT_CNTL 0x34 150#define PRP_CH1_PIXEL_FORMAT_CNTL 0x38 151#define PRP_CH1_OUT_IMAGE_SIZE 0x3c 152#define PRP_CH2_OUT_IMAGE_SIZE 0x40 153#define PRP_SRC_LINE_STRIDE 0x44 154#define PRP_CSC_COEF_012 0x48 155#define PRP_CSC_COEF_345 0x4c 156#define PRP_CSC_COEF_678 0x50 157#define PRP_CH1_RZ_HORI_COEF1 0x54 158#define PRP_CH1_RZ_HORI_COEF2 0x58 159#define PRP_CH1_RZ_HORI_VALID 0x5c 160#define PRP_CH1_RZ_VERT_COEF1 0x60 161#define PRP_CH1_RZ_VERT_COEF2 0x64 162#define PRP_CH1_RZ_VERT_VALID 0x68 163#define PRP_CH2_RZ_HORI_COEF1 0x6c 164#define PRP_CH2_RZ_HORI_COEF2 0x70 165#define PRP_CH2_RZ_HORI_VALID 0x74 166#define PRP_CH2_RZ_VERT_COEF1 0x78 167#define PRP_CH2_RZ_VERT_COEF2 0x7c 168#define PRP_CH2_RZ_VERT_VALID 0x80 169 170#define PRP_CNTL_CH1EN (1 << 0) 171#define PRP_CNTL_CH2EN (1 << 1) 172#define PRP_CNTL_CSIEN (1 << 2) 173#define PRP_CNTL_DATA_IN_YUV420 (0 << 3) 174#define PRP_CNTL_DATA_IN_YUV422 (1 << 3) 175#define PRP_CNTL_DATA_IN_RGB16 (2 << 3) 176#define PRP_CNTL_DATA_IN_RGB32 (3 << 3) 177#define PRP_CNTL_CH1_OUT_RGB8 (0 << 5) 178#define PRP_CNTL_CH1_OUT_RGB16 (1 << 5) 179#define PRP_CNTL_CH1_OUT_RGB32 (2 << 5) 180#define PRP_CNTL_CH1_OUT_YUV422 (3 << 5) 181#define PRP_CNTL_CH2_OUT_YUV420 (0 << 7) 182#define PRP_CNTL_CH2_OUT_YUV422 (1 << 7) 183#define PRP_CNTL_CH2_OUT_YUV444 (2 << 7) 184#define PRP_CNTL_CH1_LEN (1 << 9) 185#define PRP_CNTL_CH2_LEN (1 << 10) 186#define PRP_CNTL_SKIP_FRAME (1 << 11) 187#define PRP_CNTL_SWRST (1 << 12) 188#define PRP_CNTL_CLKEN (1 << 13) 189#define PRP_CNTL_WEN (1 << 14) 190#define PRP_CNTL_CH1BYP (1 << 15) 191#define PRP_CNTL_IN_TSKIP(x) ((x) << 16) 192#define PRP_CNTL_CH1_TSKIP(x) ((x) << 19) 193#define PRP_CNTL_CH2_TSKIP(x) ((x) << 22) 194#define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25) 195#define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27) 196#define PRP_CNTL_CH2B1EN (1 << 29) 197#define PRP_CNTL_CH2B2EN (1 << 30) 198#define PRP_CNTL_CH2FEN (1 << 31) 199 200/* IRQ Enable and status register */ 201#define PRP_INTR_RDERR (1 << 0) 202#define PRP_INTR_CH1WERR (1 << 1) 203#define PRP_INTR_CH2WERR (1 << 2) 204#define PRP_INTR_CH1FC (1 << 3) 205#define PRP_INTR_CH2FC (1 << 5) 206#define PRP_INTR_LBOVF (1 << 7) 207#define PRP_INTR_CH2OVF (1 << 8) 208 209#define mx27_camera_emma(pcdev) (cpu_is_mx27() && pcdev->use_emma) 210 211#define MAX_VIDEO_MEM 16 212 213struct mx2_camera_dev { 214 struct device *dev; 215 struct soc_camera_host soc_host; 216 struct soc_camera_device *icd; 217 struct clk *clk_csi, *clk_emma; 218 219 unsigned int irq_csi, irq_emma; 220 void __iomem *base_csi, *base_emma; 221 unsigned long base_dma; 222 223 struct mx2_camera_platform_data *pdata; 224 struct resource *res_csi, *res_emma; 225 unsigned long platform_flags; 226 227 struct list_head capture; 228 struct list_head active_bufs; 229 230 spinlock_t lock; 231 232 int dma; 233 struct mx2_buffer *active; 234 struct mx2_buffer *fb1_active; 235 struct mx2_buffer *fb2_active; 236 237 int use_emma; 238 239 u32 csicr1; 240 241 void *discard_buffer; 242 dma_addr_t discard_buffer_dma; 243 size_t discard_size; 244}; 245 246/* buffer for one video frame */ 247struct mx2_buffer { 248 /* common v4l buffer stuff -- must be first */ 249 struct videobuf_buffer vb; 250 251 enum v4l2_mbus_pixelcode code; 252 253 int bufnum; 254}; 255 256static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev) 257{ 258 unsigned long flags; 259 260 clk_disable(pcdev->clk_csi); 261 writel(0, pcdev->base_csi + CSICR1); 262 if (mx27_camera_emma(pcdev)) { 263 writel(0, pcdev->base_emma + PRP_CNTL); 264 } else if (cpu_is_mx25()) { 265 spin_lock_irqsave(&pcdev->lock, flags); 266 pcdev->fb1_active = NULL; 267 pcdev->fb2_active = NULL; 268 writel(0, pcdev->base_csi + CSIDMASA_FB1); 269 writel(0, pcdev->base_csi + CSIDMASA_FB2); 270 spin_unlock_irqrestore(&pcdev->lock, flags); 271 } 272} 273 274/* 275 * The following two functions absolutely depend on the fact, that 276 * there can be only one camera on mx2 camera sensor interface 277 */ 278static int mx2_camera_add_device(struct soc_camera_device *icd) 279{ 280 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 281 struct mx2_camera_dev *pcdev = ici->priv; 282 int ret; 283 u32 csicr1; 284 285 if (pcdev->icd) 286 return -EBUSY; 287 288 ret = clk_enable(pcdev->clk_csi); 289 if (ret < 0) 290 return ret; 291 292 csicr1 = CSICR1_MCLKEN; 293 294 if (mx27_camera_emma(pcdev)) { 295 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC | 296 CSICR1_RXFF_LEVEL(0); 297 } else if (cpu_is_mx27()) 298 csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2); 299 300 pcdev->csicr1 = csicr1; 301 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 302 303 pcdev->icd = icd; 304 305 dev_info(icd->dev.parent, "Camera driver attached to camera %d\n", 306 icd->devnum); 307 308 return 0; 309} 310 311static void mx2_camera_remove_device(struct soc_camera_device *icd) 312{ 313 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 314 struct mx2_camera_dev *pcdev = ici->priv; 315 316 BUG_ON(icd != pcdev->icd); 317 318 dev_info(icd->dev.parent, "Camera driver detached from camera %d\n", 319 icd->devnum); 320 321 mx2_camera_deactivate(pcdev); 322 323 if (pcdev->discard_buffer) { 324 dma_free_coherent(ici->v4l2_dev.dev, pcdev->discard_size, 325 pcdev->discard_buffer, 326 pcdev->discard_buffer_dma); 327 pcdev->discard_buffer = NULL; 328 } 329 330 pcdev->icd = NULL; 331} 332 333#ifdef CONFIG_MACH_MX27 334static void mx27_camera_dma_enable(struct mx2_camera_dev *pcdev) 335{ 336 u32 tmp; 337 338 imx_dma_enable(pcdev->dma); 339 340 tmp = readl(pcdev->base_csi + CSICR1); 341 tmp |= CSICR1_RF_OR_INTEN; 342 writel(tmp, pcdev->base_csi + CSICR1); 343} 344 345static irqreturn_t mx27_camera_irq(int irq_csi, void *data) 346{ 347 struct mx2_camera_dev *pcdev = data; 348 u32 status = readl(pcdev->base_csi + CSISR); 349 350 if (status & CSISR_SOF_INT && pcdev->active) { 351 u32 tmp; 352 353 tmp = readl(pcdev->base_csi + CSICR1); 354 writel(tmp | CSICR1_CLR_RXFIFO, pcdev->base_csi + CSICR1); 355 mx27_camera_dma_enable(pcdev); 356 } 357 358 writel(CSISR_SOF_INT | CSISR_RFF_OR_INT, pcdev->base_csi + CSISR); 359 360 return IRQ_HANDLED; 361} 362#else 363static irqreturn_t mx27_camera_irq(int irq_csi, void *data) 364{ 365 return IRQ_NONE; 366} 367#endif /* CONFIG_MACH_MX27 */ 368 369static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb, 370 int state) 371{ 372 struct videobuf_buffer *vb; 373 struct mx2_buffer *buf; 374 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active : 375 &pcdev->fb2_active; 376 u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2; 377 unsigned long flags; 378 379 spin_lock_irqsave(&pcdev->lock, flags); 380 381 if (*fb_active == NULL) 382 goto out; 383 384 vb = &(*fb_active)->vb; 385 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 386 vb, vb->baddr, vb->bsize); 387 388 vb->state = state; 389 do_gettimeofday(&vb->ts); 390 vb->field_count++; 391 392 wake_up(&vb->done); 393 394 if (list_empty(&pcdev->capture)) { 395 buf = NULL; 396 writel(0, pcdev->base_csi + fb_reg); 397 } else { 398 buf = list_entry(pcdev->capture.next, struct mx2_buffer, 399 vb.queue); 400 vb = &buf->vb; 401 list_del(&vb->queue); 402 vb->state = VIDEOBUF_ACTIVE; 403 writel(videobuf_to_dma_contig(vb), pcdev->base_csi + fb_reg); 404 } 405 406 *fb_active = buf; 407 408out: 409 spin_unlock_irqrestore(&pcdev->lock, flags); 410} 411 412static irqreturn_t mx25_camera_irq(int irq_csi, void *data) 413{ 414 struct mx2_camera_dev *pcdev = data; 415 u32 status = readl(pcdev->base_csi + CSISR); 416 417 if (status & CSISR_DMA_TSF_FB1_INT) 418 mx25_camera_frame_done(pcdev, 1, VIDEOBUF_DONE); 419 else if (status & CSISR_DMA_TSF_FB2_INT) 420 mx25_camera_frame_done(pcdev, 2, VIDEOBUF_DONE); 421 422 /* FIXME: handle CSISR_RFF_OR_INT */ 423 424 writel(status, pcdev->base_csi + CSISR); 425 426 return IRQ_HANDLED; 427} 428 429/* 430 * Videobuf operations 431 */ 432static int mx2_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, 433 unsigned int *size) 434{ 435 struct soc_camera_device *icd = vq->priv_data; 436 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, 437 icd->current_fmt->host_fmt); 438 439 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size); 440 441 if (bytes_per_line < 0) 442 return bytes_per_line; 443 444 *size = bytes_per_line * icd->user_height; 445 446 if (0 == *count) 447 *count = 32; 448 if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024) 449 *count = (MAX_VIDEO_MEM * 1024 * 1024) / *size; 450 451 return 0; 452} 453 454static void free_buffer(struct videobuf_queue *vq, struct mx2_buffer *buf) 455{ 456 struct soc_camera_device *icd = vq->priv_data; 457 struct videobuf_buffer *vb = &buf->vb; 458 459 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 460 vb, vb->baddr, vb->bsize); 461 462 /* 463 * This waits until this buffer is out of danger, i.e., until it is no 464 * longer in state VIDEOBUF_QUEUED or VIDEOBUF_ACTIVE 465 */ 466 videobuf_waiton(vq, vb, 0, 0); 467 468 videobuf_dma_contig_free(vq, vb); 469 dev_dbg(&icd->dev, "%s freed\n", __func__); 470 471 vb->state = VIDEOBUF_NEEDS_INIT; 472} 473 474static int mx2_videobuf_prepare(struct videobuf_queue *vq, 475 struct videobuf_buffer *vb, enum v4l2_field field) 476{ 477 struct soc_camera_device *icd = vq->priv_data; 478 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 479 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, 480 icd->current_fmt->host_fmt); 481 int ret = 0; 482 483 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 484 vb, vb->baddr, vb->bsize); 485 486 if (bytes_per_line < 0) 487 return bytes_per_line; 488 489#ifdef DEBUG 490 /* 491 * This can be useful if you want to see if we actually fill 492 * the buffer with something 493 */ 494 memset((void *)vb->baddr, 0xaa, vb->bsize); 495#endif 496 497 if (buf->code != icd->current_fmt->code || 498 vb->width != icd->user_width || 499 vb->height != icd->user_height || 500 vb->field != field) { 501 buf->code = icd->current_fmt->code; 502 vb->width = icd->user_width; 503 vb->height = icd->user_height; 504 vb->field = field; 505 vb->state = VIDEOBUF_NEEDS_INIT; 506 } 507 508 vb->size = bytes_per_line * vb->height; 509 if (vb->baddr && vb->bsize < vb->size) { 510 ret = -EINVAL; 511 goto out; 512 } 513 514 if (vb->state == VIDEOBUF_NEEDS_INIT) { 515 ret = videobuf_iolock(vq, vb, NULL); 516 if (ret) 517 goto fail; 518 519 vb->state = VIDEOBUF_PREPARED; 520 } 521 522 return 0; 523 524fail: 525 free_buffer(vq, buf); 526out: 527 return ret; 528} 529 530static void mx2_videobuf_queue(struct videobuf_queue *vq, 531 struct videobuf_buffer *vb) 532{ 533 struct soc_camera_device *icd = vq->priv_data; 534 struct soc_camera_host *ici = 535 to_soc_camera_host(icd->dev.parent); 536 struct mx2_camera_dev *pcdev = ici->priv; 537 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 538 unsigned long flags; 539 540 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 541 vb, vb->baddr, vb->bsize); 542 543 spin_lock_irqsave(&pcdev->lock, flags); 544 545 vb->state = VIDEOBUF_QUEUED; 546 list_add_tail(&vb->queue, &pcdev->capture); 547 548 if (mx27_camera_emma(pcdev)) { 549 goto out; 550#ifdef CONFIG_MACH_MX27 551 } else if (cpu_is_mx27()) { 552 int ret; 553 554 if (pcdev->active == NULL) { 555 ret = imx_dma_setup_single(pcdev->dma, 556 videobuf_to_dma_contig(vb), vb->size, 557 (u32)pcdev->base_dma + 0x10, 558 DMA_MODE_READ); 559 if (ret) { 560 vb->state = VIDEOBUF_ERROR; 561 wake_up(&vb->done); 562 goto out; 563 } 564 565 vb->state = VIDEOBUF_ACTIVE; 566 pcdev->active = buf; 567 } 568#endif 569 } else { /* cpu_is_mx25() */ 570 u32 csicr3, dma_inten = 0; 571 572 if (pcdev->fb1_active == NULL) { 573 writel(videobuf_to_dma_contig(vb), 574 pcdev->base_csi + CSIDMASA_FB1); 575 pcdev->fb1_active = buf; 576 dma_inten = CSICR1_FB1_DMA_INTEN; 577 } else if (pcdev->fb2_active == NULL) { 578 writel(videobuf_to_dma_contig(vb), 579 pcdev->base_csi + CSIDMASA_FB2); 580 pcdev->fb2_active = buf; 581 dma_inten = CSICR1_FB2_DMA_INTEN; 582 } 583 584 if (dma_inten) { 585 list_del(&vb->queue); 586 vb->state = VIDEOBUF_ACTIVE; 587 588 csicr3 = readl(pcdev->base_csi + CSICR3); 589 590 /* Reflash DMA */ 591 writel(csicr3 | CSICR3_DMA_REFLASH_RFF, 592 pcdev->base_csi + CSICR3); 593 594 /* clear & enable interrupts */ 595 writel(dma_inten, pcdev->base_csi + CSISR); 596 pcdev->csicr1 |= dma_inten; 597 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 598 599 /* enable DMA */ 600 csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1); 601 writel(csicr3, pcdev->base_csi + CSICR3); 602 } 603 } 604 605out: 606 spin_unlock_irqrestore(&pcdev->lock, flags); 607} 608 609static void mx2_videobuf_release(struct videobuf_queue *vq, 610 struct videobuf_buffer *vb) 611{ 612 struct soc_camera_device *icd = vq->priv_data; 613 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 614 struct mx2_camera_dev *pcdev = ici->priv; 615 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 616 unsigned long flags; 617 618#ifdef DEBUG 619 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 620 vb, vb->baddr, vb->bsize); 621 622 switch (vb->state) { 623 case VIDEOBUF_ACTIVE: 624 dev_info(&icd->dev, "%s (active)\n", __func__); 625 break; 626 case VIDEOBUF_QUEUED: 627 dev_info(&icd->dev, "%s (queued)\n", __func__); 628 break; 629 case VIDEOBUF_PREPARED: 630 dev_info(&icd->dev, "%s (prepared)\n", __func__); 631 break; 632 default: 633 dev_info(&icd->dev, "%s (unknown) %d\n", __func__, 634 vb->state); 635 break; 636 } 637#endif 638 639 /* 640 * Terminate only queued but inactive buffers. Active buffers are 641 * released when they become inactive after videobuf_waiton(). 642 * 643 * FIXME: implement forced termination of active buffers for mx27 and 644 * mx27 eMMA, so that the user won't get stuck in an uninterruptible 645 * state. This requires a specific handling for each of the these DMA 646 * types. 647 */ 648 spin_lock_irqsave(&pcdev->lock, flags); 649 if (vb->state == VIDEOBUF_QUEUED) { 650 list_del(&vb->queue); 651 vb->state = VIDEOBUF_ERROR; 652 } else if (cpu_is_mx25() && vb->state == VIDEOBUF_ACTIVE) { 653 if (pcdev->fb1_active == buf) { 654 pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN; 655 writel(0, pcdev->base_csi + CSIDMASA_FB1); 656 pcdev->fb1_active = NULL; 657 } else if (pcdev->fb2_active == buf) { 658 pcdev->csicr1 &= ~CSICR1_FB2_DMA_INTEN; 659 writel(0, pcdev->base_csi + CSIDMASA_FB2); 660 pcdev->fb2_active = NULL; 661 } 662 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 663 vb->state = VIDEOBUF_ERROR; 664 } 665 spin_unlock_irqrestore(&pcdev->lock, flags); 666 667 free_buffer(vq, buf); 668} 669 670static struct videobuf_queue_ops mx2_videobuf_ops = { 671 .buf_setup = mx2_videobuf_setup, 672 .buf_prepare = mx2_videobuf_prepare, 673 .buf_queue = mx2_videobuf_queue, 674 .buf_release = mx2_videobuf_release, 675}; 676 677static void mx2_camera_init_videobuf(struct videobuf_queue *q, 678 struct soc_camera_device *icd) 679{ 680 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 681 struct mx2_camera_dev *pcdev = ici->priv; 682 683 videobuf_queue_dma_contig_init(q, &mx2_videobuf_ops, pcdev->dev, 684 &pcdev->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE, 685 V4L2_FIELD_NONE, sizeof(struct mx2_buffer), 686 icd, &icd->video_lock); 687} 688 689#define MX2_BUS_FLAGS (SOCAM_DATAWIDTH_8 | \ 690 SOCAM_MASTER | \ 691 SOCAM_VSYNC_ACTIVE_HIGH | \ 692 SOCAM_VSYNC_ACTIVE_LOW | \ 693 SOCAM_HSYNC_ACTIVE_HIGH | \ 694 SOCAM_HSYNC_ACTIVE_LOW | \ 695 SOCAM_PCLK_SAMPLE_RISING | \ 696 SOCAM_PCLK_SAMPLE_FALLING | \ 697 SOCAM_DATA_ACTIVE_HIGH | \ 698 SOCAM_DATA_ACTIVE_LOW) 699 700static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev) 701{ 702 u32 cntl; 703 int count = 0; 704 705 cntl = readl(pcdev->base_emma + PRP_CNTL); 706 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL); 707 while (count++ < 100) { 708 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST)) 709 return 0; 710 barrier(); 711 udelay(1); 712 } 713 714 return -ETIMEDOUT; 715} 716 717static void mx27_camera_emma_buf_init(struct soc_camera_device *icd, 718 int bytesperline) 719{ 720 struct soc_camera_host *ici = 721 to_soc_camera_host(icd->dev.parent); 722 struct mx2_camera_dev *pcdev = ici->priv; 723 724 writel(pcdev->discard_buffer_dma, 725 pcdev->base_emma + PRP_DEST_RGB1_PTR); 726 writel(pcdev->discard_buffer_dma, 727 pcdev->base_emma + PRP_DEST_RGB2_PTR); 728 729 /* 730 * We only use the EMMA engine to get rid of the broken 731 * DMA Engine. No color space consversion at the moment. 732 * We set the incomming and outgoing pixelformat to an 733 * 16 Bit wide format and adjust the bytesperline 734 * accordingly. With this configuration the inputdata 735 * will not be changed by the emma and could be any type 736 * of 16 Bit Pixelformat. 737 */ 738 writel(PRP_CNTL_CH1EN | 739 PRP_CNTL_CSIEN | 740 PRP_CNTL_DATA_IN_RGB16 | 741 PRP_CNTL_CH1_OUT_RGB16 | 742 PRP_CNTL_CH1_LEN | 743 PRP_CNTL_CH1BYP | 744 PRP_CNTL_CH1_TSKIP(0) | 745 PRP_CNTL_IN_TSKIP(0), 746 pcdev->base_emma + PRP_CNTL); 747 748 writel(((bytesperline >> 1) << 16) | icd->user_height, 749 pcdev->base_emma + PRP_SRC_FRAME_SIZE); 750 writel(((bytesperline >> 1) << 16) | icd->user_height, 751 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE); 752 writel(bytesperline, 753 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE); 754 writel(0x2ca00565, /* RGB565 */ 755 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL); 756 writel(0x2ca00565, /* RGB565 */ 757 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL); 758 759 /* Enable interrupts */ 760 writel(PRP_INTR_RDERR | 761 PRP_INTR_CH1WERR | 762 PRP_INTR_CH2WERR | 763 PRP_INTR_CH1FC | 764 PRP_INTR_CH2FC | 765 PRP_INTR_LBOVF | 766 PRP_INTR_CH2OVF, 767 pcdev->base_emma + PRP_INTR_CNTL); 768} 769 770static int mx2_camera_set_bus_param(struct soc_camera_device *icd, 771 __u32 pixfmt) 772{ 773 struct soc_camera_host *ici = 774 to_soc_camera_host(icd->dev.parent); 775 struct mx2_camera_dev *pcdev = ici->priv; 776 unsigned long camera_flags, common_flags; 777 int ret = 0; 778 int bytesperline; 779 u32 csicr1 = pcdev->csicr1; 780 781 camera_flags = icd->ops->query_bus_param(icd); 782 783 common_flags = soc_camera_bus_param_compatible(camera_flags, 784 MX2_BUS_FLAGS); 785 if (!common_flags) 786 return -EINVAL; 787 788 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) && 789 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) { 790 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH) 791 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW; 792 else 793 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH; 794 } 795 796 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && 797 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { 798 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING) 799 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; 800 else 801 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; 802 } 803 804 ret = icd->ops->set_bus_param(icd, common_flags); 805 if (ret < 0) 806 return ret; 807 808 if (common_flags & SOCAM_PCLK_SAMPLE_RISING) 809 csicr1 |= CSICR1_REDGE; 810 if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH) 811 csicr1 |= CSICR1_SOF_POL; 812 if (common_flags & SOCAM_HSYNC_ACTIVE_HIGH) 813 csicr1 |= CSICR1_HSYNC_POL; 814 if (pcdev->platform_flags & MX2_CAMERA_SWAP16) 815 csicr1 |= CSICR1_SWAP16_EN; 816 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC) 817 csicr1 |= CSICR1_EXT_VSYNC; 818 if (pcdev->platform_flags & MX2_CAMERA_CCIR) 819 csicr1 |= CSICR1_CCIR_EN; 820 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE) 821 csicr1 |= CSICR1_CCIR_MODE; 822 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK) 823 csicr1 |= CSICR1_GCLK_MODE; 824 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA) 825 csicr1 |= CSICR1_INV_DATA; 826 if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB) 827 csicr1 |= CSICR1_PACK_DIR; 828 829 pcdev->csicr1 = csicr1; 830 831 bytesperline = soc_mbus_bytes_per_line(icd->user_width, 832 icd->current_fmt->host_fmt); 833 if (bytesperline < 0) 834 return bytesperline; 835 836 if (mx27_camera_emma(pcdev)) { 837 ret = mx27_camera_emma_prp_reset(pcdev); 838 if (ret) 839 return ret; 840 841 if (pcdev->discard_buffer) 842 dma_free_coherent(ici->v4l2_dev.dev, 843 pcdev->discard_size, pcdev->discard_buffer, 844 pcdev->discard_buffer_dma); 845 846 /* 847 * I didn't manage to properly enable/disable the prp 848 * on a per frame basis during running transfers, 849 * thus we allocate a buffer here and use it to 850 * discard frames when no buffer is available. 851 * Feel free to work on this ;) 852 */ 853 pcdev->discard_size = icd->user_height * bytesperline; 854 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev, 855 pcdev->discard_size, &pcdev->discard_buffer_dma, 856 GFP_KERNEL); 857 if (!pcdev->discard_buffer) 858 return -ENOMEM; 859 860 mx27_camera_emma_buf_init(icd, bytesperline); 861 } else if (cpu_is_mx25()) { 862 writel((bytesperline * icd->user_height) >> 2, 863 pcdev->base_csi + CSIRXCNT); 864 writel((bytesperline << 16) | icd->user_height, 865 pcdev->base_csi + CSIIMAG_PARA); 866 } 867 868 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 869 870 return 0; 871} 872 873static int mx2_camera_set_crop(struct soc_camera_device *icd, 874 struct v4l2_crop *a) 875{ 876 struct v4l2_rect *rect = &a->c; 877 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 878 struct v4l2_mbus_framefmt mf; 879 int ret; 880 881 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096); 882 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096); 883 884 ret = v4l2_subdev_call(sd, video, s_crop, a); 885 if (ret < 0) 886 return ret; 887 888 /* The capture device might have changed its output */ 889 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); 890 if (ret < 0) 891 return ret; 892 893 dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n", 894 mf.width, mf.height); 895 896 icd->user_width = mf.width; 897 icd->user_height = mf.height; 898 899 return ret; 900} 901 902static int mx2_camera_set_fmt(struct soc_camera_device *icd, 903 struct v4l2_format *f) 904{ 905 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 906 const struct soc_camera_format_xlate *xlate; 907 struct v4l2_pix_format *pix = &f->fmt.pix; 908 struct v4l2_mbus_framefmt mf; 909 int ret; 910 911 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); 912 if (!xlate) { 913 dev_warn(icd->dev.parent, "Format %x not found\n", 914 pix->pixelformat); 915 return -EINVAL; 916 } 917 918 mf.width = pix->width; 919 mf.height = pix->height; 920 mf.field = pix->field; 921 mf.colorspace = pix->colorspace; 922 mf.code = xlate->code; 923 924 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); 925 if (ret < 0 && ret != -ENOIOCTLCMD) 926 return ret; 927 928 if (mf.code != xlate->code) 929 return -EINVAL; 930 931 pix->width = mf.width; 932 pix->height = mf.height; 933 pix->field = mf.field; 934 pix->colorspace = mf.colorspace; 935 icd->current_fmt = xlate; 936 937 return 0; 938} 939 940static int mx2_camera_try_fmt(struct soc_camera_device *icd, 941 struct v4l2_format *f) 942{ 943 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 944 const struct soc_camera_format_xlate *xlate; 945 struct v4l2_pix_format *pix = &f->fmt.pix; 946 struct v4l2_mbus_framefmt mf; 947 __u32 pixfmt = pix->pixelformat; 948 unsigned int width_limit; 949 int ret; 950 951 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); 952 if (pixfmt && !xlate) { 953 dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt); 954 return -EINVAL; 955 } 956 957 /* FIXME: implement MX27 limits */ 958 959 /* limit to MX25 hardware capabilities */ 960 if (cpu_is_mx25()) { 961 if (xlate->host_fmt->bits_per_sample <= 8) 962 width_limit = 0xffff * 4; 963 else 964 width_limit = 0xffff * 2; 965 /* CSIIMAG_PARA limit */ 966 if (pix->width > width_limit) 967 pix->width = width_limit; 968 if (pix->height > 0xffff) 969 pix->height = 0xffff; 970 971 pix->bytesperline = soc_mbus_bytes_per_line(pix->width, 972 xlate->host_fmt); 973 if (pix->bytesperline < 0) 974 return pix->bytesperline; 975 pix->sizeimage = pix->height * pix->bytesperline; 976 if (pix->sizeimage > (4 * 0x3ffff)) { /* CSIRXCNT limit */ 977 dev_warn(icd->dev.parent, 978 "Image size (%u) above limit\n", 979 pix->sizeimage); 980 return -EINVAL; 981 } 982 } 983 984 /* limit to sensor capabilities */ 985 mf.width = pix->width; 986 mf.height = pix->height; 987 mf.field = pix->field; 988 mf.colorspace = pix->colorspace; 989 mf.code = xlate->code; 990 991 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); 992 if (ret < 0) 993 return ret; 994 995 if (mf.field == V4L2_FIELD_ANY) 996 mf.field = V4L2_FIELD_NONE; 997 if (mf.field != V4L2_FIELD_NONE) { 998 dev_err(icd->dev.parent, "Field type %d unsupported.\n", 999 mf.field); 1000 return -EINVAL; 1001 } 1002 1003 pix->width = mf.width; 1004 pix->height = mf.height; 1005 pix->field = mf.field; 1006 pix->colorspace = mf.colorspace; 1007 1008 return 0; 1009} 1010 1011static int mx2_camera_querycap(struct soc_camera_host *ici, 1012 struct v4l2_capability *cap) 1013{ 1014 /* cap->name is set by the friendly caller:-> */ 1015 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card)); 1016 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; 1017 1018 return 0; 1019} 1020 1021static int mx2_camera_reqbufs(struct soc_camera_device *icd, 1022 struct v4l2_requestbuffers *p) 1023{ 1024 int i; 1025 1026 for (i = 0; i < p->count; i++) { 1027 struct mx2_buffer *buf = container_of(icd->vb_vidq.bufs[i], 1028 struct mx2_buffer, vb); 1029 INIT_LIST_HEAD(&buf->vb.queue); 1030 } 1031 1032 return 0; 1033} 1034 1035#ifdef CONFIG_MACH_MX27 1036static void mx27_camera_frame_done(struct mx2_camera_dev *pcdev, int state) 1037{ 1038 struct videobuf_buffer *vb; 1039 struct mx2_buffer *buf; 1040 unsigned long flags; 1041 int ret; 1042 1043 spin_lock_irqsave(&pcdev->lock, flags); 1044 1045 if (!pcdev->active) { 1046 dev_err(pcdev->dev, "%s called with no active buffer!\n", 1047 __func__); 1048 goto out; 1049 } 1050 1051 vb = &pcdev->active->vb; 1052 buf = container_of(vb, struct mx2_buffer, vb); 1053 WARN_ON(list_empty(&vb->queue)); 1054 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 1055 vb, vb->baddr, vb->bsize); 1056 1057 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ 1058 list_del_init(&vb->queue); 1059 vb->state = state; 1060 do_gettimeofday(&vb->ts); 1061 vb->field_count++; 1062 1063 wake_up(&vb->done); 1064 1065 if (list_empty(&pcdev->capture)) { 1066 pcdev->active = NULL; 1067 goto out; 1068 } 1069 1070 pcdev->active = list_entry(pcdev->capture.next, 1071 struct mx2_buffer, vb.queue); 1072 1073 vb = &pcdev->active->vb; 1074 vb->state = VIDEOBUF_ACTIVE; 1075 1076 ret = imx_dma_setup_single(pcdev->dma, videobuf_to_dma_contig(vb), 1077 vb->size, (u32)pcdev->base_dma + 0x10, DMA_MODE_READ); 1078 1079 if (ret) { 1080 vb->state = VIDEOBUF_ERROR; 1081 pcdev->active = NULL; 1082 wake_up(&vb->done); 1083 } 1084 1085out: 1086 spin_unlock_irqrestore(&pcdev->lock, flags); 1087} 1088 1089static void mx27_camera_dma_err_callback(int channel, void *data, int err) 1090{ 1091 struct mx2_camera_dev *pcdev = data; 1092 1093 mx27_camera_frame_done(pcdev, VIDEOBUF_ERROR); 1094} 1095 1096static void mx27_camera_dma_callback(int channel, void *data) 1097{ 1098 struct mx2_camera_dev *pcdev = data; 1099 1100 mx27_camera_frame_done(pcdev, VIDEOBUF_DONE); 1101} 1102 1103#define DMA_REQ_CSI_RX 31 /* FIXME: Add this to a resource */ 1104 1105static int __devinit mx27_camera_dma_init(struct platform_device *pdev, 1106 struct mx2_camera_dev *pcdev) 1107{ 1108 int err; 1109 1110 pcdev->dma = imx_dma_request_by_prio("CSI RX DMA", DMA_PRIO_HIGH); 1111 if (pcdev->dma < 0) { 1112 dev_err(&pdev->dev, "%s failed to request DMA channel\n", 1113 __func__); 1114 return pcdev->dma; 1115 } 1116 1117 err = imx_dma_setup_handlers(pcdev->dma, mx27_camera_dma_callback, 1118 mx27_camera_dma_err_callback, pcdev); 1119 if (err) { 1120 dev_err(&pdev->dev, "%s failed to set DMA callback\n", 1121 __func__); 1122 goto err_out; 1123 } 1124 1125 err = imx_dma_config_channel(pcdev->dma, 1126 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO, 1127 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR, 1128 DMA_REQ_CSI_RX, 1); 1129 if (err) { 1130 dev_err(&pdev->dev, "%s failed to config DMA channel\n", 1131 __func__); 1132 goto err_out; 1133 } 1134 1135 imx_dma_config_burstlen(pcdev->dma, 64); 1136 1137 return 0; 1138 1139err_out: 1140 imx_dma_free(pcdev->dma); 1141 1142 return err; 1143} 1144#endif /* CONFIG_MACH_MX27 */ 1145 1146static unsigned int mx2_camera_poll(struct file *file, poll_table *pt) 1147{ 1148 struct soc_camera_device *icd = file->private_data; 1149 1150 return videobuf_poll_stream(file, &icd->vb_vidq, pt); 1151} 1152 1153static struct soc_camera_host_ops mx2_soc_camera_host_ops = { 1154 .owner = THIS_MODULE, 1155 .add = mx2_camera_add_device, 1156 .remove = mx2_camera_remove_device, 1157 .set_fmt = mx2_camera_set_fmt, 1158 .set_crop = mx2_camera_set_crop, 1159 .try_fmt = mx2_camera_try_fmt, 1160 .init_videobuf = mx2_camera_init_videobuf, 1161 .reqbufs = mx2_camera_reqbufs, 1162 .poll = mx2_camera_poll, 1163 .querycap = mx2_camera_querycap, 1164 .set_bus_param = mx2_camera_set_bus_param, 1165}; 1166 1167static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev, 1168 int bufnum, int state) 1169{ 1170 struct mx2_buffer *buf; 1171 struct videobuf_buffer *vb; 1172 unsigned long phys; 1173 1174 if (!list_empty(&pcdev->active_bufs)) { 1175 buf = list_entry(pcdev->active_bufs.next, 1176 struct mx2_buffer, vb.queue); 1177 1178 BUG_ON(buf->bufnum != bufnum); 1179 1180 vb = &buf->vb; 1181#ifdef DEBUG 1182 phys = videobuf_to_dma_contig(vb); 1183 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum) 1184 != phys) { 1185 dev_err(pcdev->dev, "%p != %p\n", phys, 1186 readl(pcdev->base_emma + 1187 PRP_DEST_RGB1_PTR + 1188 4 * bufnum)); 1189 } 1190#endif 1191 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb, 1192 vb->baddr, vb->bsize); 1193 1194 list_del(&vb->queue); 1195 vb->state = state; 1196 do_gettimeofday(&vb->ts); 1197 vb->field_count++; 1198 1199 wake_up(&vb->done); 1200 } 1201 1202 if (list_empty(&pcdev->capture)) { 1203 writel(pcdev->discard_buffer_dma, pcdev->base_emma + 1204 PRP_DEST_RGB1_PTR + 4 * bufnum); 1205 return; 1206 } 1207 1208 buf = list_entry(pcdev->capture.next, 1209 struct mx2_buffer, vb.queue); 1210 1211 buf->bufnum = !bufnum; 1212 1213 list_move_tail(pcdev->capture.next, &pcdev->active_bufs); 1214 1215 vb = &buf->vb; 1216 vb->state = VIDEOBUF_ACTIVE; 1217 1218 phys = videobuf_to_dma_contig(vb); 1219 writel(phys, pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum); 1220} 1221 1222static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data) 1223{ 1224 struct mx2_camera_dev *pcdev = data; 1225 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS); 1226 struct mx2_buffer *buf; 1227 1228 if (status & (1 << 7)) { /* overflow */ 1229 u32 cntl; 1230 /* 1231 * We only disable channel 1 here since this is the only 1232 * enabled channel 1233 * 1234 * FIXME: the correct DMA overflow handling should be resetting 1235 * the buffer, returning an error frame, and continuing with 1236 * the next one. 1237 */ 1238 cntl = readl(pcdev->base_emma + PRP_CNTL); 1239 writel(cntl & ~PRP_CNTL_CH1EN, pcdev->base_emma + PRP_CNTL); 1240 writel(cntl, pcdev->base_emma + PRP_CNTL); 1241 } 1242 if ((status & (3 << 5)) == (3 << 5) 1243 && !list_empty(&pcdev->active_bufs)) { 1244 /* 1245 * Both buffers have triggered, process the one we're expecting 1246 * to first 1247 */ 1248 buf = list_entry(pcdev->active_bufs.next, 1249 struct mx2_buffer, vb.queue); 1250 mx27_camera_frame_done_emma(pcdev, buf->bufnum, VIDEOBUF_DONE); 1251 status &= ~(1 << (6 - buf->bufnum)); /* mark processed */ 1252 } 1253 if (status & (1 << 6)) 1254 mx27_camera_frame_done_emma(pcdev, 0, VIDEOBUF_DONE); 1255 if (status & (1 << 5)) 1256 mx27_camera_frame_done_emma(pcdev, 1, VIDEOBUF_DONE); 1257 1258 writel(status, pcdev->base_emma + PRP_INTRSTATUS); 1259 1260 return IRQ_HANDLED; 1261} 1262 1263static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev) 1264{ 1265 struct resource *res_emma = pcdev->res_emma; 1266 int err = 0; 1267 1268 if (!request_mem_region(res_emma->start, resource_size(res_emma), 1269 MX2_CAM_DRV_NAME)) { 1270 err = -EBUSY; 1271 goto out; 1272 } 1273 1274 pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma)); 1275 if (!pcdev->base_emma) { 1276 err = -ENOMEM; 1277 goto exit_release; 1278 } 1279 1280 err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0, 1281 MX2_CAM_DRV_NAME, pcdev); 1282 if (err) { 1283 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n"); 1284 goto exit_iounmap; 1285 } 1286 1287 pcdev->clk_emma = clk_get(NULL, "emma"); 1288 if (IS_ERR(pcdev->clk_emma)) { 1289 err = PTR_ERR(pcdev->clk_emma); 1290 goto exit_free_irq; 1291 } 1292 1293 clk_enable(pcdev->clk_emma); 1294 1295 err = mx27_camera_emma_prp_reset(pcdev); 1296 if (err) 1297 goto exit_clk_emma_put; 1298 1299 return err; 1300 1301exit_clk_emma_put: 1302 clk_disable(pcdev->clk_emma); 1303 clk_put(pcdev->clk_emma); 1304exit_free_irq: 1305 free_irq(pcdev->irq_emma, pcdev); 1306exit_iounmap: 1307 iounmap(pcdev->base_emma); 1308exit_release: 1309 release_mem_region(res_emma->start, resource_size(res_emma)); 1310out: 1311 return err; 1312} 1313 1314static int __devinit mx2_camera_probe(struct platform_device *pdev) 1315{ 1316 struct mx2_camera_dev *pcdev; 1317 struct resource *res_csi, *res_emma; 1318 void __iomem *base_csi; 1319 int irq_csi, irq_emma; 1320 irq_handler_t mx2_cam_irq_handler = cpu_is_mx25() ? mx25_camera_irq 1321 : mx27_camera_irq; 1322 int err = 0; 1323 1324 dev_dbg(&pdev->dev, "initialising\n"); 1325 1326 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1327 irq_csi = platform_get_irq(pdev, 0); 1328 if (res_csi == NULL || irq_csi < 0) { 1329 dev_err(&pdev->dev, "Missing platform resources data\n"); 1330 err = -ENODEV; 1331 goto exit; 1332 } 1333 1334 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); 1335 if (!pcdev) { 1336 dev_err(&pdev->dev, "Could not allocate pcdev\n"); 1337 err = -ENOMEM; 1338 goto exit; 1339 } 1340 1341 pcdev->clk_csi = clk_get(&pdev->dev, NULL); 1342 if (IS_ERR(pcdev->clk_csi)) { 1343 err = PTR_ERR(pcdev->clk_csi); 1344 goto exit_kfree; 1345 } 1346 1347 dev_dbg(&pdev->dev, "Camera clock frequency: %ld\n", 1348 clk_get_rate(pcdev->clk_csi)); 1349 1350 /* Initialize DMA */ 1351#ifdef CONFIG_MACH_MX27 1352 if (cpu_is_mx27()) { 1353 err = mx27_camera_dma_init(pdev, pcdev); 1354 if (err) 1355 goto exit_clk_put; 1356 } 1357#endif /* CONFIG_MACH_MX27 */ 1358 1359 pcdev->res_csi = res_csi; 1360 pcdev->pdata = pdev->dev.platform_data; 1361 if (pcdev->pdata) { 1362 long rate; 1363 1364 pcdev->platform_flags = pcdev->pdata->flags; 1365 1366 rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2); 1367 if (rate <= 0) { 1368 err = -ENODEV; 1369 goto exit_dma_free; 1370 } 1371 err = clk_set_rate(pcdev->clk_csi, rate); 1372 if (err < 0) 1373 goto exit_dma_free; 1374 } 1375 1376 INIT_LIST_HEAD(&pcdev->capture); 1377 INIT_LIST_HEAD(&pcdev->active_bufs); 1378 spin_lock_init(&pcdev->lock); 1379 1380 /* 1381 * Request the regions. 1382 */ 1383 if (!request_mem_region(res_csi->start, resource_size(res_csi), 1384 MX2_CAM_DRV_NAME)) { 1385 err = -EBUSY; 1386 goto exit_dma_free; 1387 } 1388 1389 base_csi = ioremap(res_csi->start, resource_size(res_csi)); 1390 if (!base_csi) { 1391 err = -ENOMEM; 1392 goto exit_release; 1393 } 1394 pcdev->irq_csi = irq_csi; 1395 pcdev->base_csi = base_csi; 1396 pcdev->base_dma = res_csi->start; 1397 pcdev->dev = &pdev->dev; 1398 1399 err = request_irq(pcdev->irq_csi, mx2_cam_irq_handler, 0, 1400 MX2_CAM_DRV_NAME, pcdev); 1401 if (err) { 1402 dev_err(pcdev->dev, "Camera interrupt register failed \n"); 1403 goto exit_iounmap; 1404 } 1405 1406 if (cpu_is_mx27()) { 1407 /* EMMA support */ 1408 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1409 irq_emma = platform_get_irq(pdev, 1); 1410 1411 if (res_emma && irq_emma >= 0) { 1412 dev_info(&pdev->dev, "Using EMMA\n"); 1413 pcdev->use_emma = 1; 1414 pcdev->res_emma = res_emma; 1415 pcdev->irq_emma = irq_emma; 1416 if (mx27_camera_emma_init(pcdev)) 1417 goto exit_free_irq; 1418 } 1419 } 1420 1421 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME, 1422 pcdev->soc_host.ops = &mx2_soc_camera_host_ops, 1423 pcdev->soc_host.priv = pcdev; 1424 pcdev->soc_host.v4l2_dev.dev = &pdev->dev; 1425 pcdev->soc_host.nr = pdev->id; 1426 err = soc_camera_host_register(&pcdev->soc_host); 1427 if (err) 1428 goto exit_free_emma; 1429 1430 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n", 1431 clk_get_rate(pcdev->clk_csi)); 1432 1433 return 0; 1434 1435exit_free_emma: 1436 if (mx27_camera_emma(pcdev)) { 1437 free_irq(pcdev->irq_emma, pcdev); 1438 clk_disable(pcdev->clk_emma); 1439 clk_put(pcdev->clk_emma); 1440 iounmap(pcdev->base_emma); 1441 release_mem_region(res_emma->start, resource_size(res_emma)); 1442 } 1443exit_free_irq: 1444 free_irq(pcdev->irq_csi, pcdev); 1445exit_iounmap: 1446 iounmap(base_csi); 1447exit_release: 1448 release_mem_region(res_csi->start, resource_size(res_csi)); 1449exit_dma_free: 1450#ifdef CONFIG_MACH_MX27 1451 if (cpu_is_mx27()) 1452 imx_dma_free(pcdev->dma); 1453exit_clk_put: 1454 clk_put(pcdev->clk_csi); 1455#endif /* CONFIG_MACH_MX27 */ 1456exit_kfree: 1457 kfree(pcdev); 1458exit: 1459 return err; 1460} 1461 1462static int __devexit mx2_camera_remove(struct platform_device *pdev) 1463{ 1464 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); 1465 struct mx2_camera_dev *pcdev = container_of(soc_host, 1466 struct mx2_camera_dev, soc_host); 1467 struct resource *res; 1468 1469 clk_put(pcdev->clk_csi); 1470#ifdef CONFIG_MACH_MX27 1471 if (cpu_is_mx27()) 1472 imx_dma_free(pcdev->dma); 1473#endif /* CONFIG_MACH_MX27 */ 1474 free_irq(pcdev->irq_csi, pcdev); 1475 if (mx27_camera_emma(pcdev)) 1476 free_irq(pcdev->irq_emma, pcdev); 1477 1478 soc_camera_host_unregister(&pcdev->soc_host); 1479 1480 iounmap(pcdev->base_csi); 1481 1482 if (mx27_camera_emma(pcdev)) { 1483 clk_disable(pcdev->clk_emma); 1484 clk_put(pcdev->clk_emma); 1485 iounmap(pcdev->base_emma); 1486 res = pcdev->res_emma; 1487 release_mem_region(res->start, resource_size(res)); 1488 } 1489 1490 res = pcdev->res_csi; 1491 release_mem_region(res->start, resource_size(res)); 1492 1493 kfree(pcdev); 1494 1495 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n"); 1496 1497 return 0; 1498} 1499 1500static struct platform_driver mx2_camera_driver = { 1501 .driver = { 1502 .name = MX2_CAM_DRV_NAME, 1503 }, 1504 .remove = __devexit_p(mx2_camera_remove), 1505}; 1506 1507 1508static int __init mx2_camera_init(void) 1509{ 1510 return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe); 1511} 1512 1513static void __exit mx2_camera_exit(void) 1514{ 1515 return platform_driver_unregister(&mx2_camera_driver); 1516} 1517 1518module_init(mx2_camera_init); 1519module_exit(mx2_camera_exit); 1520 1521MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver"); 1522MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>"); 1523MODULE_LICENSE("GPL"); 1524MODULE_VERSION(MX2_CAM_VERSION); 1525