mx2_camera.c revision 750a6dff6e81fac5ef95d054a6a907debcef9fde
1/* 2 * V4L2 Driver for i.MX27/i.MX25 camera host 3 * 4 * Copyright (C) 2008, Sascha Hauer, Pengutronix 5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography 6 * Copyright (C) 2012, Javier Martin, Vista Silicon S.L. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14#include <linux/init.h> 15#include <linux/module.h> 16#include <linux/io.h> 17#include <linux/delay.h> 18#include <linux/slab.h> 19#include <linux/dma-mapping.h> 20#include <linux/errno.h> 21#include <linux/fs.h> 22#include <linux/gcd.h> 23#include <linux/interrupt.h> 24#include <linux/kernel.h> 25#include <linux/mm.h> 26#include <linux/moduleparam.h> 27#include <linux/time.h> 28#include <linux/device.h> 29#include <linux/platform_device.h> 30#include <linux/mutex.h> 31#include <linux/clk.h> 32 33#include <media/v4l2-common.h> 34#include <media/v4l2-dev.h> 35#include <media/videobuf2-core.h> 36#include <media/videobuf2-dma-contig.h> 37#include <media/soc_camera.h> 38#include <media/soc_mediabus.h> 39 40#include <linux/videodev2.h> 41 42#include <mach/mx2_cam.h> 43#include <mach/hardware.h> 44 45#include <asm/dma.h> 46 47#define MX2_CAM_DRV_NAME "mx2-camera" 48#define MX2_CAM_VERSION "0.0.6" 49#define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera" 50 51/* reset values */ 52#define CSICR1_RESET_VAL 0x40000800 53#define CSICR2_RESET_VAL 0x0 54#define CSICR3_RESET_VAL 0x0 55 56/* csi control reg 1 */ 57#define CSICR1_SWAP16_EN (1 << 31) 58#define CSICR1_EXT_VSYNC (1 << 30) 59#define CSICR1_EOF_INTEN (1 << 29) 60#define CSICR1_PRP_IF_EN (1 << 28) 61#define CSICR1_CCIR_MODE (1 << 27) 62#define CSICR1_COF_INTEN (1 << 26) 63#define CSICR1_SF_OR_INTEN (1 << 25) 64#define CSICR1_RF_OR_INTEN (1 << 24) 65#define CSICR1_STATFF_LEVEL (3 << 22) 66#define CSICR1_STATFF_INTEN (1 << 21) 67#define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */ 68#define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */ 69#define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */ 70#define CSICR1_RXFF_INTEN (1 << 18) 71#define CSICR1_SOF_POL (1 << 17) 72#define CSICR1_SOF_INTEN (1 << 16) 73#define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12) 74#define CSICR1_HSYNC_POL (1 << 11) 75#define CSICR1_CCIR_EN (1 << 10) 76#define CSICR1_MCLKEN (1 << 9) 77#define CSICR1_FCC (1 << 8) 78#define CSICR1_PACK_DIR (1 << 7) 79#define CSICR1_CLR_STATFIFO (1 << 6) 80#define CSICR1_CLR_RXFIFO (1 << 5) 81#define CSICR1_GCLK_MODE (1 << 4) 82#define CSICR1_INV_DATA (1 << 3) 83#define CSICR1_INV_PCLK (1 << 2) 84#define CSICR1_REDGE (1 << 1) 85 86#define SHIFT_STATFF_LEVEL 22 87#define SHIFT_RXFF_LEVEL 19 88#define SHIFT_MCLKDIV 12 89 90/* control reg 3 */ 91#define CSICR3_FRMCNT (0xFFFF << 16) 92#define CSICR3_FRMCNT_RST (1 << 15) 93#define CSICR3_DMA_REFLASH_RFF (1 << 14) 94#define CSICR3_DMA_REFLASH_SFF (1 << 13) 95#define CSICR3_DMA_REQ_EN_RFF (1 << 12) 96#define CSICR3_DMA_REQ_EN_SFF (1 << 11) 97#define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */ 98#define CSICR3_CSI_SUP (1 << 3) 99#define CSICR3_ZERO_PACK_EN (1 << 2) 100#define CSICR3_ECC_INT_EN (1 << 1) 101#define CSICR3_ECC_AUTO_EN (1 << 0) 102 103#define SHIFT_FRMCNT 16 104 105/* csi status reg */ 106#define CSISR_SFF_OR_INT (1 << 25) 107#define CSISR_RFF_OR_INT (1 << 24) 108#define CSISR_STATFF_INT (1 << 21) 109#define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */ 110#define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */ 111#define CSISR_RXFF_INT (1 << 18) 112#define CSISR_EOF_INT (1 << 17) 113#define CSISR_SOF_INT (1 << 16) 114#define CSISR_F2_INT (1 << 15) 115#define CSISR_F1_INT (1 << 14) 116#define CSISR_COF_INT (1 << 13) 117#define CSISR_ECC_INT (1 << 1) 118#define CSISR_DRDY (1 << 0) 119 120#define CSICR1 0x00 121#define CSICR2 0x04 122#define CSISR (cpu_is_mx27() ? 0x08 : 0x18) 123#define CSISTATFIFO 0x0c 124#define CSIRFIFO 0x10 125#define CSIRXCNT 0x14 126#define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08) 127#define CSIDMASA_STATFIFO 0x20 128#define CSIDMATA_STATFIFO 0x24 129#define CSIDMASA_FB1 0x28 130#define CSIDMASA_FB2 0x2c 131#define CSIFBUF_PARA 0x30 132#define CSIIMAG_PARA 0x34 133 134/* EMMA PrP */ 135#define PRP_CNTL 0x00 136#define PRP_INTR_CNTL 0x04 137#define PRP_INTRSTATUS 0x08 138#define PRP_SOURCE_Y_PTR 0x0c 139#define PRP_SOURCE_CB_PTR 0x10 140#define PRP_SOURCE_CR_PTR 0x14 141#define PRP_DEST_RGB1_PTR 0x18 142#define PRP_DEST_RGB2_PTR 0x1c 143#define PRP_DEST_Y_PTR 0x20 144#define PRP_DEST_CB_PTR 0x24 145#define PRP_DEST_CR_PTR 0x28 146#define PRP_SRC_FRAME_SIZE 0x2c 147#define PRP_DEST_CH1_LINE_STRIDE 0x30 148#define PRP_SRC_PIXEL_FORMAT_CNTL 0x34 149#define PRP_CH1_PIXEL_FORMAT_CNTL 0x38 150#define PRP_CH1_OUT_IMAGE_SIZE 0x3c 151#define PRP_CH2_OUT_IMAGE_SIZE 0x40 152#define PRP_SRC_LINE_STRIDE 0x44 153#define PRP_CSC_COEF_012 0x48 154#define PRP_CSC_COEF_345 0x4c 155#define PRP_CSC_COEF_678 0x50 156#define PRP_CH1_RZ_HORI_COEF1 0x54 157#define PRP_CH1_RZ_HORI_COEF2 0x58 158#define PRP_CH1_RZ_HORI_VALID 0x5c 159#define PRP_CH1_RZ_VERT_COEF1 0x60 160#define PRP_CH1_RZ_VERT_COEF2 0x64 161#define PRP_CH1_RZ_VERT_VALID 0x68 162#define PRP_CH2_RZ_HORI_COEF1 0x6c 163#define PRP_CH2_RZ_HORI_COEF2 0x70 164#define PRP_CH2_RZ_HORI_VALID 0x74 165#define PRP_CH2_RZ_VERT_COEF1 0x78 166#define PRP_CH2_RZ_VERT_COEF2 0x7c 167#define PRP_CH2_RZ_VERT_VALID 0x80 168 169#define PRP_CNTL_CH1EN (1 << 0) 170#define PRP_CNTL_CH2EN (1 << 1) 171#define PRP_CNTL_CSIEN (1 << 2) 172#define PRP_CNTL_DATA_IN_YUV420 (0 << 3) 173#define PRP_CNTL_DATA_IN_YUV422 (1 << 3) 174#define PRP_CNTL_DATA_IN_RGB16 (2 << 3) 175#define PRP_CNTL_DATA_IN_RGB32 (3 << 3) 176#define PRP_CNTL_CH1_OUT_RGB8 (0 << 5) 177#define PRP_CNTL_CH1_OUT_RGB16 (1 << 5) 178#define PRP_CNTL_CH1_OUT_RGB32 (2 << 5) 179#define PRP_CNTL_CH1_OUT_YUV422 (3 << 5) 180#define PRP_CNTL_CH2_OUT_YUV420 (0 << 7) 181#define PRP_CNTL_CH2_OUT_YUV422 (1 << 7) 182#define PRP_CNTL_CH2_OUT_YUV444 (2 << 7) 183#define PRP_CNTL_CH1_LEN (1 << 9) 184#define PRP_CNTL_CH2_LEN (1 << 10) 185#define PRP_CNTL_SKIP_FRAME (1 << 11) 186#define PRP_CNTL_SWRST (1 << 12) 187#define PRP_CNTL_CLKEN (1 << 13) 188#define PRP_CNTL_WEN (1 << 14) 189#define PRP_CNTL_CH1BYP (1 << 15) 190#define PRP_CNTL_IN_TSKIP(x) ((x) << 16) 191#define PRP_CNTL_CH1_TSKIP(x) ((x) << 19) 192#define PRP_CNTL_CH2_TSKIP(x) ((x) << 22) 193#define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25) 194#define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27) 195#define PRP_CNTL_CH2B1EN (1 << 29) 196#define PRP_CNTL_CH2B2EN (1 << 30) 197#define PRP_CNTL_CH2FEN (1 << 31) 198 199/* IRQ Enable and status register */ 200#define PRP_INTR_RDERR (1 << 0) 201#define PRP_INTR_CH1WERR (1 << 1) 202#define PRP_INTR_CH2WERR (1 << 2) 203#define PRP_INTR_CH1FC (1 << 3) 204#define PRP_INTR_CH2FC (1 << 5) 205#define PRP_INTR_LBOVF (1 << 7) 206#define PRP_INTR_CH2OVF (1 << 8) 207 208/* Resizing registers */ 209#define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24) 210#define PRP_RZ_VALID_BILINEAR (1 << 31) 211 212#define MAX_VIDEO_MEM 16 213 214#define RESIZE_NUM_MIN 1 215#define RESIZE_NUM_MAX 20 216#define BC_COEF 3 217#define SZ_COEF (1 << BC_COEF) 218 219#define RESIZE_DIR_H 0 220#define RESIZE_DIR_V 1 221 222#define RESIZE_ALGO_BILINEAR 0 223#define RESIZE_ALGO_AVERAGING 1 224 225struct mx2_prp_cfg { 226 int channel; 227 u32 in_fmt; 228 u32 out_fmt; 229 u32 src_pixel; 230 u32 ch1_pixel; 231 u32 irq_flags; 232}; 233 234/* prp resizing parameters */ 235struct emma_prp_resize { 236 int algo; /* type of algorithm used */ 237 int len; /* number of coefficients */ 238 unsigned char s[RESIZE_NUM_MAX]; /* table of coefficients */ 239}; 240 241/* prp configuration for a client-host fmt pair */ 242struct mx2_fmt_cfg { 243 enum v4l2_mbus_pixelcode in_fmt; 244 u32 out_fmt; 245 struct mx2_prp_cfg cfg; 246}; 247 248enum mx2_buffer_state { 249 MX2_STATE_QUEUED, 250 MX2_STATE_ACTIVE, 251 MX2_STATE_DONE, 252}; 253 254struct mx2_buf_internal { 255 struct list_head queue; 256 int bufnum; 257 bool discard; 258}; 259 260/* buffer for one video frame */ 261struct mx2_buffer { 262 /* common v4l buffer stuff -- must be first */ 263 struct vb2_buffer vb; 264 enum mx2_buffer_state state; 265 struct mx2_buf_internal internal; 266}; 267 268struct mx2_camera_dev { 269 struct device *dev; 270 struct soc_camera_host soc_host; 271 struct soc_camera_device *icd; 272 struct clk *clk_csi, *clk_emma; 273 274 unsigned int irq_csi, irq_emma; 275 void __iomem *base_csi, *base_emma; 276 unsigned long base_dma; 277 278 struct mx2_camera_platform_data *pdata; 279 struct resource *res_csi, *res_emma; 280 unsigned long platform_flags; 281 282 struct list_head capture; 283 struct list_head active_bufs; 284 struct list_head discard; 285 286 spinlock_t lock; 287 288 int dma; 289 struct mx2_buffer *active; 290 struct mx2_buffer *fb1_active; 291 struct mx2_buffer *fb2_active; 292 293 u32 csicr1; 294 295 struct mx2_buf_internal buf_discard[2]; 296 void *discard_buffer; 297 dma_addr_t discard_buffer_dma; 298 size_t discard_size; 299 struct mx2_fmt_cfg *emma_prp; 300 struct emma_prp_resize resizing[2]; 301 unsigned int s_width, s_height; 302 u32 frame_count; 303 struct vb2_alloc_ctx *alloc_ctx; 304}; 305 306static struct mx2_buffer *mx2_ibuf_to_buf(struct mx2_buf_internal *int_buf) 307{ 308 return container_of(int_buf, struct mx2_buffer, internal); 309} 310 311static struct mx2_fmt_cfg mx27_emma_prp_table[] = { 312 /* 313 * This is a generic configuration which is valid for most 314 * prp input-output format combinations. 315 * We set the incomming and outgoing pixelformat to a 316 * 16 Bit wide format and adjust the bytesperline 317 * accordingly. With this configuration the inputdata 318 * will not be changed by the emma and could be any type 319 * of 16 Bit Pixelformat. 320 */ 321 { 322 .in_fmt = 0, 323 .out_fmt = 0, 324 .cfg = { 325 .channel = 1, 326 .in_fmt = PRP_CNTL_DATA_IN_RGB16, 327 .out_fmt = PRP_CNTL_CH1_OUT_RGB16, 328 .src_pixel = 0x2ca00565, /* RGB565 */ 329 .ch1_pixel = 0x2ca00565, /* RGB565 */ 330 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR | 331 PRP_INTR_CH1FC | PRP_INTR_LBOVF, 332 } 333 }, 334 { 335 .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8, 336 .out_fmt = V4L2_PIX_FMT_YUV420, 337 .cfg = { 338 .channel = 2, 339 .in_fmt = PRP_CNTL_DATA_IN_YUV422, 340 .out_fmt = PRP_CNTL_CH2_OUT_YUV420, 341 .src_pixel = 0x22000888, /* YUV422 (YUYV) */ 342 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR | 343 PRP_INTR_CH2FC | PRP_INTR_LBOVF | 344 PRP_INTR_CH2OVF, 345 } 346 }, 347}; 348 349static struct mx2_fmt_cfg *mx27_emma_prp_get_format( 350 enum v4l2_mbus_pixelcode in_fmt, 351 u32 out_fmt) 352{ 353 int i; 354 355 for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++) 356 if ((mx27_emma_prp_table[i].in_fmt == in_fmt) && 357 (mx27_emma_prp_table[i].out_fmt == out_fmt)) { 358 return &mx27_emma_prp_table[i]; 359 } 360 /* If no match return the most generic configuration */ 361 return &mx27_emma_prp_table[0]; 362}; 363 364static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev, 365 unsigned long phys, int bufnum) 366{ 367 struct mx2_fmt_cfg *prp = pcdev->emma_prp; 368 369 if (prp->cfg.channel == 1) { 370 writel(phys, pcdev->base_emma + 371 PRP_DEST_RGB1_PTR + 4 * bufnum); 372 } else { 373 writel(phys, pcdev->base_emma + 374 PRP_DEST_Y_PTR - 0x14 * bufnum); 375 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) { 376 u32 imgsize = pcdev->icd->user_height * 377 pcdev->icd->user_width; 378 379 writel(phys + imgsize, pcdev->base_emma + 380 PRP_DEST_CB_PTR - 0x14 * bufnum); 381 writel(phys + ((5 * imgsize) / 4), pcdev->base_emma + 382 PRP_DEST_CR_PTR - 0x14 * bufnum); 383 } 384 } 385} 386 387static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev) 388{ 389 unsigned long flags; 390 391 clk_disable(pcdev->clk_csi); 392 writel(0, pcdev->base_csi + CSICR1); 393 if (cpu_is_mx27()) { 394 writel(0, pcdev->base_emma + PRP_CNTL); 395 } else if (cpu_is_mx25()) { 396 spin_lock_irqsave(&pcdev->lock, flags); 397 pcdev->fb1_active = NULL; 398 pcdev->fb2_active = NULL; 399 writel(0, pcdev->base_csi + CSIDMASA_FB1); 400 writel(0, pcdev->base_csi + CSIDMASA_FB2); 401 spin_unlock_irqrestore(&pcdev->lock, flags); 402 } 403} 404 405/* 406 * The following two functions absolutely depend on the fact, that 407 * there can be only one camera on mx2 camera sensor interface 408 */ 409static int mx2_camera_add_device(struct soc_camera_device *icd) 410{ 411 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 412 struct mx2_camera_dev *pcdev = ici->priv; 413 int ret; 414 u32 csicr1; 415 416 if (pcdev->icd) 417 return -EBUSY; 418 419 ret = clk_enable(pcdev->clk_csi); 420 if (ret < 0) 421 return ret; 422 423 csicr1 = CSICR1_MCLKEN; 424 425 if (cpu_is_mx27()) { 426 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC | 427 CSICR1_RXFF_LEVEL(0); 428 } else if (cpu_is_mx27()) 429 csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2); 430 431 pcdev->csicr1 = csicr1; 432 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 433 434 pcdev->icd = icd; 435 pcdev->frame_count = 0; 436 437 dev_info(icd->parent, "Camera driver attached to camera %d\n", 438 icd->devnum); 439 440 return 0; 441} 442 443static void mx2_camera_remove_device(struct soc_camera_device *icd) 444{ 445 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 446 struct mx2_camera_dev *pcdev = ici->priv; 447 448 BUG_ON(icd != pcdev->icd); 449 450 dev_info(icd->parent, "Camera driver detached from camera %d\n", 451 icd->devnum); 452 453 mx2_camera_deactivate(pcdev); 454 455 pcdev->icd = NULL; 456} 457 458static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb, 459 int state) 460{ 461 struct vb2_buffer *vb; 462 struct mx2_buffer *buf; 463 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active : 464 &pcdev->fb2_active; 465 u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2; 466 unsigned long flags; 467 468 spin_lock_irqsave(&pcdev->lock, flags); 469 470 if (*fb_active == NULL) 471 goto out; 472 473 vb = &(*fb_active)->vb; 474 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, 475 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0)); 476 477 do_gettimeofday(&vb->v4l2_buf.timestamp); 478 vb->v4l2_buf.sequence++; 479 vb2_buffer_done(vb, VB2_BUF_STATE_DONE); 480 481 if (list_empty(&pcdev->capture)) { 482 buf = NULL; 483 writel(0, pcdev->base_csi + fb_reg); 484 } else { 485 buf = list_first_entry(&pcdev->capture, struct mx2_buffer, 486 internal.queue); 487 vb = &buf->vb; 488 list_del(&buf->internal.queue); 489 buf->state = MX2_STATE_ACTIVE; 490 writel(vb2_dma_contig_plane_dma_addr(vb, 0), 491 pcdev->base_csi + fb_reg); 492 } 493 494 *fb_active = buf; 495 496out: 497 spin_unlock_irqrestore(&pcdev->lock, flags); 498} 499 500static irqreturn_t mx25_camera_irq(int irq_csi, void *data) 501{ 502 struct mx2_camera_dev *pcdev = data; 503 u32 status = readl(pcdev->base_csi + CSISR); 504 505 if (status & CSISR_DMA_TSF_FB1_INT) 506 mx25_camera_frame_done(pcdev, 1, MX2_STATE_DONE); 507 else if (status & CSISR_DMA_TSF_FB2_INT) 508 mx25_camera_frame_done(pcdev, 2, MX2_STATE_DONE); 509 510 /* FIXME: handle CSISR_RFF_OR_INT */ 511 512 writel(status, pcdev->base_csi + CSISR); 513 514 return IRQ_HANDLED; 515} 516 517/* 518 * Videobuf operations 519 */ 520static int mx2_videobuf_setup(struct vb2_queue *vq, 521 const struct v4l2_format *fmt, 522 unsigned int *count, unsigned int *num_planes, 523 unsigned int sizes[], void *alloc_ctxs[]) 524{ 525 struct soc_camera_device *icd = soc_camera_from_vb2q(vq); 526 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 527 struct mx2_camera_dev *pcdev = ici->priv; 528 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, 529 icd->current_fmt->host_fmt); 530 531 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]); 532 533 /* TODO: support for VIDIOC_CREATE_BUFS not ready */ 534 if (fmt != NULL) 535 return -ENOTTY; 536 537 if (bytes_per_line < 0) 538 return bytes_per_line; 539 540 alloc_ctxs[0] = pcdev->alloc_ctx; 541 542 sizes[0] = bytes_per_line * icd->user_height; 543 544 if (0 == *count) 545 *count = 32; 546 if (!*num_planes && 547 sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024) 548 *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0]; 549 550 *num_planes = 1; 551 552 return 0; 553} 554 555static int mx2_videobuf_prepare(struct vb2_buffer *vb) 556{ 557 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); 558 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, 559 icd->current_fmt->host_fmt); 560 int ret = 0; 561 562 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__, 563 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0)); 564 565 if (bytes_per_line < 0) 566 return bytes_per_line; 567 568#ifdef DEBUG 569 /* 570 * This can be useful if you want to see if we actually fill 571 * the buffer with something 572 */ 573 memset((void *)vb2_plane_vaddr(vb, 0), 574 0xaa, vb2_get_plane_payload(vb, 0)); 575#endif 576 577 vb2_set_plane_payload(vb, 0, bytes_per_line * icd->user_height); 578 if (vb2_plane_vaddr(vb, 0) && 579 vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) { 580 ret = -EINVAL; 581 goto out; 582 } 583 584 return 0; 585 586out: 587 return ret; 588} 589 590static void mx2_videobuf_queue(struct vb2_buffer *vb) 591{ 592 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); 593 struct soc_camera_host *ici = 594 to_soc_camera_host(icd->parent); 595 struct mx2_camera_dev *pcdev = ici->priv; 596 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 597 unsigned long flags; 598 599 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__, 600 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0)); 601 602 spin_lock_irqsave(&pcdev->lock, flags); 603 604 buf->state = MX2_STATE_QUEUED; 605 list_add_tail(&buf->internal.queue, &pcdev->capture); 606 607 if (cpu_is_mx25()) { 608 u32 csicr3, dma_inten = 0; 609 610 if (pcdev->fb1_active == NULL) { 611 writel(vb2_dma_contig_plane_dma_addr(vb, 0), 612 pcdev->base_csi + CSIDMASA_FB1); 613 pcdev->fb1_active = buf; 614 dma_inten = CSICR1_FB1_DMA_INTEN; 615 } else if (pcdev->fb2_active == NULL) { 616 writel(vb2_dma_contig_plane_dma_addr(vb, 0), 617 pcdev->base_csi + CSIDMASA_FB2); 618 pcdev->fb2_active = buf; 619 dma_inten = CSICR1_FB2_DMA_INTEN; 620 } 621 622 if (dma_inten) { 623 list_del(&buf->internal.queue); 624 buf->state = MX2_STATE_ACTIVE; 625 626 csicr3 = readl(pcdev->base_csi + CSICR3); 627 628 /* Reflash DMA */ 629 writel(csicr3 | CSICR3_DMA_REFLASH_RFF, 630 pcdev->base_csi + CSICR3); 631 632 /* clear & enable interrupts */ 633 writel(dma_inten, pcdev->base_csi + CSISR); 634 pcdev->csicr1 |= dma_inten; 635 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 636 637 /* enable DMA */ 638 csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1); 639 writel(csicr3, pcdev->base_csi + CSICR3); 640 } 641 } 642 643 spin_unlock_irqrestore(&pcdev->lock, flags); 644} 645 646static void mx2_videobuf_release(struct vb2_buffer *vb) 647{ 648 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); 649 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 650 struct mx2_camera_dev *pcdev = ici->priv; 651 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 652 unsigned long flags; 653 654#ifdef DEBUG 655 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__, 656 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0)); 657 658 switch (buf->state) { 659 case MX2_STATE_ACTIVE: 660 dev_info(icd->parent, "%s (active)\n", __func__); 661 break; 662 case MX2_STATE_QUEUED: 663 dev_info(icd->parent, "%s (queued)\n", __func__); 664 break; 665 default: 666 dev_info(icd->parent, "%s (unknown) %d\n", __func__, 667 buf->state); 668 break; 669 } 670#endif 671 672 /* 673 * Terminate only queued but inactive buffers. Active buffers are 674 * released when they become inactive after videobuf_waiton(). 675 * 676 * FIXME: implement forced termination of active buffers for mx27 and 677 * mx27 eMMA, so that the user won't get stuck in an uninterruptible 678 * state. This requires a specific handling for each of the these DMA 679 * types. 680 */ 681 682 spin_lock_irqsave(&pcdev->lock, flags); 683 if (cpu_is_mx25() && buf->state == MX2_STATE_ACTIVE) { 684 if (pcdev->fb1_active == buf) { 685 pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN; 686 writel(0, pcdev->base_csi + CSIDMASA_FB1); 687 pcdev->fb1_active = NULL; 688 } else if (pcdev->fb2_active == buf) { 689 pcdev->csicr1 &= ~CSICR1_FB2_DMA_INTEN; 690 writel(0, pcdev->base_csi + CSIDMASA_FB2); 691 pcdev->fb2_active = NULL; 692 } 693 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 694 } 695 spin_unlock_irqrestore(&pcdev->lock, flags); 696} 697 698static void mx27_camera_emma_buf_init(struct soc_camera_device *icd, 699 int bytesperline) 700{ 701 struct soc_camera_host *ici = 702 to_soc_camera_host(icd->parent); 703 struct mx2_camera_dev *pcdev = ici->priv; 704 struct mx2_fmt_cfg *prp = pcdev->emma_prp; 705 706 writel((pcdev->s_width << 16) | pcdev->s_height, 707 pcdev->base_emma + PRP_SRC_FRAME_SIZE); 708 writel(prp->cfg.src_pixel, 709 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL); 710 if (prp->cfg.channel == 1) { 711 writel((icd->user_width << 16) | icd->user_height, 712 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE); 713 writel(bytesperline, 714 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE); 715 writel(prp->cfg.ch1_pixel, 716 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL); 717 } else { /* channel 2 */ 718 writel((icd->user_width << 16) | icd->user_height, 719 pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE); 720 } 721 722 /* Enable interrupts */ 723 writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL); 724} 725 726static void mx2_prp_resize_commit(struct mx2_camera_dev *pcdev) 727{ 728 int dir; 729 730 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) { 731 unsigned char *s = pcdev->resizing[dir].s; 732 int len = pcdev->resizing[dir].len; 733 unsigned int coeff[2] = {0, 0}; 734 unsigned int valid = 0; 735 int i; 736 737 if (len == 0) 738 continue; 739 740 for (i = RESIZE_NUM_MAX - 1; i >= 0; i--) { 741 int j; 742 743 j = i > 9 ? 1 : 0; 744 coeff[j] = (coeff[j] << BC_COEF) | 745 (s[i] & (SZ_COEF - 1)); 746 747 if (i == 5 || i == 15) 748 coeff[j] <<= 1; 749 750 valid = (valid << 1) | (s[i] >> BC_COEF); 751 } 752 753 valid |= PRP_RZ_VALID_TBL_LEN(len); 754 755 if (pcdev->resizing[dir].algo == RESIZE_ALGO_BILINEAR) 756 valid |= PRP_RZ_VALID_BILINEAR; 757 758 if (pcdev->emma_prp->cfg.channel == 1) { 759 if (dir == RESIZE_DIR_H) { 760 writel(coeff[0], pcdev->base_emma + 761 PRP_CH1_RZ_HORI_COEF1); 762 writel(coeff[1], pcdev->base_emma + 763 PRP_CH1_RZ_HORI_COEF2); 764 writel(valid, pcdev->base_emma + 765 PRP_CH1_RZ_HORI_VALID); 766 } else { 767 writel(coeff[0], pcdev->base_emma + 768 PRP_CH1_RZ_VERT_COEF1); 769 writel(coeff[1], pcdev->base_emma + 770 PRP_CH1_RZ_VERT_COEF2); 771 writel(valid, pcdev->base_emma + 772 PRP_CH1_RZ_VERT_VALID); 773 } 774 } else { 775 if (dir == RESIZE_DIR_H) { 776 writel(coeff[0], pcdev->base_emma + 777 PRP_CH2_RZ_HORI_COEF1); 778 writel(coeff[1], pcdev->base_emma + 779 PRP_CH2_RZ_HORI_COEF2); 780 writel(valid, pcdev->base_emma + 781 PRP_CH2_RZ_HORI_VALID); 782 } else { 783 writel(coeff[0], pcdev->base_emma + 784 PRP_CH2_RZ_VERT_COEF1); 785 writel(coeff[1], pcdev->base_emma + 786 PRP_CH2_RZ_VERT_COEF2); 787 writel(valid, pcdev->base_emma + 788 PRP_CH2_RZ_VERT_VALID); 789 } 790 } 791 } 792} 793 794static int mx2_start_streaming(struct vb2_queue *q, unsigned int count) 795{ 796 struct soc_camera_device *icd = soc_camera_from_vb2q(q); 797 struct soc_camera_host *ici = 798 to_soc_camera_host(icd->parent); 799 struct mx2_camera_dev *pcdev = ici->priv; 800 struct mx2_fmt_cfg *prp = pcdev->emma_prp; 801 struct vb2_buffer *vb; 802 struct mx2_buffer *buf; 803 unsigned long phys; 804 int bytesperline; 805 806 if (cpu_is_mx27()) { 807 unsigned long flags; 808 if (count < 2) 809 return -EINVAL; 810 811 spin_lock_irqsave(&pcdev->lock, flags); 812 813 buf = list_first_entry(&pcdev->capture, struct mx2_buffer, 814 internal.queue); 815 buf->internal.bufnum = 0; 816 vb = &buf->vb; 817 buf->state = MX2_STATE_ACTIVE; 818 819 phys = vb2_dma_contig_plane_dma_addr(vb, 0); 820 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum); 821 list_move_tail(pcdev->capture.next, &pcdev->active_bufs); 822 823 buf = list_first_entry(&pcdev->capture, struct mx2_buffer, 824 internal.queue); 825 buf->internal.bufnum = 1; 826 vb = &buf->vb; 827 buf->state = MX2_STATE_ACTIVE; 828 829 phys = vb2_dma_contig_plane_dma_addr(vb, 0); 830 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum); 831 list_move_tail(pcdev->capture.next, &pcdev->active_bufs); 832 833 bytesperline = soc_mbus_bytes_per_line(icd->user_width, 834 icd->current_fmt->host_fmt); 835 if (bytesperline < 0) 836 return bytesperline; 837 838 /* 839 * I didn't manage to properly enable/disable the prp 840 * on a per frame basis during running transfers, 841 * thus we allocate a buffer here and use it to 842 * discard frames when no buffer is available. 843 * Feel free to work on this ;) 844 */ 845 pcdev->discard_size = icd->user_height * bytesperline; 846 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev, 847 pcdev->discard_size, &pcdev->discard_buffer_dma, 848 GFP_KERNEL); 849 if (!pcdev->discard_buffer) 850 return -ENOMEM; 851 852 pcdev->buf_discard[0].discard = true; 853 list_add_tail(&pcdev->buf_discard[0].queue, 854 &pcdev->discard); 855 856 pcdev->buf_discard[1].discard = true; 857 list_add_tail(&pcdev->buf_discard[1].queue, 858 &pcdev->discard); 859 860 mx2_prp_resize_commit(pcdev); 861 862 mx27_camera_emma_buf_init(icd, bytesperline); 863 864 if (prp->cfg.channel == 1) { 865 writel(PRP_CNTL_CH1EN | 866 PRP_CNTL_CSIEN | 867 prp->cfg.in_fmt | 868 prp->cfg.out_fmt | 869 PRP_CNTL_CH1_LEN | 870 PRP_CNTL_CH1BYP | 871 PRP_CNTL_CH1_TSKIP(0) | 872 PRP_CNTL_IN_TSKIP(0), 873 pcdev->base_emma + PRP_CNTL); 874 } else { 875 writel(PRP_CNTL_CH2EN | 876 PRP_CNTL_CSIEN | 877 prp->cfg.in_fmt | 878 prp->cfg.out_fmt | 879 PRP_CNTL_CH2_LEN | 880 PRP_CNTL_CH2_TSKIP(0) | 881 PRP_CNTL_IN_TSKIP(0), 882 pcdev->base_emma + PRP_CNTL); 883 } 884 spin_unlock_irqrestore(&pcdev->lock, flags); 885 } 886 887 return 0; 888} 889 890static int mx2_stop_streaming(struct vb2_queue *q) 891{ 892 struct soc_camera_device *icd = soc_camera_from_vb2q(q); 893 struct soc_camera_host *ici = 894 to_soc_camera_host(icd->parent); 895 struct mx2_camera_dev *pcdev = ici->priv; 896 struct mx2_fmt_cfg *prp = pcdev->emma_prp; 897 unsigned long flags; 898 void *b; 899 u32 cntl; 900 901 if (cpu_is_mx27()) { 902 spin_lock_irqsave(&pcdev->lock, flags); 903 904 cntl = readl(pcdev->base_emma + PRP_CNTL); 905 if (prp->cfg.channel == 1) { 906 writel(cntl & ~PRP_CNTL_CH1EN, 907 pcdev->base_emma + PRP_CNTL); 908 } else { 909 writel(cntl & ~PRP_CNTL_CH2EN, 910 pcdev->base_emma + PRP_CNTL); 911 } 912 INIT_LIST_HEAD(&pcdev->capture); 913 INIT_LIST_HEAD(&pcdev->active_bufs); 914 INIT_LIST_HEAD(&pcdev->discard); 915 916 b = pcdev->discard_buffer; 917 pcdev->discard_buffer = NULL; 918 919 spin_unlock_irqrestore(&pcdev->lock, flags); 920 921 dma_free_coherent(ici->v4l2_dev.dev, 922 pcdev->discard_size, b, pcdev->discard_buffer_dma); 923 } 924 925 return 0; 926} 927 928static struct vb2_ops mx2_videobuf_ops = { 929 .queue_setup = mx2_videobuf_setup, 930 .buf_prepare = mx2_videobuf_prepare, 931 .buf_queue = mx2_videobuf_queue, 932 .buf_cleanup = mx2_videobuf_release, 933 .start_streaming = mx2_start_streaming, 934 .stop_streaming = mx2_stop_streaming, 935}; 936 937static int mx2_camera_init_videobuf(struct vb2_queue *q, 938 struct soc_camera_device *icd) 939{ 940 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 941 q->io_modes = VB2_MMAP | VB2_USERPTR; 942 q->drv_priv = icd; 943 q->ops = &mx2_videobuf_ops; 944 q->mem_ops = &vb2_dma_contig_memops; 945 q->buf_struct_size = sizeof(struct mx2_buffer); 946 947 return vb2_queue_init(q); 948} 949 950#define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \ 951 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \ 952 V4L2_MBUS_VSYNC_ACTIVE_LOW | \ 953 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \ 954 V4L2_MBUS_HSYNC_ACTIVE_LOW | \ 955 V4L2_MBUS_PCLK_SAMPLE_RISING | \ 956 V4L2_MBUS_PCLK_SAMPLE_FALLING | \ 957 V4L2_MBUS_DATA_ACTIVE_HIGH | \ 958 V4L2_MBUS_DATA_ACTIVE_LOW) 959 960static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev) 961{ 962 u32 cntl; 963 int count = 0; 964 965 cntl = readl(pcdev->base_emma + PRP_CNTL); 966 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL); 967 while (count++ < 100) { 968 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST)) 969 return 0; 970 barrier(); 971 udelay(1); 972 } 973 974 return -ETIMEDOUT; 975} 976 977static int mx2_camera_set_bus_param(struct soc_camera_device *icd) 978{ 979 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 980 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 981 struct mx2_camera_dev *pcdev = ici->priv; 982 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; 983 unsigned long common_flags; 984 int ret; 985 int bytesperline; 986 u32 csicr1 = pcdev->csicr1; 987 988 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); 989 if (!ret) { 990 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS); 991 if (!common_flags) { 992 dev_warn(icd->parent, 993 "Flags incompatible: camera 0x%x, host 0x%x\n", 994 cfg.flags, MX2_BUS_FLAGS); 995 return -EINVAL; 996 } 997 } else if (ret != -ENOIOCTLCMD) { 998 return ret; 999 } else { 1000 common_flags = MX2_BUS_FLAGS; 1001 } 1002 1003 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) && 1004 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) { 1005 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH) 1006 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW; 1007 else 1008 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH; 1009 } 1010 1011 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) && 1012 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) { 1013 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING) 1014 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING; 1015 else 1016 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING; 1017 } 1018 1019 cfg.flags = common_flags; 1020 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg); 1021 if (ret < 0 && ret != -ENOIOCTLCMD) { 1022 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n", 1023 common_flags, ret); 1024 return ret; 1025 } 1026 1027 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 1028 csicr1 |= CSICR1_REDGE; 1029 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 1030 csicr1 |= CSICR1_SOF_POL; 1031 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) 1032 csicr1 |= CSICR1_HSYNC_POL; 1033 if (pcdev->platform_flags & MX2_CAMERA_SWAP16) 1034 csicr1 |= CSICR1_SWAP16_EN; 1035 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC) 1036 csicr1 |= CSICR1_EXT_VSYNC; 1037 if (pcdev->platform_flags & MX2_CAMERA_CCIR) 1038 csicr1 |= CSICR1_CCIR_EN; 1039 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE) 1040 csicr1 |= CSICR1_CCIR_MODE; 1041 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK) 1042 csicr1 |= CSICR1_GCLK_MODE; 1043 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA) 1044 csicr1 |= CSICR1_INV_DATA; 1045 if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB) 1046 csicr1 |= CSICR1_PACK_DIR; 1047 1048 pcdev->csicr1 = csicr1; 1049 1050 bytesperline = soc_mbus_bytes_per_line(icd->user_width, 1051 icd->current_fmt->host_fmt); 1052 if (bytesperline < 0) 1053 return bytesperline; 1054 1055 if (cpu_is_mx27()) { 1056 ret = mx27_camera_emma_prp_reset(pcdev); 1057 if (ret) 1058 return ret; 1059 } else if (cpu_is_mx25()) { 1060 writel((bytesperline * icd->user_height) >> 2, 1061 pcdev->base_csi + CSIRXCNT); 1062 writel((bytesperline << 16) | icd->user_height, 1063 pcdev->base_csi + CSIIMAG_PARA); 1064 } 1065 1066 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 1067 1068 return 0; 1069} 1070 1071static int mx2_camera_set_crop(struct soc_camera_device *icd, 1072 struct v4l2_crop *a) 1073{ 1074 struct v4l2_rect *rect = &a->c; 1075 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1076 struct v4l2_mbus_framefmt mf; 1077 int ret; 1078 1079 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096); 1080 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096); 1081 1082 ret = v4l2_subdev_call(sd, video, s_crop, a); 1083 if (ret < 0) 1084 return ret; 1085 1086 /* The capture device might have changed its output */ 1087 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); 1088 if (ret < 0) 1089 return ret; 1090 1091 dev_dbg(icd->parent, "Sensor cropped %dx%d\n", 1092 mf.width, mf.height); 1093 1094 icd->user_width = mf.width; 1095 icd->user_height = mf.height; 1096 1097 return ret; 1098} 1099 1100static int mx2_camera_get_formats(struct soc_camera_device *icd, 1101 unsigned int idx, 1102 struct soc_camera_format_xlate *xlate) 1103{ 1104 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1105 const struct soc_mbus_pixelfmt *fmt; 1106 struct device *dev = icd->parent; 1107 enum v4l2_mbus_pixelcode code; 1108 int ret, formats = 0; 1109 1110 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code); 1111 if (ret < 0) 1112 /* no more formats */ 1113 return 0; 1114 1115 fmt = soc_mbus_get_fmtdesc(code); 1116 if (!fmt) { 1117 dev_err(dev, "Invalid format code #%u: %d\n", idx, code); 1118 return 0; 1119 } 1120 1121 if (code == V4L2_MBUS_FMT_YUYV8_2X8) { 1122 formats++; 1123 if (xlate) { 1124 /* 1125 * CH2 can output YUV420 which is a standard format in 1126 * soc_mediabus.c 1127 */ 1128 xlate->host_fmt = 1129 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8); 1130 xlate->code = code; 1131 dev_dbg(dev, "Providing host format %s for sensor code %d\n", 1132 xlate->host_fmt->name, code); 1133 xlate++; 1134 } 1135 } 1136 1137 /* Generic pass-trough */ 1138 formats++; 1139 if (xlate) { 1140 xlate->host_fmt = fmt; 1141 xlate->code = code; 1142 xlate++; 1143 } 1144 return formats; 1145} 1146 1147static int mx2_emmaprp_resize(struct mx2_camera_dev *pcdev, 1148 struct v4l2_mbus_framefmt *mf_in, 1149 struct v4l2_pix_format *pix_out, bool apply) 1150{ 1151 int num, den; 1152 unsigned long m; 1153 int i, dir; 1154 1155 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) { 1156 struct emma_prp_resize tmprsz; 1157 unsigned char *s = tmprsz.s; 1158 int len = 0; 1159 int in, out; 1160 1161 if (dir == RESIZE_DIR_H) { 1162 in = mf_in->width; 1163 out = pix_out->width; 1164 } else { 1165 in = mf_in->height; 1166 out = pix_out->height; 1167 } 1168 1169 if (in < out) 1170 return -EINVAL; 1171 else if (in == out) 1172 continue; 1173 1174 /* Calculate ratio */ 1175 m = gcd(in, out); 1176 num = in / m; 1177 den = out / m; 1178 if (num > RESIZE_NUM_MAX) 1179 return -EINVAL; 1180 1181 if ((num >= 2 * den) && (den == 1) && 1182 (num < 9) && (!(num & 0x01))) { 1183 int sum = 0; 1184 int j; 1185 1186 /* Average scaling for >= 2:1 ratios */ 1187 /* Support can be added for num >=9 and odd values */ 1188 1189 tmprsz.algo = RESIZE_ALGO_AVERAGING; 1190 len = num; 1191 1192 for (i = 0; i < (len / 2); i++) 1193 s[i] = 8; 1194 1195 do { 1196 for (i = 0; i < (len / 2); i++) { 1197 s[i] = s[i] >> 1; 1198 sum = 0; 1199 for (j = 0; j < (len / 2); j++) 1200 sum += s[j]; 1201 if (sum == 4) 1202 break; 1203 } 1204 } while (sum != 4); 1205 1206 for (i = (len / 2); i < len; i++) 1207 s[i] = s[len - i - 1]; 1208 1209 s[len - 1] |= SZ_COEF; 1210 } else { 1211 /* bilinear scaling for < 2:1 ratios */ 1212 int v; /* overflow counter */ 1213 int coeff, nxt; /* table output */ 1214 int in_pos_inc = 2 * den; 1215 int out_pos = num; 1216 int out_pos_inc = 2 * num; 1217 int init_carry = num - den; 1218 int carry = init_carry; 1219 1220 tmprsz.algo = RESIZE_ALGO_BILINEAR; 1221 v = den + in_pos_inc; 1222 do { 1223 coeff = v - out_pos; 1224 out_pos += out_pos_inc; 1225 carry += out_pos_inc; 1226 for (nxt = 0; v < out_pos; nxt++) { 1227 v += in_pos_inc; 1228 carry -= in_pos_inc; 1229 } 1230 1231 if (len > RESIZE_NUM_MAX) 1232 return -EINVAL; 1233 1234 coeff = ((coeff << BC_COEF) + 1235 (in_pos_inc >> 1)) / in_pos_inc; 1236 1237 if (coeff >= (SZ_COEF - 1)) 1238 coeff--; 1239 1240 coeff |= SZ_COEF; 1241 s[len] = (unsigned char)coeff; 1242 len++; 1243 1244 for (i = 1; i < nxt; i++) { 1245 if (len >= RESIZE_NUM_MAX) 1246 return -EINVAL; 1247 s[len] = 0; 1248 len++; 1249 } 1250 } while (carry != init_carry); 1251 } 1252 tmprsz.len = len; 1253 if (dir == RESIZE_DIR_H) 1254 mf_in->width = pix_out->width; 1255 else 1256 mf_in->height = pix_out->height; 1257 1258 if (apply) 1259 memcpy(&pcdev->resizing[dir], &tmprsz, sizeof(tmprsz)); 1260 } 1261 return 0; 1262} 1263 1264static int mx2_camera_set_fmt(struct soc_camera_device *icd, 1265 struct v4l2_format *f) 1266{ 1267 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 1268 struct mx2_camera_dev *pcdev = ici->priv; 1269 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1270 const struct soc_camera_format_xlate *xlate; 1271 struct v4l2_pix_format *pix = &f->fmt.pix; 1272 struct v4l2_mbus_framefmt mf; 1273 int ret; 1274 1275 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n", 1276 __func__, pix->width, pix->height); 1277 1278 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); 1279 if (!xlate) { 1280 dev_warn(icd->parent, "Format %x not found\n", 1281 pix->pixelformat); 1282 return -EINVAL; 1283 } 1284 1285 mf.width = pix->width; 1286 mf.height = pix->height; 1287 mf.field = pix->field; 1288 mf.colorspace = pix->colorspace; 1289 mf.code = xlate->code; 1290 1291 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); 1292 if (ret < 0 && ret != -ENOIOCTLCMD) 1293 return ret; 1294 1295 /* Store width and height returned by the sensor for resizing */ 1296 pcdev->s_width = mf.width; 1297 pcdev->s_height = mf.height; 1298 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n", 1299 __func__, pcdev->s_width, pcdev->s_height); 1300 1301 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code, 1302 xlate->host_fmt->fourcc); 1303 1304 memset(pcdev->resizing, 0, sizeof(pcdev->resizing)); 1305 if ((mf.width != pix->width || mf.height != pix->height) && 1306 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) { 1307 if (mx2_emmaprp_resize(pcdev, &mf, pix, true) < 0) 1308 dev_dbg(icd->parent, "%s: can't resize\n", __func__); 1309 } 1310 1311 if (mf.code != xlate->code) 1312 return -EINVAL; 1313 1314 pix->width = mf.width; 1315 pix->height = mf.height; 1316 pix->field = mf.field; 1317 pix->colorspace = mf.colorspace; 1318 icd->current_fmt = xlate; 1319 1320 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n", 1321 __func__, pix->width, pix->height); 1322 1323 return 0; 1324} 1325 1326static int mx2_camera_try_fmt(struct soc_camera_device *icd, 1327 struct v4l2_format *f) 1328{ 1329 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1330 const struct soc_camera_format_xlate *xlate; 1331 struct v4l2_pix_format *pix = &f->fmt.pix; 1332 struct v4l2_mbus_framefmt mf; 1333 __u32 pixfmt = pix->pixelformat; 1334 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 1335 struct mx2_camera_dev *pcdev = ici->priv; 1336 unsigned int width_limit; 1337 int ret; 1338 1339 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n", 1340 __func__, pix->width, pix->height); 1341 1342 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); 1343 if (pixfmt && !xlate) { 1344 dev_warn(icd->parent, "Format %x not found\n", pixfmt); 1345 return -EINVAL; 1346 } 1347 1348 /* FIXME: implement MX27 limits */ 1349 1350 /* limit to MX25 hardware capabilities */ 1351 if (cpu_is_mx25()) { 1352 if (xlate->host_fmt->bits_per_sample <= 8) 1353 width_limit = 0xffff * 4; 1354 else 1355 width_limit = 0xffff * 2; 1356 /* CSIIMAG_PARA limit */ 1357 if (pix->width > width_limit) 1358 pix->width = width_limit; 1359 if (pix->height > 0xffff) 1360 pix->height = 0xffff; 1361 1362 pix->bytesperline = soc_mbus_bytes_per_line(pix->width, 1363 xlate->host_fmt); 1364 if (pix->bytesperline < 0) 1365 return pix->bytesperline; 1366 pix->sizeimage = pix->height * pix->bytesperline; 1367 /* Check against the CSIRXCNT limit */ 1368 if (pix->sizeimage > 4 * 0x3ffff) { 1369 /* Adjust geometry, preserve aspect ratio */ 1370 unsigned int new_height = int_sqrt(4 * 0x3ffff * 1371 pix->height / pix->bytesperline); 1372 pix->width = new_height * pix->width / pix->height; 1373 pix->height = new_height; 1374 pix->bytesperline = soc_mbus_bytes_per_line(pix->width, 1375 xlate->host_fmt); 1376 BUG_ON(pix->bytesperline < 0); 1377 } 1378 } 1379 1380 /* limit to sensor capabilities */ 1381 mf.width = pix->width; 1382 mf.height = pix->height; 1383 mf.field = pix->field; 1384 mf.colorspace = pix->colorspace; 1385 mf.code = xlate->code; 1386 1387 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); 1388 if (ret < 0) 1389 return ret; 1390 1391 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n", 1392 __func__, pcdev->s_width, pcdev->s_height); 1393 1394 /* If the sensor does not support image size try PrP resizing */ 1395 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code, 1396 xlate->host_fmt->fourcc); 1397 1398 memset(pcdev->resizing, 0, sizeof(pcdev->resizing)); 1399 if ((mf.width != pix->width || mf.height != pix->height) && 1400 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) { 1401 if (mx2_emmaprp_resize(pcdev, &mf, pix, false) < 0) 1402 dev_dbg(icd->parent, "%s: can't resize\n", __func__); 1403 } 1404 1405 if (mf.field == V4L2_FIELD_ANY) 1406 mf.field = V4L2_FIELD_NONE; 1407 /* 1408 * Driver supports interlaced images provided they have 1409 * both fields so that they can be processed as if they 1410 * were progressive. 1411 */ 1412 if (mf.field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf.field)) { 1413 dev_err(icd->parent, "Field type %d unsupported.\n", 1414 mf.field); 1415 return -EINVAL; 1416 } 1417 1418 pix->width = mf.width; 1419 pix->height = mf.height; 1420 pix->field = mf.field; 1421 pix->colorspace = mf.colorspace; 1422 1423 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n", 1424 __func__, pix->width, pix->height); 1425 1426 return 0; 1427} 1428 1429static int mx2_camera_querycap(struct soc_camera_host *ici, 1430 struct v4l2_capability *cap) 1431{ 1432 /* cap->name is set by the friendly caller:-> */ 1433 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card)); 1434 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; 1435 1436 return 0; 1437} 1438 1439static unsigned int mx2_camera_poll(struct file *file, poll_table *pt) 1440{ 1441 struct soc_camera_device *icd = file->private_data; 1442 1443 return vb2_poll(&icd->vb2_vidq, file, pt); 1444} 1445 1446static struct soc_camera_host_ops mx2_soc_camera_host_ops = { 1447 .owner = THIS_MODULE, 1448 .add = mx2_camera_add_device, 1449 .remove = mx2_camera_remove_device, 1450 .set_fmt = mx2_camera_set_fmt, 1451 .set_crop = mx2_camera_set_crop, 1452 .get_formats = mx2_camera_get_formats, 1453 .try_fmt = mx2_camera_try_fmt, 1454 .init_videobuf2 = mx2_camera_init_videobuf, 1455 .poll = mx2_camera_poll, 1456 .querycap = mx2_camera_querycap, 1457 .set_bus_param = mx2_camera_set_bus_param, 1458}; 1459 1460static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev, 1461 int bufnum, bool err) 1462{ 1463#ifdef DEBUG 1464 struct mx2_fmt_cfg *prp = pcdev->emma_prp; 1465#endif 1466 struct mx2_buf_internal *ibuf; 1467 struct mx2_buffer *buf; 1468 struct vb2_buffer *vb; 1469 unsigned long phys; 1470 1471 ibuf = list_first_entry(&pcdev->active_bufs, struct mx2_buf_internal, 1472 queue); 1473 1474 BUG_ON(ibuf->bufnum != bufnum); 1475 1476 if (ibuf->discard) { 1477 /* 1478 * Discard buffer must not be returned to user space. 1479 * Just return it to the discard queue. 1480 */ 1481 list_move_tail(pcdev->active_bufs.next, &pcdev->discard); 1482 } else { 1483 buf = mx2_ibuf_to_buf(ibuf); 1484 1485 vb = &buf->vb; 1486#ifdef DEBUG 1487 phys = vb2_dma_contig_plane_dma_addr(vb, 0); 1488 if (prp->cfg.channel == 1) { 1489 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + 1490 4 * bufnum) != phys) { 1491 dev_err(pcdev->dev, "%lx != %x\n", phys, 1492 readl(pcdev->base_emma + 1493 PRP_DEST_RGB1_PTR + 4 * bufnum)); 1494 } 1495 } else { 1496 if (readl(pcdev->base_emma + PRP_DEST_Y_PTR - 1497 0x14 * bufnum) != phys) { 1498 dev_err(pcdev->dev, "%lx != %x\n", phys, 1499 readl(pcdev->base_emma + 1500 PRP_DEST_Y_PTR - 0x14 * bufnum)); 1501 } 1502 } 1503#endif 1504 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb, 1505 vb2_plane_vaddr(vb, 0), 1506 vb2_get_plane_payload(vb, 0)); 1507 1508 list_del_init(&buf->internal.queue); 1509 do_gettimeofday(&vb->v4l2_buf.timestamp); 1510 vb->v4l2_buf.sequence = pcdev->frame_count; 1511 if (err) 1512 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); 1513 else 1514 vb2_buffer_done(vb, VB2_BUF_STATE_DONE); 1515 } 1516 1517 pcdev->frame_count++; 1518 1519 if (list_empty(&pcdev->capture)) { 1520 if (list_empty(&pcdev->discard)) { 1521 dev_warn(pcdev->dev, "%s: trying to access empty discard list\n", 1522 __func__); 1523 return; 1524 } 1525 1526 ibuf = list_first_entry(&pcdev->discard, 1527 struct mx2_buf_internal, queue); 1528 ibuf->bufnum = bufnum; 1529 1530 list_move_tail(pcdev->discard.next, &pcdev->active_bufs); 1531 mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum); 1532 return; 1533 } 1534 1535 buf = list_first_entry(&pcdev->capture, struct mx2_buffer, 1536 internal.queue); 1537 1538 buf->internal.bufnum = bufnum; 1539 1540 list_move_tail(pcdev->capture.next, &pcdev->active_bufs); 1541 1542 vb = &buf->vb; 1543 buf->state = MX2_STATE_ACTIVE; 1544 1545 phys = vb2_dma_contig_plane_dma_addr(vb, 0); 1546 mx27_update_emma_buf(pcdev, phys, bufnum); 1547} 1548 1549static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data) 1550{ 1551 struct mx2_camera_dev *pcdev = data; 1552 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS); 1553 struct mx2_buf_internal *ibuf; 1554 1555 spin_lock(&pcdev->lock); 1556 1557 if (list_empty(&pcdev->active_bufs)) { 1558 dev_warn(pcdev->dev, "%s: called while active list is empty\n", 1559 __func__); 1560 1561 if (!status) { 1562 spin_unlock(&pcdev->lock); 1563 return IRQ_NONE; 1564 } 1565 } 1566 1567 if (status & (1 << 7)) { /* overflow */ 1568 u32 cntl = readl(pcdev->base_emma + PRP_CNTL); 1569 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN), 1570 pcdev->base_emma + PRP_CNTL); 1571 writel(cntl, pcdev->base_emma + PRP_CNTL); 1572 1573 ibuf = list_first_entry(&pcdev->active_bufs, 1574 struct mx2_buf_internal, queue); 1575 mx27_camera_frame_done_emma(pcdev, 1576 ibuf->bufnum, true); 1577 1578 status &= ~(1 << 7); 1579 } else if (((status & (3 << 5)) == (3 << 5)) || 1580 ((status & (3 << 3)) == (3 << 3))) { 1581 /* 1582 * Both buffers have triggered, process the one we're expecting 1583 * to first 1584 */ 1585 ibuf = list_first_entry(&pcdev->active_bufs, 1586 struct mx2_buf_internal, queue); 1587 mx27_camera_frame_done_emma(pcdev, ibuf->bufnum, false); 1588 status &= ~(1 << (6 - ibuf->bufnum)); /* mark processed */ 1589 } else if ((status & (1 << 6)) || (status & (1 << 4))) { 1590 mx27_camera_frame_done_emma(pcdev, 0, false); 1591 } else if ((status & (1 << 5)) || (status & (1 << 3))) { 1592 mx27_camera_frame_done_emma(pcdev, 1, false); 1593 } 1594 1595 spin_unlock(&pcdev->lock); 1596 writel(status, pcdev->base_emma + PRP_INTRSTATUS); 1597 1598 return IRQ_HANDLED; 1599} 1600 1601static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev) 1602{ 1603 struct resource *res_emma = pcdev->res_emma; 1604 int err = 0; 1605 1606 if (!request_mem_region(res_emma->start, resource_size(res_emma), 1607 MX2_CAM_DRV_NAME)) { 1608 err = -EBUSY; 1609 goto out; 1610 } 1611 1612 pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma)); 1613 if (!pcdev->base_emma) { 1614 err = -ENOMEM; 1615 goto exit_release; 1616 } 1617 1618 err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0, 1619 MX2_CAM_DRV_NAME, pcdev); 1620 if (err) { 1621 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n"); 1622 goto exit_iounmap; 1623 } 1624 1625 pcdev->clk_emma = clk_get(NULL, "emma"); 1626 if (IS_ERR(pcdev->clk_emma)) { 1627 err = PTR_ERR(pcdev->clk_emma); 1628 goto exit_free_irq; 1629 } 1630 1631 clk_enable(pcdev->clk_emma); 1632 1633 err = mx27_camera_emma_prp_reset(pcdev); 1634 if (err) 1635 goto exit_clk_emma_put; 1636 1637 return err; 1638 1639exit_clk_emma_put: 1640 clk_disable(pcdev->clk_emma); 1641 clk_put(pcdev->clk_emma); 1642exit_free_irq: 1643 free_irq(pcdev->irq_emma, pcdev); 1644exit_iounmap: 1645 iounmap(pcdev->base_emma); 1646exit_release: 1647 release_mem_region(res_emma->start, resource_size(res_emma)); 1648out: 1649 return err; 1650} 1651 1652static int __devinit mx2_camera_probe(struct platform_device *pdev) 1653{ 1654 struct mx2_camera_dev *pcdev; 1655 struct resource *res_csi, *res_emma; 1656 void __iomem *base_csi; 1657 int irq_csi, irq_emma; 1658 int err = 0; 1659 1660 dev_dbg(&pdev->dev, "initialising\n"); 1661 1662 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1663 irq_csi = platform_get_irq(pdev, 0); 1664 if (res_csi == NULL || irq_csi < 0) { 1665 dev_err(&pdev->dev, "Missing platform resources data\n"); 1666 err = -ENODEV; 1667 goto exit; 1668 } 1669 1670 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); 1671 if (!pcdev) { 1672 dev_err(&pdev->dev, "Could not allocate pcdev\n"); 1673 err = -ENOMEM; 1674 goto exit; 1675 } 1676 1677 pcdev->clk_csi = clk_get(&pdev->dev, NULL); 1678 if (IS_ERR(pcdev->clk_csi)) { 1679 dev_err(&pdev->dev, "Could not get csi clock\n"); 1680 err = PTR_ERR(pcdev->clk_csi); 1681 goto exit_kfree; 1682 } 1683 1684 pcdev->res_csi = res_csi; 1685 pcdev->pdata = pdev->dev.platform_data; 1686 if (pcdev->pdata) { 1687 long rate; 1688 1689 pcdev->platform_flags = pcdev->pdata->flags; 1690 1691 rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2); 1692 if (rate <= 0) { 1693 err = -ENODEV; 1694 goto exit_dma_free; 1695 } 1696 err = clk_set_rate(pcdev->clk_csi, rate); 1697 if (err < 0) 1698 goto exit_dma_free; 1699 } 1700 1701 INIT_LIST_HEAD(&pcdev->capture); 1702 INIT_LIST_HEAD(&pcdev->active_bufs); 1703 INIT_LIST_HEAD(&pcdev->discard); 1704 spin_lock_init(&pcdev->lock); 1705 1706 /* 1707 * Request the regions. 1708 */ 1709 if (!request_mem_region(res_csi->start, resource_size(res_csi), 1710 MX2_CAM_DRV_NAME)) { 1711 err = -EBUSY; 1712 goto exit_dma_free; 1713 } 1714 1715 base_csi = ioremap(res_csi->start, resource_size(res_csi)); 1716 if (!base_csi) { 1717 err = -ENOMEM; 1718 goto exit_release; 1719 } 1720 pcdev->irq_csi = irq_csi; 1721 pcdev->base_csi = base_csi; 1722 pcdev->base_dma = res_csi->start; 1723 pcdev->dev = &pdev->dev; 1724 1725 if (cpu_is_mx25()) { 1726 err = request_irq(pcdev->irq_csi, mx25_camera_irq, 0, 1727 MX2_CAM_DRV_NAME, pcdev); 1728 if (err) { 1729 dev_err(pcdev->dev, "Camera interrupt register failed \n"); 1730 goto exit_iounmap; 1731 } 1732 } 1733 1734 if (cpu_is_mx27()) { 1735 /* EMMA support */ 1736 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1737 irq_emma = platform_get_irq(pdev, 1); 1738 1739 if (!res_emma || !irq_emma) { 1740 dev_err(&pdev->dev, "no EMMA resources\n"); 1741 goto exit_free_irq; 1742 } 1743 1744 pcdev->res_emma = res_emma; 1745 pcdev->irq_emma = irq_emma; 1746 if (mx27_camera_emma_init(pcdev)) 1747 goto exit_free_irq; 1748 } 1749 1750 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME, 1751 pcdev->soc_host.ops = &mx2_soc_camera_host_ops, 1752 pcdev->soc_host.priv = pcdev; 1753 pcdev->soc_host.v4l2_dev.dev = &pdev->dev; 1754 pcdev->soc_host.nr = pdev->id; 1755 1756 pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev); 1757 if (IS_ERR(pcdev->alloc_ctx)) { 1758 err = PTR_ERR(pcdev->alloc_ctx); 1759 goto eallocctx; 1760 } 1761 err = soc_camera_host_register(&pcdev->soc_host); 1762 if (err) 1763 goto exit_free_emma; 1764 1765 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n", 1766 clk_get_rate(pcdev->clk_csi)); 1767 1768 return 0; 1769 1770exit_free_emma: 1771 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx); 1772eallocctx: 1773 if (cpu_is_mx27()) { 1774 free_irq(pcdev->irq_emma, pcdev); 1775 clk_disable(pcdev->clk_emma); 1776 clk_put(pcdev->clk_emma); 1777 iounmap(pcdev->base_emma); 1778 release_mem_region(pcdev->res_emma->start, resource_size(pcdev->res_emma)); 1779 } 1780exit_free_irq: 1781 if (cpu_is_mx25()) 1782 free_irq(pcdev->irq_csi, pcdev); 1783exit_iounmap: 1784 iounmap(base_csi); 1785exit_release: 1786 release_mem_region(res_csi->start, resource_size(res_csi)); 1787exit_dma_free: 1788 clk_put(pcdev->clk_csi); 1789exit_kfree: 1790 kfree(pcdev); 1791exit: 1792 return err; 1793} 1794 1795static int __devexit mx2_camera_remove(struct platform_device *pdev) 1796{ 1797 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); 1798 struct mx2_camera_dev *pcdev = container_of(soc_host, 1799 struct mx2_camera_dev, soc_host); 1800 struct resource *res; 1801 1802 clk_put(pcdev->clk_csi); 1803 if (cpu_is_mx25()) 1804 free_irq(pcdev->irq_csi, pcdev); 1805 if (cpu_is_mx27()) 1806 free_irq(pcdev->irq_emma, pcdev); 1807 1808 soc_camera_host_unregister(&pcdev->soc_host); 1809 1810 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx); 1811 1812 iounmap(pcdev->base_csi); 1813 1814 if (cpu_is_mx27()) { 1815 clk_disable(pcdev->clk_emma); 1816 clk_put(pcdev->clk_emma); 1817 iounmap(pcdev->base_emma); 1818 res = pcdev->res_emma; 1819 release_mem_region(res->start, resource_size(res)); 1820 } 1821 1822 res = pcdev->res_csi; 1823 release_mem_region(res->start, resource_size(res)); 1824 1825 kfree(pcdev); 1826 1827 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n"); 1828 1829 return 0; 1830} 1831 1832static struct platform_driver mx2_camera_driver = { 1833 .driver = { 1834 .name = MX2_CAM_DRV_NAME, 1835 }, 1836 .remove = __devexit_p(mx2_camera_remove), 1837}; 1838 1839 1840static int __init mx2_camera_init(void) 1841{ 1842 return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe); 1843} 1844 1845static void __exit mx2_camera_exit(void) 1846{ 1847 return platform_driver_unregister(&mx2_camera_driver); 1848} 1849 1850module_init(mx2_camera_init); 1851module_exit(mx2_camera_exit); 1852 1853MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver"); 1854MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>"); 1855MODULE_LICENSE("GPL"); 1856MODULE_VERSION(MX2_CAM_VERSION); 1857