mx2_camera.c revision cd9ebdbc0541b4e8ee145c81642d68332f79b932
1/* 2 * V4L2 Driver for i.MX27/i.MX25 camera host 3 * 4 * Copyright (C) 2008, Sascha Hauer, Pengutronix 5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/init.h> 14#include <linux/module.h> 15#include <linux/io.h> 16#include <linux/delay.h> 17#include <linux/slab.h> 18#include <linux/dma-mapping.h> 19#include <linux/errno.h> 20#include <linux/fs.h> 21#include <linux/interrupt.h> 22#include <linux/kernel.h> 23#include <linux/mm.h> 24#include <linux/moduleparam.h> 25#include <linux/time.h> 26#include <linux/version.h> 27#include <linux/device.h> 28#include <linux/platform_device.h> 29#include <linux/mutex.h> 30#include <linux/clk.h> 31 32#include <media/v4l2-common.h> 33#include <media/v4l2-dev.h> 34#include <media/videobuf-dma-contig.h> 35#include <media/soc_camera.h> 36#include <media/soc_mediabus.h> 37 38#include <linux/videodev2.h> 39 40#include <mach/mx2_cam.h> 41#ifdef CONFIG_MACH_MX27 42#include <mach/dma-mx1-mx2.h> 43#endif 44#include <mach/hardware.h> 45 46#include <asm/dma.h> 47 48#define MX2_CAM_DRV_NAME "mx2-camera" 49#define MX2_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) 50#define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera" 51 52/* reset values */ 53#define CSICR1_RESET_VAL 0x40000800 54#define CSICR2_RESET_VAL 0x0 55#define CSICR3_RESET_VAL 0x0 56 57/* csi control reg 1 */ 58#define CSICR1_SWAP16_EN (1 << 31) 59#define CSICR1_EXT_VSYNC (1 << 30) 60#define CSICR1_EOF_INTEN (1 << 29) 61#define CSICR1_PRP_IF_EN (1 << 28) 62#define CSICR1_CCIR_MODE (1 << 27) 63#define CSICR1_COF_INTEN (1 << 26) 64#define CSICR1_SF_OR_INTEN (1 << 25) 65#define CSICR1_RF_OR_INTEN (1 << 24) 66#define CSICR1_STATFF_LEVEL (3 << 22) 67#define CSICR1_STATFF_INTEN (1 << 21) 68#define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */ 69#define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */ 70#define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */ 71#define CSICR1_RXFF_INTEN (1 << 18) 72#define CSICR1_SOF_POL (1 << 17) 73#define CSICR1_SOF_INTEN (1 << 16) 74#define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12) 75#define CSICR1_HSYNC_POL (1 << 11) 76#define CSICR1_CCIR_EN (1 << 10) 77#define CSICR1_MCLKEN (1 << 9) 78#define CSICR1_FCC (1 << 8) 79#define CSICR1_PACK_DIR (1 << 7) 80#define CSICR1_CLR_STATFIFO (1 << 6) 81#define CSICR1_CLR_RXFIFO (1 << 5) 82#define CSICR1_GCLK_MODE (1 << 4) 83#define CSICR1_INV_DATA (1 << 3) 84#define CSICR1_INV_PCLK (1 << 2) 85#define CSICR1_REDGE (1 << 1) 86 87#define SHIFT_STATFF_LEVEL 22 88#define SHIFT_RXFF_LEVEL 19 89#define SHIFT_MCLKDIV 12 90 91/* control reg 3 */ 92#define CSICR3_FRMCNT (0xFFFF << 16) 93#define CSICR3_FRMCNT_RST (1 << 15) 94#define CSICR3_DMA_REFLASH_RFF (1 << 14) 95#define CSICR3_DMA_REFLASH_SFF (1 << 13) 96#define CSICR3_DMA_REQ_EN_RFF (1 << 12) 97#define CSICR3_DMA_REQ_EN_SFF (1 << 11) 98#define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */ 99#define CSICR3_CSI_SUP (1 << 3) 100#define CSICR3_ZERO_PACK_EN (1 << 2) 101#define CSICR3_ECC_INT_EN (1 << 1) 102#define CSICR3_ECC_AUTO_EN (1 << 0) 103 104#define SHIFT_FRMCNT 16 105 106/* csi status reg */ 107#define CSISR_SFF_OR_INT (1 << 25) 108#define CSISR_RFF_OR_INT (1 << 24) 109#define CSISR_STATFF_INT (1 << 21) 110#define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */ 111#define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */ 112#define CSISR_RXFF_INT (1 << 18) 113#define CSISR_EOF_INT (1 << 17) 114#define CSISR_SOF_INT (1 << 16) 115#define CSISR_F2_INT (1 << 15) 116#define CSISR_F1_INT (1 << 14) 117#define CSISR_COF_INT (1 << 13) 118#define CSISR_ECC_INT (1 << 1) 119#define CSISR_DRDY (1 << 0) 120 121#define CSICR1 0x00 122#define CSICR2 0x04 123#define CSISR (cpu_is_mx27() ? 0x08 : 0x18) 124#define CSISTATFIFO 0x0c 125#define CSIRFIFO 0x10 126#define CSIRXCNT 0x14 127#define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08) 128#define CSIDMASA_STATFIFO 0x20 129#define CSIDMATA_STATFIFO 0x24 130#define CSIDMASA_FB1 0x28 131#define CSIDMASA_FB2 0x2c 132#define CSIFBUF_PARA 0x30 133#define CSIIMAG_PARA 0x34 134 135/* EMMA PrP */ 136#define PRP_CNTL 0x00 137#define PRP_INTR_CNTL 0x04 138#define PRP_INTRSTATUS 0x08 139#define PRP_SOURCE_Y_PTR 0x0c 140#define PRP_SOURCE_CB_PTR 0x10 141#define PRP_SOURCE_CR_PTR 0x14 142#define PRP_DEST_RGB1_PTR 0x18 143#define PRP_DEST_RGB2_PTR 0x1c 144#define PRP_DEST_Y_PTR 0x20 145#define PRP_DEST_CB_PTR 0x24 146#define PRP_DEST_CR_PTR 0x28 147#define PRP_SRC_FRAME_SIZE 0x2c 148#define PRP_DEST_CH1_LINE_STRIDE 0x30 149#define PRP_SRC_PIXEL_FORMAT_CNTL 0x34 150#define PRP_CH1_PIXEL_FORMAT_CNTL 0x38 151#define PRP_CH1_OUT_IMAGE_SIZE 0x3c 152#define PRP_CH2_OUT_IMAGE_SIZE 0x40 153#define PRP_SRC_LINE_STRIDE 0x44 154#define PRP_CSC_COEF_012 0x48 155#define PRP_CSC_COEF_345 0x4c 156#define PRP_CSC_COEF_678 0x50 157#define PRP_CH1_RZ_HORI_COEF1 0x54 158#define PRP_CH1_RZ_HORI_COEF2 0x58 159#define PRP_CH1_RZ_HORI_VALID 0x5c 160#define PRP_CH1_RZ_VERT_COEF1 0x60 161#define PRP_CH1_RZ_VERT_COEF2 0x64 162#define PRP_CH1_RZ_VERT_VALID 0x68 163#define PRP_CH2_RZ_HORI_COEF1 0x6c 164#define PRP_CH2_RZ_HORI_COEF2 0x70 165#define PRP_CH2_RZ_HORI_VALID 0x74 166#define PRP_CH2_RZ_VERT_COEF1 0x78 167#define PRP_CH2_RZ_VERT_COEF2 0x7c 168#define PRP_CH2_RZ_VERT_VALID 0x80 169 170#define PRP_CNTL_CH1EN (1 << 0) 171#define PRP_CNTL_CH2EN (1 << 1) 172#define PRP_CNTL_CSIEN (1 << 2) 173#define PRP_CNTL_DATA_IN_YUV420 (0 << 3) 174#define PRP_CNTL_DATA_IN_YUV422 (1 << 3) 175#define PRP_CNTL_DATA_IN_RGB16 (2 << 3) 176#define PRP_CNTL_DATA_IN_RGB32 (3 << 3) 177#define PRP_CNTL_CH1_OUT_RGB8 (0 << 5) 178#define PRP_CNTL_CH1_OUT_RGB16 (1 << 5) 179#define PRP_CNTL_CH1_OUT_RGB32 (2 << 5) 180#define PRP_CNTL_CH1_OUT_YUV422 (3 << 5) 181#define PRP_CNTL_CH2_OUT_YUV420 (0 << 7) 182#define PRP_CNTL_CH2_OUT_YUV422 (1 << 7) 183#define PRP_CNTL_CH2_OUT_YUV444 (2 << 7) 184#define PRP_CNTL_CH1_LEN (1 << 9) 185#define PRP_CNTL_CH2_LEN (1 << 10) 186#define PRP_CNTL_SKIP_FRAME (1 << 11) 187#define PRP_CNTL_SWRST (1 << 12) 188#define PRP_CNTL_CLKEN (1 << 13) 189#define PRP_CNTL_WEN (1 << 14) 190#define PRP_CNTL_CH1BYP (1 << 15) 191#define PRP_CNTL_IN_TSKIP(x) ((x) << 16) 192#define PRP_CNTL_CH1_TSKIP(x) ((x) << 19) 193#define PRP_CNTL_CH2_TSKIP(x) ((x) << 22) 194#define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25) 195#define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27) 196#define PRP_CNTL_CH2B1EN (1 << 29) 197#define PRP_CNTL_CH2B2EN (1 << 30) 198#define PRP_CNTL_CH2FEN (1 << 31) 199 200/* IRQ Enable and status register */ 201#define PRP_INTR_RDERR (1 << 0) 202#define PRP_INTR_CH1WERR (1 << 1) 203#define PRP_INTR_CH2WERR (1 << 2) 204#define PRP_INTR_CH1FC (1 << 3) 205#define PRP_INTR_CH2FC (1 << 5) 206#define PRP_INTR_LBOVF (1 << 7) 207#define PRP_INTR_CH2OVF (1 << 8) 208 209#define mx27_camera_emma(pcdev) (cpu_is_mx27() && pcdev->use_emma) 210 211#define MAX_VIDEO_MEM 16 212 213struct mx2_camera_dev { 214 struct device *dev; 215 struct soc_camera_host soc_host; 216 struct soc_camera_device *icd; 217 struct clk *clk_csi, *clk_emma; 218 219 unsigned int irq_csi, irq_emma; 220 void __iomem *base_csi, *base_emma; 221 unsigned long base_dma; 222 223 struct mx2_camera_platform_data *pdata; 224 struct resource *res_csi, *res_emma; 225 unsigned long platform_flags; 226 227 struct list_head capture; 228 struct list_head active_bufs; 229 230 spinlock_t lock; 231 232 int dma; 233 struct mx2_buffer *active; 234 struct mx2_buffer *fb1_active; 235 struct mx2_buffer *fb2_active; 236 237 int use_emma; 238 239 u32 csicr1; 240 241 void *discard_buffer; 242 dma_addr_t discard_buffer_dma; 243 size_t discard_size; 244}; 245 246/* buffer for one video frame */ 247struct mx2_buffer { 248 /* common v4l buffer stuff -- must be first */ 249 struct videobuf_buffer vb; 250 251 enum v4l2_mbus_pixelcode code; 252 253 int bufnum; 254}; 255 256static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev) 257{ 258 unsigned long flags; 259 260 clk_disable(pcdev->clk_csi); 261 writel(0, pcdev->base_csi + CSICR1); 262 if (mx27_camera_emma(pcdev)) { 263 writel(0, pcdev->base_emma + PRP_CNTL); 264 } else if (cpu_is_mx25()) { 265 spin_lock_irqsave(&pcdev->lock, flags); 266 pcdev->fb1_active = NULL; 267 pcdev->fb2_active = NULL; 268 writel(0, pcdev->base_csi + CSIDMASA_FB1); 269 writel(0, pcdev->base_csi + CSIDMASA_FB2); 270 spin_unlock_irqrestore(&pcdev->lock, flags); 271 } 272} 273 274/* 275 * The following two functions absolutely depend on the fact, that 276 * there can be only one camera on mx2 camera sensor interface 277 */ 278static int mx2_camera_add_device(struct soc_camera_device *icd) 279{ 280 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 281 struct mx2_camera_dev *pcdev = ici->priv; 282 int ret; 283 u32 csicr1; 284 285 if (pcdev->icd) 286 return -EBUSY; 287 288 ret = clk_enable(pcdev->clk_csi); 289 if (ret < 0) 290 return ret; 291 292 csicr1 = CSICR1_MCLKEN; 293 294 if (mx27_camera_emma(pcdev)) { 295 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC | 296 CSICR1_RXFF_LEVEL(0); 297 } else if (cpu_is_mx27()) 298 csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2); 299 300 pcdev->csicr1 = csicr1; 301 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 302 303 pcdev->icd = icd; 304 305 dev_info(icd->dev.parent, "Camera driver attached to camera %d\n", 306 icd->devnum); 307 308 return 0; 309} 310 311static void mx2_camera_remove_device(struct soc_camera_device *icd) 312{ 313 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 314 struct mx2_camera_dev *pcdev = ici->priv; 315 316 BUG_ON(icd != pcdev->icd); 317 318 dev_info(icd->dev.parent, "Camera driver detached from camera %d\n", 319 icd->devnum); 320 321 mx2_camera_deactivate(pcdev); 322 323 if (pcdev->discard_buffer) { 324 dma_free_coherent(ici->v4l2_dev.dev, pcdev->discard_size, 325 pcdev->discard_buffer, 326 pcdev->discard_buffer_dma); 327 pcdev->discard_buffer = NULL; 328 } 329 330 pcdev->icd = NULL; 331} 332 333#ifdef CONFIG_MACH_MX27 334static void mx27_camera_dma_enable(struct mx2_camera_dev *pcdev) 335{ 336 u32 tmp; 337 338 imx_dma_enable(pcdev->dma); 339 340 tmp = readl(pcdev->base_csi + CSICR1); 341 tmp |= CSICR1_RF_OR_INTEN; 342 writel(tmp, pcdev->base_csi + CSICR1); 343} 344 345static irqreturn_t mx27_camera_irq(int irq_csi, void *data) 346{ 347 struct mx2_camera_dev *pcdev = data; 348 u32 status = readl(pcdev->base_csi + CSISR); 349 350 if (status & CSISR_SOF_INT && pcdev->active) { 351 u32 tmp; 352 353 tmp = readl(pcdev->base_csi + CSICR1); 354 writel(tmp | CSICR1_CLR_RXFIFO, pcdev->base_csi + CSICR1); 355 mx27_camera_dma_enable(pcdev); 356 } 357 358 writel(CSISR_SOF_INT | CSISR_RFF_OR_INT, pcdev->base_csi + CSISR); 359 360 return IRQ_HANDLED; 361} 362#else 363static irqreturn_t mx27_camera_irq(int irq_csi, void *data) 364{ 365 return IRQ_NONE; 366} 367#endif /* CONFIG_MACH_MX27 */ 368 369static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb, 370 int state) 371{ 372 struct videobuf_buffer *vb; 373 struct mx2_buffer *buf; 374 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active : 375 &pcdev->fb2_active; 376 u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2; 377 unsigned long flags; 378 379 spin_lock_irqsave(&pcdev->lock, flags); 380 381 vb = &(*fb_active)->vb; 382 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 383 vb, vb->baddr, vb->bsize); 384 385 vb->state = state; 386 do_gettimeofday(&vb->ts); 387 vb->field_count++; 388 389 wake_up(&vb->done); 390 391 if (list_empty(&pcdev->capture)) { 392 buf = NULL; 393 writel(0, pcdev->base_csi + fb_reg); 394 } else { 395 buf = list_entry(pcdev->capture.next, struct mx2_buffer, 396 vb.queue); 397 vb = &buf->vb; 398 list_del(&vb->queue); 399 vb->state = VIDEOBUF_ACTIVE; 400 writel(videobuf_to_dma_contig(vb), pcdev->base_csi + fb_reg); 401 } 402 403 *fb_active = buf; 404 405 spin_unlock_irqrestore(&pcdev->lock, flags); 406} 407 408static irqreturn_t mx25_camera_irq(int irq_csi, void *data) 409{ 410 struct mx2_camera_dev *pcdev = data; 411 u32 status = readl(pcdev->base_csi + CSISR); 412 413 if (status & CSISR_DMA_TSF_FB1_INT) 414 mx25_camera_frame_done(pcdev, 1, VIDEOBUF_DONE); 415 else if (status & CSISR_DMA_TSF_FB2_INT) 416 mx25_camera_frame_done(pcdev, 2, VIDEOBUF_DONE); 417 418 /* FIXME: handle CSISR_RFF_OR_INT */ 419 420 writel(status, pcdev->base_csi + CSISR); 421 422 return IRQ_HANDLED; 423} 424 425/* 426 * Videobuf operations 427 */ 428static int mx2_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, 429 unsigned int *size) 430{ 431 struct soc_camera_device *icd = vq->priv_data; 432 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, 433 icd->current_fmt->host_fmt); 434 435 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size); 436 437 if (bytes_per_line < 0) 438 return bytes_per_line; 439 440 *size = bytes_per_line * icd->user_height; 441 442 if (0 == *count) 443 *count = 32; 444 if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024) 445 *count = (MAX_VIDEO_MEM * 1024 * 1024) / *size; 446 447 return 0; 448} 449 450static void free_buffer(struct videobuf_queue *vq, struct mx2_buffer *buf) 451{ 452 struct soc_camera_device *icd = vq->priv_data; 453 struct videobuf_buffer *vb = &buf->vb; 454 455 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 456 vb, vb->baddr, vb->bsize); 457 458 /* 459 * This waits until this buffer is out of danger, i.e., until it is no 460 * longer in STATE_QUEUED or STATE_ACTIVE 461 */ 462 videobuf_waiton(vb, 0, 0); 463 464 videobuf_dma_contig_free(vq, vb); 465 dev_dbg(&icd->dev, "%s freed\n", __func__); 466 467 vb->state = VIDEOBUF_NEEDS_INIT; 468} 469 470static int mx2_videobuf_prepare(struct videobuf_queue *vq, 471 struct videobuf_buffer *vb, enum v4l2_field field) 472{ 473 struct soc_camera_device *icd = vq->priv_data; 474 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 475 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, 476 icd->current_fmt->host_fmt); 477 int ret = 0; 478 479 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 480 vb, vb->baddr, vb->bsize); 481 482 if (bytes_per_line < 0) 483 return bytes_per_line; 484 485#ifdef DEBUG 486 /* 487 * This can be useful if you want to see if we actually fill 488 * the buffer with something 489 */ 490 memset((void *)vb->baddr, 0xaa, vb->bsize); 491#endif 492 493 if (buf->code != icd->current_fmt->code || 494 vb->width != icd->user_width || 495 vb->height != icd->user_height || 496 vb->field != field) { 497 buf->code = icd->current_fmt->code; 498 vb->width = icd->user_width; 499 vb->height = icd->user_height; 500 vb->field = field; 501 vb->state = VIDEOBUF_NEEDS_INIT; 502 } 503 504 vb->size = bytes_per_line * vb->height; 505 if (vb->baddr && vb->bsize < vb->size) { 506 ret = -EINVAL; 507 goto out; 508 } 509 510 if (vb->state == VIDEOBUF_NEEDS_INIT) { 511 ret = videobuf_iolock(vq, vb, NULL); 512 if (ret) 513 goto fail; 514 515 vb->state = VIDEOBUF_PREPARED; 516 } 517 518 return 0; 519 520fail: 521 free_buffer(vq, buf); 522out: 523 return ret; 524} 525 526static void mx2_videobuf_queue(struct videobuf_queue *vq, 527 struct videobuf_buffer *vb) 528{ 529 struct soc_camera_device *icd = vq->priv_data; 530 struct soc_camera_host *ici = 531 to_soc_camera_host(icd->dev.parent); 532 struct mx2_camera_dev *pcdev = ici->priv; 533 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 534 unsigned long flags; 535 536 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 537 vb, vb->baddr, vb->bsize); 538 539 spin_lock_irqsave(&pcdev->lock, flags); 540 541 vb->state = VIDEOBUF_QUEUED; 542 list_add_tail(&vb->queue, &pcdev->capture); 543 544 if (mx27_camera_emma(pcdev)) { 545 goto out; 546#ifdef CONFIG_MACH_MX27 547 } else if (cpu_is_mx27()) { 548 int ret; 549 550 if (pcdev->active == NULL) { 551 ret = imx_dma_setup_single(pcdev->dma, 552 videobuf_to_dma_contig(vb), vb->size, 553 (u32)pcdev->base_dma + 0x10, 554 DMA_MODE_READ); 555 if (ret) { 556 vb->state = VIDEOBUF_ERROR; 557 wake_up(&vb->done); 558 goto out; 559 } 560 561 vb->state = VIDEOBUF_ACTIVE; 562 pcdev->active = buf; 563 } 564#endif 565 } else { /* cpu_is_mx25() */ 566 u32 csicr3, dma_inten = 0; 567 568 if (pcdev->fb1_active == NULL) { 569 writel(videobuf_to_dma_contig(vb), 570 pcdev->base_csi + CSIDMASA_FB1); 571 pcdev->fb1_active = buf; 572 dma_inten = CSICR1_FB1_DMA_INTEN; 573 } else if (pcdev->fb2_active == NULL) { 574 writel(videobuf_to_dma_contig(vb), 575 pcdev->base_csi + CSIDMASA_FB2); 576 pcdev->fb2_active = buf; 577 dma_inten = CSICR1_FB2_DMA_INTEN; 578 } 579 580 if (dma_inten) { 581 list_del(&vb->queue); 582 vb->state = VIDEOBUF_ACTIVE; 583 584 csicr3 = readl(pcdev->base_csi + CSICR3); 585 586 /* Reflash DMA */ 587 writel(csicr3 | CSICR3_DMA_REFLASH_RFF, 588 pcdev->base_csi + CSICR3); 589 590 /* clear & enable interrupts */ 591 writel(dma_inten, pcdev->base_csi + CSISR); 592 pcdev->csicr1 |= dma_inten; 593 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 594 595 /* enable DMA */ 596 csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1); 597 writel(csicr3, pcdev->base_csi + CSICR3); 598 } 599 } 600 601out: 602 spin_unlock_irqrestore(&pcdev->lock, flags); 603} 604 605static void mx2_videobuf_release(struct videobuf_queue *vq, 606 struct videobuf_buffer *vb) 607{ 608 struct soc_camera_device *icd = vq->priv_data; 609 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 610 struct mx2_camera_dev *pcdev = ici->priv; 611 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 612 unsigned long flags; 613 614#ifdef DEBUG 615 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 616 vb, vb->baddr, vb->bsize); 617 618 switch (vb->state) { 619 case VIDEOBUF_ACTIVE: 620 dev_info(&icd->dev, "%s (active)\n", __func__); 621 break; 622 case VIDEOBUF_QUEUED: 623 dev_info(&icd->dev, "%s (queued)\n", __func__); 624 break; 625 case VIDEOBUF_PREPARED: 626 dev_info(&icd->dev, "%s (prepared)\n", __func__); 627 break; 628 default: 629 dev_info(&icd->dev, "%s (unknown) %d\n", __func__, 630 vb->state); 631 break; 632 } 633#endif 634 635 /* 636 * Terminate only queued but inactive buffers. Active buffers are 637 * released when they become inactive after videobuf_waiton(). 638 * 639 * FIXME: implement forced termination of active buffers, so that the 640 * user won't get stuck in an uninterruptible state. This requires a 641 * specific handling for each of the three DMA types that this driver 642 * supports. 643 */ 644 spin_lock_irqsave(&pcdev->lock, flags); 645 if (vb->state == VIDEOBUF_QUEUED) { 646 list_del(&vb->queue); 647 vb->state = VIDEOBUF_ERROR; 648 } 649 spin_unlock_irqrestore(&pcdev->lock, flags); 650 651 free_buffer(vq, buf); 652} 653 654static struct videobuf_queue_ops mx2_videobuf_ops = { 655 .buf_setup = mx2_videobuf_setup, 656 .buf_prepare = mx2_videobuf_prepare, 657 .buf_queue = mx2_videobuf_queue, 658 .buf_release = mx2_videobuf_release, 659}; 660 661static void mx2_camera_init_videobuf(struct videobuf_queue *q, 662 struct soc_camera_device *icd) 663{ 664 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 665 struct mx2_camera_dev *pcdev = ici->priv; 666 667 videobuf_queue_dma_contig_init(q, &mx2_videobuf_ops, pcdev->dev, 668 &pcdev->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE, 669 V4L2_FIELD_NONE, sizeof(struct mx2_buffer), icd); 670} 671 672#define MX2_BUS_FLAGS (SOCAM_DATAWIDTH_8 | \ 673 SOCAM_MASTER | \ 674 SOCAM_VSYNC_ACTIVE_HIGH | \ 675 SOCAM_VSYNC_ACTIVE_LOW | \ 676 SOCAM_HSYNC_ACTIVE_HIGH | \ 677 SOCAM_HSYNC_ACTIVE_LOW | \ 678 SOCAM_PCLK_SAMPLE_RISING | \ 679 SOCAM_PCLK_SAMPLE_FALLING | \ 680 SOCAM_DATA_ACTIVE_HIGH | \ 681 SOCAM_DATA_ACTIVE_LOW) 682 683static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev) 684{ 685 u32 cntl; 686 int count = 0; 687 688 cntl = readl(pcdev->base_emma + PRP_CNTL); 689 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL); 690 while (count++ < 100) { 691 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST)) 692 return 0; 693 barrier(); 694 udelay(1); 695 } 696 697 return -ETIMEDOUT; 698} 699 700static void mx27_camera_emma_buf_init(struct soc_camera_device *icd, 701 int bytesperline) 702{ 703 struct soc_camera_host *ici = 704 to_soc_camera_host(icd->dev.parent); 705 struct mx2_camera_dev *pcdev = ici->priv; 706 707 writel(pcdev->discard_buffer_dma, 708 pcdev->base_emma + PRP_DEST_RGB1_PTR); 709 writel(pcdev->discard_buffer_dma, 710 pcdev->base_emma + PRP_DEST_RGB2_PTR); 711 712 /* 713 * We only use the EMMA engine to get rid of the broken 714 * DMA Engine. No color space consversion at the moment. 715 * We adjust incoming and outgoing pixelformat to rgb16 716 * and adjust the bytesperline accordingly. 717 */ 718 writel(PRP_CNTL_CH1EN | 719 PRP_CNTL_CSIEN | 720 PRP_CNTL_DATA_IN_RGB16 | 721 PRP_CNTL_CH1_OUT_RGB16 | 722 PRP_CNTL_CH1_LEN | 723 PRP_CNTL_CH1BYP | 724 PRP_CNTL_CH1_TSKIP(0) | 725 PRP_CNTL_IN_TSKIP(0), 726 pcdev->base_emma + PRP_CNTL); 727 728 writel(((bytesperline >> 1) << 16) | icd->user_height, 729 pcdev->base_emma + PRP_SRC_FRAME_SIZE); 730 writel(((bytesperline >> 1) << 16) | icd->user_height, 731 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE); 732 writel(bytesperline, 733 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE); 734 writel(0x2ca00565, /* RGB565 */ 735 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL); 736 writel(0x2ca00565, /* RGB565 */ 737 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL); 738 739 /* Enable interrupts */ 740 writel(PRP_INTR_RDERR | 741 PRP_INTR_CH1WERR | 742 PRP_INTR_CH2WERR | 743 PRP_INTR_CH1FC | 744 PRP_INTR_CH2FC | 745 PRP_INTR_LBOVF | 746 PRP_INTR_CH2OVF, 747 pcdev->base_emma + PRP_INTR_CNTL); 748} 749 750static int mx2_camera_set_bus_param(struct soc_camera_device *icd, 751 __u32 pixfmt) 752{ 753 struct soc_camera_host *ici = 754 to_soc_camera_host(icd->dev.parent); 755 struct mx2_camera_dev *pcdev = ici->priv; 756 unsigned long camera_flags, common_flags; 757 int ret = 0; 758 int bytesperline; 759 u32 csicr1 = pcdev->csicr1; 760 761 camera_flags = icd->ops->query_bus_param(icd); 762 763 common_flags = soc_camera_bus_param_compatible(camera_flags, 764 MX2_BUS_FLAGS); 765 if (!common_flags) 766 return -EINVAL; 767 768 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) && 769 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) { 770 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH) 771 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW; 772 else 773 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH; 774 } 775 776 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && 777 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { 778 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING) 779 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; 780 else 781 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; 782 } 783 784 ret = icd->ops->set_bus_param(icd, common_flags); 785 if (ret < 0) 786 return ret; 787 788 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING) 789 csicr1 |= CSICR1_INV_PCLK; 790 if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH) 791 csicr1 |= CSICR1_SOF_POL; 792 if (common_flags & SOCAM_HSYNC_ACTIVE_HIGH) 793 csicr1 |= CSICR1_HSYNC_POL; 794 if (pcdev->platform_flags & MX2_CAMERA_SWAP16) 795 csicr1 |= CSICR1_SWAP16_EN; 796 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC) 797 csicr1 |= CSICR1_EXT_VSYNC; 798 if (pcdev->platform_flags & MX2_CAMERA_CCIR) 799 csicr1 |= CSICR1_CCIR_EN; 800 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE) 801 csicr1 |= CSICR1_CCIR_MODE; 802 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK) 803 csicr1 |= CSICR1_GCLK_MODE; 804 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA) 805 csicr1 |= CSICR1_INV_DATA; 806 if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB) 807 csicr1 |= CSICR1_PACK_DIR; 808 809 pcdev->csicr1 = csicr1; 810 811 bytesperline = soc_mbus_bytes_per_line(icd->user_width, 812 icd->current_fmt->host_fmt); 813 if (bytesperline < 0) 814 return bytesperline; 815 816 if (mx27_camera_emma(pcdev)) { 817 ret = mx27_camera_emma_prp_reset(pcdev); 818 if (ret) 819 return ret; 820 821 if (pcdev->discard_buffer) 822 dma_free_coherent(ici->v4l2_dev.dev, 823 pcdev->discard_size, pcdev->discard_buffer, 824 pcdev->discard_buffer_dma); 825 826 /* 827 * I didn't manage to properly enable/disable the prp 828 * on a per frame basis during running transfers, 829 * thus we allocate a buffer here and use it to 830 * discard frames when no buffer is available. 831 * Feel free to work on this ;) 832 */ 833 pcdev->discard_size = icd->user_height * bytesperline; 834 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev, 835 pcdev->discard_size, &pcdev->discard_buffer_dma, 836 GFP_KERNEL); 837 if (!pcdev->discard_buffer) 838 return -ENOMEM; 839 840 mx27_camera_emma_buf_init(icd, bytesperline); 841 } else if (cpu_is_mx25()) { 842 writel((bytesperline * icd->user_height) >> 2, 843 pcdev->base_csi + CSIRXCNT); 844 writel((bytesperline << 16) | icd->user_height, 845 pcdev->base_csi + CSIIMAG_PARA); 846 } 847 848 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 849 850 return 0; 851} 852 853static int mx2_camera_set_crop(struct soc_camera_device *icd, 854 struct v4l2_crop *a) 855{ 856 struct v4l2_rect *rect = &a->c; 857 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 858 struct v4l2_mbus_framefmt mf; 859 int ret; 860 861 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096); 862 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096); 863 864 ret = v4l2_subdev_call(sd, video, s_crop, a); 865 if (ret < 0) 866 return ret; 867 868 /* The capture device might have changed its output */ 869 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); 870 if (ret < 0) 871 return ret; 872 873 dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n", 874 mf.width, mf.height); 875 876 icd->user_width = mf.width; 877 icd->user_height = mf.height; 878 879 return ret; 880} 881 882static int mx2_camera_set_fmt(struct soc_camera_device *icd, 883 struct v4l2_format *f) 884{ 885 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 886 struct mx2_camera_dev *pcdev = ici->priv; 887 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 888 const struct soc_camera_format_xlate *xlate; 889 struct v4l2_pix_format *pix = &f->fmt.pix; 890 struct v4l2_mbus_framefmt mf; 891 int ret; 892 893 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); 894 if (!xlate) { 895 dev_warn(icd->dev.parent, "Format %x not found\n", 896 pix->pixelformat); 897 return -EINVAL; 898 } 899 900 /* eMMA can only do RGB565 */ 901 if (mx27_camera_emma(pcdev) && pix->pixelformat != V4L2_PIX_FMT_RGB565) 902 return -EINVAL; 903 904 mf.width = pix->width; 905 mf.height = pix->height; 906 mf.field = pix->field; 907 mf.colorspace = pix->colorspace; 908 mf.code = xlate->code; 909 910 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); 911 if (ret < 0 && ret != -ENOIOCTLCMD) 912 return ret; 913 914 if (mf.code != xlate->code) 915 return -EINVAL; 916 917 pix->width = mf.width; 918 pix->height = mf.height; 919 pix->field = mf.field; 920 pix->colorspace = mf.colorspace; 921 icd->current_fmt = xlate; 922 923 return 0; 924} 925 926static int mx2_camera_try_fmt(struct soc_camera_device *icd, 927 struct v4l2_format *f) 928{ 929 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 930 struct mx2_camera_dev *pcdev = ici->priv; 931 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 932 const struct soc_camera_format_xlate *xlate; 933 struct v4l2_pix_format *pix = &f->fmt.pix; 934 struct v4l2_mbus_framefmt mf; 935 __u32 pixfmt = pix->pixelformat; 936 unsigned int width_limit; 937 int ret; 938 939 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); 940 if (pixfmt && !xlate) { 941 dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt); 942 return -EINVAL; 943 } 944 945 /* FIXME: implement MX27 limits */ 946 947 /* eMMA can only do RGB565 */ 948 if (mx27_camera_emma(pcdev) && pixfmt != V4L2_PIX_FMT_RGB565) 949 return -EINVAL; 950 951 /* limit to MX25 hardware capabilities */ 952 if (cpu_is_mx25()) { 953 if (xlate->host_fmt->bits_per_sample <= 8) 954 width_limit = 0xffff * 4; 955 else 956 width_limit = 0xffff * 2; 957 /* CSIIMAG_PARA limit */ 958 if (pix->width > width_limit) 959 pix->width = width_limit; 960 if (pix->height > 0xffff) 961 pix->height = 0xffff; 962 963 pix->bytesperline = soc_mbus_bytes_per_line(pix->width, 964 xlate->host_fmt); 965 if (pix->bytesperline < 0) 966 return pix->bytesperline; 967 pix->sizeimage = pix->height * pix->bytesperline; 968 if (pix->sizeimage > (4 * 0x3ffff)) { /* CSIRXCNT limit */ 969 dev_warn(icd->dev.parent, 970 "Image size (%u) above limit\n", 971 pix->sizeimage); 972 return -EINVAL; 973 } 974 } 975 976 /* limit to sensor capabilities */ 977 mf.width = pix->width; 978 mf.height = pix->height; 979 mf.field = pix->field; 980 mf.colorspace = pix->colorspace; 981 mf.code = xlate->code; 982 983 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); 984 if (ret < 0) 985 return ret; 986 987 if (mf.field == V4L2_FIELD_ANY) 988 mf.field = V4L2_FIELD_NONE; 989 if (mf.field != V4L2_FIELD_NONE) { 990 dev_err(icd->dev.parent, "Field type %d unsupported.\n", 991 mf.field); 992 return -EINVAL; 993 } 994 995 pix->width = mf.width; 996 pix->height = mf.height; 997 pix->field = mf.field; 998 pix->colorspace = mf.colorspace; 999 1000 return 0; 1001} 1002 1003static int mx2_camera_querycap(struct soc_camera_host *ici, 1004 struct v4l2_capability *cap) 1005{ 1006 /* cap->name is set by the friendly caller:-> */ 1007 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card)); 1008 cap->version = MX2_CAM_VERSION_CODE; 1009 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; 1010 1011 return 0; 1012} 1013 1014static int mx2_camera_reqbufs(struct soc_camera_file *icf, 1015 struct v4l2_requestbuffers *p) 1016{ 1017 int i; 1018 1019 for (i = 0; i < p->count; i++) { 1020 struct mx2_buffer *buf = container_of(icf->vb_vidq.bufs[i], 1021 struct mx2_buffer, vb); 1022 INIT_LIST_HEAD(&buf->vb.queue); 1023 } 1024 1025 return 0; 1026} 1027 1028#ifdef CONFIG_MACH_MX27 1029static void mx27_camera_frame_done(struct mx2_camera_dev *pcdev, int state) 1030{ 1031 struct videobuf_buffer *vb; 1032 struct mx2_buffer *buf; 1033 unsigned long flags; 1034 int ret; 1035 1036 spin_lock_irqsave(&pcdev->lock, flags); 1037 1038 if (!pcdev->active) { 1039 dev_err(pcdev->dev, "%s called with no active buffer!\n", 1040 __func__); 1041 goto out; 1042 } 1043 1044 vb = &pcdev->active->vb; 1045 buf = container_of(vb, struct mx2_buffer, vb); 1046 WARN_ON(list_empty(&vb->queue)); 1047 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 1048 vb, vb->baddr, vb->bsize); 1049 1050 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ 1051 list_del_init(&vb->queue); 1052 vb->state = state; 1053 do_gettimeofday(&vb->ts); 1054 vb->field_count++; 1055 1056 wake_up(&vb->done); 1057 1058 if (list_empty(&pcdev->capture)) { 1059 pcdev->active = NULL; 1060 goto out; 1061 } 1062 1063 pcdev->active = list_entry(pcdev->capture.next, 1064 struct mx2_buffer, vb.queue); 1065 1066 vb = &pcdev->active->vb; 1067 vb->state = VIDEOBUF_ACTIVE; 1068 1069 ret = imx_dma_setup_single(pcdev->dma, videobuf_to_dma_contig(vb), 1070 vb->size, (u32)pcdev->base_dma + 0x10, DMA_MODE_READ); 1071 1072 if (ret) { 1073 vb->state = VIDEOBUF_ERROR; 1074 pcdev->active = NULL; 1075 wake_up(&vb->done); 1076 } 1077 1078out: 1079 spin_unlock_irqrestore(&pcdev->lock, flags); 1080} 1081 1082static void mx27_camera_dma_err_callback(int channel, void *data, int err) 1083{ 1084 struct mx2_camera_dev *pcdev = data; 1085 1086 mx27_camera_frame_done(pcdev, VIDEOBUF_ERROR); 1087} 1088 1089static void mx27_camera_dma_callback(int channel, void *data) 1090{ 1091 struct mx2_camera_dev *pcdev = data; 1092 1093 mx27_camera_frame_done(pcdev, VIDEOBUF_DONE); 1094} 1095 1096#define DMA_REQ_CSI_RX 31 /* FIXME: Add this to a resource */ 1097 1098static int __devinit mx27_camera_dma_init(struct platform_device *pdev, 1099 struct mx2_camera_dev *pcdev) 1100{ 1101 int err; 1102 1103 pcdev->dma = imx_dma_request_by_prio("CSI RX DMA", DMA_PRIO_HIGH); 1104 if (pcdev->dma < 0) { 1105 dev_err(&pdev->dev, "%s failed to request DMA channel\n", 1106 __func__); 1107 return pcdev->dma; 1108 } 1109 1110 err = imx_dma_setup_handlers(pcdev->dma, mx27_camera_dma_callback, 1111 mx27_camera_dma_err_callback, pcdev); 1112 if (err) { 1113 dev_err(&pdev->dev, "%s failed to set DMA callback\n", 1114 __func__); 1115 goto err_out; 1116 } 1117 1118 err = imx_dma_config_channel(pcdev->dma, 1119 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO, 1120 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR, 1121 DMA_REQ_CSI_RX, 1); 1122 if (err) { 1123 dev_err(&pdev->dev, "%s failed to config DMA channel\n", 1124 __func__); 1125 goto err_out; 1126 } 1127 1128 imx_dma_config_burstlen(pcdev->dma, 64); 1129 1130 return 0; 1131 1132err_out: 1133 imx_dma_free(pcdev->dma); 1134 1135 return err; 1136} 1137#endif /* CONFIG_MACH_MX27 */ 1138 1139static unsigned int mx2_camera_poll(struct file *file, poll_table *pt) 1140{ 1141 struct soc_camera_file *icf = file->private_data; 1142 1143 return videobuf_poll_stream(file, &icf->vb_vidq, pt); 1144} 1145 1146static struct soc_camera_host_ops mx2_soc_camera_host_ops = { 1147 .owner = THIS_MODULE, 1148 .add = mx2_camera_add_device, 1149 .remove = mx2_camera_remove_device, 1150 .set_fmt = mx2_camera_set_fmt, 1151 .set_crop = mx2_camera_set_crop, 1152 .try_fmt = mx2_camera_try_fmt, 1153 .init_videobuf = mx2_camera_init_videobuf, 1154 .reqbufs = mx2_camera_reqbufs, 1155 .poll = mx2_camera_poll, 1156 .querycap = mx2_camera_querycap, 1157 .set_bus_param = mx2_camera_set_bus_param, 1158}; 1159 1160static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev, 1161 int bufnum, int state) 1162{ 1163 struct mx2_buffer *buf; 1164 struct videobuf_buffer *vb; 1165 unsigned long phys; 1166 1167 if (!list_empty(&pcdev->active_bufs)) { 1168 buf = list_entry(pcdev->active_bufs.next, 1169 struct mx2_buffer, vb.queue); 1170 1171 BUG_ON(buf->bufnum != bufnum); 1172 1173 vb = &buf->vb; 1174#ifdef DEBUG 1175 phys = videobuf_to_dma_contig(vb); 1176 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum) 1177 != phys) { 1178 dev_err(pcdev->dev, "%p != %p\n", phys, 1179 readl(pcdev->base_emma + 1180 PRP_DEST_RGB1_PTR + 1181 4 * bufnum)); 1182 } 1183#endif 1184 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb, 1185 vb->baddr, vb->bsize); 1186 1187 list_del(&vb->queue); 1188 vb->state = state; 1189 do_gettimeofday(&vb->ts); 1190 vb->field_count++; 1191 1192 wake_up(&vb->done); 1193 } 1194 1195 if (list_empty(&pcdev->capture)) { 1196 writel(pcdev->discard_buffer_dma, pcdev->base_emma + 1197 PRP_DEST_RGB1_PTR + 4 * bufnum); 1198 return; 1199 } 1200 1201 buf = list_entry(pcdev->capture.next, 1202 struct mx2_buffer, vb.queue); 1203 1204 buf->bufnum = !bufnum; 1205 1206 list_move_tail(pcdev->capture.next, &pcdev->active_bufs); 1207 1208 vb = &buf->vb; 1209 vb->state = VIDEOBUF_ACTIVE; 1210 1211 phys = videobuf_to_dma_contig(vb); 1212 writel(phys, pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum); 1213} 1214 1215static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data) 1216{ 1217 struct mx2_camera_dev *pcdev = data; 1218 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS); 1219 struct mx2_buffer *buf; 1220 1221 if (status & (1 << 7)) { /* overflow */ 1222 u32 cntl; 1223 /* 1224 * We only disable channel 1 here since this is the only 1225 * enabled channel 1226 * 1227 * FIXME: the correct DMA overflow handling should be resetting 1228 * the buffer, returning an error frame, and continuing with 1229 * the next one. 1230 */ 1231 cntl = readl(pcdev->base_emma + PRP_CNTL); 1232 writel(cntl & ~PRP_CNTL_CH1EN, pcdev->base_emma + PRP_CNTL); 1233 writel(cntl, pcdev->base_emma + PRP_CNTL); 1234 } 1235 if ((status & (3 << 5)) == (3 << 5) 1236 && !list_empty(&pcdev->active_bufs)) { 1237 /* 1238 * Both buffers have triggered, process the one we're expecting 1239 * to first 1240 */ 1241 buf = list_entry(pcdev->active_bufs.next, 1242 struct mx2_buffer, vb.queue); 1243 mx27_camera_frame_done_emma(pcdev, buf->bufnum, VIDEOBUF_DONE); 1244 status &= ~(1 << (6 - buf->bufnum)); /* mark processed */ 1245 } 1246 if (status & (1 << 6)) 1247 mx27_camera_frame_done_emma(pcdev, 0, VIDEOBUF_DONE); 1248 if (status & (1 << 5)) 1249 mx27_camera_frame_done_emma(pcdev, 1, VIDEOBUF_DONE); 1250 1251 writel(status, pcdev->base_emma + PRP_INTRSTATUS); 1252 1253 return IRQ_HANDLED; 1254} 1255 1256static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev) 1257{ 1258 struct resource *res_emma = pcdev->res_emma; 1259 int err = 0; 1260 1261 if (!request_mem_region(res_emma->start, resource_size(res_emma), 1262 MX2_CAM_DRV_NAME)) { 1263 err = -EBUSY; 1264 goto out; 1265 } 1266 1267 pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma)); 1268 if (!pcdev->base_emma) { 1269 err = -ENOMEM; 1270 goto exit_release; 1271 } 1272 1273 err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0, 1274 MX2_CAM_DRV_NAME, pcdev); 1275 if (err) { 1276 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n"); 1277 goto exit_iounmap; 1278 } 1279 1280 pcdev->clk_emma = clk_get(NULL, "emma"); 1281 if (IS_ERR(pcdev->clk_emma)) { 1282 err = PTR_ERR(pcdev->clk_emma); 1283 goto exit_free_irq; 1284 } 1285 1286 clk_enable(pcdev->clk_emma); 1287 1288 err = mx27_camera_emma_prp_reset(pcdev); 1289 if (err) 1290 goto exit_clk_emma_put; 1291 1292 return err; 1293 1294exit_clk_emma_put: 1295 clk_disable(pcdev->clk_emma); 1296 clk_put(pcdev->clk_emma); 1297exit_free_irq: 1298 free_irq(pcdev->irq_emma, pcdev); 1299exit_iounmap: 1300 iounmap(pcdev->base_emma); 1301exit_release: 1302 release_mem_region(res_emma->start, resource_size(res_emma)); 1303out: 1304 return err; 1305} 1306 1307static int __devinit mx2_camera_probe(struct platform_device *pdev) 1308{ 1309 struct mx2_camera_dev *pcdev; 1310 struct resource *res_csi, *res_emma; 1311 void __iomem *base_csi; 1312 int irq_csi, irq_emma; 1313 irq_handler_t mx2_cam_irq_handler = cpu_is_mx25() ? mx25_camera_irq 1314 : mx27_camera_irq; 1315 int err = 0; 1316 1317 dev_dbg(&pdev->dev, "initialising\n"); 1318 1319 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1320 irq_csi = platform_get_irq(pdev, 0); 1321 if (res_csi == NULL || irq_csi < 0) { 1322 dev_err(&pdev->dev, "Missing platform resources data\n"); 1323 err = -ENODEV; 1324 goto exit; 1325 } 1326 1327 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); 1328 if (!pcdev) { 1329 dev_err(&pdev->dev, "Could not allocate pcdev\n"); 1330 err = -ENOMEM; 1331 goto exit; 1332 } 1333 1334 pcdev->clk_csi = clk_get(&pdev->dev, NULL); 1335 if (IS_ERR(pcdev->clk_csi)) { 1336 err = PTR_ERR(pcdev->clk_csi); 1337 goto exit_kfree; 1338 } 1339 1340 dev_dbg(&pdev->dev, "Camera clock frequency: %ld\n", 1341 clk_get_rate(pcdev->clk_csi)); 1342 1343 /* Initialize DMA */ 1344#ifdef CONFIG_MACH_MX27 1345 if (cpu_is_mx27()) { 1346 err = mx27_camera_dma_init(pdev, pcdev); 1347 if (err) 1348 goto exit_clk_put; 1349 } 1350#endif /* CONFIG_MACH_MX27 */ 1351 1352 pcdev->res_csi = res_csi; 1353 pcdev->pdata = pdev->dev.platform_data; 1354 if (pcdev->pdata) { 1355 long rate; 1356 1357 pcdev->platform_flags = pcdev->pdata->flags; 1358 1359 rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2); 1360 if (rate <= 0) { 1361 err = -ENODEV; 1362 goto exit_dma_free; 1363 } 1364 err = clk_set_rate(pcdev->clk_csi, rate); 1365 if (err < 0) 1366 goto exit_dma_free; 1367 } 1368 1369 INIT_LIST_HEAD(&pcdev->capture); 1370 INIT_LIST_HEAD(&pcdev->active_bufs); 1371 spin_lock_init(&pcdev->lock); 1372 1373 /* 1374 * Request the regions. 1375 */ 1376 if (!request_mem_region(res_csi->start, resource_size(res_csi), 1377 MX2_CAM_DRV_NAME)) { 1378 err = -EBUSY; 1379 goto exit_dma_free; 1380 } 1381 1382 base_csi = ioremap(res_csi->start, resource_size(res_csi)); 1383 if (!base_csi) { 1384 err = -ENOMEM; 1385 goto exit_release; 1386 } 1387 pcdev->irq_csi = irq_csi; 1388 pcdev->base_csi = base_csi; 1389 pcdev->base_dma = res_csi->start; 1390 pcdev->dev = &pdev->dev; 1391 1392 err = request_irq(pcdev->irq_csi, mx2_cam_irq_handler, 0, 1393 MX2_CAM_DRV_NAME, pcdev); 1394 if (err) { 1395 dev_err(pcdev->dev, "Camera interrupt register failed \n"); 1396 goto exit_iounmap; 1397 } 1398 1399 if (cpu_is_mx27()) { 1400 /* EMMA support */ 1401 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1402 irq_emma = platform_get_irq(pdev, 1); 1403 1404 if (res_emma && irq_emma >= 0) { 1405 dev_info(&pdev->dev, "Using EMMA\n"); 1406 pcdev->use_emma = 1; 1407 pcdev->res_emma = res_emma; 1408 pcdev->irq_emma = irq_emma; 1409 if (mx27_camera_emma_init(pcdev)) 1410 goto exit_free_irq; 1411 } 1412 } 1413 1414 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME, 1415 pcdev->soc_host.ops = &mx2_soc_camera_host_ops, 1416 pcdev->soc_host.priv = pcdev; 1417 pcdev->soc_host.v4l2_dev.dev = &pdev->dev; 1418 pcdev->soc_host.nr = pdev->id; 1419 err = soc_camera_host_register(&pcdev->soc_host); 1420 if (err) 1421 goto exit_free_emma; 1422 1423 return 0; 1424 1425exit_free_emma: 1426 if (mx27_camera_emma(pcdev)) { 1427 free_irq(pcdev->irq_emma, pcdev); 1428 clk_disable(pcdev->clk_emma); 1429 clk_put(pcdev->clk_emma); 1430 iounmap(pcdev->base_emma); 1431 release_mem_region(res_emma->start, resource_size(res_emma)); 1432 } 1433exit_free_irq: 1434 free_irq(pcdev->irq_csi, pcdev); 1435exit_iounmap: 1436 iounmap(base_csi); 1437exit_release: 1438 release_mem_region(res_csi->start, resource_size(res_csi)); 1439exit_dma_free: 1440#ifdef CONFIG_MACH_MX27 1441 if (cpu_is_mx27()) 1442 imx_dma_free(pcdev->dma); 1443exit_clk_put: 1444 clk_put(pcdev->clk_csi); 1445#endif /* CONFIG_MACH_MX27 */ 1446exit_kfree: 1447 kfree(pcdev); 1448exit: 1449 return err; 1450} 1451 1452static int __devexit mx2_camera_remove(struct platform_device *pdev) 1453{ 1454 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); 1455 struct mx2_camera_dev *pcdev = container_of(soc_host, 1456 struct mx2_camera_dev, soc_host); 1457 struct resource *res; 1458 1459 clk_put(pcdev->clk_csi); 1460#ifdef CONFIG_MACH_MX27 1461 if (cpu_is_mx27()) 1462 imx_dma_free(pcdev->dma); 1463#endif /* CONFIG_MACH_MX27 */ 1464 free_irq(pcdev->irq_csi, pcdev); 1465 if (mx27_camera_emma(pcdev)) 1466 free_irq(pcdev->irq_emma, pcdev); 1467 1468 soc_camera_host_unregister(&pcdev->soc_host); 1469 1470 iounmap(pcdev->base_csi); 1471 1472 if (mx27_camera_emma(pcdev)) { 1473 clk_disable(pcdev->clk_emma); 1474 clk_put(pcdev->clk_emma); 1475 iounmap(pcdev->base_emma); 1476 res = pcdev->res_emma; 1477 release_mem_region(res->start, resource_size(res)); 1478 } 1479 1480 res = pcdev->res_csi; 1481 release_mem_region(res->start, resource_size(res)); 1482 1483 kfree(pcdev); 1484 1485 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n"); 1486 1487 return 0; 1488} 1489 1490static struct platform_driver mx2_camera_driver = { 1491 .driver = { 1492 .name = MX2_CAM_DRV_NAME, 1493 }, 1494 .remove = __devexit_p(mx2_camera_remove), 1495}; 1496 1497 1498static int __init mx2_camera_init(void) 1499{ 1500 return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe); 1501} 1502 1503static void __exit mx2_camera_exit(void) 1504{ 1505 return platform_driver_unregister(&mx2_camera_driver); 1506} 1507 1508module_init(mx2_camera_init); 1509module_exit(mx2_camera_exit); 1510 1511MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver"); 1512MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>"); 1513MODULE_LICENSE("GPL"); 1514