mx2_camera.c revision cdc9d6f191d81aa1b1b34db9d3a33f779f5c5ec7
1/* 2 * V4L2 Driver for i.MX27/i.MX25 camera host 3 * 4 * Copyright (C) 2008, Sascha Hauer, Pengutronix 5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography 6 * Copyright (C) 2012, Javier Martin, Vista Silicon S.L. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14#include <linux/init.h> 15#include <linux/module.h> 16#include <linux/io.h> 17#include <linux/delay.h> 18#include <linux/slab.h> 19#include <linux/dma-mapping.h> 20#include <linux/errno.h> 21#include <linux/fs.h> 22#include <linux/interrupt.h> 23#include <linux/kernel.h> 24#include <linux/mm.h> 25#include <linux/moduleparam.h> 26#include <linux/time.h> 27#include <linux/device.h> 28#include <linux/platform_device.h> 29#include <linux/mutex.h> 30#include <linux/clk.h> 31 32#include <media/v4l2-common.h> 33#include <media/v4l2-dev.h> 34#include <media/videobuf2-core.h> 35#include <media/videobuf2-dma-contig.h> 36#include <media/soc_camera.h> 37#include <media/soc_mediabus.h> 38 39#include <linux/videodev2.h> 40 41#include <mach/mx2_cam.h> 42#include <mach/hardware.h> 43 44#include <asm/dma.h> 45 46#define MX2_CAM_DRV_NAME "mx2-camera" 47#define MX2_CAM_VERSION "0.0.6" 48#define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera" 49 50/* reset values */ 51#define CSICR1_RESET_VAL 0x40000800 52#define CSICR2_RESET_VAL 0x0 53#define CSICR3_RESET_VAL 0x0 54 55/* csi control reg 1 */ 56#define CSICR1_SWAP16_EN (1 << 31) 57#define CSICR1_EXT_VSYNC (1 << 30) 58#define CSICR1_EOF_INTEN (1 << 29) 59#define CSICR1_PRP_IF_EN (1 << 28) 60#define CSICR1_CCIR_MODE (1 << 27) 61#define CSICR1_COF_INTEN (1 << 26) 62#define CSICR1_SF_OR_INTEN (1 << 25) 63#define CSICR1_RF_OR_INTEN (1 << 24) 64#define CSICR1_STATFF_LEVEL (3 << 22) 65#define CSICR1_STATFF_INTEN (1 << 21) 66#define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */ 67#define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */ 68#define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */ 69#define CSICR1_RXFF_INTEN (1 << 18) 70#define CSICR1_SOF_POL (1 << 17) 71#define CSICR1_SOF_INTEN (1 << 16) 72#define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12) 73#define CSICR1_HSYNC_POL (1 << 11) 74#define CSICR1_CCIR_EN (1 << 10) 75#define CSICR1_MCLKEN (1 << 9) 76#define CSICR1_FCC (1 << 8) 77#define CSICR1_PACK_DIR (1 << 7) 78#define CSICR1_CLR_STATFIFO (1 << 6) 79#define CSICR1_CLR_RXFIFO (1 << 5) 80#define CSICR1_GCLK_MODE (1 << 4) 81#define CSICR1_INV_DATA (1 << 3) 82#define CSICR1_INV_PCLK (1 << 2) 83#define CSICR1_REDGE (1 << 1) 84 85#define SHIFT_STATFF_LEVEL 22 86#define SHIFT_RXFF_LEVEL 19 87#define SHIFT_MCLKDIV 12 88 89/* control reg 3 */ 90#define CSICR3_FRMCNT (0xFFFF << 16) 91#define CSICR3_FRMCNT_RST (1 << 15) 92#define CSICR3_DMA_REFLASH_RFF (1 << 14) 93#define CSICR3_DMA_REFLASH_SFF (1 << 13) 94#define CSICR3_DMA_REQ_EN_RFF (1 << 12) 95#define CSICR3_DMA_REQ_EN_SFF (1 << 11) 96#define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */ 97#define CSICR3_CSI_SUP (1 << 3) 98#define CSICR3_ZERO_PACK_EN (1 << 2) 99#define CSICR3_ECC_INT_EN (1 << 1) 100#define CSICR3_ECC_AUTO_EN (1 << 0) 101 102#define SHIFT_FRMCNT 16 103 104/* csi status reg */ 105#define CSISR_SFF_OR_INT (1 << 25) 106#define CSISR_RFF_OR_INT (1 << 24) 107#define CSISR_STATFF_INT (1 << 21) 108#define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */ 109#define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */ 110#define CSISR_RXFF_INT (1 << 18) 111#define CSISR_EOF_INT (1 << 17) 112#define CSISR_SOF_INT (1 << 16) 113#define CSISR_F2_INT (1 << 15) 114#define CSISR_F1_INT (1 << 14) 115#define CSISR_COF_INT (1 << 13) 116#define CSISR_ECC_INT (1 << 1) 117#define CSISR_DRDY (1 << 0) 118 119#define CSICR1 0x00 120#define CSICR2 0x04 121#define CSISR (cpu_is_mx27() ? 0x08 : 0x18) 122#define CSISTATFIFO 0x0c 123#define CSIRFIFO 0x10 124#define CSIRXCNT 0x14 125#define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08) 126#define CSIDMASA_STATFIFO 0x20 127#define CSIDMATA_STATFIFO 0x24 128#define CSIDMASA_FB1 0x28 129#define CSIDMASA_FB2 0x2c 130#define CSIFBUF_PARA 0x30 131#define CSIIMAG_PARA 0x34 132 133/* EMMA PrP */ 134#define PRP_CNTL 0x00 135#define PRP_INTR_CNTL 0x04 136#define PRP_INTRSTATUS 0x08 137#define PRP_SOURCE_Y_PTR 0x0c 138#define PRP_SOURCE_CB_PTR 0x10 139#define PRP_SOURCE_CR_PTR 0x14 140#define PRP_DEST_RGB1_PTR 0x18 141#define PRP_DEST_RGB2_PTR 0x1c 142#define PRP_DEST_Y_PTR 0x20 143#define PRP_DEST_CB_PTR 0x24 144#define PRP_DEST_CR_PTR 0x28 145#define PRP_SRC_FRAME_SIZE 0x2c 146#define PRP_DEST_CH1_LINE_STRIDE 0x30 147#define PRP_SRC_PIXEL_FORMAT_CNTL 0x34 148#define PRP_CH1_PIXEL_FORMAT_CNTL 0x38 149#define PRP_CH1_OUT_IMAGE_SIZE 0x3c 150#define PRP_CH2_OUT_IMAGE_SIZE 0x40 151#define PRP_SRC_LINE_STRIDE 0x44 152#define PRP_CSC_COEF_012 0x48 153#define PRP_CSC_COEF_345 0x4c 154#define PRP_CSC_COEF_678 0x50 155#define PRP_CH1_RZ_HORI_COEF1 0x54 156#define PRP_CH1_RZ_HORI_COEF2 0x58 157#define PRP_CH1_RZ_HORI_VALID 0x5c 158#define PRP_CH1_RZ_VERT_COEF1 0x60 159#define PRP_CH1_RZ_VERT_COEF2 0x64 160#define PRP_CH1_RZ_VERT_VALID 0x68 161#define PRP_CH2_RZ_HORI_COEF1 0x6c 162#define PRP_CH2_RZ_HORI_COEF2 0x70 163#define PRP_CH2_RZ_HORI_VALID 0x74 164#define PRP_CH2_RZ_VERT_COEF1 0x78 165#define PRP_CH2_RZ_VERT_COEF2 0x7c 166#define PRP_CH2_RZ_VERT_VALID 0x80 167 168#define PRP_CNTL_CH1EN (1 << 0) 169#define PRP_CNTL_CH2EN (1 << 1) 170#define PRP_CNTL_CSIEN (1 << 2) 171#define PRP_CNTL_DATA_IN_YUV420 (0 << 3) 172#define PRP_CNTL_DATA_IN_YUV422 (1 << 3) 173#define PRP_CNTL_DATA_IN_RGB16 (2 << 3) 174#define PRP_CNTL_DATA_IN_RGB32 (3 << 3) 175#define PRP_CNTL_CH1_OUT_RGB8 (0 << 5) 176#define PRP_CNTL_CH1_OUT_RGB16 (1 << 5) 177#define PRP_CNTL_CH1_OUT_RGB32 (2 << 5) 178#define PRP_CNTL_CH1_OUT_YUV422 (3 << 5) 179#define PRP_CNTL_CH2_OUT_YUV420 (0 << 7) 180#define PRP_CNTL_CH2_OUT_YUV422 (1 << 7) 181#define PRP_CNTL_CH2_OUT_YUV444 (2 << 7) 182#define PRP_CNTL_CH1_LEN (1 << 9) 183#define PRP_CNTL_CH2_LEN (1 << 10) 184#define PRP_CNTL_SKIP_FRAME (1 << 11) 185#define PRP_CNTL_SWRST (1 << 12) 186#define PRP_CNTL_CLKEN (1 << 13) 187#define PRP_CNTL_WEN (1 << 14) 188#define PRP_CNTL_CH1BYP (1 << 15) 189#define PRP_CNTL_IN_TSKIP(x) ((x) << 16) 190#define PRP_CNTL_CH1_TSKIP(x) ((x) << 19) 191#define PRP_CNTL_CH2_TSKIP(x) ((x) << 22) 192#define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25) 193#define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27) 194#define PRP_CNTL_CH2B1EN (1 << 29) 195#define PRP_CNTL_CH2B2EN (1 << 30) 196#define PRP_CNTL_CH2FEN (1 << 31) 197 198/* IRQ Enable and status register */ 199#define PRP_INTR_RDERR (1 << 0) 200#define PRP_INTR_CH1WERR (1 << 1) 201#define PRP_INTR_CH2WERR (1 << 2) 202#define PRP_INTR_CH1FC (1 << 3) 203#define PRP_INTR_CH2FC (1 << 5) 204#define PRP_INTR_LBOVF (1 << 7) 205#define PRP_INTR_CH2OVF (1 << 8) 206 207#define MAX_VIDEO_MEM 16 208 209struct mx2_prp_cfg { 210 int channel; 211 u32 in_fmt; 212 u32 out_fmt; 213 u32 src_pixel; 214 u32 ch1_pixel; 215 u32 irq_flags; 216}; 217 218/* prp configuration for a client-host fmt pair */ 219struct mx2_fmt_cfg { 220 enum v4l2_mbus_pixelcode in_fmt; 221 u32 out_fmt; 222 struct mx2_prp_cfg cfg; 223}; 224 225enum mx2_buffer_state { 226 MX2_STATE_QUEUED, 227 MX2_STATE_ACTIVE, 228 MX2_STATE_DONE, 229}; 230 231/* buffer for one video frame */ 232struct mx2_buffer { 233 /* common v4l buffer stuff -- must be first */ 234 struct vb2_buffer vb; 235 struct list_head queue; 236 enum mx2_buffer_state state; 237 238 int bufnum; 239 bool discard; 240}; 241 242struct mx2_camera_dev { 243 struct device *dev; 244 struct soc_camera_host soc_host; 245 struct soc_camera_device *icd; 246 struct clk *clk_csi, *clk_emma; 247 248 unsigned int irq_csi, irq_emma; 249 void __iomem *base_csi, *base_emma; 250 unsigned long base_dma; 251 252 struct mx2_camera_platform_data *pdata; 253 struct resource *res_csi, *res_emma; 254 unsigned long platform_flags; 255 256 struct list_head capture; 257 struct list_head active_bufs; 258 struct list_head discard; 259 260 spinlock_t lock; 261 262 int dma; 263 struct mx2_buffer *active; 264 struct mx2_buffer *fb1_active; 265 struct mx2_buffer *fb2_active; 266 267 u32 csicr1; 268 269 struct mx2_buffer buf_discard[2]; 270 void *discard_buffer; 271 dma_addr_t discard_buffer_dma; 272 size_t discard_size; 273 struct mx2_fmt_cfg *emma_prp; 274 u32 frame_count; 275 struct vb2_alloc_ctx *alloc_ctx; 276}; 277 278static struct mx2_fmt_cfg mx27_emma_prp_table[] = { 279 /* 280 * This is a generic configuration which is valid for most 281 * prp input-output format combinations. 282 * We set the incomming and outgoing pixelformat to a 283 * 16 Bit wide format and adjust the bytesperline 284 * accordingly. With this configuration the inputdata 285 * will not be changed by the emma and could be any type 286 * of 16 Bit Pixelformat. 287 */ 288 { 289 .in_fmt = 0, 290 .out_fmt = 0, 291 .cfg = { 292 .channel = 1, 293 .in_fmt = PRP_CNTL_DATA_IN_RGB16, 294 .out_fmt = PRP_CNTL_CH1_OUT_RGB16, 295 .src_pixel = 0x2ca00565, /* RGB565 */ 296 .ch1_pixel = 0x2ca00565, /* RGB565 */ 297 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR | 298 PRP_INTR_CH1FC | PRP_INTR_LBOVF, 299 } 300 }, 301 { 302 .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8, 303 .out_fmt = V4L2_PIX_FMT_YUV420, 304 .cfg = { 305 .channel = 2, 306 .in_fmt = PRP_CNTL_DATA_IN_YUV422, 307 .out_fmt = PRP_CNTL_CH2_OUT_YUV420, 308 .src_pixel = 0x22000888, /* YUV422 (YUYV) */ 309 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR | 310 PRP_INTR_CH2FC | PRP_INTR_LBOVF | 311 PRP_INTR_CH2OVF, 312 } 313 }, 314}; 315 316static struct mx2_fmt_cfg *mx27_emma_prp_get_format( 317 enum v4l2_mbus_pixelcode in_fmt, 318 u32 out_fmt) 319{ 320 int i; 321 322 for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++) 323 if ((mx27_emma_prp_table[i].in_fmt == in_fmt) && 324 (mx27_emma_prp_table[i].out_fmt == out_fmt)) { 325 return &mx27_emma_prp_table[i]; 326 } 327 /* If no match return the most generic configuration */ 328 return &mx27_emma_prp_table[0]; 329}; 330 331static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev, 332 unsigned long phys, int bufnum) 333{ 334 struct mx2_fmt_cfg *prp = pcdev->emma_prp; 335 336 if (prp->cfg.channel == 1) { 337 writel(phys, pcdev->base_emma + 338 PRP_DEST_RGB1_PTR + 4 * bufnum); 339 } else { 340 writel(phys, pcdev->base_emma + 341 PRP_DEST_Y_PTR - 0x14 * bufnum); 342 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) { 343 u32 imgsize = pcdev->icd->user_height * 344 pcdev->icd->user_width; 345 346 writel(phys + imgsize, pcdev->base_emma + 347 PRP_DEST_CB_PTR - 0x14 * bufnum); 348 writel(phys + ((5 * imgsize) / 4), pcdev->base_emma + 349 PRP_DEST_CR_PTR - 0x14 * bufnum); 350 } 351 } 352} 353 354static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev) 355{ 356 unsigned long flags; 357 358 clk_disable(pcdev->clk_csi); 359 writel(0, pcdev->base_csi + CSICR1); 360 if (cpu_is_mx27()) { 361 writel(0, pcdev->base_emma + PRP_CNTL); 362 } else if (cpu_is_mx25()) { 363 spin_lock_irqsave(&pcdev->lock, flags); 364 pcdev->fb1_active = NULL; 365 pcdev->fb2_active = NULL; 366 writel(0, pcdev->base_csi + CSIDMASA_FB1); 367 writel(0, pcdev->base_csi + CSIDMASA_FB2); 368 spin_unlock_irqrestore(&pcdev->lock, flags); 369 } 370} 371 372/* 373 * The following two functions absolutely depend on the fact, that 374 * there can be only one camera on mx2 camera sensor interface 375 */ 376static int mx2_camera_add_device(struct soc_camera_device *icd) 377{ 378 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 379 struct mx2_camera_dev *pcdev = ici->priv; 380 int ret; 381 u32 csicr1; 382 383 if (pcdev->icd) 384 return -EBUSY; 385 386 ret = clk_enable(pcdev->clk_csi); 387 if (ret < 0) 388 return ret; 389 390 csicr1 = CSICR1_MCLKEN; 391 392 if (cpu_is_mx27()) { 393 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC | 394 CSICR1_RXFF_LEVEL(0); 395 } else if (cpu_is_mx27()) 396 csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2); 397 398 pcdev->csicr1 = csicr1; 399 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 400 401 pcdev->icd = icd; 402 pcdev->frame_count = 0; 403 404 dev_info(icd->parent, "Camera driver attached to camera %d\n", 405 icd->devnum); 406 407 return 0; 408} 409 410static void mx2_camera_remove_device(struct soc_camera_device *icd) 411{ 412 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 413 struct mx2_camera_dev *pcdev = ici->priv; 414 415 BUG_ON(icd != pcdev->icd); 416 417 dev_info(icd->parent, "Camera driver detached from camera %d\n", 418 icd->devnum); 419 420 mx2_camera_deactivate(pcdev); 421 422 pcdev->icd = NULL; 423} 424 425static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb, 426 int state) 427{ 428 struct vb2_buffer *vb; 429 struct mx2_buffer *buf; 430 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active : 431 &pcdev->fb2_active; 432 u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2; 433 unsigned long flags; 434 435 spin_lock_irqsave(&pcdev->lock, flags); 436 437 if (*fb_active == NULL) 438 goto out; 439 440 vb = &(*fb_active)->vb; 441 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, 442 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0)); 443 444 do_gettimeofday(&vb->v4l2_buf.timestamp); 445 vb->v4l2_buf.sequence++; 446 vb2_buffer_done(vb, VB2_BUF_STATE_DONE); 447 448 if (list_empty(&pcdev->capture)) { 449 buf = NULL; 450 writel(0, pcdev->base_csi + fb_reg); 451 } else { 452 buf = list_entry(pcdev->capture.next, struct mx2_buffer, 453 queue); 454 vb = &buf->vb; 455 list_del(&buf->queue); 456 buf->state = MX2_STATE_ACTIVE; 457 writel(vb2_dma_contig_plane_dma_addr(vb, 0), 458 pcdev->base_csi + fb_reg); 459 } 460 461 *fb_active = buf; 462 463out: 464 spin_unlock_irqrestore(&pcdev->lock, flags); 465} 466 467static irqreturn_t mx25_camera_irq(int irq_csi, void *data) 468{ 469 struct mx2_camera_dev *pcdev = data; 470 u32 status = readl(pcdev->base_csi + CSISR); 471 472 if (status & CSISR_DMA_TSF_FB1_INT) 473 mx25_camera_frame_done(pcdev, 1, MX2_STATE_DONE); 474 else if (status & CSISR_DMA_TSF_FB2_INT) 475 mx25_camera_frame_done(pcdev, 2, MX2_STATE_DONE); 476 477 /* FIXME: handle CSISR_RFF_OR_INT */ 478 479 writel(status, pcdev->base_csi + CSISR); 480 481 return IRQ_HANDLED; 482} 483 484/* 485 * Videobuf operations 486 */ 487static int mx2_videobuf_setup(struct vb2_queue *vq, 488 const struct v4l2_format *fmt, 489 unsigned int *count, unsigned int *num_planes, 490 unsigned int sizes[], void *alloc_ctxs[]) 491{ 492 struct soc_camera_device *icd = soc_camera_from_vb2q(vq); 493 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 494 struct mx2_camera_dev *pcdev = ici->priv; 495 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, 496 icd->current_fmt->host_fmt); 497 498 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]); 499 500 /* TODO: support for VIDIOC_CREATE_BUFS not ready */ 501 if (fmt != NULL) 502 return -ENOTTY; 503 504 if (bytes_per_line < 0) 505 return bytes_per_line; 506 507 alloc_ctxs[0] = pcdev->alloc_ctx; 508 509 sizes[0] = bytes_per_line * icd->user_height; 510 511 if (0 == *count) 512 *count = 32; 513 if (!*num_planes && 514 sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024) 515 *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0]; 516 517 *num_planes = 1; 518 519 return 0; 520} 521 522static int mx2_videobuf_prepare(struct vb2_buffer *vb) 523{ 524 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); 525 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, 526 icd->current_fmt->host_fmt); 527 int ret = 0; 528 529 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__, 530 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0)); 531 532 if (bytes_per_line < 0) 533 return bytes_per_line; 534 535#ifdef DEBUG 536 /* 537 * This can be useful if you want to see if we actually fill 538 * the buffer with something 539 */ 540 memset((void *)vb2_plane_vaddr(vb, 0), 541 0xaa, vb2_get_plane_payload(vb, 0)); 542#endif 543 544 vb2_set_plane_payload(vb, 0, bytes_per_line * icd->user_height); 545 if (vb2_plane_vaddr(vb, 0) && 546 vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) { 547 ret = -EINVAL; 548 goto out; 549 } 550 551 return 0; 552 553out: 554 return ret; 555} 556 557static void mx2_videobuf_queue(struct vb2_buffer *vb) 558{ 559 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); 560 struct soc_camera_host *ici = 561 to_soc_camera_host(icd->parent); 562 struct mx2_camera_dev *pcdev = ici->priv; 563 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 564 unsigned long flags; 565 566 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__, 567 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0)); 568 569 spin_lock_irqsave(&pcdev->lock, flags); 570 571 buf->state = MX2_STATE_QUEUED; 572 list_add_tail(&buf->queue, &pcdev->capture); 573 574 if (cpu_is_mx25()) { 575 u32 csicr3, dma_inten = 0; 576 577 if (pcdev->fb1_active == NULL) { 578 writel(vb2_dma_contig_plane_dma_addr(vb, 0), 579 pcdev->base_csi + CSIDMASA_FB1); 580 pcdev->fb1_active = buf; 581 dma_inten = CSICR1_FB1_DMA_INTEN; 582 } else if (pcdev->fb2_active == NULL) { 583 writel(vb2_dma_contig_plane_dma_addr(vb, 0), 584 pcdev->base_csi + CSIDMASA_FB2); 585 pcdev->fb2_active = buf; 586 dma_inten = CSICR1_FB2_DMA_INTEN; 587 } 588 589 if (dma_inten) { 590 list_del(&buf->queue); 591 buf->state = MX2_STATE_ACTIVE; 592 593 csicr3 = readl(pcdev->base_csi + CSICR3); 594 595 /* Reflash DMA */ 596 writel(csicr3 | CSICR3_DMA_REFLASH_RFF, 597 pcdev->base_csi + CSICR3); 598 599 /* clear & enable interrupts */ 600 writel(dma_inten, pcdev->base_csi + CSISR); 601 pcdev->csicr1 |= dma_inten; 602 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 603 604 /* enable DMA */ 605 csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1); 606 writel(csicr3, pcdev->base_csi + CSICR3); 607 } 608 } 609 610 spin_unlock_irqrestore(&pcdev->lock, flags); 611} 612 613static void mx2_videobuf_release(struct vb2_buffer *vb) 614{ 615 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); 616 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 617 struct mx2_camera_dev *pcdev = ici->priv; 618 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 619 unsigned long flags; 620 621#ifdef DEBUG 622 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__, 623 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0)); 624 625 switch (buf->state) { 626 case MX2_STATE_ACTIVE: 627 dev_info(icd->parent, "%s (active)\n", __func__); 628 break; 629 case MX2_STATE_QUEUED: 630 dev_info(icd->parent, "%s (queued)\n", __func__); 631 break; 632 default: 633 dev_info(icd->parent, "%s (unknown) %d\n", __func__, 634 buf->state); 635 break; 636 } 637#endif 638 639 /* 640 * Terminate only queued but inactive buffers. Active buffers are 641 * released when they become inactive after videobuf_waiton(). 642 * 643 * FIXME: implement forced termination of active buffers for mx27 and 644 * mx27 eMMA, so that the user won't get stuck in an uninterruptible 645 * state. This requires a specific handling for each of the these DMA 646 * types. 647 */ 648 649 spin_lock_irqsave(&pcdev->lock, flags); 650 if (cpu_is_mx25() && buf->state == MX2_STATE_ACTIVE) { 651 if (pcdev->fb1_active == buf) { 652 pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN; 653 writel(0, pcdev->base_csi + CSIDMASA_FB1); 654 pcdev->fb1_active = NULL; 655 } else if (pcdev->fb2_active == buf) { 656 pcdev->csicr1 &= ~CSICR1_FB2_DMA_INTEN; 657 writel(0, pcdev->base_csi + CSIDMASA_FB2); 658 pcdev->fb2_active = NULL; 659 } 660 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 661 } 662 spin_unlock_irqrestore(&pcdev->lock, flags); 663} 664 665static void mx27_camera_emma_buf_init(struct soc_camera_device *icd, 666 int bytesperline) 667{ 668 struct soc_camera_host *ici = 669 to_soc_camera_host(icd->parent); 670 struct mx2_camera_dev *pcdev = ici->priv; 671 struct mx2_fmt_cfg *prp = pcdev->emma_prp; 672 673 writel((icd->user_width << 16) | icd->user_height, 674 pcdev->base_emma + PRP_SRC_FRAME_SIZE); 675 writel(prp->cfg.src_pixel, 676 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL); 677 if (prp->cfg.channel == 1) { 678 writel((icd->user_width << 16) | icd->user_height, 679 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE); 680 writel(bytesperline, 681 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE); 682 writel(prp->cfg.ch1_pixel, 683 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL); 684 } else { /* channel 2 */ 685 writel((icd->user_width << 16) | icd->user_height, 686 pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE); 687 } 688 689 /* Enable interrupts */ 690 writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL); 691} 692 693static int mx2_start_streaming(struct vb2_queue *q, unsigned int count) 694{ 695 struct soc_camera_device *icd = soc_camera_from_vb2q(q); 696 struct soc_camera_host *ici = 697 to_soc_camera_host(icd->parent); 698 struct mx2_camera_dev *pcdev = ici->priv; 699 struct mx2_fmt_cfg *prp = pcdev->emma_prp; 700 struct vb2_buffer *vb; 701 struct mx2_buffer *buf; 702 unsigned long phys; 703 int bytesperline; 704 705 if (cpu_is_mx27()) { 706 unsigned long flags; 707 if (count < 2) 708 return -EINVAL; 709 710 spin_lock_irqsave(&pcdev->lock, flags); 711 712 buf = list_entry(pcdev->capture.next, 713 struct mx2_buffer, queue); 714 buf->bufnum = 0; 715 vb = &buf->vb; 716 buf->state = MX2_STATE_ACTIVE; 717 718 phys = vb2_dma_contig_plane_dma_addr(vb, 0); 719 mx27_update_emma_buf(pcdev, phys, buf->bufnum); 720 list_move_tail(pcdev->capture.next, &pcdev->active_bufs); 721 722 buf = list_entry(pcdev->capture.next, 723 struct mx2_buffer, queue); 724 buf->bufnum = 1; 725 vb = &buf->vb; 726 buf->state = MX2_STATE_ACTIVE; 727 728 phys = vb2_dma_contig_plane_dma_addr(vb, 0); 729 mx27_update_emma_buf(pcdev, phys, buf->bufnum); 730 list_move_tail(pcdev->capture.next, &pcdev->active_bufs); 731 732 bytesperline = soc_mbus_bytes_per_line(icd->user_width, 733 icd->current_fmt->host_fmt); 734 if (bytesperline < 0) 735 return bytesperline; 736 737 /* 738 * I didn't manage to properly enable/disable the prp 739 * on a per frame basis during running transfers, 740 * thus we allocate a buffer here and use it to 741 * discard frames when no buffer is available. 742 * Feel free to work on this ;) 743 */ 744 pcdev->discard_size = icd->user_height * bytesperline; 745 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev, 746 pcdev->discard_size, &pcdev->discard_buffer_dma, 747 GFP_KERNEL); 748 if (!pcdev->discard_buffer) 749 return -ENOMEM; 750 751 pcdev->buf_discard[0].discard = true; 752 list_add_tail(&pcdev->buf_discard[0].queue, 753 &pcdev->discard); 754 755 pcdev->buf_discard[1].discard = true; 756 list_add_tail(&pcdev->buf_discard[1].queue, 757 &pcdev->discard); 758 759 mx27_camera_emma_buf_init(icd, bytesperline); 760 761 if (prp->cfg.channel == 1) { 762 writel(PRP_CNTL_CH1EN | 763 PRP_CNTL_CSIEN | 764 prp->cfg.in_fmt | 765 prp->cfg.out_fmt | 766 PRP_CNTL_CH1_LEN | 767 PRP_CNTL_CH1BYP | 768 PRP_CNTL_CH1_TSKIP(0) | 769 PRP_CNTL_IN_TSKIP(0), 770 pcdev->base_emma + PRP_CNTL); 771 } else { 772 writel(PRP_CNTL_CH2EN | 773 PRP_CNTL_CSIEN | 774 prp->cfg.in_fmt | 775 prp->cfg.out_fmt | 776 PRP_CNTL_CH2_LEN | 777 PRP_CNTL_CH2_TSKIP(0) | 778 PRP_CNTL_IN_TSKIP(0), 779 pcdev->base_emma + PRP_CNTL); 780 } 781 spin_unlock_irqrestore(&pcdev->lock, flags); 782 } 783 784 return 0; 785} 786 787static int mx2_stop_streaming(struct vb2_queue *q) 788{ 789 struct soc_camera_device *icd = soc_camera_from_vb2q(q); 790 struct soc_camera_host *ici = 791 to_soc_camera_host(icd->parent); 792 struct mx2_camera_dev *pcdev = ici->priv; 793 struct mx2_fmt_cfg *prp = pcdev->emma_prp; 794 unsigned long flags; 795 void *b; 796 u32 cntl; 797 798 if (cpu_is_mx27()) { 799 spin_lock_irqsave(&pcdev->lock, flags); 800 801 cntl = readl(pcdev->base_emma + PRP_CNTL); 802 if (prp->cfg.channel == 1) { 803 writel(cntl & ~PRP_CNTL_CH1EN, 804 pcdev->base_emma + PRP_CNTL); 805 } else { 806 writel(cntl & ~PRP_CNTL_CH2EN, 807 pcdev->base_emma + PRP_CNTL); 808 } 809 INIT_LIST_HEAD(&pcdev->capture); 810 INIT_LIST_HEAD(&pcdev->active_bufs); 811 INIT_LIST_HEAD(&pcdev->discard); 812 813 b = pcdev->discard_buffer; 814 pcdev->discard_buffer = NULL; 815 816 spin_unlock_irqrestore(&pcdev->lock, flags); 817 818 dma_free_coherent(ici->v4l2_dev.dev, 819 pcdev->discard_size, b, pcdev->discard_buffer_dma); 820 } 821 822 return 0; 823} 824 825static struct vb2_ops mx2_videobuf_ops = { 826 .queue_setup = mx2_videobuf_setup, 827 .buf_prepare = mx2_videobuf_prepare, 828 .buf_queue = mx2_videobuf_queue, 829 .buf_cleanup = mx2_videobuf_release, 830 .start_streaming = mx2_start_streaming, 831 .stop_streaming = mx2_stop_streaming, 832}; 833 834static int mx2_camera_init_videobuf(struct vb2_queue *q, 835 struct soc_camera_device *icd) 836{ 837 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 838 q->io_modes = VB2_MMAP | VB2_USERPTR; 839 q->drv_priv = icd; 840 q->ops = &mx2_videobuf_ops; 841 q->mem_ops = &vb2_dma_contig_memops; 842 q->buf_struct_size = sizeof(struct mx2_buffer); 843 844 return vb2_queue_init(q); 845} 846 847#define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \ 848 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \ 849 V4L2_MBUS_VSYNC_ACTIVE_LOW | \ 850 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \ 851 V4L2_MBUS_HSYNC_ACTIVE_LOW | \ 852 V4L2_MBUS_PCLK_SAMPLE_RISING | \ 853 V4L2_MBUS_PCLK_SAMPLE_FALLING | \ 854 V4L2_MBUS_DATA_ACTIVE_HIGH | \ 855 V4L2_MBUS_DATA_ACTIVE_LOW) 856 857static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev) 858{ 859 u32 cntl; 860 int count = 0; 861 862 cntl = readl(pcdev->base_emma + PRP_CNTL); 863 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL); 864 while (count++ < 100) { 865 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST)) 866 return 0; 867 barrier(); 868 udelay(1); 869 } 870 871 return -ETIMEDOUT; 872} 873 874static int mx2_camera_set_bus_param(struct soc_camera_device *icd) 875{ 876 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 877 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 878 struct mx2_camera_dev *pcdev = ici->priv; 879 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; 880 unsigned long common_flags; 881 int ret; 882 int bytesperline; 883 u32 csicr1 = pcdev->csicr1; 884 885 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); 886 if (!ret) { 887 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS); 888 if (!common_flags) { 889 dev_warn(icd->parent, 890 "Flags incompatible: camera 0x%x, host 0x%x\n", 891 cfg.flags, MX2_BUS_FLAGS); 892 return -EINVAL; 893 } 894 } else if (ret != -ENOIOCTLCMD) { 895 return ret; 896 } else { 897 common_flags = MX2_BUS_FLAGS; 898 } 899 900 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) && 901 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) { 902 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH) 903 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW; 904 else 905 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH; 906 } 907 908 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) && 909 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) { 910 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING) 911 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING; 912 else 913 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING; 914 } 915 916 cfg.flags = common_flags; 917 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg); 918 if (ret < 0 && ret != -ENOIOCTLCMD) { 919 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n", 920 common_flags, ret); 921 return ret; 922 } 923 924 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 925 csicr1 |= CSICR1_REDGE; 926 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 927 csicr1 |= CSICR1_SOF_POL; 928 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) 929 csicr1 |= CSICR1_HSYNC_POL; 930 if (pcdev->platform_flags & MX2_CAMERA_SWAP16) 931 csicr1 |= CSICR1_SWAP16_EN; 932 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC) 933 csicr1 |= CSICR1_EXT_VSYNC; 934 if (pcdev->platform_flags & MX2_CAMERA_CCIR) 935 csicr1 |= CSICR1_CCIR_EN; 936 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE) 937 csicr1 |= CSICR1_CCIR_MODE; 938 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK) 939 csicr1 |= CSICR1_GCLK_MODE; 940 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA) 941 csicr1 |= CSICR1_INV_DATA; 942 if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB) 943 csicr1 |= CSICR1_PACK_DIR; 944 945 pcdev->csicr1 = csicr1; 946 947 bytesperline = soc_mbus_bytes_per_line(icd->user_width, 948 icd->current_fmt->host_fmt); 949 if (bytesperline < 0) 950 return bytesperline; 951 952 if (cpu_is_mx27()) { 953 ret = mx27_camera_emma_prp_reset(pcdev); 954 if (ret) 955 return ret; 956 } else if (cpu_is_mx25()) { 957 writel((bytesperline * icd->user_height) >> 2, 958 pcdev->base_csi + CSIRXCNT); 959 writel((bytesperline << 16) | icd->user_height, 960 pcdev->base_csi + CSIIMAG_PARA); 961 } 962 963 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 964 965 return 0; 966} 967 968static int mx2_camera_set_crop(struct soc_camera_device *icd, 969 struct v4l2_crop *a) 970{ 971 struct v4l2_rect *rect = &a->c; 972 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 973 struct v4l2_mbus_framefmt mf; 974 int ret; 975 976 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096); 977 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096); 978 979 ret = v4l2_subdev_call(sd, video, s_crop, a); 980 if (ret < 0) 981 return ret; 982 983 /* The capture device might have changed its output */ 984 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); 985 if (ret < 0) 986 return ret; 987 988 dev_dbg(icd->parent, "Sensor cropped %dx%d\n", 989 mf.width, mf.height); 990 991 icd->user_width = mf.width; 992 icd->user_height = mf.height; 993 994 return ret; 995} 996 997static int mx2_camera_get_formats(struct soc_camera_device *icd, 998 unsigned int idx, 999 struct soc_camera_format_xlate *xlate) 1000{ 1001 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1002 const struct soc_mbus_pixelfmt *fmt; 1003 struct device *dev = icd->parent; 1004 enum v4l2_mbus_pixelcode code; 1005 int ret, formats = 0; 1006 1007 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code); 1008 if (ret < 0) 1009 /* no more formats */ 1010 return 0; 1011 1012 fmt = soc_mbus_get_fmtdesc(code); 1013 if (!fmt) { 1014 dev_err(dev, "Invalid format code #%u: %d\n", idx, code); 1015 return 0; 1016 } 1017 1018 if (code == V4L2_MBUS_FMT_YUYV8_2X8) { 1019 formats++; 1020 if (xlate) { 1021 /* 1022 * CH2 can output YUV420 which is a standard format in 1023 * soc_mediabus.c 1024 */ 1025 xlate->host_fmt = 1026 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8); 1027 xlate->code = code; 1028 dev_dbg(dev, "Providing host format %s for sensor code %d\n", 1029 xlate->host_fmt->name, code); 1030 xlate++; 1031 } 1032 } 1033 1034 /* Generic pass-trough */ 1035 formats++; 1036 if (xlate) { 1037 xlate->host_fmt = fmt; 1038 xlate->code = code; 1039 xlate++; 1040 } 1041 return formats; 1042} 1043 1044static int mx2_camera_set_fmt(struct soc_camera_device *icd, 1045 struct v4l2_format *f) 1046{ 1047 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 1048 struct mx2_camera_dev *pcdev = ici->priv; 1049 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1050 const struct soc_camera_format_xlate *xlate; 1051 struct v4l2_pix_format *pix = &f->fmt.pix; 1052 struct v4l2_mbus_framefmt mf; 1053 int ret; 1054 1055 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); 1056 if (!xlate) { 1057 dev_warn(icd->parent, "Format %x not found\n", 1058 pix->pixelformat); 1059 return -EINVAL; 1060 } 1061 1062 mf.width = pix->width; 1063 mf.height = pix->height; 1064 mf.field = pix->field; 1065 mf.colorspace = pix->colorspace; 1066 mf.code = xlate->code; 1067 1068 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); 1069 if (ret < 0 && ret != -ENOIOCTLCMD) 1070 return ret; 1071 1072 if (mf.code != xlate->code) 1073 return -EINVAL; 1074 1075 pix->width = mf.width; 1076 pix->height = mf.height; 1077 pix->field = mf.field; 1078 pix->colorspace = mf.colorspace; 1079 icd->current_fmt = xlate; 1080 1081 if (cpu_is_mx27()) 1082 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code, 1083 xlate->host_fmt->fourcc); 1084 1085 return 0; 1086} 1087 1088static int mx2_camera_try_fmt(struct soc_camera_device *icd, 1089 struct v4l2_format *f) 1090{ 1091 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 1092 const struct soc_camera_format_xlate *xlate; 1093 struct v4l2_pix_format *pix = &f->fmt.pix; 1094 struct v4l2_mbus_framefmt mf; 1095 __u32 pixfmt = pix->pixelformat; 1096 unsigned int width_limit; 1097 int ret; 1098 1099 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); 1100 if (pixfmt && !xlate) { 1101 dev_warn(icd->parent, "Format %x not found\n", pixfmt); 1102 return -EINVAL; 1103 } 1104 1105 /* FIXME: implement MX27 limits */ 1106 1107 /* limit to MX25 hardware capabilities */ 1108 if (cpu_is_mx25()) { 1109 if (xlate->host_fmt->bits_per_sample <= 8) 1110 width_limit = 0xffff * 4; 1111 else 1112 width_limit = 0xffff * 2; 1113 /* CSIIMAG_PARA limit */ 1114 if (pix->width > width_limit) 1115 pix->width = width_limit; 1116 if (pix->height > 0xffff) 1117 pix->height = 0xffff; 1118 1119 pix->bytesperline = soc_mbus_bytes_per_line(pix->width, 1120 xlate->host_fmt); 1121 if (pix->bytesperline < 0) 1122 return pix->bytesperline; 1123 pix->sizeimage = pix->height * pix->bytesperline; 1124 /* Check against the CSIRXCNT limit */ 1125 if (pix->sizeimage > 4 * 0x3ffff) { 1126 /* Adjust geometry, preserve aspect ratio */ 1127 unsigned int new_height = int_sqrt(4 * 0x3ffff * 1128 pix->height / pix->bytesperline); 1129 pix->width = new_height * pix->width / pix->height; 1130 pix->height = new_height; 1131 pix->bytesperline = soc_mbus_bytes_per_line(pix->width, 1132 xlate->host_fmt); 1133 BUG_ON(pix->bytesperline < 0); 1134 } 1135 } 1136 1137 /* limit to sensor capabilities */ 1138 mf.width = pix->width; 1139 mf.height = pix->height; 1140 mf.field = pix->field; 1141 mf.colorspace = pix->colorspace; 1142 mf.code = xlate->code; 1143 1144 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); 1145 if (ret < 0) 1146 return ret; 1147 1148 if (mf.field == V4L2_FIELD_ANY) 1149 mf.field = V4L2_FIELD_NONE; 1150 /* 1151 * Driver supports interlaced images provided they have 1152 * both fields so that they can be processed as if they 1153 * were progressive. 1154 */ 1155 if (mf.field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf.field)) { 1156 dev_err(icd->parent, "Field type %d unsupported.\n", 1157 mf.field); 1158 return -EINVAL; 1159 } 1160 1161 pix->width = mf.width; 1162 pix->height = mf.height; 1163 pix->field = mf.field; 1164 pix->colorspace = mf.colorspace; 1165 1166 return 0; 1167} 1168 1169static int mx2_camera_querycap(struct soc_camera_host *ici, 1170 struct v4l2_capability *cap) 1171{ 1172 /* cap->name is set by the friendly caller:-> */ 1173 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card)); 1174 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; 1175 1176 return 0; 1177} 1178 1179static unsigned int mx2_camera_poll(struct file *file, poll_table *pt) 1180{ 1181 struct soc_camera_device *icd = file->private_data; 1182 1183 return vb2_poll(&icd->vb2_vidq, file, pt); 1184} 1185 1186static struct soc_camera_host_ops mx2_soc_camera_host_ops = { 1187 .owner = THIS_MODULE, 1188 .add = mx2_camera_add_device, 1189 .remove = mx2_camera_remove_device, 1190 .set_fmt = mx2_camera_set_fmt, 1191 .set_crop = mx2_camera_set_crop, 1192 .get_formats = mx2_camera_get_formats, 1193 .try_fmt = mx2_camera_try_fmt, 1194 .init_videobuf2 = mx2_camera_init_videobuf, 1195 .poll = mx2_camera_poll, 1196 .querycap = mx2_camera_querycap, 1197 .set_bus_param = mx2_camera_set_bus_param, 1198}; 1199 1200static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev, 1201 int bufnum) 1202{ 1203 struct mx2_fmt_cfg *prp = pcdev->emma_prp; 1204 struct mx2_buffer *buf; 1205 struct vb2_buffer *vb; 1206 unsigned long phys; 1207 1208 buf = list_entry(pcdev->active_bufs.next, 1209 struct mx2_buffer, queue); 1210 1211 BUG_ON(buf->bufnum != bufnum); 1212 1213 if (buf->discard) { 1214 /* 1215 * Discard buffer must not be returned to user space. 1216 * Just return it to the discard queue. 1217 */ 1218 list_move_tail(pcdev->active_bufs.next, &pcdev->discard); 1219 } else { 1220 vb = &buf->vb; 1221#ifdef DEBUG 1222 phys = vb2_dma_contig_plane_dma_addr(vb, 0); 1223 if (prp->cfg.channel == 1) { 1224 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + 1225 4 * bufnum) != phys) { 1226 dev_err(pcdev->dev, "%p != %p\n", phys, 1227 readl(pcdev->base_emma + 1228 PRP_DEST_RGB1_PTR + 1229 4 * bufnum)); 1230 } 1231 } else { 1232 if (readl(pcdev->base_emma + PRP_DEST_Y_PTR - 1233 0x14 * bufnum) != phys) { 1234 dev_err(pcdev->dev, "%p != %p\n", phys, 1235 readl(pcdev->base_emma + 1236 PRP_DEST_Y_PTR - 1237 0x14 * bufnum)); 1238 } 1239 } 1240#endif 1241 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb, 1242 vb2_plane_vaddr(vb, 0), 1243 vb2_get_plane_payload(vb, 0)); 1244 1245 list_del_init(&buf->queue); 1246 do_gettimeofday(&vb->v4l2_buf.timestamp); 1247 vb->v4l2_buf.sequence = pcdev->frame_count; 1248 vb2_buffer_done(vb, VB2_BUF_STATE_DONE); 1249 } 1250 1251 pcdev->frame_count++; 1252 1253 if (list_empty(&pcdev->capture)) { 1254 if (list_empty(&pcdev->discard)) { 1255 dev_warn(pcdev->dev, "%s: trying to access empty discard list\n", 1256 __func__); 1257 return; 1258 } 1259 1260 buf = list_entry(pcdev->discard.next, 1261 struct mx2_buffer, queue); 1262 buf->bufnum = bufnum; 1263 1264 list_move_tail(pcdev->discard.next, &pcdev->active_bufs); 1265 mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum); 1266 return; 1267 } 1268 1269 buf = list_entry(pcdev->capture.next, 1270 struct mx2_buffer, queue); 1271 1272 buf->bufnum = bufnum; 1273 1274 list_move_tail(pcdev->capture.next, &pcdev->active_bufs); 1275 1276 vb = &buf->vb; 1277 buf->state = MX2_STATE_ACTIVE; 1278 1279 phys = vb2_dma_contig_plane_dma_addr(vb, 0); 1280 mx27_update_emma_buf(pcdev, phys, bufnum); 1281} 1282 1283static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data) 1284{ 1285 struct mx2_camera_dev *pcdev = data; 1286 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS); 1287 struct mx2_buffer *buf; 1288 unsigned long flags; 1289 1290 spin_lock_irqsave(&pcdev->lock, flags); 1291 1292 if (list_empty(&pcdev->active_bufs)) { 1293 dev_warn(pcdev->dev, "%s: called while active list is empty\n", 1294 __func__); 1295 goto irq_ok; 1296 } 1297 1298 if (status & (1 << 7)) { /* overflow */ 1299 u32 cntl; 1300 /* 1301 * We only disable channel 1 here since this is the only 1302 * enabled channel 1303 * 1304 * FIXME: the correct DMA overflow handling should be resetting 1305 * the buffer, returning an error frame, and continuing with 1306 * the next one. 1307 */ 1308 cntl = readl(pcdev->base_emma + PRP_CNTL); 1309 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN), 1310 pcdev->base_emma + PRP_CNTL); 1311 writel(cntl, pcdev->base_emma + PRP_CNTL); 1312 } 1313 if (((status & (3 << 5)) == (3 << 5)) || 1314 ((status & (3 << 3)) == (3 << 3))) { 1315 /* 1316 * Both buffers have triggered, process the one we're expecting 1317 * to first 1318 */ 1319 buf = list_entry(pcdev->active_bufs.next, 1320 struct mx2_buffer, queue); 1321 mx27_camera_frame_done_emma(pcdev, buf->bufnum); 1322 status &= ~(1 << (6 - buf->bufnum)); /* mark processed */ 1323 } 1324 if ((status & (1 << 6)) || (status & (1 << 4))) 1325 mx27_camera_frame_done_emma(pcdev, 0); 1326 if ((status & (1 << 5)) || (status & (1 << 3))) 1327 mx27_camera_frame_done_emma(pcdev, 1); 1328 1329irq_ok: 1330 spin_unlock_irqrestore(&pcdev->lock, flags); 1331 writel(status, pcdev->base_emma + PRP_INTRSTATUS); 1332 1333 return IRQ_HANDLED; 1334} 1335 1336static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev) 1337{ 1338 struct resource *res_emma = pcdev->res_emma; 1339 int err = 0; 1340 1341 if (!request_mem_region(res_emma->start, resource_size(res_emma), 1342 MX2_CAM_DRV_NAME)) { 1343 err = -EBUSY; 1344 goto out; 1345 } 1346 1347 pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma)); 1348 if (!pcdev->base_emma) { 1349 err = -ENOMEM; 1350 goto exit_release; 1351 } 1352 1353 err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0, 1354 MX2_CAM_DRV_NAME, pcdev); 1355 if (err) { 1356 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n"); 1357 goto exit_iounmap; 1358 } 1359 1360 pcdev->clk_emma = clk_get(NULL, "emma"); 1361 if (IS_ERR(pcdev->clk_emma)) { 1362 err = PTR_ERR(pcdev->clk_emma); 1363 goto exit_free_irq; 1364 } 1365 1366 clk_enable(pcdev->clk_emma); 1367 1368 err = mx27_camera_emma_prp_reset(pcdev); 1369 if (err) 1370 goto exit_clk_emma_put; 1371 1372 return err; 1373 1374exit_clk_emma_put: 1375 clk_disable(pcdev->clk_emma); 1376 clk_put(pcdev->clk_emma); 1377exit_free_irq: 1378 free_irq(pcdev->irq_emma, pcdev); 1379exit_iounmap: 1380 iounmap(pcdev->base_emma); 1381exit_release: 1382 release_mem_region(res_emma->start, resource_size(res_emma)); 1383out: 1384 return err; 1385} 1386 1387static int __devinit mx2_camera_probe(struct platform_device *pdev) 1388{ 1389 struct mx2_camera_dev *pcdev; 1390 struct resource *res_csi, *res_emma; 1391 void __iomem *base_csi; 1392 int irq_csi, irq_emma; 1393 int err = 0; 1394 1395 dev_dbg(&pdev->dev, "initialising\n"); 1396 1397 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1398 irq_csi = platform_get_irq(pdev, 0); 1399 if (res_csi == NULL || irq_csi < 0) { 1400 dev_err(&pdev->dev, "Missing platform resources data\n"); 1401 err = -ENODEV; 1402 goto exit; 1403 } 1404 1405 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); 1406 if (!pcdev) { 1407 dev_err(&pdev->dev, "Could not allocate pcdev\n"); 1408 err = -ENOMEM; 1409 goto exit; 1410 } 1411 1412 pcdev->clk_csi = clk_get(&pdev->dev, NULL); 1413 if (IS_ERR(pcdev->clk_csi)) { 1414 err = PTR_ERR(pcdev->clk_csi); 1415 goto exit_kfree; 1416 } 1417 1418 dev_dbg(&pdev->dev, "Camera clock frequency: %ld\n", 1419 clk_get_rate(pcdev->clk_csi)); 1420 1421 pcdev->res_csi = res_csi; 1422 pcdev->pdata = pdev->dev.platform_data; 1423 if (pcdev->pdata) { 1424 long rate; 1425 1426 pcdev->platform_flags = pcdev->pdata->flags; 1427 1428 rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2); 1429 if (rate <= 0) { 1430 err = -ENODEV; 1431 goto exit_dma_free; 1432 } 1433 err = clk_set_rate(pcdev->clk_csi, rate); 1434 if (err < 0) 1435 goto exit_dma_free; 1436 } 1437 1438 INIT_LIST_HEAD(&pcdev->capture); 1439 INIT_LIST_HEAD(&pcdev->active_bufs); 1440 INIT_LIST_HEAD(&pcdev->discard); 1441 spin_lock_init(&pcdev->lock); 1442 1443 /* 1444 * Request the regions. 1445 */ 1446 if (!request_mem_region(res_csi->start, resource_size(res_csi), 1447 MX2_CAM_DRV_NAME)) { 1448 err = -EBUSY; 1449 goto exit_dma_free; 1450 } 1451 1452 base_csi = ioremap(res_csi->start, resource_size(res_csi)); 1453 if (!base_csi) { 1454 err = -ENOMEM; 1455 goto exit_release; 1456 } 1457 pcdev->irq_csi = irq_csi; 1458 pcdev->base_csi = base_csi; 1459 pcdev->base_dma = res_csi->start; 1460 pcdev->dev = &pdev->dev; 1461 1462 if (cpu_is_mx25()) { 1463 err = request_irq(pcdev->irq_csi, mx25_camera_irq, 0, 1464 MX2_CAM_DRV_NAME, pcdev); 1465 if (err) { 1466 dev_err(pcdev->dev, "Camera interrupt register failed \n"); 1467 goto exit_iounmap; 1468 } 1469 } 1470 1471 if (cpu_is_mx27()) { 1472 /* EMMA support */ 1473 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1474 irq_emma = platform_get_irq(pdev, 1); 1475 1476 if (!res_emma || !irq_emma) { 1477 dev_err(&pdev->dev, "no EMMA resources\n"); 1478 goto exit_free_irq; 1479 } 1480 1481 pcdev->res_emma = res_emma; 1482 pcdev->irq_emma = irq_emma; 1483 if (mx27_camera_emma_init(pcdev)) 1484 goto exit_free_irq; 1485 } 1486 1487 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME, 1488 pcdev->soc_host.ops = &mx2_soc_camera_host_ops, 1489 pcdev->soc_host.priv = pcdev; 1490 pcdev->soc_host.v4l2_dev.dev = &pdev->dev; 1491 pcdev->soc_host.nr = pdev->id; 1492 1493 pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev); 1494 if (IS_ERR(pcdev->alloc_ctx)) { 1495 err = PTR_ERR(pcdev->alloc_ctx); 1496 goto eallocctx; 1497 } 1498 err = soc_camera_host_register(&pcdev->soc_host); 1499 if (err) 1500 goto exit_free_emma; 1501 1502 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n", 1503 clk_get_rate(pcdev->clk_csi)); 1504 1505 return 0; 1506 1507exit_free_emma: 1508 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx); 1509eallocctx: 1510 if (cpu_is_mx27()) { 1511 free_irq(pcdev->irq_emma, pcdev); 1512 clk_disable(pcdev->clk_emma); 1513 clk_put(pcdev->clk_emma); 1514 iounmap(pcdev->base_emma); 1515 release_mem_region(pcdev->res_emma->start, resource_size(pcdev->res_emma)); 1516 } 1517exit_free_irq: 1518 if (cpu_is_mx25()) 1519 free_irq(pcdev->irq_csi, pcdev); 1520exit_iounmap: 1521 iounmap(base_csi); 1522exit_release: 1523 release_mem_region(res_csi->start, resource_size(res_csi)); 1524exit_dma_free: 1525 clk_put(pcdev->clk_csi); 1526exit_kfree: 1527 kfree(pcdev); 1528exit: 1529 return err; 1530} 1531 1532static int __devexit mx2_camera_remove(struct platform_device *pdev) 1533{ 1534 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); 1535 struct mx2_camera_dev *pcdev = container_of(soc_host, 1536 struct mx2_camera_dev, soc_host); 1537 struct resource *res; 1538 1539 clk_put(pcdev->clk_csi); 1540 if (cpu_is_mx25()) 1541 free_irq(pcdev->irq_csi, pcdev); 1542 if (cpu_is_mx27()) 1543 free_irq(pcdev->irq_emma, pcdev); 1544 1545 soc_camera_host_unregister(&pcdev->soc_host); 1546 1547 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx); 1548 1549 iounmap(pcdev->base_csi); 1550 1551 if (cpu_is_mx27()) { 1552 clk_disable(pcdev->clk_emma); 1553 clk_put(pcdev->clk_emma); 1554 iounmap(pcdev->base_emma); 1555 res = pcdev->res_emma; 1556 release_mem_region(res->start, resource_size(res)); 1557 } 1558 1559 res = pcdev->res_csi; 1560 release_mem_region(res->start, resource_size(res)); 1561 1562 kfree(pcdev); 1563 1564 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n"); 1565 1566 return 0; 1567} 1568 1569static struct platform_driver mx2_camera_driver = { 1570 .driver = { 1571 .name = MX2_CAM_DRV_NAME, 1572 }, 1573 .remove = __devexit_p(mx2_camera_remove), 1574}; 1575 1576 1577static int __init mx2_camera_init(void) 1578{ 1579 return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe); 1580} 1581 1582static void __exit mx2_camera_exit(void) 1583{ 1584 return platform_driver_unregister(&mx2_camera_driver); 1585} 1586 1587module_init(mx2_camera_init); 1588module_exit(mx2_camera_exit); 1589 1590MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver"); 1591MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>"); 1592MODULE_LICENSE("GPL"); 1593MODULE_VERSION(MX2_CAM_VERSION); 1594