mx2_camera.c revision d86097e19cef2f13a29fc37db0dad17b99b6d5f8
1/* 2 * V4L2 Driver for i.MX27/i.MX25 camera host 3 * 4 * Copyright (C) 2008, Sascha Hauer, Pengutronix 5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/init.h> 14#include <linux/module.h> 15#include <linux/io.h> 16#include <linux/delay.h> 17#include <linux/slab.h> 18#include <linux/dma-mapping.h> 19#include <linux/errno.h> 20#include <linux/fs.h> 21#include <linux/interrupt.h> 22#include <linux/kernel.h> 23#include <linux/mm.h> 24#include <linux/moduleparam.h> 25#include <linux/time.h> 26#include <linux/version.h> 27#include <linux/device.h> 28#include <linux/platform_device.h> 29#include <linux/mutex.h> 30#include <linux/clk.h> 31 32#include <media/v4l2-common.h> 33#include <media/v4l2-dev.h> 34#include <media/videobuf-dma-contig.h> 35#include <media/soc_camera.h> 36#include <media/soc_mediabus.h> 37 38#include <linux/videodev2.h> 39 40#include <mach/mx2_cam.h> 41#ifdef CONFIG_MACH_MX27 42#include <mach/dma-mx1-mx2.h> 43#endif 44#include <mach/hardware.h> 45 46#include <asm/dma.h> 47 48#define MX2_CAM_DRV_NAME "mx2-camera" 49#define MX2_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) 50#define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera" 51 52/* reset values */ 53#define CSICR1_RESET_VAL 0x40000800 54#define CSICR2_RESET_VAL 0x0 55#define CSICR3_RESET_VAL 0x0 56 57/* csi control reg 1 */ 58#define CSICR1_SWAP16_EN (1 << 31) 59#define CSICR1_EXT_VSYNC (1 << 30) 60#define CSICR1_EOF_INTEN (1 << 29) 61#define CSICR1_PRP_IF_EN (1 << 28) 62#define CSICR1_CCIR_MODE (1 << 27) 63#define CSICR1_COF_INTEN (1 << 26) 64#define CSICR1_SF_OR_INTEN (1 << 25) 65#define CSICR1_RF_OR_INTEN (1 << 24) 66#define CSICR1_STATFF_LEVEL (3 << 22) 67#define CSICR1_STATFF_INTEN (1 << 21) 68#define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */ 69#define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */ 70#define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */ 71#define CSICR1_RXFF_INTEN (1 << 18) 72#define CSICR1_SOF_POL (1 << 17) 73#define CSICR1_SOF_INTEN (1 << 16) 74#define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12) 75#define CSICR1_HSYNC_POL (1 << 11) 76#define CSICR1_CCIR_EN (1 << 10) 77#define CSICR1_MCLKEN (1 << 9) 78#define CSICR1_FCC (1 << 8) 79#define CSICR1_PACK_DIR (1 << 7) 80#define CSICR1_CLR_STATFIFO (1 << 6) 81#define CSICR1_CLR_RXFIFO (1 << 5) 82#define CSICR1_GCLK_MODE (1 << 4) 83#define CSICR1_INV_DATA (1 << 3) 84#define CSICR1_INV_PCLK (1 << 2) 85#define CSICR1_REDGE (1 << 1) 86 87#define SHIFT_STATFF_LEVEL 22 88#define SHIFT_RXFF_LEVEL 19 89#define SHIFT_MCLKDIV 12 90 91/* control reg 3 */ 92#define CSICR3_FRMCNT (0xFFFF << 16) 93#define CSICR3_FRMCNT_RST (1 << 15) 94#define CSICR3_DMA_REFLASH_RFF (1 << 14) 95#define CSICR3_DMA_REFLASH_SFF (1 << 13) 96#define CSICR3_DMA_REQ_EN_RFF (1 << 12) 97#define CSICR3_DMA_REQ_EN_SFF (1 << 11) 98#define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */ 99#define CSICR3_CSI_SUP (1 << 3) 100#define CSICR3_ZERO_PACK_EN (1 << 2) 101#define CSICR3_ECC_INT_EN (1 << 1) 102#define CSICR3_ECC_AUTO_EN (1 << 0) 103 104#define SHIFT_FRMCNT 16 105 106/* csi status reg */ 107#define CSISR_SFF_OR_INT (1 << 25) 108#define CSISR_RFF_OR_INT (1 << 24) 109#define CSISR_STATFF_INT (1 << 21) 110#define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */ 111#define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */ 112#define CSISR_RXFF_INT (1 << 18) 113#define CSISR_EOF_INT (1 << 17) 114#define CSISR_SOF_INT (1 << 16) 115#define CSISR_F2_INT (1 << 15) 116#define CSISR_F1_INT (1 << 14) 117#define CSISR_COF_INT (1 << 13) 118#define CSISR_ECC_INT (1 << 1) 119#define CSISR_DRDY (1 << 0) 120 121#define CSICR1 0x00 122#define CSICR2 0x04 123#define CSISR (cpu_is_mx27() ? 0x08 : 0x18) 124#define CSISTATFIFO 0x0c 125#define CSIRFIFO 0x10 126#define CSIRXCNT 0x14 127#define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08) 128#define CSIDMASA_STATFIFO 0x20 129#define CSIDMATA_STATFIFO 0x24 130#define CSIDMASA_FB1 0x28 131#define CSIDMASA_FB2 0x2c 132#define CSIFBUF_PARA 0x30 133#define CSIIMAG_PARA 0x34 134 135/* EMMA PrP */ 136#define PRP_CNTL 0x00 137#define PRP_INTR_CNTL 0x04 138#define PRP_INTRSTATUS 0x08 139#define PRP_SOURCE_Y_PTR 0x0c 140#define PRP_SOURCE_CB_PTR 0x10 141#define PRP_SOURCE_CR_PTR 0x14 142#define PRP_DEST_RGB1_PTR 0x18 143#define PRP_DEST_RGB2_PTR 0x1c 144#define PRP_DEST_Y_PTR 0x20 145#define PRP_DEST_CB_PTR 0x24 146#define PRP_DEST_CR_PTR 0x28 147#define PRP_SRC_FRAME_SIZE 0x2c 148#define PRP_DEST_CH1_LINE_STRIDE 0x30 149#define PRP_SRC_PIXEL_FORMAT_CNTL 0x34 150#define PRP_CH1_PIXEL_FORMAT_CNTL 0x38 151#define PRP_CH1_OUT_IMAGE_SIZE 0x3c 152#define PRP_CH2_OUT_IMAGE_SIZE 0x40 153#define PRP_SRC_LINE_STRIDE 0x44 154#define PRP_CSC_COEF_012 0x48 155#define PRP_CSC_COEF_345 0x4c 156#define PRP_CSC_COEF_678 0x50 157#define PRP_CH1_RZ_HORI_COEF1 0x54 158#define PRP_CH1_RZ_HORI_COEF2 0x58 159#define PRP_CH1_RZ_HORI_VALID 0x5c 160#define PRP_CH1_RZ_VERT_COEF1 0x60 161#define PRP_CH1_RZ_VERT_COEF2 0x64 162#define PRP_CH1_RZ_VERT_VALID 0x68 163#define PRP_CH2_RZ_HORI_COEF1 0x6c 164#define PRP_CH2_RZ_HORI_COEF2 0x70 165#define PRP_CH2_RZ_HORI_VALID 0x74 166#define PRP_CH2_RZ_VERT_COEF1 0x78 167#define PRP_CH2_RZ_VERT_COEF2 0x7c 168#define PRP_CH2_RZ_VERT_VALID 0x80 169 170#define PRP_CNTL_CH1EN (1 << 0) 171#define PRP_CNTL_CH2EN (1 << 1) 172#define PRP_CNTL_CSIEN (1 << 2) 173#define PRP_CNTL_DATA_IN_YUV420 (0 << 3) 174#define PRP_CNTL_DATA_IN_YUV422 (1 << 3) 175#define PRP_CNTL_DATA_IN_RGB16 (2 << 3) 176#define PRP_CNTL_DATA_IN_RGB32 (3 << 3) 177#define PRP_CNTL_CH1_OUT_RGB8 (0 << 5) 178#define PRP_CNTL_CH1_OUT_RGB16 (1 << 5) 179#define PRP_CNTL_CH1_OUT_RGB32 (2 << 5) 180#define PRP_CNTL_CH1_OUT_YUV422 (3 << 5) 181#define PRP_CNTL_CH2_OUT_YUV420 (0 << 7) 182#define PRP_CNTL_CH2_OUT_YUV422 (1 << 7) 183#define PRP_CNTL_CH2_OUT_YUV444 (2 << 7) 184#define PRP_CNTL_CH1_LEN (1 << 9) 185#define PRP_CNTL_CH2_LEN (1 << 10) 186#define PRP_CNTL_SKIP_FRAME (1 << 11) 187#define PRP_CNTL_SWRST (1 << 12) 188#define PRP_CNTL_CLKEN (1 << 13) 189#define PRP_CNTL_WEN (1 << 14) 190#define PRP_CNTL_CH1BYP (1 << 15) 191#define PRP_CNTL_IN_TSKIP(x) ((x) << 16) 192#define PRP_CNTL_CH1_TSKIP(x) ((x) << 19) 193#define PRP_CNTL_CH2_TSKIP(x) ((x) << 22) 194#define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25) 195#define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27) 196#define PRP_CNTL_CH2B1EN (1 << 29) 197#define PRP_CNTL_CH2B2EN (1 << 30) 198#define PRP_CNTL_CH2FEN (1 << 31) 199 200/* IRQ Enable and status register */ 201#define PRP_INTR_RDERR (1 << 0) 202#define PRP_INTR_CH1WERR (1 << 1) 203#define PRP_INTR_CH2WERR (1 << 2) 204#define PRP_INTR_CH1FC (1 << 3) 205#define PRP_INTR_CH2FC (1 << 5) 206#define PRP_INTR_LBOVF (1 << 7) 207#define PRP_INTR_CH2OVF (1 << 8) 208 209#define mx27_camera_emma(pcdev) (cpu_is_mx27() && pcdev->use_emma) 210 211#define MAX_VIDEO_MEM 16 212 213struct mx2_camera_dev { 214 struct device *dev; 215 struct soc_camera_host soc_host; 216 struct soc_camera_device *icd; 217 struct clk *clk_csi, *clk_emma; 218 219 unsigned int irq_csi, irq_emma; 220 void __iomem *base_csi, *base_emma; 221 unsigned long base_dma; 222 223 struct mx2_camera_platform_data *pdata; 224 struct resource *res_csi, *res_emma; 225 unsigned long platform_flags; 226 227 struct list_head capture; 228 struct list_head active_bufs; 229 230 spinlock_t lock; 231 232 int dma; 233 struct mx2_buffer *active; 234 struct mx2_buffer *fb1_active; 235 struct mx2_buffer *fb2_active; 236 237 int use_emma; 238 239 u32 csicr1; 240 241 void *discard_buffer; 242 dma_addr_t discard_buffer_dma; 243 size_t discard_size; 244}; 245 246/* buffer for one video frame */ 247struct mx2_buffer { 248 /* common v4l buffer stuff -- must be first */ 249 struct videobuf_buffer vb; 250 251 enum v4l2_mbus_pixelcode code; 252 253 int bufnum; 254}; 255 256static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev) 257{ 258 unsigned long flags; 259 260 clk_disable(pcdev->clk_csi); 261 writel(0, pcdev->base_csi + CSICR1); 262 if (mx27_camera_emma(pcdev)) { 263 writel(0, pcdev->base_emma + PRP_CNTL); 264 } else if (cpu_is_mx25()) { 265 spin_lock_irqsave(&pcdev->lock, flags); 266 pcdev->fb1_active = NULL; 267 pcdev->fb2_active = NULL; 268 writel(0, pcdev->base_csi + CSIDMASA_FB1); 269 writel(0, pcdev->base_csi + CSIDMASA_FB2); 270 spin_unlock_irqrestore(&pcdev->lock, flags); 271 } 272} 273 274/* 275 * The following two functions absolutely depend on the fact, that 276 * there can be only one camera on mx2 camera sensor interface 277 */ 278static int mx2_camera_add_device(struct soc_camera_device *icd) 279{ 280 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 281 struct mx2_camera_dev *pcdev = ici->priv; 282 int ret; 283 u32 csicr1; 284 285 if (pcdev->icd) 286 return -EBUSY; 287 288 ret = clk_enable(pcdev->clk_csi); 289 if (ret < 0) 290 return ret; 291 292 csicr1 = CSICR1_MCLKEN; 293 294 if (mx27_camera_emma(pcdev)) { 295 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC | 296 CSICR1_RXFF_LEVEL(0); 297 } else if (cpu_is_mx27()) 298 csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2); 299 300 pcdev->csicr1 = csicr1; 301 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 302 303 pcdev->icd = icd; 304 305 dev_info(icd->dev.parent, "Camera driver attached to camera %d\n", 306 icd->devnum); 307 308 return 0; 309} 310 311static void mx2_camera_remove_device(struct soc_camera_device *icd) 312{ 313 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 314 struct mx2_camera_dev *pcdev = ici->priv; 315 316 BUG_ON(icd != pcdev->icd); 317 318 dev_info(icd->dev.parent, "Camera driver detached from camera %d\n", 319 icd->devnum); 320 321 mx2_camera_deactivate(pcdev); 322 323 if (pcdev->discard_buffer) { 324 dma_free_coherent(ici->v4l2_dev.dev, pcdev->discard_size, 325 pcdev->discard_buffer, 326 pcdev->discard_buffer_dma); 327 pcdev->discard_buffer = NULL; 328 } 329 330 pcdev->icd = NULL; 331} 332 333#ifdef CONFIG_MACH_MX27 334static void mx27_camera_dma_enable(struct mx2_camera_dev *pcdev) 335{ 336 u32 tmp; 337 338 imx_dma_enable(pcdev->dma); 339 340 tmp = readl(pcdev->base_csi + CSICR1); 341 tmp |= CSICR1_RF_OR_INTEN; 342 writel(tmp, pcdev->base_csi + CSICR1); 343} 344 345static irqreturn_t mx27_camera_irq(int irq_csi, void *data) 346{ 347 struct mx2_camera_dev *pcdev = data; 348 u32 status = readl(pcdev->base_csi + CSISR); 349 350 if (status & CSISR_SOF_INT && pcdev->active) { 351 u32 tmp; 352 353 tmp = readl(pcdev->base_csi + CSICR1); 354 writel(tmp | CSICR1_CLR_RXFIFO, pcdev->base_csi + CSICR1); 355 mx27_camera_dma_enable(pcdev); 356 } 357 358 writel(CSISR_SOF_INT | CSISR_RFF_OR_INT, pcdev->base_csi + CSISR); 359 360 return IRQ_HANDLED; 361} 362#else 363static irqreturn_t mx27_camera_irq(int irq_csi, void *data) 364{ 365 return IRQ_NONE; 366} 367#endif /* CONFIG_MACH_MX27 */ 368 369static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb, 370 int state) 371{ 372 struct videobuf_buffer *vb; 373 struct mx2_buffer *buf; 374 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active : 375 &pcdev->fb2_active; 376 u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2; 377 unsigned long flags; 378 379 spin_lock_irqsave(&pcdev->lock, flags); 380 381 vb = &(*fb_active)->vb; 382 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 383 vb, vb->baddr, vb->bsize); 384 385 vb->state = state; 386 do_gettimeofday(&vb->ts); 387 vb->field_count++; 388 389 wake_up(&vb->done); 390 391 if (list_empty(&pcdev->capture)) { 392 buf = NULL; 393 writel(0, pcdev->base_csi + fb_reg); 394 } else { 395 buf = list_entry(pcdev->capture.next, struct mx2_buffer, 396 vb.queue); 397 vb = &buf->vb; 398 list_del(&vb->queue); 399 vb->state = VIDEOBUF_ACTIVE; 400 writel(videobuf_to_dma_contig(vb), pcdev->base_csi + fb_reg); 401 } 402 403 *fb_active = buf; 404 405 spin_unlock_irqrestore(&pcdev->lock, flags); 406} 407 408static irqreturn_t mx25_camera_irq(int irq_csi, void *data) 409{ 410 struct mx2_camera_dev *pcdev = data; 411 u32 status = readl(pcdev->base_csi + CSISR); 412 413 if (status & CSISR_DMA_TSF_FB1_INT) 414 mx25_camera_frame_done(pcdev, 1, VIDEOBUF_DONE); 415 else if (status & CSISR_DMA_TSF_FB2_INT) 416 mx25_camera_frame_done(pcdev, 2, VIDEOBUF_DONE); 417 418 /* FIXME: handle CSISR_RFF_OR_INT */ 419 420 writel(status, pcdev->base_csi + CSISR); 421 422 return IRQ_HANDLED; 423} 424 425/* 426 * Videobuf operations 427 */ 428static int mx2_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, 429 unsigned int *size) 430{ 431 struct soc_camera_device *icd = vq->priv_data; 432 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, 433 icd->current_fmt->host_fmt); 434 435 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size); 436 437 if (bytes_per_line < 0) 438 return bytes_per_line; 439 440 *size = bytes_per_line * icd->user_height; 441 442 if (0 == *count) 443 *count = 32; 444 if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024) 445 *count = (MAX_VIDEO_MEM * 1024 * 1024) / *size; 446 447 return 0; 448} 449 450static void free_buffer(struct videobuf_queue *vq, struct mx2_buffer *buf) 451{ 452 struct soc_camera_device *icd = vq->priv_data; 453 struct videobuf_buffer *vb = &buf->vb; 454 455 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 456 vb, vb->baddr, vb->bsize); 457 458 /* 459 * This waits until this buffer is out of danger, i.e., until it is no 460 * longer in STATE_QUEUED or STATE_ACTIVE 461 */ 462 videobuf_waiton(vb, 0, 0); 463 464 videobuf_dma_contig_free(vq, vb); 465 dev_dbg(&icd->dev, "%s freed\n", __func__); 466 467 vb->state = VIDEOBUF_NEEDS_INIT; 468} 469 470static int mx2_videobuf_prepare(struct videobuf_queue *vq, 471 struct videobuf_buffer *vb, enum v4l2_field field) 472{ 473 struct soc_camera_device *icd = vq->priv_data; 474 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 475 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, 476 icd->current_fmt->host_fmt); 477 int ret = 0; 478 479 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 480 vb, vb->baddr, vb->bsize); 481 482 if (bytes_per_line < 0) 483 return bytes_per_line; 484 485#ifdef DEBUG 486 /* 487 * This can be useful if you want to see if we actually fill 488 * the buffer with something 489 */ 490 memset((void *)vb->baddr, 0xaa, vb->bsize); 491#endif 492 493 if (buf->code != icd->current_fmt->code || 494 vb->width != icd->user_width || 495 vb->height != icd->user_height || 496 vb->field != field) { 497 buf->code = icd->current_fmt->code; 498 vb->width = icd->user_width; 499 vb->height = icd->user_height; 500 vb->field = field; 501 vb->state = VIDEOBUF_NEEDS_INIT; 502 } 503 504 vb->size = bytes_per_line * vb->height; 505 if (vb->baddr && vb->bsize < vb->size) { 506 ret = -EINVAL; 507 goto out; 508 } 509 510 if (vb->state == VIDEOBUF_NEEDS_INIT) { 511 ret = videobuf_iolock(vq, vb, NULL); 512 if (ret) 513 goto fail; 514 515 vb->state = VIDEOBUF_PREPARED; 516 } 517 518 return 0; 519 520fail: 521 free_buffer(vq, buf); 522out: 523 return ret; 524} 525 526static void mx2_videobuf_queue(struct videobuf_queue *vq, 527 struct videobuf_buffer *vb) 528{ 529 struct soc_camera_device *icd = vq->priv_data; 530 struct soc_camera_host *ici = 531 to_soc_camera_host(icd->dev.parent); 532 struct mx2_camera_dev *pcdev = ici->priv; 533 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 534 unsigned long flags; 535 536 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 537 vb, vb->baddr, vb->bsize); 538 539 spin_lock_irqsave(&pcdev->lock, flags); 540 541 vb->state = VIDEOBUF_QUEUED; 542 list_add_tail(&vb->queue, &pcdev->capture); 543 544 if (mx27_camera_emma(pcdev)) { 545 goto out; 546#ifdef CONFIG_MACH_MX27 547 } else if (cpu_is_mx27()) { 548 int ret; 549 550 if (pcdev->active == NULL) { 551 ret = imx_dma_setup_single(pcdev->dma, 552 videobuf_to_dma_contig(vb), vb->size, 553 (u32)pcdev->base_dma + 0x10, 554 DMA_MODE_READ); 555 if (ret) { 556 vb->state = VIDEOBUF_ERROR; 557 wake_up(&vb->done); 558 goto out; 559 } 560 561 vb->state = VIDEOBUF_ACTIVE; 562 pcdev->active = buf; 563 } 564#endif 565 } else { /* cpu_is_mx25() */ 566 u32 csicr3, dma_inten = 0; 567 568 if (pcdev->fb1_active == NULL) { 569 writel(videobuf_to_dma_contig(vb), 570 pcdev->base_csi + CSIDMASA_FB1); 571 pcdev->fb1_active = buf; 572 dma_inten = CSICR1_FB1_DMA_INTEN; 573 } else if (pcdev->fb2_active == NULL) { 574 writel(videobuf_to_dma_contig(vb), 575 pcdev->base_csi + CSIDMASA_FB2); 576 pcdev->fb2_active = buf; 577 dma_inten = CSICR1_FB2_DMA_INTEN; 578 } 579 580 if (dma_inten) { 581 list_del(&vb->queue); 582 vb->state = VIDEOBUF_ACTIVE; 583 584 csicr3 = readl(pcdev->base_csi + CSICR3); 585 586 /* Reflash DMA */ 587 writel(csicr3 | CSICR3_DMA_REFLASH_RFF, 588 pcdev->base_csi + CSICR3); 589 590 /* clear & enable interrupts */ 591 writel(dma_inten, pcdev->base_csi + CSISR); 592 pcdev->csicr1 |= dma_inten; 593 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 594 595 /* enable DMA */ 596 csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1); 597 writel(csicr3, pcdev->base_csi + CSICR3); 598 } 599 } 600 601out: 602 spin_unlock_irqrestore(&pcdev->lock, flags); 603} 604 605static void mx2_videobuf_release(struct videobuf_queue *vq, 606 struct videobuf_buffer *vb) 607{ 608 struct soc_camera_device *icd = vq->priv_data; 609 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 610 struct mx2_camera_dev *pcdev = ici->priv; 611 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 612 unsigned long flags; 613 614#ifdef DEBUG 615 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 616 vb, vb->baddr, vb->bsize); 617 618 switch (vb->state) { 619 case VIDEOBUF_ACTIVE: 620 dev_info(&icd->dev, "%s (active)\n", __func__); 621 break; 622 case VIDEOBUF_QUEUED: 623 dev_info(&icd->dev, "%s (queued)\n", __func__); 624 break; 625 case VIDEOBUF_PREPARED: 626 dev_info(&icd->dev, "%s (prepared)\n", __func__); 627 break; 628 default: 629 dev_info(&icd->dev, "%s (unknown) %d\n", __func__, 630 vb->state); 631 break; 632 } 633#endif 634 635 /* 636 * Terminate only queued but inactive buffers. Active buffers are 637 * released when they become inactive after videobuf_waiton(). 638 * 639 * FIXME: implement forced termination of active buffers, so that the 640 * user won't get stuck in an uninterruptible state. This requires a 641 * specific handling for each of the three DMA types that this driver 642 * supports. 643 */ 644 spin_lock_irqsave(&pcdev->lock, flags); 645 if (vb->state == VIDEOBUF_QUEUED) { 646 list_del(&vb->queue); 647 vb->state = VIDEOBUF_ERROR; 648 } 649 spin_unlock_irqrestore(&pcdev->lock, flags); 650 651 free_buffer(vq, buf); 652} 653 654static struct videobuf_queue_ops mx2_videobuf_ops = { 655 .buf_setup = mx2_videobuf_setup, 656 .buf_prepare = mx2_videobuf_prepare, 657 .buf_queue = mx2_videobuf_queue, 658 .buf_release = mx2_videobuf_release, 659}; 660 661static void mx2_camera_init_videobuf(struct videobuf_queue *q, 662 struct soc_camera_device *icd) 663{ 664 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 665 struct mx2_camera_dev *pcdev = ici->priv; 666 667 videobuf_queue_dma_contig_init(q, &mx2_videobuf_ops, pcdev->dev, 668 &pcdev->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE, 669 V4L2_FIELD_NONE, sizeof(struct mx2_buffer), icd); 670} 671 672#define MX2_BUS_FLAGS (SOCAM_DATAWIDTH_8 | \ 673 SOCAM_MASTER | \ 674 SOCAM_VSYNC_ACTIVE_HIGH | \ 675 SOCAM_VSYNC_ACTIVE_LOW | \ 676 SOCAM_HSYNC_ACTIVE_HIGH | \ 677 SOCAM_HSYNC_ACTIVE_LOW | \ 678 SOCAM_PCLK_SAMPLE_RISING | \ 679 SOCAM_PCLK_SAMPLE_FALLING | \ 680 SOCAM_DATA_ACTIVE_HIGH | \ 681 SOCAM_DATA_ACTIVE_LOW) 682 683static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev) 684{ 685 u32 cntl; 686 int count = 0; 687 688 cntl = readl(pcdev->base_emma + PRP_CNTL); 689 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL); 690 while (count++ < 100) { 691 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST)) 692 return 0; 693 barrier(); 694 udelay(1); 695 } 696 697 return -ETIMEDOUT; 698} 699 700static void mx27_camera_emma_buf_init(struct soc_camera_device *icd, 701 int bytesperline) 702{ 703 struct soc_camera_host *ici = 704 to_soc_camera_host(icd->dev.parent); 705 struct mx2_camera_dev *pcdev = ici->priv; 706 707 writel(pcdev->discard_buffer_dma, 708 pcdev->base_emma + PRP_DEST_RGB1_PTR); 709 writel(pcdev->discard_buffer_dma, 710 pcdev->base_emma + PRP_DEST_RGB2_PTR); 711 712 /* 713 * We only use the EMMA engine to get rid of the broken 714 * DMA Engine. No color space consversion at the moment. 715 * We adjust incoming and outgoing pixelformat to rgb16 716 * and adjust the bytesperline accordingly. 717 */ 718 writel(PRP_CNTL_CH1EN | 719 PRP_CNTL_CSIEN | 720 PRP_CNTL_DATA_IN_RGB16 | 721 PRP_CNTL_CH1_OUT_RGB16 | 722 PRP_CNTL_CH1_LEN | 723 PRP_CNTL_CH1BYP | 724 PRP_CNTL_CH1_TSKIP(0) | 725 PRP_CNTL_IN_TSKIP(0), 726 pcdev->base_emma + PRP_CNTL); 727 728 writel(((bytesperline >> 1) << 16) | icd->user_height, 729 pcdev->base_emma + PRP_SRC_FRAME_SIZE); 730 writel(((bytesperline >> 1) << 16) | icd->user_height, 731 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE); 732 writel(bytesperline, 733 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE); 734 writel(0x2ca00565, /* RGB565 */ 735 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL); 736 writel(0x2ca00565, /* RGB565 */ 737 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL); 738 739 /* Enable interrupts */ 740 writel(PRP_INTR_RDERR | 741 PRP_INTR_CH1WERR | 742 PRP_INTR_CH2WERR | 743 PRP_INTR_CH1FC | 744 PRP_INTR_CH2FC | 745 PRP_INTR_LBOVF | 746 PRP_INTR_CH2OVF, 747 pcdev->base_emma + PRP_INTR_CNTL); 748} 749 750static int mx2_camera_set_bus_param(struct soc_camera_device *icd, 751 __u32 pixfmt) 752{ 753 struct soc_camera_host *ici = 754 to_soc_camera_host(icd->dev.parent); 755 struct mx2_camera_dev *pcdev = ici->priv; 756 unsigned long camera_flags, common_flags; 757 int ret = 0; 758 int bytesperline; 759 u32 csicr1 = pcdev->csicr1; 760 761 camera_flags = icd->ops->query_bus_param(icd); 762 763 common_flags = soc_camera_bus_param_compatible(camera_flags, 764 MX2_BUS_FLAGS); 765 if (!common_flags) 766 return -EINVAL; 767 768 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) && 769 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) { 770 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH) 771 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW; 772 else 773 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH; 774 } 775 776 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && 777 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { 778 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING) 779 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; 780 else 781 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; 782 } 783 784 ret = icd->ops->set_bus_param(icd, common_flags); 785 if (ret < 0) 786 return ret; 787 788 if (common_flags & SOCAM_PCLK_SAMPLE_RISING) 789 csicr1 |= CSICR1_REDGE; 790 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING) 791 csicr1 |= CSICR1_INV_PCLK; 792 if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH) 793 csicr1 |= CSICR1_SOF_POL; 794 if (common_flags & SOCAM_HSYNC_ACTIVE_HIGH) 795 csicr1 |= CSICR1_HSYNC_POL; 796 if (pcdev->platform_flags & MX2_CAMERA_SWAP16) 797 csicr1 |= CSICR1_SWAP16_EN; 798 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC) 799 csicr1 |= CSICR1_EXT_VSYNC; 800 if (pcdev->platform_flags & MX2_CAMERA_CCIR) 801 csicr1 |= CSICR1_CCIR_EN; 802 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE) 803 csicr1 |= CSICR1_CCIR_MODE; 804 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK) 805 csicr1 |= CSICR1_GCLK_MODE; 806 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA) 807 csicr1 |= CSICR1_INV_DATA; 808 if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB) 809 csicr1 |= CSICR1_PACK_DIR; 810 811 pcdev->csicr1 = csicr1; 812 813 bytesperline = soc_mbus_bytes_per_line(icd->user_width, 814 icd->current_fmt->host_fmt); 815 if (bytesperline < 0) 816 return bytesperline; 817 818 if (mx27_camera_emma(pcdev)) { 819 ret = mx27_camera_emma_prp_reset(pcdev); 820 if (ret) 821 return ret; 822 823 if (pcdev->discard_buffer) 824 dma_free_coherent(ici->v4l2_dev.dev, 825 pcdev->discard_size, pcdev->discard_buffer, 826 pcdev->discard_buffer_dma); 827 828 /* 829 * I didn't manage to properly enable/disable the prp 830 * on a per frame basis during running transfers, 831 * thus we allocate a buffer here and use it to 832 * discard frames when no buffer is available. 833 * Feel free to work on this ;) 834 */ 835 pcdev->discard_size = icd->user_height * bytesperline; 836 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev, 837 pcdev->discard_size, &pcdev->discard_buffer_dma, 838 GFP_KERNEL); 839 if (!pcdev->discard_buffer) 840 return -ENOMEM; 841 842 mx27_camera_emma_buf_init(icd, bytesperline); 843 } else if (cpu_is_mx25()) { 844 writel((bytesperline * icd->user_height) >> 2, 845 pcdev->base_csi + CSIRXCNT); 846 writel((bytesperline << 16) | icd->user_height, 847 pcdev->base_csi + CSIIMAG_PARA); 848 } 849 850 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 851 852 return 0; 853} 854 855static int mx2_camera_set_crop(struct soc_camera_device *icd, 856 struct v4l2_crop *a) 857{ 858 struct v4l2_rect *rect = &a->c; 859 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 860 struct v4l2_mbus_framefmt mf; 861 int ret; 862 863 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096); 864 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096); 865 866 ret = v4l2_subdev_call(sd, video, s_crop, a); 867 if (ret < 0) 868 return ret; 869 870 /* The capture device might have changed its output */ 871 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); 872 if (ret < 0) 873 return ret; 874 875 dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n", 876 mf.width, mf.height); 877 878 icd->user_width = mf.width; 879 icd->user_height = mf.height; 880 881 return ret; 882} 883 884static int mx2_camera_set_fmt(struct soc_camera_device *icd, 885 struct v4l2_format *f) 886{ 887 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 888 struct mx2_camera_dev *pcdev = ici->priv; 889 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 890 const struct soc_camera_format_xlate *xlate; 891 struct v4l2_pix_format *pix = &f->fmt.pix; 892 struct v4l2_mbus_framefmt mf; 893 int ret; 894 895 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); 896 if (!xlate) { 897 dev_warn(icd->dev.parent, "Format %x not found\n", 898 pix->pixelformat); 899 return -EINVAL; 900 } 901 902 /* eMMA can only do RGB565 */ 903 if (mx27_camera_emma(pcdev) && pix->pixelformat != V4L2_PIX_FMT_RGB565) 904 return -EINVAL; 905 906 mf.width = pix->width; 907 mf.height = pix->height; 908 mf.field = pix->field; 909 mf.colorspace = pix->colorspace; 910 mf.code = xlate->code; 911 912 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); 913 if (ret < 0 && ret != -ENOIOCTLCMD) 914 return ret; 915 916 if (mf.code != xlate->code) 917 return -EINVAL; 918 919 pix->width = mf.width; 920 pix->height = mf.height; 921 pix->field = mf.field; 922 pix->colorspace = mf.colorspace; 923 icd->current_fmt = xlate; 924 925 return 0; 926} 927 928static int mx2_camera_try_fmt(struct soc_camera_device *icd, 929 struct v4l2_format *f) 930{ 931 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 932 struct mx2_camera_dev *pcdev = ici->priv; 933 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 934 const struct soc_camera_format_xlate *xlate; 935 struct v4l2_pix_format *pix = &f->fmt.pix; 936 struct v4l2_mbus_framefmt mf; 937 __u32 pixfmt = pix->pixelformat; 938 unsigned int width_limit; 939 int ret; 940 941 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); 942 if (pixfmt && !xlate) { 943 dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt); 944 return -EINVAL; 945 } 946 947 /* FIXME: implement MX27 limits */ 948 949 /* eMMA can only do RGB565 */ 950 if (mx27_camera_emma(pcdev) && pixfmt != V4L2_PIX_FMT_RGB565) 951 return -EINVAL; 952 953 /* limit to MX25 hardware capabilities */ 954 if (cpu_is_mx25()) { 955 if (xlate->host_fmt->bits_per_sample <= 8) 956 width_limit = 0xffff * 4; 957 else 958 width_limit = 0xffff * 2; 959 /* CSIIMAG_PARA limit */ 960 if (pix->width > width_limit) 961 pix->width = width_limit; 962 if (pix->height > 0xffff) 963 pix->height = 0xffff; 964 965 pix->bytesperline = soc_mbus_bytes_per_line(pix->width, 966 xlate->host_fmt); 967 if (pix->bytesperline < 0) 968 return pix->bytesperline; 969 pix->sizeimage = pix->height * pix->bytesperline; 970 if (pix->sizeimage > (4 * 0x3ffff)) { /* CSIRXCNT limit */ 971 dev_warn(icd->dev.parent, 972 "Image size (%u) above limit\n", 973 pix->sizeimage); 974 return -EINVAL; 975 } 976 } 977 978 /* limit to sensor capabilities */ 979 mf.width = pix->width; 980 mf.height = pix->height; 981 mf.field = pix->field; 982 mf.colorspace = pix->colorspace; 983 mf.code = xlate->code; 984 985 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); 986 if (ret < 0) 987 return ret; 988 989 if (mf.field == V4L2_FIELD_ANY) 990 mf.field = V4L2_FIELD_NONE; 991 if (mf.field != V4L2_FIELD_NONE) { 992 dev_err(icd->dev.parent, "Field type %d unsupported.\n", 993 mf.field); 994 return -EINVAL; 995 } 996 997 pix->width = mf.width; 998 pix->height = mf.height; 999 pix->field = mf.field; 1000 pix->colorspace = mf.colorspace; 1001 1002 return 0; 1003} 1004 1005static int mx2_camera_querycap(struct soc_camera_host *ici, 1006 struct v4l2_capability *cap) 1007{ 1008 /* cap->name is set by the friendly caller:-> */ 1009 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card)); 1010 cap->version = MX2_CAM_VERSION_CODE; 1011 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; 1012 1013 return 0; 1014} 1015 1016static int mx2_camera_reqbufs(struct soc_camera_file *icf, 1017 struct v4l2_requestbuffers *p) 1018{ 1019 int i; 1020 1021 for (i = 0; i < p->count; i++) { 1022 struct mx2_buffer *buf = container_of(icf->vb_vidq.bufs[i], 1023 struct mx2_buffer, vb); 1024 INIT_LIST_HEAD(&buf->vb.queue); 1025 } 1026 1027 return 0; 1028} 1029 1030#ifdef CONFIG_MACH_MX27 1031static void mx27_camera_frame_done(struct mx2_camera_dev *pcdev, int state) 1032{ 1033 struct videobuf_buffer *vb; 1034 struct mx2_buffer *buf; 1035 unsigned long flags; 1036 int ret; 1037 1038 spin_lock_irqsave(&pcdev->lock, flags); 1039 1040 if (!pcdev->active) { 1041 dev_err(pcdev->dev, "%s called with no active buffer!\n", 1042 __func__); 1043 goto out; 1044 } 1045 1046 vb = &pcdev->active->vb; 1047 buf = container_of(vb, struct mx2_buffer, vb); 1048 WARN_ON(list_empty(&vb->queue)); 1049 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 1050 vb, vb->baddr, vb->bsize); 1051 1052 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ 1053 list_del_init(&vb->queue); 1054 vb->state = state; 1055 do_gettimeofday(&vb->ts); 1056 vb->field_count++; 1057 1058 wake_up(&vb->done); 1059 1060 if (list_empty(&pcdev->capture)) { 1061 pcdev->active = NULL; 1062 goto out; 1063 } 1064 1065 pcdev->active = list_entry(pcdev->capture.next, 1066 struct mx2_buffer, vb.queue); 1067 1068 vb = &pcdev->active->vb; 1069 vb->state = VIDEOBUF_ACTIVE; 1070 1071 ret = imx_dma_setup_single(pcdev->dma, videobuf_to_dma_contig(vb), 1072 vb->size, (u32)pcdev->base_dma + 0x10, DMA_MODE_READ); 1073 1074 if (ret) { 1075 vb->state = VIDEOBUF_ERROR; 1076 pcdev->active = NULL; 1077 wake_up(&vb->done); 1078 } 1079 1080out: 1081 spin_unlock_irqrestore(&pcdev->lock, flags); 1082} 1083 1084static void mx27_camera_dma_err_callback(int channel, void *data, int err) 1085{ 1086 struct mx2_camera_dev *pcdev = data; 1087 1088 mx27_camera_frame_done(pcdev, VIDEOBUF_ERROR); 1089} 1090 1091static void mx27_camera_dma_callback(int channel, void *data) 1092{ 1093 struct mx2_camera_dev *pcdev = data; 1094 1095 mx27_camera_frame_done(pcdev, VIDEOBUF_DONE); 1096} 1097 1098#define DMA_REQ_CSI_RX 31 /* FIXME: Add this to a resource */ 1099 1100static int __devinit mx27_camera_dma_init(struct platform_device *pdev, 1101 struct mx2_camera_dev *pcdev) 1102{ 1103 int err; 1104 1105 pcdev->dma = imx_dma_request_by_prio("CSI RX DMA", DMA_PRIO_HIGH); 1106 if (pcdev->dma < 0) { 1107 dev_err(&pdev->dev, "%s failed to request DMA channel\n", 1108 __func__); 1109 return pcdev->dma; 1110 } 1111 1112 err = imx_dma_setup_handlers(pcdev->dma, mx27_camera_dma_callback, 1113 mx27_camera_dma_err_callback, pcdev); 1114 if (err) { 1115 dev_err(&pdev->dev, "%s failed to set DMA callback\n", 1116 __func__); 1117 goto err_out; 1118 } 1119 1120 err = imx_dma_config_channel(pcdev->dma, 1121 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO, 1122 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR, 1123 DMA_REQ_CSI_RX, 1); 1124 if (err) { 1125 dev_err(&pdev->dev, "%s failed to config DMA channel\n", 1126 __func__); 1127 goto err_out; 1128 } 1129 1130 imx_dma_config_burstlen(pcdev->dma, 64); 1131 1132 return 0; 1133 1134err_out: 1135 imx_dma_free(pcdev->dma); 1136 1137 return err; 1138} 1139#endif /* CONFIG_MACH_MX27 */ 1140 1141static unsigned int mx2_camera_poll(struct file *file, poll_table *pt) 1142{ 1143 struct soc_camera_file *icf = file->private_data; 1144 1145 return videobuf_poll_stream(file, &icf->vb_vidq, pt); 1146} 1147 1148static struct soc_camera_host_ops mx2_soc_camera_host_ops = { 1149 .owner = THIS_MODULE, 1150 .add = mx2_camera_add_device, 1151 .remove = mx2_camera_remove_device, 1152 .set_fmt = mx2_camera_set_fmt, 1153 .set_crop = mx2_camera_set_crop, 1154 .try_fmt = mx2_camera_try_fmt, 1155 .init_videobuf = mx2_camera_init_videobuf, 1156 .reqbufs = mx2_camera_reqbufs, 1157 .poll = mx2_camera_poll, 1158 .querycap = mx2_camera_querycap, 1159 .set_bus_param = mx2_camera_set_bus_param, 1160}; 1161 1162static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev, 1163 int bufnum, int state) 1164{ 1165 struct mx2_buffer *buf; 1166 struct videobuf_buffer *vb; 1167 unsigned long phys; 1168 1169 if (!list_empty(&pcdev->active_bufs)) { 1170 buf = list_entry(pcdev->active_bufs.next, 1171 struct mx2_buffer, vb.queue); 1172 1173 BUG_ON(buf->bufnum != bufnum); 1174 1175 vb = &buf->vb; 1176#ifdef DEBUG 1177 phys = videobuf_to_dma_contig(vb); 1178 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum) 1179 != phys) { 1180 dev_err(pcdev->dev, "%p != %p\n", phys, 1181 readl(pcdev->base_emma + 1182 PRP_DEST_RGB1_PTR + 1183 4 * bufnum)); 1184 } 1185#endif 1186 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb, 1187 vb->baddr, vb->bsize); 1188 1189 list_del(&vb->queue); 1190 vb->state = state; 1191 do_gettimeofday(&vb->ts); 1192 vb->field_count++; 1193 1194 wake_up(&vb->done); 1195 } 1196 1197 if (list_empty(&pcdev->capture)) { 1198 writel(pcdev->discard_buffer_dma, pcdev->base_emma + 1199 PRP_DEST_RGB1_PTR + 4 * bufnum); 1200 return; 1201 } 1202 1203 buf = list_entry(pcdev->capture.next, 1204 struct mx2_buffer, vb.queue); 1205 1206 buf->bufnum = !bufnum; 1207 1208 list_move_tail(pcdev->capture.next, &pcdev->active_bufs); 1209 1210 vb = &buf->vb; 1211 vb->state = VIDEOBUF_ACTIVE; 1212 1213 phys = videobuf_to_dma_contig(vb); 1214 writel(phys, pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum); 1215} 1216 1217static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data) 1218{ 1219 struct mx2_camera_dev *pcdev = data; 1220 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS); 1221 struct mx2_buffer *buf; 1222 1223 if (status & (1 << 7)) { /* overflow */ 1224 u32 cntl; 1225 /* 1226 * We only disable channel 1 here since this is the only 1227 * enabled channel 1228 * 1229 * FIXME: the correct DMA overflow handling should be resetting 1230 * the buffer, returning an error frame, and continuing with 1231 * the next one. 1232 */ 1233 cntl = readl(pcdev->base_emma + PRP_CNTL); 1234 writel(cntl & ~PRP_CNTL_CH1EN, pcdev->base_emma + PRP_CNTL); 1235 writel(cntl, pcdev->base_emma + PRP_CNTL); 1236 } 1237 if ((status & (3 << 5)) == (3 << 5) 1238 && !list_empty(&pcdev->active_bufs)) { 1239 /* 1240 * Both buffers have triggered, process the one we're expecting 1241 * to first 1242 */ 1243 buf = list_entry(pcdev->active_bufs.next, 1244 struct mx2_buffer, vb.queue); 1245 mx27_camera_frame_done_emma(pcdev, buf->bufnum, VIDEOBUF_DONE); 1246 status &= ~(1 << (6 - buf->bufnum)); /* mark processed */ 1247 } 1248 if (status & (1 << 6)) 1249 mx27_camera_frame_done_emma(pcdev, 0, VIDEOBUF_DONE); 1250 if (status & (1 << 5)) 1251 mx27_camera_frame_done_emma(pcdev, 1, VIDEOBUF_DONE); 1252 1253 writel(status, pcdev->base_emma + PRP_INTRSTATUS); 1254 1255 return IRQ_HANDLED; 1256} 1257 1258static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev) 1259{ 1260 struct resource *res_emma = pcdev->res_emma; 1261 int err = 0; 1262 1263 if (!request_mem_region(res_emma->start, resource_size(res_emma), 1264 MX2_CAM_DRV_NAME)) { 1265 err = -EBUSY; 1266 goto out; 1267 } 1268 1269 pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma)); 1270 if (!pcdev->base_emma) { 1271 err = -ENOMEM; 1272 goto exit_release; 1273 } 1274 1275 err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0, 1276 MX2_CAM_DRV_NAME, pcdev); 1277 if (err) { 1278 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n"); 1279 goto exit_iounmap; 1280 } 1281 1282 pcdev->clk_emma = clk_get(NULL, "emma"); 1283 if (IS_ERR(pcdev->clk_emma)) { 1284 err = PTR_ERR(pcdev->clk_emma); 1285 goto exit_free_irq; 1286 } 1287 1288 clk_enable(pcdev->clk_emma); 1289 1290 err = mx27_camera_emma_prp_reset(pcdev); 1291 if (err) 1292 goto exit_clk_emma_put; 1293 1294 return err; 1295 1296exit_clk_emma_put: 1297 clk_disable(pcdev->clk_emma); 1298 clk_put(pcdev->clk_emma); 1299exit_free_irq: 1300 free_irq(pcdev->irq_emma, pcdev); 1301exit_iounmap: 1302 iounmap(pcdev->base_emma); 1303exit_release: 1304 release_mem_region(res_emma->start, resource_size(res_emma)); 1305out: 1306 return err; 1307} 1308 1309static int __devinit mx2_camera_probe(struct platform_device *pdev) 1310{ 1311 struct mx2_camera_dev *pcdev; 1312 struct resource *res_csi, *res_emma; 1313 void __iomem *base_csi; 1314 int irq_csi, irq_emma; 1315 irq_handler_t mx2_cam_irq_handler = cpu_is_mx25() ? mx25_camera_irq 1316 : mx27_camera_irq; 1317 int err = 0; 1318 1319 dev_dbg(&pdev->dev, "initialising\n"); 1320 1321 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1322 irq_csi = platform_get_irq(pdev, 0); 1323 if (res_csi == NULL || irq_csi < 0) { 1324 dev_err(&pdev->dev, "Missing platform resources data\n"); 1325 err = -ENODEV; 1326 goto exit; 1327 } 1328 1329 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); 1330 if (!pcdev) { 1331 dev_err(&pdev->dev, "Could not allocate pcdev\n"); 1332 err = -ENOMEM; 1333 goto exit; 1334 } 1335 1336 pcdev->clk_csi = clk_get(&pdev->dev, NULL); 1337 if (IS_ERR(pcdev->clk_csi)) { 1338 err = PTR_ERR(pcdev->clk_csi); 1339 goto exit_kfree; 1340 } 1341 1342 dev_dbg(&pdev->dev, "Camera clock frequency: %ld\n", 1343 clk_get_rate(pcdev->clk_csi)); 1344 1345 /* Initialize DMA */ 1346#ifdef CONFIG_MACH_MX27 1347 if (cpu_is_mx27()) { 1348 err = mx27_camera_dma_init(pdev, pcdev); 1349 if (err) 1350 goto exit_clk_put; 1351 } 1352#endif /* CONFIG_MACH_MX27 */ 1353 1354 pcdev->res_csi = res_csi; 1355 pcdev->pdata = pdev->dev.platform_data; 1356 if (pcdev->pdata) { 1357 long rate; 1358 1359 pcdev->platform_flags = pcdev->pdata->flags; 1360 1361 rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2); 1362 if (rate <= 0) { 1363 err = -ENODEV; 1364 goto exit_dma_free; 1365 } 1366 err = clk_set_rate(pcdev->clk_csi, rate); 1367 if (err < 0) 1368 goto exit_dma_free; 1369 } 1370 1371 INIT_LIST_HEAD(&pcdev->capture); 1372 INIT_LIST_HEAD(&pcdev->active_bufs); 1373 spin_lock_init(&pcdev->lock); 1374 1375 /* 1376 * Request the regions. 1377 */ 1378 if (!request_mem_region(res_csi->start, resource_size(res_csi), 1379 MX2_CAM_DRV_NAME)) { 1380 err = -EBUSY; 1381 goto exit_dma_free; 1382 } 1383 1384 base_csi = ioremap(res_csi->start, resource_size(res_csi)); 1385 if (!base_csi) { 1386 err = -ENOMEM; 1387 goto exit_release; 1388 } 1389 pcdev->irq_csi = irq_csi; 1390 pcdev->base_csi = base_csi; 1391 pcdev->base_dma = res_csi->start; 1392 pcdev->dev = &pdev->dev; 1393 1394 err = request_irq(pcdev->irq_csi, mx2_cam_irq_handler, 0, 1395 MX2_CAM_DRV_NAME, pcdev); 1396 if (err) { 1397 dev_err(pcdev->dev, "Camera interrupt register failed \n"); 1398 goto exit_iounmap; 1399 } 1400 1401 if (cpu_is_mx27()) { 1402 /* EMMA support */ 1403 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1404 irq_emma = platform_get_irq(pdev, 1); 1405 1406 if (res_emma && irq_emma >= 0) { 1407 dev_info(&pdev->dev, "Using EMMA\n"); 1408 pcdev->use_emma = 1; 1409 pcdev->res_emma = res_emma; 1410 pcdev->irq_emma = irq_emma; 1411 if (mx27_camera_emma_init(pcdev)) 1412 goto exit_free_irq; 1413 } 1414 } 1415 1416 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME, 1417 pcdev->soc_host.ops = &mx2_soc_camera_host_ops, 1418 pcdev->soc_host.priv = pcdev; 1419 pcdev->soc_host.v4l2_dev.dev = &pdev->dev; 1420 pcdev->soc_host.nr = pdev->id; 1421 err = soc_camera_host_register(&pcdev->soc_host); 1422 if (err) 1423 goto exit_free_emma; 1424 1425 return 0; 1426 1427exit_free_emma: 1428 if (mx27_camera_emma(pcdev)) { 1429 free_irq(pcdev->irq_emma, pcdev); 1430 clk_disable(pcdev->clk_emma); 1431 clk_put(pcdev->clk_emma); 1432 iounmap(pcdev->base_emma); 1433 release_mem_region(res_emma->start, resource_size(res_emma)); 1434 } 1435exit_free_irq: 1436 free_irq(pcdev->irq_csi, pcdev); 1437exit_iounmap: 1438 iounmap(base_csi); 1439exit_release: 1440 release_mem_region(res_csi->start, resource_size(res_csi)); 1441exit_dma_free: 1442#ifdef CONFIG_MACH_MX27 1443 if (cpu_is_mx27()) 1444 imx_dma_free(pcdev->dma); 1445exit_clk_put: 1446 clk_put(pcdev->clk_csi); 1447#endif /* CONFIG_MACH_MX27 */ 1448exit_kfree: 1449 kfree(pcdev); 1450exit: 1451 return err; 1452} 1453 1454static int __devexit mx2_camera_remove(struct platform_device *pdev) 1455{ 1456 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); 1457 struct mx2_camera_dev *pcdev = container_of(soc_host, 1458 struct mx2_camera_dev, soc_host); 1459 struct resource *res; 1460 1461 clk_put(pcdev->clk_csi); 1462#ifdef CONFIG_MACH_MX27 1463 if (cpu_is_mx27()) 1464 imx_dma_free(pcdev->dma); 1465#endif /* CONFIG_MACH_MX27 */ 1466 free_irq(pcdev->irq_csi, pcdev); 1467 if (mx27_camera_emma(pcdev)) 1468 free_irq(pcdev->irq_emma, pcdev); 1469 1470 soc_camera_host_unregister(&pcdev->soc_host); 1471 1472 iounmap(pcdev->base_csi); 1473 1474 if (mx27_camera_emma(pcdev)) { 1475 clk_disable(pcdev->clk_emma); 1476 clk_put(pcdev->clk_emma); 1477 iounmap(pcdev->base_emma); 1478 res = pcdev->res_emma; 1479 release_mem_region(res->start, resource_size(res)); 1480 } 1481 1482 res = pcdev->res_csi; 1483 release_mem_region(res->start, resource_size(res)); 1484 1485 kfree(pcdev); 1486 1487 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n"); 1488 1489 return 0; 1490} 1491 1492static struct platform_driver mx2_camera_driver = { 1493 .driver = { 1494 .name = MX2_CAM_DRV_NAME, 1495 }, 1496 .remove = __devexit_p(mx2_camera_remove), 1497}; 1498 1499 1500static int __init mx2_camera_init(void) 1501{ 1502 return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe); 1503} 1504 1505static void __exit mx2_camera_exit(void) 1506{ 1507 return platform_driver_unregister(&mx2_camera_driver); 1508} 1509 1510module_init(mx2_camera_init); 1511module_exit(mx2_camera_exit); 1512 1513MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver"); 1514MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>"); 1515MODULE_LICENSE("GPL"); 1516