ov772x.c revision 6a6c8786725c0b3d143674effa8b772f47b1c189 
1/*
2 * ov772x Camera Driver
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ov7670 and soc_camera_platform driver,
8 *
9 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
10 * Copyright (C) 2008 Magnus Damm
11 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/i2c.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/videodev2.h>
24#include <media/v4l2-chip-ident.h>
25#include <media/v4l2-subdev.h>
26#include <media/soc_camera.h>
27#include <media/ov772x.h>
28
29/*
30 * register offset
31 */
32#define GAIN        0x00 /* AGC - Gain control gain setting */
33#define BLUE        0x01 /* AWB - Blue channel gain setting */
34#define RED         0x02 /* AWB - Red   channel gain setting */
35#define GREEN       0x03 /* AWB - Green channel gain setting */
36#define COM1        0x04 /* Common control 1 */
37#define BAVG        0x05 /* U/B Average Level */
38#define GAVG        0x06 /* Y/Gb Average Level */
39#define RAVG        0x07 /* V/R Average Level */
40#define AECH        0x08 /* Exposure Value - AEC MSBs */
41#define COM2        0x09 /* Common control 2 */
42#define PID         0x0A /* Product ID Number MSB */
43#define VER         0x0B /* Product ID Number LSB */
44#define COM3        0x0C /* Common control 3 */
45#define COM4        0x0D /* Common control 4 */
46#define COM5        0x0E /* Common control 5 */
47#define COM6        0x0F /* Common control 6 */
48#define AEC         0x10 /* Exposure Value */
49#define CLKRC       0x11 /* Internal clock */
50#define COM7        0x12 /* Common control 7 */
51#define COM8        0x13 /* Common control 8 */
52#define COM9        0x14 /* Common control 9 */
53#define COM10       0x15 /* Common control 10 */
54#define REG16       0x16 /* Register 16 */
55#define HSTART      0x17 /* Horizontal sensor size */
56#define HSIZE       0x18 /* Horizontal frame (HREF column) end high 8-bit */
57#define VSTART      0x19 /* Vertical frame (row) start high 8-bit */
58#define VSIZE       0x1A /* Vertical sensor size */
59#define PSHFT       0x1B /* Data format - pixel delay select */
60#define MIDH        0x1C /* Manufacturer ID byte - high */
61#define MIDL        0x1D /* Manufacturer ID byte - low  */
62#define LAEC        0x1F /* Fine AEC value */
63#define COM11       0x20 /* Common control 11 */
64#define BDBASE      0x22 /* Banding filter Minimum AEC value */
65#define DBSTEP      0x23 /* Banding filter Maximum Setp */
66#define AEW         0x24 /* AGC/AEC - Stable operating region (upper limit) */
67#define AEB         0x25 /* AGC/AEC - Stable operating region (lower limit) */
68#define VPT         0x26 /* AGC/AEC Fast mode operating region */
69#define REG28       0x28 /* Register 28 */
70#define HOUTSIZE    0x29 /* Horizontal data output size MSBs */
71#define EXHCH       0x2A /* Dummy pixel insert MSB */
72#define EXHCL       0x2B /* Dummy pixel insert LSB */
73#define VOUTSIZE    0x2C /* Vertical data output size MSBs */
74#define ADVFL       0x2D /* LSB of insert dummy lines in Vertical direction */
75#define ADVFH       0x2E /* MSG of insert dummy lines in Vertical direction */
76#define YAVE        0x2F /* Y/G Channel Average value */
77#define LUMHTH      0x30 /* Histogram AEC/AGC Luminance high level threshold */
78#define LUMLTH      0x31 /* Histogram AEC/AGC Luminance low  level threshold */
79#define HREF        0x32 /* Image start and size control */
80#define DM_LNL      0x33 /* Dummy line low  8 bits */
81#define DM_LNH      0x34 /* Dummy line high 8 bits */
82#define ADOFF_B     0x35 /* AD offset compensation value for B  channel */
83#define ADOFF_R     0x36 /* AD offset compensation value for R  channel */
84#define ADOFF_GB    0x37 /* AD offset compensation value for Gb channel */
85#define ADOFF_GR    0x38 /* AD offset compensation value for Gr channel */
86#define OFF_B       0x39 /* Analog process B  channel offset value */
87#define OFF_R       0x3A /* Analog process R  channel offset value */
88#define OFF_GB      0x3B /* Analog process Gb channel offset value */
89#define OFF_GR      0x3C /* Analog process Gr channel offset value */
90#define COM12       0x3D /* Common control 12 */
91#define COM13       0x3E /* Common control 13 */
92#define COM14       0x3F /* Common control 14 */
93#define COM15       0x40 /* Common control 15*/
94#define COM16       0x41 /* Common control 16 */
95#define TGT_B       0x42 /* BLC blue channel target value */
96#define TGT_R       0x43 /* BLC red  channel target value */
97#define TGT_GB      0x44 /* BLC Gb   channel target value */
98#define TGT_GR      0x45 /* BLC Gr   channel target value */
99/* for ov7720 */
100#define LCC0        0x46 /* Lens correction control 0 */
101#define LCC1        0x47 /* Lens correction option 1 - X coordinate */
102#define LCC2        0x48 /* Lens correction option 2 - Y coordinate */
103#define LCC3        0x49 /* Lens correction option 3 */
104#define LCC4        0x4A /* Lens correction option 4 - radius of the circular */
105#define LCC5        0x4B /* Lens correction option 5 */
106#define LCC6        0x4C /* Lens correction option 6 */
107/* for ov7725 */
108#define LC_CTR      0x46 /* Lens correction control */
109#define LC_XC       0x47 /* X coordinate of lens correction center relative */
110#define LC_YC       0x48 /* Y coordinate of lens correction center relative */
111#define LC_COEF     0x49 /* Lens correction coefficient */
112#define LC_RADI     0x4A /* Lens correction radius */
113#define LC_COEFB    0x4B /* Lens B channel compensation coefficient */
114#define LC_COEFR    0x4C /* Lens R channel compensation coefficient */
115
116#define FIXGAIN     0x4D /* Analog fix gain amplifer */
117#define AREF0       0x4E /* Sensor reference control */
118#define AREF1       0x4F /* Sensor reference current control */
119#define AREF2       0x50 /* Analog reference control */
120#define AREF3       0x51 /* ADC    reference control */
121#define AREF4       0x52 /* ADC    reference control */
122#define AREF5       0x53 /* ADC    reference control */
123#define AREF6       0x54 /* Analog reference control */
124#define AREF7       0x55 /* Analog reference control */
125#define UFIX        0x60 /* U channel fixed value output */
126#define VFIX        0x61 /* V channel fixed value output */
127#define AWBB_BLK    0x62 /* AWB option for advanced AWB */
128#define AWB_CTRL0   0x63 /* AWB control byte 0 */
129#define DSP_CTRL1   0x64 /* DSP control byte 1 */
130#define DSP_CTRL2   0x65 /* DSP control byte 2 */
131#define DSP_CTRL3   0x66 /* DSP control byte 3 */
132#define DSP_CTRL4   0x67 /* DSP control byte 4 */
133#define AWB_BIAS    0x68 /* AWB BLC level clip */
134#define AWB_CTRL1   0x69 /* AWB control  1 */
135#define AWB_CTRL2   0x6A /* AWB control  2 */
136#define AWB_CTRL3   0x6B /* AWB control  3 */
137#define AWB_CTRL4   0x6C /* AWB control  4 */
138#define AWB_CTRL5   0x6D /* AWB control  5 */
139#define AWB_CTRL6   0x6E /* AWB control  6 */
140#define AWB_CTRL7   0x6F /* AWB control  7 */
141#define AWB_CTRL8   0x70 /* AWB control  8 */
142#define AWB_CTRL9   0x71 /* AWB control  9 */
143#define AWB_CTRL10  0x72 /* AWB control 10 */
144#define AWB_CTRL11  0x73 /* AWB control 11 */
145#define AWB_CTRL12  0x74 /* AWB control 12 */
146#define AWB_CTRL13  0x75 /* AWB control 13 */
147#define AWB_CTRL14  0x76 /* AWB control 14 */
148#define AWB_CTRL15  0x77 /* AWB control 15 */
149#define AWB_CTRL16  0x78 /* AWB control 16 */
150#define AWB_CTRL17  0x79 /* AWB control 17 */
151#define AWB_CTRL18  0x7A /* AWB control 18 */
152#define AWB_CTRL19  0x7B /* AWB control 19 */
153#define AWB_CTRL20  0x7C /* AWB control 20 */
154#define AWB_CTRL21  0x7D /* AWB control 21 */
155#define GAM1        0x7E /* Gamma Curve  1st segment input end point */
156#define GAM2        0x7F /* Gamma Curve  2nd segment input end point */
157#define GAM3        0x80 /* Gamma Curve  3rd segment input end point */
158#define GAM4        0x81 /* Gamma Curve  4th segment input end point */
159#define GAM5        0x82 /* Gamma Curve  5th segment input end point */
160#define GAM6        0x83 /* Gamma Curve  6th segment input end point */
161#define GAM7        0x84 /* Gamma Curve  7th segment input end point */
162#define GAM8        0x85 /* Gamma Curve  8th segment input end point */
163#define GAM9        0x86 /* Gamma Curve  9th segment input end point */
164#define GAM10       0x87 /* Gamma Curve 10th segment input end point */
165#define GAM11       0x88 /* Gamma Curve 11th segment input end point */
166#define GAM12       0x89 /* Gamma Curve 12th segment input end point */
167#define GAM13       0x8A /* Gamma Curve 13th segment input end point */
168#define GAM14       0x8B /* Gamma Curve 14th segment input end point */
169#define GAM15       0x8C /* Gamma Curve 15th segment input end point */
170#define SLOP        0x8D /* Gamma curve highest segment slope */
171#define DNSTH       0x8E /* De-noise threshold */
172#define EDGE_STRNGT 0x8F /* Edge strength  control when manual mode */
173#define EDGE_TRSHLD 0x90 /* Edge threshold control when manual mode */
174#define DNSOFF      0x91 /* Auto De-noise threshold control */
175#define EDGE_UPPER  0x92 /* Edge strength upper limit when Auto mode */
176#define EDGE_LOWER  0x93 /* Edge strength lower limit when Auto mode */
177#define MTX1        0x94 /* Matrix coefficient 1 */
178#define MTX2        0x95 /* Matrix coefficient 2 */
179#define MTX3        0x96 /* Matrix coefficient 3 */
180#define MTX4        0x97 /* Matrix coefficient 4 */
181#define MTX5        0x98 /* Matrix coefficient 5 */
182#define MTX6        0x99 /* Matrix coefficient 6 */
183#define MTX_CTRL    0x9A /* Matrix control */
184#define BRIGHT      0x9B /* Brightness control */
185#define CNTRST      0x9C /* Contrast contrast */
186#define CNTRST_CTRL 0x9D /* Contrast contrast center */
187#define UVAD_J0     0x9E /* Auto UV adjust contrast 0 */
188#define UVAD_J1     0x9F /* Auto UV adjust contrast 1 */
189#define SCAL0       0xA0 /* Scaling control 0 */
190#define SCAL1       0xA1 /* Scaling control 1 */
191#define SCAL2       0xA2 /* Scaling control 2 */
192#define FIFODLYM    0xA3 /* FIFO manual mode delay control */
193#define FIFODLYA    0xA4 /* FIFO auto   mode delay control */
194#define SDE         0xA6 /* Special digital effect control */
195#define USAT        0xA7 /* U component saturation control */
196#define VSAT        0xA8 /* V component saturation control */
197/* for ov7720 */
198#define HUE0        0xA9 /* Hue control 0 */
199#define HUE1        0xAA /* Hue control 1 */
200/* for ov7725 */
201#define HUECOS      0xA9 /* Cosine value */
202#define HUESIN      0xAA /* Sine value */
203
204#define SIGN        0xAB /* Sign bit for Hue and contrast */
205#define DSPAUTO     0xAC /* DSP auto function ON/OFF control */
206
207/*
208 * register detail
209 */
210
211/* COM2 */
212#define SOFT_SLEEP_MODE 0x10	/* Soft sleep mode */
213				/* Output drive capability */
214#define OCAP_1x         0x00	/* 1x */
215#define OCAP_2x         0x01	/* 2x */
216#define OCAP_3x         0x02	/* 3x */
217#define OCAP_4x         0x03	/* 4x */
218
219/* COM3 */
220#define SWAP_MASK       (SWAP_RGB | SWAP_YUV | SWAP_ML)
221#define IMG_MASK        (VFLIP_IMG | HFLIP_IMG)
222
223#define VFLIP_IMG       0x80	/* Vertical flip image ON/OFF selection */
224#define HFLIP_IMG       0x40	/* Horizontal mirror image ON/OFF selection */
225#define SWAP_RGB        0x20	/* Swap B/R  output sequence in RGB mode */
226#define SWAP_YUV        0x10	/* Swap Y/UV output sequence in YUV mode */
227#define SWAP_ML         0x08	/* Swap output MSB/LSB */
228				/* Tri-state option for output clock */
229#define NOTRI_CLOCK     0x04	/*   0: Tri-state    at this period */
230				/*   1: No tri-state at this period */
231				/* Tri-state option for output data */
232#define NOTRI_DATA      0x02	/*   0: Tri-state    at this period */
233				/*   1: No tri-state at this period */
234#define SCOLOR_TEST     0x01	/* Sensor color bar test pattern */
235
236/* COM4 */
237				/* PLL frequency control */
238#define PLL_BYPASS      0x00	/*  00: Bypass PLL */
239#define PLL_4x          0x40	/*  01: PLL 4x */
240#define PLL_6x          0x80	/*  10: PLL 6x */
241#define PLL_8x          0xc0	/*  11: PLL 8x */
242				/* AEC evaluate window */
243#define AEC_FULL        0x00	/*  00: Full window */
244#define AEC_1p2         0x10	/*  01: 1/2  window */
245#define AEC_1p4         0x20	/*  10: 1/4  window */
246#define AEC_2p3         0x30	/*  11: Low 2/3 window */
247
248/* COM5 */
249#define AFR_ON_OFF      0x80	/* Auto frame rate control ON/OFF selection */
250#define AFR_SPPED       0x40	/* Auto frame rate control speed slection */
251				/* Auto frame rate max rate control */
252#define AFR_NO_RATE     0x00	/*     No  reduction of frame rate */
253#define AFR_1p2         0x10	/*     Max reduction to 1/2 frame rate */
254#define AFR_1p4         0x20	/*     Max reduction to 1/4 frame rate */
255#define AFR_1p8         0x30	/* Max reduction to 1/8 frame rate */
256				/* Auto frame rate active point control */
257#define AF_2x           0x00	/*     Add frame when AGC reaches  2x gain */
258#define AF_4x           0x04	/*     Add frame when AGC reaches  4x gain */
259#define AF_8x           0x08	/*     Add frame when AGC reaches  8x gain */
260#define AF_16x          0x0c	/* Add frame when AGC reaches 16x gain */
261				/* AEC max step control */
262#define AEC_NO_LIMIT    0x01	/*   0 : AEC incease step has limit */
263				/*   1 : No limit to AEC increase step */
264
265/* COM7 */
266				/* SCCB Register Reset */
267#define SCCB_RESET      0x80	/*   0 : No change */
268				/*   1 : Resets all registers to default */
269				/* Resolution selection */
270#define SLCT_MASK       0x40	/*   Mask of VGA or QVGA */
271#define SLCT_VGA        0x00	/*   0 : VGA */
272#define SLCT_QVGA       0x40	/*   1 : QVGA */
273#define ITU656_ON_OFF   0x20	/* ITU656 protocol ON/OFF selection */
274				/* RGB output format control */
275#define FMT_MASK        0x0c	/*      Mask of color format */
276#define FMT_GBR422      0x00	/*      00 : GBR 4:2:2 */
277#define FMT_RGB565      0x04	/*      01 : RGB 565 */
278#define FMT_RGB555      0x08	/*      10 : RGB 555 */
279#define FMT_RGB444      0x0c	/* 11 : RGB 444 */
280				/* Output format control */
281#define OFMT_MASK       0x03    /*      Mask of output format */
282#define OFMT_YUV        0x00	/*      00 : YUV */
283#define OFMT_P_BRAW     0x01	/*      01 : Processed Bayer RAW */
284#define OFMT_RGB        0x02	/*      10 : RGB */
285#define OFMT_BRAW       0x03	/* 11 : Bayer RAW */
286
287/* COM8 */
288#define FAST_ALGO       0x80	/* Enable fast AGC/AEC algorithm */
289				/* AEC Setp size limit */
290#define UNLMT_STEP      0x40	/*   0 : Step size is limited */
291				/*   1 : Unlimited step size */
292#define BNDF_ON_OFF     0x20	/* Banding filter ON/OFF */
293#define AEC_BND         0x10	/* Enable AEC below banding value */
294#define AEC_ON_OFF      0x08	/* Fine AEC ON/OFF control */
295#define AGC_ON          0x04	/* AGC Enable */
296#define AWB_ON          0x02	/* AWB Enable */
297#define AEC_ON          0x01	/* AEC Enable */
298
299/* COM9 */
300#define BASE_AECAGC     0x80	/* Histogram or average based AEC/AGC */
301				/* Automatic gain ceiling - maximum AGC value */
302#define GAIN_2x         0x00	/*    000 :   2x */
303#define GAIN_4x         0x10	/*    001 :   4x */
304#define GAIN_8x         0x20	/*    010 :   8x */
305#define GAIN_16x        0x30	/*    011 :  16x */
306#define GAIN_32x        0x40	/*    100 :  32x */
307#define GAIN_64x        0x50	/* 101 :  64x */
308#define GAIN_128x       0x60	/* 110 : 128x */
309#define DROP_VSYNC      0x04	/* Drop VSYNC output of corrupt frame */
310#define DROP_HREF       0x02	/* Drop HREF  output of corrupt frame */
311
312/* COM11 */
313#define SGLF_ON_OFF     0x02	/* Single frame ON/OFF selection */
314#define SGLF_TRIG       0x01	/* Single frame transfer trigger */
315
316/* EXHCH */
317#define VSIZE_LSB       0x04	/* Vertical data output size LSB */
318
319/* DSP_CTRL1 */
320#define FIFO_ON         0x80	/* FIFO enable/disable selection */
321#define UV_ON_OFF       0x40	/* UV adjust function ON/OFF selection */
322#define YUV444_2_422    0x20	/* YUV444 to 422 UV channel option selection */
323#define CLR_MTRX_ON_OFF 0x10	/* Color matrix ON/OFF selection */
324#define INTPLT_ON_OFF   0x08	/* Interpolation ON/OFF selection */
325#define GMM_ON_OFF      0x04	/* Gamma function ON/OFF selection */
326#define AUTO_BLK_ON_OFF 0x02	/* Black defect auto correction ON/OFF */
327#define AUTO_WHT_ON_OFF 0x01	/* White define auto correction ON/OFF */
328
329/* DSP_CTRL3 */
330#define UV_MASK         0x80	/* UV output sequence option */
331#define UV_ON           0x80	/*   ON */
332#define UV_OFF          0x00	/*   OFF */
333#define CBAR_MASK       0x20	/* DSP Color bar mask */
334#define CBAR_ON         0x20	/*   ON */
335#define CBAR_OFF        0x00	/*   OFF */
336
337/* HSTART */
338#define HST_VGA         0x23
339#define HST_QVGA        0x3F
340
341/* HSIZE */
342#define HSZ_VGA         0xA0
343#define HSZ_QVGA        0x50
344
345/* VSTART */
346#define VST_VGA         0x07
347#define VST_QVGA        0x03
348
349/* VSIZE */
350#define VSZ_VGA         0xF0
351#define VSZ_QVGA        0x78
352
353/* HOUTSIZE */
354#define HOSZ_VGA        0xA0
355#define HOSZ_QVGA       0x50
356
357/* VOUTSIZE */
358#define VOSZ_VGA        0xF0
359#define VOSZ_QVGA       0x78
360
361/* DSPAUTO (DSP Auto Function ON/OFF Control) */
362#define AWB_ACTRL       0x80 /* AWB auto threshold control */
363#define DENOISE_ACTRL   0x40 /* De-noise auto threshold control */
364#define EDGE_ACTRL      0x20 /* Edge enhancement auto strength control */
365#define UV_ACTRL        0x10 /* UV adjust auto slope control */
366#define SCAL0_ACTRL     0x08 /* Auto scaling factor control */
367#define SCAL1_2_ACTRL   0x04 /* Auto scaling factor control */
368
369/*
370 * ID
371 */
372#define OV7720  0x7720
373#define OV7725  0x7721
374#define VERSION(pid, ver) ((pid<<8)|(ver&0xFF))
375
376/*
377 * struct
378 */
379struct regval_list {
380	unsigned char reg_num;
381	unsigned char value;
382};
383
384struct ov772x_color_format {
385	const struct soc_camera_data_format *format;
386	u8 dsp3;
387	u8 com3;
388	u8 com7;
389};
390
391struct ov772x_win_size {
392	char                     *name;
393	__u32                     width;
394	__u32                     height;
395	unsigned char             com7_bit;
396	const struct regval_list *regs;
397};
398
399struct ov772x_priv {
400	struct v4l2_subdev                subdev;
401	struct ov772x_camera_info        *info;
402	const struct ov772x_color_format *fmt;
403	const struct ov772x_win_size     *win;
404	int                               model;
405	unsigned short                    flag_vflip:1;
406	unsigned short                    flag_hflip:1;
407	unsigned short                    band_filter;	/* 256 - BDBASE, 0 if (!COM8[5]) */
408};
409
410#define ENDMARKER { 0xff, 0xff }
411
412/*
413 * register setting for window size
414 */
415static const struct regval_list ov772x_qvga_regs[] = {
416	{ HSTART,   HST_QVGA },
417	{ HSIZE,    HSZ_QVGA },
418	{ VSTART,   VST_QVGA },
419	{ VSIZE,    VSZ_QVGA  },
420	{ HOUTSIZE, HOSZ_QVGA },
421	{ VOUTSIZE, VOSZ_QVGA },
422	ENDMARKER,
423};
424
425static const struct regval_list ov772x_vga_regs[] = {
426	{ HSTART,   HST_VGA },
427	{ HSIZE,    HSZ_VGA },
428	{ VSTART,   VST_VGA },
429	{ VSIZE,    VSZ_VGA },
430	{ HOUTSIZE, HOSZ_VGA },
431	{ VOUTSIZE, VOSZ_VGA },
432	ENDMARKER,
433};
434
435/*
436 * supported format list
437 */
438
439#define SETFOURCC(type) .name = (#type), .fourcc = (V4L2_PIX_FMT_ ## type)
440static const struct soc_camera_data_format ov772x_fmt_lists[] = {
441	{
442		SETFOURCC(YUYV),
443		.depth      = 16,
444		.colorspace = V4L2_COLORSPACE_JPEG,
445	},
446	{
447		SETFOURCC(YVYU),
448		.depth      = 16,
449		.colorspace = V4L2_COLORSPACE_JPEG,
450	},
451	{
452		SETFOURCC(UYVY),
453		.depth      = 16,
454		.colorspace = V4L2_COLORSPACE_JPEG,
455	},
456	{
457		SETFOURCC(RGB555),
458		.depth      = 16,
459		.colorspace = V4L2_COLORSPACE_SRGB,
460	},
461	{
462		SETFOURCC(RGB555X),
463		.depth      = 16,
464		.colorspace = V4L2_COLORSPACE_SRGB,
465	},
466	{
467		SETFOURCC(RGB565),
468		.depth      = 16,
469		.colorspace = V4L2_COLORSPACE_SRGB,
470	},
471	{
472		SETFOURCC(RGB565X),
473		.depth      = 16,
474		.colorspace = V4L2_COLORSPACE_SRGB,
475	},
476};
477
478/*
479 * color format list
480 */
481static const struct ov772x_color_format ov772x_cfmts[] = {
482	{
483		.format = &ov772x_fmt_lists[0],
484		.dsp3   = 0x0,
485		.com3   = SWAP_YUV,
486		.com7   = OFMT_YUV,
487	},
488	{
489		.format = &ov772x_fmt_lists[1],
490		.dsp3   = UV_ON,
491		.com3   = SWAP_YUV,
492		.com7   = OFMT_YUV,
493	},
494	{
495		.format = &ov772x_fmt_lists[2],
496		.dsp3   = 0x0,
497		.com3   = 0x0,
498		.com7   = OFMT_YUV,
499	},
500	{
501		.format = &ov772x_fmt_lists[3],
502		.dsp3   = 0x0,
503		.com3   = SWAP_RGB,
504		.com7   = FMT_RGB555 | OFMT_RGB,
505	},
506	{
507		.format = &ov772x_fmt_lists[4],
508		.dsp3   = 0x0,
509		.com3   = 0x0,
510		.com7   = FMT_RGB555 | OFMT_RGB,
511	},
512	{
513		.format = &ov772x_fmt_lists[5],
514		.dsp3   = 0x0,
515		.com3   = SWAP_RGB,
516		.com7   = FMT_RGB565 | OFMT_RGB,
517	},
518	{
519		.format = &ov772x_fmt_lists[6],
520		.dsp3   = 0x0,
521		.com3   = 0x0,
522		.com7   = FMT_RGB565 | OFMT_RGB,
523	},
524};
525
526
527/*
528 * window size list
529 */
530#define VGA_WIDTH   640
531#define VGA_HEIGHT  480
532#define QVGA_WIDTH  320
533#define QVGA_HEIGHT 240
534#define MAX_WIDTH   VGA_WIDTH
535#define MAX_HEIGHT  VGA_HEIGHT
536
537static const struct ov772x_win_size ov772x_win_vga = {
538	.name     = "VGA",
539	.width    = VGA_WIDTH,
540	.height   = VGA_HEIGHT,
541	.com7_bit = SLCT_VGA,
542	.regs     = ov772x_vga_regs,
543};
544
545static const struct ov772x_win_size ov772x_win_qvga = {
546	.name     = "QVGA",
547	.width    = QVGA_WIDTH,
548	.height   = QVGA_HEIGHT,
549	.com7_bit = SLCT_QVGA,
550	.regs     = ov772x_qvga_regs,
551};
552
553static const struct v4l2_queryctrl ov772x_controls[] = {
554	{
555		.id		= V4L2_CID_VFLIP,
556		.type		= V4L2_CTRL_TYPE_BOOLEAN,
557		.name		= "Flip Vertically",
558		.minimum	= 0,
559		.maximum	= 1,
560		.step		= 1,
561		.default_value	= 0,
562	},
563	{
564		.id		= V4L2_CID_HFLIP,
565		.type		= V4L2_CTRL_TYPE_BOOLEAN,
566		.name		= "Flip Horizontally",
567		.minimum	= 0,
568		.maximum	= 1,
569		.step		= 1,
570		.default_value	= 0,
571	},
572	{
573		.id		= V4L2_CID_BAND_STOP_FILTER,
574		.type		= V4L2_CTRL_TYPE_INTEGER,
575		.name		= "Band-stop filter",
576		.minimum	= 0,
577		.maximum	= 256,
578		.step		= 1,
579		.default_value	= 0,
580	},
581};
582
583
584/*
585 * general function
586 */
587
588static struct ov772x_priv *to_ov772x(const struct i2c_client *client)
589{
590	return container_of(i2c_get_clientdata(client), struct ov772x_priv, subdev);
591}
592
593static int ov772x_write_array(struct i2c_client        *client,
594			      const struct regval_list *vals)
595{
596	while (vals->reg_num != 0xff) {
597		int ret = i2c_smbus_write_byte_data(client,
598						    vals->reg_num,
599						    vals->value);
600		if (ret < 0)
601			return ret;
602		vals++;
603	}
604	return 0;
605}
606
607static int ov772x_mask_set(struct i2c_client *client,
608					  u8  command,
609					  u8  mask,
610					  u8  set)
611{
612	s32 val = i2c_smbus_read_byte_data(client, command);
613	if (val < 0)
614		return val;
615
616	val &= ~mask;
617	val |= set & mask;
618
619	return i2c_smbus_write_byte_data(client, command, val);
620}
621
622static int ov772x_reset(struct i2c_client *client)
623{
624	int ret = i2c_smbus_write_byte_data(client, COM7, SCCB_RESET);
625	msleep(1);
626	return ret;
627}
628
629/*
630 * soc_camera_ops function
631 */
632
633static int ov772x_s_stream(struct v4l2_subdev *sd, int enable)
634{
635	struct i2c_client *client = sd->priv;
636	struct ov772x_priv *priv = to_ov772x(client);
637
638	if (!enable) {
639		ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, SOFT_SLEEP_MODE);
640		return 0;
641	}
642
643	if (!priv->win || !priv->fmt) {
644		dev_err(&client->dev, "norm or win select error\n");
645		return -EPERM;
646	}
647
648	ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, 0);
649
650	dev_dbg(&client->dev, "format %s, win %s\n",
651		priv->fmt->format->name, priv->win->name);
652
653	return 0;
654}
655
656static int ov772x_set_bus_param(struct soc_camera_device *icd,
657				unsigned long		  flags)
658{
659	return 0;
660}
661
662static unsigned long ov772x_query_bus_param(struct soc_camera_device *icd)
663{
664	struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
665	struct ov772x_priv *priv = i2c_get_clientdata(client);
666	struct soc_camera_link *icl = to_soc_camera_link(icd);
667	unsigned long flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_MASTER |
668		SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_HSYNC_ACTIVE_HIGH |
669		SOCAM_DATA_ACTIVE_HIGH | priv->info->buswidth;
670
671	return soc_camera_apply_sensor_flags(icl, flags);
672}
673
674static int ov772x_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
675{
676	struct i2c_client *client = sd->priv;
677	struct ov772x_priv *priv = to_ov772x(client);
678
679	switch (ctrl->id) {
680	case V4L2_CID_VFLIP:
681		ctrl->value = priv->flag_vflip;
682		break;
683	case V4L2_CID_HFLIP:
684		ctrl->value = priv->flag_hflip;
685		break;
686	case V4L2_CID_BAND_STOP_FILTER:
687		ctrl->value = priv->band_filter;
688		break;
689	}
690	return 0;
691}
692
693static int ov772x_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
694{
695	struct i2c_client *client = sd->priv;
696	struct ov772x_priv *priv = to_ov772x(client);
697	int ret = 0;
698	u8 val;
699
700	switch (ctrl->id) {
701	case V4L2_CID_VFLIP:
702		val = ctrl->value ? VFLIP_IMG : 0x00;
703		priv->flag_vflip = ctrl->value;
704		if (priv->info->flags & OV772X_FLAG_VFLIP)
705			val ^= VFLIP_IMG;
706		ret = ov772x_mask_set(client, COM3, VFLIP_IMG, val);
707		break;
708	case V4L2_CID_HFLIP:
709		val = ctrl->value ? HFLIP_IMG : 0x00;
710		priv->flag_hflip = ctrl->value;
711		if (priv->info->flags & OV772X_FLAG_HFLIP)
712			val ^= HFLIP_IMG;
713		ret = ov772x_mask_set(client, COM3, HFLIP_IMG, val);
714		break;
715	case V4L2_CID_BAND_STOP_FILTER:
716		if ((unsigned)ctrl->value > 256)
717			ctrl->value = 256;
718		if (ctrl->value == priv->band_filter)
719			break;
720		if (!ctrl->value) {
721			/* Switch the filter off, it is on now */
722			ret = ov772x_mask_set(client, BDBASE, 0xff, 0xff);
723			if (!ret)
724				ret = ov772x_mask_set(client, COM8,
725						      BNDF_ON_OFF, 0);
726		} else {
727			/* Switch the filter on, set AEC low limit */
728			val = 256 - ctrl->value;
729			ret = ov772x_mask_set(client, COM8,
730					      BNDF_ON_OFF, BNDF_ON_OFF);
731			if (!ret)
732				ret = ov772x_mask_set(client, BDBASE,
733						      0xff, val);
734		}
735		if (!ret)
736			priv->band_filter = ctrl->value;
737		break;
738	}
739
740	return ret;
741}
742
743static int ov772x_g_chip_ident(struct v4l2_subdev *sd,
744			       struct v4l2_dbg_chip_ident *id)
745{
746	struct i2c_client *client = sd->priv;
747	struct ov772x_priv *priv = to_ov772x(client);
748
749	id->ident    = priv->model;
750	id->revision = 0;
751
752	return 0;
753}
754
755#ifdef CONFIG_VIDEO_ADV_DEBUG
756static int ov772x_g_register(struct v4l2_subdev *sd,
757			     struct v4l2_dbg_register *reg)
758{
759	struct i2c_client *client = sd->priv;
760	int ret;
761
762	reg->size = 1;
763	if (reg->reg > 0xff)
764		return -EINVAL;
765
766	ret = i2c_smbus_read_byte_data(client, reg->reg);
767	if (ret < 0)
768		return ret;
769
770	reg->val = (__u64)ret;
771
772	return 0;
773}
774
775static int ov772x_s_register(struct v4l2_subdev *sd,
776			     struct v4l2_dbg_register *reg)
777{
778	struct i2c_client *client = sd->priv;
779
780	if (reg->reg > 0xff ||
781	    reg->val > 0xff)
782		return -EINVAL;
783
784	return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
785}
786#endif
787
788static const struct ov772x_win_size *ov772x_select_win(u32 width, u32 height)
789{
790	__u32 diff;
791	const struct ov772x_win_size *win;
792
793	/* default is QVGA */
794	diff = abs(width - ov772x_win_qvga.width) +
795		abs(height - ov772x_win_qvga.height);
796	win = &ov772x_win_qvga;
797
798	/* VGA */
799	if (diff >
800	    abs(width  - ov772x_win_vga.width) +
801	    abs(height - ov772x_win_vga.height))
802		win = &ov772x_win_vga;
803
804	return win;
805}
806
807static int ov772x_set_params(struct i2c_client *client,
808			     u32 *width, u32 *height, u32 pixfmt)
809{
810	struct ov772x_priv *priv = to_ov772x(client);
811	int ret = -EINVAL;
812	u8  val;
813	int i;
814
815	/*
816	 * select format
817	 */
818	priv->fmt = NULL;
819	for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) {
820		if (pixfmt == ov772x_cfmts[i].format->fourcc) {
821			priv->fmt = ov772x_cfmts + i;
822			break;
823		}
824	}
825	if (!priv->fmt)
826		goto ov772x_set_fmt_error;
827
828	/*
829	 * select win
830	 */
831	priv->win = ov772x_select_win(*width, *height);
832
833	/*
834	 * reset hardware
835	 */
836	ov772x_reset(client);
837
838	/*
839	 * Edge Ctrl
840	 */
841	if (priv->info->edgectrl.strength & OV772X_MANUAL_EDGE_CTRL) {
842
843		/*
844		 * Manual Edge Control Mode
845		 *
846		 * Edge auto strength bit is set by default.
847		 * Remove it when manual mode.
848		 */
849
850		ret = ov772x_mask_set(client, DSPAUTO, EDGE_ACTRL, 0x00);
851		if (ret < 0)
852			goto ov772x_set_fmt_error;
853
854		ret = ov772x_mask_set(client,
855				      EDGE_TRSHLD, EDGE_THRESHOLD_MASK,
856				      priv->info->edgectrl.threshold);
857		if (ret < 0)
858			goto ov772x_set_fmt_error;
859
860		ret = ov772x_mask_set(client,
861				      EDGE_STRNGT, EDGE_STRENGTH_MASK,
862				      priv->info->edgectrl.strength);
863		if (ret < 0)
864			goto ov772x_set_fmt_error;
865
866	} else if (priv->info->edgectrl.upper > priv->info->edgectrl.lower) {
867		/*
868		 * Auto Edge Control Mode
869		 *
870		 * set upper and lower limit
871		 */
872		ret = ov772x_mask_set(client,
873				      EDGE_UPPER, EDGE_UPPER_MASK,
874				      priv->info->edgectrl.upper);
875		if (ret < 0)
876			goto ov772x_set_fmt_error;
877
878		ret = ov772x_mask_set(client,
879				      EDGE_LOWER, EDGE_LOWER_MASK,
880				      priv->info->edgectrl.lower);
881		if (ret < 0)
882			goto ov772x_set_fmt_error;
883	}
884
885	/*
886	 * set size format
887	 */
888	ret = ov772x_write_array(client, priv->win->regs);
889	if (ret < 0)
890		goto ov772x_set_fmt_error;
891
892	/*
893	 * set DSP_CTRL3
894	 */
895	val = priv->fmt->dsp3;
896	if (val) {
897		ret = ov772x_mask_set(client,
898				      DSP_CTRL3, UV_MASK, val);
899		if (ret < 0)
900			goto ov772x_set_fmt_error;
901	}
902
903	/*
904	 * set COM3
905	 */
906	val = priv->fmt->com3;
907	if (priv->info->flags & OV772X_FLAG_VFLIP)
908		val |= VFLIP_IMG;
909	if (priv->info->flags & OV772X_FLAG_HFLIP)
910		val |= HFLIP_IMG;
911	if (priv->flag_vflip)
912		val ^= VFLIP_IMG;
913	if (priv->flag_hflip)
914		val ^= HFLIP_IMG;
915
916	ret = ov772x_mask_set(client,
917			      COM3, SWAP_MASK | IMG_MASK, val);
918	if (ret < 0)
919		goto ov772x_set_fmt_error;
920
921	/*
922	 * set COM7
923	 */
924	val = priv->win->com7_bit | priv->fmt->com7;
925	ret = ov772x_mask_set(client,
926			      COM7, (SLCT_MASK | FMT_MASK | OFMT_MASK),
927			      val);
928	if (ret < 0)
929		goto ov772x_set_fmt_error;
930
931	/*
932	 * set COM8
933	 */
934	if (priv->band_filter) {
935		ret = ov772x_mask_set(client, COM8, BNDF_ON_OFF, 1);
936		if (!ret)
937			ret = ov772x_mask_set(client, BDBASE,
938					      0xff, 256 - priv->band_filter);
939		if (ret < 0)
940			goto ov772x_set_fmt_error;
941	}
942
943	*width = priv->win->width;
944	*height = priv->win->height;
945
946	return ret;
947
948ov772x_set_fmt_error:
949
950	ov772x_reset(client);
951	priv->win = NULL;
952	priv->fmt = NULL;
953
954	return ret;
955}
956
957static int ov772x_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
958{
959	a->c.left	= 0;
960	a->c.top	= 0;
961	a->c.width	= VGA_WIDTH;
962	a->c.height	= VGA_HEIGHT;
963	a->type		= V4L2_BUF_TYPE_VIDEO_CAPTURE;
964
965	return 0;
966}
967
968static int ov772x_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
969{
970	a->bounds.left			= 0;
971	a->bounds.top			= 0;
972	a->bounds.width			= VGA_WIDTH;
973	a->bounds.height		= VGA_HEIGHT;
974	a->defrect			= a->bounds;
975	a->type				= V4L2_BUF_TYPE_VIDEO_CAPTURE;
976	a->pixelaspect.numerator	= 1;
977	a->pixelaspect.denominator	= 1;
978
979	return 0;
980}
981
982static int ov772x_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *f)
983{
984	struct i2c_client *client = sd->priv;
985	struct ov772x_priv *priv = to_ov772x(client);
986	struct v4l2_pix_format *pix = &f->fmt.pix;
987
988	if (!priv->win || !priv->fmt) {
989		u32 width = VGA_WIDTH, height = VGA_HEIGHT;
990		int ret = ov772x_set_params(client, &width, &height,
991					    V4L2_PIX_FMT_YUYV);
992		if (ret < 0)
993			return ret;
994	}
995
996	f->type			= V4L2_BUF_TYPE_VIDEO_CAPTURE;
997
998	pix->width		= priv->win->width;
999	pix->height		= priv->win->height;
1000	pix->pixelformat	= priv->fmt->format->fourcc;
1001	pix->colorspace		= priv->fmt->format->colorspace;
1002	pix->field		= V4L2_FIELD_NONE;
1003
1004	return 0;
1005}
1006
1007static int ov772x_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *f)
1008{
1009	struct i2c_client *client = sd->priv;
1010	struct v4l2_pix_format *pix = &f->fmt.pix;
1011
1012	return ov772x_set_params(client, &pix->width, &pix->height,
1013				 pix->pixelformat);
1014}
1015
1016static int ov772x_try_fmt(struct v4l2_subdev *sd,
1017			  struct v4l2_format *f)
1018{
1019	struct v4l2_pix_format *pix = &f->fmt.pix;
1020	const struct ov772x_win_size *win;
1021
1022	/*
1023	 * select suitable win
1024	 */
1025	win = ov772x_select_win(pix->width, pix->height);
1026
1027	pix->width  = win->width;
1028	pix->height = win->height;
1029	pix->field  = V4L2_FIELD_NONE;
1030
1031	return 0;
1032}
1033
1034static int ov772x_video_probe(struct soc_camera_device *icd,
1035			      struct i2c_client *client)
1036{
1037	struct ov772x_priv *priv = to_ov772x(client);
1038	u8                  pid, ver;
1039	const char         *devname;
1040
1041	/*
1042	 * We must have a parent by now. And it cannot be a wrong one.
1043	 * So this entire test is completely redundant.
1044	 */
1045	if (!icd->dev.parent ||
1046	    to_soc_camera_host(icd->dev.parent)->nr != icd->iface)
1047		return -ENODEV;
1048
1049	/*
1050	 * ov772x only use 8 or 10 bit bus width
1051	 */
1052	if (SOCAM_DATAWIDTH_10 != priv->info->buswidth &&
1053	    SOCAM_DATAWIDTH_8  != priv->info->buswidth) {
1054		dev_err(&client->dev, "bus width error\n");
1055		return -ENODEV;
1056	}
1057
1058	icd->formats     = ov772x_fmt_lists;
1059	icd->num_formats = ARRAY_SIZE(ov772x_fmt_lists);
1060
1061	/*
1062	 * check and show product ID and manufacturer ID
1063	 */
1064	pid = i2c_smbus_read_byte_data(client, PID);
1065	ver = i2c_smbus_read_byte_data(client, VER);
1066
1067	switch (VERSION(pid, ver)) {
1068	case OV7720:
1069		devname     = "ov7720";
1070		priv->model = V4L2_IDENT_OV7720;
1071		break;
1072	case OV7725:
1073		devname     = "ov7725";
1074		priv->model = V4L2_IDENT_OV7725;
1075		break;
1076	default:
1077		dev_err(&client->dev,
1078			"Product ID error %x:%x\n", pid, ver);
1079		return -ENODEV;
1080	}
1081
1082	dev_info(&client->dev,
1083		 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
1084		 devname,
1085		 pid,
1086		 ver,
1087		 i2c_smbus_read_byte_data(client, MIDH),
1088		 i2c_smbus_read_byte_data(client, MIDL));
1089
1090	return 0;
1091}
1092
1093static struct soc_camera_ops ov772x_ops = {
1094	.set_bus_param		= ov772x_set_bus_param,
1095	.query_bus_param	= ov772x_query_bus_param,
1096	.controls		= ov772x_controls,
1097	.num_controls		= ARRAY_SIZE(ov772x_controls),
1098};
1099
1100static struct v4l2_subdev_core_ops ov772x_subdev_core_ops = {
1101	.g_ctrl		= ov772x_g_ctrl,
1102	.s_ctrl		= ov772x_s_ctrl,
1103	.g_chip_ident	= ov772x_g_chip_ident,
1104#ifdef CONFIG_VIDEO_ADV_DEBUG
1105	.g_register	= ov772x_g_register,
1106	.s_register	= ov772x_s_register,
1107#endif
1108};
1109
1110static struct v4l2_subdev_video_ops ov772x_subdev_video_ops = {
1111	.s_stream	= ov772x_s_stream,
1112	.g_fmt		= ov772x_g_fmt,
1113	.s_fmt		= ov772x_s_fmt,
1114	.try_fmt	= ov772x_try_fmt,
1115	.cropcap	= ov772x_cropcap,
1116	.g_crop		= ov772x_g_crop,
1117};
1118
1119static struct v4l2_subdev_ops ov772x_subdev_ops = {
1120	.core	= &ov772x_subdev_core_ops,
1121	.video	= &ov772x_subdev_video_ops,
1122};
1123
1124/*
1125 * i2c_driver function
1126 */
1127
1128static int ov772x_probe(struct i2c_client *client,
1129			const struct i2c_device_id *did)
1130{
1131	struct ov772x_priv        *priv;
1132	struct ov772x_camera_info *info;
1133	struct soc_camera_device  *icd = client->dev.platform_data;
1134	struct i2c_adapter        *adapter = to_i2c_adapter(client->dev.parent);
1135	struct soc_camera_link    *icl;
1136	int                        ret;
1137
1138	if (!icd) {
1139		dev_err(&client->dev, "OV772X: missing soc-camera data!\n");
1140		return -EINVAL;
1141	}
1142
1143	icl = to_soc_camera_link(icd);
1144	if (!icl)
1145		return -EINVAL;
1146
1147	info = container_of(icl, struct ov772x_camera_info, link);
1148
1149	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1150		dev_err(&adapter->dev,
1151			"I2C-Adapter doesn't support "
1152			"I2C_FUNC_SMBUS_BYTE_DATA\n");
1153		return -EIO;
1154	}
1155
1156	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1157	if (!priv)
1158		return -ENOMEM;
1159
1160	priv->info = info;
1161
1162	v4l2_i2c_subdev_init(&priv->subdev, client, &ov772x_subdev_ops);
1163
1164	icd->ops		= &ov772x_ops;
1165
1166	ret = ov772x_video_probe(icd, client);
1167	if (ret) {
1168		icd->ops = NULL;
1169		i2c_set_clientdata(client, NULL);
1170		kfree(priv);
1171	}
1172
1173	return ret;
1174}
1175
1176static int ov772x_remove(struct i2c_client *client)
1177{
1178	struct ov772x_priv *priv = to_ov772x(client);
1179	struct soc_camera_device *icd = client->dev.platform_data;
1180
1181	icd->ops = NULL;
1182	i2c_set_clientdata(client, NULL);
1183	kfree(priv);
1184	return 0;
1185}
1186
1187static const struct i2c_device_id ov772x_id[] = {
1188	{ "ov772x", 0 },
1189	{ }
1190};
1191MODULE_DEVICE_TABLE(i2c, ov772x_id);
1192
1193static struct i2c_driver ov772x_i2c_driver = {
1194	.driver = {
1195		.name = "ov772x",
1196	},
1197	.probe    = ov772x_probe,
1198	.remove   = ov772x_remove,
1199	.id_table = ov772x_id,
1200};
1201
1202/*
1203 * module function
1204 */
1205
1206static int __init ov772x_module_init(void)
1207{
1208	return i2c_add_driver(&ov772x_i2c_driver);
1209}
1210
1211static void __exit ov772x_module_exit(void)
1212{
1213	i2c_del_driver(&ov772x_i2c_driver);
1214}
1215
1216module_init(ov772x_module_init);
1217module_exit(ov772x_module_exit);
1218
1219MODULE_DESCRIPTION("SoC Camera driver for ov772x");
1220MODULE_AUTHOR("Kuninori Morimoto");
1221MODULE_LICENSE("GPL v2");
1222