ov772x.c revision 96c75399544838e1752001c8abdde36dd459cf8f 
1/*
2 * ov772x Camera Driver
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ov7670 and soc_camera_platform driver,
8 *
9 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
10 * Copyright (C) 2008 Magnus Damm
11 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/i2c.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/videodev2.h>
24#include <media/v4l2-chip-ident.h>
25#include <media/v4l2-subdev.h>
26#include <media/soc_camera.h>
27#include <media/ov772x.h>
28
29/*
30 * register offset
31 */
32#define GAIN        0x00 /* AGC - Gain control gain setting */
33#define BLUE        0x01 /* AWB - Blue channel gain setting */
34#define RED         0x02 /* AWB - Red   channel gain setting */
35#define GREEN       0x03 /* AWB - Green channel gain setting */
36#define COM1        0x04 /* Common control 1 */
37#define BAVG        0x05 /* U/B Average Level */
38#define GAVG        0x06 /* Y/Gb Average Level */
39#define RAVG        0x07 /* V/R Average Level */
40#define AECH        0x08 /* Exposure Value - AEC MSBs */
41#define COM2        0x09 /* Common control 2 */
42#define PID         0x0A /* Product ID Number MSB */
43#define VER         0x0B /* Product ID Number LSB */
44#define COM3        0x0C /* Common control 3 */
45#define COM4        0x0D /* Common control 4 */
46#define COM5        0x0E /* Common control 5 */
47#define COM6        0x0F /* Common control 6 */
48#define AEC         0x10 /* Exposure Value */
49#define CLKRC       0x11 /* Internal clock */
50#define COM7        0x12 /* Common control 7 */
51#define COM8        0x13 /* Common control 8 */
52#define COM9        0x14 /* Common control 9 */
53#define COM10       0x15 /* Common control 10 */
54#define REG16       0x16 /* Register 16 */
55#define HSTART      0x17 /* Horizontal sensor size */
56#define HSIZE       0x18 /* Horizontal frame (HREF column) end high 8-bit */
57#define VSTART      0x19 /* Vertical frame (row) start high 8-bit */
58#define VSIZE       0x1A /* Vertical sensor size */
59#define PSHFT       0x1B /* Data format - pixel delay select */
60#define MIDH        0x1C /* Manufacturer ID byte - high */
61#define MIDL        0x1D /* Manufacturer ID byte - low  */
62#define LAEC        0x1F /* Fine AEC value */
63#define COM11       0x20 /* Common control 11 */
64#define BDBASE      0x22 /* Banding filter Minimum AEC value */
65#define DBSTEP      0x23 /* Banding filter Maximum Setp */
66#define AEW         0x24 /* AGC/AEC - Stable operating region (upper limit) */
67#define AEB         0x25 /* AGC/AEC - Stable operating region (lower limit) */
68#define VPT         0x26 /* AGC/AEC Fast mode operating region */
69#define REG28       0x28 /* Register 28 */
70#define HOUTSIZE    0x29 /* Horizontal data output size MSBs */
71#define EXHCH       0x2A /* Dummy pixel insert MSB */
72#define EXHCL       0x2B /* Dummy pixel insert LSB */
73#define VOUTSIZE    0x2C /* Vertical data output size MSBs */
74#define ADVFL       0x2D /* LSB of insert dummy lines in Vertical direction */
75#define ADVFH       0x2E /* MSG of insert dummy lines in Vertical direction */
76#define YAVE        0x2F /* Y/G Channel Average value */
77#define LUMHTH      0x30 /* Histogram AEC/AGC Luminance high level threshold */
78#define LUMLTH      0x31 /* Histogram AEC/AGC Luminance low  level threshold */
79#define HREF        0x32 /* Image start and size control */
80#define DM_LNL      0x33 /* Dummy line low  8 bits */
81#define DM_LNH      0x34 /* Dummy line high 8 bits */
82#define ADOFF_B     0x35 /* AD offset compensation value for B  channel */
83#define ADOFF_R     0x36 /* AD offset compensation value for R  channel */
84#define ADOFF_GB    0x37 /* AD offset compensation value for Gb channel */
85#define ADOFF_GR    0x38 /* AD offset compensation value for Gr channel */
86#define OFF_B       0x39 /* Analog process B  channel offset value */
87#define OFF_R       0x3A /* Analog process R  channel offset value */
88#define OFF_GB      0x3B /* Analog process Gb channel offset value */
89#define OFF_GR      0x3C /* Analog process Gr channel offset value */
90#define COM12       0x3D /* Common control 12 */
91#define COM13       0x3E /* Common control 13 */
92#define COM14       0x3F /* Common control 14 */
93#define COM15       0x40 /* Common control 15*/
94#define COM16       0x41 /* Common control 16 */
95#define TGT_B       0x42 /* BLC blue channel target value */
96#define TGT_R       0x43 /* BLC red  channel target value */
97#define TGT_GB      0x44 /* BLC Gb   channel target value */
98#define TGT_GR      0x45 /* BLC Gr   channel target value */
99/* for ov7720 */
100#define LCC0        0x46 /* Lens correction control 0 */
101#define LCC1        0x47 /* Lens correction option 1 - X coordinate */
102#define LCC2        0x48 /* Lens correction option 2 - Y coordinate */
103#define LCC3        0x49 /* Lens correction option 3 */
104#define LCC4        0x4A /* Lens correction option 4 - radius of the circular */
105#define LCC5        0x4B /* Lens correction option 5 */
106#define LCC6        0x4C /* Lens correction option 6 */
107/* for ov7725 */
108#define LC_CTR      0x46 /* Lens correction control */
109#define LC_XC       0x47 /* X coordinate of lens correction center relative */
110#define LC_YC       0x48 /* Y coordinate of lens correction center relative */
111#define LC_COEF     0x49 /* Lens correction coefficient */
112#define LC_RADI     0x4A /* Lens correction radius */
113#define LC_COEFB    0x4B /* Lens B channel compensation coefficient */
114#define LC_COEFR    0x4C /* Lens R channel compensation coefficient */
115
116#define FIXGAIN     0x4D /* Analog fix gain amplifer */
117#define AREF0       0x4E /* Sensor reference control */
118#define AREF1       0x4F /* Sensor reference current control */
119#define AREF2       0x50 /* Analog reference control */
120#define AREF3       0x51 /* ADC    reference control */
121#define AREF4       0x52 /* ADC    reference control */
122#define AREF5       0x53 /* ADC    reference control */
123#define AREF6       0x54 /* Analog reference control */
124#define AREF7       0x55 /* Analog reference control */
125#define UFIX        0x60 /* U channel fixed value output */
126#define VFIX        0x61 /* V channel fixed value output */
127#define AWBB_BLK    0x62 /* AWB option for advanced AWB */
128#define AWB_CTRL0   0x63 /* AWB control byte 0 */
129#define DSP_CTRL1   0x64 /* DSP control byte 1 */
130#define DSP_CTRL2   0x65 /* DSP control byte 2 */
131#define DSP_CTRL3   0x66 /* DSP control byte 3 */
132#define DSP_CTRL4   0x67 /* DSP control byte 4 */
133#define AWB_BIAS    0x68 /* AWB BLC level clip */
134#define AWB_CTRL1   0x69 /* AWB control  1 */
135#define AWB_CTRL2   0x6A /* AWB control  2 */
136#define AWB_CTRL3   0x6B /* AWB control  3 */
137#define AWB_CTRL4   0x6C /* AWB control  4 */
138#define AWB_CTRL5   0x6D /* AWB control  5 */
139#define AWB_CTRL6   0x6E /* AWB control  6 */
140#define AWB_CTRL7   0x6F /* AWB control  7 */
141#define AWB_CTRL8   0x70 /* AWB control  8 */
142#define AWB_CTRL9   0x71 /* AWB control  9 */
143#define AWB_CTRL10  0x72 /* AWB control 10 */
144#define AWB_CTRL11  0x73 /* AWB control 11 */
145#define AWB_CTRL12  0x74 /* AWB control 12 */
146#define AWB_CTRL13  0x75 /* AWB control 13 */
147#define AWB_CTRL14  0x76 /* AWB control 14 */
148#define AWB_CTRL15  0x77 /* AWB control 15 */
149#define AWB_CTRL16  0x78 /* AWB control 16 */
150#define AWB_CTRL17  0x79 /* AWB control 17 */
151#define AWB_CTRL18  0x7A /* AWB control 18 */
152#define AWB_CTRL19  0x7B /* AWB control 19 */
153#define AWB_CTRL20  0x7C /* AWB control 20 */
154#define AWB_CTRL21  0x7D /* AWB control 21 */
155#define GAM1        0x7E /* Gamma Curve  1st segment input end point */
156#define GAM2        0x7F /* Gamma Curve  2nd segment input end point */
157#define GAM3        0x80 /* Gamma Curve  3rd segment input end point */
158#define GAM4        0x81 /* Gamma Curve  4th segment input end point */
159#define GAM5        0x82 /* Gamma Curve  5th segment input end point */
160#define GAM6        0x83 /* Gamma Curve  6th segment input end point */
161#define GAM7        0x84 /* Gamma Curve  7th segment input end point */
162#define GAM8        0x85 /* Gamma Curve  8th segment input end point */
163#define GAM9        0x86 /* Gamma Curve  9th segment input end point */
164#define GAM10       0x87 /* Gamma Curve 10th segment input end point */
165#define GAM11       0x88 /* Gamma Curve 11th segment input end point */
166#define GAM12       0x89 /* Gamma Curve 12th segment input end point */
167#define GAM13       0x8A /* Gamma Curve 13th segment input end point */
168#define GAM14       0x8B /* Gamma Curve 14th segment input end point */
169#define GAM15       0x8C /* Gamma Curve 15th segment input end point */
170#define SLOP        0x8D /* Gamma curve highest segment slope */
171#define DNSTH       0x8E /* De-noise threshold */
172#define EDGE_STRNGT 0x8F /* Edge strength  control when manual mode */
173#define EDGE_TRSHLD 0x90 /* Edge threshold control when manual mode */
174#define DNSOFF      0x91 /* Auto De-noise threshold control */
175#define EDGE_UPPER  0x92 /* Edge strength upper limit when Auto mode */
176#define EDGE_LOWER  0x93 /* Edge strength lower limit when Auto mode */
177#define MTX1        0x94 /* Matrix coefficient 1 */
178#define MTX2        0x95 /* Matrix coefficient 2 */
179#define MTX3        0x96 /* Matrix coefficient 3 */
180#define MTX4        0x97 /* Matrix coefficient 4 */
181#define MTX5        0x98 /* Matrix coefficient 5 */
182#define MTX6        0x99 /* Matrix coefficient 6 */
183#define MTX_CTRL    0x9A /* Matrix control */
184#define BRIGHT      0x9B /* Brightness control */
185#define CNTRST      0x9C /* Contrast contrast */
186#define CNTRST_CTRL 0x9D /* Contrast contrast center */
187#define UVAD_J0     0x9E /* Auto UV adjust contrast 0 */
188#define UVAD_J1     0x9F /* Auto UV adjust contrast 1 */
189#define SCAL0       0xA0 /* Scaling control 0 */
190#define SCAL1       0xA1 /* Scaling control 1 */
191#define SCAL2       0xA2 /* Scaling control 2 */
192#define FIFODLYM    0xA3 /* FIFO manual mode delay control */
193#define FIFODLYA    0xA4 /* FIFO auto   mode delay control */
194#define SDE         0xA6 /* Special digital effect control */
195#define USAT        0xA7 /* U component saturation control */
196#define VSAT        0xA8 /* V component saturation control */
197/* for ov7720 */
198#define HUE0        0xA9 /* Hue control 0 */
199#define HUE1        0xAA /* Hue control 1 */
200/* for ov7725 */
201#define HUECOS      0xA9 /* Cosine value */
202#define HUESIN      0xAA /* Sine value */
203
204#define SIGN        0xAB /* Sign bit for Hue and contrast */
205#define DSPAUTO     0xAC /* DSP auto function ON/OFF control */
206
207/*
208 * register detail
209 */
210
211/* COM2 */
212#define SOFT_SLEEP_MODE 0x10	/* Soft sleep mode */
213				/* Output drive capability */
214#define OCAP_1x         0x00	/* 1x */
215#define OCAP_2x         0x01	/* 2x */
216#define OCAP_3x         0x02	/* 3x */
217#define OCAP_4x         0x03	/* 4x */
218
219/* COM3 */
220#define SWAP_MASK       (SWAP_RGB | SWAP_YUV | SWAP_ML)
221#define IMG_MASK        (VFLIP_IMG | HFLIP_IMG)
222
223#define VFLIP_IMG       0x80	/* Vertical flip image ON/OFF selection */
224#define HFLIP_IMG       0x40	/* Horizontal mirror image ON/OFF selection */
225#define SWAP_RGB        0x20	/* Swap B/R  output sequence in RGB mode */
226#define SWAP_YUV        0x10	/* Swap Y/UV output sequence in YUV mode */
227#define SWAP_ML         0x08	/* Swap output MSB/LSB */
228				/* Tri-state option for output clock */
229#define NOTRI_CLOCK     0x04	/*   0: Tri-state    at this period */
230				/*   1: No tri-state at this period */
231				/* Tri-state option for output data */
232#define NOTRI_DATA      0x02	/*   0: Tri-state    at this period */
233				/*   1: No tri-state at this period */
234#define SCOLOR_TEST     0x01	/* Sensor color bar test pattern */
235
236/* COM4 */
237				/* PLL frequency control */
238#define PLL_BYPASS      0x00	/*  00: Bypass PLL */
239#define PLL_4x          0x40	/*  01: PLL 4x */
240#define PLL_6x          0x80	/*  10: PLL 6x */
241#define PLL_8x          0xc0	/*  11: PLL 8x */
242				/* AEC evaluate window */
243#define AEC_FULL        0x00	/*  00: Full window */
244#define AEC_1p2         0x10	/*  01: 1/2  window */
245#define AEC_1p4         0x20	/*  10: 1/4  window */
246#define AEC_2p3         0x30	/*  11: Low 2/3 window */
247
248/* COM5 */
249#define AFR_ON_OFF      0x80	/* Auto frame rate control ON/OFF selection */
250#define AFR_SPPED       0x40	/* Auto frame rate control speed slection */
251				/* Auto frame rate max rate control */
252#define AFR_NO_RATE     0x00	/*     No  reduction of frame rate */
253#define AFR_1p2         0x10	/*     Max reduction to 1/2 frame rate */
254#define AFR_1p4         0x20	/*     Max reduction to 1/4 frame rate */
255#define AFR_1p8         0x30	/* Max reduction to 1/8 frame rate */
256				/* Auto frame rate active point control */
257#define AF_2x           0x00	/*     Add frame when AGC reaches  2x gain */
258#define AF_4x           0x04	/*     Add frame when AGC reaches  4x gain */
259#define AF_8x           0x08	/*     Add frame when AGC reaches  8x gain */
260#define AF_16x          0x0c	/* Add frame when AGC reaches 16x gain */
261				/* AEC max step control */
262#define AEC_NO_LIMIT    0x01	/*   0 : AEC incease step has limit */
263				/*   1 : No limit to AEC increase step */
264
265/* COM7 */
266				/* SCCB Register Reset */
267#define SCCB_RESET      0x80	/*   0 : No change */
268				/*   1 : Resets all registers to default */
269				/* Resolution selection */
270#define SLCT_MASK       0x40	/*   Mask of VGA or QVGA */
271#define SLCT_VGA        0x00	/*   0 : VGA */
272#define SLCT_QVGA       0x40	/*   1 : QVGA */
273#define ITU656_ON_OFF   0x20	/* ITU656 protocol ON/OFF selection */
274				/* RGB output format control */
275#define FMT_MASK        0x0c	/*      Mask of color format */
276#define FMT_GBR422      0x00	/*      00 : GBR 4:2:2 */
277#define FMT_RGB565      0x04	/*      01 : RGB 565 */
278#define FMT_RGB555      0x08	/*      10 : RGB 555 */
279#define FMT_RGB444      0x0c	/* 11 : RGB 444 */
280				/* Output format control */
281#define OFMT_MASK       0x03    /*      Mask of output format */
282#define OFMT_YUV        0x00	/*      00 : YUV */
283#define OFMT_P_BRAW     0x01	/*      01 : Processed Bayer RAW */
284#define OFMT_RGB        0x02	/*      10 : RGB */
285#define OFMT_BRAW       0x03	/* 11 : Bayer RAW */
286
287/* COM8 */
288#define FAST_ALGO       0x80	/* Enable fast AGC/AEC algorithm */
289				/* AEC Setp size limit */
290#define UNLMT_STEP      0x40	/*   0 : Step size is limited */
291				/*   1 : Unlimited step size */
292#define BNDF_ON_OFF     0x20	/* Banding filter ON/OFF */
293#define AEC_BND         0x10	/* Enable AEC below banding value */
294#define AEC_ON_OFF      0x08	/* Fine AEC ON/OFF control */
295#define AGC_ON          0x04	/* AGC Enable */
296#define AWB_ON          0x02	/* AWB Enable */
297#define AEC_ON          0x01	/* AEC Enable */
298
299/* COM9 */
300#define BASE_AECAGC     0x80	/* Histogram or average based AEC/AGC */
301				/* Automatic gain ceiling - maximum AGC value */
302#define GAIN_2x         0x00	/*    000 :   2x */
303#define GAIN_4x         0x10	/*    001 :   4x */
304#define GAIN_8x         0x20	/*    010 :   8x */
305#define GAIN_16x        0x30	/*    011 :  16x */
306#define GAIN_32x        0x40	/*    100 :  32x */
307#define GAIN_64x        0x50	/* 101 :  64x */
308#define GAIN_128x       0x60	/* 110 : 128x */
309#define DROP_VSYNC      0x04	/* Drop VSYNC output of corrupt frame */
310#define DROP_HREF       0x02	/* Drop HREF  output of corrupt frame */
311
312/* COM11 */
313#define SGLF_ON_OFF     0x02	/* Single frame ON/OFF selection */
314#define SGLF_TRIG       0x01	/* Single frame transfer trigger */
315
316/* EXHCH */
317#define VSIZE_LSB       0x04	/* Vertical data output size LSB */
318
319/* DSP_CTRL1 */
320#define FIFO_ON         0x80	/* FIFO enable/disable selection */
321#define UV_ON_OFF       0x40	/* UV adjust function ON/OFF selection */
322#define YUV444_2_422    0x20	/* YUV444 to 422 UV channel option selection */
323#define CLR_MTRX_ON_OFF 0x10	/* Color matrix ON/OFF selection */
324#define INTPLT_ON_OFF   0x08	/* Interpolation ON/OFF selection */
325#define GMM_ON_OFF      0x04	/* Gamma function ON/OFF selection */
326#define AUTO_BLK_ON_OFF 0x02	/* Black defect auto correction ON/OFF */
327#define AUTO_WHT_ON_OFF 0x01	/* White define auto correction ON/OFF */
328
329/* DSP_CTRL3 */
330#define UV_MASK         0x80	/* UV output sequence option */
331#define UV_ON           0x80	/*   ON */
332#define UV_OFF          0x00	/*   OFF */
333#define CBAR_MASK       0x20	/* DSP Color bar mask */
334#define CBAR_ON         0x20	/*   ON */
335#define CBAR_OFF        0x00	/*   OFF */
336
337/* HSTART */
338#define HST_VGA         0x23
339#define HST_QVGA        0x3F
340
341/* HSIZE */
342#define HSZ_VGA         0xA0
343#define HSZ_QVGA        0x50
344
345/* VSTART */
346#define VST_VGA         0x07
347#define VST_QVGA        0x03
348
349/* VSIZE */
350#define VSZ_VGA         0xF0
351#define VSZ_QVGA        0x78
352
353/* HOUTSIZE */
354#define HOSZ_VGA        0xA0
355#define HOSZ_QVGA       0x50
356
357/* VOUTSIZE */
358#define VOSZ_VGA        0xF0
359#define VOSZ_QVGA       0x78
360
361/* DSPAUTO (DSP Auto Function ON/OFF Control) */
362#define AWB_ACTRL       0x80 /* AWB auto threshold control */
363#define DENOISE_ACTRL   0x40 /* De-noise auto threshold control */
364#define EDGE_ACTRL      0x20 /* Edge enhancement auto strength control */
365#define UV_ACTRL        0x10 /* UV adjust auto slope control */
366#define SCAL0_ACTRL     0x08 /* Auto scaling factor control */
367#define SCAL1_2_ACTRL   0x04 /* Auto scaling factor control */
368
369/*
370 * ID
371 */
372#define OV7720  0x7720
373#define OV7725  0x7721
374#define VERSION(pid, ver) ((pid<<8)|(ver&0xFF))
375
376/*
377 * struct
378 */
379struct regval_list {
380	unsigned char reg_num;
381	unsigned char value;
382};
383
384struct ov772x_color_format {
385	const struct soc_camera_data_format *format;
386	u8 dsp3;
387	u8 com3;
388	u8 com7;
389};
390
391struct ov772x_win_size {
392	char                     *name;
393	__u32                     width;
394	__u32                     height;
395	unsigned char             com7_bit;
396	const struct regval_list *regs;
397};
398
399struct ov772x_priv {
400	struct v4l2_subdev                subdev;
401	struct ov772x_camera_info        *info;
402	const struct ov772x_color_format *fmt;
403	const struct ov772x_win_size     *win;
404	int                               model;
405	unsigned short                    flag_vflip:1;
406	unsigned short                    flag_hflip:1;
407	/* band_filter = COM8[5] ? 256 - BDBASE : 0 */
408	unsigned short                    band_filter;
409};
410
411#define ENDMARKER { 0xff, 0xff }
412
413/*
414 * register setting for window size
415 */
416static const struct regval_list ov772x_qvga_regs[] = {
417	{ HSTART,   HST_QVGA },
418	{ HSIZE,    HSZ_QVGA },
419	{ VSTART,   VST_QVGA },
420	{ VSIZE,    VSZ_QVGA  },
421	{ HOUTSIZE, HOSZ_QVGA },
422	{ VOUTSIZE, VOSZ_QVGA },
423	ENDMARKER,
424};
425
426static const struct regval_list ov772x_vga_regs[] = {
427	{ HSTART,   HST_VGA },
428	{ HSIZE,    HSZ_VGA },
429	{ VSTART,   VST_VGA },
430	{ VSIZE,    VSZ_VGA },
431	{ HOUTSIZE, HOSZ_VGA },
432	{ VOUTSIZE, VOSZ_VGA },
433	ENDMARKER,
434};
435
436/*
437 * supported format list
438 */
439
440#define SETFOURCC(type) .name = (#type), .fourcc = (V4L2_PIX_FMT_ ## type)
441static const struct soc_camera_data_format ov772x_fmt_lists[] = {
442	{
443		SETFOURCC(YUYV),
444		.depth      = 16,
445		.colorspace = V4L2_COLORSPACE_JPEG,
446	},
447	{
448		SETFOURCC(YVYU),
449		.depth      = 16,
450		.colorspace = V4L2_COLORSPACE_JPEG,
451	},
452	{
453		SETFOURCC(UYVY),
454		.depth      = 16,
455		.colorspace = V4L2_COLORSPACE_JPEG,
456	},
457	{
458		SETFOURCC(RGB555),
459		.depth      = 16,
460		.colorspace = V4L2_COLORSPACE_SRGB,
461	},
462	{
463		SETFOURCC(RGB555X),
464		.depth      = 16,
465		.colorspace = V4L2_COLORSPACE_SRGB,
466	},
467	{
468		SETFOURCC(RGB565),
469		.depth      = 16,
470		.colorspace = V4L2_COLORSPACE_SRGB,
471	},
472	{
473		SETFOURCC(RGB565X),
474		.depth      = 16,
475		.colorspace = V4L2_COLORSPACE_SRGB,
476	},
477};
478
479/*
480 * color format list
481 */
482static const struct ov772x_color_format ov772x_cfmts[] = {
483	{
484		.format = &ov772x_fmt_lists[0],
485		.dsp3   = 0x0,
486		.com3   = SWAP_YUV,
487		.com7   = OFMT_YUV,
488	},
489	{
490		.format = &ov772x_fmt_lists[1],
491		.dsp3   = UV_ON,
492		.com3   = SWAP_YUV,
493		.com7   = OFMT_YUV,
494	},
495	{
496		.format = &ov772x_fmt_lists[2],
497		.dsp3   = 0x0,
498		.com3   = 0x0,
499		.com7   = OFMT_YUV,
500	},
501	{
502		.format = &ov772x_fmt_lists[3],
503		.dsp3   = 0x0,
504		.com3   = SWAP_RGB,
505		.com7   = FMT_RGB555 | OFMT_RGB,
506	},
507	{
508		.format = &ov772x_fmt_lists[4],
509		.dsp3   = 0x0,
510		.com3   = 0x0,
511		.com7   = FMT_RGB555 | OFMT_RGB,
512	},
513	{
514		.format = &ov772x_fmt_lists[5],
515		.dsp3   = 0x0,
516		.com3   = SWAP_RGB,
517		.com7   = FMT_RGB565 | OFMT_RGB,
518	},
519	{
520		.format = &ov772x_fmt_lists[6],
521		.dsp3   = 0x0,
522		.com3   = 0x0,
523		.com7   = FMT_RGB565 | OFMT_RGB,
524	},
525};
526
527
528/*
529 * window size list
530 */
531#define VGA_WIDTH   640
532#define VGA_HEIGHT  480
533#define QVGA_WIDTH  320
534#define QVGA_HEIGHT 240
535#define MAX_WIDTH   VGA_WIDTH
536#define MAX_HEIGHT  VGA_HEIGHT
537
538static const struct ov772x_win_size ov772x_win_vga = {
539	.name     = "VGA",
540	.width    = VGA_WIDTH,
541	.height   = VGA_HEIGHT,
542	.com7_bit = SLCT_VGA,
543	.regs     = ov772x_vga_regs,
544};
545
546static const struct ov772x_win_size ov772x_win_qvga = {
547	.name     = "QVGA",
548	.width    = QVGA_WIDTH,
549	.height   = QVGA_HEIGHT,
550	.com7_bit = SLCT_QVGA,
551	.regs     = ov772x_qvga_regs,
552};
553
554static const struct v4l2_queryctrl ov772x_controls[] = {
555	{
556		.id		= V4L2_CID_VFLIP,
557		.type		= V4L2_CTRL_TYPE_BOOLEAN,
558		.name		= "Flip Vertically",
559		.minimum	= 0,
560		.maximum	= 1,
561		.step		= 1,
562		.default_value	= 0,
563	},
564	{
565		.id		= V4L2_CID_HFLIP,
566		.type		= V4L2_CTRL_TYPE_BOOLEAN,
567		.name		= "Flip Horizontally",
568		.minimum	= 0,
569		.maximum	= 1,
570		.step		= 1,
571		.default_value	= 0,
572	},
573	{
574		.id		= V4L2_CID_BAND_STOP_FILTER,
575		.type		= V4L2_CTRL_TYPE_INTEGER,
576		.name		= "Band-stop filter",
577		.minimum	= 0,
578		.maximum	= 256,
579		.step		= 1,
580		.default_value	= 0,
581	},
582};
583
584
585/*
586 * general function
587 */
588
589static struct ov772x_priv *to_ov772x(const struct i2c_client *client)
590{
591	return container_of(i2c_get_clientdata(client), struct ov772x_priv,
592			    subdev);
593}
594
595static int ov772x_write_array(struct i2c_client        *client,
596			      const struct regval_list *vals)
597{
598	while (vals->reg_num != 0xff) {
599		int ret = i2c_smbus_write_byte_data(client,
600						    vals->reg_num,
601						    vals->value);
602		if (ret < 0)
603			return ret;
604		vals++;
605	}
606	return 0;
607}
608
609static int ov772x_mask_set(struct i2c_client *client,
610					  u8  command,
611					  u8  mask,
612					  u8  set)
613{
614	s32 val = i2c_smbus_read_byte_data(client, command);
615	if (val < 0)
616		return val;
617
618	val &= ~mask;
619	val |= set & mask;
620
621	return i2c_smbus_write_byte_data(client, command, val);
622}
623
624static int ov772x_reset(struct i2c_client *client)
625{
626	int ret = i2c_smbus_write_byte_data(client, COM7, SCCB_RESET);
627	msleep(1);
628	return ret;
629}
630
631/*
632 * soc_camera_ops function
633 */
634
635static int ov772x_s_stream(struct v4l2_subdev *sd, int enable)
636{
637	struct i2c_client *client = sd->priv;
638	struct ov772x_priv *priv = to_ov772x(client);
639
640	if (!enable) {
641		ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, SOFT_SLEEP_MODE);
642		return 0;
643	}
644
645	if (!priv->win || !priv->fmt) {
646		dev_err(&client->dev, "norm or win select error\n");
647		return -EPERM;
648	}
649
650	ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, 0);
651
652	dev_dbg(&client->dev, "format %s, win %s\n",
653		priv->fmt->format->name, priv->win->name);
654
655	return 0;
656}
657
658static int ov772x_set_bus_param(struct soc_camera_device *icd,
659				unsigned long		  flags)
660{
661	return 0;
662}
663
664static unsigned long ov772x_query_bus_param(struct soc_camera_device *icd)
665{
666	struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
667	struct ov772x_priv *priv = i2c_get_clientdata(client);
668	struct soc_camera_link *icl = to_soc_camera_link(icd);
669	unsigned long flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_MASTER |
670		SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_HSYNC_ACTIVE_HIGH |
671		SOCAM_DATA_ACTIVE_HIGH | priv->info->buswidth;
672
673	return soc_camera_apply_sensor_flags(icl, flags);
674}
675
676static int ov772x_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
677{
678	struct i2c_client *client = sd->priv;
679	struct ov772x_priv *priv = to_ov772x(client);
680
681	switch (ctrl->id) {
682	case V4L2_CID_VFLIP:
683		ctrl->value = priv->flag_vflip;
684		break;
685	case V4L2_CID_HFLIP:
686		ctrl->value = priv->flag_hflip;
687		break;
688	case V4L2_CID_BAND_STOP_FILTER:
689		ctrl->value = priv->band_filter;
690		break;
691	}
692	return 0;
693}
694
695static int ov772x_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
696{
697	struct i2c_client *client = sd->priv;
698	struct ov772x_priv *priv = to_ov772x(client);
699	int ret = 0;
700	u8 val;
701
702	switch (ctrl->id) {
703	case V4L2_CID_VFLIP:
704		val = ctrl->value ? VFLIP_IMG : 0x00;
705		priv->flag_vflip = ctrl->value;
706		if (priv->info->flags & OV772X_FLAG_VFLIP)
707			val ^= VFLIP_IMG;
708		ret = ov772x_mask_set(client, COM3, VFLIP_IMG, val);
709		break;
710	case V4L2_CID_HFLIP:
711		val = ctrl->value ? HFLIP_IMG : 0x00;
712		priv->flag_hflip = ctrl->value;
713		if (priv->info->flags & OV772X_FLAG_HFLIP)
714			val ^= HFLIP_IMG;
715		ret = ov772x_mask_set(client, COM3, HFLIP_IMG, val);
716		break;
717	case V4L2_CID_BAND_STOP_FILTER:
718		if ((unsigned)ctrl->value > 256)
719			ctrl->value = 256;
720		if (ctrl->value == priv->band_filter)
721			break;
722		if (!ctrl->value) {
723			/* Switch the filter off, it is on now */
724			ret = ov772x_mask_set(client, BDBASE, 0xff, 0xff);
725			if (!ret)
726				ret = ov772x_mask_set(client, COM8,
727						      BNDF_ON_OFF, 0);
728		} else {
729			/* Switch the filter on, set AEC low limit */
730			val = 256 - ctrl->value;
731			ret = ov772x_mask_set(client, COM8,
732					      BNDF_ON_OFF, BNDF_ON_OFF);
733			if (!ret)
734				ret = ov772x_mask_set(client, BDBASE,
735						      0xff, val);
736		}
737		if (!ret)
738			priv->band_filter = ctrl->value;
739		break;
740	}
741
742	return ret;
743}
744
745static int ov772x_g_chip_ident(struct v4l2_subdev *sd,
746			       struct v4l2_dbg_chip_ident *id)
747{
748	struct i2c_client *client = sd->priv;
749	struct ov772x_priv *priv = to_ov772x(client);
750
751	id->ident    = priv->model;
752	id->revision = 0;
753
754	return 0;
755}
756
757#ifdef CONFIG_VIDEO_ADV_DEBUG
758static int ov772x_g_register(struct v4l2_subdev *sd,
759			     struct v4l2_dbg_register *reg)
760{
761	struct i2c_client *client = sd->priv;
762	int ret;
763
764	reg->size = 1;
765	if (reg->reg > 0xff)
766		return -EINVAL;
767
768	ret = i2c_smbus_read_byte_data(client, reg->reg);
769	if (ret < 0)
770		return ret;
771
772	reg->val = (__u64)ret;
773
774	return 0;
775}
776
777static int ov772x_s_register(struct v4l2_subdev *sd,
778			     struct v4l2_dbg_register *reg)
779{
780	struct i2c_client *client = sd->priv;
781
782	if (reg->reg > 0xff ||
783	    reg->val > 0xff)
784		return -EINVAL;
785
786	return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
787}
788#endif
789
790static const struct ov772x_win_size *ov772x_select_win(u32 width, u32 height)
791{
792	__u32 diff;
793	const struct ov772x_win_size *win;
794
795	/* default is QVGA */
796	diff = abs(width - ov772x_win_qvga.width) +
797		abs(height - ov772x_win_qvga.height);
798	win = &ov772x_win_qvga;
799
800	/* VGA */
801	if (diff >
802	    abs(width  - ov772x_win_vga.width) +
803	    abs(height - ov772x_win_vga.height))
804		win = &ov772x_win_vga;
805
806	return win;
807}
808
809static int ov772x_set_params(struct i2c_client *client,
810			     u32 *width, u32 *height, u32 pixfmt)
811{
812	struct ov772x_priv *priv = to_ov772x(client);
813	int ret = -EINVAL;
814	u8  val;
815	int i;
816
817	/*
818	 * select format
819	 */
820	priv->fmt = NULL;
821	for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) {
822		if (pixfmt == ov772x_cfmts[i].format->fourcc) {
823			priv->fmt = ov772x_cfmts + i;
824			break;
825		}
826	}
827	if (!priv->fmt)
828		goto ov772x_set_fmt_error;
829
830	/*
831	 * select win
832	 */
833	priv->win = ov772x_select_win(*width, *height);
834
835	/*
836	 * reset hardware
837	 */
838	ov772x_reset(client);
839
840	/*
841	 * Edge Ctrl
842	 */
843	if (priv->info->edgectrl.strength & OV772X_MANUAL_EDGE_CTRL) {
844
845		/*
846		 * Manual Edge Control Mode
847		 *
848		 * Edge auto strength bit is set by default.
849		 * Remove it when manual mode.
850		 */
851
852		ret = ov772x_mask_set(client, DSPAUTO, EDGE_ACTRL, 0x00);
853		if (ret < 0)
854			goto ov772x_set_fmt_error;
855
856		ret = ov772x_mask_set(client,
857				      EDGE_TRSHLD, EDGE_THRESHOLD_MASK,
858				      priv->info->edgectrl.threshold);
859		if (ret < 0)
860			goto ov772x_set_fmt_error;
861
862		ret = ov772x_mask_set(client,
863				      EDGE_STRNGT, EDGE_STRENGTH_MASK,
864				      priv->info->edgectrl.strength);
865		if (ret < 0)
866			goto ov772x_set_fmt_error;
867
868	} else if (priv->info->edgectrl.upper > priv->info->edgectrl.lower) {
869		/*
870		 * Auto Edge Control Mode
871		 *
872		 * set upper and lower limit
873		 */
874		ret = ov772x_mask_set(client,
875				      EDGE_UPPER, EDGE_UPPER_MASK,
876				      priv->info->edgectrl.upper);
877		if (ret < 0)
878			goto ov772x_set_fmt_error;
879
880		ret = ov772x_mask_set(client,
881				      EDGE_LOWER, EDGE_LOWER_MASK,
882				      priv->info->edgectrl.lower);
883		if (ret < 0)
884			goto ov772x_set_fmt_error;
885	}
886
887	/*
888	 * set size format
889	 */
890	ret = ov772x_write_array(client, priv->win->regs);
891	if (ret < 0)
892		goto ov772x_set_fmt_error;
893
894	/*
895	 * set DSP_CTRL3
896	 */
897	val = priv->fmt->dsp3;
898	if (val) {
899		ret = ov772x_mask_set(client,
900				      DSP_CTRL3, UV_MASK, val);
901		if (ret < 0)
902			goto ov772x_set_fmt_error;
903	}
904
905	/*
906	 * set COM3
907	 */
908	val = priv->fmt->com3;
909	if (priv->info->flags & OV772X_FLAG_VFLIP)
910		val |= VFLIP_IMG;
911	if (priv->info->flags & OV772X_FLAG_HFLIP)
912		val |= HFLIP_IMG;
913	if (priv->flag_vflip)
914		val ^= VFLIP_IMG;
915	if (priv->flag_hflip)
916		val ^= HFLIP_IMG;
917
918	ret = ov772x_mask_set(client,
919			      COM3, SWAP_MASK | IMG_MASK, val);
920	if (ret < 0)
921		goto ov772x_set_fmt_error;
922
923	/*
924	 * set COM7
925	 */
926	val = priv->win->com7_bit | priv->fmt->com7;
927	ret = ov772x_mask_set(client,
928			      COM7, (SLCT_MASK | FMT_MASK | OFMT_MASK),
929			      val);
930	if (ret < 0)
931		goto ov772x_set_fmt_error;
932
933	/*
934	 * set COM8
935	 */
936	if (priv->band_filter) {
937		ret = ov772x_mask_set(client, COM8, BNDF_ON_OFF, 1);
938		if (!ret)
939			ret = ov772x_mask_set(client, BDBASE,
940					      0xff, 256 - priv->band_filter);
941		if (ret < 0)
942			goto ov772x_set_fmt_error;
943	}
944
945	*width = priv->win->width;
946	*height = priv->win->height;
947
948	return ret;
949
950ov772x_set_fmt_error:
951
952	ov772x_reset(client);
953	priv->win = NULL;
954	priv->fmt = NULL;
955
956	return ret;
957}
958
959static int ov772x_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
960{
961	a->c.left	= 0;
962	a->c.top	= 0;
963	a->c.width	= VGA_WIDTH;
964	a->c.height	= VGA_HEIGHT;
965	a->type		= V4L2_BUF_TYPE_VIDEO_CAPTURE;
966
967	return 0;
968}
969
970static int ov772x_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
971{
972	a->bounds.left			= 0;
973	a->bounds.top			= 0;
974	a->bounds.width			= VGA_WIDTH;
975	a->bounds.height		= VGA_HEIGHT;
976	a->defrect			= a->bounds;
977	a->type				= V4L2_BUF_TYPE_VIDEO_CAPTURE;
978	a->pixelaspect.numerator	= 1;
979	a->pixelaspect.denominator	= 1;
980
981	return 0;
982}
983
984static int ov772x_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *f)
985{
986	struct i2c_client *client = sd->priv;
987	struct ov772x_priv *priv = to_ov772x(client);
988	struct v4l2_pix_format *pix = &f->fmt.pix;
989
990	if (!priv->win || !priv->fmt) {
991		u32 width = VGA_WIDTH, height = VGA_HEIGHT;
992		int ret = ov772x_set_params(client, &width, &height,
993					    V4L2_PIX_FMT_YUYV);
994		if (ret < 0)
995			return ret;
996	}
997
998	f->type			= V4L2_BUF_TYPE_VIDEO_CAPTURE;
999
1000	pix->width		= priv->win->width;
1001	pix->height		= priv->win->height;
1002	pix->pixelformat	= priv->fmt->format->fourcc;
1003	pix->colorspace		= priv->fmt->format->colorspace;
1004	pix->field		= V4L2_FIELD_NONE;
1005
1006	return 0;
1007}
1008
1009static int ov772x_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *f)
1010{
1011	struct i2c_client *client = sd->priv;
1012	struct v4l2_pix_format *pix = &f->fmt.pix;
1013
1014	return ov772x_set_params(client, &pix->width, &pix->height,
1015				 pix->pixelformat);
1016}
1017
1018static int ov772x_try_fmt(struct v4l2_subdev *sd,
1019			  struct v4l2_format *f)
1020{
1021	struct v4l2_pix_format *pix = &f->fmt.pix;
1022	const struct ov772x_win_size *win;
1023
1024	/*
1025	 * select suitable win
1026	 */
1027	win = ov772x_select_win(pix->width, pix->height);
1028
1029	pix->width  = win->width;
1030	pix->height = win->height;
1031	pix->field  = V4L2_FIELD_NONE;
1032
1033	return 0;
1034}
1035
1036static int ov772x_video_probe(struct soc_camera_device *icd,
1037			      struct i2c_client *client)
1038{
1039	struct ov772x_priv *priv = to_ov772x(client);
1040	u8                  pid, ver;
1041	const char         *devname;
1042
1043	/*
1044	 * We must have a parent by now. And it cannot be a wrong one.
1045	 * So this entire test is completely redundant.
1046	 */
1047	if (!icd->dev.parent ||
1048	    to_soc_camera_host(icd->dev.parent)->nr != icd->iface)
1049		return -ENODEV;
1050
1051	/*
1052	 * ov772x only use 8 or 10 bit bus width
1053	 */
1054	if (SOCAM_DATAWIDTH_10 != priv->info->buswidth &&
1055	    SOCAM_DATAWIDTH_8  != priv->info->buswidth) {
1056		dev_err(&client->dev, "bus width error\n");
1057		return -ENODEV;
1058	}
1059
1060	icd->formats     = ov772x_fmt_lists;
1061	icd->num_formats = ARRAY_SIZE(ov772x_fmt_lists);
1062
1063	/*
1064	 * check and show product ID and manufacturer ID
1065	 */
1066	pid = i2c_smbus_read_byte_data(client, PID);
1067	ver = i2c_smbus_read_byte_data(client, VER);
1068
1069	switch (VERSION(pid, ver)) {
1070	case OV7720:
1071		devname     = "ov7720";
1072		priv->model = V4L2_IDENT_OV7720;
1073		break;
1074	case OV7725:
1075		devname     = "ov7725";
1076		priv->model = V4L2_IDENT_OV7725;
1077		break;
1078	default:
1079		dev_err(&client->dev,
1080			"Product ID error %x:%x\n", pid, ver);
1081		return -ENODEV;
1082	}
1083
1084	dev_info(&client->dev,
1085		 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
1086		 devname,
1087		 pid,
1088		 ver,
1089		 i2c_smbus_read_byte_data(client, MIDH),
1090		 i2c_smbus_read_byte_data(client, MIDL));
1091
1092	return 0;
1093}
1094
1095static struct soc_camera_ops ov772x_ops = {
1096	.set_bus_param		= ov772x_set_bus_param,
1097	.query_bus_param	= ov772x_query_bus_param,
1098	.controls		= ov772x_controls,
1099	.num_controls		= ARRAY_SIZE(ov772x_controls),
1100};
1101
1102static struct v4l2_subdev_core_ops ov772x_subdev_core_ops = {
1103	.g_ctrl		= ov772x_g_ctrl,
1104	.s_ctrl		= ov772x_s_ctrl,
1105	.g_chip_ident	= ov772x_g_chip_ident,
1106#ifdef CONFIG_VIDEO_ADV_DEBUG
1107	.g_register	= ov772x_g_register,
1108	.s_register	= ov772x_s_register,
1109#endif
1110};
1111
1112static struct v4l2_subdev_video_ops ov772x_subdev_video_ops = {
1113	.s_stream	= ov772x_s_stream,
1114	.g_fmt		= ov772x_g_fmt,
1115	.s_fmt		= ov772x_s_fmt,
1116	.try_fmt	= ov772x_try_fmt,
1117	.cropcap	= ov772x_cropcap,
1118	.g_crop		= ov772x_g_crop,
1119};
1120
1121static struct v4l2_subdev_ops ov772x_subdev_ops = {
1122	.core	= &ov772x_subdev_core_ops,
1123	.video	= &ov772x_subdev_video_ops,
1124};
1125
1126/*
1127 * i2c_driver function
1128 */
1129
1130static int ov772x_probe(struct i2c_client *client,
1131			const struct i2c_device_id *did)
1132{
1133	struct ov772x_priv        *priv;
1134	struct ov772x_camera_info *info;
1135	struct soc_camera_device  *icd = client->dev.platform_data;
1136	struct i2c_adapter        *adapter = to_i2c_adapter(client->dev.parent);
1137	struct soc_camera_link    *icl;
1138	int                        ret;
1139
1140	if (!icd) {
1141		dev_err(&client->dev, "OV772X: missing soc-camera data!\n");
1142		return -EINVAL;
1143	}
1144
1145	icl = to_soc_camera_link(icd);
1146	if (!icl)
1147		return -EINVAL;
1148
1149	info = container_of(icl, struct ov772x_camera_info, link);
1150
1151	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1152		dev_err(&adapter->dev,
1153			"I2C-Adapter doesn't support "
1154			"I2C_FUNC_SMBUS_BYTE_DATA\n");
1155		return -EIO;
1156	}
1157
1158	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1159	if (!priv)
1160		return -ENOMEM;
1161
1162	priv->info = info;
1163
1164	v4l2_i2c_subdev_init(&priv->subdev, client, &ov772x_subdev_ops);
1165
1166	icd->ops		= &ov772x_ops;
1167
1168	ret = ov772x_video_probe(icd, client);
1169	if (ret) {
1170		icd->ops = NULL;
1171		i2c_set_clientdata(client, NULL);
1172		kfree(priv);
1173	}
1174
1175	return ret;
1176}
1177
1178static int ov772x_remove(struct i2c_client *client)
1179{
1180	struct ov772x_priv *priv = to_ov772x(client);
1181	struct soc_camera_device *icd = client->dev.platform_data;
1182
1183	icd->ops = NULL;
1184	i2c_set_clientdata(client, NULL);
1185	kfree(priv);
1186	return 0;
1187}
1188
1189static const struct i2c_device_id ov772x_id[] = {
1190	{ "ov772x", 0 },
1191	{ }
1192};
1193MODULE_DEVICE_TABLE(i2c, ov772x_id);
1194
1195static struct i2c_driver ov772x_i2c_driver = {
1196	.driver = {
1197		.name = "ov772x",
1198	},
1199	.probe    = ov772x_probe,
1200	.remove   = ov772x_remove,
1201	.id_table = ov772x_id,
1202};
1203
1204/*
1205 * module function
1206 */
1207
1208static int __init ov772x_module_init(void)
1209{
1210	return i2c_add_driver(&ov772x_i2c_driver);
1211}
1212
1213static void __exit ov772x_module_exit(void)
1214{
1215	i2c_del_driver(&ov772x_i2c_driver);
1216}
1217
1218module_init(ov772x_module_init);
1219module_exit(ov772x_module_exit);
1220
1221MODULE_DESCRIPTION("SoC Camera driver for ov772x");
1222MODULE_AUTHOR("Kuninori Morimoto");
1223MODULE_LICENSE("GPL v2");
1224