1/* 2 * Samsung S5P Multi Format Codec v 5.1 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Kamil Debski, <k.debski@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/clk.h> 14#include <linux/delay.h> 15#include <linux/interrupt.h> 16#include <linux/io.h> 17#include <linux/module.h> 18#include <linux/platform_device.h> 19#include <linux/sched.h> 20#include <linux/slab.h> 21#include <linux/videodev2.h> 22#include <linux/workqueue.h> 23#include <media/videobuf2-core.h> 24#include "regs-mfc.h" 25#include "s5p_mfc_ctrl.h" 26#include "s5p_mfc_debug.h" 27#include "s5p_mfc_dec.h" 28#include "s5p_mfc_enc.h" 29#include "s5p_mfc_intr.h" 30#include "s5p_mfc_opr.h" 31#include "s5p_mfc_pm.h" 32#include "s5p_mfc_shm.h" 33 34#define S5P_MFC_NAME "s5p-mfc" 35#define S5P_MFC_DEC_NAME "s5p-mfc-dec" 36#define S5P_MFC_ENC_NAME "s5p-mfc-enc" 37 38int debug; 39module_param(debug, int, S_IRUGO | S_IWUSR); 40MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages"); 41 42/* Helper functions for interrupt processing */ 43/* Remove from hw execution round robin */ 44static void clear_work_bit(struct s5p_mfc_ctx *ctx) 45{ 46 struct s5p_mfc_dev *dev = ctx->dev; 47 48 spin_lock(&dev->condlock); 49 clear_bit(ctx->num, &dev->ctx_work_bits); 50 spin_unlock(&dev->condlock); 51} 52 53/* Wake up context wait_queue */ 54static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, 55 unsigned int err) 56{ 57 ctx->int_cond = 1; 58 ctx->int_type = reason; 59 ctx->int_err = err; 60 wake_up(&ctx->queue); 61} 62 63/* Wake up device wait_queue */ 64static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason, 65 unsigned int err) 66{ 67 dev->int_cond = 1; 68 dev->int_type = reason; 69 dev->int_err = err; 70 wake_up(&dev->queue); 71} 72 73void s5p_mfc_watchdog(unsigned long arg) 74{ 75 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg; 76 77 if (test_bit(0, &dev->hw_lock)) 78 atomic_inc(&dev->watchdog_cnt); 79 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) { 80 /* This means that hw is busy and no interrupts were 81 * generated by hw for the Nth time of running this 82 * watchdog timer. This usually means a serious hw 83 * error. Now it is time to kill all instances and 84 * reset the MFC. */ 85 mfc_err("Time out during waiting for HW\n"); 86 queue_work(dev->watchdog_workqueue, &dev->watchdog_work); 87 } 88 dev->watchdog_timer.expires = jiffies + 89 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 90 add_timer(&dev->watchdog_timer); 91} 92 93static void s5p_mfc_watchdog_worker(struct work_struct *work) 94{ 95 struct s5p_mfc_dev *dev; 96 struct s5p_mfc_ctx *ctx; 97 unsigned long flags; 98 int mutex_locked; 99 int i, ret; 100 101 dev = container_of(work, struct s5p_mfc_dev, watchdog_work); 102 103 mfc_err("Driver timeout error handling\n"); 104 /* Lock the mutex that protects open and release. 105 * This is necessary as they may load and unload firmware. */ 106 mutex_locked = mutex_trylock(&dev->mfc_mutex); 107 if (!mutex_locked) 108 mfc_err("Error: some instance may be closing/opening\n"); 109 spin_lock_irqsave(&dev->irqlock, flags); 110 111 s5p_mfc_clock_off(); 112 113 for (i = 0; i < MFC_NUM_CONTEXTS; i++) { 114 ctx = dev->ctx[i]; 115 if (!ctx) 116 continue; 117 ctx->state = MFCINST_ERROR; 118 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst); 119 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src); 120 clear_work_bit(ctx); 121 wake_up_ctx(ctx, S5P_FIMV_R2H_CMD_ERR_RET, 0); 122 } 123 clear_bit(0, &dev->hw_lock); 124 spin_unlock_irqrestore(&dev->irqlock, flags); 125 /* Double check if there is at least one instance running. 126 * If no instance is in memory than no firmware should be present */ 127 if (dev->num_inst > 0) { 128 ret = s5p_mfc_reload_firmware(dev); 129 if (ret) { 130 mfc_err("Failed to reload FW\n"); 131 goto unlock; 132 } 133 s5p_mfc_clock_on(); 134 ret = s5p_mfc_init_hw(dev); 135 if (ret) 136 mfc_err("Failed to reinit FW\n"); 137 } 138unlock: 139 if (mutex_locked) 140 mutex_unlock(&dev->mfc_mutex); 141} 142 143static enum s5p_mfc_node_type s5p_mfc_get_node_type(struct file *file) 144{ 145 struct video_device *vdev = video_devdata(file); 146 147 if (!vdev) { 148 mfc_err("failed to get video_device"); 149 return MFCNODE_INVALID; 150 } 151 if (vdev->index == 0) 152 return MFCNODE_DECODER; 153 else if (vdev->index == 1) 154 return MFCNODE_ENCODER; 155 return MFCNODE_INVALID; 156} 157 158static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev) 159{ 160 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT); 161 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD); 162 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID); 163} 164 165static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx) 166{ 167 struct s5p_mfc_buf *dst_buf; 168 169 ctx->state = MFCINST_FINISHED; 170 ctx->sequence++; 171 while (!list_empty(&ctx->dst_queue)) { 172 dst_buf = list_entry(ctx->dst_queue.next, 173 struct s5p_mfc_buf, list); 174 mfc_debug(2, "Cleaning up buffer: %d\n", 175 dst_buf->b->v4l2_buf.index); 176 vb2_set_plane_payload(dst_buf->b, 0, 0); 177 vb2_set_plane_payload(dst_buf->b, 1, 0); 178 list_del(&dst_buf->list); 179 ctx->dst_queue_cnt--; 180 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++); 181 182 if (s5p_mfc_read_shm(ctx, PIC_TIME_TOP) == 183 s5p_mfc_read_shm(ctx, PIC_TIME_BOT)) 184 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 185 else 186 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED; 187 188 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index); 189 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE); 190 } 191} 192 193static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx) 194{ 195 struct s5p_mfc_dev *dev = ctx->dev; 196 struct s5p_mfc_buf *dst_buf, *src_buf; 197 size_t dec_y_addr = s5p_mfc_get_dec_y_adr(); 198 unsigned int frame_type = s5p_mfc_get_frame_type(); 199 200 /* Copy timestamp / timecode from decoded src to dst and set 201 appropraite flags */ 202 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 203 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 204 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) { 205 memcpy(&dst_buf->b->v4l2_buf.timecode, 206 &src_buf->b->v4l2_buf.timecode, 207 sizeof(struct v4l2_timecode)); 208 memcpy(&dst_buf->b->v4l2_buf.timestamp, 209 &src_buf->b->v4l2_buf.timestamp, 210 sizeof(struct timeval)); 211 switch (frame_type) { 212 case S5P_FIMV_DECODE_FRAME_I_FRAME: 213 dst_buf->b->v4l2_buf.flags |= 214 V4L2_BUF_FLAG_KEYFRAME; 215 break; 216 case S5P_FIMV_DECODE_FRAME_P_FRAME: 217 dst_buf->b->v4l2_buf.flags |= 218 V4L2_BUF_FLAG_PFRAME; 219 break; 220 case S5P_FIMV_DECODE_FRAME_B_FRAME: 221 dst_buf->b->v4l2_buf.flags |= 222 V4L2_BUF_FLAG_BFRAME; 223 break; 224 } 225 break; 226 } 227 } 228} 229 230static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err) 231{ 232 struct s5p_mfc_dev *dev = ctx->dev; 233 struct s5p_mfc_buf *dst_buf; 234 size_t dspl_y_addr = s5p_mfc_get_dspl_y_adr(); 235 unsigned int frame_type = s5p_mfc_get_frame_type(); 236 unsigned int index; 237 238 /* If frame is same as previous then skip and do not dequeue */ 239 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) { 240 if (!ctx->after_packed_pb) 241 ctx->sequence++; 242 ctx->after_packed_pb = 0; 243 return; 244 } 245 ctx->sequence++; 246 /* The MFC returns address of the buffer, now we have to 247 * check which videobuf does it correspond to */ 248 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 249 /* Check if this is the buffer we're looking for */ 250 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) { 251 list_del(&dst_buf->list); 252 ctx->dst_queue_cnt--; 253 dst_buf->b->v4l2_buf.sequence = ctx->sequence; 254 if (s5p_mfc_read_shm(ctx, PIC_TIME_TOP) == 255 s5p_mfc_read_shm(ctx, PIC_TIME_BOT)) 256 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 257 else 258 dst_buf->b->v4l2_buf.field = 259 V4L2_FIELD_INTERLACED; 260 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size); 261 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size); 262 clear_bit(dst_buf->b->v4l2_buf.index, 263 &ctx->dec_dst_flag); 264 265 vb2_buffer_done(dst_buf->b, 266 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); 267 268 index = dst_buf->b->v4l2_buf.index; 269 break; 270 } 271 } 272} 273 274/* Handle frame decoding interrupt */ 275static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx, 276 unsigned int reason, unsigned int err) 277{ 278 struct s5p_mfc_dev *dev = ctx->dev; 279 unsigned int dst_frame_status; 280 struct s5p_mfc_buf *src_buf; 281 unsigned long flags; 282 unsigned int res_change; 283 284 unsigned int index; 285 286 dst_frame_status = s5p_mfc_get_dspl_status() 287 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; 288 res_change = s5p_mfc_get_dspl_status() 289 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK; 290 mfc_debug(2, "Frame Status: %x\n", dst_frame_status); 291 if (ctx->state == MFCINST_RES_CHANGE_INIT) 292 ctx->state = MFCINST_RES_CHANGE_FLUSH; 293 if (res_change) { 294 ctx->state = MFCINST_RES_CHANGE_INIT; 295 s5p_mfc_clear_int_flags(dev); 296 wake_up_ctx(ctx, reason, err); 297 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 298 BUG(); 299 s5p_mfc_clock_off(); 300 s5p_mfc_try_run(dev); 301 return; 302 } 303 if (ctx->dpb_flush_flag) 304 ctx->dpb_flush_flag = 0; 305 306 spin_lock_irqsave(&dev->irqlock, flags); 307 /* All frames remaining in the buffer have been extracted */ 308 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) { 309 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) { 310 s5p_mfc_handle_frame_all_extracted(ctx); 311 ctx->state = MFCINST_RES_CHANGE_END; 312 goto leave_handle_frame; 313 } else { 314 s5p_mfc_handle_frame_all_extracted(ctx); 315 } 316 } 317 318 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY || 319 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY) 320 s5p_mfc_handle_frame_copy_time(ctx); 321 322 /* A frame has been decoded and is in the buffer */ 323 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY || 324 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) { 325 s5p_mfc_handle_frame_new(ctx, err); 326 } else { 327 mfc_debug(2, "No frame decode\n"); 328 } 329 /* Mark source buffer as complete */ 330 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY 331 && !list_empty(&ctx->src_queue)) { 332 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, 333 list); 334 ctx->consumed_stream += s5p_mfc_get_consumed_stream(); 335 if (ctx->codec_mode != S5P_FIMV_CODEC_H264_DEC && 336 s5p_mfc_get_frame_type() == S5P_FIMV_DECODE_FRAME_P_FRAME 337 && ctx->consumed_stream + STUFF_BYTE < 338 src_buf->b->v4l2_planes[0].bytesused) { 339 /* Run MFC again on the same buffer */ 340 mfc_debug(2, "Running again the same buffer\n"); 341 ctx->after_packed_pb = 1; 342 } else { 343 index = src_buf->b->v4l2_buf.index; 344 mfc_debug(2, "MFC needs next buffer\n"); 345 ctx->consumed_stream = 0; 346 list_del(&src_buf->list); 347 ctx->src_queue_cnt--; 348 if (s5p_mfc_err_dec(err) > 0) 349 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR); 350 else 351 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE); 352 } 353 } 354leave_handle_frame: 355 spin_unlock_irqrestore(&dev->irqlock, flags); 356 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING) 357 || ctx->dst_queue_cnt < ctx->dpb_count) 358 clear_work_bit(ctx); 359 s5p_mfc_clear_int_flags(dev); 360 wake_up_ctx(ctx, reason, err); 361 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 362 BUG(); 363 s5p_mfc_clock_off(); 364 s5p_mfc_try_run(dev); 365} 366 367/* Error handling for interrupt */ 368static void s5p_mfc_handle_error(struct s5p_mfc_ctx *ctx, 369 unsigned int reason, unsigned int err) 370{ 371 struct s5p_mfc_dev *dev; 372 unsigned long flags; 373 374 /* If no context is available then all necessary 375 * processing has been done. */ 376 if (ctx == 0) 377 return; 378 379 dev = ctx->dev; 380 mfc_err("Interrupt Error: %08x\n", err); 381 s5p_mfc_clear_int_flags(dev); 382 wake_up_dev(dev, reason, err); 383 384 /* Error recovery is dependent on the state of context */ 385 switch (ctx->state) { 386 case MFCINST_INIT: 387 /* This error had to happen while acquireing instance */ 388 case MFCINST_GOT_INST: 389 /* This error had to happen while parsing the header */ 390 case MFCINST_HEAD_PARSED: 391 /* This error had to happen while setting dst buffers */ 392 case MFCINST_RETURN_INST: 393 /* This error had to happen while releasing instance */ 394 clear_work_bit(ctx); 395 wake_up_ctx(ctx, reason, err); 396 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 397 BUG(); 398 s5p_mfc_clock_off(); 399 ctx->state = MFCINST_ERROR; 400 break; 401 case MFCINST_FINISHING: 402 case MFCINST_FINISHED: 403 case MFCINST_RUNNING: 404 /* It is higly probable that an error occured 405 * while decoding a frame */ 406 clear_work_bit(ctx); 407 ctx->state = MFCINST_ERROR; 408 /* Mark all dst buffers as having an error */ 409 spin_lock_irqsave(&dev->irqlock, flags); 410 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst); 411 /* Mark all src buffers as having an error */ 412 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src); 413 spin_unlock_irqrestore(&dev->irqlock, flags); 414 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 415 BUG(); 416 s5p_mfc_clock_off(); 417 break; 418 default: 419 mfc_err("Encountered an error interrupt which had not been handled\n"); 420 break; 421 } 422 return; 423} 424 425/* Header parsing interrupt handling */ 426static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, 427 unsigned int reason, unsigned int err) 428{ 429 struct s5p_mfc_dev *dev; 430 unsigned int guard_width, guard_height; 431 432 if (ctx == 0) 433 return; 434 dev = ctx->dev; 435 if (ctx->c_ops->post_seq_start) { 436 if (ctx->c_ops->post_seq_start(ctx)) 437 mfc_err("post_seq_start() failed\n"); 438 } else { 439 ctx->img_width = s5p_mfc_get_img_width(); 440 ctx->img_height = s5p_mfc_get_img_height(); 441 442 ctx->buf_width = ALIGN(ctx->img_width, 443 S5P_FIMV_NV12MT_HALIGN); 444 ctx->buf_height = ALIGN(ctx->img_height, 445 S5P_FIMV_NV12MT_VALIGN); 446 mfc_debug(2, "SEQ Done: Movie dimensions %dx%d, " 447 "buffer dimensions: %dx%d\n", ctx->img_width, 448 ctx->img_height, ctx->buf_width, 449 ctx->buf_height); 450 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC) { 451 ctx->luma_size = ALIGN(ctx->buf_width * 452 ctx->buf_height, S5P_FIMV_DEC_BUF_ALIGN); 453 ctx->chroma_size = ALIGN(ctx->buf_width * 454 ALIGN((ctx->img_height >> 1), 455 S5P_FIMV_NV12MT_VALIGN), 456 S5P_FIMV_DEC_BUF_ALIGN); 457 ctx->mv_size = ALIGN(ctx->buf_width * 458 ALIGN((ctx->buf_height >> 2), 459 S5P_FIMV_NV12MT_VALIGN), 460 S5P_FIMV_DEC_BUF_ALIGN); 461 } else { 462 guard_width = ALIGN(ctx->img_width + 24, 463 S5P_FIMV_NV12MT_HALIGN); 464 guard_height = ALIGN(ctx->img_height + 16, 465 S5P_FIMV_NV12MT_VALIGN); 466 ctx->luma_size = ALIGN(guard_width * 467 guard_height, S5P_FIMV_DEC_BUF_ALIGN); 468 guard_width = ALIGN(ctx->img_width + 16, 469 S5P_FIMV_NV12MT_HALIGN); 470 guard_height = ALIGN((ctx->img_height >> 1) + 4, 471 S5P_FIMV_NV12MT_VALIGN); 472 ctx->chroma_size = ALIGN(guard_width * 473 guard_height, S5P_FIMV_DEC_BUF_ALIGN); 474 ctx->mv_size = 0; 475 } 476 ctx->dpb_count = s5p_mfc_get_dpb_count(); 477 if (ctx->img_width == 0 || ctx->img_height == 0) 478 ctx->state = MFCINST_ERROR; 479 else 480 ctx->state = MFCINST_HEAD_PARSED; 481 } 482 s5p_mfc_clear_int_flags(dev); 483 clear_work_bit(ctx); 484 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 485 BUG(); 486 s5p_mfc_clock_off(); 487 s5p_mfc_try_run(dev); 488 wake_up_ctx(ctx, reason, err); 489} 490 491/* Header parsing interrupt handling */ 492static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx, 493 unsigned int reason, unsigned int err) 494{ 495 struct s5p_mfc_buf *src_buf; 496 struct s5p_mfc_dev *dev; 497 unsigned long flags; 498 499 if (ctx == 0) 500 return; 501 dev = ctx->dev; 502 s5p_mfc_clear_int_flags(dev); 503 ctx->int_type = reason; 504 ctx->int_err = err; 505 ctx->int_cond = 1; 506 spin_lock(&dev->condlock); 507 clear_bit(ctx->num, &dev->ctx_work_bits); 508 spin_unlock(&dev->condlock); 509 if (err == 0) { 510 ctx->state = MFCINST_RUNNING; 511 if (!ctx->dpb_flush_flag) { 512 spin_lock_irqsave(&dev->irqlock, flags); 513 if (!list_empty(&ctx->src_queue)) { 514 src_buf = list_entry(ctx->src_queue.next, 515 struct s5p_mfc_buf, list); 516 list_del(&src_buf->list); 517 ctx->src_queue_cnt--; 518 vb2_buffer_done(src_buf->b, 519 VB2_BUF_STATE_DONE); 520 } 521 spin_unlock_irqrestore(&dev->irqlock, flags); 522 } else { 523 ctx->dpb_flush_flag = 0; 524 } 525 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 526 BUG(); 527 528 s5p_mfc_clock_off(); 529 530 wake_up(&ctx->queue); 531 s5p_mfc_try_run(dev); 532 } else { 533 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 534 BUG(); 535 536 s5p_mfc_clock_off(); 537 538 wake_up(&ctx->queue); 539 } 540} 541 542/* Interrupt processing */ 543static irqreturn_t s5p_mfc_irq(int irq, void *priv) 544{ 545 struct s5p_mfc_dev *dev = priv; 546 struct s5p_mfc_ctx *ctx; 547 unsigned int reason; 548 unsigned int err; 549 550 mfc_debug_enter(); 551 /* Reset the timeout watchdog */ 552 atomic_set(&dev->watchdog_cnt, 0); 553 ctx = dev->ctx[dev->curr_ctx]; 554 /* Get the reason of interrupt and the error code */ 555 reason = s5p_mfc_get_int_reason(); 556 err = s5p_mfc_get_int_err(); 557 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err); 558 switch (reason) { 559 case S5P_FIMV_R2H_CMD_ERR_RET: 560 /* An error has occured */ 561 if (ctx->state == MFCINST_RUNNING && 562 s5p_mfc_err_dec(err) >= S5P_FIMV_ERR_WARNINGS_START) 563 s5p_mfc_handle_frame(ctx, reason, err); 564 else 565 s5p_mfc_handle_error(ctx, reason, err); 566 clear_bit(0, &dev->enter_suspend); 567 break; 568 569 case S5P_FIMV_R2H_CMD_SLICE_DONE_RET: 570 case S5P_FIMV_R2H_CMD_FRAME_DONE_RET: 571 if (ctx->c_ops->post_frame_start) { 572 if (ctx->c_ops->post_frame_start(ctx)) 573 mfc_err("post_frame_start() failed\n"); 574 s5p_mfc_clear_int_flags(dev); 575 wake_up_ctx(ctx, reason, err); 576 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 577 BUG(); 578 s5p_mfc_clock_off(); 579 s5p_mfc_try_run(dev); 580 } else { 581 s5p_mfc_handle_frame(ctx, reason, err); 582 } 583 break; 584 585 case S5P_FIMV_R2H_CMD_SEQ_DONE_RET: 586 s5p_mfc_handle_seq_done(ctx, reason, err); 587 break; 588 589 case S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET: 590 ctx->inst_no = s5p_mfc_get_inst_no(); 591 ctx->state = MFCINST_GOT_INST; 592 clear_work_bit(ctx); 593 wake_up(&ctx->queue); 594 goto irq_cleanup_hw; 595 596 case S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET: 597 clear_work_bit(ctx); 598 ctx->state = MFCINST_FREE; 599 wake_up(&ctx->queue); 600 goto irq_cleanup_hw; 601 602 case S5P_FIMV_R2H_CMD_SYS_INIT_RET: 603 case S5P_FIMV_R2H_CMD_FW_STATUS_RET: 604 case S5P_FIMV_R2H_CMD_SLEEP_RET: 605 case S5P_FIMV_R2H_CMD_WAKEUP_RET: 606 if (ctx) 607 clear_work_bit(ctx); 608 s5p_mfc_clear_int_flags(dev); 609 wake_up_dev(dev, reason, err); 610 clear_bit(0, &dev->hw_lock); 611 clear_bit(0, &dev->enter_suspend); 612 break; 613 614 case S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET: 615 s5p_mfc_handle_init_buffers(ctx, reason, err); 616 break; 617 default: 618 mfc_debug(2, "Unknown int reason\n"); 619 s5p_mfc_clear_int_flags(dev); 620 } 621 mfc_debug_leave(); 622 return IRQ_HANDLED; 623irq_cleanup_hw: 624 s5p_mfc_clear_int_flags(dev); 625 ctx->int_type = reason; 626 ctx->int_err = err; 627 ctx->int_cond = 1; 628 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 629 mfc_err("Failed to unlock hw\n"); 630 631 s5p_mfc_clock_off(); 632 633 s5p_mfc_try_run(dev); 634 mfc_debug(2, "Exit via irq_cleanup_hw\n"); 635 return IRQ_HANDLED; 636} 637 638/* Open an MFC node */ 639static int s5p_mfc_open(struct file *file) 640{ 641 struct s5p_mfc_dev *dev = video_drvdata(file); 642 struct s5p_mfc_ctx *ctx = NULL; 643 struct vb2_queue *q; 644 unsigned long flags; 645 int ret = 0; 646 647 mfc_debug_enter(); 648 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */ 649 /* Allocate memory for context */ 650 ctx = kzalloc(sizeof *ctx, GFP_KERNEL); 651 if (!ctx) { 652 mfc_err("Not enough memory\n"); 653 ret = -ENOMEM; 654 goto err_alloc; 655 } 656 v4l2_fh_init(&ctx->fh, video_devdata(file)); 657 file->private_data = &ctx->fh; 658 v4l2_fh_add(&ctx->fh); 659 ctx->dev = dev; 660 INIT_LIST_HEAD(&ctx->src_queue); 661 INIT_LIST_HEAD(&ctx->dst_queue); 662 ctx->src_queue_cnt = 0; 663 ctx->dst_queue_cnt = 0; 664 /* Get context number */ 665 ctx->num = 0; 666 while (dev->ctx[ctx->num]) { 667 ctx->num++; 668 if (ctx->num >= MFC_NUM_CONTEXTS) { 669 mfc_err("Too many open contexts\n"); 670 ret = -EBUSY; 671 goto err_no_ctx; 672 } 673 } 674 /* Mark context as idle */ 675 spin_lock_irqsave(&dev->condlock, flags); 676 clear_bit(ctx->num, &dev->ctx_work_bits); 677 spin_unlock_irqrestore(&dev->condlock, flags); 678 dev->ctx[ctx->num] = ctx; 679 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 680 ctx->type = MFCINST_DECODER; 681 ctx->c_ops = get_dec_codec_ops(); 682 /* Setup ctrl handler */ 683 ret = s5p_mfc_dec_ctrls_setup(ctx); 684 if (ret) { 685 mfc_err("Failed to setup mfc controls\n"); 686 goto err_ctrls_setup; 687 } 688 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 689 ctx->type = MFCINST_ENCODER; 690 ctx->c_ops = get_enc_codec_ops(); 691 /* only for encoder */ 692 INIT_LIST_HEAD(&ctx->ref_queue); 693 ctx->ref_queue_cnt = 0; 694 /* Setup ctrl handler */ 695 ret = s5p_mfc_enc_ctrls_setup(ctx); 696 if (ret) { 697 mfc_err("Failed to setup mfc controls\n"); 698 goto err_ctrls_setup; 699 } 700 } else { 701 ret = -ENOENT; 702 goto err_bad_node; 703 } 704 ctx->fh.ctrl_handler = &ctx->ctrl_handler; 705 ctx->inst_no = -1; 706 /* Load firmware if this is the first instance */ 707 if (dev->num_inst == 1) { 708 dev->watchdog_timer.expires = jiffies + 709 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 710 add_timer(&dev->watchdog_timer); 711 ret = s5p_mfc_power_on(); 712 if (ret < 0) { 713 mfc_err("power on failed\n"); 714 goto err_pwr_enable; 715 } 716 s5p_mfc_clock_on(); 717 ret = s5p_mfc_alloc_and_load_firmware(dev); 718 if (ret) 719 goto err_alloc_fw; 720 /* Init the FW */ 721 ret = s5p_mfc_init_hw(dev); 722 if (ret) 723 goto err_init_hw; 724 s5p_mfc_clock_off(); 725 } 726 /* Init videobuf2 queue for CAPTURE */ 727 q = &ctx->vq_dst; 728 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 729 q->drv_priv = &ctx->fh; 730 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 731 q->io_modes = VB2_MMAP; 732 q->ops = get_dec_queue_ops(); 733 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 734 q->io_modes = VB2_MMAP | VB2_USERPTR; 735 q->ops = get_enc_queue_ops(); 736 } else { 737 ret = -ENOENT; 738 goto err_queue_init; 739 } 740 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 741 ret = vb2_queue_init(q); 742 if (ret) { 743 mfc_err("Failed to initialize videobuf2 queue(capture)\n"); 744 goto err_queue_init; 745 } 746 /* Init videobuf2 queue for OUTPUT */ 747 q = &ctx->vq_src; 748 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 749 q->io_modes = VB2_MMAP; 750 q->drv_priv = &ctx->fh; 751 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 752 q->io_modes = VB2_MMAP; 753 q->ops = get_dec_queue_ops(); 754 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 755 q->io_modes = VB2_MMAP | VB2_USERPTR; 756 q->ops = get_enc_queue_ops(); 757 } else { 758 ret = -ENOENT; 759 goto err_queue_init; 760 } 761 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 762 ret = vb2_queue_init(q); 763 if (ret) { 764 mfc_err("Failed to initialize videobuf2 queue(output)\n"); 765 goto err_queue_init; 766 } 767 init_waitqueue_head(&ctx->queue); 768 mfc_debug_leave(); 769 return ret; 770 /* Deinit when failure occured */ 771err_queue_init: 772err_init_hw: 773 s5p_mfc_release_firmware(dev); 774err_alloc_fw: 775 dev->ctx[ctx->num] = 0; 776 del_timer_sync(&dev->watchdog_timer); 777 s5p_mfc_clock_off(); 778err_pwr_enable: 779 if (dev->num_inst == 1) { 780 if (s5p_mfc_power_off() < 0) 781 mfc_err("power off failed\n"); 782 s5p_mfc_release_firmware(dev); 783 } 784err_ctrls_setup: 785 s5p_mfc_dec_ctrls_delete(ctx); 786err_bad_node: 787err_no_ctx: 788 v4l2_fh_del(&ctx->fh); 789 v4l2_fh_exit(&ctx->fh); 790 kfree(ctx); 791err_alloc: 792 dev->num_inst--; 793 mfc_debug_leave(); 794 return ret; 795} 796 797/* Release MFC context */ 798static int s5p_mfc_release(struct file *file) 799{ 800 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 801 struct s5p_mfc_dev *dev = ctx->dev; 802 unsigned long flags; 803 804 mfc_debug_enter(); 805 s5p_mfc_clock_on(); 806 vb2_queue_release(&ctx->vq_src); 807 vb2_queue_release(&ctx->vq_dst); 808 /* Mark context as idle */ 809 spin_lock_irqsave(&dev->condlock, flags); 810 clear_bit(ctx->num, &dev->ctx_work_bits); 811 spin_unlock_irqrestore(&dev->condlock, flags); 812 /* If instance was initialised then 813 * return instance and free reosurces */ 814 if (ctx->inst_no != MFC_NO_INSTANCE_SET) { 815 mfc_debug(2, "Has to free instance\n"); 816 ctx->state = MFCINST_RETURN_INST; 817 spin_lock_irqsave(&dev->condlock, flags); 818 set_bit(ctx->num, &dev->ctx_work_bits); 819 spin_unlock_irqrestore(&dev->condlock, flags); 820 s5p_mfc_clean_ctx_int_flags(ctx); 821 s5p_mfc_try_run(dev); 822 /* Wait until instance is returned or timeout occured */ 823 if (s5p_mfc_wait_for_done_ctx 824 (ctx, S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET, 0)) { 825 s5p_mfc_clock_off(); 826 mfc_err("Err returning instance\n"); 827 } 828 mfc_debug(2, "After free instance\n"); 829 /* Free resources */ 830 s5p_mfc_release_codec_buffers(ctx); 831 s5p_mfc_release_instance_buffer(ctx); 832 if (ctx->type == MFCINST_DECODER) 833 s5p_mfc_release_dec_desc_buffer(ctx); 834 835 ctx->inst_no = MFC_NO_INSTANCE_SET; 836 } 837 /* hardware locking scheme */ 838 if (dev->curr_ctx == ctx->num) 839 clear_bit(0, &dev->hw_lock); 840 dev->num_inst--; 841 if (dev->num_inst == 0) { 842 mfc_debug(2, "Last instance - release firmware\n"); 843 /* reset <-> F/W release */ 844 s5p_mfc_reset(dev); 845 s5p_mfc_release_firmware(dev); 846 del_timer_sync(&dev->watchdog_timer); 847 if (s5p_mfc_power_off() < 0) 848 mfc_err("Power off failed\n"); 849 } 850 mfc_debug(2, "Shutting down clock\n"); 851 s5p_mfc_clock_off(); 852 dev->ctx[ctx->num] = 0; 853 s5p_mfc_dec_ctrls_delete(ctx); 854 v4l2_fh_del(&ctx->fh); 855 v4l2_fh_exit(&ctx->fh); 856 kfree(ctx); 857 mfc_debug_leave(); 858 return 0; 859} 860 861/* Poll */ 862static unsigned int s5p_mfc_poll(struct file *file, 863 struct poll_table_struct *wait) 864{ 865 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 866 struct s5p_mfc_dev *dev = ctx->dev; 867 struct vb2_queue *src_q, *dst_q; 868 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL; 869 unsigned int rc = 0; 870 unsigned long flags; 871 872 src_q = &ctx->vq_src; 873 dst_q = &ctx->vq_dst; 874 /* 875 * There has to be at least one buffer queued on each queued_list, which 876 * means either in driver already or waiting for driver to claim it 877 * and start processing. 878 */ 879 if ((!src_q->streaming || list_empty(&src_q->queued_list)) 880 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) { 881 rc = POLLERR; 882 goto end; 883 } 884 mutex_unlock(&dev->mfc_mutex); 885 poll_wait(file, &src_q->done_wq, wait); 886 poll_wait(file, &dst_q->done_wq, wait); 887 mutex_lock(&dev->mfc_mutex); 888 spin_lock_irqsave(&src_q->done_lock, flags); 889 if (!list_empty(&src_q->done_list)) 890 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer, 891 done_entry); 892 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE 893 || src_vb->state == VB2_BUF_STATE_ERROR)) 894 rc |= POLLOUT | POLLWRNORM; 895 spin_unlock_irqrestore(&src_q->done_lock, flags); 896 spin_lock_irqsave(&dst_q->done_lock, flags); 897 if (!list_empty(&dst_q->done_list)) 898 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer, 899 done_entry); 900 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE 901 || dst_vb->state == VB2_BUF_STATE_ERROR)) 902 rc |= POLLIN | POLLRDNORM; 903 spin_unlock_irqrestore(&dst_q->done_lock, flags); 904end: 905 return rc; 906} 907 908/* Mmap */ 909static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma) 910{ 911 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 912 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; 913 int ret; 914 if (offset < DST_QUEUE_OFF_BASE) { 915 mfc_debug(2, "mmaping source\n"); 916 ret = vb2_mmap(&ctx->vq_src, vma); 917 } else { /* capture */ 918 mfc_debug(2, "mmaping destination\n"); 919 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT); 920 ret = vb2_mmap(&ctx->vq_dst, vma); 921 } 922 return ret; 923} 924 925/* v4l2 ops */ 926static const struct v4l2_file_operations s5p_mfc_fops = { 927 .owner = THIS_MODULE, 928 .open = s5p_mfc_open, 929 .release = s5p_mfc_release, 930 .poll = s5p_mfc_poll, 931 .unlocked_ioctl = video_ioctl2, 932 .mmap = s5p_mfc_mmap, 933}; 934 935static int match_child(struct device *dev, void *data) 936{ 937 if (!dev_name(dev)) 938 return 0; 939 return !strcmp(dev_name(dev), (char *)data); 940} 941 942/* MFC probe function */ 943static int s5p_mfc_probe(struct platform_device *pdev) 944{ 945 struct s5p_mfc_dev *dev; 946 struct video_device *vfd; 947 struct resource *res; 948 int ret; 949 950 pr_debug("%s++\n", __func__); 951 dev = kzalloc(sizeof *dev, GFP_KERNEL); 952 if (!dev) { 953 dev_err(&pdev->dev, "Not enough memory for MFC device\n"); 954 return -ENOMEM; 955 } 956 957 spin_lock_init(&dev->irqlock); 958 spin_lock_init(&dev->condlock); 959 dev->plat_dev = pdev; 960 if (!dev->plat_dev) { 961 dev_err(&pdev->dev, "No platform data specified\n"); 962 ret = -ENODEV; 963 goto err_dev; 964 } 965 966 ret = s5p_mfc_init_pm(dev); 967 if (ret < 0) { 968 dev_err(&pdev->dev, "failed to get mfc clock source\n"); 969 goto err_clk; 970 } 971 972 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 973 if (res == NULL) { 974 dev_err(&pdev->dev, "failed to get memory region resource\n"); 975 ret = -ENOENT; 976 goto err_res; 977 } 978 979 dev->mfc_mem = request_mem_region(res->start, resource_size(res), 980 pdev->name); 981 if (dev->mfc_mem == NULL) { 982 dev_err(&pdev->dev, "failed to get memory region\n"); 983 ret = -ENOENT; 984 goto err_mem_reg; 985 } 986 dev->regs_base = ioremap(dev->mfc_mem->start, resource_size(dev->mfc_mem)); 987 if (dev->regs_base == NULL) { 988 dev_err(&pdev->dev, "failed to ioremap address region\n"); 989 ret = -ENOENT; 990 goto err_ioremap; 991 } 992 993 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 994 if (res == NULL) { 995 dev_err(&pdev->dev, "failed to get irq resource\n"); 996 ret = -ENOENT; 997 goto err_get_res; 998 } 999 dev->irq = res->start; 1000 ret = request_irq(dev->irq, s5p_mfc_irq, IRQF_DISABLED, pdev->name, 1001 dev); 1002 if (ret) { 1003 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret); 1004 goto err_req_irq; 1005 } 1006 1007 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev, "s5p-mfc-l", 1008 match_child); 1009 if (!dev->mem_dev_l) { 1010 mfc_err("Mem child (L) device get failed\n"); 1011 ret = -ENODEV; 1012 goto err_find_child; 1013 } 1014 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev, "s5p-mfc-r", 1015 match_child); 1016 if (!dev->mem_dev_r) { 1017 mfc_err("Mem child (R) device get failed\n"); 1018 ret = -ENODEV; 1019 goto err_find_child; 1020 } 1021 1022 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l); 1023 if (IS_ERR_OR_NULL(dev->alloc_ctx[0])) { 1024 ret = PTR_ERR(dev->alloc_ctx[0]); 1025 goto err_mem_init_ctx_0; 1026 } 1027 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r); 1028 if (IS_ERR_OR_NULL(dev->alloc_ctx[1])) { 1029 ret = PTR_ERR(dev->alloc_ctx[1]); 1030 goto err_mem_init_ctx_1; 1031 } 1032 1033 mutex_init(&dev->mfc_mutex); 1034 1035 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); 1036 if (ret) 1037 goto err_v4l2_dev_reg; 1038 init_waitqueue_head(&dev->queue); 1039 1040 /* decoder */ 1041 vfd = video_device_alloc(); 1042 if (!vfd) { 1043 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1044 ret = -ENOMEM; 1045 goto err_dec_alloc; 1046 } 1047 vfd->fops = &s5p_mfc_fops, 1048 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops(); 1049 vfd->release = video_device_release, 1050 vfd->lock = &dev->mfc_mutex; 1051 vfd->v4l2_dev = &dev->v4l2_dev; 1052 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME); 1053 dev->vfd_dec = vfd; 1054 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1055 if (ret) { 1056 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1057 video_device_release(vfd); 1058 goto err_dec_reg; 1059 } 1060 v4l2_info(&dev->v4l2_dev, 1061 "decoder registered as /dev/video%d\n", vfd->num); 1062 video_set_drvdata(vfd, dev); 1063 1064 /* encoder */ 1065 vfd = video_device_alloc(); 1066 if (!vfd) { 1067 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1068 ret = -ENOMEM; 1069 goto err_enc_alloc; 1070 } 1071 vfd->fops = &s5p_mfc_fops, 1072 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops(); 1073 vfd->release = video_device_release, 1074 vfd->lock = &dev->mfc_mutex; 1075 vfd->v4l2_dev = &dev->v4l2_dev; 1076 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME); 1077 dev->vfd_enc = vfd; 1078 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1079 if (ret) { 1080 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1081 video_device_release(vfd); 1082 goto err_enc_reg; 1083 } 1084 v4l2_info(&dev->v4l2_dev, 1085 "encoder registered as /dev/video%d\n", vfd->num); 1086 video_set_drvdata(vfd, dev); 1087 platform_set_drvdata(pdev, dev); 1088 1089 dev->hw_lock = 0; 1090 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME); 1091 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker); 1092 atomic_set(&dev->watchdog_cnt, 0); 1093 init_timer(&dev->watchdog_timer); 1094 dev->watchdog_timer.data = (unsigned long)dev; 1095 dev->watchdog_timer.function = s5p_mfc_watchdog; 1096 1097 pr_debug("%s--\n", __func__); 1098 return 0; 1099 1100/* Deinit MFC if probe had failed */ 1101err_enc_reg: 1102 video_device_release(dev->vfd_enc); 1103err_enc_alloc: 1104 video_unregister_device(dev->vfd_dec); 1105err_dec_reg: 1106 video_device_release(dev->vfd_dec); 1107err_dec_alloc: 1108 v4l2_device_unregister(&dev->v4l2_dev); 1109err_v4l2_dev_reg: 1110 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1111err_mem_init_ctx_1: 1112 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1113err_mem_init_ctx_0: 1114err_find_child: 1115 free_irq(dev->irq, dev); 1116err_req_irq: 1117err_get_res: 1118 iounmap(dev->regs_base); 1119 dev->regs_base = NULL; 1120err_ioremap: 1121 release_resource(dev->mfc_mem); 1122 kfree(dev->mfc_mem); 1123err_mem_reg: 1124err_res: 1125 s5p_mfc_final_pm(dev); 1126err_clk: 1127err_dev: 1128 kfree(dev); 1129 pr_debug("%s-- with error\n", __func__); 1130 return ret; 1131 1132} 1133 1134/* Remove the driver */ 1135static int __devexit s5p_mfc_remove(struct platform_device *pdev) 1136{ 1137 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev); 1138 1139 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name); 1140 1141 del_timer_sync(&dev->watchdog_timer); 1142 flush_workqueue(dev->watchdog_workqueue); 1143 destroy_workqueue(dev->watchdog_workqueue); 1144 1145 video_unregister_device(dev->vfd_enc); 1146 video_unregister_device(dev->vfd_dec); 1147 v4l2_device_unregister(&dev->v4l2_dev); 1148 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1149 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1150 1151 free_irq(dev->irq, dev); 1152 iounmap(dev->regs_base); 1153 if (dev->mfc_mem) { 1154 release_resource(dev->mfc_mem); 1155 kfree(dev->mfc_mem); 1156 dev->mfc_mem = NULL; 1157 } 1158 s5p_mfc_final_pm(dev); 1159 kfree(dev); 1160 return 0; 1161} 1162 1163#ifdef CONFIG_PM_SLEEP 1164 1165static int s5p_mfc_suspend(struct device *dev) 1166{ 1167 struct platform_device *pdev = to_platform_device(dev); 1168 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1169 int ret; 1170 1171 if (m_dev->num_inst == 0) 1172 return 0; 1173 return s5p_mfc_sleep(m_dev); 1174 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) { 1175 mfc_err("Error: going to suspend for a second time\n"); 1176 return -EIO; 1177 } 1178 1179 /* Check if we're processing then wait if it necessary. */ 1180 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) { 1181 /* Try and lock the HW */ 1182 /* Wait on the interrupt waitqueue */ 1183 ret = wait_event_interruptible_timeout(m_dev->queue, 1184 m_dev->int_cond || m_dev->ctx[m_dev->curr_ctx]->int_cond, 1185 msecs_to_jiffies(MFC_INT_TIMEOUT)); 1186 1187 if (ret == 0) { 1188 mfc_err("Waiting for hardware to finish timed out\n"); 1189 return -EIO; 1190 } 1191 } 1192 return 0; 1193} 1194 1195static int s5p_mfc_resume(struct device *dev) 1196{ 1197 struct platform_device *pdev = to_platform_device(dev); 1198 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1199 1200 if (m_dev->num_inst == 0) 1201 return 0; 1202 return s5p_mfc_wakeup(m_dev); 1203} 1204#endif 1205 1206#ifdef CONFIG_PM_RUNTIME 1207static int s5p_mfc_runtime_suspend(struct device *dev) 1208{ 1209 struct platform_device *pdev = to_platform_device(dev); 1210 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1211 1212 atomic_set(&m_dev->pm.power, 0); 1213 return 0; 1214} 1215 1216static int s5p_mfc_runtime_resume(struct device *dev) 1217{ 1218 struct platform_device *pdev = to_platform_device(dev); 1219 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1220 int pre_power; 1221 1222 if (!m_dev->alloc_ctx) 1223 return 0; 1224 pre_power = atomic_read(&m_dev->pm.power); 1225 atomic_set(&m_dev->pm.power, 1); 1226 return 0; 1227} 1228#endif 1229 1230/* Power management */ 1231static const struct dev_pm_ops s5p_mfc_pm_ops = { 1232 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume) 1233 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume, 1234 NULL) 1235}; 1236 1237static struct platform_driver s5p_mfc_driver = { 1238 .probe = s5p_mfc_probe, 1239 .remove = __devexit_p(s5p_mfc_remove), 1240 .driver = { 1241 .name = S5P_MFC_NAME, 1242 .owner = THIS_MODULE, 1243 .pm = &s5p_mfc_pm_ops 1244 }, 1245}; 1246 1247module_platform_driver(s5p_mfc_driver); 1248 1249MODULE_LICENSE("GPL"); 1250MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>"); 1251MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver"); 1252 1253