atmel-mci.c revision 341fa4c3affe1171005597847a86e4c26dea8bb1
1/* 2 * Atmel MultiMedia Card Interface driver 3 * 4 * Copyright (C) 2004-2008 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10#include <linux/blkdev.h> 11#include <linux/clk.h> 12#include <linux/debugfs.h> 13#include <linux/device.h> 14#include <linux/dmaengine.h> 15#include <linux/dma-mapping.h> 16#include <linux/err.h> 17#include <linux/gpio.h> 18#include <linux/init.h> 19#include <linux/interrupt.h> 20#include <linux/ioport.h> 21#include <linux/module.h> 22#include <linux/platform_device.h> 23#include <linux/scatterlist.h> 24#include <linux/seq_file.h> 25#include <linux/slab.h> 26#include <linux/stat.h> 27 28#include <linux/mmc/host.h> 29#include <linux/mmc/sdio.h> 30 31#include <mach/atmel-mci.h> 32#include <linux/atmel-mci.h> 33#include <linux/atmel_pdc.h> 34 35#include <asm/io.h> 36#include <asm/unaligned.h> 37 38#include <mach/cpu.h> 39#include <mach/board.h> 40 41#include "atmel-mci-regs.h" 42 43#define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE) 44#define ATMCI_DMA_THRESHOLD 16 45 46enum { 47 EVENT_CMD_COMPLETE = 0, 48 EVENT_XFER_COMPLETE, 49 EVENT_DATA_COMPLETE, 50 EVENT_DATA_ERROR, 51}; 52 53enum atmel_mci_state { 54 STATE_IDLE = 0, 55 STATE_SENDING_CMD, 56 STATE_SENDING_DATA, 57 STATE_DATA_BUSY, 58 STATE_SENDING_STOP, 59 STATE_DATA_ERROR, 60}; 61 62enum atmci_xfer_dir { 63 XFER_RECEIVE = 0, 64 XFER_TRANSMIT, 65}; 66 67enum atmci_pdc_buf { 68 PDC_FIRST_BUF = 0, 69 PDC_SECOND_BUF, 70}; 71 72struct atmel_mci_caps { 73 bool has_dma; 74 bool has_pdc; 75 bool has_cfg_reg; 76 bool has_cstor_reg; 77 bool has_highspeed; 78 bool has_rwproof; 79}; 80 81struct atmel_mci_dma { 82 struct dma_chan *chan; 83 struct dma_async_tx_descriptor *data_desc; 84}; 85 86/** 87 * struct atmel_mci - MMC controller state shared between all slots 88 * @lock: Spinlock protecting the queue and associated data. 89 * @regs: Pointer to MMIO registers. 90 * @sg: Scatterlist entry currently being processed by PIO or PDC code. 91 * @pio_offset: Offset into the current scatterlist entry. 92 * @cur_slot: The slot which is currently using the controller. 93 * @mrq: The request currently being processed on @cur_slot, 94 * or NULL if the controller is idle. 95 * @cmd: The command currently being sent to the card, or NULL. 96 * @data: The data currently being transferred, or NULL if no data 97 * transfer is in progress. 98 * @data_size: just data->blocks * data->blksz. 99 * @dma: DMA client state. 100 * @data_chan: DMA channel being used for the current data transfer. 101 * @cmd_status: Snapshot of SR taken upon completion of the current 102 * command. Only valid when EVENT_CMD_COMPLETE is pending. 103 * @data_status: Snapshot of SR taken upon completion of the current 104 * data transfer. Only valid when EVENT_DATA_COMPLETE or 105 * EVENT_DATA_ERROR is pending. 106 * @stop_cmdr: Value to be loaded into CMDR when the stop command is 107 * to be sent. 108 * @tasklet: Tasklet running the request state machine. 109 * @pending_events: Bitmask of events flagged by the interrupt handler 110 * to be processed by the tasklet. 111 * @completed_events: Bitmask of events which the state machine has 112 * processed. 113 * @state: Tasklet state. 114 * @queue: List of slots waiting for access to the controller. 115 * @need_clock_update: Update the clock rate before the next request. 116 * @need_reset: Reset controller before next request. 117 * @mode_reg: Value of the MR register. 118 * @cfg_reg: Value of the CFG register. 119 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 120 * rate and timeout calculations. 121 * @mapbase: Physical address of the MMIO registers. 122 * @mck: The peripheral bus clock hooked up to the MMC controller. 123 * @pdev: Platform device associated with the MMC controller. 124 * @slot: Slots sharing this MMC controller. 125 * @caps: MCI capabilities depending on MCI version. 126 * @prepare_data: function to setup MCI before data transfer which 127 * depends on MCI capabilities. 128 * @submit_data: function to start data transfer which depends on MCI 129 * capabilities. 130 * @stop_transfer: function to stop data transfer which depends on MCI 131 * capabilities. 132 * 133 * Locking 134 * ======= 135 * 136 * @lock is a softirq-safe spinlock protecting @queue as well as 137 * @cur_slot, @mrq and @state. These must always be updated 138 * at the same time while holding @lock. 139 * 140 * @lock also protects mode_reg and need_clock_update since these are 141 * used to synchronize mode register updates with the queue 142 * processing. 143 * 144 * The @mrq field of struct atmel_mci_slot is also protected by @lock, 145 * and must always be written at the same time as the slot is added to 146 * @queue. 147 * 148 * @pending_events and @completed_events are accessed using atomic bit 149 * operations, so they don't need any locking. 150 * 151 * None of the fields touched by the interrupt handler need any 152 * locking. However, ordering is important: Before EVENT_DATA_ERROR or 153 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 154 * interrupts must be disabled and @data_status updated with a 155 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 156 * CMDRDY interrupt must be disabled and @cmd_status updated with a 157 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 158 * bytes_xfered field of @data must be written. This is ensured by 159 * using barriers. 160 */ 161struct atmel_mci { 162 spinlock_t lock; 163 void __iomem *regs; 164 165 struct scatterlist *sg; 166 unsigned int pio_offset; 167 168 struct atmel_mci_slot *cur_slot; 169 struct mmc_request *mrq; 170 struct mmc_command *cmd; 171 struct mmc_data *data; 172 unsigned int data_size; 173 174 struct atmel_mci_dma dma; 175 struct dma_chan *data_chan; 176 177 u32 cmd_status; 178 u32 data_status; 179 u32 stop_cmdr; 180 181 struct tasklet_struct tasklet; 182 unsigned long pending_events; 183 unsigned long completed_events; 184 enum atmel_mci_state state; 185 struct list_head queue; 186 187 bool need_clock_update; 188 bool need_reset; 189 u32 mode_reg; 190 u32 cfg_reg; 191 unsigned long bus_hz; 192 unsigned long mapbase; 193 struct clk *mck; 194 struct platform_device *pdev; 195 196 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS]; 197 198 struct atmel_mci_caps caps; 199 200 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data); 201 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data); 202 void (*stop_transfer)(struct atmel_mci *host); 203}; 204 205/** 206 * struct atmel_mci_slot - MMC slot state 207 * @mmc: The mmc_host representing this slot. 208 * @host: The MMC controller this slot is using. 209 * @sdc_reg: Value of SDCR to be written before using this slot. 210 * @sdio_irq: SDIO irq mask for this slot. 211 * @mrq: mmc_request currently being processed or waiting to be 212 * processed, or NULL when the slot is idle. 213 * @queue_node: List node for placing this node in the @queue list of 214 * &struct atmel_mci. 215 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 216 * @flags: Random state bits associated with the slot. 217 * @detect_pin: GPIO pin used for card detection, or negative if not 218 * available. 219 * @wp_pin: GPIO pin used for card write protect sending, or negative 220 * if not available. 221 * @detect_is_active_high: The state of the detect pin when it is active. 222 * @detect_timer: Timer used for debouncing @detect_pin interrupts. 223 */ 224struct atmel_mci_slot { 225 struct mmc_host *mmc; 226 struct atmel_mci *host; 227 228 u32 sdc_reg; 229 u32 sdio_irq; 230 231 struct mmc_request *mrq; 232 struct list_head queue_node; 233 234 unsigned int clock; 235 unsigned long flags; 236#define ATMCI_CARD_PRESENT 0 237#define ATMCI_CARD_NEED_INIT 1 238#define ATMCI_SHUTDOWN 2 239#define ATMCI_SUSPENDED 3 240 241 int detect_pin; 242 int wp_pin; 243 bool detect_is_active_high; 244 245 struct timer_list detect_timer; 246}; 247 248#define atmci_test_and_clear_pending(host, event) \ 249 test_and_clear_bit(event, &host->pending_events) 250#define atmci_set_completed(host, event) \ 251 set_bit(event, &host->completed_events) 252#define atmci_set_pending(host, event) \ 253 set_bit(event, &host->pending_events) 254 255/* 256 * The debugfs stuff below is mostly optimized away when 257 * CONFIG_DEBUG_FS is not set. 258 */ 259static int atmci_req_show(struct seq_file *s, void *v) 260{ 261 struct atmel_mci_slot *slot = s->private; 262 struct mmc_request *mrq; 263 struct mmc_command *cmd; 264 struct mmc_command *stop; 265 struct mmc_data *data; 266 267 /* Make sure we get a consistent snapshot */ 268 spin_lock_bh(&slot->host->lock); 269 mrq = slot->mrq; 270 271 if (mrq) { 272 cmd = mrq->cmd; 273 data = mrq->data; 274 stop = mrq->stop; 275 276 if (cmd) 277 seq_printf(s, 278 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 279 cmd->opcode, cmd->arg, cmd->flags, 280 cmd->resp[0], cmd->resp[1], cmd->resp[2], 281 cmd->resp[3], cmd->error); 282 if (data) 283 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 284 data->bytes_xfered, data->blocks, 285 data->blksz, data->flags, data->error); 286 if (stop) 287 seq_printf(s, 288 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 289 stop->opcode, stop->arg, stop->flags, 290 stop->resp[0], stop->resp[1], stop->resp[2], 291 stop->resp[3], stop->error); 292 } 293 294 spin_unlock_bh(&slot->host->lock); 295 296 return 0; 297} 298 299static int atmci_req_open(struct inode *inode, struct file *file) 300{ 301 return single_open(file, atmci_req_show, inode->i_private); 302} 303 304static const struct file_operations atmci_req_fops = { 305 .owner = THIS_MODULE, 306 .open = atmci_req_open, 307 .read = seq_read, 308 .llseek = seq_lseek, 309 .release = single_release, 310}; 311 312static void atmci_show_status_reg(struct seq_file *s, 313 const char *regname, u32 value) 314{ 315 static const char *sr_bit[] = { 316 [0] = "CMDRDY", 317 [1] = "RXRDY", 318 [2] = "TXRDY", 319 [3] = "BLKE", 320 [4] = "DTIP", 321 [5] = "NOTBUSY", 322 [6] = "ENDRX", 323 [7] = "ENDTX", 324 [8] = "SDIOIRQA", 325 [9] = "SDIOIRQB", 326 [12] = "SDIOWAIT", 327 [14] = "RXBUFF", 328 [15] = "TXBUFE", 329 [16] = "RINDE", 330 [17] = "RDIRE", 331 [18] = "RCRCE", 332 [19] = "RENDE", 333 [20] = "RTOE", 334 [21] = "DCRCE", 335 [22] = "DTOE", 336 [23] = "CSTOE", 337 [24] = "BLKOVRE", 338 [25] = "DMADONE", 339 [26] = "FIFOEMPTY", 340 [27] = "XFRDONE", 341 [30] = "OVRE", 342 [31] = "UNRE", 343 }; 344 unsigned int i; 345 346 seq_printf(s, "%s:\t0x%08x", regname, value); 347 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) { 348 if (value & (1 << i)) { 349 if (sr_bit[i]) 350 seq_printf(s, " %s", sr_bit[i]); 351 else 352 seq_puts(s, " UNKNOWN"); 353 } 354 } 355 seq_putc(s, '\n'); 356} 357 358static int atmci_regs_show(struct seq_file *s, void *v) 359{ 360 struct atmel_mci *host = s->private; 361 u32 *buf; 362 363 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL); 364 if (!buf) 365 return -ENOMEM; 366 367 /* 368 * Grab a more or less consistent snapshot. Note that we're 369 * not disabling interrupts, so IMR and SR may not be 370 * consistent. 371 */ 372 spin_lock_bh(&host->lock); 373 clk_enable(host->mck); 374 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE); 375 clk_disable(host->mck); 376 spin_unlock_bh(&host->lock); 377 378 seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n", 379 buf[ATMCI_MR / 4], 380 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "", 381 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "", 382 buf[ATMCI_MR / 4] & 0xff); 383 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]); 384 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]); 385 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]); 386 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n", 387 buf[ATMCI_BLKR / 4], 388 buf[ATMCI_BLKR / 4] & 0xffff, 389 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff); 390 if (host->caps.has_cstor_reg) 391 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]); 392 393 /* Don't read RSPR and RDR; it will consume the data there */ 394 395 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]); 396 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]); 397 398 if (host->caps.has_dma) { 399 u32 val; 400 401 val = buf[ATMCI_DMA / 4]; 402 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n", 403 val, val & 3, 404 ((val >> 4) & 3) ? 405 1 << (((val >> 4) & 3) + 1) : 1, 406 val & ATMCI_DMAEN ? " DMAEN" : ""); 407 } 408 if (host->caps.has_cfg_reg) { 409 u32 val; 410 411 val = buf[ATMCI_CFG / 4]; 412 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n", 413 val, 414 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "", 415 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "", 416 val & ATMCI_CFG_HSMODE ? " HSMODE" : "", 417 val & ATMCI_CFG_LSYNC ? " LSYNC" : ""); 418 } 419 420 kfree(buf); 421 422 return 0; 423} 424 425static int atmci_regs_open(struct inode *inode, struct file *file) 426{ 427 return single_open(file, atmci_regs_show, inode->i_private); 428} 429 430static const struct file_operations atmci_regs_fops = { 431 .owner = THIS_MODULE, 432 .open = atmci_regs_open, 433 .read = seq_read, 434 .llseek = seq_lseek, 435 .release = single_release, 436}; 437 438static void atmci_init_debugfs(struct atmel_mci_slot *slot) 439{ 440 struct mmc_host *mmc = slot->mmc; 441 struct atmel_mci *host = slot->host; 442 struct dentry *root; 443 struct dentry *node; 444 445 root = mmc->debugfs_root; 446 if (!root) 447 return; 448 449 node = debugfs_create_file("regs", S_IRUSR, root, host, 450 &atmci_regs_fops); 451 if (IS_ERR(node)) 452 return; 453 if (!node) 454 goto err; 455 456 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops); 457 if (!node) 458 goto err; 459 460 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 461 if (!node) 462 goto err; 463 464 node = debugfs_create_x32("pending_events", S_IRUSR, root, 465 (u32 *)&host->pending_events); 466 if (!node) 467 goto err; 468 469 node = debugfs_create_x32("completed_events", S_IRUSR, root, 470 (u32 *)&host->completed_events); 471 if (!node) 472 goto err; 473 474 return; 475 476err: 477 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 478} 479 480static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host, 481 unsigned int ns) 482{ 483 return (ns * (host->bus_hz / 1000000) + 999) / 1000; 484} 485 486static void atmci_set_timeout(struct atmel_mci *host, 487 struct atmel_mci_slot *slot, struct mmc_data *data) 488{ 489 static unsigned dtomul_to_shift[] = { 490 0, 4, 7, 8, 10, 12, 16, 20 491 }; 492 unsigned timeout; 493 unsigned dtocyc; 494 unsigned dtomul; 495 496 timeout = atmci_ns_to_clocks(host, data->timeout_ns) 497 + data->timeout_clks; 498 499 for (dtomul = 0; dtomul < 8; dtomul++) { 500 unsigned shift = dtomul_to_shift[dtomul]; 501 dtocyc = (timeout + (1 << shift) - 1) >> shift; 502 if (dtocyc < 15) 503 break; 504 } 505 506 if (dtomul >= 8) { 507 dtomul = 7; 508 dtocyc = 15; 509 } 510 511 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n", 512 dtocyc << dtomul_to_shift[dtomul]); 513 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc))); 514} 515 516/* 517 * Return mask with command flags to be enabled for this command. 518 */ 519static u32 atmci_prepare_command(struct mmc_host *mmc, 520 struct mmc_command *cmd) 521{ 522 struct mmc_data *data; 523 u32 cmdr; 524 525 cmd->error = -EINPROGRESS; 526 527 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode); 528 529 if (cmd->flags & MMC_RSP_PRESENT) { 530 if (cmd->flags & MMC_RSP_136) 531 cmdr |= ATMCI_CMDR_RSPTYP_136BIT; 532 else 533 cmdr |= ATMCI_CMDR_RSPTYP_48BIT; 534 } 535 536 /* 537 * This should really be MAXLAT_5 for CMD2 and ACMD41, but 538 * it's too difficult to determine whether this is an ACMD or 539 * not. Better make it 64. 540 */ 541 cmdr |= ATMCI_CMDR_MAXLAT_64CYC; 542 543 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN) 544 cmdr |= ATMCI_CMDR_OPDCMD; 545 546 data = cmd->data; 547 if (data) { 548 cmdr |= ATMCI_CMDR_START_XFER; 549 550 if (cmd->opcode == SD_IO_RW_EXTENDED) { 551 cmdr |= ATMCI_CMDR_SDIO_BLOCK; 552 } else { 553 if (data->flags & MMC_DATA_STREAM) 554 cmdr |= ATMCI_CMDR_STREAM; 555 else if (data->blocks > 1) 556 cmdr |= ATMCI_CMDR_MULTI_BLOCK; 557 else 558 cmdr |= ATMCI_CMDR_BLOCK; 559 } 560 561 if (data->flags & MMC_DATA_READ) 562 cmdr |= ATMCI_CMDR_TRDIR_READ; 563 } 564 565 return cmdr; 566} 567 568static void atmci_send_command(struct atmel_mci *host, 569 struct mmc_command *cmd, u32 cmd_flags) 570{ 571 WARN_ON(host->cmd); 572 host->cmd = cmd; 573 574 dev_vdbg(&host->pdev->dev, 575 "start command: ARGR=0x%08x CMDR=0x%08x\n", 576 cmd->arg, cmd_flags); 577 578 atmci_writel(host, ATMCI_ARGR, cmd->arg); 579 atmci_writel(host, ATMCI_CMDR, cmd_flags); 580} 581 582static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data) 583{ 584 atmci_send_command(host, data->stop, host->stop_cmdr); 585 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); 586} 587 588/* 589 * Configure given PDC buffer taking care of alignement issues. 590 * Update host->data_size and host->sg. 591 */ 592static void atmci_pdc_set_single_buf(struct atmel_mci *host, 593 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb) 594{ 595 u32 pointer_reg, counter_reg; 596 597 if (dir == XFER_RECEIVE) { 598 pointer_reg = ATMEL_PDC_RPR; 599 counter_reg = ATMEL_PDC_RCR; 600 } else { 601 pointer_reg = ATMEL_PDC_TPR; 602 counter_reg = ATMEL_PDC_TCR; 603 } 604 605 if (buf_nb == PDC_SECOND_BUF) { 606 pointer_reg += ATMEL_PDC_SCND_BUF_OFF; 607 counter_reg += ATMEL_PDC_SCND_BUF_OFF; 608 } 609 610 atmci_writel(host, pointer_reg, sg_dma_address(host->sg)); 611 if (host->data_size <= sg_dma_len(host->sg)) { 612 if (host->data_size & 0x3) { 613 /* If size is different from modulo 4, transfer bytes */ 614 atmci_writel(host, counter_reg, host->data_size); 615 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE); 616 } else { 617 /* Else transfer 32-bits words */ 618 atmci_writel(host, counter_reg, host->data_size / 4); 619 } 620 host->data_size = 0; 621 } else { 622 /* We assume the size of a page is 32-bits aligned */ 623 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4); 624 host->data_size -= sg_dma_len(host->sg); 625 if (host->data_size) 626 host->sg = sg_next(host->sg); 627 } 628} 629 630/* 631 * Configure PDC buffer according to the data size ie configuring one or two 632 * buffers. Don't use this function if you want to configure only the second 633 * buffer. In this case, use atmci_pdc_set_single_buf. 634 */ 635static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir) 636{ 637 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF); 638 if (host->data_size) 639 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF); 640} 641 642/* 643 * Unmap sg lists, called when transfer is finished. 644 */ 645static void atmci_pdc_cleanup(struct atmel_mci *host) 646{ 647 struct mmc_data *data = host->data; 648 649 if (data) 650 dma_unmap_sg(&host->pdev->dev, 651 data->sg, data->sg_len, 652 ((data->flags & MMC_DATA_WRITE) 653 ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); 654} 655 656/* 657 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after 658 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY 659 * interrupt needed for both transfer directions. 660 */ 661static void atmci_pdc_complete(struct atmel_mci *host) 662{ 663 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 664 atmci_pdc_cleanup(host); 665 666 /* 667 * If the card was removed, data will be NULL. No point trying 668 * to send the stop command or waiting for NBUSY in this case. 669 */ 670 if (host->data) { 671 atmci_set_pending(host, EVENT_XFER_COMPLETE); 672 tasklet_schedule(&host->tasklet); 673 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 674 } 675} 676 677static void atmci_dma_cleanup(struct atmel_mci *host) 678{ 679 struct mmc_data *data = host->data; 680 681 if (data) 682 dma_unmap_sg(host->dma.chan->device->dev, 683 data->sg, data->sg_len, 684 ((data->flags & MMC_DATA_WRITE) 685 ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); 686} 687 688/* 689 * This function is called by the DMA driver from tasklet context. 690 */ 691static void atmci_dma_complete(void *arg) 692{ 693 struct atmel_mci *host = arg; 694 struct mmc_data *data = host->data; 695 696 dev_vdbg(&host->pdev->dev, "DMA complete\n"); 697 698 if (host->caps.has_dma) 699 /* Disable DMA hardware handshaking on MCI */ 700 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN); 701 702 atmci_dma_cleanup(host); 703 704 /* 705 * If the card was removed, data will be NULL. No point trying 706 * to send the stop command or waiting for NBUSY in this case. 707 */ 708 if (data) { 709 atmci_set_pending(host, EVENT_XFER_COMPLETE); 710 tasklet_schedule(&host->tasklet); 711 712 /* 713 * Regardless of what the documentation says, we have 714 * to wait for NOTBUSY even after block read 715 * operations. 716 * 717 * When the DMA transfer is complete, the controller 718 * may still be reading the CRC from the card, i.e. 719 * the data transfer is still in progress and we 720 * haven't seen all the potential error bits yet. 721 * 722 * The interrupt handler will schedule a different 723 * tasklet to finish things up when the data transfer 724 * is completely done. 725 * 726 * We may not complete the mmc request here anyway 727 * because the mmc layer may call back and cause us to 728 * violate the "don't submit new operations from the 729 * completion callback" rule of the dma engine 730 * framework. 731 */ 732 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 733 } 734} 735 736/* 737 * Returns a mask of interrupt flags to be enabled after the whole 738 * request has been prepared. 739 */ 740static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data) 741{ 742 u32 iflags; 743 744 data->error = -EINPROGRESS; 745 746 host->sg = data->sg; 747 host->data = data; 748 host->data_chan = NULL; 749 750 iflags = ATMCI_DATA_ERROR_FLAGS; 751 752 /* 753 * Errata: MMC data write operation with less than 12 754 * bytes is impossible. 755 * 756 * Errata: MCI Transmit Data Register (TDR) FIFO 757 * corruption when length is not multiple of 4. 758 */ 759 if (data->blocks * data->blksz < 12 760 || (data->blocks * data->blksz) & 3) 761 host->need_reset = true; 762 763 host->pio_offset = 0; 764 if (data->flags & MMC_DATA_READ) 765 iflags |= ATMCI_RXRDY; 766 else 767 iflags |= ATMCI_TXRDY; 768 769 return iflags; 770} 771 772/* 773 * Set interrupt flags and set block length into the MCI mode register even 774 * if this value is also accessible in the MCI block register. It seems to be 775 * necessary before the High Speed MCI version. It also map sg and configure 776 * PDC registers. 777 */ 778static u32 779atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data) 780{ 781 u32 iflags, tmp; 782 unsigned int sg_len; 783 enum dma_data_direction dir; 784 785 data->error = -EINPROGRESS; 786 787 host->data = data; 788 host->sg = data->sg; 789 iflags = ATMCI_DATA_ERROR_FLAGS; 790 791 /* Enable pdc mode */ 792 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE); 793 794 if (data->flags & MMC_DATA_READ) { 795 dir = DMA_FROM_DEVICE; 796 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF; 797 } else { 798 dir = DMA_TO_DEVICE; 799 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE; 800 } 801 802 /* Set BLKLEN */ 803 tmp = atmci_readl(host, ATMCI_MR); 804 tmp &= 0x0000ffff; 805 tmp |= ATMCI_BLKLEN(data->blksz); 806 atmci_writel(host, ATMCI_MR, tmp); 807 808 /* Configure PDC */ 809 host->data_size = data->blocks * data->blksz; 810 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir); 811 if (host->data_size) 812 atmci_pdc_set_both_buf(host, 813 ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT)); 814 815 return iflags; 816} 817 818static u32 819atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data) 820{ 821 struct dma_chan *chan; 822 struct dma_async_tx_descriptor *desc; 823 struct scatterlist *sg; 824 unsigned int i; 825 enum dma_data_direction direction; 826 unsigned int sglen; 827 u32 iflags; 828 829 data->error = -EINPROGRESS; 830 831 WARN_ON(host->data); 832 host->sg = NULL; 833 host->data = data; 834 835 iflags = ATMCI_DATA_ERROR_FLAGS; 836 837 /* 838 * We don't do DMA on "complex" transfers, i.e. with 839 * non-word-aligned buffers or lengths. Also, we don't bother 840 * with all the DMA setup overhead for short transfers. 841 */ 842 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD) 843 return atmci_prepare_data(host, data); 844 if (data->blksz & 3) 845 return atmci_prepare_data(host, data); 846 847 for_each_sg(data->sg, sg, data->sg_len, i) { 848 if (sg->offset & 3 || sg->length & 3) 849 return atmci_prepare_data(host, data); 850 } 851 852 /* If we don't have a channel, we can't do DMA */ 853 chan = host->dma.chan; 854 if (chan) 855 host->data_chan = chan; 856 857 if (!chan) 858 return -ENODEV; 859 860 if (host->caps.has_dma) 861 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(3) | ATMCI_DMAEN); 862 863 if (data->flags & MMC_DATA_READ) 864 direction = DMA_FROM_DEVICE; 865 else 866 direction = DMA_TO_DEVICE; 867 868 sglen = dma_map_sg(chan->device->dev, data->sg, 869 data->sg_len, direction); 870 871 desc = chan->device->device_prep_slave_sg(chan, 872 data->sg, sglen, direction, 873 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 874 if (!desc) 875 goto unmap_exit; 876 877 host->dma.data_desc = desc; 878 desc->callback = atmci_dma_complete; 879 desc->callback_param = host; 880 881 return iflags; 882unmap_exit: 883 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction); 884 return -ENOMEM; 885} 886 887static void 888atmci_submit_data(struct atmel_mci *host, struct mmc_data *data) 889{ 890 return; 891} 892 893/* 894 * Start PDC according to transfer direction. 895 */ 896static void 897atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data) 898{ 899 if (data->flags & MMC_DATA_READ) 900 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 901 else 902 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 903} 904 905static void 906atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data) 907{ 908 struct dma_chan *chan = host->data_chan; 909 struct dma_async_tx_descriptor *desc = host->dma.data_desc; 910 911 if (chan) { 912 dmaengine_submit(desc); 913 dma_async_issue_pending(chan); 914 } 915} 916 917static void atmci_stop_transfer(struct atmel_mci *host) 918{ 919 atmci_set_pending(host, EVENT_XFER_COMPLETE); 920 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 921} 922 923/* 924 * Stop data transfer because error(s) occured. 925 */ 926static void atmci_stop_transfer_pdc(struct atmel_mci *host) 927{ 928 atmci_set_pending(host, EVENT_XFER_COMPLETE); 929 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 930} 931 932static void atmci_stop_transfer_dma(struct atmel_mci *host) 933{ 934 struct dma_chan *chan = host->data_chan; 935 936 if (chan) { 937 dmaengine_terminate_all(chan); 938 atmci_dma_cleanup(host); 939 } else { 940 /* Data transfer was stopped by the interrupt handler */ 941 atmci_set_pending(host, EVENT_XFER_COMPLETE); 942 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 943 } 944} 945 946/* 947 * Start a request: prepare data if needed, prepare the command and activate 948 * interrupts. 949 */ 950static void atmci_start_request(struct atmel_mci *host, 951 struct atmel_mci_slot *slot) 952{ 953 struct mmc_request *mrq; 954 struct mmc_command *cmd; 955 struct mmc_data *data; 956 u32 iflags; 957 u32 cmdflags; 958 959 mrq = slot->mrq; 960 host->cur_slot = slot; 961 host->mrq = mrq; 962 963 host->pending_events = 0; 964 host->completed_events = 0; 965 host->data_status = 0; 966 967 if (host->need_reset) { 968 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 969 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 970 atmci_writel(host, ATMCI_MR, host->mode_reg); 971 if (host->caps.has_cfg_reg) 972 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 973 host->need_reset = false; 974 } 975 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg); 976 977 iflags = atmci_readl(host, ATMCI_IMR); 978 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) 979 dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n", 980 iflags); 981 982 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) { 983 /* Send init sequence (74 clock cycles) */ 984 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT); 985 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY)) 986 cpu_relax(); 987 } 988 iflags = 0; 989 data = mrq->data; 990 if (data) { 991 atmci_set_timeout(host, slot, data); 992 993 /* Must set block count/size before sending command */ 994 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks) 995 | ATMCI_BLKLEN(data->blksz)); 996 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n", 997 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz)); 998 999 iflags |= host->prepare_data(host, data); 1000 } 1001 1002 iflags |= ATMCI_CMDRDY; 1003 cmd = mrq->cmd; 1004 cmdflags = atmci_prepare_command(slot->mmc, cmd); 1005 atmci_send_command(host, cmd, cmdflags); 1006 1007 if (data) 1008 host->submit_data(host, data); 1009 1010 if (mrq->stop) { 1011 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop); 1012 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER; 1013 if (!(data->flags & MMC_DATA_WRITE)) 1014 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ; 1015 if (data->flags & MMC_DATA_STREAM) 1016 host->stop_cmdr |= ATMCI_CMDR_STREAM; 1017 else 1018 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK; 1019 } 1020 1021 /* 1022 * We could have enabled interrupts earlier, but I suspect 1023 * that would open up a nice can of interesting race 1024 * conditions (e.g. command and data complete, but stop not 1025 * prepared yet.) 1026 */ 1027 atmci_writel(host, ATMCI_IER, iflags); 1028} 1029 1030static void atmci_queue_request(struct atmel_mci *host, 1031 struct atmel_mci_slot *slot, struct mmc_request *mrq) 1032{ 1033 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1034 host->state); 1035 1036 spin_lock_bh(&host->lock); 1037 slot->mrq = mrq; 1038 if (host->state == STATE_IDLE) { 1039 host->state = STATE_SENDING_CMD; 1040 atmci_start_request(host, slot); 1041 } else { 1042 list_add_tail(&slot->queue_node, &host->queue); 1043 } 1044 spin_unlock_bh(&host->lock); 1045} 1046 1047static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1048{ 1049 struct atmel_mci_slot *slot = mmc_priv(mmc); 1050 struct atmel_mci *host = slot->host; 1051 struct mmc_data *data; 1052 1053 WARN_ON(slot->mrq); 1054 1055 /* 1056 * We may "know" the card is gone even though there's still an 1057 * electrical connection. If so, we really need to communicate 1058 * this to the MMC core since there won't be any more 1059 * interrupts as the card is completely removed. Otherwise, 1060 * the MMC core might believe the card is still there even 1061 * though the card was just removed very slowly. 1062 */ 1063 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) { 1064 mrq->cmd->error = -ENOMEDIUM; 1065 mmc_request_done(mmc, mrq); 1066 return; 1067 } 1068 1069 /* We don't support multiple blocks of weird lengths. */ 1070 data = mrq->data; 1071 if (data && data->blocks > 1 && data->blksz & 3) { 1072 mrq->cmd->error = -EINVAL; 1073 mmc_request_done(mmc, mrq); 1074 } 1075 1076 atmci_queue_request(host, slot, mrq); 1077} 1078 1079static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1080{ 1081 struct atmel_mci_slot *slot = mmc_priv(mmc); 1082 struct atmel_mci *host = slot->host; 1083 unsigned int i; 1084 1085 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK; 1086 switch (ios->bus_width) { 1087 case MMC_BUS_WIDTH_1: 1088 slot->sdc_reg |= ATMCI_SDCBUS_1BIT; 1089 break; 1090 case MMC_BUS_WIDTH_4: 1091 slot->sdc_reg |= ATMCI_SDCBUS_4BIT; 1092 break; 1093 } 1094 1095 if (ios->clock) { 1096 unsigned int clock_min = ~0U; 1097 u32 clkdiv; 1098 1099 spin_lock_bh(&host->lock); 1100 if (!host->mode_reg) { 1101 clk_enable(host->mck); 1102 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 1103 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 1104 if (host->caps.has_cfg_reg) 1105 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1106 } 1107 1108 /* 1109 * Use mirror of ios->clock to prevent race with mmc 1110 * core ios update when finding the minimum. 1111 */ 1112 slot->clock = ios->clock; 1113 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 1114 if (host->slot[i] && host->slot[i]->clock 1115 && host->slot[i]->clock < clock_min) 1116 clock_min = host->slot[i]->clock; 1117 } 1118 1119 /* Calculate clock divider */ 1120 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1; 1121 if (clkdiv > 255) { 1122 dev_warn(&mmc->class_dev, 1123 "clock %u too slow; using %lu\n", 1124 clock_min, host->bus_hz / (2 * 256)); 1125 clkdiv = 255; 1126 } 1127 1128 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv); 1129 1130 /* 1131 * WRPROOF and RDPROOF prevent overruns/underruns by 1132 * stopping the clock when the FIFO is full/empty. 1133 * This state is not expected to last for long. 1134 */ 1135 if (host->caps.has_rwproof) 1136 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF); 1137 1138 if (host->caps.has_cfg_reg) { 1139 /* setup High Speed mode in relation with card capacity */ 1140 if (ios->timing == MMC_TIMING_SD_HS) 1141 host->cfg_reg |= ATMCI_CFG_HSMODE; 1142 else 1143 host->cfg_reg &= ~ATMCI_CFG_HSMODE; 1144 } 1145 1146 if (list_empty(&host->queue)) { 1147 atmci_writel(host, ATMCI_MR, host->mode_reg); 1148 if (host->caps.has_cfg_reg) 1149 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1150 } else { 1151 host->need_clock_update = true; 1152 } 1153 1154 spin_unlock_bh(&host->lock); 1155 } else { 1156 bool any_slot_active = false; 1157 1158 spin_lock_bh(&host->lock); 1159 slot->clock = 0; 1160 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 1161 if (host->slot[i] && host->slot[i]->clock) { 1162 any_slot_active = true; 1163 break; 1164 } 1165 } 1166 if (!any_slot_active) { 1167 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); 1168 if (host->mode_reg) { 1169 atmci_readl(host, ATMCI_MR); 1170 clk_disable(host->mck); 1171 } 1172 host->mode_reg = 0; 1173 } 1174 spin_unlock_bh(&host->lock); 1175 } 1176 1177 switch (ios->power_mode) { 1178 case MMC_POWER_UP: 1179 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags); 1180 break; 1181 default: 1182 /* 1183 * TODO: None of the currently available AVR32-based 1184 * boards allow MMC power to be turned off. Implement 1185 * power control when this can be tested properly. 1186 * 1187 * We also need to hook this into the clock management 1188 * somehow so that newly inserted cards aren't 1189 * subjected to a fast clock before we have a chance 1190 * to figure out what the maximum rate is. Currently, 1191 * there's no way to avoid this, and there never will 1192 * be for boards that don't support power control. 1193 */ 1194 break; 1195 } 1196} 1197 1198static int atmci_get_ro(struct mmc_host *mmc) 1199{ 1200 int read_only = -ENOSYS; 1201 struct atmel_mci_slot *slot = mmc_priv(mmc); 1202 1203 if (gpio_is_valid(slot->wp_pin)) { 1204 read_only = gpio_get_value(slot->wp_pin); 1205 dev_dbg(&mmc->class_dev, "card is %s\n", 1206 read_only ? "read-only" : "read-write"); 1207 } 1208 1209 return read_only; 1210} 1211 1212static int atmci_get_cd(struct mmc_host *mmc) 1213{ 1214 int present = -ENOSYS; 1215 struct atmel_mci_slot *slot = mmc_priv(mmc); 1216 1217 if (gpio_is_valid(slot->detect_pin)) { 1218 present = !(gpio_get_value(slot->detect_pin) ^ 1219 slot->detect_is_active_high); 1220 dev_dbg(&mmc->class_dev, "card is %spresent\n", 1221 present ? "" : "not "); 1222 } 1223 1224 return present; 1225} 1226 1227static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1228{ 1229 struct atmel_mci_slot *slot = mmc_priv(mmc); 1230 struct atmel_mci *host = slot->host; 1231 1232 if (enable) 1233 atmci_writel(host, ATMCI_IER, slot->sdio_irq); 1234 else 1235 atmci_writel(host, ATMCI_IDR, slot->sdio_irq); 1236} 1237 1238static const struct mmc_host_ops atmci_ops = { 1239 .request = atmci_request, 1240 .set_ios = atmci_set_ios, 1241 .get_ro = atmci_get_ro, 1242 .get_cd = atmci_get_cd, 1243 .enable_sdio_irq = atmci_enable_sdio_irq, 1244}; 1245 1246/* Called with host->lock held */ 1247static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq) 1248 __releases(&host->lock) 1249 __acquires(&host->lock) 1250{ 1251 struct atmel_mci_slot *slot = NULL; 1252 struct mmc_host *prev_mmc = host->cur_slot->mmc; 1253 1254 WARN_ON(host->cmd || host->data); 1255 1256 /* 1257 * Update the MMC clock rate if necessary. This may be 1258 * necessary if set_ios() is called when a different slot is 1259 * busy transferring data. 1260 */ 1261 if (host->need_clock_update) { 1262 atmci_writel(host, ATMCI_MR, host->mode_reg); 1263 if (host->caps.has_cfg_reg) 1264 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1265 } 1266 1267 host->cur_slot->mrq = NULL; 1268 host->mrq = NULL; 1269 if (!list_empty(&host->queue)) { 1270 slot = list_entry(host->queue.next, 1271 struct atmel_mci_slot, queue_node); 1272 list_del(&slot->queue_node); 1273 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n", 1274 mmc_hostname(slot->mmc)); 1275 host->state = STATE_SENDING_CMD; 1276 atmci_start_request(host, slot); 1277 } else { 1278 dev_vdbg(&host->pdev->dev, "list empty\n"); 1279 host->state = STATE_IDLE; 1280 } 1281 1282 spin_unlock(&host->lock); 1283 mmc_request_done(prev_mmc, mrq); 1284 spin_lock(&host->lock); 1285} 1286 1287static void atmci_command_complete(struct atmel_mci *host, 1288 struct mmc_command *cmd) 1289{ 1290 u32 status = host->cmd_status; 1291 1292 /* Read the response from the card (up to 16 bytes) */ 1293 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR); 1294 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR); 1295 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR); 1296 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR); 1297 1298 if (status & ATMCI_RTOE) 1299 cmd->error = -ETIMEDOUT; 1300 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE)) 1301 cmd->error = -EILSEQ; 1302 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE)) 1303 cmd->error = -EIO; 1304 else 1305 cmd->error = 0; 1306 1307 if (cmd->error) { 1308 dev_dbg(&host->pdev->dev, 1309 "command error: status=0x%08x\n", status); 1310 1311 if (cmd->data) { 1312 host->stop_transfer(host); 1313 host->data = NULL; 1314 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY 1315 | ATMCI_TXRDY | ATMCI_RXRDY 1316 | ATMCI_DATA_ERROR_FLAGS); 1317 } 1318 } 1319} 1320 1321static void atmci_detect_change(unsigned long data) 1322{ 1323 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data; 1324 bool present; 1325 bool present_old; 1326 1327 /* 1328 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before 1329 * freeing the interrupt. We must not re-enable the interrupt 1330 * if it has been freed, and if we're shutting down, it 1331 * doesn't really matter whether the card is present or not. 1332 */ 1333 smp_rmb(); 1334 if (test_bit(ATMCI_SHUTDOWN, &slot->flags)) 1335 return; 1336 1337 enable_irq(gpio_to_irq(slot->detect_pin)); 1338 present = !(gpio_get_value(slot->detect_pin) ^ 1339 slot->detect_is_active_high); 1340 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags); 1341 1342 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n", 1343 present, present_old); 1344 1345 if (present != present_old) { 1346 struct atmel_mci *host = slot->host; 1347 struct mmc_request *mrq; 1348 1349 dev_dbg(&slot->mmc->class_dev, "card %s\n", 1350 present ? "inserted" : "removed"); 1351 1352 spin_lock(&host->lock); 1353 1354 if (!present) 1355 clear_bit(ATMCI_CARD_PRESENT, &slot->flags); 1356 else 1357 set_bit(ATMCI_CARD_PRESENT, &slot->flags); 1358 1359 /* Clean up queue if present */ 1360 mrq = slot->mrq; 1361 if (mrq) { 1362 if (mrq == host->mrq) { 1363 /* 1364 * Reset controller to terminate any ongoing 1365 * commands or data transfers. 1366 */ 1367 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 1368 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); 1369 atmci_writel(host, ATMCI_MR, host->mode_reg); 1370 if (host->caps.has_cfg_reg) 1371 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1372 1373 host->data = NULL; 1374 host->cmd = NULL; 1375 1376 switch (host->state) { 1377 case STATE_IDLE: 1378 break; 1379 case STATE_SENDING_CMD: 1380 mrq->cmd->error = -ENOMEDIUM; 1381 if (!mrq->data) 1382 break; 1383 /* fall through */ 1384 case STATE_SENDING_DATA: 1385 mrq->data->error = -ENOMEDIUM; 1386 host->stop_transfer(host); 1387 break; 1388 case STATE_DATA_BUSY: 1389 case STATE_DATA_ERROR: 1390 if (mrq->data->error == -EINPROGRESS) 1391 mrq->data->error = -ENOMEDIUM; 1392 if (!mrq->stop) 1393 break; 1394 /* fall through */ 1395 case STATE_SENDING_STOP: 1396 mrq->stop->error = -ENOMEDIUM; 1397 break; 1398 } 1399 1400 atmci_request_end(host, mrq); 1401 } else { 1402 list_del(&slot->queue_node); 1403 mrq->cmd->error = -ENOMEDIUM; 1404 if (mrq->data) 1405 mrq->data->error = -ENOMEDIUM; 1406 if (mrq->stop) 1407 mrq->stop->error = -ENOMEDIUM; 1408 1409 spin_unlock(&host->lock); 1410 mmc_request_done(slot->mmc, mrq); 1411 spin_lock(&host->lock); 1412 } 1413 } 1414 spin_unlock(&host->lock); 1415 1416 mmc_detect_change(slot->mmc, 0); 1417 } 1418} 1419 1420static void atmci_tasklet_func(unsigned long priv) 1421{ 1422 struct atmel_mci *host = (struct atmel_mci *)priv; 1423 struct mmc_request *mrq = host->mrq; 1424 struct mmc_data *data = host->data; 1425 struct mmc_command *cmd = host->cmd; 1426 enum atmel_mci_state state = host->state; 1427 enum atmel_mci_state prev_state; 1428 u32 status; 1429 1430 spin_lock(&host->lock); 1431 1432 state = host->state; 1433 1434 dev_vdbg(&host->pdev->dev, 1435 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n", 1436 state, host->pending_events, host->completed_events, 1437 atmci_readl(host, ATMCI_IMR)); 1438 1439 do { 1440 prev_state = state; 1441 1442 switch (state) { 1443 case STATE_IDLE: 1444 break; 1445 1446 case STATE_SENDING_CMD: 1447 if (!atmci_test_and_clear_pending(host, 1448 EVENT_CMD_COMPLETE)) 1449 break; 1450 1451 host->cmd = NULL; 1452 atmci_set_completed(host, EVENT_CMD_COMPLETE); 1453 atmci_command_complete(host, mrq->cmd); 1454 if (!mrq->data || cmd->error) { 1455 atmci_request_end(host, host->mrq); 1456 goto unlock; 1457 } 1458 1459 prev_state = state = STATE_SENDING_DATA; 1460 /* fall through */ 1461 1462 case STATE_SENDING_DATA: 1463 if (atmci_test_and_clear_pending(host, 1464 EVENT_DATA_ERROR)) { 1465 host->stop_transfer(host); 1466 if (data->stop) 1467 atmci_send_stop_cmd(host, data); 1468 state = STATE_DATA_ERROR; 1469 break; 1470 } 1471 1472 if (!atmci_test_and_clear_pending(host, 1473 EVENT_XFER_COMPLETE)) 1474 break; 1475 1476 atmci_set_completed(host, EVENT_XFER_COMPLETE); 1477 prev_state = state = STATE_DATA_BUSY; 1478 /* fall through */ 1479 1480 case STATE_DATA_BUSY: 1481 if (!atmci_test_and_clear_pending(host, 1482 EVENT_DATA_COMPLETE)) 1483 break; 1484 1485 host->data = NULL; 1486 atmci_set_completed(host, EVENT_DATA_COMPLETE); 1487 status = host->data_status; 1488 if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) { 1489 if (status & ATMCI_DTOE) { 1490 dev_dbg(&host->pdev->dev, 1491 "data timeout error\n"); 1492 data->error = -ETIMEDOUT; 1493 } else if (status & ATMCI_DCRCE) { 1494 dev_dbg(&host->pdev->dev, 1495 "data CRC error\n"); 1496 data->error = -EILSEQ; 1497 } else { 1498 dev_dbg(&host->pdev->dev, 1499 "data FIFO error (status=%08x)\n", 1500 status); 1501 data->error = -EIO; 1502 } 1503 } else { 1504 data->bytes_xfered = data->blocks * data->blksz; 1505 data->error = 0; 1506 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS); 1507 } 1508 1509 if (!data->stop) { 1510 atmci_request_end(host, host->mrq); 1511 goto unlock; 1512 } 1513 1514 prev_state = state = STATE_SENDING_STOP; 1515 if (!data->error) 1516 atmci_send_stop_cmd(host, data); 1517 /* fall through */ 1518 1519 case STATE_SENDING_STOP: 1520 if (!atmci_test_and_clear_pending(host, 1521 EVENT_CMD_COMPLETE)) 1522 break; 1523 1524 host->cmd = NULL; 1525 atmci_command_complete(host, mrq->stop); 1526 atmci_request_end(host, host->mrq); 1527 goto unlock; 1528 1529 case STATE_DATA_ERROR: 1530 if (!atmci_test_and_clear_pending(host, 1531 EVENT_XFER_COMPLETE)) 1532 break; 1533 1534 state = STATE_DATA_BUSY; 1535 break; 1536 } 1537 } while (state != prev_state); 1538 1539 host->state = state; 1540 1541unlock: 1542 spin_unlock(&host->lock); 1543} 1544 1545static void atmci_read_data_pio(struct atmel_mci *host) 1546{ 1547 struct scatterlist *sg = host->sg; 1548 void *buf = sg_virt(sg); 1549 unsigned int offset = host->pio_offset; 1550 struct mmc_data *data = host->data; 1551 u32 value; 1552 u32 status; 1553 unsigned int nbytes = 0; 1554 1555 do { 1556 value = atmci_readl(host, ATMCI_RDR); 1557 if (likely(offset + 4 <= sg->length)) { 1558 put_unaligned(value, (u32 *)(buf + offset)); 1559 1560 offset += 4; 1561 nbytes += 4; 1562 1563 if (offset == sg->length) { 1564 flush_dcache_page(sg_page(sg)); 1565 host->sg = sg = sg_next(sg); 1566 if (!sg) 1567 goto done; 1568 1569 offset = 0; 1570 buf = sg_virt(sg); 1571 } 1572 } else { 1573 unsigned int remaining = sg->length - offset; 1574 memcpy(buf + offset, &value, remaining); 1575 nbytes += remaining; 1576 1577 flush_dcache_page(sg_page(sg)); 1578 host->sg = sg = sg_next(sg); 1579 if (!sg) 1580 goto done; 1581 1582 offset = 4 - remaining; 1583 buf = sg_virt(sg); 1584 memcpy(buf, (u8 *)&value + remaining, offset); 1585 nbytes += offset; 1586 } 1587 1588 status = atmci_readl(host, ATMCI_SR); 1589 if (status & ATMCI_DATA_ERROR_FLAGS) { 1590 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY 1591 | ATMCI_DATA_ERROR_FLAGS)); 1592 host->data_status = status; 1593 data->bytes_xfered += nbytes; 1594 smp_wmb(); 1595 atmci_set_pending(host, EVENT_DATA_ERROR); 1596 tasklet_schedule(&host->tasklet); 1597 return; 1598 } 1599 } while (status & ATMCI_RXRDY); 1600 1601 host->pio_offset = offset; 1602 data->bytes_xfered += nbytes; 1603 1604 return; 1605 1606done: 1607 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY); 1608 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1609 data->bytes_xfered += nbytes; 1610 smp_wmb(); 1611 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1612} 1613 1614static void atmci_write_data_pio(struct atmel_mci *host) 1615{ 1616 struct scatterlist *sg = host->sg; 1617 void *buf = sg_virt(sg); 1618 unsigned int offset = host->pio_offset; 1619 struct mmc_data *data = host->data; 1620 u32 value; 1621 u32 status; 1622 unsigned int nbytes = 0; 1623 1624 do { 1625 if (likely(offset + 4 <= sg->length)) { 1626 value = get_unaligned((u32 *)(buf + offset)); 1627 atmci_writel(host, ATMCI_TDR, value); 1628 1629 offset += 4; 1630 nbytes += 4; 1631 if (offset == sg->length) { 1632 host->sg = sg = sg_next(sg); 1633 if (!sg) 1634 goto done; 1635 1636 offset = 0; 1637 buf = sg_virt(sg); 1638 } 1639 } else { 1640 unsigned int remaining = sg->length - offset; 1641 1642 value = 0; 1643 memcpy(&value, buf + offset, remaining); 1644 nbytes += remaining; 1645 1646 host->sg = sg = sg_next(sg); 1647 if (!sg) { 1648 atmci_writel(host, ATMCI_TDR, value); 1649 goto done; 1650 } 1651 1652 offset = 4 - remaining; 1653 buf = sg_virt(sg); 1654 memcpy((u8 *)&value + remaining, buf, offset); 1655 atmci_writel(host, ATMCI_TDR, value); 1656 nbytes += offset; 1657 } 1658 1659 status = atmci_readl(host, ATMCI_SR); 1660 if (status & ATMCI_DATA_ERROR_FLAGS) { 1661 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY 1662 | ATMCI_DATA_ERROR_FLAGS)); 1663 host->data_status = status; 1664 data->bytes_xfered += nbytes; 1665 smp_wmb(); 1666 atmci_set_pending(host, EVENT_DATA_ERROR); 1667 tasklet_schedule(&host->tasklet); 1668 return; 1669 } 1670 } while (status & ATMCI_TXRDY); 1671 1672 host->pio_offset = offset; 1673 data->bytes_xfered += nbytes; 1674 1675 return; 1676 1677done: 1678 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY); 1679 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1680 data->bytes_xfered += nbytes; 1681 smp_wmb(); 1682 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1683} 1684 1685static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status) 1686{ 1687 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY); 1688 1689 host->cmd_status = status; 1690 smp_wmb(); 1691 atmci_set_pending(host, EVENT_CMD_COMPLETE); 1692 tasklet_schedule(&host->tasklet); 1693} 1694 1695static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status) 1696{ 1697 int i; 1698 1699 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 1700 struct atmel_mci_slot *slot = host->slot[i]; 1701 if (slot && (status & slot->sdio_irq)) { 1702 mmc_signal_sdio_irq(slot->mmc); 1703 } 1704 } 1705} 1706 1707 1708static irqreturn_t atmci_interrupt(int irq, void *dev_id) 1709{ 1710 struct atmel_mci *host = dev_id; 1711 u32 status, mask, pending; 1712 unsigned int pass_count = 0; 1713 1714 do { 1715 status = atmci_readl(host, ATMCI_SR); 1716 mask = atmci_readl(host, ATMCI_IMR); 1717 pending = status & mask; 1718 if (!pending) 1719 break; 1720 1721 if (pending & ATMCI_DATA_ERROR_FLAGS) { 1722 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS 1723 | ATMCI_RXRDY | ATMCI_TXRDY); 1724 pending &= atmci_readl(host, ATMCI_IMR); 1725 1726 host->data_status = status; 1727 smp_wmb(); 1728 atmci_set_pending(host, EVENT_DATA_ERROR); 1729 tasklet_schedule(&host->tasklet); 1730 } 1731 1732 if (pending & ATMCI_ENDTX) { 1733 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); 1734 if (host->data_size) { 1735 atmci_pdc_set_single_buf(host, 1736 XFER_TRANSMIT, PDC_SECOND_BUF); 1737 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX); 1738 } 1739 } 1740 1741 if (pending & ATMCI_TXBUFE) { 1742 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE); 1743 /* 1744 * We can receive this interruption before having configured 1745 * the second pdc buffer, so we need to reconfigure first and 1746 * second buffers again 1747 */ 1748 if (host->data_size) { 1749 atmci_pdc_set_both_buf(host, XFER_TRANSMIT); 1750 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE); 1751 } else { 1752 atmci_pdc_complete(host); 1753 } 1754 } 1755 1756 if (pending & ATMCI_ENDRX) { 1757 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); 1758 1759 if (host->data_size) { 1760 atmci_pdc_set_single_buf(host, 1761 XFER_RECEIVE, PDC_SECOND_BUF); 1762 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX); 1763 } 1764 } 1765 1766 if (pending & ATMCI_RXBUFF) { 1767 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF); 1768 /* 1769 * We can receive this interruption before having configured 1770 * the second pdc buffer, so we need to reconfigure first and 1771 * second buffers again 1772 */ 1773 if (host->data_size) { 1774 atmci_pdc_set_both_buf(host, XFER_RECEIVE); 1775 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF); 1776 } else { 1777 atmci_pdc_complete(host); 1778 } 1779 } 1780 1781 if (pending & ATMCI_NOTBUSY) { 1782 atmci_writel(host, ATMCI_IDR, 1783 ATMCI_DATA_ERROR_FLAGS | ATMCI_NOTBUSY); 1784 if (!host->data_status) 1785 host->data_status = status; 1786 smp_wmb(); 1787 atmci_set_pending(host, EVENT_DATA_COMPLETE); 1788 tasklet_schedule(&host->tasklet); 1789 } 1790 if (pending & ATMCI_RXRDY) 1791 atmci_read_data_pio(host); 1792 if (pending & ATMCI_TXRDY) 1793 atmci_write_data_pio(host); 1794 1795 if (pending & ATMCI_CMDRDY) 1796 atmci_cmd_interrupt(host, status); 1797 1798 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) 1799 atmci_sdio_interrupt(host, status); 1800 1801 } while (pass_count++ < 5); 1802 1803 return pass_count ? IRQ_HANDLED : IRQ_NONE; 1804} 1805 1806static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id) 1807{ 1808 struct atmel_mci_slot *slot = dev_id; 1809 1810 /* 1811 * Disable interrupts until the pin has stabilized and check 1812 * the state then. Use mod_timer() since we may be in the 1813 * middle of the timer routine when this interrupt triggers. 1814 */ 1815 disable_irq_nosync(irq); 1816 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20)); 1817 1818 return IRQ_HANDLED; 1819} 1820 1821static int __init atmci_init_slot(struct atmel_mci *host, 1822 struct mci_slot_pdata *slot_data, unsigned int id, 1823 u32 sdc_reg, u32 sdio_irq) 1824{ 1825 struct mmc_host *mmc; 1826 struct atmel_mci_slot *slot; 1827 1828 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev); 1829 if (!mmc) 1830 return -ENOMEM; 1831 1832 slot = mmc_priv(mmc); 1833 slot->mmc = mmc; 1834 slot->host = host; 1835 slot->detect_pin = slot_data->detect_pin; 1836 slot->wp_pin = slot_data->wp_pin; 1837 slot->detect_is_active_high = slot_data->detect_is_active_high; 1838 slot->sdc_reg = sdc_reg; 1839 slot->sdio_irq = sdio_irq; 1840 1841 mmc->ops = &atmci_ops; 1842 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512); 1843 mmc->f_max = host->bus_hz / 2; 1844 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1845 if (sdio_irq) 1846 mmc->caps |= MMC_CAP_SDIO_IRQ; 1847 if (host->caps.has_highspeed) 1848 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1849 if (slot_data->bus_width >= 4) 1850 mmc->caps |= MMC_CAP_4_BIT_DATA; 1851 1852 mmc->max_segs = 64; 1853 mmc->max_req_size = 32768 * 512; 1854 mmc->max_blk_size = 32768; 1855 mmc->max_blk_count = 512; 1856 1857 /* Assume card is present initially */ 1858 set_bit(ATMCI_CARD_PRESENT, &slot->flags); 1859 if (gpio_is_valid(slot->detect_pin)) { 1860 if (gpio_request(slot->detect_pin, "mmc_detect")) { 1861 dev_dbg(&mmc->class_dev, "no detect pin available\n"); 1862 slot->detect_pin = -EBUSY; 1863 } else if (gpio_get_value(slot->detect_pin) ^ 1864 slot->detect_is_active_high) { 1865 clear_bit(ATMCI_CARD_PRESENT, &slot->flags); 1866 } 1867 } 1868 1869 if (!gpio_is_valid(slot->detect_pin)) 1870 mmc->caps |= MMC_CAP_NEEDS_POLL; 1871 1872 if (gpio_is_valid(slot->wp_pin)) { 1873 if (gpio_request(slot->wp_pin, "mmc_wp")) { 1874 dev_dbg(&mmc->class_dev, "no WP pin available\n"); 1875 slot->wp_pin = -EBUSY; 1876 } 1877 } 1878 1879 host->slot[id] = slot; 1880 mmc_add_host(mmc); 1881 1882 if (gpio_is_valid(slot->detect_pin)) { 1883 int ret; 1884 1885 setup_timer(&slot->detect_timer, atmci_detect_change, 1886 (unsigned long)slot); 1887 1888 ret = request_irq(gpio_to_irq(slot->detect_pin), 1889 atmci_detect_interrupt, 1890 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, 1891 "mmc-detect", slot); 1892 if (ret) { 1893 dev_dbg(&mmc->class_dev, 1894 "could not request IRQ %d for detect pin\n", 1895 gpio_to_irq(slot->detect_pin)); 1896 gpio_free(slot->detect_pin); 1897 slot->detect_pin = -EBUSY; 1898 } 1899 } 1900 1901 atmci_init_debugfs(slot); 1902 1903 return 0; 1904} 1905 1906static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot, 1907 unsigned int id) 1908{ 1909 /* Debugfs stuff is cleaned up by mmc core */ 1910 1911 set_bit(ATMCI_SHUTDOWN, &slot->flags); 1912 smp_wmb(); 1913 1914 mmc_remove_host(slot->mmc); 1915 1916 if (gpio_is_valid(slot->detect_pin)) { 1917 int pin = slot->detect_pin; 1918 1919 free_irq(gpio_to_irq(pin), slot); 1920 del_timer_sync(&slot->detect_timer); 1921 gpio_free(pin); 1922 } 1923 if (gpio_is_valid(slot->wp_pin)) 1924 gpio_free(slot->wp_pin); 1925 1926 slot->host->slot[id] = NULL; 1927 mmc_free_host(slot->mmc); 1928} 1929 1930static bool atmci_filter(struct dma_chan *chan, void *slave) 1931{ 1932 struct mci_dma_data *sl = slave; 1933 1934 if (sl && find_slave_dev(sl) == chan->device->dev) { 1935 chan->private = slave_data_ptr(sl); 1936 return true; 1937 } else { 1938 return false; 1939 } 1940} 1941 1942static void atmci_configure_dma(struct atmel_mci *host) 1943{ 1944 struct mci_platform_data *pdata; 1945 1946 if (host == NULL) 1947 return; 1948 1949 pdata = host->pdev->dev.platform_data; 1950 1951 if (pdata && find_slave_dev(pdata->dma_slave)) { 1952 dma_cap_mask_t mask; 1953 1954 setup_dma_addr(pdata->dma_slave, 1955 host->mapbase + ATMCI_TDR, 1956 host->mapbase + ATMCI_RDR); 1957 1958 /* Try to grab a DMA channel */ 1959 dma_cap_zero(mask); 1960 dma_cap_set(DMA_SLAVE, mask); 1961 host->dma.chan = 1962 dma_request_channel(mask, atmci_filter, pdata->dma_slave); 1963 } 1964 if (!host->dma.chan) 1965 dev_notice(&host->pdev->dev, "DMA not available, using PIO\n"); 1966 else 1967 dev_info(&host->pdev->dev, 1968 "Using %s for DMA transfers\n", 1969 dma_chan_name(host->dma.chan)); 1970} 1971 1972static inline unsigned int atmci_get_version(struct atmel_mci *host) 1973{ 1974 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff; 1975} 1976 1977/* 1978 * HSMCI (High Speed MCI) module is not fully compatible with MCI module. 1979 * HSMCI provides DMA support and a new config register but no more supports 1980 * PDC. 1981 */ 1982static void __init atmci_get_cap(struct atmel_mci *host) 1983{ 1984 unsigned int version; 1985 1986 version = atmci_get_version(host); 1987 dev_info(&host->pdev->dev, 1988 "version: 0x%x\n", version); 1989 1990 host->caps.has_dma = 0; 1991 host->caps.has_pdc = 0; 1992 host->caps.has_cfg_reg = 0; 1993 host->caps.has_cstor_reg = 0; 1994 host->caps.has_highspeed = 0; 1995 host->caps.has_rwproof = 0; 1996 1997 /* keep only major version number */ 1998 switch (version & 0xf00) { 1999 case 0x100: 2000 case 0x200: 2001 host->caps.has_pdc = 1; 2002 host->caps.has_rwproof = 1; 2003 break; 2004 case 0x300: 2005 case 0x400: 2006 case 0x500: 2007#ifdef CONFIG_AT_HDMAC 2008 host->caps.has_dma = 1; 2009#else 2010 host->caps.has_dma = 0; 2011 dev_info(&host->pdev->dev, 2012 "has dma capability but dma engine is not selected, then use pio\n"); 2013#endif 2014 host->caps.has_cfg_reg = 1; 2015 host->caps.has_cstor_reg = 1; 2016 host->caps.has_highspeed = 1; 2017 host->caps.has_rwproof = 1; 2018 break; 2019 default: 2020 dev_warn(&host->pdev->dev, 2021 "Unmanaged mci version, set minimum capabilities\n"); 2022 break; 2023 } 2024} 2025 2026static int __init atmci_probe(struct platform_device *pdev) 2027{ 2028 struct mci_platform_data *pdata; 2029 struct atmel_mci *host; 2030 struct resource *regs; 2031 unsigned int nr_slots; 2032 int irq; 2033 int ret; 2034 2035 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2036 if (!regs) 2037 return -ENXIO; 2038 pdata = pdev->dev.platform_data; 2039 if (!pdata) 2040 return -ENXIO; 2041 irq = platform_get_irq(pdev, 0); 2042 if (irq < 0) 2043 return irq; 2044 2045 host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL); 2046 if (!host) 2047 return -ENOMEM; 2048 2049 host->pdev = pdev; 2050 spin_lock_init(&host->lock); 2051 INIT_LIST_HEAD(&host->queue); 2052 2053 host->mck = clk_get(&pdev->dev, "mci_clk"); 2054 if (IS_ERR(host->mck)) { 2055 ret = PTR_ERR(host->mck); 2056 goto err_clk_get; 2057 } 2058 2059 ret = -ENOMEM; 2060 host->regs = ioremap(regs->start, resource_size(regs)); 2061 if (!host->regs) 2062 goto err_ioremap; 2063 2064 clk_enable(host->mck); 2065 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); 2066 host->bus_hz = clk_get_rate(host->mck); 2067 clk_disable(host->mck); 2068 2069 host->mapbase = regs->start; 2070 2071 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host); 2072 2073 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host); 2074 if (ret) 2075 goto err_request_irq; 2076 2077 /* Get MCI capabilities and set operations according to it */ 2078 atmci_get_cap(host); 2079 if (host->caps.has_dma) { 2080 dev_info(&pdev->dev, "using DMA\n"); 2081 host->prepare_data = &atmci_prepare_data_dma; 2082 host->submit_data = &atmci_submit_data_dma; 2083 host->stop_transfer = &atmci_stop_transfer_dma; 2084 } else if (host->caps.has_pdc) { 2085 dev_info(&pdev->dev, "using PDC\n"); 2086 host->prepare_data = &atmci_prepare_data_pdc; 2087 host->submit_data = &atmci_submit_data_pdc; 2088 host->stop_transfer = &atmci_stop_transfer_pdc; 2089 } else { 2090 dev_info(&pdev->dev, "no DMA, no PDC\n"); 2091 host->prepare_data = &atmci_prepare_data; 2092 host->submit_data = &atmci_submit_data; 2093 host->stop_transfer = &atmci_stop_transfer; 2094 } 2095 2096 if (host->caps.has_dma) 2097 atmci_configure_dma(host); 2098 2099 platform_set_drvdata(pdev, host); 2100 2101 /* We need at least one slot to succeed */ 2102 nr_slots = 0; 2103 ret = -ENODEV; 2104 if (pdata->slot[0].bus_width) { 2105 ret = atmci_init_slot(host, &pdata->slot[0], 2106 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA); 2107 if (!ret) 2108 nr_slots++; 2109 } 2110 if (pdata->slot[1].bus_width) { 2111 ret = atmci_init_slot(host, &pdata->slot[1], 2112 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB); 2113 if (!ret) 2114 nr_slots++; 2115 } 2116 2117 if (!nr_slots) { 2118 dev_err(&pdev->dev, "init failed: no slot defined\n"); 2119 goto err_init_slot; 2120 } 2121 2122 dev_info(&pdev->dev, 2123 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n", 2124 host->mapbase, irq, nr_slots); 2125 2126 return 0; 2127 2128err_init_slot: 2129 if (host->dma.chan) 2130 dma_release_channel(host->dma.chan); 2131 free_irq(irq, host); 2132err_request_irq: 2133 iounmap(host->regs); 2134err_ioremap: 2135 clk_put(host->mck); 2136err_clk_get: 2137 kfree(host); 2138 return ret; 2139} 2140 2141static int __exit atmci_remove(struct platform_device *pdev) 2142{ 2143 struct atmel_mci *host = platform_get_drvdata(pdev); 2144 unsigned int i; 2145 2146 platform_set_drvdata(pdev, NULL); 2147 2148 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 2149 if (host->slot[i]) 2150 atmci_cleanup_slot(host->slot[i], i); 2151 } 2152 2153 clk_enable(host->mck); 2154 atmci_writel(host, ATMCI_IDR, ~0UL); 2155 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); 2156 atmci_readl(host, ATMCI_SR); 2157 clk_disable(host->mck); 2158 2159#ifdef CONFIG_MMC_ATMELMCI_DMA 2160 if (host->dma.chan) 2161 dma_release_channel(host->dma.chan); 2162#endif 2163 2164 free_irq(platform_get_irq(pdev, 0), host); 2165 iounmap(host->regs); 2166 2167 clk_put(host->mck); 2168 kfree(host); 2169 2170 return 0; 2171} 2172 2173#ifdef CONFIG_PM 2174static int atmci_suspend(struct device *dev) 2175{ 2176 struct atmel_mci *host = dev_get_drvdata(dev); 2177 int i; 2178 2179 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 2180 struct atmel_mci_slot *slot = host->slot[i]; 2181 int ret; 2182 2183 if (!slot) 2184 continue; 2185 ret = mmc_suspend_host(slot->mmc); 2186 if (ret < 0) { 2187 while (--i >= 0) { 2188 slot = host->slot[i]; 2189 if (slot 2190 && test_bit(ATMCI_SUSPENDED, &slot->flags)) { 2191 mmc_resume_host(host->slot[i]->mmc); 2192 clear_bit(ATMCI_SUSPENDED, &slot->flags); 2193 } 2194 } 2195 return ret; 2196 } else { 2197 set_bit(ATMCI_SUSPENDED, &slot->flags); 2198 } 2199 } 2200 2201 return 0; 2202} 2203 2204static int atmci_resume(struct device *dev) 2205{ 2206 struct atmel_mci *host = dev_get_drvdata(dev); 2207 int i; 2208 int ret = 0; 2209 2210 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 2211 struct atmel_mci_slot *slot = host->slot[i]; 2212 int err; 2213 2214 slot = host->slot[i]; 2215 if (!slot) 2216 continue; 2217 if (!test_bit(ATMCI_SUSPENDED, &slot->flags)) 2218 continue; 2219 err = mmc_resume_host(slot->mmc); 2220 if (err < 0) 2221 ret = err; 2222 else 2223 clear_bit(ATMCI_SUSPENDED, &slot->flags); 2224 } 2225 2226 return ret; 2227} 2228static SIMPLE_DEV_PM_OPS(atmci_pm, atmci_suspend, atmci_resume); 2229#define ATMCI_PM_OPS (&atmci_pm) 2230#else 2231#define ATMCI_PM_OPS NULL 2232#endif 2233 2234static struct platform_driver atmci_driver = { 2235 .remove = __exit_p(atmci_remove), 2236 .driver = { 2237 .name = "atmel_mci", 2238 .pm = ATMCI_PM_OPS, 2239 }, 2240}; 2241 2242static int __init atmci_init(void) 2243{ 2244 return platform_driver_probe(&atmci_driver, atmci_probe); 2245} 2246 2247static void __exit atmci_exit(void) 2248{ 2249 platform_driver_unregister(&atmci_driver); 2250} 2251 2252late_initcall(atmci_init); /* try to load after dma driver when built-in */ 2253module_exit(atmci_exit); 2254 2255MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver"); 2256MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 2257MODULE_LICENSE("GPL v2"); 2258