atmel-mci.c revision c3635c78e500a52c9fcd55de381a72928d9e054d
1/* 2 * Atmel MultiMedia Card Interface driver 3 * 4 * Copyright (C) 2004-2008 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10#include <linux/blkdev.h> 11#include <linux/clk.h> 12#include <linux/debugfs.h> 13#include <linux/device.h> 14#include <linux/dmaengine.h> 15#include <linux/dma-mapping.h> 16#include <linux/err.h> 17#include <linux/gpio.h> 18#include <linux/init.h> 19#include <linux/interrupt.h> 20#include <linux/ioport.h> 21#include <linux/module.h> 22#include <linux/platform_device.h> 23#include <linux/scatterlist.h> 24#include <linux/seq_file.h> 25#include <linux/stat.h> 26 27#include <linux/mmc/host.h> 28 29#include <mach/atmel-mci.h> 30#include <linux/atmel-mci.h> 31 32#include <asm/io.h> 33#include <asm/unaligned.h> 34 35#include <mach/cpu.h> 36#include <mach/board.h> 37 38#include "atmel-mci-regs.h" 39 40#define ATMCI_DATA_ERROR_FLAGS (MCI_DCRCE | MCI_DTOE | MCI_OVRE | MCI_UNRE) 41#define ATMCI_DMA_THRESHOLD 16 42 43enum { 44 EVENT_CMD_COMPLETE = 0, 45 EVENT_XFER_COMPLETE, 46 EVENT_DATA_COMPLETE, 47 EVENT_DATA_ERROR, 48}; 49 50enum atmel_mci_state { 51 STATE_IDLE = 0, 52 STATE_SENDING_CMD, 53 STATE_SENDING_DATA, 54 STATE_DATA_BUSY, 55 STATE_SENDING_STOP, 56 STATE_DATA_ERROR, 57}; 58 59struct atmel_mci_dma { 60#ifdef CONFIG_MMC_ATMELMCI_DMA 61 struct dma_chan *chan; 62 struct dma_async_tx_descriptor *data_desc; 63#endif 64}; 65 66/** 67 * struct atmel_mci - MMC controller state shared between all slots 68 * @lock: Spinlock protecting the queue and associated data. 69 * @regs: Pointer to MMIO registers. 70 * @sg: Scatterlist entry currently being processed by PIO code, if any. 71 * @pio_offset: Offset into the current scatterlist entry. 72 * @cur_slot: The slot which is currently using the controller. 73 * @mrq: The request currently being processed on @cur_slot, 74 * or NULL if the controller is idle. 75 * @cmd: The command currently being sent to the card, or NULL. 76 * @data: The data currently being transferred, or NULL if no data 77 * transfer is in progress. 78 * @dma: DMA client state. 79 * @data_chan: DMA channel being used for the current data transfer. 80 * @cmd_status: Snapshot of SR taken upon completion of the current 81 * command. Only valid when EVENT_CMD_COMPLETE is pending. 82 * @data_status: Snapshot of SR taken upon completion of the current 83 * data transfer. Only valid when EVENT_DATA_COMPLETE or 84 * EVENT_DATA_ERROR is pending. 85 * @stop_cmdr: Value to be loaded into CMDR when the stop command is 86 * to be sent. 87 * @tasklet: Tasklet running the request state machine. 88 * @pending_events: Bitmask of events flagged by the interrupt handler 89 * to be processed by the tasklet. 90 * @completed_events: Bitmask of events which the state machine has 91 * processed. 92 * @state: Tasklet state. 93 * @queue: List of slots waiting for access to the controller. 94 * @need_clock_update: Update the clock rate before the next request. 95 * @need_reset: Reset controller before next request. 96 * @mode_reg: Value of the MR register. 97 * @cfg_reg: Value of the CFG register. 98 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 99 * rate and timeout calculations. 100 * @mapbase: Physical address of the MMIO registers. 101 * @mck: The peripheral bus clock hooked up to the MMC controller. 102 * @pdev: Platform device associated with the MMC controller. 103 * @slot: Slots sharing this MMC controller. 104 * 105 * Locking 106 * ======= 107 * 108 * @lock is a softirq-safe spinlock protecting @queue as well as 109 * @cur_slot, @mrq and @state. These must always be updated 110 * at the same time while holding @lock. 111 * 112 * @lock also protects mode_reg and need_clock_update since these are 113 * used to synchronize mode register updates with the queue 114 * processing. 115 * 116 * The @mrq field of struct atmel_mci_slot is also protected by @lock, 117 * and must always be written at the same time as the slot is added to 118 * @queue. 119 * 120 * @pending_events and @completed_events are accessed using atomic bit 121 * operations, so they don't need any locking. 122 * 123 * None of the fields touched by the interrupt handler need any 124 * locking. However, ordering is important: Before EVENT_DATA_ERROR or 125 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 126 * interrupts must be disabled and @data_status updated with a 127 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 128 * CMDRDY interupt must be disabled and @cmd_status updated with a 129 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 130 * bytes_xfered field of @data must be written. This is ensured by 131 * using barriers. 132 */ 133struct atmel_mci { 134 spinlock_t lock; 135 void __iomem *regs; 136 137 struct scatterlist *sg; 138 unsigned int pio_offset; 139 140 struct atmel_mci_slot *cur_slot; 141 struct mmc_request *mrq; 142 struct mmc_command *cmd; 143 struct mmc_data *data; 144 145 struct atmel_mci_dma dma; 146 struct dma_chan *data_chan; 147 148 u32 cmd_status; 149 u32 data_status; 150 u32 stop_cmdr; 151 152 struct tasklet_struct tasklet; 153 unsigned long pending_events; 154 unsigned long completed_events; 155 enum atmel_mci_state state; 156 struct list_head queue; 157 158 bool need_clock_update; 159 bool need_reset; 160 u32 mode_reg; 161 u32 cfg_reg; 162 unsigned long bus_hz; 163 unsigned long mapbase; 164 struct clk *mck; 165 struct platform_device *pdev; 166 167 struct atmel_mci_slot *slot[ATMEL_MCI_MAX_NR_SLOTS]; 168}; 169 170/** 171 * struct atmel_mci_slot - MMC slot state 172 * @mmc: The mmc_host representing this slot. 173 * @host: The MMC controller this slot is using. 174 * @sdc_reg: Value of SDCR to be written before using this slot. 175 * @mrq: mmc_request currently being processed or waiting to be 176 * processed, or NULL when the slot is idle. 177 * @queue_node: List node for placing this node in the @queue list of 178 * &struct atmel_mci. 179 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 180 * @flags: Random state bits associated with the slot. 181 * @detect_pin: GPIO pin used for card detection, or negative if not 182 * available. 183 * @wp_pin: GPIO pin used for card write protect sending, or negative 184 * if not available. 185 * @detect_is_active_high: The state of the detect pin when it is active. 186 * @detect_timer: Timer used for debouncing @detect_pin interrupts. 187 */ 188struct atmel_mci_slot { 189 struct mmc_host *mmc; 190 struct atmel_mci *host; 191 192 u32 sdc_reg; 193 194 struct mmc_request *mrq; 195 struct list_head queue_node; 196 197 unsigned int clock; 198 unsigned long flags; 199#define ATMCI_CARD_PRESENT 0 200#define ATMCI_CARD_NEED_INIT 1 201#define ATMCI_SHUTDOWN 2 202 203 int detect_pin; 204 int wp_pin; 205 bool detect_is_active_high; 206 207 struct timer_list detect_timer; 208}; 209 210#define atmci_test_and_clear_pending(host, event) \ 211 test_and_clear_bit(event, &host->pending_events) 212#define atmci_set_completed(host, event) \ 213 set_bit(event, &host->completed_events) 214#define atmci_set_pending(host, event) \ 215 set_bit(event, &host->pending_events) 216 217/* 218 * Enable or disable features/registers based on 219 * whether the processor supports them 220 */ 221static bool mci_has_rwproof(void) 222{ 223 if (cpu_is_at91sam9261() || cpu_is_at91rm9200()) 224 return false; 225 else 226 return true; 227} 228 229/* 230 * The new MCI2 module isn't 100% compatible with the old MCI module, 231 * and it has a few nice features which we want to use... 232 */ 233static inline bool atmci_is_mci2(void) 234{ 235 if (cpu_is_at91sam9g45()) 236 return true; 237 238 return false; 239} 240 241 242/* 243 * The debugfs stuff below is mostly optimized away when 244 * CONFIG_DEBUG_FS is not set. 245 */ 246static int atmci_req_show(struct seq_file *s, void *v) 247{ 248 struct atmel_mci_slot *slot = s->private; 249 struct mmc_request *mrq; 250 struct mmc_command *cmd; 251 struct mmc_command *stop; 252 struct mmc_data *data; 253 254 /* Make sure we get a consistent snapshot */ 255 spin_lock_bh(&slot->host->lock); 256 mrq = slot->mrq; 257 258 if (mrq) { 259 cmd = mrq->cmd; 260 data = mrq->data; 261 stop = mrq->stop; 262 263 if (cmd) 264 seq_printf(s, 265 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 266 cmd->opcode, cmd->arg, cmd->flags, 267 cmd->resp[0], cmd->resp[1], cmd->resp[2], 268 cmd->resp[2], cmd->error); 269 if (data) 270 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 271 data->bytes_xfered, data->blocks, 272 data->blksz, data->flags, data->error); 273 if (stop) 274 seq_printf(s, 275 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 276 stop->opcode, stop->arg, stop->flags, 277 stop->resp[0], stop->resp[1], stop->resp[2], 278 stop->resp[2], stop->error); 279 } 280 281 spin_unlock_bh(&slot->host->lock); 282 283 return 0; 284} 285 286static int atmci_req_open(struct inode *inode, struct file *file) 287{ 288 return single_open(file, atmci_req_show, inode->i_private); 289} 290 291static const struct file_operations atmci_req_fops = { 292 .owner = THIS_MODULE, 293 .open = atmci_req_open, 294 .read = seq_read, 295 .llseek = seq_lseek, 296 .release = single_release, 297}; 298 299static void atmci_show_status_reg(struct seq_file *s, 300 const char *regname, u32 value) 301{ 302 static const char *sr_bit[] = { 303 [0] = "CMDRDY", 304 [1] = "RXRDY", 305 [2] = "TXRDY", 306 [3] = "BLKE", 307 [4] = "DTIP", 308 [5] = "NOTBUSY", 309 [6] = "ENDRX", 310 [7] = "ENDTX", 311 [8] = "SDIOIRQA", 312 [9] = "SDIOIRQB", 313 [12] = "SDIOWAIT", 314 [14] = "RXBUFF", 315 [15] = "TXBUFE", 316 [16] = "RINDE", 317 [17] = "RDIRE", 318 [18] = "RCRCE", 319 [19] = "RENDE", 320 [20] = "RTOE", 321 [21] = "DCRCE", 322 [22] = "DTOE", 323 [23] = "CSTOE", 324 [24] = "BLKOVRE", 325 [25] = "DMADONE", 326 [26] = "FIFOEMPTY", 327 [27] = "XFRDONE", 328 [30] = "OVRE", 329 [31] = "UNRE", 330 }; 331 unsigned int i; 332 333 seq_printf(s, "%s:\t0x%08x", regname, value); 334 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) { 335 if (value & (1 << i)) { 336 if (sr_bit[i]) 337 seq_printf(s, " %s", sr_bit[i]); 338 else 339 seq_puts(s, " UNKNOWN"); 340 } 341 } 342 seq_putc(s, '\n'); 343} 344 345static int atmci_regs_show(struct seq_file *s, void *v) 346{ 347 struct atmel_mci *host = s->private; 348 u32 *buf; 349 350 buf = kmalloc(MCI_REGS_SIZE, GFP_KERNEL); 351 if (!buf) 352 return -ENOMEM; 353 354 /* 355 * Grab a more or less consistent snapshot. Note that we're 356 * not disabling interrupts, so IMR and SR may not be 357 * consistent. 358 */ 359 spin_lock_bh(&host->lock); 360 clk_enable(host->mck); 361 memcpy_fromio(buf, host->regs, MCI_REGS_SIZE); 362 clk_disable(host->mck); 363 spin_unlock_bh(&host->lock); 364 365 seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n", 366 buf[MCI_MR / 4], 367 buf[MCI_MR / 4] & MCI_MR_RDPROOF ? " RDPROOF" : "", 368 buf[MCI_MR / 4] & MCI_MR_WRPROOF ? " WRPROOF" : "", 369 buf[MCI_MR / 4] & 0xff); 370 seq_printf(s, "DTOR:\t0x%08x\n", buf[MCI_DTOR / 4]); 371 seq_printf(s, "SDCR:\t0x%08x\n", buf[MCI_SDCR / 4]); 372 seq_printf(s, "ARGR:\t0x%08x\n", buf[MCI_ARGR / 4]); 373 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n", 374 buf[MCI_BLKR / 4], 375 buf[MCI_BLKR / 4] & 0xffff, 376 (buf[MCI_BLKR / 4] >> 16) & 0xffff); 377 if (atmci_is_mci2()) 378 seq_printf(s, "CSTOR:\t0x%08x\n", buf[MCI_CSTOR / 4]); 379 380 /* Don't read RSPR and RDR; it will consume the data there */ 381 382 atmci_show_status_reg(s, "SR", buf[MCI_SR / 4]); 383 atmci_show_status_reg(s, "IMR", buf[MCI_IMR / 4]); 384 385 if (atmci_is_mci2()) { 386 u32 val; 387 388 val = buf[MCI_DMA / 4]; 389 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n", 390 val, val & 3, 391 ((val >> 4) & 3) ? 392 1 << (((val >> 4) & 3) + 1) : 1, 393 val & MCI_DMAEN ? " DMAEN" : ""); 394 395 val = buf[MCI_CFG / 4]; 396 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n", 397 val, 398 val & MCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "", 399 val & MCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "", 400 val & MCI_CFG_HSMODE ? " HSMODE" : "", 401 val & MCI_CFG_LSYNC ? " LSYNC" : ""); 402 } 403 404 kfree(buf); 405 406 return 0; 407} 408 409static int atmci_regs_open(struct inode *inode, struct file *file) 410{ 411 return single_open(file, atmci_regs_show, inode->i_private); 412} 413 414static const struct file_operations atmci_regs_fops = { 415 .owner = THIS_MODULE, 416 .open = atmci_regs_open, 417 .read = seq_read, 418 .llseek = seq_lseek, 419 .release = single_release, 420}; 421 422static void atmci_init_debugfs(struct atmel_mci_slot *slot) 423{ 424 struct mmc_host *mmc = slot->mmc; 425 struct atmel_mci *host = slot->host; 426 struct dentry *root; 427 struct dentry *node; 428 429 root = mmc->debugfs_root; 430 if (!root) 431 return; 432 433 node = debugfs_create_file("regs", S_IRUSR, root, host, 434 &atmci_regs_fops); 435 if (IS_ERR(node)) 436 return; 437 if (!node) 438 goto err; 439 440 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops); 441 if (!node) 442 goto err; 443 444 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 445 if (!node) 446 goto err; 447 448 node = debugfs_create_x32("pending_events", S_IRUSR, root, 449 (u32 *)&host->pending_events); 450 if (!node) 451 goto err; 452 453 node = debugfs_create_x32("completed_events", S_IRUSR, root, 454 (u32 *)&host->completed_events); 455 if (!node) 456 goto err; 457 458 return; 459 460err: 461 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 462} 463 464static inline unsigned int ns_to_clocks(struct atmel_mci *host, 465 unsigned int ns) 466{ 467 return (ns * (host->bus_hz / 1000000) + 999) / 1000; 468} 469 470static void atmci_set_timeout(struct atmel_mci *host, 471 struct atmel_mci_slot *slot, struct mmc_data *data) 472{ 473 static unsigned dtomul_to_shift[] = { 474 0, 4, 7, 8, 10, 12, 16, 20 475 }; 476 unsigned timeout; 477 unsigned dtocyc; 478 unsigned dtomul; 479 480 timeout = ns_to_clocks(host, data->timeout_ns) + data->timeout_clks; 481 482 for (dtomul = 0; dtomul < 8; dtomul++) { 483 unsigned shift = dtomul_to_shift[dtomul]; 484 dtocyc = (timeout + (1 << shift) - 1) >> shift; 485 if (dtocyc < 15) 486 break; 487 } 488 489 if (dtomul >= 8) { 490 dtomul = 7; 491 dtocyc = 15; 492 } 493 494 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n", 495 dtocyc << dtomul_to_shift[dtomul]); 496 mci_writel(host, DTOR, (MCI_DTOMUL(dtomul) | MCI_DTOCYC(dtocyc))); 497} 498 499/* 500 * Return mask with command flags to be enabled for this command. 501 */ 502static u32 atmci_prepare_command(struct mmc_host *mmc, 503 struct mmc_command *cmd) 504{ 505 struct mmc_data *data; 506 u32 cmdr; 507 508 cmd->error = -EINPROGRESS; 509 510 cmdr = MCI_CMDR_CMDNB(cmd->opcode); 511 512 if (cmd->flags & MMC_RSP_PRESENT) { 513 if (cmd->flags & MMC_RSP_136) 514 cmdr |= MCI_CMDR_RSPTYP_136BIT; 515 else 516 cmdr |= MCI_CMDR_RSPTYP_48BIT; 517 } 518 519 /* 520 * This should really be MAXLAT_5 for CMD2 and ACMD41, but 521 * it's too difficult to determine whether this is an ACMD or 522 * not. Better make it 64. 523 */ 524 cmdr |= MCI_CMDR_MAXLAT_64CYC; 525 526 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN) 527 cmdr |= MCI_CMDR_OPDCMD; 528 529 data = cmd->data; 530 if (data) { 531 cmdr |= MCI_CMDR_START_XFER; 532 if (data->flags & MMC_DATA_STREAM) 533 cmdr |= MCI_CMDR_STREAM; 534 else if (data->blocks > 1) 535 cmdr |= MCI_CMDR_MULTI_BLOCK; 536 else 537 cmdr |= MCI_CMDR_BLOCK; 538 539 if (data->flags & MMC_DATA_READ) 540 cmdr |= MCI_CMDR_TRDIR_READ; 541 } 542 543 return cmdr; 544} 545 546static void atmci_start_command(struct atmel_mci *host, 547 struct mmc_command *cmd, u32 cmd_flags) 548{ 549 WARN_ON(host->cmd); 550 host->cmd = cmd; 551 552 dev_vdbg(&host->pdev->dev, 553 "start command: ARGR=0x%08x CMDR=0x%08x\n", 554 cmd->arg, cmd_flags); 555 556 mci_writel(host, ARGR, cmd->arg); 557 mci_writel(host, CMDR, cmd_flags); 558} 559 560static void send_stop_cmd(struct atmel_mci *host, struct mmc_data *data) 561{ 562 atmci_start_command(host, data->stop, host->stop_cmdr); 563 mci_writel(host, IER, MCI_CMDRDY); 564} 565 566#ifdef CONFIG_MMC_ATMELMCI_DMA 567static void atmci_dma_cleanup(struct atmel_mci *host) 568{ 569 struct mmc_data *data = host->data; 570 571 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, 572 ((data->flags & MMC_DATA_WRITE) 573 ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); 574} 575 576static void atmci_stop_dma(struct atmel_mci *host) 577{ 578 struct dma_chan *chan = host->data_chan; 579 580 if (chan) { 581 chan->device->device_control(chan, DMA_TERMINATE_ALL); 582 atmci_dma_cleanup(host); 583 } else { 584 /* Data transfer was stopped by the interrupt handler */ 585 atmci_set_pending(host, EVENT_XFER_COMPLETE); 586 mci_writel(host, IER, MCI_NOTBUSY); 587 } 588} 589 590/* This function is called by the DMA driver from tasklet context. */ 591static void atmci_dma_complete(void *arg) 592{ 593 struct atmel_mci *host = arg; 594 struct mmc_data *data = host->data; 595 596 dev_vdbg(&host->pdev->dev, "DMA complete\n"); 597 598 if (atmci_is_mci2()) 599 /* Disable DMA hardware handshaking on MCI */ 600 mci_writel(host, DMA, mci_readl(host, DMA) & ~MCI_DMAEN); 601 602 atmci_dma_cleanup(host); 603 604 /* 605 * If the card was removed, data will be NULL. No point trying 606 * to send the stop command or waiting for NBUSY in this case. 607 */ 608 if (data) { 609 atmci_set_pending(host, EVENT_XFER_COMPLETE); 610 tasklet_schedule(&host->tasklet); 611 612 /* 613 * Regardless of what the documentation says, we have 614 * to wait for NOTBUSY even after block read 615 * operations. 616 * 617 * When the DMA transfer is complete, the controller 618 * may still be reading the CRC from the card, i.e. 619 * the data transfer is still in progress and we 620 * haven't seen all the potential error bits yet. 621 * 622 * The interrupt handler will schedule a different 623 * tasklet to finish things up when the data transfer 624 * is completely done. 625 * 626 * We may not complete the mmc request here anyway 627 * because the mmc layer may call back and cause us to 628 * violate the "don't submit new operations from the 629 * completion callback" rule of the dma engine 630 * framework. 631 */ 632 mci_writel(host, IER, MCI_NOTBUSY); 633 } 634} 635 636static int 637atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data) 638{ 639 struct dma_chan *chan; 640 struct dma_async_tx_descriptor *desc; 641 struct scatterlist *sg; 642 unsigned int i; 643 enum dma_data_direction direction; 644 unsigned int sglen; 645 646 /* 647 * We don't do DMA on "complex" transfers, i.e. with 648 * non-word-aligned buffers or lengths. Also, we don't bother 649 * with all the DMA setup overhead for short transfers. 650 */ 651 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD) 652 return -EINVAL; 653 if (data->blksz & 3) 654 return -EINVAL; 655 656 for_each_sg(data->sg, sg, data->sg_len, i) { 657 if (sg->offset & 3 || sg->length & 3) 658 return -EINVAL; 659 } 660 661 /* If we don't have a channel, we can't do DMA */ 662 chan = host->dma.chan; 663 if (chan) 664 host->data_chan = chan; 665 666 if (!chan) 667 return -ENODEV; 668 669 if (atmci_is_mci2()) 670 mci_writel(host, DMA, MCI_DMA_CHKSIZE(3) | MCI_DMAEN); 671 672 if (data->flags & MMC_DATA_READ) 673 direction = DMA_FROM_DEVICE; 674 else 675 direction = DMA_TO_DEVICE; 676 677 sglen = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, direction); 678 if (sglen != data->sg_len) 679 goto unmap_exit; 680 desc = chan->device->device_prep_slave_sg(chan, 681 data->sg, data->sg_len, direction, 682 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 683 if (!desc) 684 goto unmap_exit; 685 686 host->dma.data_desc = desc; 687 desc->callback = atmci_dma_complete; 688 desc->callback_param = host; 689 690 return 0; 691unmap_exit: 692 dma_unmap_sg(&host->pdev->dev, data->sg, sglen, direction); 693 return -ENOMEM; 694} 695 696static void atmci_submit_data(struct atmel_mci *host) 697{ 698 struct dma_chan *chan = host->data_chan; 699 struct dma_async_tx_descriptor *desc = host->dma.data_desc; 700 701 if (chan) { 702 desc->tx_submit(desc); 703 chan->device->device_issue_pending(chan); 704 } 705} 706 707#else /* CONFIG_MMC_ATMELMCI_DMA */ 708 709static int atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data) 710{ 711 return -ENOSYS; 712} 713 714static void atmci_submit_data(struct atmel_mci *host) {} 715 716static void atmci_stop_dma(struct atmel_mci *host) 717{ 718 /* Data transfer was stopped by the interrupt handler */ 719 atmci_set_pending(host, EVENT_XFER_COMPLETE); 720 mci_writel(host, IER, MCI_NOTBUSY); 721} 722 723#endif /* CONFIG_MMC_ATMELMCI_DMA */ 724 725/* 726 * Returns a mask of interrupt flags to be enabled after the whole 727 * request has been prepared. 728 */ 729static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data) 730{ 731 u32 iflags; 732 733 data->error = -EINPROGRESS; 734 735 WARN_ON(host->data); 736 host->sg = NULL; 737 host->data = data; 738 739 iflags = ATMCI_DATA_ERROR_FLAGS; 740 if (atmci_prepare_data_dma(host, data)) { 741 host->data_chan = NULL; 742 743 /* 744 * Errata: MMC data write operation with less than 12 745 * bytes is impossible. 746 * 747 * Errata: MCI Transmit Data Register (TDR) FIFO 748 * corruption when length is not multiple of 4. 749 */ 750 if (data->blocks * data->blksz < 12 751 || (data->blocks * data->blksz) & 3) 752 host->need_reset = true; 753 754 host->sg = data->sg; 755 host->pio_offset = 0; 756 if (data->flags & MMC_DATA_READ) 757 iflags |= MCI_RXRDY; 758 else 759 iflags |= MCI_TXRDY; 760 } 761 762 return iflags; 763} 764 765static void atmci_start_request(struct atmel_mci *host, 766 struct atmel_mci_slot *slot) 767{ 768 struct mmc_request *mrq; 769 struct mmc_command *cmd; 770 struct mmc_data *data; 771 u32 iflags; 772 u32 cmdflags; 773 774 mrq = slot->mrq; 775 host->cur_slot = slot; 776 host->mrq = mrq; 777 778 host->pending_events = 0; 779 host->completed_events = 0; 780 host->data_status = 0; 781 782 if (host->need_reset) { 783 mci_writel(host, CR, MCI_CR_SWRST); 784 mci_writel(host, CR, MCI_CR_MCIEN); 785 mci_writel(host, MR, host->mode_reg); 786 if (atmci_is_mci2()) 787 mci_writel(host, CFG, host->cfg_reg); 788 host->need_reset = false; 789 } 790 mci_writel(host, SDCR, slot->sdc_reg); 791 792 iflags = mci_readl(host, IMR); 793 if (iflags) 794 dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n", 795 iflags); 796 797 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) { 798 /* Send init sequence (74 clock cycles) */ 799 mci_writel(host, CMDR, MCI_CMDR_SPCMD_INIT); 800 while (!(mci_readl(host, SR) & MCI_CMDRDY)) 801 cpu_relax(); 802 } 803 iflags = 0; 804 data = mrq->data; 805 if (data) { 806 atmci_set_timeout(host, slot, data); 807 808 /* Must set block count/size before sending command */ 809 mci_writel(host, BLKR, MCI_BCNT(data->blocks) 810 | MCI_BLKLEN(data->blksz)); 811 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n", 812 MCI_BCNT(data->blocks) | MCI_BLKLEN(data->blksz)); 813 814 iflags |= atmci_prepare_data(host, data); 815 } 816 817 iflags |= MCI_CMDRDY; 818 cmd = mrq->cmd; 819 cmdflags = atmci_prepare_command(slot->mmc, cmd); 820 atmci_start_command(host, cmd, cmdflags); 821 822 if (data) 823 atmci_submit_data(host); 824 825 if (mrq->stop) { 826 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop); 827 host->stop_cmdr |= MCI_CMDR_STOP_XFER; 828 if (!(data->flags & MMC_DATA_WRITE)) 829 host->stop_cmdr |= MCI_CMDR_TRDIR_READ; 830 if (data->flags & MMC_DATA_STREAM) 831 host->stop_cmdr |= MCI_CMDR_STREAM; 832 else 833 host->stop_cmdr |= MCI_CMDR_MULTI_BLOCK; 834 } 835 836 /* 837 * We could have enabled interrupts earlier, but I suspect 838 * that would open up a nice can of interesting race 839 * conditions (e.g. command and data complete, but stop not 840 * prepared yet.) 841 */ 842 mci_writel(host, IER, iflags); 843} 844 845static void atmci_queue_request(struct atmel_mci *host, 846 struct atmel_mci_slot *slot, struct mmc_request *mrq) 847{ 848 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 849 host->state); 850 851 spin_lock_bh(&host->lock); 852 slot->mrq = mrq; 853 if (host->state == STATE_IDLE) { 854 host->state = STATE_SENDING_CMD; 855 atmci_start_request(host, slot); 856 } else { 857 list_add_tail(&slot->queue_node, &host->queue); 858 } 859 spin_unlock_bh(&host->lock); 860} 861 862static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 863{ 864 struct atmel_mci_slot *slot = mmc_priv(mmc); 865 struct atmel_mci *host = slot->host; 866 struct mmc_data *data; 867 868 WARN_ON(slot->mrq); 869 870 /* 871 * We may "know" the card is gone even though there's still an 872 * electrical connection. If so, we really need to communicate 873 * this to the MMC core since there won't be any more 874 * interrupts as the card is completely removed. Otherwise, 875 * the MMC core might believe the card is still there even 876 * though the card was just removed very slowly. 877 */ 878 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) { 879 mrq->cmd->error = -ENOMEDIUM; 880 mmc_request_done(mmc, mrq); 881 return; 882 } 883 884 /* We don't support multiple blocks of weird lengths. */ 885 data = mrq->data; 886 if (data && data->blocks > 1 && data->blksz & 3) { 887 mrq->cmd->error = -EINVAL; 888 mmc_request_done(mmc, mrq); 889 } 890 891 atmci_queue_request(host, slot, mrq); 892} 893 894static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 895{ 896 struct atmel_mci_slot *slot = mmc_priv(mmc); 897 struct atmel_mci *host = slot->host; 898 unsigned int i; 899 900 slot->sdc_reg &= ~MCI_SDCBUS_MASK; 901 switch (ios->bus_width) { 902 case MMC_BUS_WIDTH_1: 903 slot->sdc_reg |= MCI_SDCBUS_1BIT; 904 break; 905 case MMC_BUS_WIDTH_4: 906 slot->sdc_reg |= MCI_SDCBUS_4BIT; 907 break; 908 } 909 910 if (ios->clock) { 911 unsigned int clock_min = ~0U; 912 u32 clkdiv; 913 914 spin_lock_bh(&host->lock); 915 if (!host->mode_reg) { 916 clk_enable(host->mck); 917 mci_writel(host, CR, MCI_CR_SWRST); 918 mci_writel(host, CR, MCI_CR_MCIEN); 919 if (atmci_is_mci2()) 920 mci_writel(host, CFG, host->cfg_reg); 921 } 922 923 /* 924 * Use mirror of ios->clock to prevent race with mmc 925 * core ios update when finding the minimum. 926 */ 927 slot->clock = ios->clock; 928 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { 929 if (host->slot[i] && host->slot[i]->clock 930 && host->slot[i]->clock < clock_min) 931 clock_min = host->slot[i]->clock; 932 } 933 934 /* Calculate clock divider */ 935 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1; 936 if (clkdiv > 255) { 937 dev_warn(&mmc->class_dev, 938 "clock %u too slow; using %lu\n", 939 clock_min, host->bus_hz / (2 * 256)); 940 clkdiv = 255; 941 } 942 943 host->mode_reg = MCI_MR_CLKDIV(clkdiv); 944 945 /* 946 * WRPROOF and RDPROOF prevent overruns/underruns by 947 * stopping the clock when the FIFO is full/empty. 948 * This state is not expected to last for long. 949 */ 950 if (mci_has_rwproof()) 951 host->mode_reg |= (MCI_MR_WRPROOF | MCI_MR_RDPROOF); 952 953 if (list_empty(&host->queue)) 954 mci_writel(host, MR, host->mode_reg); 955 else 956 host->need_clock_update = true; 957 958 spin_unlock_bh(&host->lock); 959 } else { 960 bool any_slot_active = false; 961 962 spin_lock_bh(&host->lock); 963 slot->clock = 0; 964 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { 965 if (host->slot[i] && host->slot[i]->clock) { 966 any_slot_active = true; 967 break; 968 } 969 } 970 if (!any_slot_active) { 971 mci_writel(host, CR, MCI_CR_MCIDIS); 972 if (host->mode_reg) { 973 mci_readl(host, MR); 974 clk_disable(host->mck); 975 } 976 host->mode_reg = 0; 977 } 978 spin_unlock_bh(&host->lock); 979 } 980 981 switch (ios->power_mode) { 982 case MMC_POWER_UP: 983 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags); 984 break; 985 default: 986 /* 987 * TODO: None of the currently available AVR32-based 988 * boards allow MMC power to be turned off. Implement 989 * power control when this can be tested properly. 990 * 991 * We also need to hook this into the clock management 992 * somehow so that newly inserted cards aren't 993 * subjected to a fast clock before we have a chance 994 * to figure out what the maximum rate is. Currently, 995 * there's no way to avoid this, and there never will 996 * be for boards that don't support power control. 997 */ 998 break; 999 } 1000} 1001 1002static int atmci_get_ro(struct mmc_host *mmc) 1003{ 1004 int read_only = -ENOSYS; 1005 struct atmel_mci_slot *slot = mmc_priv(mmc); 1006 1007 if (gpio_is_valid(slot->wp_pin)) { 1008 read_only = gpio_get_value(slot->wp_pin); 1009 dev_dbg(&mmc->class_dev, "card is %s\n", 1010 read_only ? "read-only" : "read-write"); 1011 } 1012 1013 return read_only; 1014} 1015 1016static int atmci_get_cd(struct mmc_host *mmc) 1017{ 1018 int present = -ENOSYS; 1019 struct atmel_mci_slot *slot = mmc_priv(mmc); 1020 1021 if (gpio_is_valid(slot->detect_pin)) { 1022 present = !(gpio_get_value(slot->detect_pin) ^ 1023 slot->detect_is_active_high); 1024 dev_dbg(&mmc->class_dev, "card is %spresent\n", 1025 present ? "" : "not "); 1026 } 1027 1028 return present; 1029} 1030 1031static const struct mmc_host_ops atmci_ops = { 1032 .request = atmci_request, 1033 .set_ios = atmci_set_ios, 1034 .get_ro = atmci_get_ro, 1035 .get_cd = atmci_get_cd, 1036}; 1037 1038/* Called with host->lock held */ 1039static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq) 1040 __releases(&host->lock) 1041 __acquires(&host->lock) 1042{ 1043 struct atmel_mci_slot *slot = NULL; 1044 struct mmc_host *prev_mmc = host->cur_slot->mmc; 1045 1046 WARN_ON(host->cmd || host->data); 1047 1048 /* 1049 * Update the MMC clock rate if necessary. This may be 1050 * necessary if set_ios() is called when a different slot is 1051 * busy transfering data. 1052 */ 1053 if (host->need_clock_update) 1054 mci_writel(host, MR, host->mode_reg); 1055 1056 host->cur_slot->mrq = NULL; 1057 host->mrq = NULL; 1058 if (!list_empty(&host->queue)) { 1059 slot = list_entry(host->queue.next, 1060 struct atmel_mci_slot, queue_node); 1061 list_del(&slot->queue_node); 1062 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n", 1063 mmc_hostname(slot->mmc)); 1064 host->state = STATE_SENDING_CMD; 1065 atmci_start_request(host, slot); 1066 } else { 1067 dev_vdbg(&host->pdev->dev, "list empty\n"); 1068 host->state = STATE_IDLE; 1069 } 1070 1071 spin_unlock(&host->lock); 1072 mmc_request_done(prev_mmc, mrq); 1073 spin_lock(&host->lock); 1074} 1075 1076static void atmci_command_complete(struct atmel_mci *host, 1077 struct mmc_command *cmd) 1078{ 1079 u32 status = host->cmd_status; 1080 1081 /* Read the response from the card (up to 16 bytes) */ 1082 cmd->resp[0] = mci_readl(host, RSPR); 1083 cmd->resp[1] = mci_readl(host, RSPR); 1084 cmd->resp[2] = mci_readl(host, RSPR); 1085 cmd->resp[3] = mci_readl(host, RSPR); 1086 1087 if (status & MCI_RTOE) 1088 cmd->error = -ETIMEDOUT; 1089 else if ((cmd->flags & MMC_RSP_CRC) && (status & MCI_RCRCE)) 1090 cmd->error = -EILSEQ; 1091 else if (status & (MCI_RINDE | MCI_RDIRE | MCI_RENDE)) 1092 cmd->error = -EIO; 1093 else 1094 cmd->error = 0; 1095 1096 if (cmd->error) { 1097 dev_dbg(&host->pdev->dev, 1098 "command error: status=0x%08x\n", status); 1099 1100 if (cmd->data) { 1101 host->data = NULL; 1102 atmci_stop_dma(host); 1103 mci_writel(host, IDR, MCI_NOTBUSY 1104 | MCI_TXRDY | MCI_RXRDY 1105 | ATMCI_DATA_ERROR_FLAGS); 1106 } 1107 } 1108} 1109 1110static void atmci_detect_change(unsigned long data) 1111{ 1112 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data; 1113 bool present; 1114 bool present_old; 1115 1116 /* 1117 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before 1118 * freeing the interrupt. We must not re-enable the interrupt 1119 * if it has been freed, and if we're shutting down, it 1120 * doesn't really matter whether the card is present or not. 1121 */ 1122 smp_rmb(); 1123 if (test_bit(ATMCI_SHUTDOWN, &slot->flags)) 1124 return; 1125 1126 enable_irq(gpio_to_irq(slot->detect_pin)); 1127 present = !(gpio_get_value(slot->detect_pin) ^ 1128 slot->detect_is_active_high); 1129 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags); 1130 1131 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n", 1132 present, present_old); 1133 1134 if (present != present_old) { 1135 struct atmel_mci *host = slot->host; 1136 struct mmc_request *mrq; 1137 1138 dev_dbg(&slot->mmc->class_dev, "card %s\n", 1139 present ? "inserted" : "removed"); 1140 1141 spin_lock(&host->lock); 1142 1143 if (!present) 1144 clear_bit(ATMCI_CARD_PRESENT, &slot->flags); 1145 else 1146 set_bit(ATMCI_CARD_PRESENT, &slot->flags); 1147 1148 /* Clean up queue if present */ 1149 mrq = slot->mrq; 1150 if (mrq) { 1151 if (mrq == host->mrq) { 1152 /* 1153 * Reset controller to terminate any ongoing 1154 * commands or data transfers. 1155 */ 1156 mci_writel(host, CR, MCI_CR_SWRST); 1157 mci_writel(host, CR, MCI_CR_MCIEN); 1158 mci_writel(host, MR, host->mode_reg); 1159 if (atmci_is_mci2()) 1160 mci_writel(host, CFG, host->cfg_reg); 1161 1162 host->data = NULL; 1163 host->cmd = NULL; 1164 1165 switch (host->state) { 1166 case STATE_IDLE: 1167 break; 1168 case STATE_SENDING_CMD: 1169 mrq->cmd->error = -ENOMEDIUM; 1170 if (!mrq->data) 1171 break; 1172 /* fall through */ 1173 case STATE_SENDING_DATA: 1174 mrq->data->error = -ENOMEDIUM; 1175 atmci_stop_dma(host); 1176 break; 1177 case STATE_DATA_BUSY: 1178 case STATE_DATA_ERROR: 1179 if (mrq->data->error == -EINPROGRESS) 1180 mrq->data->error = -ENOMEDIUM; 1181 if (!mrq->stop) 1182 break; 1183 /* fall through */ 1184 case STATE_SENDING_STOP: 1185 mrq->stop->error = -ENOMEDIUM; 1186 break; 1187 } 1188 1189 atmci_request_end(host, mrq); 1190 } else { 1191 list_del(&slot->queue_node); 1192 mrq->cmd->error = -ENOMEDIUM; 1193 if (mrq->data) 1194 mrq->data->error = -ENOMEDIUM; 1195 if (mrq->stop) 1196 mrq->stop->error = -ENOMEDIUM; 1197 1198 spin_unlock(&host->lock); 1199 mmc_request_done(slot->mmc, mrq); 1200 spin_lock(&host->lock); 1201 } 1202 } 1203 spin_unlock(&host->lock); 1204 1205 mmc_detect_change(slot->mmc, 0); 1206 } 1207} 1208 1209static void atmci_tasklet_func(unsigned long priv) 1210{ 1211 struct atmel_mci *host = (struct atmel_mci *)priv; 1212 struct mmc_request *mrq = host->mrq; 1213 struct mmc_data *data = host->data; 1214 struct mmc_command *cmd = host->cmd; 1215 enum atmel_mci_state state = host->state; 1216 enum atmel_mci_state prev_state; 1217 u32 status; 1218 1219 spin_lock(&host->lock); 1220 1221 state = host->state; 1222 1223 dev_vdbg(&host->pdev->dev, 1224 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n", 1225 state, host->pending_events, host->completed_events, 1226 mci_readl(host, IMR)); 1227 1228 do { 1229 prev_state = state; 1230 1231 switch (state) { 1232 case STATE_IDLE: 1233 break; 1234 1235 case STATE_SENDING_CMD: 1236 if (!atmci_test_and_clear_pending(host, 1237 EVENT_CMD_COMPLETE)) 1238 break; 1239 1240 host->cmd = NULL; 1241 atmci_set_completed(host, EVENT_CMD_COMPLETE); 1242 atmci_command_complete(host, mrq->cmd); 1243 if (!mrq->data || cmd->error) { 1244 atmci_request_end(host, host->mrq); 1245 goto unlock; 1246 } 1247 1248 prev_state = state = STATE_SENDING_DATA; 1249 /* fall through */ 1250 1251 case STATE_SENDING_DATA: 1252 if (atmci_test_and_clear_pending(host, 1253 EVENT_DATA_ERROR)) { 1254 atmci_stop_dma(host); 1255 if (data->stop) 1256 send_stop_cmd(host, data); 1257 state = STATE_DATA_ERROR; 1258 break; 1259 } 1260 1261 if (!atmci_test_and_clear_pending(host, 1262 EVENT_XFER_COMPLETE)) 1263 break; 1264 1265 atmci_set_completed(host, EVENT_XFER_COMPLETE); 1266 prev_state = state = STATE_DATA_BUSY; 1267 /* fall through */ 1268 1269 case STATE_DATA_BUSY: 1270 if (!atmci_test_and_clear_pending(host, 1271 EVENT_DATA_COMPLETE)) 1272 break; 1273 1274 host->data = NULL; 1275 atmci_set_completed(host, EVENT_DATA_COMPLETE); 1276 status = host->data_status; 1277 if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) { 1278 if (status & MCI_DTOE) { 1279 dev_dbg(&host->pdev->dev, 1280 "data timeout error\n"); 1281 data->error = -ETIMEDOUT; 1282 } else if (status & MCI_DCRCE) { 1283 dev_dbg(&host->pdev->dev, 1284 "data CRC error\n"); 1285 data->error = -EILSEQ; 1286 } else { 1287 dev_dbg(&host->pdev->dev, 1288 "data FIFO error (status=%08x)\n", 1289 status); 1290 data->error = -EIO; 1291 } 1292 } else { 1293 data->bytes_xfered = data->blocks * data->blksz; 1294 data->error = 0; 1295 } 1296 1297 if (!data->stop) { 1298 atmci_request_end(host, host->mrq); 1299 goto unlock; 1300 } 1301 1302 prev_state = state = STATE_SENDING_STOP; 1303 if (!data->error) 1304 send_stop_cmd(host, data); 1305 /* fall through */ 1306 1307 case STATE_SENDING_STOP: 1308 if (!atmci_test_and_clear_pending(host, 1309 EVENT_CMD_COMPLETE)) 1310 break; 1311 1312 host->cmd = NULL; 1313 atmci_command_complete(host, mrq->stop); 1314 atmci_request_end(host, host->mrq); 1315 goto unlock; 1316 1317 case STATE_DATA_ERROR: 1318 if (!atmci_test_and_clear_pending(host, 1319 EVENT_XFER_COMPLETE)) 1320 break; 1321 1322 state = STATE_DATA_BUSY; 1323 break; 1324 } 1325 } while (state != prev_state); 1326 1327 host->state = state; 1328 1329unlock: 1330 spin_unlock(&host->lock); 1331} 1332 1333static void atmci_read_data_pio(struct atmel_mci *host) 1334{ 1335 struct scatterlist *sg = host->sg; 1336 void *buf = sg_virt(sg); 1337 unsigned int offset = host->pio_offset; 1338 struct mmc_data *data = host->data; 1339 u32 value; 1340 u32 status; 1341 unsigned int nbytes = 0; 1342 1343 do { 1344 value = mci_readl(host, RDR); 1345 if (likely(offset + 4 <= sg->length)) { 1346 put_unaligned(value, (u32 *)(buf + offset)); 1347 1348 offset += 4; 1349 nbytes += 4; 1350 1351 if (offset == sg->length) { 1352 flush_dcache_page(sg_page(sg)); 1353 host->sg = sg = sg_next(sg); 1354 if (!sg) 1355 goto done; 1356 1357 offset = 0; 1358 buf = sg_virt(sg); 1359 } 1360 } else { 1361 unsigned int remaining = sg->length - offset; 1362 memcpy(buf + offset, &value, remaining); 1363 nbytes += remaining; 1364 1365 flush_dcache_page(sg_page(sg)); 1366 host->sg = sg = sg_next(sg); 1367 if (!sg) 1368 goto done; 1369 1370 offset = 4 - remaining; 1371 buf = sg_virt(sg); 1372 memcpy(buf, (u8 *)&value + remaining, offset); 1373 nbytes += offset; 1374 } 1375 1376 status = mci_readl(host, SR); 1377 if (status & ATMCI_DATA_ERROR_FLAGS) { 1378 mci_writel(host, IDR, (MCI_NOTBUSY | MCI_RXRDY 1379 | ATMCI_DATA_ERROR_FLAGS)); 1380 host->data_status = status; 1381 data->bytes_xfered += nbytes; 1382 smp_wmb(); 1383 atmci_set_pending(host, EVENT_DATA_ERROR); 1384 tasklet_schedule(&host->tasklet); 1385 return; 1386 } 1387 } while (status & MCI_RXRDY); 1388 1389 host->pio_offset = offset; 1390 data->bytes_xfered += nbytes; 1391 1392 return; 1393 1394done: 1395 mci_writel(host, IDR, MCI_RXRDY); 1396 mci_writel(host, IER, MCI_NOTBUSY); 1397 data->bytes_xfered += nbytes; 1398 smp_wmb(); 1399 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1400} 1401 1402static void atmci_write_data_pio(struct atmel_mci *host) 1403{ 1404 struct scatterlist *sg = host->sg; 1405 void *buf = sg_virt(sg); 1406 unsigned int offset = host->pio_offset; 1407 struct mmc_data *data = host->data; 1408 u32 value; 1409 u32 status; 1410 unsigned int nbytes = 0; 1411 1412 do { 1413 if (likely(offset + 4 <= sg->length)) { 1414 value = get_unaligned((u32 *)(buf + offset)); 1415 mci_writel(host, TDR, value); 1416 1417 offset += 4; 1418 nbytes += 4; 1419 if (offset == sg->length) { 1420 host->sg = sg = sg_next(sg); 1421 if (!sg) 1422 goto done; 1423 1424 offset = 0; 1425 buf = sg_virt(sg); 1426 } 1427 } else { 1428 unsigned int remaining = sg->length - offset; 1429 1430 value = 0; 1431 memcpy(&value, buf + offset, remaining); 1432 nbytes += remaining; 1433 1434 host->sg = sg = sg_next(sg); 1435 if (!sg) { 1436 mci_writel(host, TDR, value); 1437 goto done; 1438 } 1439 1440 offset = 4 - remaining; 1441 buf = sg_virt(sg); 1442 memcpy((u8 *)&value + remaining, buf, offset); 1443 mci_writel(host, TDR, value); 1444 nbytes += offset; 1445 } 1446 1447 status = mci_readl(host, SR); 1448 if (status & ATMCI_DATA_ERROR_FLAGS) { 1449 mci_writel(host, IDR, (MCI_NOTBUSY | MCI_TXRDY 1450 | ATMCI_DATA_ERROR_FLAGS)); 1451 host->data_status = status; 1452 data->bytes_xfered += nbytes; 1453 smp_wmb(); 1454 atmci_set_pending(host, EVENT_DATA_ERROR); 1455 tasklet_schedule(&host->tasklet); 1456 return; 1457 } 1458 } while (status & MCI_TXRDY); 1459 1460 host->pio_offset = offset; 1461 data->bytes_xfered += nbytes; 1462 1463 return; 1464 1465done: 1466 mci_writel(host, IDR, MCI_TXRDY); 1467 mci_writel(host, IER, MCI_NOTBUSY); 1468 data->bytes_xfered += nbytes; 1469 smp_wmb(); 1470 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1471} 1472 1473static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status) 1474{ 1475 mci_writel(host, IDR, MCI_CMDRDY); 1476 1477 host->cmd_status = status; 1478 smp_wmb(); 1479 atmci_set_pending(host, EVENT_CMD_COMPLETE); 1480 tasklet_schedule(&host->tasklet); 1481} 1482 1483static irqreturn_t atmci_interrupt(int irq, void *dev_id) 1484{ 1485 struct atmel_mci *host = dev_id; 1486 u32 status, mask, pending; 1487 unsigned int pass_count = 0; 1488 1489 do { 1490 status = mci_readl(host, SR); 1491 mask = mci_readl(host, IMR); 1492 pending = status & mask; 1493 if (!pending) 1494 break; 1495 1496 if (pending & ATMCI_DATA_ERROR_FLAGS) { 1497 mci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS 1498 | MCI_RXRDY | MCI_TXRDY); 1499 pending &= mci_readl(host, IMR); 1500 1501 host->data_status = status; 1502 smp_wmb(); 1503 atmci_set_pending(host, EVENT_DATA_ERROR); 1504 tasklet_schedule(&host->tasklet); 1505 } 1506 if (pending & MCI_NOTBUSY) { 1507 mci_writel(host, IDR, 1508 ATMCI_DATA_ERROR_FLAGS | MCI_NOTBUSY); 1509 if (!host->data_status) 1510 host->data_status = status; 1511 smp_wmb(); 1512 atmci_set_pending(host, EVENT_DATA_COMPLETE); 1513 tasklet_schedule(&host->tasklet); 1514 } 1515 if (pending & MCI_RXRDY) 1516 atmci_read_data_pio(host); 1517 if (pending & MCI_TXRDY) 1518 atmci_write_data_pio(host); 1519 1520 if (pending & MCI_CMDRDY) 1521 atmci_cmd_interrupt(host, status); 1522 } while (pass_count++ < 5); 1523 1524 return pass_count ? IRQ_HANDLED : IRQ_NONE; 1525} 1526 1527static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id) 1528{ 1529 struct atmel_mci_slot *slot = dev_id; 1530 1531 /* 1532 * Disable interrupts until the pin has stabilized and check 1533 * the state then. Use mod_timer() since we may be in the 1534 * middle of the timer routine when this interrupt triggers. 1535 */ 1536 disable_irq_nosync(irq); 1537 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20)); 1538 1539 return IRQ_HANDLED; 1540} 1541 1542static int __init atmci_init_slot(struct atmel_mci *host, 1543 struct mci_slot_pdata *slot_data, unsigned int id, 1544 u32 sdc_reg) 1545{ 1546 struct mmc_host *mmc; 1547 struct atmel_mci_slot *slot; 1548 1549 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev); 1550 if (!mmc) 1551 return -ENOMEM; 1552 1553 slot = mmc_priv(mmc); 1554 slot->mmc = mmc; 1555 slot->host = host; 1556 slot->detect_pin = slot_data->detect_pin; 1557 slot->wp_pin = slot_data->wp_pin; 1558 slot->detect_is_active_high = slot_data->detect_is_active_high; 1559 slot->sdc_reg = sdc_reg; 1560 1561 mmc->ops = &atmci_ops; 1562 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512); 1563 mmc->f_max = host->bus_hz / 2; 1564 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1565 if (slot_data->bus_width >= 4) 1566 mmc->caps |= MMC_CAP_4_BIT_DATA; 1567 1568 mmc->max_hw_segs = 64; 1569 mmc->max_phys_segs = 64; 1570 mmc->max_req_size = 32768 * 512; 1571 mmc->max_blk_size = 32768; 1572 mmc->max_blk_count = 512; 1573 1574 /* Assume card is present initially */ 1575 set_bit(ATMCI_CARD_PRESENT, &slot->flags); 1576 if (gpio_is_valid(slot->detect_pin)) { 1577 if (gpio_request(slot->detect_pin, "mmc_detect")) { 1578 dev_dbg(&mmc->class_dev, "no detect pin available\n"); 1579 slot->detect_pin = -EBUSY; 1580 } else if (gpio_get_value(slot->detect_pin) ^ 1581 slot->detect_is_active_high) { 1582 clear_bit(ATMCI_CARD_PRESENT, &slot->flags); 1583 } 1584 } 1585 1586 if (!gpio_is_valid(slot->detect_pin)) 1587 mmc->caps |= MMC_CAP_NEEDS_POLL; 1588 1589 if (gpio_is_valid(slot->wp_pin)) { 1590 if (gpio_request(slot->wp_pin, "mmc_wp")) { 1591 dev_dbg(&mmc->class_dev, "no WP pin available\n"); 1592 slot->wp_pin = -EBUSY; 1593 } 1594 } 1595 1596 host->slot[id] = slot; 1597 mmc_add_host(mmc); 1598 1599 if (gpio_is_valid(slot->detect_pin)) { 1600 int ret; 1601 1602 setup_timer(&slot->detect_timer, atmci_detect_change, 1603 (unsigned long)slot); 1604 1605 ret = request_irq(gpio_to_irq(slot->detect_pin), 1606 atmci_detect_interrupt, 1607 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, 1608 "mmc-detect", slot); 1609 if (ret) { 1610 dev_dbg(&mmc->class_dev, 1611 "could not request IRQ %d for detect pin\n", 1612 gpio_to_irq(slot->detect_pin)); 1613 gpio_free(slot->detect_pin); 1614 slot->detect_pin = -EBUSY; 1615 } 1616 } 1617 1618 atmci_init_debugfs(slot); 1619 1620 return 0; 1621} 1622 1623static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot, 1624 unsigned int id) 1625{ 1626 /* Debugfs stuff is cleaned up by mmc core */ 1627 1628 set_bit(ATMCI_SHUTDOWN, &slot->flags); 1629 smp_wmb(); 1630 1631 mmc_remove_host(slot->mmc); 1632 1633 if (gpio_is_valid(slot->detect_pin)) { 1634 int pin = slot->detect_pin; 1635 1636 free_irq(gpio_to_irq(pin), slot); 1637 del_timer_sync(&slot->detect_timer); 1638 gpio_free(pin); 1639 } 1640 if (gpio_is_valid(slot->wp_pin)) 1641 gpio_free(slot->wp_pin); 1642 1643 slot->host->slot[id] = NULL; 1644 mmc_free_host(slot->mmc); 1645} 1646 1647#ifdef CONFIG_MMC_ATMELMCI_DMA 1648static bool filter(struct dma_chan *chan, void *slave) 1649{ 1650 struct mci_dma_data *sl = slave; 1651 1652 if (sl && find_slave_dev(sl) == chan->device->dev) { 1653 chan->private = slave_data_ptr(sl); 1654 return true; 1655 } else { 1656 return false; 1657 } 1658} 1659 1660static void atmci_configure_dma(struct atmel_mci *host) 1661{ 1662 struct mci_platform_data *pdata; 1663 1664 if (host == NULL) 1665 return; 1666 1667 pdata = host->pdev->dev.platform_data; 1668 1669 if (pdata && find_slave_dev(pdata->dma_slave)) { 1670 dma_cap_mask_t mask; 1671 1672 setup_dma_addr(pdata->dma_slave, 1673 host->mapbase + MCI_TDR, 1674 host->mapbase + MCI_RDR); 1675 1676 /* Try to grab a DMA channel */ 1677 dma_cap_zero(mask); 1678 dma_cap_set(DMA_SLAVE, mask); 1679 host->dma.chan = 1680 dma_request_channel(mask, filter, pdata->dma_slave); 1681 } 1682 if (!host->dma.chan) 1683 dev_notice(&host->pdev->dev, "DMA not available, using PIO\n"); 1684 else 1685 dev_info(&host->pdev->dev, 1686 "Using %s for DMA transfers\n", 1687 dma_chan_name(host->dma.chan)); 1688} 1689#else 1690static void atmci_configure_dma(struct atmel_mci *host) {} 1691#endif 1692 1693static int __init atmci_probe(struct platform_device *pdev) 1694{ 1695 struct mci_platform_data *pdata; 1696 struct atmel_mci *host; 1697 struct resource *regs; 1698 unsigned int nr_slots; 1699 int irq; 1700 int ret; 1701 1702 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1703 if (!regs) 1704 return -ENXIO; 1705 pdata = pdev->dev.platform_data; 1706 if (!pdata) 1707 return -ENXIO; 1708 irq = platform_get_irq(pdev, 0); 1709 if (irq < 0) 1710 return irq; 1711 1712 host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL); 1713 if (!host) 1714 return -ENOMEM; 1715 1716 host->pdev = pdev; 1717 spin_lock_init(&host->lock); 1718 INIT_LIST_HEAD(&host->queue); 1719 1720 host->mck = clk_get(&pdev->dev, "mci_clk"); 1721 if (IS_ERR(host->mck)) { 1722 ret = PTR_ERR(host->mck); 1723 goto err_clk_get; 1724 } 1725 1726 ret = -ENOMEM; 1727 host->regs = ioremap(regs->start, regs->end - regs->start + 1); 1728 if (!host->regs) 1729 goto err_ioremap; 1730 1731 clk_enable(host->mck); 1732 mci_writel(host, CR, MCI_CR_SWRST); 1733 host->bus_hz = clk_get_rate(host->mck); 1734 clk_disable(host->mck); 1735 1736 host->mapbase = regs->start; 1737 1738 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host); 1739 1740 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host); 1741 if (ret) 1742 goto err_request_irq; 1743 1744 atmci_configure_dma(host); 1745 1746 platform_set_drvdata(pdev, host); 1747 1748 /* We need at least one slot to succeed */ 1749 nr_slots = 0; 1750 ret = -ENODEV; 1751 if (pdata->slot[0].bus_width) { 1752 ret = atmci_init_slot(host, &pdata->slot[0], 1753 MCI_SDCSEL_SLOT_A, 0); 1754 if (!ret) 1755 nr_slots++; 1756 } 1757 if (pdata->slot[1].bus_width) { 1758 ret = atmci_init_slot(host, &pdata->slot[1], 1759 MCI_SDCSEL_SLOT_B, 1); 1760 if (!ret) 1761 nr_slots++; 1762 } 1763 1764 if (!nr_slots) { 1765 dev_err(&pdev->dev, "init failed: no slot defined\n"); 1766 goto err_init_slot; 1767 } 1768 1769 dev_info(&pdev->dev, 1770 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n", 1771 host->mapbase, irq, nr_slots); 1772 1773 return 0; 1774 1775err_init_slot: 1776#ifdef CONFIG_MMC_ATMELMCI_DMA 1777 if (host->dma.chan) 1778 dma_release_channel(host->dma.chan); 1779#endif 1780 free_irq(irq, host); 1781err_request_irq: 1782 iounmap(host->regs); 1783err_ioremap: 1784 clk_put(host->mck); 1785err_clk_get: 1786 kfree(host); 1787 return ret; 1788} 1789 1790static int __exit atmci_remove(struct platform_device *pdev) 1791{ 1792 struct atmel_mci *host = platform_get_drvdata(pdev); 1793 unsigned int i; 1794 1795 platform_set_drvdata(pdev, NULL); 1796 1797 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { 1798 if (host->slot[i]) 1799 atmci_cleanup_slot(host->slot[i], i); 1800 } 1801 1802 clk_enable(host->mck); 1803 mci_writel(host, IDR, ~0UL); 1804 mci_writel(host, CR, MCI_CR_MCIDIS); 1805 mci_readl(host, SR); 1806 clk_disable(host->mck); 1807 1808#ifdef CONFIG_MMC_ATMELMCI_DMA 1809 if (host->dma.chan) 1810 dma_release_channel(host->dma.chan); 1811#endif 1812 1813 free_irq(platform_get_irq(pdev, 0), host); 1814 iounmap(host->regs); 1815 1816 clk_put(host->mck); 1817 kfree(host); 1818 1819 return 0; 1820} 1821 1822static struct platform_driver atmci_driver = { 1823 .remove = __exit_p(atmci_remove), 1824 .driver = { 1825 .name = "atmel_mci", 1826 }, 1827}; 1828 1829static int __init atmci_init(void) 1830{ 1831 return platform_driver_probe(&atmci_driver, atmci_probe); 1832} 1833 1834static void __exit atmci_exit(void) 1835{ 1836 platform_driver_unregister(&atmci_driver); 1837} 1838 1839late_initcall(atmci_init); /* try to load after dma driver when built-in */ 1840module_exit(atmci_exit); 1841 1842MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver"); 1843MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>"); 1844MODULE_LICENSE("GPL v2"); 1845