dw_mmc.c revision 94dd5b3371c989b32685a00a54cba7bb530f864d
1/* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14#include <linux/blkdev.h> 15#include <linux/clk.h> 16#include <linux/debugfs.h> 17#include <linux/device.h> 18#include <linux/dma-mapping.h> 19#include <linux/err.h> 20#include <linux/init.h> 21#include <linux/interrupt.h> 22#include <linux/ioport.h> 23#include <linux/module.h> 24#include <linux/platform_device.h> 25#include <linux/scatterlist.h> 26#include <linux/seq_file.h> 27#include <linux/slab.h> 28#include <linux/stat.h> 29#include <linux/delay.h> 30#include <linux/irq.h> 31#include <linux/mmc/host.h> 32#include <linux/mmc/mmc.h> 33#include <linux/mmc/dw_mmc.h> 34#include <linux/bitops.h> 35#include <linux/regulator/consumer.h> 36#include <linux/workqueue.h> 37 38#include "dw_mmc.h" 39 40/* Common flag combinations */ 41#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \ 42 SDMMC_INT_HTO | SDMMC_INT_SBE | \ 43 SDMMC_INT_EBE) 44#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 45 SDMMC_INT_RESP_ERR) 46#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 47 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) 48#define DW_MCI_SEND_STATUS 1 49#define DW_MCI_RECV_STATUS 2 50#define DW_MCI_DMA_THRESHOLD 16 51 52#ifdef CONFIG_MMC_DW_IDMAC 53struct idmac_desc { 54 u32 des0; /* Control Descriptor */ 55#define IDMAC_DES0_DIC BIT(1) 56#define IDMAC_DES0_LD BIT(2) 57#define IDMAC_DES0_FD BIT(3) 58#define IDMAC_DES0_CH BIT(4) 59#define IDMAC_DES0_ER BIT(5) 60#define IDMAC_DES0_CES BIT(30) 61#define IDMAC_DES0_OWN BIT(31) 62 63 u32 des1; /* Buffer sizes */ 64#define IDMAC_SET_BUFFER1_SIZE(d, s) \ 65 ((d)->des1 = ((d)->des1 & 0x03ffc000) | ((s) & 0x3fff)) 66 67 u32 des2; /* buffer 1 physical address */ 68 69 u32 des3; /* buffer 2 physical address */ 70}; 71#endif /* CONFIG_MMC_DW_IDMAC */ 72 73/** 74 * struct dw_mci_slot - MMC slot state 75 * @mmc: The mmc_host representing this slot. 76 * @host: The MMC controller this slot is using. 77 * @ctype: Card type for this slot. 78 * @mrq: mmc_request currently being processed or waiting to be 79 * processed, or NULL when the slot is idle. 80 * @queue_node: List node for placing this node in the @queue list of 81 * &struct dw_mci. 82 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 83 * @flags: Random state bits associated with the slot. 84 * @id: Number of this slot. 85 * @last_detect_state: Most recently observed card detect state. 86 */ 87struct dw_mci_slot { 88 struct mmc_host *mmc; 89 struct dw_mci *host; 90 91 u32 ctype; 92 93 struct mmc_request *mrq; 94 struct list_head queue_node; 95 96 unsigned int clock; 97 unsigned long flags; 98#define DW_MMC_CARD_PRESENT 0 99#define DW_MMC_CARD_NEED_INIT 1 100 int id; 101 int last_detect_state; 102}; 103 104static struct workqueue_struct *dw_mci_card_workqueue; 105 106#if defined(CONFIG_DEBUG_FS) 107static int dw_mci_req_show(struct seq_file *s, void *v) 108{ 109 struct dw_mci_slot *slot = s->private; 110 struct mmc_request *mrq; 111 struct mmc_command *cmd; 112 struct mmc_command *stop; 113 struct mmc_data *data; 114 115 /* Make sure we get a consistent snapshot */ 116 spin_lock_bh(&slot->host->lock); 117 mrq = slot->mrq; 118 119 if (mrq) { 120 cmd = mrq->cmd; 121 data = mrq->data; 122 stop = mrq->stop; 123 124 if (cmd) 125 seq_printf(s, 126 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 127 cmd->opcode, cmd->arg, cmd->flags, 128 cmd->resp[0], cmd->resp[1], cmd->resp[2], 129 cmd->resp[2], cmd->error); 130 if (data) 131 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 132 data->bytes_xfered, data->blocks, 133 data->blksz, data->flags, data->error); 134 if (stop) 135 seq_printf(s, 136 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 137 stop->opcode, stop->arg, stop->flags, 138 stop->resp[0], stop->resp[1], stop->resp[2], 139 stop->resp[2], stop->error); 140 } 141 142 spin_unlock_bh(&slot->host->lock); 143 144 return 0; 145} 146 147static int dw_mci_req_open(struct inode *inode, struct file *file) 148{ 149 return single_open(file, dw_mci_req_show, inode->i_private); 150} 151 152static const struct file_operations dw_mci_req_fops = { 153 .owner = THIS_MODULE, 154 .open = dw_mci_req_open, 155 .read = seq_read, 156 .llseek = seq_lseek, 157 .release = single_release, 158}; 159 160static int dw_mci_regs_show(struct seq_file *s, void *v) 161{ 162 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); 163 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); 164 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); 165 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); 166 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); 167 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); 168 169 return 0; 170} 171 172static int dw_mci_regs_open(struct inode *inode, struct file *file) 173{ 174 return single_open(file, dw_mci_regs_show, inode->i_private); 175} 176 177static const struct file_operations dw_mci_regs_fops = { 178 .owner = THIS_MODULE, 179 .open = dw_mci_regs_open, 180 .read = seq_read, 181 .llseek = seq_lseek, 182 .release = single_release, 183}; 184 185static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 186{ 187 struct mmc_host *mmc = slot->mmc; 188 struct dw_mci *host = slot->host; 189 struct dentry *root; 190 struct dentry *node; 191 192 root = mmc->debugfs_root; 193 if (!root) 194 return; 195 196 node = debugfs_create_file("regs", S_IRUSR, root, host, 197 &dw_mci_regs_fops); 198 if (!node) 199 goto err; 200 201 node = debugfs_create_file("req", S_IRUSR, root, slot, 202 &dw_mci_req_fops); 203 if (!node) 204 goto err; 205 206 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); 207 if (!node) 208 goto err; 209 210 node = debugfs_create_x32("pending_events", S_IRUSR, root, 211 (u32 *)&host->pending_events); 212 if (!node) 213 goto err; 214 215 node = debugfs_create_x32("completed_events", S_IRUSR, root, 216 (u32 *)&host->completed_events); 217 if (!node) 218 goto err; 219 220 return; 221 222err: 223 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 224} 225#endif /* defined(CONFIG_DEBUG_FS) */ 226 227static void dw_mci_set_timeout(struct dw_mci *host) 228{ 229 /* timeout (maximum) */ 230 mci_writel(host, TMOUT, 0xffffffff); 231} 232 233static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 234{ 235 struct mmc_data *data; 236 u32 cmdr; 237 cmd->error = -EINPROGRESS; 238 239 cmdr = cmd->opcode; 240 241 if (cmdr == MMC_STOP_TRANSMISSION) 242 cmdr |= SDMMC_CMD_STOP; 243 else 244 cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 245 246 if (cmd->flags & MMC_RSP_PRESENT) { 247 /* We expect a response, so set this bit */ 248 cmdr |= SDMMC_CMD_RESP_EXP; 249 if (cmd->flags & MMC_RSP_136) 250 cmdr |= SDMMC_CMD_RESP_LONG; 251 } 252 253 if (cmd->flags & MMC_RSP_CRC) 254 cmdr |= SDMMC_CMD_RESP_CRC; 255 256 data = cmd->data; 257 if (data) { 258 cmdr |= SDMMC_CMD_DAT_EXP; 259 if (data->flags & MMC_DATA_STREAM) 260 cmdr |= SDMMC_CMD_STRM_MODE; 261 if (data->flags & MMC_DATA_WRITE) 262 cmdr |= SDMMC_CMD_DAT_WR; 263 } 264 265 return cmdr; 266} 267 268static void dw_mci_start_command(struct dw_mci *host, 269 struct mmc_command *cmd, u32 cmd_flags) 270{ 271 host->cmd = cmd; 272 dev_vdbg(&host->pdev->dev, 273 "start command: ARGR=0x%08x CMDR=0x%08x\n", 274 cmd->arg, cmd_flags); 275 276 mci_writel(host, CMDARG, cmd->arg); 277 wmb(); 278 279 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 280} 281 282static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data) 283{ 284 dw_mci_start_command(host, data->stop, host->stop_cmdr); 285} 286 287/* DMA interface functions */ 288static void dw_mci_stop_dma(struct dw_mci *host) 289{ 290 if (host->using_dma) { 291 host->dma_ops->stop(host); 292 host->dma_ops->cleanup(host); 293 } else { 294 /* Data transfer was stopped by the interrupt handler */ 295 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 296 } 297} 298 299#ifdef CONFIG_MMC_DW_IDMAC 300static void dw_mci_dma_cleanup(struct dw_mci *host) 301{ 302 struct mmc_data *data = host->data; 303 304 if (data) 305 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, 306 ((data->flags & MMC_DATA_WRITE) 307 ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); 308} 309 310static void dw_mci_idmac_stop_dma(struct dw_mci *host) 311{ 312 u32 temp; 313 314 /* Disable and reset the IDMAC interface */ 315 temp = mci_readl(host, CTRL); 316 temp &= ~SDMMC_CTRL_USE_IDMAC; 317 temp |= SDMMC_CTRL_DMA_RESET; 318 mci_writel(host, CTRL, temp); 319 320 /* Stop the IDMAC running */ 321 temp = mci_readl(host, BMOD); 322 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 323 mci_writel(host, BMOD, temp); 324} 325 326static void dw_mci_idmac_complete_dma(struct dw_mci *host) 327{ 328 struct mmc_data *data = host->data; 329 330 dev_vdbg(&host->pdev->dev, "DMA complete\n"); 331 332 host->dma_ops->cleanup(host); 333 334 /* 335 * If the card was removed, data will be NULL. No point in trying to 336 * send the stop command or waiting for NBUSY in this case. 337 */ 338 if (data) { 339 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 340 tasklet_schedule(&host->tasklet); 341 } 342} 343 344static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, 345 unsigned int sg_len) 346{ 347 int i; 348 struct idmac_desc *desc = host->sg_cpu; 349 350 for (i = 0; i < sg_len; i++, desc++) { 351 unsigned int length = sg_dma_len(&data->sg[i]); 352 u32 mem_addr = sg_dma_address(&data->sg[i]); 353 354 /* Set the OWN bit and disable interrupts for this descriptor */ 355 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH; 356 357 /* Buffer length */ 358 IDMAC_SET_BUFFER1_SIZE(desc, length); 359 360 /* Physical address to DMA to/from */ 361 desc->des2 = mem_addr; 362 } 363 364 /* Set first descriptor */ 365 desc = host->sg_cpu; 366 desc->des0 |= IDMAC_DES0_FD; 367 368 /* Set last descriptor */ 369 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc); 370 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 371 desc->des0 |= IDMAC_DES0_LD; 372 373 wmb(); 374} 375 376static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 377{ 378 u32 temp; 379 380 dw_mci_translate_sglist(host, host->data, sg_len); 381 382 /* Select IDMAC interface */ 383 temp = mci_readl(host, CTRL); 384 temp |= SDMMC_CTRL_USE_IDMAC; 385 mci_writel(host, CTRL, temp); 386 387 wmb(); 388 389 /* Enable the IDMAC */ 390 temp = mci_readl(host, BMOD); 391 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 392 mci_writel(host, BMOD, temp); 393 394 /* Start it running */ 395 mci_writel(host, PLDMND, 1); 396} 397 398static int dw_mci_idmac_init(struct dw_mci *host) 399{ 400 struct idmac_desc *p; 401 int i; 402 403 /* Number of descriptors in the ring buffer */ 404 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); 405 406 /* Forward link the descriptor list */ 407 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) 408 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1)); 409 410 /* Set the last descriptor as the end-of-ring descriptor */ 411 p->des3 = host->sg_dma; 412 p->des0 = IDMAC_DES0_ER; 413 414 /* Mask out interrupts - get Tx & Rx complete only */ 415 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI | 416 SDMMC_IDMAC_INT_TI); 417 418 /* Set the descriptor base address */ 419 mci_writel(host, DBADDR, host->sg_dma); 420 return 0; 421} 422 423static struct dw_mci_dma_ops dw_mci_idmac_ops = { 424 .init = dw_mci_idmac_init, 425 .start = dw_mci_idmac_start_dma, 426 .stop = dw_mci_idmac_stop_dma, 427 .complete = dw_mci_idmac_complete_dma, 428 .cleanup = dw_mci_dma_cleanup, 429}; 430#endif /* CONFIG_MMC_DW_IDMAC */ 431 432static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 433{ 434 struct scatterlist *sg; 435 unsigned int i, direction, sg_len; 436 u32 temp; 437 438 host->using_dma = 0; 439 440 /* If we don't have a channel, we can't do DMA */ 441 if (!host->use_dma) 442 return -ENODEV; 443 444 /* 445 * We don't do DMA on "complex" transfers, i.e. with 446 * non-word-aligned buffers or lengths. Also, we don't bother 447 * with all the DMA setup overhead for short transfers. 448 */ 449 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 450 return -EINVAL; 451 if (data->blksz & 3) 452 return -EINVAL; 453 454 for_each_sg(data->sg, sg, data->sg_len, i) { 455 if (sg->offset & 3 || sg->length & 3) 456 return -EINVAL; 457 } 458 459 host->using_dma = 1; 460 461 if (data->flags & MMC_DATA_READ) 462 direction = DMA_FROM_DEVICE; 463 else 464 direction = DMA_TO_DEVICE; 465 466 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, 467 direction); 468 469 dev_vdbg(&host->pdev->dev, 470 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 471 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma, 472 sg_len); 473 474 /* Enable the DMA interface */ 475 temp = mci_readl(host, CTRL); 476 temp |= SDMMC_CTRL_DMA_ENABLE; 477 mci_writel(host, CTRL, temp); 478 479 /* Disable RX/TX IRQs, let DMA handle it */ 480 temp = mci_readl(host, INTMASK); 481 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 482 mci_writel(host, INTMASK, temp); 483 484 host->dma_ops->start(host, sg_len); 485 486 return 0; 487} 488 489static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 490{ 491 u32 temp; 492 493 data->error = -EINPROGRESS; 494 495 WARN_ON(host->data); 496 host->sg = NULL; 497 host->data = data; 498 499 if (data->flags & MMC_DATA_READ) 500 host->dir_status = DW_MCI_RECV_STATUS; 501 else 502 host->dir_status = DW_MCI_SEND_STATUS; 503 504 if (dw_mci_submit_data_dma(host, data)) { 505 host->sg = data->sg; 506 host->pio_offset = 0; 507 host->part_buf_start = 0; 508 host->part_buf_count = 0; 509 510 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 511 temp = mci_readl(host, INTMASK); 512 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 513 mci_writel(host, INTMASK, temp); 514 515 temp = mci_readl(host, CTRL); 516 temp &= ~SDMMC_CTRL_DMA_ENABLE; 517 mci_writel(host, CTRL, temp); 518 } 519} 520 521static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 522{ 523 struct dw_mci *host = slot->host; 524 unsigned long timeout = jiffies + msecs_to_jiffies(500); 525 unsigned int cmd_status = 0; 526 527 mci_writel(host, CMDARG, arg); 528 wmb(); 529 mci_writel(host, CMD, SDMMC_CMD_START | cmd); 530 531 while (time_before(jiffies, timeout)) { 532 cmd_status = mci_readl(host, CMD); 533 if (!(cmd_status & SDMMC_CMD_START)) 534 return; 535 } 536 dev_err(&slot->mmc->class_dev, 537 "Timeout sending command (cmd %#x arg %#x status %#x)\n", 538 cmd, arg, cmd_status); 539} 540 541static void dw_mci_setup_bus(struct dw_mci_slot *slot) 542{ 543 struct dw_mci *host = slot->host; 544 u32 div; 545 546 if (slot->clock != host->current_speed) { 547 if (host->bus_hz % slot->clock) 548 /* 549 * move the + 1 after the divide to prevent 550 * over-clocking the card. 551 */ 552 div = ((host->bus_hz / slot->clock) >> 1) + 1; 553 else 554 div = (host->bus_hz / slot->clock) >> 1; 555 556 dev_info(&slot->mmc->class_dev, 557 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ" 558 " div = %d)\n", slot->id, host->bus_hz, slot->clock, 559 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div); 560 561 /* disable clock */ 562 mci_writel(host, CLKENA, 0); 563 mci_writel(host, CLKSRC, 0); 564 565 /* inform CIU */ 566 mci_send_cmd(slot, 567 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); 568 569 /* set clock to desired speed */ 570 mci_writel(host, CLKDIV, div); 571 572 /* inform CIU */ 573 mci_send_cmd(slot, 574 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); 575 576 /* enable clock */ 577 mci_writel(host, CLKENA, SDMMC_CLKEN_ENABLE | 578 SDMMC_CLKEN_LOW_PWR); 579 580 /* inform CIU */ 581 mci_send_cmd(slot, 582 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); 583 584 host->current_speed = slot->clock; 585 } 586 587 /* Set the current slot bus width */ 588 mci_writel(host, CTYPE, (slot->ctype << slot->id)); 589} 590 591static void dw_mci_start_request(struct dw_mci *host, 592 struct dw_mci_slot *slot) 593{ 594 struct mmc_request *mrq; 595 struct mmc_command *cmd; 596 struct mmc_data *data; 597 u32 cmdflags; 598 599 mrq = slot->mrq; 600 if (host->pdata->select_slot) 601 host->pdata->select_slot(slot->id); 602 603 /* Slot specific timing and width adjustment */ 604 dw_mci_setup_bus(slot); 605 606 host->cur_slot = slot; 607 host->mrq = mrq; 608 609 host->pending_events = 0; 610 host->completed_events = 0; 611 host->data_status = 0; 612 613 data = mrq->data; 614 if (data) { 615 dw_mci_set_timeout(host); 616 mci_writel(host, BYTCNT, data->blksz*data->blocks); 617 mci_writel(host, BLKSIZ, data->blksz); 618 } 619 620 cmd = mrq->cmd; 621 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 622 623 /* this is the first command, send the initialization clock */ 624 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 625 cmdflags |= SDMMC_CMD_INIT; 626 627 if (data) { 628 dw_mci_submit_data(host, data); 629 wmb(); 630 } 631 632 dw_mci_start_command(host, cmd, cmdflags); 633 634 if (mrq->stop) 635 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); 636} 637 638/* must be called with host->lock held */ 639static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 640 struct mmc_request *mrq) 641{ 642 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 643 host->state); 644 645 slot->mrq = mrq; 646 647 if (host->state == STATE_IDLE) { 648 host->state = STATE_SENDING_CMD; 649 dw_mci_start_request(host, slot); 650 } else { 651 list_add_tail(&slot->queue_node, &host->queue); 652 } 653} 654 655static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 656{ 657 struct dw_mci_slot *slot = mmc_priv(mmc); 658 struct dw_mci *host = slot->host; 659 660 WARN_ON(slot->mrq); 661 662 /* 663 * The check for card presence and queueing of the request must be 664 * atomic, otherwise the card could be removed in between and the 665 * request wouldn't fail until another card was inserted. 666 */ 667 spin_lock_bh(&host->lock); 668 669 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 670 spin_unlock_bh(&host->lock); 671 mrq->cmd->error = -ENOMEDIUM; 672 mmc_request_done(mmc, mrq); 673 return; 674 } 675 676 dw_mci_queue_request(host, slot, mrq); 677 678 spin_unlock_bh(&host->lock); 679} 680 681static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 682{ 683 struct dw_mci_slot *slot = mmc_priv(mmc); 684 u32 regs; 685 686 /* set default 1 bit mode */ 687 slot->ctype = SDMMC_CTYPE_1BIT; 688 689 switch (ios->bus_width) { 690 case MMC_BUS_WIDTH_1: 691 slot->ctype = SDMMC_CTYPE_1BIT; 692 break; 693 case MMC_BUS_WIDTH_4: 694 slot->ctype = SDMMC_CTYPE_4BIT; 695 break; 696 case MMC_BUS_WIDTH_8: 697 slot->ctype = SDMMC_CTYPE_8BIT; 698 break; 699 } 700 701 /* DDR mode set */ 702 if (ios->ddr) { 703 regs = mci_readl(slot->host, UHS_REG); 704 regs |= (0x1 << slot->id) << 16; 705 mci_writel(slot->host, UHS_REG, regs); 706 } 707 708 if (ios->clock) { 709 /* 710 * Use mirror of ios->clock to prevent race with mmc 711 * core ios update when finding the minimum. 712 */ 713 slot->clock = ios->clock; 714 } 715 716 switch (ios->power_mode) { 717 case MMC_POWER_UP: 718 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 719 break; 720 default: 721 break; 722 } 723} 724 725static int dw_mci_get_ro(struct mmc_host *mmc) 726{ 727 int read_only; 728 struct dw_mci_slot *slot = mmc_priv(mmc); 729 struct dw_mci_board *brd = slot->host->pdata; 730 731 /* Use platform get_ro function, else try on board write protect */ 732 if (brd->get_ro) 733 read_only = brd->get_ro(slot->id); 734 else 735 read_only = 736 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 737 738 dev_dbg(&mmc->class_dev, "card is %s\n", 739 read_only ? "read-only" : "read-write"); 740 741 return read_only; 742} 743 744static int dw_mci_get_cd(struct mmc_host *mmc) 745{ 746 int present; 747 struct dw_mci_slot *slot = mmc_priv(mmc); 748 struct dw_mci_board *brd = slot->host->pdata; 749 750 /* Use platform get_cd function, else try onboard card detect */ 751 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) 752 present = 1; 753 else if (brd->get_cd) 754 present = !brd->get_cd(slot->id); 755 else 756 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 757 == 0 ? 1 : 0; 758 759 if (present) 760 dev_dbg(&mmc->class_dev, "card is present\n"); 761 else 762 dev_dbg(&mmc->class_dev, "card is not present\n"); 763 764 return present; 765} 766 767static const struct mmc_host_ops dw_mci_ops = { 768 .request = dw_mci_request, 769 .set_ios = dw_mci_set_ios, 770 .get_ro = dw_mci_get_ro, 771 .get_cd = dw_mci_get_cd, 772}; 773 774static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 775 __releases(&host->lock) 776 __acquires(&host->lock) 777{ 778 struct dw_mci_slot *slot; 779 struct mmc_host *prev_mmc = host->cur_slot->mmc; 780 781 WARN_ON(host->cmd || host->data); 782 783 host->cur_slot->mrq = NULL; 784 host->mrq = NULL; 785 if (!list_empty(&host->queue)) { 786 slot = list_entry(host->queue.next, 787 struct dw_mci_slot, queue_node); 788 list_del(&slot->queue_node); 789 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n", 790 mmc_hostname(slot->mmc)); 791 host->state = STATE_SENDING_CMD; 792 dw_mci_start_request(host, slot); 793 } else { 794 dev_vdbg(&host->pdev->dev, "list empty\n"); 795 host->state = STATE_IDLE; 796 } 797 798 spin_unlock(&host->lock); 799 mmc_request_done(prev_mmc, mrq); 800 spin_lock(&host->lock); 801} 802 803static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 804{ 805 u32 status = host->cmd_status; 806 807 host->cmd_status = 0; 808 809 /* Read the response from the card (up to 16 bytes) */ 810 if (cmd->flags & MMC_RSP_PRESENT) { 811 if (cmd->flags & MMC_RSP_136) { 812 cmd->resp[3] = mci_readl(host, RESP0); 813 cmd->resp[2] = mci_readl(host, RESP1); 814 cmd->resp[1] = mci_readl(host, RESP2); 815 cmd->resp[0] = mci_readl(host, RESP3); 816 } else { 817 cmd->resp[0] = mci_readl(host, RESP0); 818 cmd->resp[1] = 0; 819 cmd->resp[2] = 0; 820 cmd->resp[3] = 0; 821 } 822 } 823 824 if (status & SDMMC_INT_RTO) 825 cmd->error = -ETIMEDOUT; 826 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 827 cmd->error = -EILSEQ; 828 else if (status & SDMMC_INT_RESP_ERR) 829 cmd->error = -EIO; 830 else 831 cmd->error = 0; 832 833 if (cmd->error) { 834 /* newer ip versions need a delay between retries */ 835 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY) 836 mdelay(20); 837 838 if (cmd->data) { 839 host->data = NULL; 840 dw_mci_stop_dma(host); 841 } 842 } 843} 844 845static void dw_mci_tasklet_func(unsigned long priv) 846{ 847 struct dw_mci *host = (struct dw_mci *)priv; 848 struct mmc_data *data; 849 struct mmc_command *cmd; 850 enum dw_mci_state state; 851 enum dw_mci_state prev_state; 852 u32 status, ctrl; 853 854 spin_lock(&host->lock); 855 856 state = host->state; 857 data = host->data; 858 859 do { 860 prev_state = state; 861 862 switch (state) { 863 case STATE_IDLE: 864 break; 865 866 case STATE_SENDING_CMD: 867 if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 868 &host->pending_events)) 869 break; 870 871 cmd = host->cmd; 872 host->cmd = NULL; 873 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 874 dw_mci_command_complete(host, host->mrq->cmd); 875 if (!host->mrq->data || cmd->error) { 876 dw_mci_request_end(host, host->mrq); 877 goto unlock; 878 } 879 880 prev_state = state = STATE_SENDING_DATA; 881 /* fall through */ 882 883 case STATE_SENDING_DATA: 884 if (test_and_clear_bit(EVENT_DATA_ERROR, 885 &host->pending_events)) { 886 dw_mci_stop_dma(host); 887 if (data->stop) 888 send_stop_cmd(host, data); 889 state = STATE_DATA_ERROR; 890 break; 891 } 892 893 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 894 &host->pending_events)) 895 break; 896 897 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 898 prev_state = state = STATE_DATA_BUSY; 899 /* fall through */ 900 901 case STATE_DATA_BUSY: 902 if (!test_and_clear_bit(EVENT_DATA_COMPLETE, 903 &host->pending_events)) 904 break; 905 906 host->data = NULL; 907 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 908 status = host->data_status; 909 910 if (status & DW_MCI_DATA_ERROR_FLAGS) { 911 if (status & SDMMC_INT_DTO) { 912 data->error = -ETIMEDOUT; 913 } else if (status & SDMMC_INT_DCRC) { 914 data->error = -EILSEQ; 915 } else if (status & SDMMC_INT_EBE && 916 host->dir_status == 917 DW_MCI_SEND_STATUS) { 918 /* 919 * No data CRC status was returned. 920 * The number of bytes transferred will 921 * be exaggerated in PIO mode. 922 */ 923 data->bytes_xfered = 0; 924 data->error = -ETIMEDOUT; 925 } else { 926 dev_err(&host->pdev->dev, 927 "data FIFO error " 928 "(status=%08x)\n", 929 status); 930 data->error = -EIO; 931 } 932 /* 933 * After an error, there may be data lingering 934 * in the FIFO, so reset it - doing so 935 * generates a block interrupt, hence setting 936 * the scatter-gather pointer to NULL. 937 */ 938 host->sg = NULL; 939 ctrl = mci_readl(host, CTRL); 940 ctrl |= SDMMC_CTRL_FIFO_RESET; 941 mci_writel(host, CTRL, ctrl); 942 } else { 943 data->bytes_xfered = data->blocks * data->blksz; 944 data->error = 0; 945 } 946 947 if (!data->stop) { 948 dw_mci_request_end(host, host->mrq); 949 goto unlock; 950 } 951 952 prev_state = state = STATE_SENDING_STOP; 953 if (!data->error) 954 send_stop_cmd(host, data); 955 /* fall through */ 956 957 case STATE_SENDING_STOP: 958 if (!test_and_clear_bit(EVENT_CMD_COMPLETE, 959 &host->pending_events)) 960 break; 961 962 host->cmd = NULL; 963 dw_mci_command_complete(host, host->mrq->stop); 964 dw_mci_request_end(host, host->mrq); 965 goto unlock; 966 967 case STATE_DATA_ERROR: 968 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 969 &host->pending_events)) 970 break; 971 972 state = STATE_DATA_BUSY; 973 break; 974 } 975 } while (state != prev_state); 976 977 host->state = state; 978unlock: 979 spin_unlock(&host->lock); 980 981} 982 983/* push final bytes to part_buf, only use during push */ 984static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 985{ 986 memcpy((void *)&host->part_buf, buf, cnt); 987 host->part_buf_count = cnt; 988} 989 990/* append bytes to part_buf, only use during push */ 991static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 992{ 993 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 994 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 995 host->part_buf_count += cnt; 996 return cnt; 997} 998 999/* pull first bytes from part_buf, only use during pull */ 1000static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 1001{ 1002 cnt = min(cnt, (int)host->part_buf_count); 1003 if (cnt) { 1004 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 1005 cnt); 1006 host->part_buf_count -= cnt; 1007 host->part_buf_start += cnt; 1008 } 1009 return cnt; 1010} 1011 1012/* pull final bytes from the part_buf, assuming it's just been filled */ 1013static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 1014{ 1015 memcpy(buf, &host->part_buf, cnt); 1016 host->part_buf_start = cnt; 1017 host->part_buf_count = (1 << host->data_shift) - cnt; 1018} 1019 1020static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 1021{ 1022 /* try and push anything in the part_buf */ 1023 if (unlikely(host->part_buf_count)) { 1024 int len = dw_mci_push_part_bytes(host, buf, cnt); 1025 buf += len; 1026 cnt -= len; 1027 if (!sg_next(host->sg) || host->part_buf_count == 2) { 1028 mci_writew(host, DATA, host->part_buf16); 1029 host->part_buf_count = 0; 1030 } 1031 } 1032#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1033 if (unlikely((unsigned long)buf & 0x1)) { 1034 while (cnt >= 2) { 1035 u16 aligned_buf[64]; 1036 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 1037 int items = len >> 1; 1038 int i; 1039 /* memcpy from input buffer into aligned buffer */ 1040 memcpy(aligned_buf, buf, len); 1041 buf += len; 1042 cnt -= len; 1043 /* push data from aligned buffer into fifo */ 1044 for (i = 0; i < items; ++i) 1045 mci_writew(host, DATA, aligned_buf[i]); 1046 } 1047 } else 1048#endif 1049 { 1050 u16 *pdata = buf; 1051 for (; cnt >= 2; cnt -= 2) 1052 mci_writew(host, DATA, *pdata++); 1053 buf = pdata; 1054 } 1055 /* put anything remaining in the part_buf */ 1056 if (cnt) { 1057 dw_mci_set_part_bytes(host, buf, cnt); 1058 if (!sg_next(host->sg)) 1059 mci_writew(host, DATA, host->part_buf16); 1060 } 1061} 1062 1063static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 1064{ 1065#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1066 if (unlikely((unsigned long)buf & 0x1)) { 1067 while (cnt >= 2) { 1068 /* pull data from fifo into aligned buffer */ 1069 u16 aligned_buf[64]; 1070 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 1071 int items = len >> 1; 1072 int i; 1073 for (i = 0; i < items; ++i) 1074 aligned_buf[i] = mci_readw(host, DATA); 1075 /* memcpy from aligned buffer into output buffer */ 1076 memcpy(buf, aligned_buf, len); 1077 buf += len; 1078 cnt -= len; 1079 } 1080 } else 1081#endif 1082 { 1083 u16 *pdata = buf; 1084 for (; cnt >= 2; cnt -= 2) 1085 *pdata++ = mci_readw(host, DATA); 1086 buf = pdata; 1087 } 1088 if (cnt) { 1089 host->part_buf16 = mci_readw(host, DATA); 1090 dw_mci_pull_final_bytes(host, buf, cnt); 1091 } 1092} 1093 1094static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 1095{ 1096 /* try and push anything in the part_buf */ 1097 if (unlikely(host->part_buf_count)) { 1098 int len = dw_mci_push_part_bytes(host, buf, cnt); 1099 buf += len; 1100 cnt -= len; 1101 if (!sg_next(host->sg) || host->part_buf_count == 4) { 1102 mci_writel(host, DATA, host->part_buf32); 1103 host->part_buf_count = 0; 1104 } 1105 } 1106#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1107 if (unlikely((unsigned long)buf & 0x3)) { 1108 while (cnt >= 4) { 1109 u32 aligned_buf[32]; 1110 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 1111 int items = len >> 2; 1112 int i; 1113 /* memcpy from input buffer into aligned buffer */ 1114 memcpy(aligned_buf, buf, len); 1115 buf += len; 1116 cnt -= len; 1117 /* push data from aligned buffer into fifo */ 1118 for (i = 0; i < items; ++i) 1119 mci_writel(host, DATA, aligned_buf[i]); 1120 } 1121 } else 1122#endif 1123 { 1124 u32 *pdata = buf; 1125 for (; cnt >= 4; cnt -= 4) 1126 mci_writel(host, DATA, *pdata++); 1127 buf = pdata; 1128 } 1129 /* put anything remaining in the part_buf */ 1130 if (cnt) { 1131 dw_mci_set_part_bytes(host, buf, cnt); 1132 if (!sg_next(host->sg)) 1133 mci_writel(host, DATA, host->part_buf32); 1134 } 1135} 1136 1137static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 1138{ 1139#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1140 if (unlikely((unsigned long)buf & 0x3)) { 1141 while (cnt >= 4) { 1142 /* pull data from fifo into aligned buffer */ 1143 u32 aligned_buf[32]; 1144 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 1145 int items = len >> 2; 1146 int i; 1147 for (i = 0; i < items; ++i) 1148 aligned_buf[i] = mci_readl(host, DATA); 1149 /* memcpy from aligned buffer into output buffer */ 1150 memcpy(buf, aligned_buf, len); 1151 buf += len; 1152 cnt -= len; 1153 } 1154 } else 1155#endif 1156 { 1157 u32 *pdata = buf; 1158 for (; cnt >= 4; cnt -= 4) 1159 *pdata++ = mci_readl(host, DATA); 1160 buf = pdata; 1161 } 1162 if (cnt) { 1163 host->part_buf32 = mci_readl(host, DATA); 1164 dw_mci_pull_final_bytes(host, buf, cnt); 1165 } 1166} 1167 1168static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 1169{ 1170 /* try and push anything in the part_buf */ 1171 if (unlikely(host->part_buf_count)) { 1172 int len = dw_mci_push_part_bytes(host, buf, cnt); 1173 buf += len; 1174 cnt -= len; 1175 if (!sg_next(host->sg) || host->part_buf_count == 8) { 1176 mci_writew(host, DATA, host->part_buf); 1177 host->part_buf_count = 0; 1178 } 1179 } 1180#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1181 if (unlikely((unsigned long)buf & 0x7)) { 1182 while (cnt >= 8) { 1183 u64 aligned_buf[16]; 1184 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 1185 int items = len >> 3; 1186 int i; 1187 /* memcpy from input buffer into aligned buffer */ 1188 memcpy(aligned_buf, buf, len); 1189 buf += len; 1190 cnt -= len; 1191 /* push data from aligned buffer into fifo */ 1192 for (i = 0; i < items; ++i) 1193 mci_writeq(host, DATA, aligned_buf[i]); 1194 } 1195 } else 1196#endif 1197 { 1198 u64 *pdata = buf; 1199 for (; cnt >= 8; cnt -= 8) 1200 mci_writeq(host, DATA, *pdata++); 1201 buf = pdata; 1202 } 1203 /* put anything remaining in the part_buf */ 1204 if (cnt) { 1205 dw_mci_set_part_bytes(host, buf, cnt); 1206 if (!sg_next(host->sg)) 1207 mci_writeq(host, DATA, host->part_buf); 1208 } 1209} 1210 1211static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 1212{ 1213#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1214 if (unlikely((unsigned long)buf & 0x7)) { 1215 while (cnt >= 8) { 1216 /* pull data from fifo into aligned buffer */ 1217 u64 aligned_buf[16]; 1218 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 1219 int items = len >> 3; 1220 int i; 1221 for (i = 0; i < items; ++i) 1222 aligned_buf[i] = mci_readq(host, DATA); 1223 /* memcpy from aligned buffer into output buffer */ 1224 memcpy(buf, aligned_buf, len); 1225 buf += len; 1226 cnt -= len; 1227 } 1228 } else 1229#endif 1230 { 1231 u64 *pdata = buf; 1232 for (; cnt >= 8; cnt -= 8) 1233 *pdata++ = mci_readq(host, DATA); 1234 buf = pdata; 1235 } 1236 if (cnt) { 1237 host->part_buf = mci_readq(host, DATA); 1238 dw_mci_pull_final_bytes(host, buf, cnt); 1239 } 1240} 1241 1242static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 1243{ 1244 int len; 1245 1246 /* get remaining partial bytes */ 1247 len = dw_mci_pull_part_bytes(host, buf, cnt); 1248 if (unlikely(len == cnt)) 1249 return; 1250 buf += len; 1251 cnt -= len; 1252 1253 /* get the rest of the data */ 1254 host->pull_data(host, buf, cnt); 1255} 1256 1257static void dw_mci_read_data_pio(struct dw_mci *host) 1258{ 1259 struct scatterlist *sg = host->sg; 1260 void *buf = sg_virt(sg); 1261 unsigned int offset = host->pio_offset; 1262 struct mmc_data *data = host->data; 1263 int shift = host->data_shift; 1264 u32 status; 1265 unsigned int nbytes = 0, len; 1266 1267 do { 1268 len = host->part_buf_count + 1269 (SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift); 1270 if (offset + len <= sg->length) { 1271 dw_mci_pull_data(host, (void *)(buf + offset), len); 1272 1273 offset += len; 1274 nbytes += len; 1275 1276 if (offset == sg->length) { 1277 flush_dcache_page(sg_page(sg)); 1278 host->sg = sg = sg_next(sg); 1279 if (!sg) 1280 goto done; 1281 1282 offset = 0; 1283 buf = sg_virt(sg); 1284 } 1285 } else { 1286 unsigned int remaining = sg->length - offset; 1287 dw_mci_pull_data(host, (void *)(buf + offset), 1288 remaining); 1289 nbytes += remaining; 1290 1291 flush_dcache_page(sg_page(sg)); 1292 host->sg = sg = sg_next(sg); 1293 if (!sg) 1294 goto done; 1295 1296 offset = len - remaining; 1297 buf = sg_virt(sg); 1298 dw_mci_pull_data(host, buf, offset); 1299 nbytes += offset; 1300 } 1301 1302 status = mci_readl(host, MINTSTS); 1303 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 1304 if (status & DW_MCI_DATA_ERROR_FLAGS) { 1305 host->data_status = status; 1306 data->bytes_xfered += nbytes; 1307 smp_wmb(); 1308 1309 set_bit(EVENT_DATA_ERROR, &host->pending_events); 1310 1311 tasklet_schedule(&host->tasklet); 1312 return; 1313 } 1314 } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/ 1315 host->pio_offset = offset; 1316 data->bytes_xfered += nbytes; 1317 return; 1318 1319done: 1320 data->bytes_xfered += nbytes; 1321 smp_wmb(); 1322 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 1323} 1324 1325static void dw_mci_write_data_pio(struct dw_mci *host) 1326{ 1327 struct scatterlist *sg = host->sg; 1328 void *buf = sg_virt(sg); 1329 unsigned int offset = host->pio_offset; 1330 struct mmc_data *data = host->data; 1331 int shift = host->data_shift; 1332 u32 status; 1333 unsigned int nbytes = 0, len; 1334 1335 do { 1336 len = ((host->fifo_depth - 1337 SDMMC_GET_FCNT(mci_readl(host, STATUS))) << shift) 1338 - host->part_buf_count; 1339 if (offset + len <= sg->length) { 1340 host->push_data(host, (void *)(buf + offset), len); 1341 1342 offset += len; 1343 nbytes += len; 1344 if (offset == sg->length) { 1345 host->sg = sg = sg_next(sg); 1346 if (!sg) 1347 goto done; 1348 1349 offset = 0; 1350 buf = sg_virt(sg); 1351 } 1352 } else { 1353 unsigned int remaining = sg->length - offset; 1354 1355 host->push_data(host, (void *)(buf + offset), 1356 remaining); 1357 nbytes += remaining; 1358 1359 host->sg = sg = sg_next(sg); 1360 if (!sg) 1361 goto done; 1362 1363 offset = len - remaining; 1364 buf = sg_virt(sg); 1365 host->push_data(host, (void *)buf, offset); 1366 nbytes += offset; 1367 } 1368 1369 status = mci_readl(host, MINTSTS); 1370 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 1371 if (status & DW_MCI_DATA_ERROR_FLAGS) { 1372 host->data_status = status; 1373 data->bytes_xfered += nbytes; 1374 1375 smp_wmb(); 1376 1377 set_bit(EVENT_DATA_ERROR, &host->pending_events); 1378 1379 tasklet_schedule(&host->tasklet); 1380 return; 1381 } 1382 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 1383 host->pio_offset = offset; 1384 data->bytes_xfered += nbytes; 1385 return; 1386 1387done: 1388 data->bytes_xfered += nbytes; 1389 smp_wmb(); 1390 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 1391} 1392 1393static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 1394{ 1395 if (!host->cmd_status) 1396 host->cmd_status = status; 1397 1398 smp_wmb(); 1399 1400 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 1401 tasklet_schedule(&host->tasklet); 1402} 1403 1404static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 1405{ 1406 struct dw_mci *host = dev_id; 1407 u32 status, pending; 1408 unsigned int pass_count = 0; 1409 1410 do { 1411 status = mci_readl(host, RINTSTS); 1412 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 1413 1414 /* 1415 * DTO fix - version 2.10a and below, and only if internal DMA 1416 * is configured. 1417 */ 1418 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) { 1419 if (!pending && 1420 ((mci_readl(host, STATUS) >> 17) & 0x1fff)) 1421 pending |= SDMMC_INT_DATA_OVER; 1422 } 1423 1424 if (!pending) 1425 break; 1426 1427 if (pending & DW_MCI_CMD_ERROR_FLAGS) { 1428 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 1429 host->cmd_status = status; 1430 smp_wmb(); 1431 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 1432 } 1433 1434 if (pending & DW_MCI_DATA_ERROR_FLAGS) { 1435 /* if there is an error report DATA_ERROR */ 1436 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 1437 host->data_status = status; 1438 smp_wmb(); 1439 set_bit(EVENT_DATA_ERROR, &host->pending_events); 1440 if (!(pending & (SDMMC_INT_DTO | SDMMC_INT_DCRC | 1441 SDMMC_INT_SBE | SDMMC_INT_EBE))) 1442 tasklet_schedule(&host->tasklet); 1443 } 1444 1445 if (pending & SDMMC_INT_DATA_OVER) { 1446 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 1447 if (!host->data_status) 1448 host->data_status = status; 1449 smp_wmb(); 1450 if (host->dir_status == DW_MCI_RECV_STATUS) { 1451 if (host->sg != NULL) 1452 dw_mci_read_data_pio(host); 1453 } 1454 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 1455 tasklet_schedule(&host->tasklet); 1456 } 1457 1458 if (pending & SDMMC_INT_RXDR) { 1459 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 1460 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 1461 dw_mci_read_data_pio(host); 1462 } 1463 1464 if (pending & SDMMC_INT_TXDR) { 1465 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 1466 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 1467 dw_mci_write_data_pio(host); 1468 } 1469 1470 if (pending & SDMMC_INT_CMD_DONE) { 1471 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 1472 dw_mci_cmd_interrupt(host, status); 1473 } 1474 1475 if (pending & SDMMC_INT_CD) { 1476 mci_writel(host, RINTSTS, SDMMC_INT_CD); 1477 queue_work(dw_mci_card_workqueue, &host->card_work); 1478 } 1479 1480 } while (pass_count++ < 5); 1481 1482#ifdef CONFIG_MMC_DW_IDMAC 1483 /* Handle DMA interrupts */ 1484 pending = mci_readl(host, IDSTS); 1485 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 1486 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI); 1487 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 1488 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 1489 host->dma_ops->complete(host); 1490 } 1491#endif 1492 1493 return IRQ_HANDLED; 1494} 1495 1496static void dw_mci_work_routine_card(struct work_struct *work) 1497{ 1498 struct dw_mci *host = container_of(work, struct dw_mci, card_work); 1499 int i; 1500 1501 for (i = 0; i < host->num_slots; i++) { 1502 struct dw_mci_slot *slot = host->slot[i]; 1503 struct mmc_host *mmc = slot->mmc; 1504 struct mmc_request *mrq; 1505 int present; 1506 u32 ctrl; 1507 1508 present = dw_mci_get_cd(mmc); 1509 while (present != slot->last_detect_state) { 1510 dev_dbg(&slot->mmc->class_dev, "card %s\n", 1511 present ? "inserted" : "removed"); 1512 1513 /* Power up slot (before spin_lock, may sleep) */ 1514 if (present != 0 && host->pdata->setpower) 1515 host->pdata->setpower(slot->id, mmc->ocr_avail); 1516 1517 spin_lock_bh(&host->lock); 1518 1519 /* Card change detected */ 1520 slot->last_detect_state = present; 1521 1522 /* Mark card as present if applicable */ 1523 if (present != 0) 1524 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1525 1526 /* Clean up queue if present */ 1527 mrq = slot->mrq; 1528 if (mrq) { 1529 if (mrq == host->mrq) { 1530 host->data = NULL; 1531 host->cmd = NULL; 1532 1533 switch (host->state) { 1534 case STATE_IDLE: 1535 break; 1536 case STATE_SENDING_CMD: 1537 mrq->cmd->error = -ENOMEDIUM; 1538 if (!mrq->data) 1539 break; 1540 /* fall through */ 1541 case STATE_SENDING_DATA: 1542 mrq->data->error = -ENOMEDIUM; 1543 dw_mci_stop_dma(host); 1544 break; 1545 case STATE_DATA_BUSY: 1546 case STATE_DATA_ERROR: 1547 if (mrq->data->error == -EINPROGRESS) 1548 mrq->data->error = -ENOMEDIUM; 1549 if (!mrq->stop) 1550 break; 1551 /* fall through */ 1552 case STATE_SENDING_STOP: 1553 mrq->stop->error = -ENOMEDIUM; 1554 break; 1555 } 1556 1557 dw_mci_request_end(host, mrq); 1558 } else { 1559 list_del(&slot->queue_node); 1560 mrq->cmd->error = -ENOMEDIUM; 1561 if (mrq->data) 1562 mrq->data->error = -ENOMEDIUM; 1563 if (mrq->stop) 1564 mrq->stop->error = -ENOMEDIUM; 1565 1566 spin_unlock(&host->lock); 1567 mmc_request_done(slot->mmc, mrq); 1568 spin_lock(&host->lock); 1569 } 1570 } 1571 1572 /* Power down slot */ 1573 if (present == 0) { 1574 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1575 1576 /* 1577 * Clear down the FIFO - doing so generates a 1578 * block interrupt, hence setting the 1579 * scatter-gather pointer to NULL. 1580 */ 1581 host->sg = NULL; 1582 1583 ctrl = mci_readl(host, CTRL); 1584 ctrl |= SDMMC_CTRL_FIFO_RESET; 1585 mci_writel(host, CTRL, ctrl); 1586 1587#ifdef CONFIG_MMC_DW_IDMAC 1588 ctrl = mci_readl(host, BMOD); 1589 ctrl |= 0x01; /* Software reset of DMA */ 1590 mci_writel(host, BMOD, ctrl); 1591#endif 1592 1593 } 1594 1595 spin_unlock_bh(&host->lock); 1596 1597 /* Power down slot (after spin_unlock, may sleep) */ 1598 if (present == 0 && host->pdata->setpower) 1599 host->pdata->setpower(slot->id, 0); 1600 1601 present = dw_mci_get_cd(mmc); 1602 } 1603 1604 mmc_detect_change(slot->mmc, 1605 msecs_to_jiffies(host->pdata->detect_delay_ms)); 1606 } 1607} 1608 1609static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id) 1610{ 1611 struct mmc_host *mmc; 1612 struct dw_mci_slot *slot; 1613 1614 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->pdev->dev); 1615 if (!mmc) 1616 return -ENOMEM; 1617 1618 slot = mmc_priv(mmc); 1619 slot->id = id; 1620 slot->mmc = mmc; 1621 slot->host = host; 1622 1623 mmc->ops = &dw_mci_ops; 1624 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510); 1625 mmc->f_max = host->bus_hz; 1626 1627 if (host->pdata->get_ocr) 1628 mmc->ocr_avail = host->pdata->get_ocr(id); 1629 else 1630 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1631 1632 /* 1633 * Start with slot power disabled, it will be enabled when a card 1634 * is detected. 1635 */ 1636 if (host->pdata->setpower) 1637 host->pdata->setpower(id, 0); 1638 1639 if (host->pdata->caps) 1640 mmc->caps = host->pdata->caps; 1641 else 1642 mmc->caps = 0; 1643 1644 if (host->pdata->get_bus_wd) 1645 if (host->pdata->get_bus_wd(slot->id) >= 4) 1646 mmc->caps |= MMC_CAP_4_BIT_DATA; 1647 1648 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED) 1649 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1650 1651#ifdef CONFIG_MMC_DW_IDMAC 1652 mmc->max_segs = host->ring_size; 1653 mmc->max_blk_size = 65536; 1654 mmc->max_blk_count = host->ring_size; 1655 mmc->max_seg_size = 0x1000; 1656 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count; 1657#else 1658 if (host->pdata->blk_settings) { 1659 mmc->max_segs = host->pdata->blk_settings->max_segs; 1660 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size; 1661 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count; 1662 mmc->max_req_size = host->pdata->blk_settings->max_req_size; 1663 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size; 1664 } else { 1665 /* Useful defaults if platform data is unset. */ 1666 mmc->max_segs = 64; 1667 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ 1668 mmc->max_blk_count = 512; 1669 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1670 mmc->max_seg_size = mmc->max_req_size; 1671 } 1672#endif /* CONFIG_MMC_DW_IDMAC */ 1673 1674 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc"); 1675 if (IS_ERR(host->vmmc)) { 1676 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc)); 1677 host->vmmc = NULL; 1678 } else 1679 regulator_enable(host->vmmc); 1680 1681 if (dw_mci_get_cd(mmc)) 1682 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1683 else 1684 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); 1685 1686 host->slot[id] = slot; 1687 mmc_add_host(mmc); 1688 1689#if defined(CONFIG_DEBUG_FS) 1690 dw_mci_init_debugfs(slot); 1691#endif 1692 1693 /* Card initially undetected */ 1694 slot->last_detect_state = 0; 1695 1696 /* 1697 * Card may have been plugged in prior to boot so we 1698 * need to run the detect tasklet 1699 */ 1700 queue_work(dw_mci_card_workqueue, &host->card_work); 1701 1702 return 0; 1703} 1704 1705static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) 1706{ 1707 /* Shutdown detect IRQ */ 1708 if (slot->host->pdata->exit) 1709 slot->host->pdata->exit(id); 1710 1711 /* Debugfs stuff is cleaned up by mmc core */ 1712 mmc_remove_host(slot->mmc); 1713 slot->host->slot[id] = NULL; 1714 mmc_free_host(slot->mmc); 1715} 1716 1717static void dw_mci_init_dma(struct dw_mci *host) 1718{ 1719 /* Alloc memory for sg translation */ 1720 host->sg_cpu = dma_alloc_coherent(&host->pdev->dev, PAGE_SIZE, 1721 &host->sg_dma, GFP_KERNEL); 1722 if (!host->sg_cpu) { 1723 dev_err(&host->pdev->dev, "%s: could not alloc DMA memory\n", 1724 __func__); 1725 goto no_dma; 1726 } 1727 1728 /* Determine which DMA interface to use */ 1729#ifdef CONFIG_MMC_DW_IDMAC 1730 host->dma_ops = &dw_mci_idmac_ops; 1731 dev_info(&host->pdev->dev, "Using internal DMA controller.\n"); 1732#endif 1733 1734 if (!host->dma_ops) 1735 goto no_dma; 1736 1737 if (host->dma_ops->init) { 1738 if (host->dma_ops->init(host)) { 1739 dev_err(&host->pdev->dev, "%s: Unable to initialize " 1740 "DMA Controller.\n", __func__); 1741 goto no_dma; 1742 } 1743 } else { 1744 dev_err(&host->pdev->dev, "DMA initialization not found.\n"); 1745 goto no_dma; 1746 } 1747 1748 host->use_dma = 1; 1749 return; 1750 1751no_dma: 1752 dev_info(&host->pdev->dev, "Using PIO mode.\n"); 1753 host->use_dma = 0; 1754 return; 1755} 1756 1757static bool mci_wait_reset(struct device *dev, struct dw_mci *host) 1758{ 1759 unsigned long timeout = jiffies + msecs_to_jiffies(500); 1760 unsigned int ctrl; 1761 1762 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | 1763 SDMMC_CTRL_DMA_RESET)); 1764 1765 /* wait till resets clear */ 1766 do { 1767 ctrl = mci_readl(host, CTRL); 1768 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | 1769 SDMMC_CTRL_DMA_RESET))) 1770 return true; 1771 } while (time_before(jiffies, timeout)); 1772 1773 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl); 1774 1775 return false; 1776} 1777 1778static int dw_mci_probe(struct platform_device *pdev) 1779{ 1780 struct dw_mci *host; 1781 struct resource *regs; 1782 struct dw_mci_board *pdata; 1783 int irq, ret, i, width; 1784 u32 fifo_size; 1785 1786 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1787 if (!regs) 1788 return -ENXIO; 1789 1790 irq = platform_get_irq(pdev, 0); 1791 if (irq < 0) 1792 return irq; 1793 1794 host = kzalloc(sizeof(struct dw_mci), GFP_KERNEL); 1795 if (!host) 1796 return -ENOMEM; 1797 1798 host->pdev = pdev; 1799 host->pdata = pdata = pdev->dev.platform_data; 1800 if (!pdata || !pdata->init) { 1801 dev_err(&pdev->dev, 1802 "Platform data must supply init function\n"); 1803 ret = -ENODEV; 1804 goto err_freehost; 1805 } 1806 1807 if (!pdata->select_slot && pdata->num_slots > 1) { 1808 dev_err(&pdev->dev, 1809 "Platform data must supply select_slot function\n"); 1810 ret = -ENODEV; 1811 goto err_freehost; 1812 } 1813 1814 if (!pdata->bus_hz) { 1815 dev_err(&pdev->dev, 1816 "Platform data must supply bus speed\n"); 1817 ret = -ENODEV; 1818 goto err_freehost; 1819 } 1820 1821 host->bus_hz = pdata->bus_hz; 1822 host->quirks = pdata->quirks; 1823 1824 spin_lock_init(&host->lock); 1825 INIT_LIST_HEAD(&host->queue); 1826 1827 ret = -ENOMEM; 1828 host->regs = ioremap(regs->start, regs->end - regs->start + 1); 1829 if (!host->regs) 1830 goto err_freehost; 1831 1832 host->dma_ops = pdata->dma_ops; 1833 dw_mci_init_dma(host); 1834 1835 /* 1836 * Get the host data width - this assumes that HCON has been set with 1837 * the correct values. 1838 */ 1839 i = (mci_readl(host, HCON) >> 7) & 0x7; 1840 if (!i) { 1841 host->push_data = dw_mci_push_data16; 1842 host->pull_data = dw_mci_pull_data16; 1843 width = 16; 1844 host->data_shift = 1; 1845 } else if (i == 2) { 1846 host->push_data = dw_mci_push_data64; 1847 host->pull_data = dw_mci_pull_data64; 1848 width = 64; 1849 host->data_shift = 3; 1850 } else { 1851 /* Check for a reserved value, and warn if it is */ 1852 WARN((i != 1), 1853 "HCON reports a reserved host data width!\n" 1854 "Defaulting to 32-bit access.\n"); 1855 host->push_data = dw_mci_push_data32; 1856 host->pull_data = dw_mci_pull_data32; 1857 width = 32; 1858 host->data_shift = 2; 1859 } 1860 1861 /* Reset all blocks */ 1862 if (!mci_wait_reset(&pdev->dev, host)) { 1863 ret = -ENODEV; 1864 goto err_dmaunmap; 1865 } 1866 1867 /* Clear the interrupts for the host controller */ 1868 mci_writel(host, RINTSTS, 0xFFFFFFFF); 1869 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 1870 1871 /* Put in max timeout */ 1872 mci_writel(host, TMOUT, 0xFFFFFFFF); 1873 1874 /* 1875 * FIFO threshold settings RxMark = fifo_size / 2 - 1, 1876 * Tx Mark = fifo_size / 2 DMA Size = 8 1877 */ 1878 if (!host->pdata->fifo_depth) { 1879 /* 1880 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 1881 * have been overwritten by the bootloader, just like we're 1882 * about to do, so if you know the value for your hardware, you 1883 * should put it in the platform data. 1884 */ 1885 fifo_size = mci_readl(host, FIFOTH); 1886 fifo_size = 1 + ((fifo_size >> 16) & 0x7ff); 1887 } else { 1888 fifo_size = host->pdata->fifo_depth; 1889 } 1890 host->fifo_depth = fifo_size; 1891 host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) | 1892 ((fifo_size/2) << 0)); 1893 mci_writel(host, FIFOTH, host->fifoth_val); 1894 1895 /* disable clock to CIU */ 1896 mci_writel(host, CLKENA, 0); 1897 mci_writel(host, CLKSRC, 0); 1898 1899 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 1900 dw_mci_card_workqueue = alloc_workqueue("dw-mci-card", 1901 WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1); 1902 if (!dw_mci_card_workqueue) 1903 goto err_dmaunmap; 1904 INIT_WORK(&host->card_work, dw_mci_work_routine_card); 1905 1906 ret = request_irq(irq, dw_mci_interrupt, 0, "dw-mci", host); 1907 if (ret) 1908 goto err_workqueue; 1909 1910 platform_set_drvdata(pdev, host); 1911 1912 if (host->pdata->num_slots) 1913 host->num_slots = host->pdata->num_slots; 1914 else 1915 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1; 1916 1917 /* We need at least one slot to succeed */ 1918 for (i = 0; i < host->num_slots; i++) { 1919 ret = dw_mci_init_slot(host, i); 1920 if (ret) { 1921 ret = -ENODEV; 1922 goto err_init_slot; 1923 } 1924 } 1925 1926 /* 1927 * Enable interrupts for command done, data over, data empty, card det, 1928 * receive ready and error such as transmit, receive timeout, crc error 1929 */ 1930 mci_writel(host, RINTSTS, 0xFFFFFFFF); 1931 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 1932 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 1933 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); 1934 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */ 1935 1936 dev_info(&pdev->dev, "DW MMC controller at irq %d, " 1937 "%d bit host data width, " 1938 "%u deep fifo\n", 1939 irq, width, fifo_size); 1940 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) 1941 dev_info(&pdev->dev, "Internal DMAC interrupt fix enabled.\n"); 1942 1943 return 0; 1944 1945err_init_slot: 1946 /* De-init any initialized slots */ 1947 while (i > 0) { 1948 if (host->slot[i]) 1949 dw_mci_cleanup_slot(host->slot[i], i); 1950 i--; 1951 } 1952 free_irq(irq, host); 1953 1954err_workqueue: 1955 destroy_workqueue(dw_mci_card_workqueue); 1956 1957err_dmaunmap: 1958 if (host->use_dma && host->dma_ops->exit) 1959 host->dma_ops->exit(host); 1960 dma_free_coherent(&host->pdev->dev, PAGE_SIZE, 1961 host->sg_cpu, host->sg_dma); 1962 iounmap(host->regs); 1963 1964 if (host->vmmc) { 1965 regulator_disable(host->vmmc); 1966 regulator_put(host->vmmc); 1967 } 1968 1969 1970err_freehost: 1971 kfree(host); 1972 return ret; 1973} 1974 1975static int __exit dw_mci_remove(struct platform_device *pdev) 1976{ 1977 struct dw_mci *host = platform_get_drvdata(pdev); 1978 int i; 1979 1980 mci_writel(host, RINTSTS, 0xFFFFFFFF); 1981 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 1982 1983 platform_set_drvdata(pdev, NULL); 1984 1985 for (i = 0; i < host->num_slots; i++) { 1986 dev_dbg(&pdev->dev, "remove slot %d\n", i); 1987 if (host->slot[i]) 1988 dw_mci_cleanup_slot(host->slot[i], i); 1989 } 1990 1991 /* disable clock to CIU */ 1992 mci_writel(host, CLKENA, 0); 1993 mci_writel(host, CLKSRC, 0); 1994 1995 free_irq(platform_get_irq(pdev, 0), host); 1996 destroy_workqueue(dw_mci_card_workqueue); 1997 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1998 1999 if (host->use_dma && host->dma_ops->exit) 2000 host->dma_ops->exit(host); 2001 2002 if (host->vmmc) { 2003 regulator_disable(host->vmmc); 2004 regulator_put(host->vmmc); 2005 } 2006 2007 iounmap(host->regs); 2008 2009 kfree(host); 2010 return 0; 2011} 2012 2013#ifdef CONFIG_PM 2014/* 2015 * TODO: we should probably disable the clock to the card in the suspend path. 2016 */ 2017static int dw_mci_suspend(struct platform_device *pdev, pm_message_t mesg) 2018{ 2019 int i, ret; 2020 struct dw_mci *host = platform_get_drvdata(pdev); 2021 2022 for (i = 0; i < host->num_slots; i++) { 2023 struct dw_mci_slot *slot = host->slot[i]; 2024 if (!slot) 2025 continue; 2026 ret = mmc_suspend_host(slot->mmc); 2027 if (ret < 0) { 2028 while (--i >= 0) { 2029 slot = host->slot[i]; 2030 if (slot) 2031 mmc_resume_host(host->slot[i]->mmc); 2032 } 2033 return ret; 2034 } 2035 } 2036 2037 if (host->vmmc) 2038 regulator_disable(host->vmmc); 2039 2040 return 0; 2041} 2042 2043static int dw_mci_resume(struct platform_device *pdev) 2044{ 2045 int i, ret; 2046 struct dw_mci *host = platform_get_drvdata(pdev); 2047 2048 if (host->vmmc) 2049 regulator_enable(host->vmmc); 2050 2051 if (host->dma_ops->init) 2052 host->dma_ops->init(host); 2053 2054 if (!mci_wait_reset(&pdev->dev, host)) { 2055 ret = -ENODEV; 2056 return ret; 2057 } 2058 2059 /* Restore the old value at FIFOTH register */ 2060 mci_writel(host, FIFOTH, host->fifoth_val); 2061 2062 mci_writel(host, RINTSTS, 0xFFFFFFFF); 2063 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 2064 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 2065 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); 2066 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 2067 2068 for (i = 0; i < host->num_slots; i++) { 2069 struct dw_mci_slot *slot = host->slot[i]; 2070 if (!slot) 2071 continue; 2072 ret = mmc_resume_host(host->slot[i]->mmc); 2073 if (ret < 0) 2074 return ret; 2075 } 2076 2077 return 0; 2078} 2079#else 2080#define dw_mci_suspend NULL 2081#define dw_mci_resume NULL 2082#endif /* CONFIG_PM */ 2083 2084static struct platform_driver dw_mci_driver = { 2085 .remove = __exit_p(dw_mci_remove), 2086 .suspend = dw_mci_suspend, 2087 .resume = dw_mci_resume, 2088 .driver = { 2089 .name = "dw_mmc", 2090 }, 2091}; 2092 2093static int __init dw_mci_init(void) 2094{ 2095 return platform_driver_probe(&dw_mci_driver, dw_mci_probe); 2096} 2097 2098static void __exit dw_mci_exit(void) 2099{ 2100 platform_driver_unregister(&dw_mci_driver); 2101} 2102 2103module_init(dw_mci_init); 2104module_exit(dw_mci_exit); 2105 2106MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 2107MODULE_AUTHOR("NXP Semiconductor VietNam"); 2108MODULE_AUTHOR("Imagination Technologies Ltd"); 2109MODULE_LICENSE("GPL v2"); 2110