ndfc.c revision 9d7948c50055e74b693ce9e99a709b2e5bbc1942 
1/*
2 *  drivers/mtd/ndfc.c
3 *
4 *  Overview:
5 *   Platform independent driver for NDFC (NanD Flash Controller)
6 *   integrated into EP440 cores
7 *
8 *   Ported to an OF platform driver by Sean MacLennan
9 *
10 *   The NDFC supports multiple chips, but this driver only supports a
11 *   single chip since I do not have access to any boards with
12 *   multiple chips.
13 *
14 *  Author: Thomas Gleixner
15 *
16 *  Copyright 2006 IBM
17 *  Copyright 2008 PIKA Technologies
18 *    Sean MacLennan <smaclennan@pikatech.com>
19 *
20 *  This program is free software; you can redistribute	 it and/or modify it
21 *  under  the terms of	 the GNU General  Public License as published by the
22 *  Free Software Foundation;  either version 2 of the	License, or (at your
23 *  option) any later version.
24 *
25 */
26#include <linux/module.h>
27#include <linux/mtd/nand.h>
28#include <linux/mtd/nand_ecc.h>
29#include <linux/mtd/partitions.h>
30#include <linux/mtd/ndfc.h>
31#include <linux/slab.h>
32#include <linux/mtd/mtd.h>
33#include <linux/of_platform.h>
34#include <asm/io.h>
35
36#define NDFC_MAX_CS    4
37
38struct ndfc_controller {
39	struct platform_device *ofdev;
40	void __iomem *ndfcbase;
41	struct mtd_info mtd;
42	struct nand_chip chip;
43	int chip_select;
44	struct nand_hw_control ndfc_control;
45	struct mtd_partition *parts;
46};
47
48static struct ndfc_controller ndfc_ctrl[NDFC_MAX_CS];
49
50static void ndfc_select_chip(struct mtd_info *mtd, int chip)
51{
52	uint32_t ccr;
53	struct nand_chip *nchip = mtd->priv;
54	struct ndfc_controller *ndfc = nchip->priv;
55
56	ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
57	if (chip >= 0) {
58		ccr &= ~NDFC_CCR_BS_MASK;
59		ccr |= NDFC_CCR_BS(chip + ndfc->chip_select);
60	} else
61		ccr |= NDFC_CCR_RESET_CE;
62	out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
63}
64
65static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
66{
67	struct nand_chip *chip = mtd->priv;
68	struct ndfc_controller *ndfc = chip->priv;
69
70	if (cmd == NAND_CMD_NONE)
71		return;
72
73	if (ctrl & NAND_CLE)
74		writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD);
75	else
76		writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE);
77}
78
79static int ndfc_ready(struct mtd_info *mtd)
80{
81	struct nand_chip *chip = mtd->priv;
82	struct ndfc_controller *ndfc = chip->priv;
83
84	return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY;
85}
86
87static void ndfc_enable_hwecc(struct mtd_info *mtd, int mode)
88{
89	uint32_t ccr;
90	struct nand_chip *chip = mtd->priv;
91	struct ndfc_controller *ndfc = chip->priv;
92
93	ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
94	ccr |= NDFC_CCR_RESET_ECC;
95	out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
96	wmb();
97}
98
99static int ndfc_calculate_ecc(struct mtd_info *mtd,
100			      const u_char *dat, u_char *ecc_code)
101{
102	struct nand_chip *chip = mtd->priv;
103	struct ndfc_controller *ndfc = chip->priv;
104	uint32_t ecc;
105	uint8_t *p = (uint8_t *)&ecc;
106
107	wmb();
108	ecc = in_be32(ndfc->ndfcbase + NDFC_ECC);
109	/* The NDFC uses Smart Media (SMC) bytes order */
110	ecc_code[0] = p[1];
111	ecc_code[1] = p[2];
112	ecc_code[2] = p[3];
113
114	return 0;
115}
116
117/*
118 * Speedups for buffer read/write/verify
119 *
120 * NDFC allows 32bit read/write of data. So we can speed up the buffer
121 * functions. No further checking, as nand_base will always read/write
122 * page aligned.
123 */
124static void ndfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
125{
126	struct nand_chip *chip = mtd->priv;
127	struct ndfc_controller *ndfc = chip->priv;
128	uint32_t *p = (uint32_t *) buf;
129
130	for(;len > 0; len -= 4)
131		*p++ = in_be32(ndfc->ndfcbase + NDFC_DATA);
132}
133
134static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
135{
136	struct nand_chip *chip = mtd->priv;
137	struct ndfc_controller *ndfc = chip->priv;
138	uint32_t *p = (uint32_t *) buf;
139
140	for(;len > 0; len -= 4)
141		out_be32(ndfc->ndfcbase + NDFC_DATA, *p++);
142}
143
144static int ndfc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
145{
146	struct nand_chip *chip = mtd->priv;
147	struct ndfc_controller *ndfc = chip->priv;
148	uint32_t *p = (uint32_t *) buf;
149
150	for(;len > 0; len -= 4)
151		if (*p++ != in_be32(ndfc->ndfcbase + NDFC_DATA))
152			return -EFAULT;
153	return 0;
154}
155
156/*
157 * Initialize chip structure
158 */
159static int ndfc_chip_init(struct ndfc_controller *ndfc,
160			  struct device_node *node)
161{
162	struct device_node *flash_np;
163	struct nand_chip *chip = &ndfc->chip;
164	struct mtd_part_parser_data ppdata;
165	int ret;
166
167	chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
168	chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
169	chip->cmd_ctrl = ndfc_hwcontrol;
170	chip->dev_ready = ndfc_ready;
171	chip->select_chip = ndfc_select_chip;
172	chip->chip_delay = 50;
173	chip->controller = &ndfc->ndfc_control;
174	chip->read_buf = ndfc_read_buf;
175	chip->write_buf = ndfc_write_buf;
176	chip->verify_buf = ndfc_verify_buf;
177	chip->ecc.correct = nand_correct_data;
178	chip->ecc.hwctl = ndfc_enable_hwecc;
179	chip->ecc.calculate = ndfc_calculate_ecc;
180	chip->ecc.mode = NAND_ECC_HW;
181	chip->ecc.size = 256;
182	chip->ecc.bytes = 3;
183	chip->priv = ndfc;
184
185	ndfc->mtd.priv = chip;
186	ndfc->mtd.owner = THIS_MODULE;
187
188	flash_np = of_get_next_child(node, NULL);
189	if (!flash_np)
190		return -ENODEV;
191
192	ppdata->of_node = flash_np;
193	ndfc->mtd.name = kasprintf(GFP_KERNEL, "%s.%s",
194			dev_name(&ndfc->ofdev->dev), flash_np->name);
195	if (!ndfc->mtd.name) {
196		ret = -ENOMEM;
197		goto err;
198	}
199
200	ret = nand_scan(&ndfc->mtd, 1);
201	if (ret)
202		goto err;
203
204	ret = parse_mtd_partitions(&ndfc->mtd, NULL, &ndfc->parts, &ppdata);
205	if (ret < 0)
206		goto err;
207
208	ret = mtd_device_register(&ndfc->mtd, ndfc->parts, ret);
209
210err:
211	of_node_put(flash_np);
212	if (ret)
213		kfree(ndfc->mtd.name);
214	return ret;
215}
216
217static int __devinit ndfc_probe(struct platform_device *ofdev)
218{
219	struct ndfc_controller *ndfc;
220	const __be32 *reg;
221	u32 ccr;
222	int err, len, cs;
223
224	/* Read the reg property to get the chip select */
225	reg = of_get_property(ofdev->dev.of_node, "reg", &len);
226	if (reg == NULL || len != 12) {
227		dev_err(&ofdev->dev, "unable read reg property (%d)\n", len);
228		return -ENOENT;
229	}
230
231	cs = be32_to_cpu(reg[0]);
232	if (cs >= NDFC_MAX_CS) {
233		dev_err(&ofdev->dev, "invalid CS number (%d)\n", cs);
234		return -EINVAL;
235	}
236
237	ndfc = &ndfc_ctrl[cs];
238	ndfc->chip_select = cs;
239
240	spin_lock_init(&ndfc->ndfc_control.lock);
241	init_waitqueue_head(&ndfc->ndfc_control.wq);
242	ndfc->ofdev = ofdev;
243	dev_set_drvdata(&ofdev->dev, ndfc);
244
245	ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0);
246	if (!ndfc->ndfcbase) {
247		dev_err(&ofdev->dev, "failed to get memory\n");
248		return -EIO;
249	}
250
251	ccr = NDFC_CCR_BS(ndfc->chip_select);
252
253	/* It is ok if ccr does not exist - just default to 0 */
254	reg = of_get_property(ofdev->dev.of_node, "ccr", NULL);
255	if (reg)
256		ccr |= be32_to_cpup(reg);
257
258	out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
259
260	/* Set the bank settings if given */
261	reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL);
262	if (reg) {
263		int offset = NDFC_BCFG0 + (ndfc->chip_select << 2);
264		out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg));
265	}
266
267	err = ndfc_chip_init(ndfc, ofdev->dev.of_node);
268	if (err) {
269		iounmap(ndfc->ndfcbase);
270		return err;
271	}
272
273	return 0;
274}
275
276static int __devexit ndfc_remove(struct platform_device *ofdev)
277{
278	struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev);
279
280	nand_release(&ndfc->mtd);
281	kfree(ndfc->mtd.name);
282
283	return 0;
284}
285
286static const struct of_device_id ndfc_match[] = {
287	{ .compatible = "ibm,ndfc", },
288	{}
289};
290MODULE_DEVICE_TABLE(of, ndfc_match);
291
292static struct platform_driver ndfc_driver = {
293	.driver = {
294		.name = "ndfc",
295		.owner = THIS_MODULE,
296		.of_match_table = ndfc_match,
297	},
298	.probe = ndfc_probe,
299	.remove = __devexit_p(ndfc_remove),
300};
301
302static int __init ndfc_nand_init(void)
303{
304	return platform_driver_register(&ndfc_driver);
305}
306
307static void __exit ndfc_nand_exit(void)
308{
309	platform_driver_unregister(&ndfc_driver);
310}
311
312module_init(ndfc_nand_init);
313module_exit(ndfc_nand_exit);
314
315MODULE_LICENSE("GPL");
316MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
317MODULE_DESCRIPTION("OF Platform driver for NDFC");
318