1/* linux/drivers/mtd/nand/s3c2410.c 2 * 3 * Copyright © 2004-2008 Simtec Electronics 4 * http://armlinux.simtec.co.uk/ 5 * Ben Dooks <ben@simtec.co.uk> 6 * 7 * Samsung S3C2410/S3C2440/S3C2412 NAND driver 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22*/ 23 24#ifdef CONFIG_MTD_NAND_S3C2410_DEBUG 25#define DEBUG 26#endif 27 28#include <linux/module.h> 29#include <linux/types.h> 30#include <linux/init.h> 31#include <linux/kernel.h> 32#include <linux/string.h> 33#include <linux/ioport.h> 34#include <linux/platform_device.h> 35#include <linux/delay.h> 36#include <linux/err.h> 37#include <linux/slab.h> 38#include <linux/clk.h> 39#include <linux/cpufreq.h> 40 41#include <linux/mtd/mtd.h> 42#include <linux/mtd/nand.h> 43#include <linux/mtd/nand_ecc.h> 44#include <linux/mtd/partitions.h> 45 46#include <asm/io.h> 47 48#include <plat/regs-nand.h> 49#include <plat/nand.h> 50 51#ifdef CONFIG_MTD_NAND_S3C2410_HWECC 52static int hardware_ecc = 1; 53#else 54static int hardware_ecc = 0; 55#endif 56 57#ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP 58static const int clock_stop = 1; 59#else 60static const int clock_stop = 0; 61#endif 62 63 64/* new oob placement block for use with hardware ecc generation 65 */ 66 67static struct nand_ecclayout nand_hw_eccoob = { 68 .eccbytes = 3, 69 .eccpos = {0, 1, 2}, 70 .oobfree = {{8, 8}} 71}; 72 73/* controller and mtd information */ 74 75struct s3c2410_nand_info; 76 77/** 78 * struct s3c2410_nand_mtd - driver MTD structure 79 * @mtd: The MTD instance to pass to the MTD layer. 80 * @chip: The NAND chip information. 81 * @set: The platform information supplied for this set of NAND chips. 82 * @info: Link back to the hardware information. 83 * @scan_res: The result from calling nand_scan_ident(). 84*/ 85struct s3c2410_nand_mtd { 86 struct mtd_info mtd; 87 struct nand_chip chip; 88 struct s3c2410_nand_set *set; 89 struct s3c2410_nand_info *info; 90 int scan_res; 91}; 92 93enum s3c_cpu_type { 94 TYPE_S3C2410, 95 TYPE_S3C2412, 96 TYPE_S3C2440, 97}; 98 99enum s3c_nand_clk_state { 100 CLOCK_DISABLE = 0, 101 CLOCK_ENABLE, 102 CLOCK_SUSPEND, 103}; 104 105/* overview of the s3c2410 nand state */ 106 107/** 108 * struct s3c2410_nand_info - NAND controller state. 109 * @mtds: An array of MTD instances on this controoler. 110 * @platform: The platform data for this board. 111 * @device: The platform device we bound to. 112 * @area: The IO area resource that came from request_mem_region(). 113 * @clk: The clock resource for this controller. 114 * @regs: The area mapped for the hardware registers described by @area. 115 * @sel_reg: Pointer to the register controlling the NAND selection. 116 * @sel_bit: The bit in @sel_reg to select the NAND chip. 117 * @mtd_count: The number of MTDs created from this controller. 118 * @save_sel: The contents of @sel_reg to be saved over suspend. 119 * @clk_rate: The clock rate from @clk. 120 * @clk_state: The current clock state. 121 * @cpu_type: The exact type of this controller. 122 */ 123struct s3c2410_nand_info { 124 /* mtd info */ 125 struct nand_hw_control controller; 126 struct s3c2410_nand_mtd *mtds; 127 struct s3c2410_platform_nand *platform; 128 129 /* device info */ 130 struct device *device; 131 struct resource *area; 132 struct clk *clk; 133 void __iomem *regs; 134 void __iomem *sel_reg; 135 int sel_bit; 136 int mtd_count; 137 unsigned long save_sel; 138 unsigned long clk_rate; 139 enum s3c_nand_clk_state clk_state; 140 141 enum s3c_cpu_type cpu_type; 142 143#ifdef CONFIG_CPU_FREQ 144 struct notifier_block freq_transition; 145#endif 146}; 147 148/* conversion functions */ 149 150static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd) 151{ 152 return container_of(mtd, struct s3c2410_nand_mtd, mtd); 153} 154 155static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd) 156{ 157 return s3c2410_nand_mtd_toours(mtd)->info; 158} 159 160static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev) 161{ 162 return platform_get_drvdata(dev); 163} 164 165static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) 166{ 167 return dev->dev.platform_data; 168} 169 170static inline int allow_clk_suspend(struct s3c2410_nand_info *info) 171{ 172 return clock_stop; 173} 174 175/** 176 * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock. 177 * @info: The controller instance. 178 * @new_state: State to which clock should be set. 179 */ 180static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info, 181 enum s3c_nand_clk_state new_state) 182{ 183 if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND) 184 return; 185 186 if (info->clk_state == CLOCK_ENABLE) { 187 if (new_state != CLOCK_ENABLE) 188 clk_disable(info->clk); 189 } else { 190 if (new_state == CLOCK_ENABLE) 191 clk_enable(info->clk); 192 } 193 194 info->clk_state = new_state; 195} 196 197/* timing calculations */ 198 199#define NS_IN_KHZ 1000000 200 201/** 202 * s3c_nand_calc_rate - calculate timing data. 203 * @wanted: The cycle time in nanoseconds. 204 * @clk: The clock rate in kHz. 205 * @max: The maximum divider value. 206 * 207 * Calculate the timing value from the given parameters. 208 */ 209static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max) 210{ 211 int result; 212 213 result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ); 214 215 pr_debug("result %d from %ld, %d\n", result, clk, wanted); 216 217 if (result > max) { 218 printk("%d ns is too big for current clock rate %ld\n", wanted, clk); 219 return -1; 220 } 221 222 if (result < 1) 223 result = 1; 224 225 return result; 226} 227 228#define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk)) 229 230/* controller setup */ 231 232/** 233 * s3c2410_nand_setrate - setup controller timing information. 234 * @info: The controller instance. 235 * 236 * Given the information supplied by the platform, calculate and set 237 * the necessary timing registers in the hardware to generate the 238 * necessary timing cycles to the hardware. 239 */ 240static int s3c2410_nand_setrate(struct s3c2410_nand_info *info) 241{ 242 struct s3c2410_platform_nand *plat = info->platform; 243 int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4; 244 int tacls, twrph0, twrph1; 245 unsigned long clkrate = clk_get_rate(info->clk); 246 unsigned long uninitialized_var(set), cfg, uninitialized_var(mask); 247 unsigned long flags; 248 249 /* calculate the timing information for the controller */ 250 251 info->clk_rate = clkrate; 252 clkrate /= 1000; /* turn clock into kHz for ease of use */ 253 254 if (plat != NULL) { 255 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max); 256 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8); 257 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8); 258 } else { 259 /* default timings */ 260 tacls = tacls_max; 261 twrph0 = 8; 262 twrph1 = 8; 263 } 264 265 if (tacls < 0 || twrph0 < 0 || twrph1 < 0) { 266 dev_err(info->device, "cannot get suitable timings\n"); 267 return -EINVAL; 268 } 269 270 dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", 271 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate)); 272 273 switch (info->cpu_type) { 274 case TYPE_S3C2410: 275 mask = (S3C2410_NFCONF_TACLS(3) | 276 S3C2410_NFCONF_TWRPH0(7) | 277 S3C2410_NFCONF_TWRPH1(7)); 278 set = S3C2410_NFCONF_EN; 279 set |= S3C2410_NFCONF_TACLS(tacls - 1); 280 set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); 281 set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); 282 break; 283 284 case TYPE_S3C2440: 285 case TYPE_S3C2412: 286 mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) | 287 S3C2440_NFCONF_TWRPH0(7) | 288 S3C2440_NFCONF_TWRPH1(7)); 289 290 set = S3C2440_NFCONF_TACLS(tacls - 1); 291 set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1); 292 set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1); 293 break; 294 295 default: 296 BUG(); 297 } 298 299 local_irq_save(flags); 300 301 cfg = readl(info->regs + S3C2410_NFCONF); 302 cfg &= ~mask; 303 cfg |= set; 304 writel(cfg, info->regs + S3C2410_NFCONF); 305 306 local_irq_restore(flags); 307 308 dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg); 309 310 return 0; 311} 312 313/** 314 * s3c2410_nand_inithw - basic hardware initialisation 315 * @info: The hardware state. 316 * 317 * Do the basic initialisation of the hardware, using s3c2410_nand_setrate() 318 * to setup the hardware access speeds and set the controller to be enabled. 319*/ 320static int s3c2410_nand_inithw(struct s3c2410_nand_info *info) 321{ 322 int ret; 323 324 ret = s3c2410_nand_setrate(info); 325 if (ret < 0) 326 return ret; 327 328 switch (info->cpu_type) { 329 case TYPE_S3C2410: 330 default: 331 break; 332 333 case TYPE_S3C2440: 334 case TYPE_S3C2412: 335 /* enable the controller and de-assert nFCE */ 336 337 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT); 338 } 339 340 return 0; 341} 342 343/** 344 * s3c2410_nand_select_chip - select the given nand chip 345 * @mtd: The MTD instance for this chip. 346 * @chip: The chip number. 347 * 348 * This is called by the MTD layer to either select a given chip for the 349 * @mtd instance, or to indicate that the access has finished and the 350 * chip can be de-selected. 351 * 352 * The routine ensures that the nFCE line is correctly setup, and any 353 * platform specific selection code is called to route nFCE to the specific 354 * chip. 355 */ 356static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) 357{ 358 struct s3c2410_nand_info *info; 359 struct s3c2410_nand_mtd *nmtd; 360 struct nand_chip *this = mtd->priv; 361 unsigned long cur; 362 363 nmtd = this->priv; 364 info = nmtd->info; 365 366 if (chip != -1) 367 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); 368 369 cur = readl(info->sel_reg); 370 371 if (chip == -1) { 372 cur |= info->sel_bit; 373 } else { 374 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) { 375 dev_err(info->device, "invalid chip %d\n", chip); 376 return; 377 } 378 379 if (info->platform != NULL) { 380 if (info->platform->select_chip != NULL) 381 (info->platform->select_chip) (nmtd->set, chip); 382 } 383 384 cur &= ~info->sel_bit; 385 } 386 387 writel(cur, info->sel_reg); 388 389 if (chip == -1) 390 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); 391} 392 393/* s3c2410_nand_hwcontrol 394 * 395 * Issue command and address cycles to the chip 396*/ 397 398static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd, 399 unsigned int ctrl) 400{ 401 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 402 403 if (cmd == NAND_CMD_NONE) 404 return; 405 406 if (ctrl & NAND_CLE) 407 writeb(cmd, info->regs + S3C2410_NFCMD); 408 else 409 writeb(cmd, info->regs + S3C2410_NFADDR); 410} 411 412/* command and control functions */ 413 414static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd, 415 unsigned int ctrl) 416{ 417 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 418 419 if (cmd == NAND_CMD_NONE) 420 return; 421 422 if (ctrl & NAND_CLE) 423 writeb(cmd, info->regs + S3C2440_NFCMD); 424 else 425 writeb(cmd, info->regs + S3C2440_NFADDR); 426} 427 428/* s3c2410_nand_devready() 429 * 430 * returns 0 if the nand is busy, 1 if it is ready 431*/ 432 433static int s3c2410_nand_devready(struct mtd_info *mtd) 434{ 435 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 436 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; 437} 438 439static int s3c2440_nand_devready(struct mtd_info *mtd) 440{ 441 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 442 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; 443} 444 445static int s3c2412_nand_devready(struct mtd_info *mtd) 446{ 447 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 448 return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY; 449} 450 451/* ECC handling functions */ 452 453static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, 454 u_char *read_ecc, u_char *calc_ecc) 455{ 456 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 457 unsigned int diff0, diff1, diff2; 458 unsigned int bit, byte; 459 460 pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc); 461 462 diff0 = read_ecc[0] ^ calc_ecc[0]; 463 diff1 = read_ecc[1] ^ calc_ecc[1]; 464 diff2 = read_ecc[2] ^ calc_ecc[2]; 465 466 pr_debug("%s: rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n", 467 __func__, 468 read_ecc[0], read_ecc[1], read_ecc[2], 469 calc_ecc[0], calc_ecc[1], calc_ecc[2], 470 diff0, diff1, diff2); 471 472 if (diff0 == 0 && diff1 == 0 && diff2 == 0) 473 return 0; /* ECC is ok */ 474 475 /* sometimes people do not think about using the ECC, so check 476 * to see if we have an 0xff,0xff,0xff read ECC and then ignore 477 * the error, on the assumption that this is an un-eccd page. 478 */ 479 if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff 480 && info->platform->ignore_unset_ecc) 481 return 0; 482 483 /* Can we correct this ECC (ie, one row and column change). 484 * Note, this is similar to the 256 error code on smartmedia */ 485 486 if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 && 487 ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 && 488 ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) { 489 /* calculate the bit position of the error */ 490 491 bit = ((diff2 >> 3) & 1) | 492 ((diff2 >> 4) & 2) | 493 ((diff2 >> 5) & 4); 494 495 /* calculate the byte position of the error */ 496 497 byte = ((diff2 << 7) & 0x100) | 498 ((diff1 << 0) & 0x80) | 499 ((diff1 << 1) & 0x40) | 500 ((diff1 << 2) & 0x20) | 501 ((diff1 << 3) & 0x10) | 502 ((diff0 >> 4) & 0x08) | 503 ((diff0 >> 3) & 0x04) | 504 ((diff0 >> 2) & 0x02) | 505 ((diff0 >> 1) & 0x01); 506 507 dev_dbg(info->device, "correcting error bit %d, byte %d\n", 508 bit, byte); 509 510 dat[byte] ^= (1 << bit); 511 return 1; 512 } 513 514 /* if there is only one bit difference in the ECC, then 515 * one of only a row or column parity has changed, which 516 * means the error is most probably in the ECC itself */ 517 518 diff0 |= (diff1 << 8); 519 diff0 |= (diff2 << 16); 520 521 if ((diff0 & ~(1<<fls(diff0))) == 0) 522 return 1; 523 524 return -1; 525} 526 527/* ECC functions 528 * 529 * These allow the s3c2410 and s3c2440 to use the controller's ECC 530 * generator block to ECC the data as it passes through] 531*/ 532 533static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) 534{ 535 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 536 unsigned long ctrl; 537 538 ctrl = readl(info->regs + S3C2410_NFCONF); 539 ctrl |= S3C2410_NFCONF_INITECC; 540 writel(ctrl, info->regs + S3C2410_NFCONF); 541} 542 543static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode) 544{ 545 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 546 unsigned long ctrl; 547 548 ctrl = readl(info->regs + S3C2440_NFCONT); 549 writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, info->regs + S3C2440_NFCONT); 550} 551 552static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) 553{ 554 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 555 unsigned long ctrl; 556 557 ctrl = readl(info->regs + S3C2440_NFCONT); 558 writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); 559} 560 561static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) 562{ 563 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 564 565 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0); 566 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); 567 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); 568 569 pr_debug("%s: returning ecc %02x%02x%02x\n", __func__, 570 ecc_code[0], ecc_code[1], ecc_code[2]); 571 572 return 0; 573} 574 575static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) 576{ 577 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 578 unsigned long ecc = readl(info->regs + S3C2412_NFMECC0); 579 580 ecc_code[0] = ecc; 581 ecc_code[1] = ecc >> 8; 582 ecc_code[2] = ecc >> 16; 583 584 pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]); 585 586 return 0; 587} 588 589static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) 590{ 591 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 592 unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); 593 594 ecc_code[0] = ecc; 595 ecc_code[1] = ecc >> 8; 596 ecc_code[2] = ecc >> 16; 597 598 pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff); 599 600 return 0; 601} 602 603/* over-ride the standard functions for a little more speed. We can 604 * use read/write block to move the data buffers to/from the controller 605*/ 606 607static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) 608{ 609 struct nand_chip *this = mtd->priv; 610 readsb(this->IO_ADDR_R, buf, len); 611} 612 613static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) 614{ 615 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 616 617 readsl(info->regs + S3C2440_NFDATA, buf, len >> 2); 618 619 /* cleanup if we've got less than a word to do */ 620 if (len & 3) { 621 buf += len & ~3; 622 623 for (; len & 3; len--) 624 *buf++ = readb(info->regs + S3C2440_NFDATA); 625 } 626} 627 628static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) 629{ 630 struct nand_chip *this = mtd->priv; 631 writesb(this->IO_ADDR_W, buf, len); 632} 633 634static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) 635{ 636 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 637 638 writesl(info->regs + S3C2440_NFDATA, buf, len >> 2); 639 640 /* cleanup any fractional write */ 641 if (len & 3) { 642 buf += len & ~3; 643 644 for (; len & 3; len--, buf++) 645 writeb(*buf, info->regs + S3C2440_NFDATA); 646 } 647} 648 649/* cpufreq driver support */ 650 651#ifdef CONFIG_CPU_FREQ 652 653static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb, 654 unsigned long val, void *data) 655{ 656 struct s3c2410_nand_info *info; 657 unsigned long newclk; 658 659 info = container_of(nb, struct s3c2410_nand_info, freq_transition); 660 newclk = clk_get_rate(info->clk); 661 662 if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) || 663 (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) { 664 s3c2410_nand_setrate(info); 665 } 666 667 return 0; 668} 669 670static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) 671{ 672 info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition; 673 674 return cpufreq_register_notifier(&info->freq_transition, 675 CPUFREQ_TRANSITION_NOTIFIER); 676} 677 678static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) 679{ 680 cpufreq_unregister_notifier(&info->freq_transition, 681 CPUFREQ_TRANSITION_NOTIFIER); 682} 683 684#else 685static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) 686{ 687 return 0; 688} 689 690static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) 691{ 692} 693#endif 694 695/* device management functions */ 696 697static int s3c24xx_nand_remove(struct platform_device *pdev) 698{ 699 struct s3c2410_nand_info *info = to_nand_info(pdev); 700 701 platform_set_drvdata(pdev, NULL); 702 703 if (info == NULL) 704 return 0; 705 706 s3c2410_nand_cpufreq_deregister(info); 707 708 /* Release all our mtds and their partitions, then go through 709 * freeing the resources used 710 */ 711 712 if (info->mtds != NULL) { 713 struct s3c2410_nand_mtd *ptr = info->mtds; 714 int mtdno; 715 716 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) { 717 pr_debug("releasing mtd %d (%p)\n", mtdno, ptr); 718 nand_release(&ptr->mtd); 719 } 720 721 kfree(info->mtds); 722 } 723 724 /* free the common resources */ 725 726 if (!IS_ERR(info->clk)) { 727 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); 728 clk_put(info->clk); 729 } 730 731 if (info->regs != NULL) { 732 iounmap(info->regs); 733 info->regs = NULL; 734 } 735 736 if (info->area != NULL) { 737 release_resource(info->area); 738 kfree(info->area); 739 info->area = NULL; 740 } 741 742 kfree(info); 743 744 return 0; 745} 746 747static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, 748 struct s3c2410_nand_mtd *mtd, 749 struct s3c2410_nand_set *set) 750{ 751 if (set) 752 mtd->mtd.name = set->name; 753 754 return mtd_device_parse_register(&mtd->mtd, NULL, NULL, 755 set->partitions, set->nr_partitions); 756} 757 758/** 759 * s3c2410_nand_init_chip - initialise a single instance of an chip 760 * @info: The base NAND controller the chip is on. 761 * @nmtd: The new controller MTD instance to fill in. 762 * @set: The information passed from the board specific platform data. 763 * 764 * Initialise the given @nmtd from the information in @info and @set. This 765 * readies the structure for use with the MTD layer functions by ensuring 766 * all pointers are setup and the necessary control routines selected. 767 */ 768static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, 769 struct s3c2410_nand_mtd *nmtd, 770 struct s3c2410_nand_set *set) 771{ 772 struct nand_chip *chip = &nmtd->chip; 773 void __iomem *regs = info->regs; 774 775 chip->write_buf = s3c2410_nand_write_buf; 776 chip->read_buf = s3c2410_nand_read_buf; 777 chip->select_chip = s3c2410_nand_select_chip; 778 chip->chip_delay = 50; 779 chip->priv = nmtd; 780 chip->options = set->options; 781 chip->controller = &info->controller; 782 783 switch (info->cpu_type) { 784 case TYPE_S3C2410: 785 chip->IO_ADDR_W = regs + S3C2410_NFDATA; 786 info->sel_reg = regs + S3C2410_NFCONF; 787 info->sel_bit = S3C2410_NFCONF_nFCE; 788 chip->cmd_ctrl = s3c2410_nand_hwcontrol; 789 chip->dev_ready = s3c2410_nand_devready; 790 break; 791 792 case TYPE_S3C2440: 793 chip->IO_ADDR_W = regs + S3C2440_NFDATA; 794 info->sel_reg = regs + S3C2440_NFCONT; 795 info->sel_bit = S3C2440_NFCONT_nFCE; 796 chip->cmd_ctrl = s3c2440_nand_hwcontrol; 797 chip->dev_ready = s3c2440_nand_devready; 798 chip->read_buf = s3c2440_nand_read_buf; 799 chip->write_buf = s3c2440_nand_write_buf; 800 break; 801 802 case TYPE_S3C2412: 803 chip->IO_ADDR_W = regs + S3C2440_NFDATA; 804 info->sel_reg = regs + S3C2440_NFCONT; 805 info->sel_bit = S3C2412_NFCONT_nFCE0; 806 chip->cmd_ctrl = s3c2440_nand_hwcontrol; 807 chip->dev_ready = s3c2412_nand_devready; 808 809 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT) 810 dev_info(info->device, "System booted from NAND\n"); 811 812 break; 813 } 814 815 chip->IO_ADDR_R = chip->IO_ADDR_W; 816 817 nmtd->info = info; 818 nmtd->mtd.priv = chip; 819 nmtd->mtd.owner = THIS_MODULE; 820 nmtd->set = set; 821 822 if (hardware_ecc) { 823 chip->ecc.calculate = s3c2410_nand_calculate_ecc; 824 chip->ecc.correct = s3c2410_nand_correct_data; 825 chip->ecc.mode = NAND_ECC_HW; 826 chip->ecc.strength = 1; 827 828 switch (info->cpu_type) { 829 case TYPE_S3C2410: 830 chip->ecc.hwctl = s3c2410_nand_enable_hwecc; 831 chip->ecc.calculate = s3c2410_nand_calculate_ecc; 832 break; 833 834 case TYPE_S3C2412: 835 chip->ecc.hwctl = s3c2412_nand_enable_hwecc; 836 chip->ecc.calculate = s3c2412_nand_calculate_ecc; 837 break; 838 839 case TYPE_S3C2440: 840 chip->ecc.hwctl = s3c2440_nand_enable_hwecc; 841 chip->ecc.calculate = s3c2440_nand_calculate_ecc; 842 break; 843 844 } 845 } else { 846 chip->ecc.mode = NAND_ECC_SOFT; 847 } 848 849 if (set->ecc_layout != NULL) 850 chip->ecc.layout = set->ecc_layout; 851 852 if (set->disable_ecc) 853 chip->ecc.mode = NAND_ECC_NONE; 854 855 switch (chip->ecc.mode) { 856 case NAND_ECC_NONE: 857 dev_info(info->device, "NAND ECC disabled\n"); 858 break; 859 case NAND_ECC_SOFT: 860 dev_info(info->device, "NAND soft ECC\n"); 861 break; 862 case NAND_ECC_HW: 863 dev_info(info->device, "NAND hardware ECC\n"); 864 break; 865 default: 866 dev_info(info->device, "NAND ECC UNKNOWN\n"); 867 break; 868 } 869 870 /* If you use u-boot BBT creation code, specifying this flag will 871 * let the kernel fish out the BBT from the NAND, and also skip the 872 * full NAND scan that can take 1/2s or so. Little things... */ 873 if (set->flash_bbt) { 874 chip->bbt_options |= NAND_BBT_USE_FLASH; 875 chip->options |= NAND_SKIP_BBTSCAN; 876 } 877} 878 879/** 880 * s3c2410_nand_update_chip - post probe update 881 * @info: The controller instance. 882 * @nmtd: The driver version of the MTD instance. 883 * 884 * This routine is called after the chip probe has successfully completed 885 * and the relevant per-chip information updated. This call ensure that 886 * we update the internal state accordingly. 887 * 888 * The internal state is currently limited to the ECC state information. 889*/ 890static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info, 891 struct s3c2410_nand_mtd *nmtd) 892{ 893 struct nand_chip *chip = &nmtd->chip; 894 895 dev_dbg(info->device, "chip %p => page shift %d\n", 896 chip, chip->page_shift); 897 898 if (chip->ecc.mode != NAND_ECC_HW) 899 return; 900 901 /* change the behaviour depending on wether we are using 902 * the large or small page nand device */ 903 904 if (chip->page_shift > 10) { 905 chip->ecc.size = 256; 906 chip->ecc.bytes = 3; 907 } else { 908 chip->ecc.size = 512; 909 chip->ecc.bytes = 3; 910 chip->ecc.layout = &nand_hw_eccoob; 911 } 912} 913 914/* s3c24xx_nand_probe 915 * 916 * called by device layer when it finds a device matching 917 * one our driver can handled. This code checks to see if 918 * it can allocate all necessary resources then calls the 919 * nand layer to look for devices 920*/ 921static int s3c24xx_nand_probe(struct platform_device *pdev) 922{ 923 struct s3c2410_platform_nand *plat = to_nand_plat(pdev); 924 enum s3c_cpu_type cpu_type; 925 struct s3c2410_nand_info *info; 926 struct s3c2410_nand_mtd *nmtd; 927 struct s3c2410_nand_set *sets; 928 struct resource *res; 929 int err = 0; 930 int size; 931 int nr_sets; 932 int setno; 933 934 cpu_type = platform_get_device_id(pdev)->driver_data; 935 936 pr_debug("s3c2410_nand_probe(%p)\n", pdev); 937 938 info = kzalloc(sizeof(*info), GFP_KERNEL); 939 if (info == NULL) { 940 dev_err(&pdev->dev, "no memory for flash info\n"); 941 err = -ENOMEM; 942 goto exit_error; 943 } 944 945 platform_set_drvdata(pdev, info); 946 947 spin_lock_init(&info->controller.lock); 948 init_waitqueue_head(&info->controller.wq); 949 950 /* get the clock source and enable it */ 951 952 info->clk = clk_get(&pdev->dev, "nand"); 953 if (IS_ERR(info->clk)) { 954 dev_err(&pdev->dev, "failed to get clock\n"); 955 err = -ENOENT; 956 goto exit_error; 957 } 958 959 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); 960 961 /* allocate and map the resource */ 962 963 /* currently we assume we have the one resource */ 964 res = pdev->resource; 965 size = resource_size(res); 966 967 info->area = request_mem_region(res->start, size, pdev->name); 968 969 if (info->area == NULL) { 970 dev_err(&pdev->dev, "cannot reserve register region\n"); 971 err = -ENOENT; 972 goto exit_error; 973 } 974 975 info->device = &pdev->dev; 976 info->platform = plat; 977 info->regs = ioremap(res->start, size); 978 info->cpu_type = cpu_type; 979 980 if (info->regs == NULL) { 981 dev_err(&pdev->dev, "cannot reserve register region\n"); 982 err = -EIO; 983 goto exit_error; 984 } 985 986 dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs); 987 988 /* initialise the hardware */ 989 990 err = s3c2410_nand_inithw(info); 991 if (err != 0) 992 goto exit_error; 993 994 sets = (plat != NULL) ? plat->sets : NULL; 995 nr_sets = (plat != NULL) ? plat->nr_sets : 1; 996 997 info->mtd_count = nr_sets; 998 999 /* allocate our information */ 1000 1001 size = nr_sets * sizeof(*info->mtds); 1002 info->mtds = kzalloc(size, GFP_KERNEL); 1003 if (info->mtds == NULL) { 1004 dev_err(&pdev->dev, "failed to allocate mtd storage\n"); 1005 err = -ENOMEM; 1006 goto exit_error; 1007 } 1008 1009 /* initialise all possible chips */ 1010 1011 nmtd = info->mtds; 1012 1013 for (setno = 0; setno < nr_sets; setno++, nmtd++) { 1014 pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info); 1015 1016 s3c2410_nand_init_chip(info, nmtd, sets); 1017 1018 nmtd->scan_res = nand_scan_ident(&nmtd->mtd, 1019 (sets) ? sets->nr_chips : 1, 1020 NULL); 1021 1022 if (nmtd->scan_res == 0) { 1023 s3c2410_nand_update_chip(info, nmtd); 1024 nand_scan_tail(&nmtd->mtd); 1025 s3c2410_nand_add_partition(info, nmtd, sets); 1026 } 1027 1028 if (sets != NULL) 1029 sets++; 1030 } 1031 1032 err = s3c2410_nand_cpufreq_register(info); 1033 if (err < 0) { 1034 dev_err(&pdev->dev, "failed to init cpufreq support\n"); 1035 goto exit_error; 1036 } 1037 1038 if (allow_clk_suspend(info)) { 1039 dev_info(&pdev->dev, "clock idle support enabled\n"); 1040 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); 1041 } 1042 1043 pr_debug("initialised ok\n"); 1044 return 0; 1045 1046 exit_error: 1047 s3c24xx_nand_remove(pdev); 1048 1049 if (err == 0) 1050 err = -EINVAL; 1051 return err; 1052} 1053 1054/* PM Support */ 1055#ifdef CONFIG_PM 1056 1057static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm) 1058{ 1059 struct s3c2410_nand_info *info = platform_get_drvdata(dev); 1060 1061 if (info) { 1062 info->save_sel = readl(info->sel_reg); 1063 1064 /* For the moment, we must ensure nFCE is high during 1065 * the time we are suspended. This really should be 1066 * handled by suspending the MTDs we are using, but 1067 * that is currently not the case. */ 1068 1069 writel(info->save_sel | info->sel_bit, info->sel_reg); 1070 1071 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); 1072 } 1073 1074 return 0; 1075} 1076 1077static int s3c24xx_nand_resume(struct platform_device *dev) 1078{ 1079 struct s3c2410_nand_info *info = platform_get_drvdata(dev); 1080 unsigned long sel; 1081 1082 if (info) { 1083 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); 1084 s3c2410_nand_inithw(info); 1085 1086 /* Restore the state of the nFCE line. */ 1087 1088 sel = readl(info->sel_reg); 1089 sel &= ~info->sel_bit; 1090 sel |= info->save_sel & info->sel_bit; 1091 writel(sel, info->sel_reg); 1092 1093 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); 1094 } 1095 1096 return 0; 1097} 1098 1099#else 1100#define s3c24xx_nand_suspend NULL 1101#define s3c24xx_nand_resume NULL 1102#endif 1103 1104/* driver device registration */ 1105 1106static struct platform_device_id s3c24xx_driver_ids[] = { 1107 { 1108 .name = "s3c2410-nand", 1109 .driver_data = TYPE_S3C2410, 1110 }, { 1111 .name = "s3c2440-nand", 1112 .driver_data = TYPE_S3C2440, 1113 }, { 1114 .name = "s3c2412-nand", 1115 .driver_data = TYPE_S3C2412, 1116 }, { 1117 .name = "s3c6400-nand", 1118 .driver_data = TYPE_S3C2412, /* compatible with 2412 */ 1119 }, 1120 { } 1121}; 1122 1123MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); 1124 1125static struct platform_driver s3c24xx_nand_driver = { 1126 .probe = s3c24xx_nand_probe, 1127 .remove = s3c24xx_nand_remove, 1128 .suspend = s3c24xx_nand_suspend, 1129 .resume = s3c24xx_nand_resume, 1130 .id_table = s3c24xx_driver_ids, 1131 .driver = { 1132 .name = "s3c24xx-nand", 1133 .owner = THIS_MODULE, 1134 }, 1135}; 1136 1137static int __init s3c2410_nand_init(void) 1138{ 1139 printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n"); 1140 1141 return platform_driver_register(&s3c24xx_nand_driver); 1142} 1143 1144static void __exit s3c2410_nand_exit(void) 1145{ 1146 platform_driver_unregister(&s3c24xx_nand_driver); 1147} 1148 1149module_init(s3c2410_nand_init); 1150module_exit(s3c2410_nand_exit); 1151 1152MODULE_LICENSE("GPL"); 1153MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 1154MODULE_DESCRIPTION("S3C24XX MTD NAND driver"); 1155