s3c2410.c revision 5bd34c091a044d130601370c370f84b1c59f1627
1/* linux/drivers/mtd/nand/s3c2410.c 2 * 3 * Copyright (c) 2004,2005 Simtec Electronics 4 * http://www.simtec.co.uk/products/SWLINUX/ 5 * Ben Dooks <ben@simtec.co.uk> 6 * 7 * Samsung S3C2410/S3C240 NAND driver 8 * 9 * Changelog: 10 * 21-Sep-2004 BJD Initial version 11 * 23-Sep-2004 BJD Mulitple device support 12 * 28-Sep-2004 BJD Fixed ECC placement for Hardware mode 13 * 12-Oct-2004 BJD Fixed errors in use of platform data 14 * 18-Feb-2005 BJD Fix sparse errors 15 * 14-Mar-2005 BJD Applied tglx's code reduction patch 16 * 02-May-2005 BJD Fixed s3c2440 support 17 * 02-May-2005 BJD Reduced hwcontrol decode 18 * 20-Jun-2005 BJD Updated s3c2440 support, fixed timing bug 19 * 08-Jul-2005 BJD Fix OOPS when no platform data supplied 20 * 20-Oct-2005 BJD Fix timing calculation bug 21 * 22 * $Id: s3c2410.c,v 1.20 2005/11/07 11:14:31 gleixner Exp $ 23 * 24 * This program is free software; you can redistribute it and/or modify 25 * it under the terms of the GNU General Public License as published by 26 * the Free Software Foundation; either version 2 of the License, or 27 * (at your option) any later version. 28 * 29 * This program is distributed in the hope that it will be useful, 30 * but WITHOUT ANY WARRANTY; without even the implied warranty of 31 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 32 * GNU General Public License for more details. 33 * 34 * You should have received a copy of the GNU General Public License 35 * along with this program; if not, write to the Free Software 36 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 37*/ 38 39#include <config/mtd/nand/s3c2410/hwecc.h> 40#include <config/mtd/nand/s3c2410/debug.h> 41 42#ifdef CONFIG_MTD_NAND_S3C2410_DEBUG 43#define DEBUG 44#endif 45 46#include <linux/module.h> 47#include <linux/types.h> 48#include <linux/init.h> 49#include <linux/kernel.h> 50#include <linux/string.h> 51#include <linux/ioport.h> 52#include <linux/platform_device.h> 53#include <linux/delay.h> 54#include <linux/err.h> 55#include <linux/slab.h> 56#include <linux/clk.h> 57 58#include <linux/mtd/mtd.h> 59#include <linux/mtd/nand.h> 60#include <linux/mtd/nand_ecc.h> 61#include <linux/mtd/partitions.h> 62 63#include <asm/io.h> 64 65#include <asm/arch/regs-nand.h> 66#include <asm/arch/nand.h> 67 68#define PFX "s3c2410-nand: " 69 70#ifdef CONFIG_MTD_NAND_S3C2410_HWECC 71static int hardware_ecc = 1; 72#else 73static int hardware_ecc = 0; 74#endif 75 76/* new oob placement block for use with hardware ecc generation 77 */ 78 79static struct nand_ecclayout nand_hw_eccoob = { 80 .eccbytes = 3, 81 .eccpos = {0, 1, 2}, 82 .oobfree = {{8, 8}} 83}; 84 85/* controller and mtd information */ 86 87struct s3c2410_nand_info; 88 89struct s3c2410_nand_mtd { 90 struct mtd_info mtd; 91 struct nand_chip chip; 92 struct s3c2410_nand_set *set; 93 struct s3c2410_nand_info *info; 94 int scan_res; 95}; 96 97/* overview of the s3c2410 nand state */ 98 99struct s3c2410_nand_info { 100 /* mtd info */ 101 struct nand_hw_control controller; 102 struct s3c2410_nand_mtd *mtds; 103 struct s3c2410_platform_nand *platform; 104 105 /* device info */ 106 struct device *device; 107 struct resource *area; 108 struct clk *clk; 109 void __iomem *regs; 110 int mtd_count; 111 112 unsigned char is_s3c2440; 113}; 114 115/* conversion functions */ 116 117static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd) 118{ 119 return container_of(mtd, struct s3c2410_nand_mtd, mtd); 120} 121 122static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd) 123{ 124 return s3c2410_nand_mtd_toours(mtd)->info; 125} 126 127static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev) 128{ 129 return platform_get_drvdata(dev); 130} 131 132static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) 133{ 134 return dev->dev.platform_data; 135} 136 137/* timing calculations */ 138 139#define NS_IN_KHZ 1000000 140 141static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max) 142{ 143 int result; 144 145 result = (wanted * clk) / NS_IN_KHZ; 146 result++; 147 148 pr_debug("result %d from %ld, %d\n", result, clk, wanted); 149 150 if (result > max) { 151 printk("%d ns is too big for current clock rate %ld\n", wanted, clk); 152 return -1; 153 } 154 155 if (result < 1) 156 result = 1; 157 158 return result; 159} 160 161#define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk)) 162 163/* controller setup */ 164 165static int s3c2410_nand_inithw(struct s3c2410_nand_info *info, struct platform_device *pdev) 166{ 167 struct s3c2410_platform_nand *plat = to_nand_plat(pdev); 168 unsigned long clkrate = clk_get_rate(info->clk); 169 int tacls, twrph0, twrph1; 170 unsigned long cfg; 171 172 /* calculate the timing information for the controller */ 173 174 clkrate /= 1000; /* turn clock into kHz for ease of use */ 175 176 if (plat != NULL) { 177 tacls = s3c2410_nand_calc_rate(plat->tacls, clkrate, 4); 178 twrph0 = s3c2410_nand_calc_rate(plat->twrph0, clkrate, 8); 179 twrph1 = s3c2410_nand_calc_rate(plat->twrph1, clkrate, 8); 180 } else { 181 /* default timings */ 182 tacls = 4; 183 twrph0 = 8; 184 twrph1 = 8; 185 } 186 187 if (tacls < 0 || twrph0 < 0 || twrph1 < 0) { 188 printk(KERN_ERR PFX "cannot get timings suitable for board\n"); 189 return -EINVAL; 190 } 191 192 printk(KERN_INFO PFX "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", 193 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate)); 194 195 if (!info->is_s3c2440) { 196 cfg = S3C2410_NFCONF_EN; 197 cfg |= S3C2410_NFCONF_TACLS(tacls - 1); 198 cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); 199 cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); 200 } else { 201 cfg = S3C2440_NFCONF_TACLS(tacls - 1); 202 cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1); 203 cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1); 204 } 205 206 pr_debug(PFX "NF_CONF is 0x%lx\n", cfg); 207 208 writel(cfg, info->regs + S3C2410_NFCONF); 209 return 0; 210} 211 212/* select chip */ 213 214static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) 215{ 216 struct s3c2410_nand_info *info; 217 struct s3c2410_nand_mtd *nmtd; 218 struct nand_chip *this = mtd->priv; 219 void __iomem *reg; 220 unsigned long cur; 221 unsigned long bit; 222 223 nmtd = this->priv; 224 info = nmtd->info; 225 226 bit = (info->is_s3c2440) ? S3C2440_NFCONT_nFCE : S3C2410_NFCONF_nFCE; 227 reg = info->regs + ((info->is_s3c2440) ? S3C2440_NFCONT : S3C2410_NFCONF); 228 229 cur = readl(reg); 230 231 if (chip == -1) { 232 cur |= bit; 233 } else { 234 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) { 235 printk(KERN_ERR PFX "chip %d out of range\n", chip); 236 return; 237 } 238 239 if (info->platform != NULL) { 240 if (info->platform->select_chip != NULL) 241 (info->platform->select_chip) (nmtd->set, chip); 242 } 243 244 cur &= ~bit; 245 } 246 247 writel(cur, reg); 248} 249 250/* command and control functions 251 * 252 * Note, these all use tglx's method of changing the IO_ADDR_W field 253 * to make the code simpler, and use the nand layer's code to issue the 254 * command and address sequences via the proper IO ports. 255 * 256*/ 257 258static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd, 259 unsigend int ctrl) 260{ 261 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 262 struct nand_chip *chip = mtd->priv; 263 264 if (cmd == NAND_CMD_NONE) 265 return; 266 267 if (cmd & NAND_CLE) 268 writeb(cmd, info->regs + S3C2410_NFCMD); 269 else 270 writeb(cmd, info->regs + S3C2410_NFADDR); 271} 272 273/* command and control functions */ 274 275static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd, 276 unsigend int ctrl) 277{ 278 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 279 struct nand_chip *chip = mtd->priv; 280 281 if (cmd == NAND_CMD_NONE) 282 return; 283 284 if (cmd & NAND_CLE) 285 writeb(cmd, info->regs + S3C2440_NFCMD); 286 else 287 writeb(cmd, info->regs + S3C2440_NFADDR); 288} 289 290/* s3c2410_nand_devready() 291 * 292 * returns 0 if the nand is busy, 1 if it is ready 293*/ 294 295static int s3c2410_nand_devready(struct mtd_info *mtd) 296{ 297 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 298 299 if (info->is_s3c2440) 300 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; 301 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; 302} 303 304/* ECC handling functions */ 305 306static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) 307{ 308 pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n", mtd, dat, read_ecc, calc_ecc); 309 310 pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n", 311 read_ecc[0], read_ecc[1], read_ecc[2], calc_ecc[0], calc_ecc[1], calc_ecc[2]); 312 313 if (read_ecc[0] == calc_ecc[0] && read_ecc[1] == calc_ecc[1] && read_ecc[2] == calc_ecc[2]) 314 return 0; 315 316 /* we curently have no method for correcting the error */ 317 318 return -1; 319} 320 321/* ECC functions 322 * 323 * These allow the s3c2410 and s3c2440 to use the controller's ECC 324 * generator block to ECC the data as it passes through] 325*/ 326 327static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) 328{ 329 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 330 unsigned long ctrl; 331 332 ctrl = readl(info->regs + S3C2410_NFCONF); 333 ctrl |= S3C2410_NFCONF_INITECC; 334 writel(ctrl, info->regs + S3C2410_NFCONF); 335} 336 337static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) 338{ 339 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 340 unsigned long ctrl; 341 342 ctrl = readl(info->regs + S3C2440_NFCONT); 343 writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); 344} 345 346static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) 347{ 348 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 349 350 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0); 351 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); 352 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); 353 354 pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]); 355 356 return 0; 357} 358 359static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) 360{ 361 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 362 unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); 363 364 ecc_code[0] = ecc; 365 ecc_code[1] = ecc >> 8; 366 ecc_code[2] = ecc >> 16; 367 368 pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]); 369 370 return 0; 371} 372 373/* over-ride the standard functions for a little more speed. We can 374 * use read/write block to move the data buffers to/from the controller 375*/ 376 377static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) 378{ 379 struct nand_chip *this = mtd->priv; 380 readsb(this->IO_ADDR_R, buf, len); 381} 382 383static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) 384{ 385 struct nand_chip *this = mtd->priv; 386 writesb(this->IO_ADDR_W, buf, len); 387} 388 389/* device management functions */ 390 391static int s3c2410_nand_remove(struct platform_device *pdev) 392{ 393 struct s3c2410_nand_info *info = to_nand_info(pdev); 394 395 platform_set_drvdata(pdev, NULL); 396 397 if (info == NULL) 398 return 0; 399 400 /* first thing we need to do is release all our mtds 401 * and their partitions, then go through freeing the 402 * resources used 403 */ 404 405 if (info->mtds != NULL) { 406 struct s3c2410_nand_mtd *ptr = info->mtds; 407 int mtdno; 408 409 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) { 410 pr_debug("releasing mtd %d (%p)\n", mtdno, ptr); 411 nand_release(&ptr->mtd); 412 } 413 414 kfree(info->mtds); 415 } 416 417 /* free the common resources */ 418 419 if (info->clk != NULL && !IS_ERR(info->clk)) { 420 clk_disable(info->clk); 421 clk_put(info->clk); 422 } 423 424 if (info->regs != NULL) { 425 iounmap(info->regs); 426 info->regs = NULL; 427 } 428 429 if (info->area != NULL) { 430 release_resource(info->area); 431 kfree(info->area); 432 info->area = NULL; 433 } 434 435 kfree(info); 436 437 return 0; 438} 439 440#ifdef CONFIG_MTD_PARTITIONS 441static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, 442 struct s3c2410_nand_mtd *mtd, 443 struct s3c2410_nand_set *set) 444{ 445 if (set == NULL) 446 return add_mtd_device(&mtd->mtd); 447 448 if (set->nr_partitions > 0 && set->partitions != NULL) { 449 return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions); 450 } 451 452 return add_mtd_device(&mtd->mtd); 453} 454#else 455static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, 456 struct s3c2410_nand_mtd *mtd, 457 struct s3c2410_nand_set *set) 458{ 459 return add_mtd_device(&mtd->mtd); 460} 461#endif 462 463/* s3c2410_nand_init_chip 464 * 465 * init a single instance of an chip 466*/ 467 468static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, 469 struct s3c2410_nand_mtd *nmtd, 470 struct s3c2410_nand_set *set) 471{ 472 struct nand_chip *chip = &nmtd->chip; 473 474 chip->IO_ADDR_R = info->regs + S3C2410_NFDATA; 475 chip->IO_ADDR_W = info->regs + S3C2410_NFDATA; 476 chip->cmd_ctrl = s3c2410_nand_hwcontrol; 477 chip->dev_ready = s3c2410_nand_devready; 478 chip->write_buf = s3c2410_nand_write_buf; 479 chip->read_buf = s3c2410_nand_read_buf; 480 chip->select_chip = s3c2410_nand_select_chip; 481 chip->chip_delay = 50; 482 chip->priv = nmtd; 483 chip->options = 0; 484 chip->controller = &info->controller; 485 486 if (info->is_s3c2440) { 487 chip->IO_ADDR_R = info->regs + S3C2440_NFDATA; 488 chip->IO_ADDR_W = info->regs + S3C2440_NFDATA; 489 chip->cmd_ctrl = s3c2440_nand_hwcontrol; 490 } 491 492 nmtd->info = info; 493 nmtd->mtd.priv = chip; 494 nmtd->mtd.owner = THIS_MODULE; 495 nmtd->set = set; 496 497 if (hardware_ecc) { 498 chip->ecc.correct = s3c2410_nand_correct_data; 499 chip->ecc.hwctl = s3c2410_nand_enable_hwecc; 500 chip->ecc.calculate = s3c2410_nand_calculate_ecc; 501 chip->ecc.mode = NAND_ECC_HW; 502 chip->ecc.size = 512; 503 chip->ecc.bytes = 3; 504 chip->ecc.layout = &nand_hw_eccoob; 505 506 if (info->is_s3c2440) { 507 chip->ecc.hwctl = s3c2440_nand_enable_hwecc; 508 chip->ecc.calculate = s3c2440_nand_calculate_ecc; 509 } 510 } else { 511 chip->ecc.mode = NAND_ECC_SOFT; 512 } 513} 514 515/* s3c2410_nand_probe 516 * 517 * called by device layer when it finds a device matching 518 * one our driver can handled. This code checks to see if 519 * it can allocate all necessary resources then calls the 520 * nand layer to look for devices 521*/ 522 523static int s3c24xx_nand_probe(struct platform_device *pdev, int is_s3c2440) 524{ 525 struct s3c2410_platform_nand *plat = to_nand_plat(pdev); 526 struct s3c2410_nand_info *info; 527 struct s3c2410_nand_mtd *nmtd; 528 struct s3c2410_nand_set *sets; 529 struct resource *res; 530 int err = 0; 531 int size; 532 int nr_sets; 533 int setno; 534 535 pr_debug("s3c2410_nand_probe(%p)\n", pdev); 536 537 info = kmalloc(sizeof(*info), GFP_KERNEL); 538 if (info == NULL) { 539 dev_err(&pdev->dev, "no memory for flash info\n"); 540 err = -ENOMEM; 541 goto exit_error; 542 } 543 544 memzero(info, sizeof(*info)); 545 platform_set_drvdata(pdev, info); 546 547 spin_lock_init(&info->controller.lock); 548 init_waitqueue_head(&info->controller.wq); 549 550 /* get the clock source and enable it */ 551 552 info->clk = clk_get(&pdev->dev, "nand"); 553 if (IS_ERR(info->clk)) { 554 dev_err(&pdev->dev, "failed to get clock"); 555 err = -ENOENT; 556 goto exit_error; 557 } 558 559 clk_enable(info->clk); 560 561 /* allocate and map the resource */ 562 563 /* currently we assume we have the one resource */ 564 res = pdev->resource; 565 size = res->end - res->start + 1; 566 567 info->area = request_mem_region(res->start, size, pdev->name); 568 569 if (info->area == NULL) { 570 dev_err(&pdev->dev, "cannot reserve register region\n"); 571 err = -ENOENT; 572 goto exit_error; 573 } 574 575 info->device = &pdev->dev; 576 info->platform = plat; 577 info->regs = ioremap(res->start, size); 578 info->is_s3c2440 = is_s3c2440; 579 580 if (info->regs == NULL) { 581 dev_err(&pdev->dev, "cannot reserve register region\n"); 582 err = -EIO; 583 goto exit_error; 584 } 585 586 dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs); 587 588 /* initialise the hardware */ 589 590 err = s3c2410_nand_inithw(info, pdev); 591 if (err != 0) 592 goto exit_error; 593 594 sets = (plat != NULL) ? plat->sets : NULL; 595 nr_sets = (plat != NULL) ? plat->nr_sets : 1; 596 597 info->mtd_count = nr_sets; 598 599 /* allocate our information */ 600 601 size = nr_sets * sizeof(*info->mtds); 602 info->mtds = kmalloc(size, GFP_KERNEL); 603 if (info->mtds == NULL) { 604 dev_err(&pdev->dev, "failed to allocate mtd storage\n"); 605 err = -ENOMEM; 606 goto exit_error; 607 } 608 609 memzero(info->mtds, size); 610 611 /* initialise all possible chips */ 612 613 nmtd = info->mtds; 614 615 for (setno = 0; setno < nr_sets; setno++, nmtd++) { 616 pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info); 617 618 s3c2410_nand_init_chip(info, nmtd, sets); 619 620 nmtd->scan_res = nand_scan(&nmtd->mtd, (sets) ? sets->nr_chips : 1); 621 622 if (nmtd->scan_res == 0) { 623 s3c2410_nand_add_partition(info, nmtd, sets); 624 } 625 626 if (sets != NULL) 627 sets++; 628 } 629 630 pr_debug("initialised ok\n"); 631 return 0; 632 633 exit_error: 634 s3c2410_nand_remove(pdev); 635 636 if (err == 0) 637 err = -EINVAL; 638 return err; 639} 640 641/* driver device registration */ 642 643static int s3c2410_nand_probe(struct platform_device *dev) 644{ 645 return s3c24xx_nand_probe(dev, 0); 646} 647 648static int s3c2440_nand_probe(struct platform_device *dev) 649{ 650 return s3c24xx_nand_probe(dev, 1); 651} 652 653static struct platform_driver s3c2410_nand_driver = { 654 .probe = s3c2410_nand_probe, 655 .remove = s3c2410_nand_remove, 656 .driver = { 657 .name = "s3c2410-nand", 658 .owner = THIS_MODULE, 659 }, 660}; 661 662static struct platform_driver s3c2440_nand_driver = { 663 .probe = s3c2440_nand_probe, 664 .remove = s3c2410_nand_remove, 665 .driver = { 666 .name = "s3c2440-nand", 667 .owner = THIS_MODULE, 668 }, 669}; 670 671static int __init s3c2410_nand_init(void) 672{ 673 printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n"); 674 675 platform_driver_register(&s3c2440_nand_driver); 676 return platform_driver_register(&s3c2410_nand_driver); 677} 678 679static void __exit s3c2410_nand_exit(void) 680{ 681 platform_driver_unregister(&s3c2440_nand_driver); 682 platform_driver_unregister(&s3c2410_nand_driver); 683} 684 685module_init(s3c2410_nand_init); 686module_exit(s3c2410_nand_exit); 687 688MODULE_LICENSE("GPL"); 689MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 690MODULE_DESCRIPTION("S3C24XX MTD NAND driver"); 691