s3c2410.c revision a4f957f16d41b9ff944dddd84c4892496a129f68
1/* linux/drivers/mtd/nand/s3c2410.c 2 * 3 * Copyright (c) 2004,2005 Simtec Electronics 4 * http://www.simtec.co.uk/products/SWLINUX/ 5 * Ben Dooks <ben@simtec.co.uk> 6 * 7 * Samsung S3C2410/S3C240 NAND driver 8 * 9 * Changelog: 10 * 21-Sep-2004 BJD Initial version 11 * 23-Sep-2004 BJD Mulitple device support 12 * 28-Sep-2004 BJD Fixed ECC placement for Hardware mode 13 * 12-Oct-2004 BJD Fixed errors in use of platform data 14 * 18-Feb-2005 BJD Fix sparse errors 15 * 14-Mar-2005 BJD Applied tglx's code reduction patch 16 * 02-May-2005 BJD Fixed s3c2440 support 17 * 02-May-2005 BJD Reduced hwcontrol decode 18 * 20-Jun-2005 BJD Updated s3c2440 support, fixed timing bug 19 * 20 * $Id: s3c2410.c,v 1.13 2005/06/20 11:48:21 bjd Exp $ 21 * 22 * This program is free software; you can redistribute it and/or modify 23 * it under the terms of the GNU General Public License as published by 24 * the Free Software Foundation; either version 2 of the License, or 25 * (at your option) any later version. 26 * 27 * This program is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 30 * GNU General Public License for more details. 31 * 32 * You should have received a copy of the GNU General Public License 33 * along with this program; if not, write to the Free Software 34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 35*/ 36 37#include <config/mtd/nand/s3c2410/hwecc.h> 38#include <config/mtd/nand/s3c2410/debug.h> 39 40#ifdef CONFIG_MTD_NAND_S3C2410_DEBUG 41#define DEBUG 42#endif 43 44#include <linux/module.h> 45#include <linux/types.h> 46#include <linux/init.h> 47#include <linux/kernel.h> 48#include <linux/string.h> 49#include <linux/ioport.h> 50#include <linux/device.h> 51#include <linux/delay.h> 52#include <linux/err.h> 53 54#include <linux/mtd/mtd.h> 55#include <linux/mtd/nand.h> 56#include <linux/mtd/nand_ecc.h> 57#include <linux/mtd/partitions.h> 58 59#include <asm/io.h> 60#include <asm/mach-types.h> 61#include <asm/hardware/clock.h> 62 63#include <asm/arch/regs-nand.h> 64#include <asm/arch/nand.h> 65 66#define PFX "s3c2410-nand: " 67 68#ifdef CONFIG_MTD_NAND_S3C2410_HWECC 69static int hardware_ecc = 1; 70#else 71static int hardware_ecc = 0; 72#endif 73 74/* new oob placement block for use with hardware ecc generation 75 */ 76 77static struct nand_oobinfo nand_hw_eccoob = { 78 .useecc = MTD_NANDECC_AUTOPLACE, 79 .eccbytes = 3, 80 .eccpos = {0, 1, 2 }, 81 .oobfree = { {8, 8} } 82}; 83 84/* controller and mtd information */ 85 86struct s3c2410_nand_info; 87 88struct s3c2410_nand_mtd { 89 struct mtd_info mtd; 90 struct nand_chip chip; 91 struct s3c2410_nand_set *set; 92 struct s3c2410_nand_info *info; 93 int scan_res; 94}; 95 96/* overview of the s3c2410 nand state */ 97 98struct s3c2410_nand_info { 99 /* mtd info */ 100 struct nand_hw_control controller; 101 struct s3c2410_nand_mtd *mtds; 102 struct s3c2410_platform_nand *platform; 103 104 /* device info */ 105 struct device *device; 106 struct resource *area; 107 struct clk *clk; 108 void __iomem *regs; 109 int mtd_count; 110 111 unsigned char is_s3c2440; 112}; 113 114/* conversion functions */ 115 116static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd) 117{ 118 return container_of(mtd, struct s3c2410_nand_mtd, mtd); 119} 120 121static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd) 122{ 123 return s3c2410_nand_mtd_toours(mtd)->info; 124} 125 126static struct s3c2410_nand_info *to_nand_info(struct device *dev) 127{ 128 return dev_get_drvdata(dev); 129} 130 131static struct s3c2410_platform_nand *to_nand_plat(struct device *dev) 132{ 133 return dev->platform_data; 134} 135 136/* timing calculations */ 137 138#define NS_IN_KHZ 10000000 139 140static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max) 141{ 142 int result; 143 144 result = (wanted * NS_IN_KHZ) / clk; 145 result++; 146 147 pr_debug("result %d from %ld, %d\n", result, clk, wanted); 148 149 if (result > max) { 150 printk("%d ns is too big for current clock rate %ld\n", 151 wanted, clk); 152 return -1; 153 } 154 155 if (result < 1) 156 result = 1; 157 158 return result; 159} 160 161#define to_ns(ticks,clk) (((clk) * (ticks)) / NS_IN_KHZ) 162 163/* controller setup */ 164 165static int s3c2410_nand_inithw(struct s3c2410_nand_info *info, 166 struct device *dev) 167{ 168 struct s3c2410_platform_nand *plat = to_nand_plat(dev); 169 unsigned int tacls, twrph0, twrph1; 170 unsigned long clkrate = clk_get_rate(info->clk); 171 unsigned long cfg; 172 173 /* calculate the timing information for the controller */ 174 175 if (plat != NULL) { 176 tacls = s3c2410_nand_calc_rate(plat->tacls, clkrate, 4); 177 twrph0 = s3c2410_nand_calc_rate(plat->twrph0, clkrate, 8); 178 twrph1 = s3c2410_nand_calc_rate(plat->twrph1, clkrate, 8); 179 } else { 180 /* default timings */ 181 tacls = 4; 182 twrph0 = 8; 183 twrph1 = 8; 184 } 185 186 if (tacls < 0 || twrph0 < 0 || twrph1 < 0) { 187 printk(KERN_ERR PFX "cannot get timings suitable for board\n"); 188 return -EINVAL; 189 } 190 191 printk(KERN_INFO PFX "timing: Tacls %ldns, Twrph0 %ldns, Twrph1 %ldns\n", 192 to_ns(tacls, clkrate), 193 to_ns(twrph0, clkrate), 194 to_ns(twrph1, clkrate)); 195 196 if (!info->is_s3c2440) { 197 cfg = S3C2410_NFCONF_EN; 198 cfg |= S3C2410_NFCONF_TACLS(tacls-1); 199 cfg |= S3C2410_NFCONF_TWRPH0(twrph0-1); 200 cfg |= S3C2410_NFCONF_TWRPH1(twrph1-1); 201 } else { 202 cfg = S3C2440_NFCONF_TACLS(tacls-1); 203 cfg |= S3C2440_NFCONF_TWRPH0(twrph0-1); 204 cfg |= S3C2440_NFCONF_TWRPH1(twrph1-1); 205 } 206 207 pr_debug(PFX "NF_CONF is 0x%lx\n", cfg); 208 209 writel(cfg, info->regs + S3C2410_NFCONF); 210 return 0; 211} 212 213/* select chip */ 214 215static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) 216{ 217 struct s3c2410_nand_info *info; 218 struct s3c2410_nand_mtd *nmtd; 219 struct nand_chip *this = mtd->priv; 220 void __iomem *reg; 221 unsigned long cur; 222 unsigned long bit; 223 224 nmtd = this->priv; 225 info = nmtd->info; 226 227 bit = (info->is_s3c2440) ? S3C2440_NFCONT_nFCE : S3C2410_NFCONF_nFCE; 228 reg = info->regs+((info->is_s3c2440) ? S3C2440_NFCONT:S3C2410_NFCONF); 229 230 cur = readl(reg); 231 232 if (chip == -1) { 233 cur |= bit; 234 } else { 235 if (chip > nmtd->set->nr_chips) { 236 printk(KERN_ERR PFX "chip %d out of range\n", chip); 237 return; 238 } 239 240 if (info->platform != NULL) { 241 if (info->platform->select_chip != NULL) 242 (info->platform->select_chip)(nmtd->set, chip); 243 } 244 245 cur &= ~bit; 246 } 247 248 writel(cur, reg); 249} 250 251/* command and control functions 252 * 253 * Note, these all use tglx's method of changing the IO_ADDR_W field 254 * to make the code simpler, and use the nand layer's code to issue the 255 * command and address sequences via the proper IO ports. 256 * 257*/ 258 259static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd) 260{ 261 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 262 struct nand_chip *chip = mtd->priv; 263 264 switch (cmd) { 265 case NAND_CTL_SETNCE: 266 case NAND_CTL_CLRNCE: 267 printk(KERN_ERR "%s: called for NCE\n", __FUNCTION__); 268 break; 269 270 case NAND_CTL_SETCLE: 271 chip->IO_ADDR_W = info->regs + S3C2410_NFCMD; 272 break; 273 274 case NAND_CTL_SETALE: 275 chip->IO_ADDR_W = info->regs + S3C2410_NFADDR; 276 break; 277 278 /* NAND_CTL_CLRCLE: */ 279 /* NAND_CTL_CLRALE: */ 280 default: 281 chip->IO_ADDR_W = info->regs + S3C2410_NFDATA; 282 break; 283 } 284} 285 286/* command and control functions */ 287 288static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd) 289{ 290 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 291 struct nand_chip *chip = mtd->priv; 292 293 switch (cmd) { 294 case NAND_CTL_SETNCE: 295 case NAND_CTL_CLRNCE: 296 printk(KERN_ERR "%s: called for NCE\n", __FUNCTION__); 297 break; 298 299 case NAND_CTL_SETCLE: 300 chip->IO_ADDR_W = info->regs + S3C2440_NFCMD; 301 break; 302 303 case NAND_CTL_SETALE: 304 chip->IO_ADDR_W = info->regs + S3C2440_NFADDR; 305 break; 306 307 /* NAND_CTL_CLRCLE: */ 308 /* NAND_CTL_CLRALE: */ 309 default: 310 chip->IO_ADDR_W = info->regs + S3C2440_NFDATA; 311 break; 312 } 313} 314 315/* s3c2410_nand_devready() 316 * 317 * returns 0 if the nand is busy, 1 if it is ready 318*/ 319 320static int s3c2410_nand_devready(struct mtd_info *mtd) 321{ 322 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 323 324 if (info->is_s3c2440) 325 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; 326 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; 327} 328 329 330/* ECC handling functions */ 331 332static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, 333 u_char *read_ecc, u_char *calc_ecc) 334{ 335 pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n", 336 mtd, dat, read_ecc, calc_ecc); 337 338 pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n", 339 read_ecc[0], read_ecc[1], read_ecc[2], 340 calc_ecc[0], calc_ecc[1], calc_ecc[2]); 341 342 if (read_ecc[0] == calc_ecc[0] && 343 read_ecc[1] == calc_ecc[1] && 344 read_ecc[2] == calc_ecc[2]) 345 return 0; 346 347 /* we curently have no method for correcting the error */ 348 349 return -1; 350} 351 352/* ECC functions 353 * 354 * These allow the s3c2410 and s3c2440 to use the controller's ECC 355 * generator block to ECC the data as it passes through] 356*/ 357 358static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) 359{ 360 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 361 unsigned long ctrl; 362 363 ctrl = readl(info->regs + S3C2410_NFCONF); 364 ctrl |= S3C2410_NFCONF_INITECC; 365 writel(ctrl, info->regs + S3C2410_NFCONF); 366} 367 368static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) 369{ 370 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 371 unsigned long ctrl; 372 373 ctrl = readl(info->regs + S3C2440_NFCONT); 374 writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); 375} 376 377static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, 378 const u_char *dat, u_char *ecc_code) 379{ 380 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 381 382 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0); 383 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); 384 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); 385 386 pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", 387 ecc_code[0], ecc_code[1], ecc_code[2]); 388 389 return 0; 390} 391 392 393static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, 394 const u_char *dat, u_char *ecc_code) 395{ 396 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 397 unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); 398 399 ecc_code[0] = ecc; 400 ecc_code[1] = ecc >> 8; 401 ecc_code[2] = ecc >> 16; 402 403 pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", 404 ecc_code[0], ecc_code[1], ecc_code[2]); 405 406 return 0; 407} 408 409 410/* over-ride the standard functions for a little more speed. We can 411 * use read/write block to move the data buffers to/from the controller 412*/ 413 414static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) 415{ 416 struct nand_chip *this = mtd->priv; 417 readsb(this->IO_ADDR_R, buf, len); 418} 419 420static void s3c2410_nand_write_buf(struct mtd_info *mtd, 421 const u_char *buf, int len) 422{ 423 struct nand_chip *this = mtd->priv; 424 writesb(this->IO_ADDR_W, buf, len); 425} 426 427/* device management functions */ 428 429static int s3c2410_nand_remove(struct device *dev) 430{ 431 struct s3c2410_nand_info *info = to_nand_info(dev); 432 433 dev_set_drvdata(dev, NULL); 434 435 if (info == NULL) 436 return 0; 437 438 /* first thing we need to do is release all our mtds 439 * and their partitions, then go through freeing the 440 * resources used 441 */ 442 443 if (info->mtds != NULL) { 444 struct s3c2410_nand_mtd *ptr = info->mtds; 445 int mtdno; 446 447 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) { 448 pr_debug("releasing mtd %d (%p)\n", mtdno, ptr); 449 nand_release(&ptr->mtd); 450 } 451 452 kfree(info->mtds); 453 } 454 455 /* free the common resources */ 456 457 if (info->clk != NULL && !IS_ERR(info->clk)) { 458 clk_disable(info->clk); 459 clk_unuse(info->clk); 460 clk_put(info->clk); 461 } 462 463 if (info->regs != NULL) { 464 iounmap(info->regs); 465 info->regs = NULL; 466 } 467 468 if (info->area != NULL) { 469 release_resource(info->area); 470 kfree(info->area); 471 info->area = NULL; 472 } 473 474 kfree(info); 475 476 return 0; 477} 478 479#ifdef CONFIG_MTD_PARTITIONS 480static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, 481 struct s3c2410_nand_mtd *mtd, 482 struct s3c2410_nand_set *set) 483{ 484 if (set == NULL) 485 return add_mtd_device(&mtd->mtd); 486 487 if (set->nr_partitions > 0 && set->partitions != NULL) { 488 return add_mtd_partitions(&mtd->mtd, 489 set->partitions, 490 set->nr_partitions); 491 } 492 493 return add_mtd_device(&mtd->mtd); 494} 495#else 496static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, 497 struct s3c2410_nand_mtd *mtd, 498 struct s3c2410_nand_set *set) 499{ 500 return add_mtd_device(&mtd->mtd); 501} 502#endif 503 504/* s3c2410_nand_init_chip 505 * 506 * init a single instance of an chip 507*/ 508 509static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, 510 struct s3c2410_nand_mtd *nmtd, 511 struct s3c2410_nand_set *set) 512{ 513 struct nand_chip *chip = &nmtd->chip; 514 515 chip->IO_ADDR_R = info->regs + S3C2410_NFDATA; 516 chip->IO_ADDR_W = info->regs + S3C2410_NFDATA; 517 chip->hwcontrol = s3c2410_nand_hwcontrol; 518 chip->dev_ready = s3c2410_nand_devready; 519 chip->write_buf = s3c2410_nand_write_buf; 520 chip->read_buf = s3c2410_nand_read_buf; 521 chip->select_chip = s3c2410_nand_select_chip; 522 chip->chip_delay = 50; 523 chip->priv = nmtd; 524 chip->options = 0; 525 chip->controller = &info->controller; 526 527 if (info->is_s3c2440) { 528 chip->IO_ADDR_R = info->regs + S3C2440_NFDATA; 529 chip->IO_ADDR_W = info->regs + S3C2440_NFDATA; 530 chip->hwcontrol = s3c2440_nand_hwcontrol; 531 } 532 533 nmtd->info = info; 534 nmtd->mtd.priv = chip; 535 nmtd->set = set; 536 537 if (hardware_ecc) { 538 chip->correct_data = s3c2410_nand_correct_data; 539 chip->enable_hwecc = s3c2410_nand_enable_hwecc; 540 chip->calculate_ecc = s3c2410_nand_calculate_ecc; 541 chip->eccmode = NAND_ECC_HW3_512; 542 chip->autooob = &nand_hw_eccoob; 543 544 if (info->is_s3c2440) { 545 chip->enable_hwecc = s3c2440_nand_enable_hwecc; 546 chip->calculate_ecc = s3c2440_nand_calculate_ecc; 547 } 548 } else { 549 chip->eccmode = NAND_ECC_SOFT; 550 } 551} 552 553/* s3c2410_nand_probe 554 * 555 * called by device layer when it finds a device matching 556 * one our driver can handled. This code checks to see if 557 * it can allocate all necessary resources then calls the 558 * nand layer to look for devices 559*/ 560 561static int s3c24xx_nand_probe(struct device *dev, int is_s3c2440) 562{ 563 struct platform_device *pdev = to_platform_device(dev); 564 struct s3c2410_platform_nand *plat = to_nand_plat(dev); 565 struct s3c2410_nand_info *info; 566 struct s3c2410_nand_mtd *nmtd; 567 struct s3c2410_nand_set *sets; 568 struct resource *res; 569 int err = 0; 570 int size; 571 int nr_sets; 572 int setno; 573 574 pr_debug("s3c2410_nand_probe(%p)\n", dev); 575 576 info = kmalloc(sizeof(*info), GFP_KERNEL); 577 if (info == NULL) { 578 printk(KERN_ERR PFX "no memory for flash info\n"); 579 err = -ENOMEM; 580 goto exit_error; 581 } 582 583 memzero(info, sizeof(*info)); 584 dev_set_drvdata(dev, info); 585 586 spin_lock_init(&info->controller.lock); 587 init_waitqueue_head(&info->controller.wq); 588 589 /* get the clock source and enable it */ 590 591 info->clk = clk_get(dev, "nand"); 592 if (IS_ERR(info->clk)) { 593 printk(KERN_ERR PFX "failed to get clock"); 594 err = -ENOENT; 595 goto exit_error; 596 } 597 598 clk_use(info->clk); 599 clk_enable(info->clk); 600 601 /* allocate and map the resource */ 602 603 /* currently we assume we have the one resource */ 604 res = pdev->resource; 605 size = res->end - res->start + 1; 606 607 info->area = request_mem_region(res->start, size, pdev->name); 608 609 if (info->area == NULL) { 610 printk(KERN_ERR PFX "cannot reserve register region\n"); 611 err = -ENOENT; 612 goto exit_error; 613 } 614 615 info->device = dev; 616 info->platform = plat; 617 info->regs = ioremap(res->start, size); 618 info->is_s3c2440 = is_s3c2440; 619 620 if (info->regs == NULL) { 621 printk(KERN_ERR PFX "cannot reserve register region\n"); 622 err = -EIO; 623 goto exit_error; 624 } 625 626 printk(KERN_INFO PFX "mapped registers at %p\n", info->regs); 627 628 /* initialise the hardware */ 629 630 err = s3c2410_nand_inithw(info, dev); 631 if (err != 0) 632 goto exit_error; 633 634 sets = (plat != NULL) ? plat->sets : NULL; 635 nr_sets = (plat != NULL) ? plat->nr_sets : 1; 636 637 info->mtd_count = nr_sets; 638 639 /* allocate our information */ 640 641 size = nr_sets * sizeof(*info->mtds); 642 info->mtds = kmalloc(size, GFP_KERNEL); 643 if (info->mtds == NULL) { 644 printk(KERN_ERR PFX "failed to allocate mtd storage\n"); 645 err = -ENOMEM; 646 goto exit_error; 647 } 648 649 memzero(info->mtds, size); 650 651 /* initialise all possible chips */ 652 653 nmtd = info->mtds; 654 655 for (setno = 0; setno < nr_sets; setno++, nmtd++) { 656 pr_debug("initialising set %d (%p, info %p)\n", 657 setno, nmtd, info); 658 659 s3c2410_nand_init_chip(info, nmtd, sets); 660 661 nmtd->scan_res = nand_scan(&nmtd->mtd, 662 (sets) ? sets->nr_chips : 1); 663 664 if (nmtd->scan_res == 0) { 665 s3c2410_nand_add_partition(info, nmtd, sets); 666 } 667 668 if (sets != NULL) 669 sets++; 670 } 671 672 pr_debug("initialised ok\n"); 673 return 0; 674 675 exit_error: 676 s3c2410_nand_remove(dev); 677 678 if (err == 0) 679 err = -EINVAL; 680 return err; 681} 682 683/* driver device registration */ 684 685static int s3c2410_nand_probe(struct device *dev) 686{ 687 return s3c24xx_nand_probe(dev, 0); 688} 689 690static int s3c2440_nand_probe(struct device *dev) 691{ 692 return s3c24xx_nand_probe(dev, 1); 693} 694 695static struct device_driver s3c2410_nand_driver = { 696 .name = "s3c2410-nand", 697 .bus = &platform_bus_type, 698 .probe = s3c2410_nand_probe, 699 .remove = s3c2410_nand_remove, 700}; 701 702static struct device_driver s3c2440_nand_driver = { 703 .name = "s3c2440-nand", 704 .bus = &platform_bus_type, 705 .probe = s3c2440_nand_probe, 706 .remove = s3c2410_nand_remove, 707}; 708 709static int __init s3c2410_nand_init(void) 710{ 711 printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n"); 712 713 driver_register(&s3c2440_nand_driver); 714 return driver_register(&s3c2410_nand_driver); 715} 716 717static void __exit s3c2410_nand_exit(void) 718{ 719 driver_unregister(&s3c2440_nand_driver); 720 driver_unregister(&s3c2410_nand_driver); 721} 722 723module_init(s3c2410_nand_init); 724module_exit(s3c2410_nand_exit); 725 726MODULE_LICENSE("GPL"); 727MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 728MODULE_DESCRIPTION("S3C24XX MTD NAND driver"); 729