11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef _B44_H 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define _B44_H 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Register layout. (These correspond to struct _bcmenettregs in bcm4400.) */ 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_DEVCTRL 0x0000UL /* Device Control */ 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DEVCTRL_MPM 0x00000040 /* Magic Packet PME Enable (B0 only) */ 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DEVCTRL_PFE 0x00000080 /* Pattern Filtering Enable */ 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DEVCTRL_IPP 0x00000400 /* Internal EPHY Present */ 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DEVCTRL_EPR 0x00008000 /* EPHY Reset */ 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DEVCTRL_PME 0x00001000 /* PHY Mode Enable */ 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DEVCTRL_PMCE 0x00002000 /* PHY Mode Clocks Enable */ 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DEVCTRL_PADDR 0x0007c000 /* PHY Address */ 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DEVCTRL_PADDR_SHIFT 18 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */ 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_WKUP_LEN 0x0010UL /* Wakeup Length */ 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WKUP_LEN_P0_MASK 0x0000007f /* Pattern 0 */ 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WKUP_LEN_D0 0x00000080 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WKUP_LEN_P1_MASK 0x00007f00 /* Pattern 1 */ 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WKUP_LEN_P1_SHIFT 8 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WKUP_LEN_D1 0x00008000 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WKUP_LEN_P2_MASK 0x007f0000 /* Pattern 2 */ 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WKUP_LEN_P2_SHIFT 16 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WKUP_LEN_D2 0x00000000 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WKUP_LEN_P3_MASK 0x7f000000 /* Pattern 3 */ 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WKUP_LEN_P3_SHIFT 24 261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WKUP_LEN_D3 0x80000000 27725ad800b73a71fe91bfd8859f928852de688ea0Gary Zambrano#define WKUP_LEN_DISABLE 0x80808080 28725ad800b73a71fe91bfd8859f928852de688ea0Gary Zambrano#define WKUP_LEN_ENABLE_TWO 0x80800000 29725ad800b73a71fe91bfd8859f928852de688ea0Gary Zambrano#define WKUP_LEN_ENABLE_THREE 0x80000000 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_ISTAT 0x0020UL /* Interrupt Status */ 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ISTAT_LS 0x00000020 /* Link Change (B0 only) */ 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ISTAT_PME 0x00000040 /* Power Management Event */ 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ISTAT_TO 0x00000080 /* General Purpose Timeout */ 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ISTAT_DSCE 0x00000400 /* Descriptor Error */ 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ISTAT_DATAE 0x00000800 /* Data Error */ 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ISTAT_DPE 0x00001000 /* Descr. Protocol Error */ 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */ 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */ 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */ 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ISTAT_RX 0x00010000 /* RX Interrupt */ 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ISTAT_TX 0x01000000 /* TX Interrupt */ 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ISTAT_EMAC 0x04000000 /* EMAC Interrupt */ 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */ 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */ 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ISTAT_ERRORS (ISTAT_DSCE|ISTAT_DATAE|ISTAT_DPE|ISTAT_RDU|ISTAT_RFO|ISTAT_TFU) 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_IMASK 0x0024UL /* Interrupt Mask */ 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IMASK_DEF (ISTAT_ERRORS | ISTAT_TO | ISTAT_RX | ISTAT_TX) 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_GPTIMER 0x0028UL /* General Purpose Timer */ 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_ADDR_LO 0x0088UL /* ENET Address Lo (B0 only) */ 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_ADDR_HI 0x008CUL /* ENET Address Hi (B0 only) */ 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_FILT_ADDR 0x0090UL /* ENET Filter Address */ 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_FILT_DATA 0x0094UL /* ENET Filter Data */ 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TXBURST 0x00A0UL /* TX Max Burst Length */ 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RXBURST 0x00A4UL /* RX Max Burst Length */ 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_MAC_CTRL 0x00A8UL /* MAC Control */ 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */ 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_CTRL_PHY_PDOWN 0x00000004 /* Onchip EPHY Powerdown */ 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_CTRL_PHY_EDET 0x00000008 /* Onchip EPHY Energy Detected */ 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_CTRL_PHY_LEDCTRL 0x000000e0 /* Onchip EPHY LED Control */ 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_CTRL_PHY_LEDCTRL_SHIFT 5 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_MAC_FLOW 0x00ACUL /* MAC Flow Control */ 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_FLOW_RX_HI_WATER 0x000000ff /* Receive FIFO HI Water Mark */ 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */ 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RCV_LAZY 0x0100UL /* Lazy Interrupt Control */ 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RCV_LAZY_TO_MASK 0x00ffffff /* Timeout */ 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RCV_LAZY_FC_MASK 0xff000000 /* Frame Count */ 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RCV_LAZY_FC_SHIFT 24 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_DMATX_CTRL 0x0200UL /* DMA TX Control */ 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_CTRL_ENABLE 0x00000001 /* Enable */ 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_CTRL_SUSPEND 0x00000002 /* Suepend Request */ 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_CTRL_LPBACK 0x00000004 /* Loopback Enable */ 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_CTRL_FAIRPRIOR 0x00000008 /* Fair Priority */ 731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_CTRL_FLUSH 0x00000010 /* Flush Request */ 741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_DMATX_ADDR 0x0204UL /* DMA TX Descriptor Ring Address */ 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_DMATX_PTR 0x0208UL /* DMA TX Last Posted Descriptor */ 761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_DMATX_STAT 0x020CUL /* DMA TX Current Active Desc. + Status */ 771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_STAT_SMASK 0x0000f000 /* State Mask */ 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_STAT_SDISABLED 0x00000000 /* State Disabled */ 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_STAT_SACTIVE 0x00001000 /* State Active */ 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_STAT_SIDLE 0x00002000 /* State Idle Wait */ 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_STAT_SSTOPPED 0x00003000 /* State Stopped */ 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_STAT_SSUSP 0x00004000 /* State Suspend Pending */ 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_STAT_EMASK 0x000f0000 /* Error Mask */ 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_STAT_ENONE 0x00000000 /* Error None */ 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */ 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */ 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */ 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMATX_STAT_FLUSHED 0x00100000 /* Flushed */ 911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_DMARX_CTRL 0x0210UL /* DMA RX Control */ 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMARX_CTRL_ENABLE 0x00000001 /* Enable */ 931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMARX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */ 941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMARX_CTRL_ROSHIFT 1 /* Receive Offset Shift */ 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_DMARX_ADDR 0x0214UL /* DMA RX Descriptor Ring Address */ 961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_DMARX_PTR 0x0218UL /* DMA RX Last Posted Descriptor */ 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_DMARX_STAT 0x021CUL /* DMA RX Current Active Desc. + Status */ 981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMARX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMARX_STAT_SMASK 0x0000f000 /* State Mask */ 1004b512d26f425be1c779c8319249b42ce3c3424d2Thadeu Lima de Souza Cascardo#define DMARX_STAT_SDISABLED 0x00000000 /* State Disabled */ 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMARX_STAT_SACTIVE 0x00001000 /* State Active */ 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMARX_STAT_SIDLE 0x00002000 /* State Idle Wait */ 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMARX_STAT_SSTOPPED 0x00003000 /* State Stopped */ 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMARX_STAT_EMASK 0x000f0000 /* Error Mask */ 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMARX_STAT_ENONE 0x00000000 /* Error None */ 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMARX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ 1071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMARX_STAT_EDFO 0x00020000 /* Error Data FIFO Overflow */ 1081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMARX_STAT_EBEBW 0x00030000 /* Error Bus Error on Buffer Write */ 1091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMARX_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */ 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_DMAFIFO_AD 0x0220UL /* DMA FIFO Diag Address */ 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMAFIFO_AD_OMASK 0x0000ffff /* Offset Mask */ 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMAFIFO_AD_SMASK 0x000f0000 /* Select Mask */ 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMAFIFO_AD_SXDD 0x00000000 /* Select Transmit DMA Data */ 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMAFIFO_AD_SXDP 0x00010000 /* Select Transmit DMA Pointers */ 1151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMAFIFO_AD_SRDD 0x00040000 /* Select Receive DMA Data */ 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMAFIFO_AD_SRDP 0x00050000 /* Select Receive DMA Pointers */ 1171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMAFIFO_AD_SXFD 0x00080000 /* Select Transmit FIFO Data */ 1181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMAFIFO_AD_SXFP 0x00090000 /* Select Transmit FIFO Pointers */ 1191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMAFIFO_AD_SRFD 0x000c0000 /* Select Receive FIFO Data */ 1201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMAFIFO_AD_SRFP 0x000c0000 /* Select Receive FIFO Pointers */ 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_DMAFIFO_LO 0x0224UL /* DMA FIFO Diag Low Data */ 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_DMAFIFO_HI 0x0228UL /* DMA FIFO Diag High Data */ 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RXCONFIG 0x0400UL /* EMAC RX Config */ 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXCONFIG_DBCAST 0x00000001 /* Disable Broadcast */ 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXCONFIG_ALLMULTI 0x00000002 /* Accept All Multicast */ 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXCONFIG_NORX_WHILE_TX 0x00000004 /* Receive Disable While Transmitting */ 1271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXCONFIG_PROMISC 0x00000008 /* Promiscuous Enable */ 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXCONFIG_LPBACK 0x00000010 /* Loopback Enable */ 1291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXCONFIG_FLOW 0x00000020 /* Flow Control Enable */ 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXCONFIG_FLOW_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */ 1311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXCONFIG_RFILT 0x00000080 /* Reject Filter */ 132753f492093da7a40141bfe083073400f518f4c68Michael Buesch#define RXCONFIG_CAM_ABSENT 0x00000100 /* CAM Absent */ 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RXMAXLEN 0x0404UL /* EMAC RX Max Packet Length */ 1341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */ 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_MDIO_CTRL 0x0410UL /* EMAC MDIO Control */ 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDIO_CTRL_MAXF_MASK 0x0000007f /* MDC Frequency */ 1371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDIO_CTRL_PREAMBLE 0x00000080 /* MII Preamble Enable */ 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_MDIO_DATA 0x0414UL /* EMAC MDIO Data */ 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDIO_DATA_DATA 0x0000ffff /* R/W Data */ 1401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDIO_DATA_TA_MASK 0x00030000 /* Turnaround Value */ 1411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDIO_DATA_TA_SHIFT 16 1421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDIO_TA_VALID 2 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDIO_DATA_RA_MASK 0x007c0000 /* Register Address */ 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDIO_DATA_RA_SHIFT 18 1451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDIO_DATA_PMD_MASK 0x0f800000 /* Physical Media Device */ 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDIO_DATA_PMD_SHIFT 23 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDIO_DATA_OP_MASK 0x30000000 /* Opcode */ 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDIO_DATA_OP_SHIFT 28 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDIO_OP_WRITE 1 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDIO_OP_READ 2 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDIO_DATA_SB_MASK 0xc0000000 /* Start Bits */ 1521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDIO_DATA_SB_SHIFT 30 1531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDIO_DATA_SB_START 0x40000000 /* Start Of Frame */ 1541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_EMAC_IMASK 0x0418UL /* EMAC Interrupt Mask */ 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_EMAC_ISTAT 0x041CUL /* EMAC Interrupt Status */ 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */ 1571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EMAC_INT_MIB 0x00000002 /* MIB Interrupt */ 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */ 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_CAM_DATA_LO 0x0420UL /* EMAC CAM Data Low */ 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_CAM_DATA_HI 0x0424UL /* EMAC CAM Data High */ 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CAM_DATA_HI_VALID 0x00010000 /* Valid Bit */ 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_CAM_CTRL 0x0428UL /* EMAC CAM Control */ 1631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CAM_CTRL_ENABLE 0x00000001 /* CAM Enable */ 1641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CAM_CTRL_MSEL 0x00000002 /* Mask Select */ 1651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CAM_CTRL_READ 0x00000004 /* Read */ 1661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CAM_CTRL_WRITE 0x00000008 /* Read */ 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CAM_CTRL_INDEX_MASK 0x003f0000 /* Index Mask */ 1681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CAM_CTRL_INDEX_SHIFT 16 1691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CAM_CTRL_BUSY 0x80000000 /* CAM Busy */ 1701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_ENET_CTRL 0x042CUL /* EMAC ENET Control */ 1711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ENET_CTRL_ENABLE 0x00000001 /* EMAC Enable */ 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ENET_CTRL_DISABLE 0x00000002 /* EMAC Disable */ 1731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ENET_CTRL_SRST 0x00000004 /* EMAC Soft Reset */ 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ENET_CTRL_EPSEL 0x00000008 /* External PHY Select */ 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_CTRL 0x0430UL /* EMAC TX Control */ 1761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TX_CTRL_DUPLEX 0x00000001 /* Full Duplex */ 1771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TX_CTRL_FMODE 0x00000002 /* Flow Mode */ 1781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TX_CTRL_SBENAB 0x00000004 /* Single Backoff Enable */ 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TX_CTRL_SMALL_SLOT 0x00000008 /* Small Slottime */ 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_WMARK 0x0434UL /* EMAC TX Watermark */ 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_MIB_CTRL 0x0438UL /* EMAC MIB Control */ 1821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIB_CTRL_CLR_ON_READ 0x00000001 /* Autoclear on Read */ 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_GOOD_O 0x0500UL /* MIB TX Good Octets */ 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_GOOD_P 0x0504UL /* MIB TX Good Packets */ 1851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_O 0x0508UL /* MIB TX Octets */ 1861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_P 0x050CUL /* MIB TX Packets */ 1871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_BCAST 0x0510UL /* MIB TX Broadcast Packets */ 1881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_MCAST 0x0514UL /* MIB TX Multicast Packets */ 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_64 0x0518UL /* MIB TX <= 64 byte Packets */ 1901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_65_127 0x051CUL /* MIB TX 65 to 127 byte Packets */ 1911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_128_255 0x0520UL /* MIB TX 128 to 255 byte Packets */ 1921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_256_511 0x0524UL /* MIB TX 256 to 511 byte Packets */ 1931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_512_1023 0x0528UL /* MIB TX 512 to 1023 byte Packets */ 1941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_1024_MAX 0x052CUL /* MIB TX 1024 to max byte Packets */ 1951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_JABBER 0x0530UL /* MIB TX Jabber Packets */ 1961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_OSIZE 0x0534UL /* MIB TX Oversize Packets */ 1971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_FRAG 0x0538UL /* MIB TX Fragment Packets */ 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_URUNS 0x053CUL /* MIB TX Underruns */ 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_TCOLS 0x0540UL /* MIB TX Total Collisions */ 2001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_SCOLS 0x0544UL /* MIB TX Single Collisions */ 2011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_MCOLS 0x0548UL /* MIB TX Multiple Collisions */ 2021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_ECOLS 0x054CUL /* MIB TX Excessive Collisions */ 2031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_LCOLS 0x0550UL /* MIB TX Late Collisions */ 2041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_DEFERED 0x0554UL /* MIB TX Defered Packets */ 2051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_CLOST 0x0558UL /* MIB TX Carrier Lost */ 2061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_TX_PAUSE 0x055CUL /* MIB TX Pause Packets */ 2071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_GOOD_O 0x0580UL /* MIB RX Good Octets */ 2081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_GOOD_P 0x0584UL /* MIB RX Good Packets */ 2091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_O 0x0588UL /* MIB RX Octets */ 2101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_P 0x058CUL /* MIB RX Packets */ 2111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_BCAST 0x0590UL /* MIB RX Broadcast Packets */ 2121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_MCAST 0x0594UL /* MIB RX Multicast Packets */ 2131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_64 0x0598UL /* MIB RX <= 64 byte Packets */ 2141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_65_127 0x059CUL /* MIB RX 65 to 127 byte Packets */ 2151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_128_255 0x05A0UL /* MIB RX 128 to 255 byte Packets */ 2161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_256_511 0x05A4UL /* MIB RX 256 to 511 byte Packets */ 2171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_512_1023 0x05A8UL /* MIB RX 512 to 1023 byte Packets */ 2181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_1024_MAX 0x05ACUL /* MIB RX 1024 to max byte Packets */ 2191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_JABBER 0x05B0UL /* MIB RX Jabber Packets */ 2201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_OSIZE 0x05B4UL /* MIB RX Oversize Packets */ 2211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_FRAG 0x05B8UL /* MIB RX Fragment Packets */ 2221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_MISS 0x05BCUL /* MIB RX Missed Packets */ 2231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_CRCA 0x05C0UL /* MIB RX CRC Align Errors */ 2241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_USIZE 0x05C4UL /* MIB RX Undersize Packets */ 2251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_CRC 0x05C8UL /* MIB RX CRC Errors */ 2261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_ALIGN 0x05CCUL /* MIB RX Align Errors */ 2271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_SYM 0x05D0UL /* MIB RX Symbol Errors */ 2281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_PAUSE 0x05D4UL /* MIB RX Pause Packets */ 2291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_RX_NPAUSE 0x05D8UL /* MIB RX Non-Pause Packets */ 2301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 4400 PHY registers */ 2321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_MII_AUXCTRL 24 /* Auxiliary Control */ 2331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */ 2341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_AUXCTRL_SPEED 0x0002 /* 1=100Mbps, 0=10Mbps */ 2351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_AUXCTRL_FORCED 0x0004 /* Forced 10/100 */ 2361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_MII_ALEDCTRL 26 /* Activity LED */ 2371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_ALEDCTRL_ALLMSK 0x7fff 2381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_MII_TLEDCTRL 27 /* Traffic Meter LED */ 2391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_TLEDCTRL_ENABLE 0x0040 2401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct dma_desc { 242a7bed27dc69e3bc9238549a4964ea94ec318362cAl Viro __le32 ctrl; 243a7bed27dc69e3bc9238549a4964ea94ec318362cAl Viro __le32 addr; 2441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* There are only 12 bits in the DMA engine for descriptor offsetting 2471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * so the table must be aligned on a boundary of this. 2481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMA_TABLE_BYTES 4096 2501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DESC_CTRL_LEN 0x00001fff 2521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DESC_CTRL_CMASK 0x0ff00000 /* Core specific bits */ 2531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DESC_CTRL_EOT 0x10000000 /* End of Table */ 2541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DESC_CTRL_IOC 0x20000000 /* Interrupt On Completion */ 2551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DESC_CTRL_EOF 0x40000000 /* End of Frame */ 2561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DESC_CTRL_SOF 0x80000000 /* Start of Frame */ 2571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_COPY_THRESHOLD 256 2591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct rx_header { 261a7bed27dc69e3bc9238549a4964ea94ec318362cAl Viro __le16 len; 262a7bed27dc69e3bc9238549a4964ea94ec318362cAl Viro __le16 flags; 263a7bed27dc69e3bc9238549a4964ea94ec318362cAl Viro __le16 pad[12]; 2641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_HEADER_LEN 28 2661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */ 2681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_FLAG_CRCERR 0x00000002 /* CRC Error */ 2691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */ 2701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */ 2711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */ 2721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */ 2731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */ 2741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */ 2751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_FLAG_LAST 0x00000800 /* Last buffer in frame */ 2761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_FLAG_ERRORS (RX_FLAG_ODD | RX_FLAG_SERR | RX_FLAG_CRCERR | RX_FLAG_OFIFO) 2771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct ring_info { 2791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct sk_buff *skb; 280753f492093da7a40141bfe083073400f518f4c68Michael Buesch dma_addr_t mapping; 2811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_MCAST_TABLE_SIZE 32 284753f492093da7a40141bfe083073400f518f4c68Michael Buesch#define B44_PHY_ADDR_NO_PHY 30 285753f492093da7a40141bfe083073400f518f4c68Michael Buesch#define B44_MDC_RATIO 5000000 2861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2873353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu#define B44_STAT_REG_DECLARE \ 2883353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_good_octets) \ 2893353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_good_pkts) \ 2903353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_octets) \ 2913353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_pkts) \ 2923353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_broadcast_pkts) \ 2933353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_multicast_pkts) \ 2943353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_len_64) \ 2953353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_len_65_to_127) \ 2963353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_len_128_to_255) \ 2973353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_len_256_to_511) \ 2983353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_len_512_to_1023) \ 2993353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_len_1024_to_max) \ 3003353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_jabber_pkts) \ 3013353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_oversize_pkts) \ 3023353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_fragment_pkts) \ 3033353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_underruns) \ 3043353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_total_cols) \ 3053353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_single_cols) \ 3063353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_multiple_cols) \ 3073353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_excessive_cols) \ 3083353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_late_cols) \ 3093353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_defered) \ 3103353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_carrier_lost) \ 3113353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(tx_pause_pkts) \ 3123353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_good_octets) \ 3133353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_good_pkts) \ 3143353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_octets) \ 3153353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_pkts) \ 3163353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_broadcast_pkts) \ 3173353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_multicast_pkts) \ 3183353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_len_64) \ 3193353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_len_65_to_127) \ 3203353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_len_128_to_255) \ 3213353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_len_256_to_511) \ 3223353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_len_512_to_1023) \ 3233353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_len_1024_to_max) \ 3243353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_jabber_pkts) \ 3253353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_oversize_pkts) \ 3263353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_fragment_pkts) \ 3273353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_missed_pkts) \ 3283353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_crc_align_errs) \ 3293353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_undersize) \ 3303353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_crc_errs) \ 3313353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_align_errs) \ 3323353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_symbol_errs) \ 3333353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_pause_pkts) \ 3343353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu _B44(rx_nonpause_pkts) 3353353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu 3361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* SW copy of device statistics, kept up to date by periodic timer 3373353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu * which probes HW values. Check b44_stats_update if you mess with 3383353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu * the layout 3391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct b44_hw_stats { 3413353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu#define _B44(x) u32 x; 3423353930d9d026ca94747d0766f864b2a0a8c714bFrancois RomieuB44_STAT_REG_DECLARE 3433353930d9d026ca94747d0766f864b2a0a8c714bFrancois Romieu#undef _B44 3441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 3451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 346753f492093da7a40141bfe083073400f518f4c68Michael Bueschstruct ssb_device; 347753f492093da7a40141bfe083073400f518f4c68Michael Buesch 3481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct b44 { 3491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds spinlock_t lock; 3501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 imask, istat; 3521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct dma_desc *rx_ring, *tx_ring; 3541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 tx_prod, tx_cons; 3561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 rx_prod, rx_cons; 3571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct ring_info *rx_buffers; 3591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct ring_info *tx_buffers; 3601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 361bea3348eef27e6044b6161fd04c3152215f96411Stephen Hemminger struct napi_struct napi; 362bea3348eef27e6044b6161fd04c3152215f96411Stephen Hemminger 3631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 dma_offset; 3641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 flags; 36552cafd965507b7a7bb962486539f6d7422552692Gary Zambrano#define B44_FLAG_B0_ANDLATER 0x00000001 3661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_FLAG_BUGGY_TXPTR 0x00000002 3671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_FLAG_REORDER_BUG 0x00000004 3681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_FLAG_PAUSE_AUTO 0x00008000 3691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_FLAG_FULL_DUPLEX 0x00010000 3701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_FLAG_100_BASE_T 0x00020000 3711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_FLAG_TX_PAUSE 0x00040000 3721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_FLAG_RX_PAUSE 0x00080000 3731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_FLAG_FORCE_LINK 0x00100000 3741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_FLAG_ADV_10HALF 0x01000000 3751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_FLAG_ADV_10FULL 0x02000000 3761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_FLAG_ADV_100HALF 0x04000000 3771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_FLAG_ADV_100FULL 0x08000000 3781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B44_FLAG_INTERNAL_PHY 0x10000000 3799f38c636ababfb41e58c9ec1e9719492ef7f0479John W. Linville#define B44_FLAG_RX_RING_HACK 0x20000000 3809f38c636ababfb41e58c9ec1e9719492ef7f0479John W. Linville#define B44_FLAG_TX_RING_HACK 0x40000000 38152cafd965507b7a7bb962486539f6d7422552692Gary Zambrano#define B44_FLAG_WOL_ENABLE 0x80000000 3821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 msg_enable; 3841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct timer_list timer; 3861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct b44_hw_stats hw_stats; 3881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 389753f492093da7a40141bfe083073400f518f4c68Michael Buesch struct ssb_device *sdev; 3901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct net_device *dev; 3911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dma_addr_t rx_ring_dma, tx_ring_dma; 3931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 rx_pending; 3951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 tx_pending; 3961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u8 phy_addr; 397a58c891a53aca81c78f9cbe0572a301042470e96Eric Dumazet u8 force_copybreak; 3981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct mii_if_info mii_if; 3991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 4001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* _B44_H */ 402