19b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#ifndef BCM63XX_ENET_H_ 29b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define BCM63XX_ENET_H_ 39b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 49b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#include <linux/types.h> 59b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#include <linux/mii.h> 69b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#include <linux/mutex.h> 79b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#include <linux/phy.h> 89b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#include <linux/platform_device.h> 99b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 109b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#include <bcm63xx_regs.h> 119b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#include <bcm63xx_irq.h> 129b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#include <bcm63xx_io.h> 139b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 149b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon/* default number of descriptor */ 159b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define BCMENET_DEF_RX_DESC 64 169b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define BCMENET_DEF_TX_DESC 32 179b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 189b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon/* maximum burst len for dma (4 bytes unit) */ 199b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define BCMENET_DMA_MAXBURST 16 209b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 219b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon/* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value 229b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon * must be low enough so that a DMA transfer of above burst length can 239b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon * not overflow the fifo */ 249b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define BCMENET_TX_FIFO_TRESH 32 259b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 269b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon/* 279b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon * hardware maximum rx/tx packet size including FCS, max mtu is 289b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon * actually 2047, but if we set max rx size register to 2047 we won't 299b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon * get overflow information if packet size is 2048 or above 309b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon */ 319b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define BCMENET_MAX_MTU 2046 329b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 339b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon/* 349b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon * rx/tx dma descriptor 359b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon */ 369b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizonstruct bcm_enet_desc { 379b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 len_stat; 389b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 address; 399b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon}; 409b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 419b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define DMADESC_LENGTH_SHIFT 16 429b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT) 439b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define DMADESC_OWNER_MASK (1 << 15) 449b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define DMADESC_EOP_MASK (1 << 14) 459b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define DMADESC_SOP_MASK (1 << 13) 469b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK) 479b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define DMADESC_WRAP_MASK (1 << 12) 489b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 499b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define DMADESC_UNDER_MASK (1 << 9) 509b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define DMADESC_APPEND_CRC (1 << 8) 519b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define DMADESC_OVSIZE_MASK (1 << 4) 529b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define DMADESC_RXER_MASK (1 << 2) 539b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define DMADESC_CRC_MASK (1 << 1) 549b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define DMADESC_OV_MASK (1 << 0) 559b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define DMADESC_ERR_MASK (DMADESC_UNDER_MASK | \ 569b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon DMADESC_OVSIZE_MASK | \ 579b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon DMADESC_RXER_MASK | \ 589b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon DMADESC_CRC_MASK | \ 599b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon DMADESC_OV_MASK) 609b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 619b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 629b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon/* 639b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon * MIB Counters register definitions 649b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon*/ 659b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_GD_OCTETS 0 669b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_GD_PKTS 1 679b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_ALL_OCTETS 2 689b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_ALL_PKTS 3 699b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_BRDCAST 4 709b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_MULT 5 719b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_64 6 729b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_65_127 7 739b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_128_255 8 749b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_256_511 9 759b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_512_1023 10 769b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_1024_MAX 11 779b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_JAB 12 789b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_OVR 13 799b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_FRAG 14 809b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_UNDERRUN 15 819b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_COL 16 829b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_1_COL 17 839b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_M_COL 18 849b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_EX_COL 19 859b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_LATE 20 869b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_DEF 21 879b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_CRS 22 889b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_TX_PAUSE 23 899b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 909b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_GD_OCTETS 32 919b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_GD_PKTS 33 929b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_ALL_OCTETS 34 939b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_ALL_PKTS 35 949b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_BRDCAST 36 959b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_MULT 37 969b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_64 38 979b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_65_127 39 989b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_128_255 40 999b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_256_511 41 1009b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_512_1023 42 1019b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_1024_MAX 43 1029b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_JAB 44 1039b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_OVR 45 1049b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_FRAG 46 1059b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_DROP 47 1069b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_CRC_ALIGN 48 1079b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_UND 49 1089b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_CRC 50 1099b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_ALIGN 51 1109b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_SYM 52 1119b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_PAUSE 53 1129b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#define ETH_MIB_RX_CNTRL 54 1139b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 1149b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 1159b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizonstruct bcm_enet_mib_counters { 1169b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u64 tx_gd_octets; 1179b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_gd_pkts; 1189b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_all_octets; 1199b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_all_pkts; 1209b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_brdcast; 1219b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_mult; 1229b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_64; 1239b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_65_127; 1249b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_128_255; 1259b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_256_511; 1269b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_512_1023; 1279b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_1024_max; 1289b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_jab; 1299b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_ovr; 1309b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_frag; 1319b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_underrun; 1329b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_col; 1339b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_1_col; 1349b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_m_col; 1359b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_ex_col; 1369b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_late; 1379b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_def; 1389b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_crs; 1399b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 tx_pause; 1409b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u64 rx_gd_octets; 1419b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_gd_pkts; 1429b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_all_octets; 1439b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_all_pkts; 1449b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_brdcast; 1459b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_mult; 1469b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_64; 1479b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_65_127; 1489b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_128_255; 1499b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_256_511; 1509b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_512_1023; 1519b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_1024_max; 1529b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_jab; 1539b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_ovr; 1549b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_frag; 1559b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_drop; 1569b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_crc_align; 1579b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_und; 1589b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_crc; 1599b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_align; 1609b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_sym; 1619b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_pause; 1629b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon u32 rx_cntrl; 1639b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon}; 1649b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 1659b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 1669b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizonstruct bcm_enet_priv { 1679b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 1689b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* mac id (from platform device id) */ 1699b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int mac_id; 1709b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 1719b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* base remapped address of device */ 1729b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon void __iomem *base; 1739b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 1749b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* mac irq, rx_dma irq, tx_dma irq */ 1759b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int irq; 1769b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int irq_rx; 1779b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int irq_tx; 1789b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 1799b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* hw view of rx & tx dma ring */ 1809b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon dma_addr_t rx_desc_dma; 1819b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon dma_addr_t tx_desc_dma; 1829b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 1839b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* allocated size (in bytes) for rx & tx dma ring */ 1849b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon unsigned int rx_desc_alloc_size; 1859b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon unsigned int tx_desc_alloc_size; 1869b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 1879b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 1889b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon struct napi_struct napi; 1899b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 1909b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* dma channel id for rx */ 1919b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int rx_chan; 1929b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 1939b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* number of dma desc in rx ring */ 1949b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int rx_ring_size; 1959b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 1969b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* cpu view of rx dma ring */ 1979b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon struct bcm_enet_desc *rx_desc_cpu; 1989b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 1999b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* current number of armed descriptor given to hardware for rx */ 2009b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int rx_desc_count; 2019b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2029b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* next rx descriptor to fetch from hardware */ 2039b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int rx_curr_desc; 2049b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2059b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* next dirty rx descriptor to refill */ 2069b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int rx_dirty_desc; 2079b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2089b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* size of allocated rx skbs */ 2099b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon unsigned int rx_skb_size; 2109b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2119b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* list of skb given to hw for rx */ 2129b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon struct sk_buff **rx_skb; 2139b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2149b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* used when rx skb allocation failed, so we defer rx queue 2159b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon * refill */ 2169b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon struct timer_list rx_timeout; 2179b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2189b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* lock rx_timeout against rx normal operation */ 2199b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon spinlock_t rx_lock; 2209b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2219b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2229b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* dma channel id for tx */ 2239b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int tx_chan; 2249b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2259b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* number of dma desc in tx ring */ 2269b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int tx_ring_size; 2279b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2289b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* cpu view of rx dma ring */ 2299b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon struct bcm_enet_desc *tx_desc_cpu; 2309b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2319b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* number of available descriptor for tx */ 2329b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int tx_desc_count; 2339b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2349b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* next tx descriptor avaiable */ 2359b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int tx_curr_desc; 2369b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2379b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* next dirty tx descriptor to reclaim */ 2389b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int tx_dirty_desc; 2399b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2409b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* list of skb given to hw for tx */ 2419b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon struct sk_buff **tx_skb; 2429b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2439b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* lock used by tx reclaim and xmit */ 2449b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon spinlock_t tx_lock; 2459b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2469b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2479b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* set if internal phy is ignored and external mii interface 2489b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon * is selected */ 2499b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int use_external_mii; 2509b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2519b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* set if a phy is connected, phy address must be known, 2529b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon * probing is not possible */ 2539b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int has_phy; 2549b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int phy_id; 2559b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2569b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* set if connected phy has an associated irq */ 2579b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int has_phy_interrupt; 2589b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int phy_interrupt; 2599b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2609b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* used when a phy is connected (phylib used) */ 2619b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon struct mii_bus *mii_bus; 2629b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon struct phy_device *phydev; 2639b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int old_link; 2649b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int old_duplex; 2659b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int old_pause; 2669b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2679b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* used when no phy is connected */ 2689b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int force_speed_100; 2699b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int force_duplex_full; 2709b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2719b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* pause parameters */ 2729b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int pause_auto; 2739b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int pause_rx; 2749b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon int pause_tx; 2759b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2769b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* stats */ 2779b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon struct bcm_enet_mib_counters mib; 2789b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2799b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* after mib interrupt, mib registers update is done in this 2809b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon * work queue */ 2819b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon struct work_struct mib_update_task; 2829b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2839b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* lock mib update between userspace request and workqueue */ 2849b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon struct mutex mib_update_lock; 2859b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2869b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* mac clock */ 2879b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon struct clk *mac_clk; 2889b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2899b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* phy clock if internal phy is used */ 2909b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon struct clk *phy_clk; 2919b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2929b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* network device reference */ 2939b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon struct net_device *net_dev; 2949b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2959b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* platform device reference */ 2969b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon struct platform_device *pdev; 2979b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 2989b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon /* maximum hardware transmit/receive size */ 2999b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon unsigned int hw_mtu; 3009b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon}; 3019b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon 3029b1fc55a05006523bced65f4d99f7072831ff56aMaxime Bizon#endif /* ! BCM63XX_ENET_H_ */ 303