bnx2x.h revision 0f9dad10a040fa72c588db46a94c9e96545cc509
1/* bnx2x.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2011 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 */ 13 14#ifndef BNX2X_H 15#define BNX2X_H 16#include <linux/netdevice.h> 17#include <linux/dma-mapping.h> 18#include <linux/types.h> 19 20/* compilation time flags */ 21 22/* define this to make the driver freeze on error to allow getting debug info 23 * (you will need to reboot afterwards) */ 24/* #define BNX2X_STOP_ON_ERROR */ 25 26#define DRV_MODULE_VERSION "1.70.00-0" 27#define DRV_MODULE_RELDATE "2011/06/13" 28#define BNX2X_BC_VER 0x040200 29 30#if defined(CONFIG_DCB) 31#define BCM_DCBNL 32#endif 33#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) 34#define BCM_CNIC 1 35#include "../cnic_if.h" 36#endif 37 38#ifdef BCM_CNIC 39#define BNX2X_MIN_MSIX_VEC_CNT 3 40#define BNX2X_MSIX_VEC_FP_START 2 41#else 42#define BNX2X_MIN_MSIX_VEC_CNT 2 43#define BNX2X_MSIX_VEC_FP_START 1 44#endif 45 46#include <linux/mdio.h> 47 48#include "bnx2x_reg.h" 49#include "bnx2x_fw_defs.h" 50#include "bnx2x_hsi.h" 51#include "bnx2x_link.h" 52#include "bnx2x_sp.h" 53#include "bnx2x_dcb.h" 54#include "bnx2x_stats.h" 55 56/* error/debug prints */ 57 58#define DRV_MODULE_NAME "bnx2x" 59 60/* for messages that are currently off */ 61#define BNX2X_MSG_OFF 0 62#define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */ 63#define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */ 64#define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */ 65#define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */ 66#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ 67#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ 68 69#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ 70 71/* regular debug print */ 72#define DP(__mask, __fmt, __args...) \ 73do { \ 74 if (bp->msg_enable & (__mask)) \ 75 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \ 76 __func__, __LINE__, \ 77 bp->dev ? (bp->dev->name) : "?", \ 78 ##__args); \ 79} while (0) 80 81#define DP_CONT(__mask, __fmt, __args...) \ 82do { \ 83 if (bp->msg_enable & (__mask)) \ 84 pr_cont(__fmt, ##__args); \ 85} while (0) 86 87/* errors debug print */ 88#define BNX2X_DBG_ERR(__fmt, __args...) \ 89do { \ 90 if (netif_msg_probe(bp)) \ 91 pr_err("[%s:%d(%s)]" __fmt, \ 92 __func__, __LINE__, \ 93 bp->dev ? (bp->dev->name) : "?", \ 94 ##__args); \ 95} while (0) 96 97/* for errors (never masked) */ 98#define BNX2X_ERR(__fmt, __args...) \ 99do { \ 100 pr_err("[%s:%d(%s)]" __fmt, \ 101 __func__, __LINE__, \ 102 bp->dev ? (bp->dev->name) : "?", \ 103 ##__args); \ 104 } while (0) 105 106#define BNX2X_ERROR(__fmt, __args...) do { \ 107 pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \ 108 } while (0) 109 110 111/* before we have a dev->name use dev_info() */ 112#define BNX2X_DEV_INFO(__fmt, __args...) \ 113do { \ 114 if (netif_msg_probe(bp)) \ 115 dev_info(&bp->pdev->dev, __fmt, ##__args); \ 116} while (0) 117 118#ifdef BNX2X_STOP_ON_ERROR 119void bnx2x_int_disable(struct bnx2x *bp); 120#define bnx2x_panic() do { \ 121 bp->panic = 1; \ 122 BNX2X_ERR("driver assert\n"); \ 123 bnx2x_int_disable(bp); \ 124 bnx2x_panic_dump(bp); \ 125 } while (0) 126#else 127#define bnx2x_panic() do { \ 128 bp->panic = 1; \ 129 BNX2X_ERR("driver assert\n"); \ 130 bnx2x_panic_dump(bp); \ 131 } while (0) 132#endif 133 134#define bnx2x_mc_addr(ha) ((ha)->addr) 135#define bnx2x_uc_addr(ha) ((ha)->addr) 136 137#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) 138#define U64_HI(x) (u32)(((u64)(x)) >> 32) 139#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 140 141 142#define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 143 144#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 145#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 146#define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 147 148#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 149#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 150#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 151 152#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 153#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 154 155#define REG_RD_DMAE(bp, offset, valp, len32) \ 156 do { \ 157 bnx2x_read_dmae(bp, offset, len32);\ 158 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 159 } while (0) 160 161#define REG_WR_DMAE(bp, offset, valp, len32) \ 162 do { \ 163 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 164 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 165 offset, len32); \ 166 } while (0) 167 168#define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 169 REG_WR_DMAE(bp, offset, valp, len32) 170 171#define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 172 do { \ 173 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 174 bnx2x_write_big_buf_wb(bp, addr, len32); \ 175 } while (0) 176 177#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 178 offsetof(struct shmem_region, field)) 179#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 180#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 181 182#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 183 offsetof(struct shmem2_region, field)) 184#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 185#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 186#define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 187 offsetof(struct mf_cfg, field)) 188#define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 189 offsetof(struct mf2_cfg, field)) 190 191#define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 192#define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 193 MF_CFG_ADDR(bp, field), (val)) 194#define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 195 196#define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 197 (SHMEM2_RD((bp), size) > \ 198 offsetof(struct shmem2_region, field))) 199 200#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 201#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 202 203/* SP SB indices */ 204 205/* General SP events - stats query, cfc delete, etc */ 206#define HC_SP_INDEX_ETH_DEF_CONS 3 207 208/* EQ completions */ 209#define HC_SP_INDEX_EQ_CONS 7 210 211/* FCoE L2 connection completions */ 212#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 213#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 214/* iSCSI L2 */ 215#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 216#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 217 218/* Special clients parameters */ 219 220/* SB indices */ 221/* FCoE L2 */ 222#define BNX2X_FCOE_L2_RX_INDEX \ 223 (&bp->def_status_blk->sp_sb.\ 224 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 225 226#define BNX2X_FCOE_L2_TX_INDEX \ 227 (&bp->def_status_blk->sp_sb.\ 228 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 229 230/** 231 * CIDs and CLIDs: 232 * CLIDs below is a CLID for func 0, then the CLID for other 233 * functions will be calculated by the formula: 234 * 235 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 236 * 237 */ 238/* iSCSI L2 */ 239#define BNX2X_ISCSI_ETH_CL_ID_IDX 1 240#define BNX2X_ISCSI_ETH_CID 49 241 242/* FCoE L2 */ 243#define BNX2X_FCOE_ETH_CL_ID_IDX 2 244#define BNX2X_FCOE_ETH_CID 50 245 246/** Additional rings budgeting */ 247#ifdef BCM_CNIC 248#define CNIC_PRESENT 1 249#define FCOE_PRESENT 1 250#else 251#define CNIC_PRESENT 0 252#define FCOE_PRESENT 0 253#endif /* BCM_CNIC */ 254#define NON_ETH_CONTEXT_USE (FCOE_PRESENT) 255 256#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 257 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 258 259#define SM_RX_ID 0 260#define SM_TX_ID 1 261 262/* defines for multiple tx priority indices */ 263#define FIRST_TX_ONLY_COS_INDEX 1 264#define FIRST_TX_COS_INDEX 0 265 266/* defines for decodeing the fastpath index and the cos index out of the 267 * transmission queue index 268 */ 269#define MAX_TXQS_PER_COS FP_SB_MAX_E1x 270 271#define TXQ_TO_FP(txq_index) ((txq_index) % MAX_TXQS_PER_COS) 272#define TXQ_TO_COS(txq_index) ((txq_index) / MAX_TXQS_PER_COS) 273 274/* rules for calculating the cids of tx-only connections */ 275#define CID_TO_FP(cid) ((cid) % MAX_TXQS_PER_COS) 276#define CID_COS_TO_TX_ONLY_CID(cid, cos) (cid + cos * MAX_TXQS_PER_COS) 277 278/* fp index inside class of service range */ 279#define FP_COS_TO_TXQ(fp, cos) ((fp)->index + cos * MAX_TXQS_PER_COS) 280 281/* 282 * 0..15 eth cos0 283 * 16..31 eth cos1 if applicable 284 * 32..47 eth cos2 If applicable 285 * fcoe queue follows eth queues (16, 32, 48 depending on cos) 286 */ 287#define MAX_ETH_TXQ_IDX(bp) (MAX_TXQS_PER_COS * (bp)->max_cos) 288#define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp)) 289 290/* fast path */ 291struct sw_rx_bd { 292 struct sk_buff *skb; 293 DEFINE_DMA_UNMAP_ADDR(mapping); 294}; 295 296struct sw_tx_bd { 297 struct sk_buff *skb; 298 u16 first_bd; 299 u8 flags; 300/* Set on the first BD descriptor when there is a split BD */ 301#define BNX2X_TSO_SPLIT_BD (1<<0) 302}; 303 304struct sw_rx_page { 305 struct page *page; 306 DEFINE_DMA_UNMAP_ADDR(mapping); 307}; 308 309union db_prod { 310 struct doorbell_set_prod data; 311 u32 raw; 312}; 313 314 315/* MC hsi */ 316#define BCM_PAGE_SHIFT 12 317#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 318#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 319#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 320 321#define PAGES_PER_SGE_SHIFT 0 322#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 323#define SGE_PAGE_SIZE PAGE_SIZE 324#define SGE_PAGE_SHIFT PAGE_SHIFT 325#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) 326 327/* SGE ring related macros */ 328#define NUM_RX_SGE_PAGES 2 329#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 330#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2) 331/* RX_SGE_CNT is promised to be a power of 2 */ 332#define RX_SGE_MASK (RX_SGE_CNT - 1) 333#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 334#define MAX_RX_SGE (NUM_RX_SGE - 1) 335#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 336 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1) 337#define RX_SGE(x) ((x) & MAX_RX_SGE) 338 339/* Manipulate a bit vector defined as an array of u64 */ 340 341/* Number of bits in one sge_mask array element */ 342#define BIT_VEC64_ELEM_SZ 64 343#define BIT_VEC64_ELEM_SHIFT 6 344#define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 345 346 347#define __BIT_VEC64_SET_BIT(el, bit) \ 348 do { \ 349 el = ((el) | ((u64)0x1 << (bit))); \ 350 } while (0) 351 352#define __BIT_VEC64_CLEAR_BIT(el, bit) \ 353 do { \ 354 el = ((el) & (~((u64)0x1 << (bit)))); \ 355 } while (0) 356 357 358#define BIT_VEC64_SET_BIT(vec64, idx) \ 359 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 360 (idx) & BIT_VEC64_ELEM_MASK) 361 362#define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 363 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 364 (idx) & BIT_VEC64_ELEM_MASK) 365 366#define BIT_VEC64_TEST_BIT(vec64, idx) \ 367 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 368 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 369 370/* Creates a bitmask of all ones in less significant bits. 371 idx - index of the most significant bit in the created mask */ 372#define BIT_VEC64_ONES_MASK(idx) \ 373 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 374#define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 375 376/*******************************************************/ 377 378 379 380/* Number of u64 elements in SGE mask array */ 381#define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \ 382 BIT_VEC64_ELEM_SZ) 383#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 384#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 385 386union host_hc_status_block { 387 /* pointer to fp status block e1x */ 388 struct host_hc_status_block_e1x *e1x_sb; 389 /* pointer to fp status block e2 */ 390 struct host_hc_status_block_e2 *e2_sb; 391}; 392 393struct bnx2x_agg_info { 394 /* 395 * First aggregation buffer is an skb, the following - are pages. 396 * We will preallocate the skbs for each aggregation when 397 * we open the interface and will replace the BD at the consumer 398 * with this one when we receive the TPA_START CQE in order to 399 * keep the Rx BD ring consistent. 400 */ 401 struct sw_rx_bd first_buf; 402 u8 tpa_state; 403#define BNX2X_TPA_START 1 404#define BNX2X_TPA_STOP 2 405#define BNX2X_TPA_ERROR 3 406 u8 placement_offset; 407 u16 parsing_flags; 408 u16 vlan_tag; 409 u16 len_on_bd; 410}; 411 412#define Q_STATS_OFFSET32(stat_name) \ 413 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 414 415struct bnx2x_fp_txdata { 416 417 struct sw_tx_bd *tx_buf_ring; 418 419 union eth_tx_bd_types *tx_desc_ring; 420 dma_addr_t tx_desc_mapping; 421 422 u32 cid; 423 424 union db_prod tx_db; 425 426 u16 tx_pkt_prod; 427 u16 tx_pkt_cons; 428 u16 tx_bd_prod; 429 u16 tx_bd_cons; 430 431 unsigned long tx_pkt; 432 433 __le16 *tx_cons_sb; 434 435 int txq_index; 436}; 437 438struct bnx2x_fastpath { 439 struct bnx2x *bp; /* parent */ 440 441#define BNX2X_NAPI_WEIGHT 128 442 struct napi_struct napi; 443 union host_hc_status_block status_blk; 444 /* chip independed shortcuts into sb structure */ 445 __le16 *sb_index_values; 446 __le16 *sb_running_index; 447 /* chip independed shortcut into rx_prods_offset memory */ 448 u32 ustorm_rx_prods_offset; 449 450 u32 rx_buf_size; 451 452 dma_addr_t status_blk_mapping; 453 454 u8 max_cos; /* actual number of active tx coses */ 455 struct bnx2x_fp_txdata txdata[BNX2X_MULTI_TX_COS]; 456 457 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 458 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 459 460 struct eth_rx_bd *rx_desc_ring; 461 dma_addr_t rx_desc_mapping; 462 463 union eth_rx_cqe *rx_comp_ring; 464 dma_addr_t rx_comp_mapping; 465 466 /* SGE ring */ 467 struct eth_rx_sge *rx_sge_ring; 468 dma_addr_t rx_sge_mapping; 469 470 u64 sge_mask[RX_SGE_MASK_LEN]; 471 472 u32 cid; 473 474 __le16 fp_hc_idx; 475 476 u8 index; /* number in fp array */ 477 u8 cl_id; /* eth client id */ 478 u8 cl_qzone_id; 479 u8 fw_sb_id; /* status block number in FW */ 480 u8 igu_sb_id; /* status block number in HW */ 481 482 u16 rx_bd_prod; 483 u16 rx_bd_cons; 484 u16 rx_comp_prod; 485 u16 rx_comp_cons; 486 u16 rx_sge_prod; 487 /* The last maximal completed SGE */ 488 u16 last_max_sge; 489 __le16 *rx_cons_sb; 490 unsigned long rx_pkt, 491 rx_calls; 492 493 /* TPA related */ 494 struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 495 u8 disable_tpa; 496#ifdef BNX2X_STOP_ON_ERROR 497 u64 tpa_queue_used; 498#endif 499 500 struct tstorm_per_queue_stats old_tclient; 501 struct ustorm_per_queue_stats old_uclient; 502 struct xstorm_per_queue_stats old_xclient; 503 struct bnx2x_eth_q_stats eth_q_stats; 504 505 /* The size is calculated using the following: 506 sizeof name field from netdev structure + 507 4 ('-Xx-' string) + 508 4 (for the digits and to make it DWORD aligned) */ 509#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 510 char name[FP_NAME_SIZE]; 511 512 /* MACs object */ 513 struct bnx2x_vlan_mac_obj mac_obj; 514 515 /* Queue State object */ 516 struct bnx2x_queue_sp_obj q_obj; 517 518}; 519 520#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) 521 522/* Use 2500 as a mini-jumbo MTU for FCoE */ 523#define BNX2X_FCOE_MINI_JUMBO_MTU 2500 524 525/* FCoE L2 `fastpath' entry is right after the eth entries */ 526#define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp) 527#define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX]) 528#define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 529#define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 530 txdata[FIRST_TX_COS_INDEX].var) 531 532 533#define IS_ETH_FP(fp) (fp->index < \ 534 BNX2X_NUM_ETH_QUEUES(fp->bp)) 535#ifdef BCM_CNIC 536#define IS_FCOE_FP(fp) (fp->index == FCOE_IDX) 537#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX) 538#else 539#define IS_FCOE_FP(fp) false 540#define IS_FCOE_IDX(idx) false 541#endif 542 543 544/* MC hsi */ 545#define MAX_FETCH_BD 13 /* HW max BDs per packet */ 546#define RX_COPY_THRESH 92 547 548#define NUM_TX_RINGS 16 549#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 550#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) 551#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 552#define MAX_TX_BD (NUM_TX_BD - 1) 553#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 554#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 555 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) 556#define TX_BD(x) ((x) & MAX_TX_BD) 557#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 558 559/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 560#define NUM_RX_RINGS 8 561#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 562#define MAX_RX_DESC_CNT (RX_DESC_CNT - 2) 563#define RX_DESC_MASK (RX_DESC_CNT - 1) 564#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 565#define MAX_RX_BD (NUM_RX_BD - 1) 566#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 567#define MIN_RX_AVAIL 128 568 569#define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 570 ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 571 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 572#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 573#define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 574#define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 575 MIN_RX_AVAIL)) 576 577#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 578 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1) 579#define RX_BD(x) ((x) & MAX_RX_BD) 580 581/* 582 * As long as CQE is X times bigger than BD entry we have to allocate X times 583 * more pages for CQ ring in order to keep it balanced with BD ring 584 */ 585#define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 586#define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 587#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 588#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1) 589#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 590#define MAX_RCQ_BD (NUM_RCQ_BD - 1) 591#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 592#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 593 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) 594#define RCQ_BD(x) ((x) & MAX_RCQ_BD) 595 596 597/* This is needed for determining of last_max */ 598#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 599#define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 600 601 602#define BNX2X_SWCID_SHIFT 17 603#define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 604 605/* used on a CID received from the HW */ 606#define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 607#define CQE_CMD(x) (le32_to_cpu(x) >> \ 608 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 609 610#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 611 le32_to_cpu((bd)->addr_lo)) 612#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 613 614#define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 615#define BNX2X_DB_SHIFT 7 /* 128 bytes*/ 616#if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 617#error "Min DB doorbell stride is 8" 618#endif 619#define DPM_TRIGER_TYPE 0x40 620#define DOORBELL(bp, cid, val) \ 621 do { \ 622 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ 623 DPM_TRIGER_TYPE); \ 624 } while (0) 625 626 627/* TX CSUM helpers */ 628#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 629 skb->csum_offset) 630#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 631 skb->csum_offset)) 632 633#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) 634 635#define XMIT_PLAIN 0 636#define XMIT_CSUM_V4 0x1 637#define XMIT_CSUM_V6 0x2 638#define XMIT_CSUM_TCP 0x4 639#define XMIT_GSO_V4 0x8 640#define XMIT_GSO_V6 0x10 641 642#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) 643#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) 644 645 646/* stuff added to make the code fit 80Col */ 647#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 648#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 649#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 650#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 651#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 652 653#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 654 655#define BNX2X_IP_CSUM_ERR(cqe) \ 656 (!((cqe)->fast_path_cqe.status_flags & \ 657 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \ 658 ((cqe)->fast_path_cqe.type_error_flags & \ 659 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) 660 661#define BNX2X_L4_CSUM_ERR(cqe) \ 662 (!((cqe)->fast_path_cqe.status_flags & \ 663 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \ 664 ((cqe)->fast_path_cqe.type_error_flags & \ 665 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) 666 667#define BNX2X_RX_CSUM_OK(cqe) \ 668 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) 669 670#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 671 (((le16_to_cpu(flags) & \ 672 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 673 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 674 == PRS_FLAG_OVERETH_IPV4) 675#define BNX2X_RX_SUM_FIX(cqe) \ 676 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 677 678 679#define FP_USB_FUNC_OFF \ 680 offsetof(struct cstorm_status_block_u, func) 681#define FP_CSB_FUNC_OFF \ 682 offsetof(struct cstorm_status_block_c, func) 683 684#define HC_INDEX_TOE_RX_CQ_CONS 0 /* Formerly Ustorm TOE CQ index */ 685 /* (HC_INDEX_U_TOE_RX_CQ_CONS) */ 686#define HC_INDEX_ETH_RX_CQ_CONS 1 /* Formerly Ustorm ETH CQ index */ 687 /* (HC_INDEX_U_ETH_RX_CQ_CONS) */ 688#define HC_INDEX_ETH_RX_BD_CONS 2 /* Formerly Ustorm ETH BD index */ 689 /* (HC_INDEX_U_ETH_RX_BD_CONS) */ 690 691#define HC_INDEX_TOE_TX_CQ_CONS 4 /* Formerly Cstorm TOE CQ index */ 692 /* (HC_INDEX_C_TOE_TX_CQ_CONS) */ 693#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 /* Formerly Cstorm ETH CQ index */ 694 /* (HC_INDEX_C_ETH_TX_CQ_CONS) */ 695#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 /* Formerly Cstorm ETH CQ index */ 696 /* (HC_INDEX_C_ETH_TX_CQ_CONS) */ 697#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 /* Formerly Cstorm ETH CQ index */ 698 /* (HC_INDEX_C_ETH_TX_CQ_CONS) */ 699 700#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 701 702 703#define BNX2X_RX_SB_INDEX \ 704 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 705 706#define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 707 708#define BNX2X_TX_SB_INDEX_COS0 \ 709 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 710 711/* end of fast path */ 712 713/* common */ 714 715struct bnx2x_common { 716 717 u32 chip_id; 718/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 719#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 720 721#define CHIP_NUM(bp) (bp->common.chip_id >> 16) 722#define CHIP_NUM_57710 0x164e 723#define CHIP_NUM_57711 0x164f 724#define CHIP_NUM_57711E 0x1650 725#define CHIP_NUM_57712 0x1662 726#define CHIP_NUM_57712_MF 0x1663 727#define CHIP_NUM_57713 0x1651 728#define CHIP_NUM_57713E 0x1652 729#define CHIP_NUM_57800 0x168a 730#define CHIP_NUM_57800_MF 0x16a5 731#define CHIP_NUM_57810 0x168e 732#define CHIP_NUM_57810_MF 0x16ae 733#define CHIP_NUM_57840 0x168d 734#define CHIP_NUM_57840_MF 0x16ab 735#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 736#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 737#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 738#define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 739#define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 740#define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 741#define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 742#define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 743#define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 744#define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840) 745#define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF) 746#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 747 CHIP_IS_57711E(bp)) 748#define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 749 CHIP_IS_57712_MF(bp)) 750#define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 751 CHIP_IS_57800_MF(bp) || \ 752 CHIP_IS_57810(bp) || \ 753 CHIP_IS_57810_MF(bp) || \ 754 CHIP_IS_57840(bp) || \ 755 CHIP_IS_57840_MF(bp)) 756#define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 757#define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 758#define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 759 760#define CHIP_REV_SHIFT 12 761#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 762#define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 763#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 764#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 765/* assume maximum 5 revisions */ 766#define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 767/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 768#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 769 !(CHIP_REV_VAL(bp) & 0x00001000)) 770/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 771#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 772 (CHIP_REV_VAL(bp) & 0x00001000)) 773 774#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 775 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 776 777#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 778#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 779#define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 780 (CHIP_REV_SHIFT + 1)) \ 781 << CHIP_REV_SHIFT) 782#define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 783 CHIP_REV_SIM(bp) :\ 784 CHIP_REV_VAL(bp)) 785#define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 786 (CHIP_REV(bp) == CHIP_REV_Bx)) 787#define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 788 (CHIP_REV(bp) == CHIP_REV_Ax)) 789 790 int flash_size; 791#define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 792#define BNX2X_NVRAM_TIMEOUT_COUNT 30000 793#define BNX2X_NVRAM_PAGE_SIZE 256 794 795 u32 shmem_base; 796 u32 shmem2_base; 797 u32 mf_cfg_base; 798 u32 mf2_cfg_base; 799 800 u32 hw_config; 801 802 u32 bc_ver; 803 804 u8 int_block; 805#define INT_BLOCK_HC 0 806#define INT_BLOCK_IGU 1 807#define INT_BLOCK_MODE_NORMAL 0 808#define INT_BLOCK_MODE_BW_COMP 2 809#define CHIP_INT_MODE_IS_NBC(bp) \ 810 (!CHIP_IS_E1x(bp) && \ 811 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 812#define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 813 814 u8 chip_port_mode; 815#define CHIP_4_PORT_MODE 0x0 816#define CHIP_2_PORT_MODE 0x1 817#define CHIP_PORT_MODE_NONE 0x2 818#define CHIP_MODE(bp) (bp->common.chip_port_mode) 819#define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 820}; 821 822/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 823#define BNX2X_IGU_STAS_MSG_VF_CNT 64 824#define BNX2X_IGU_STAS_MSG_PF_CNT 4 825 826/* end of common */ 827 828/* port */ 829 830struct bnx2x_port { 831 u32 pmf; 832 833 u32 link_config[LINK_CONFIG_SIZE]; 834 835 u32 supported[LINK_CONFIG_SIZE]; 836/* link settings - missing defines */ 837#define SUPPORTED_2500baseX_Full (1 << 15) 838 839 u32 advertising[LINK_CONFIG_SIZE]; 840/* link settings - missing defines */ 841#define ADVERTISED_2500baseX_Full (1 << 15) 842 843 u32 phy_addr; 844 845 /* used to synchronize phy accesses */ 846 struct mutex phy_mutex; 847 int need_hw_lock; 848 849 u32 port_stx; 850 851 struct nig_stats old_nig_stats; 852}; 853 854/* end of port */ 855 856#define STATS_OFFSET32(stat_name) \ 857 (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 858 859/* slow path */ 860 861/* slow path work-queue */ 862extern struct workqueue_struct *bnx2x_wq; 863 864#define BNX2X_MAX_NUM_OF_VFS 64 865#define BNX2X_VF_ID_INVALID 0xFF 866 867/* 868 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 869 * control by the number of fast-path status blocks supported by the 870 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 871 * status block represents an independent interrupts context that can 872 * serve a regular L2 networking queue. However special L2 queues such 873 * as the FCoE queue do not require a FP-SB and other components like 874 * the CNIC may consume FP-SB reducing the number of possible L2 queues 875 * 876 * If the maximum number of FP-SB available is X then: 877 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 878 * regular L2 queues is Y=X-1 879 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 880 * c. If the FCoE L2 queue is supported the actual number of L2 queues 881 * is Y+1 882 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 883 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 884 * FP interrupt context for the CNIC). 885 * e. The number of HW context (CID count) is always X or X+1 if FCoE 886 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 887 */ 888 889/* fast-path interrupt contexts E1x */ 890#define FP_SB_MAX_E1x 16 891/* fast-path interrupt contexts E2 */ 892#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 893 894union cdu_context { 895 struct eth_context eth; 896 char pad[1024]; 897}; 898 899/* CDU host DB constants */ 900#define CDU_ILT_PAGE_SZ_HW 3 901#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 64K */ 902#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 903 904#ifdef BCM_CNIC 905#define CNIC_ISCSI_CID_MAX 256 906#define CNIC_FCOE_CID_MAX 2048 907#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 908#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 909#endif 910 911#define QM_ILT_PAGE_SZ_HW 0 912#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 913#define QM_CID_ROUND 1024 914 915#ifdef BCM_CNIC 916/* TM (timers) host DB constants */ 917#define TM_ILT_PAGE_SZ_HW 0 918#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 919/* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 920#define TM_CONN_NUM 1024 921#define TM_ILT_SZ (8 * TM_CONN_NUM) 922#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 923 924/* SRC (Searcher) host DB constants */ 925#define SRC_ILT_PAGE_SZ_HW 0 926#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 927#define SRC_HASH_BITS 10 928#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 929#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 930#define SRC_T2_SZ SRC_ILT_SZ 931#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 932 933#endif 934 935#define MAX_DMAE_C 8 936 937/* DMA memory not used in fastpath */ 938struct bnx2x_slowpath { 939 union { 940 struct mac_configuration_cmd e1x; 941 struct eth_classify_rules_ramrod_data e2; 942 } mac_rdata; 943 944 945 union { 946 struct tstorm_eth_mac_filter_config e1x; 947 struct eth_filter_rules_ramrod_data e2; 948 } rx_mode_rdata; 949 950 union { 951 struct mac_configuration_cmd e1; 952 struct eth_multicast_rules_ramrod_data e2; 953 } mcast_rdata; 954 955 struct eth_rss_update_ramrod_data rss_rdata; 956 957 /* Queue State related ramrods are always sent under rtnl_lock */ 958 union { 959 struct client_init_ramrod_data init_data; 960 struct client_update_ramrod_data update_data; 961 } q_rdata; 962 963 union { 964 struct function_start_data func_start; 965 /* pfc configuration for DCBX ramrod */ 966 struct flow_control_configuration pfc_config; 967 } func_rdata; 968 969 /* used by dmae command executer */ 970 struct dmae_command dmae[MAX_DMAE_C]; 971 972 u32 stats_comp; 973 union mac_stats mac_stats; 974 struct nig_stats nig_stats; 975 struct host_port_stats port_stats; 976 struct host_func_stats func_stats; 977 struct host_func_stats func_stats_base; 978 979 u32 wb_comp; 980 u32 wb_data[4]; 981}; 982 983#define bnx2x_sp(bp, var) (&bp->slowpath->var) 984#define bnx2x_sp_mapping(bp, var) \ 985 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 986 987 988/* attn group wiring */ 989#define MAX_DYNAMIC_ATTN_GRPS 8 990 991struct attn_route { 992 u32 sig[5]; 993}; 994 995struct iro { 996 u32 base; 997 u16 m1; 998 u16 m2; 999 u16 m3; 1000 u16 size; 1001}; 1002 1003struct hw_context { 1004 union cdu_context *vcxt; 1005 dma_addr_t cxt_mapping; 1006 size_t size; 1007}; 1008 1009/* forward */ 1010struct bnx2x_ilt; 1011 1012 1013enum bnx2x_recovery_state { 1014 BNX2X_RECOVERY_DONE, 1015 BNX2X_RECOVERY_INIT, 1016 BNX2X_RECOVERY_WAIT, 1017 BNX2X_RECOVERY_FAILED 1018}; 1019 1020/* 1021 * Event queue (EQ or event ring) MC hsi 1022 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1023 */ 1024#define NUM_EQ_PAGES 1 1025#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1026#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1027#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1028#define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1029#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1030 1031/* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1032#define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1033 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1034 1035/* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1036#define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1037 1038#define BNX2X_EQ_INDEX \ 1039 (&bp->def_status_blk->sp_sb.\ 1040 index_values[HC_SP_INDEX_EQ_CONS]) 1041 1042/* This is a data that will be used to create a link report message. 1043 * We will keep the data used for the last link report in order 1044 * to prevent reporting the same link parameters twice. 1045 */ 1046struct bnx2x_link_report_data { 1047 u16 line_speed; /* Effective line speed */ 1048 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1049}; 1050 1051enum { 1052 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1053 BNX2X_LINK_REPORT_LINK_DOWN, 1054 BNX2X_LINK_REPORT_RX_FC_ON, 1055 BNX2X_LINK_REPORT_TX_FC_ON, 1056}; 1057 1058enum { 1059 BNX2X_PORT_QUERY_IDX, 1060 BNX2X_PF_QUERY_IDX, 1061 BNX2X_FIRST_QUEUE_QUERY_IDX, 1062}; 1063 1064struct bnx2x_fw_stats_req { 1065 struct stats_query_header hdr; 1066 struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 1067}; 1068 1069struct bnx2x_fw_stats_data { 1070 struct stats_counter storm_counters; 1071 struct per_port_stats port; 1072 struct per_pf_stats pf; 1073 struct per_queue_stats queue_stats[1]; 1074}; 1075 1076/* Public slow path states */ 1077enum { 1078 BNX2X_SP_RTNL_SETUP_TC, 1079 BNX2X_SP_RTNL_TX_TIMEOUT, 1080}; 1081 1082 1083struct bnx2x { 1084 /* Fields used in the tx and intr/napi performance paths 1085 * are grouped together in the beginning of the structure 1086 */ 1087 struct bnx2x_fastpath *fp; 1088 void __iomem *regview; 1089 void __iomem *doorbells; 1090 u16 db_size; 1091 1092 u8 pf_num; /* absolute PF number */ 1093 u8 pfid; /* per-path PF number */ 1094 int base_fw_ndsb; /**/ 1095#define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1096#define BP_PORT(bp) (bp->pfid & 1) 1097#define BP_FUNC(bp) (bp->pfid) 1098#define BP_ABS_FUNC(bp) (bp->pf_num) 1099#define BP_E1HVN(bp) (bp->pfid >> 1) 1100#define BP_VN(bp) (BP_E1HVN(bp)) /*remove when approved*/ 1101#define BP_L_ID(bp) (BP_E1HVN(bp) << 2) 1102#define BP_FW_MB_IDX(bp) (BP_PORT(bp) +\ 1103 BP_VN(bp) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1104 1105 struct net_device *dev; 1106 struct pci_dev *pdev; 1107 1108 const struct iro *iro_arr; 1109#define IRO (bp->iro_arr) 1110 1111 enum bnx2x_recovery_state recovery_state; 1112 int is_leader; 1113 struct msix_entry *msix_table; 1114 1115 int tx_ring_size; 1116 1117/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1118#define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1119#define ETH_MIN_PACKET_SIZE 60 1120#define ETH_MAX_PACKET_SIZE 1500 1121#define ETH_MAX_JUMBO_PACKET_SIZE 9600 1122 1123 /* Max supported alignment is 256 (8 shift) */ 1124#define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \ 1125 L1_CACHE_SHIFT : 8) 1126 /* FW use 2 Cache lines Alignment for start packet and size */ 1127#define BNX2X_FW_RX_ALIGN (2 << BNX2X_RX_ALIGN_SHIFT) 1128#define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1129 1130 struct host_sp_status_block *def_status_blk; 1131#define DEF_SB_IGU_ID 16 1132#define DEF_SB_ID HC_SP_SB_ID 1133 __le16 def_idx; 1134 __le16 def_att_idx; 1135 u32 attn_state; 1136 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1137 1138 /* slow path ring */ 1139 struct eth_spe *spq; 1140 dma_addr_t spq_mapping; 1141 u16 spq_prod_idx; 1142 struct eth_spe *spq_prod_bd; 1143 struct eth_spe *spq_last_bd; 1144 __le16 *dsb_sp_prod; 1145 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1146 /* used to synchronize spq accesses */ 1147 spinlock_t spq_lock; 1148 1149 /* event queue */ 1150 union event_ring_elem *eq_ring; 1151 dma_addr_t eq_mapping; 1152 u16 eq_prod; 1153 u16 eq_cons; 1154 __le16 *eq_cons_sb; 1155 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1156 1157 1158 1159 /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1160 u16 stats_pending; 1161 /* Counter for completed statistics ramrods */ 1162 u16 stats_comp; 1163 1164 /* End of fields used in the performance code paths */ 1165 1166 int panic; 1167 int msg_enable; 1168 1169 u32 flags; 1170#define PCIX_FLAG (1 << 0) 1171#define PCI_32BIT_FLAG (1 << 1) 1172#define ONE_PORT_FLAG (1 << 2) 1173#define NO_WOL_FLAG (1 << 3) 1174#define USING_DAC_FLAG (1 << 4) 1175#define USING_MSIX_FLAG (1 << 5) 1176#define USING_MSI_FLAG (1 << 6) 1177#define DISABLE_MSI_FLAG (1 << 7) 1178#define TPA_ENABLE_FLAG (1 << 8) 1179#define NO_MCP_FLAG (1 << 9) 1180 1181#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) 1182#define MF_FUNC_DIS (1 << 11) 1183#define OWN_CNIC_IRQ (1 << 12) 1184#define NO_ISCSI_OOO_FLAG (1 << 13) 1185#define NO_ISCSI_FLAG (1 << 14) 1186#define NO_FCOE_FLAG (1 << 15) 1187 1188#define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1189#define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1190#define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1191 1192 int pm_cap; 1193 int mrrs; 1194 1195 struct delayed_work sp_task; 1196 struct delayed_work sp_rtnl_task; 1197 1198 struct delayed_work period_task; 1199 struct timer_list timer; 1200 int current_interval; 1201 1202 u16 fw_seq; 1203 u16 fw_drv_pulse_wr_seq; 1204 u32 func_stx; 1205 1206 struct link_params link_params; 1207 struct link_vars link_vars; 1208 u32 link_cnt; 1209 struct bnx2x_link_report_data last_reported_link; 1210 1211 struct mdio_if_info mdio; 1212 1213 struct bnx2x_common common; 1214 struct bnx2x_port port; 1215 1216 struct cmng_struct_per_port cmng; 1217 u32 vn_weight_sum; 1218 u32 mf_config[E1HVN_MAX]; 1219 u32 mf2_config[E2_FUNC_MAX]; 1220 u32 path_has_ovlan; /* E3 */ 1221 u16 mf_ov; 1222 u8 mf_mode; 1223#define IS_MF(bp) (bp->mf_mode != 0) 1224#define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1225#define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1226 1227 u8 wol; 1228 1229 int rx_ring_size; 1230 1231 u16 tx_quick_cons_trip_int; 1232 u16 tx_quick_cons_trip; 1233 u16 tx_ticks_int; 1234 u16 tx_ticks; 1235 1236 u16 rx_quick_cons_trip_int; 1237 u16 rx_quick_cons_trip; 1238 u16 rx_ticks_int; 1239 u16 rx_ticks; 1240/* Maximal coalescing timeout in us */ 1241#define BNX2X_MAX_COALESCE_TOUT (0xf0*12) 1242 1243 u32 lin_cnt; 1244 1245 u16 state; 1246#define BNX2X_STATE_CLOSED 0 1247#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1248#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1249#define BNX2X_STATE_OPEN 0x3000 1250#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1251#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1252 1253#define BNX2X_STATE_DIAG 0xe000 1254#define BNX2X_STATE_ERROR 0xf000 1255 1256 int multi_mode; 1257#define BNX2X_MAX_PRIORITY 8 1258#define BNX2X_MAX_ENTRIES_PER_PRI 16 1259#define BNX2X_MAX_COS 3 1260#define BNX2X_MAX_TX_COS 2 1261 int num_queues; 1262 int disable_tpa; 1263 1264 u32 rx_mode; 1265#define BNX2X_RX_MODE_NONE 0 1266#define BNX2X_RX_MODE_NORMAL 1 1267#define BNX2X_RX_MODE_ALLMULTI 2 1268#define BNX2X_RX_MODE_PROMISC 3 1269#define BNX2X_MAX_MULTICAST 64 1270 1271 u8 igu_dsb_id; 1272 u8 igu_base_sb; 1273 u8 igu_sb_cnt; 1274 dma_addr_t def_status_blk_mapping; 1275 1276 struct bnx2x_slowpath *slowpath; 1277 dma_addr_t slowpath_mapping; 1278 1279 /* Total number of FW statistics requests */ 1280 u8 fw_stats_num; 1281 1282 /* 1283 * This is a memory buffer that will contain both statistics 1284 * ramrod request and data. 1285 */ 1286 void *fw_stats; 1287 dma_addr_t fw_stats_mapping; 1288 1289 /* 1290 * FW statistics request shortcut (points at the 1291 * beginning of fw_stats buffer). 1292 */ 1293 struct bnx2x_fw_stats_req *fw_stats_req; 1294 dma_addr_t fw_stats_req_mapping; 1295 int fw_stats_req_sz; 1296 1297 /* 1298 * FW statistics data shortcut (points at the begining of 1299 * fw_stats buffer + fw_stats_req_sz). 1300 */ 1301 struct bnx2x_fw_stats_data *fw_stats_data; 1302 dma_addr_t fw_stats_data_mapping; 1303 int fw_stats_data_sz; 1304 1305 struct hw_context context; 1306 1307 struct bnx2x_ilt *ilt; 1308#define BP_ILT(bp) ((bp)->ilt) 1309#define ILT_MAX_LINES 256 1310/* 1311 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1312 * to CNIC. 1313 */ 1314#define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT) 1315 1316/* 1317 * Maximum CID count that might be required by the bnx2x: 1318 * Max Tss * Max_Tx_Multi_Cos + CNIC L2 Clients (FCoE and iSCSI related) 1319 */ 1320#define BNX2X_L2_CID_COUNT(bp) (MAX_TXQS_PER_COS * BNX2X_MULTI_TX_COS +\ 1321 NON_ETH_CONTEXT_USE + CNIC_PRESENT) 1322#define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1323 ILT_PAGE_CIDS)) 1324#define BNX2X_DB_SIZE(bp) (BNX2X_L2_CID_COUNT(bp) * (1 << BNX2X_DB_SHIFT)) 1325 1326 int qm_cid_count; 1327 1328 int dropless_fc; 1329 1330#ifdef BCM_CNIC 1331 u32 cnic_flags; 1332#define BNX2X_CNIC_FLAG_MAC_SET 1 1333 void *t2; 1334 dma_addr_t t2_mapping; 1335 struct cnic_ops __rcu *cnic_ops; 1336 void *cnic_data; 1337 u32 cnic_tag; 1338 struct cnic_eth_dev cnic_eth_dev; 1339 union host_hc_status_block cnic_sb; 1340 dma_addr_t cnic_sb_mapping; 1341 struct eth_spe *cnic_kwq; 1342 struct eth_spe *cnic_kwq_prod; 1343 struct eth_spe *cnic_kwq_cons; 1344 struct eth_spe *cnic_kwq_last; 1345 u16 cnic_kwq_pending; 1346 u16 cnic_spq_pending; 1347 u8 fip_mac[ETH_ALEN]; 1348 struct mutex cnic_mutex; 1349 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1350 1351 /* Start index of the "special" (CNIC related) L2 cleints */ 1352 u8 cnic_base_cl_id; 1353#endif 1354 1355 int dmae_ready; 1356 /* used to synchronize dmae accesses */ 1357 spinlock_t dmae_lock; 1358 1359 /* used to protect the FW mail box */ 1360 struct mutex fw_mb_mutex; 1361 1362 /* used to synchronize stats collecting */ 1363 int stats_state; 1364 1365 /* used for synchronization of concurrent threads statistics handling */ 1366 spinlock_t stats_lock; 1367 1368 /* used by dmae command loader */ 1369 struct dmae_command stats_dmae; 1370 int executer_idx; 1371 1372 u16 stats_counter; 1373 struct bnx2x_eth_stats eth_stats; 1374 1375 struct z_stream_s *strm; 1376 void *gunzip_buf; 1377 dma_addr_t gunzip_mapping; 1378 int gunzip_outlen; 1379#define FW_BUF_SIZE 0x8000 1380#define GUNZIP_BUF(bp) (bp->gunzip_buf) 1381#define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1382#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1383 1384 struct raw_op *init_ops; 1385 /* Init blocks offsets inside init_ops */ 1386 u16 *init_ops_offsets; 1387 /* Data blob - has 32 bit granularity */ 1388 u32 *init_data; 1389 u32 init_mode_flags; 1390#define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1391 /* Zipped PRAM blobs - raw data */ 1392 const u8 *tsem_int_table_data; 1393 const u8 *tsem_pram_data; 1394 const u8 *usem_int_table_data; 1395 const u8 *usem_pram_data; 1396 const u8 *xsem_int_table_data; 1397 const u8 *xsem_pram_data; 1398 const u8 *csem_int_table_data; 1399 const u8 *csem_pram_data; 1400#define INIT_OPS(bp) (bp->init_ops) 1401#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1402#define INIT_DATA(bp) (bp->init_data) 1403#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1404#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1405#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1406#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1407#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1408#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1409#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1410#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1411 1412#define PHY_FW_VER_LEN 20 1413 char fw_ver[32]; 1414 const struct firmware *firmware; 1415 1416 /* DCB support on/off */ 1417 u16 dcb_state; 1418#define BNX2X_DCB_STATE_OFF 0 1419#define BNX2X_DCB_STATE_ON 1 1420 1421 /* DCBX engine mode */ 1422 int dcbx_enabled; 1423#define BNX2X_DCBX_ENABLED_OFF 0 1424#define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1425#define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1426#define BNX2X_DCBX_ENABLED_INVALID (-1) 1427 1428 bool dcbx_mode_uset; 1429 1430 struct bnx2x_config_dcbx_params dcbx_config_params; 1431 struct bnx2x_dcbx_port_params dcbx_port_params; 1432 int dcb_version; 1433 1434 /* CAM credit pools */ 1435 struct bnx2x_credit_pool_obj macs_pool; 1436 1437 /* RX_MODE object */ 1438 struct bnx2x_rx_mode_obj rx_mode_obj; 1439 1440 /* MCAST object */ 1441 struct bnx2x_mcast_obj mcast_obj; 1442 1443 /* RSS configuration object */ 1444 struct bnx2x_rss_config_obj rss_conf_obj; 1445 1446 /* Function State controlling object */ 1447 struct bnx2x_func_sp_obj func_obj; 1448 1449 unsigned long sp_state; 1450 1451 /* operation indication for the sp_rtnl task */ 1452 unsigned long sp_rtnl_state; 1453 1454 /* DCBX Negotation results */ 1455 struct dcbx_features dcbx_local_feat; 1456 u32 dcbx_error; 1457 1458#ifdef BCM_DCBNL 1459 struct dcbx_features dcbx_remote_feat; 1460 u32 dcbx_remote_flags; 1461#endif 1462 u32 pending_max; 1463 1464 /* multiple tx classes of service */ 1465 u8 max_cos; 1466 1467 /* priority to cos mapping */ 1468 u8 prio_to_cos[8]; 1469}; 1470 1471/* Tx queues may be less or equal to Rx queues */ 1472extern int num_queues; 1473#define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 1474#define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE) 1475#define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1476 1477#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1478 1479#define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1480/* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1481 1482#define RSS_IPV4_CAP_MASK \ 1483 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1484 1485#define RSS_IPV4_TCP_CAP_MASK \ 1486 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1487 1488#define RSS_IPV6_CAP_MASK \ 1489 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1490 1491#define RSS_IPV6_TCP_CAP_MASK \ 1492 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1493 1494/* func init flags */ 1495#define FUNC_FLG_RSS 0x0001 1496#define FUNC_FLG_STATS 0x0002 1497/* removed FUNC_FLG_UNMATCHED 0x0004 */ 1498#define FUNC_FLG_TPA 0x0008 1499#define FUNC_FLG_SPQ 0x0010 1500#define FUNC_FLG_LEADING 0x0020 /* PF only */ 1501 1502 1503struct bnx2x_func_init_params { 1504 /* dma */ 1505 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1506 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1507 1508 u16 func_flgs; 1509 u16 func_id; /* abs fid */ 1510 u16 pf_id; 1511 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1512}; 1513 1514#define for_each_eth_queue(bp, var) \ 1515 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1516 1517#define for_each_nondefault_eth_queue(bp, var) \ 1518 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1519 1520#define for_each_queue(bp, var) \ 1521 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1522 if (skip_queue(bp, var)) \ 1523 continue; \ 1524 else 1525 1526/* Skip forwarding FP */ 1527#define for_each_rx_queue(bp, var) \ 1528 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1529 if (skip_rx_queue(bp, var)) \ 1530 continue; \ 1531 else 1532 1533/* Skip OOO FP */ 1534#define for_each_tx_queue(bp, var) \ 1535 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1536 if (skip_tx_queue(bp, var)) \ 1537 continue; \ 1538 else 1539 1540#define for_each_nondefault_queue(bp, var) \ 1541 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1542 if (skip_queue(bp, var)) \ 1543 continue; \ 1544 else 1545 1546#define for_each_cos_in_tx_queue(fp, var) \ 1547 for ((var) = 0; (var) < (fp)->max_cos; (var)++) 1548 1549/* skip rx queue 1550 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1551 */ 1552#define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1553 1554/* skip tx queue 1555 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1556 */ 1557#define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1558 1559#define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1560 1561 1562 1563 1564/** 1565 * bnx2x_set_mac_one - configure a single MAC address 1566 * 1567 * @bp: driver handle 1568 * @mac: MAC to configure 1569 * @obj: MAC object handle 1570 * @set: if 'true' add a new MAC, otherwise - delete 1571 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 1572 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 1573 * 1574 * Configures one MAC according to provided parameters or continues the 1575 * execution of previously scheduled commands if RAMROD_CONT is set in 1576 * ramrod_flags. 1577 * 1578 * Returns zero if operation has successfully completed, a positive value if the 1579 * operation has been successfully scheduled and a negative - if a requested 1580 * operations has failed. 1581 */ 1582int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 1583 struct bnx2x_vlan_mac_obj *obj, bool set, 1584 int mac_type, unsigned long *ramrod_flags); 1585/** 1586 * Deletes all MACs configured for the specific MAC object. 1587 * 1588 * @param bp Function driver instance 1589 * @param mac_obj MAC object to cleanup 1590 * 1591 * @return zero if all MACs were cleaned 1592 */ 1593 1594/** 1595 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 1596 * 1597 * @bp: driver handle 1598 * @mac_obj: MAC object handle 1599 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 1600 * @wait_for_comp: if 'true' block until completion 1601 * 1602 * Deletes all MACs of the specific type (e.g. ETH, UC list). 1603 * 1604 * Returns zero if operation has successfully completed, a positive value if the 1605 * operation has been successfully scheduled and a negative - if a requested 1606 * operations has failed. 1607 */ 1608int bnx2x_del_all_macs(struct bnx2x *bp, 1609 struct bnx2x_vlan_mac_obj *mac_obj, 1610 int mac_type, bool wait_for_comp); 1611 1612/* Init Function API */ 1613void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 1614int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 1615int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1616int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 1617int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1618void bnx2x_read_mf_cfg(struct bnx2x *bp); 1619 1620 1621/* dmae */ 1622void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 1623void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 1624 u32 len32); 1625void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 1626u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 1627u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 1628u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 1629 bool with_comp, u8 comp_type); 1630 1631 1632void bnx2x_calc_fc_adv(struct bnx2x *bp); 1633int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 1634 u32 data_hi, u32 data_lo, int cmd_type); 1635void bnx2x_update_coalesce(struct bnx2x *bp); 1636int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 1637 1638static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 1639 int wait) 1640{ 1641 u32 val; 1642 1643 do { 1644 val = REG_RD(bp, reg); 1645 if (val == expected) 1646 break; 1647 ms -= wait; 1648 msleep(wait); 1649 1650 } while (ms > 0); 1651 1652 return val; 1653} 1654 1655#define BNX2X_ILT_ZALLOC(x, y, size) \ 1656 do { \ 1657 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 1658 if (x) \ 1659 memset(x, 0, size); \ 1660 } while (0) 1661 1662#define BNX2X_ILT_FREE(x, y, size) \ 1663 do { \ 1664 if (x) { \ 1665 dma_free_coherent(&bp->pdev->dev, size, x, y); \ 1666 x = NULL; \ 1667 y = 0; \ 1668 } \ 1669 } while (0) 1670 1671#define ILOG2(x) (ilog2((x))) 1672 1673#define ILT_NUM_PAGE_ENTRIES (3072) 1674/* In 57710/11 we use whole table since we have 8 func 1675 * In 57712 we have only 4 func, but use same size per func, then only half of 1676 * the table in use 1677 */ 1678#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 1679 1680#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 1681/* 1682 * the phys address is shifted right 12 bits and has an added 1683 * 1=valid bit added to the 53rd bit 1684 * then since this is a wide register(TM) 1685 * we split it into two 32 bit writes 1686 */ 1687#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 1688#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 1689 1690/* load/unload mode */ 1691#define LOAD_NORMAL 0 1692#define LOAD_OPEN 1 1693#define LOAD_DIAG 2 1694#define UNLOAD_NORMAL 0 1695#define UNLOAD_CLOSE 1 1696#define UNLOAD_RECOVERY 2 1697 1698 1699/* DMAE command defines */ 1700#define DMAE_TIMEOUT -1 1701#define DMAE_PCI_ERROR -2 /* E2 and onward */ 1702#define DMAE_NOT_RDY -3 1703#define DMAE_PCI_ERR_FLAG 0x80000000 1704 1705#define DMAE_SRC_PCI 0 1706#define DMAE_SRC_GRC 1 1707 1708#define DMAE_DST_NONE 0 1709#define DMAE_DST_PCI 1 1710#define DMAE_DST_GRC 2 1711 1712#define DMAE_COMP_PCI 0 1713#define DMAE_COMP_GRC 1 1714 1715/* E2 and onward - PCI error handling in the completion */ 1716 1717#define DMAE_COMP_REGULAR 0 1718#define DMAE_COM_SET_ERR 1 1719 1720#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 1721 DMAE_COMMAND_SRC_SHIFT) 1722#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 1723 DMAE_COMMAND_SRC_SHIFT) 1724 1725#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 1726 DMAE_COMMAND_DST_SHIFT) 1727#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 1728 DMAE_COMMAND_DST_SHIFT) 1729 1730#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 1731 DMAE_COMMAND_C_DST_SHIFT) 1732#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 1733 DMAE_COMMAND_C_DST_SHIFT) 1734 1735#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 1736 1737#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 1738#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 1739#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 1740#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 1741 1742#define DMAE_CMD_PORT_0 0 1743#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 1744 1745#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 1746#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 1747#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 1748 1749#define DMAE_SRC_PF 0 1750#define DMAE_SRC_VF 1 1751 1752#define DMAE_DST_PF 0 1753#define DMAE_DST_VF 1 1754 1755#define DMAE_C_SRC 0 1756#define DMAE_C_DST 1 1757 1758#define DMAE_LEN32_RD_MAX 0x80 1759#define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 1760 1761#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 1762 indicates eror */ 1763 1764#define MAX_DMAE_C_PER_PORT 8 1765#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 1766 BP_E1HVN(bp)) 1767#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 1768 E1HVN_MAX) 1769 1770/* PCIE link and speed */ 1771#define PCICFG_LINK_WIDTH 0x1f00000 1772#define PCICFG_LINK_WIDTH_SHIFT 20 1773#define PCICFG_LINK_SPEED 0xf0000 1774#define PCICFG_LINK_SPEED_SHIFT 16 1775 1776 1777#define BNX2X_NUM_TESTS 7 1778 1779#define BNX2X_PHY_LOOPBACK 0 1780#define BNX2X_MAC_LOOPBACK 1 1781#define BNX2X_PHY_LOOPBACK_FAILED 1 1782#define BNX2X_MAC_LOOPBACK_FAILED 2 1783#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 1784 BNX2X_PHY_LOOPBACK_FAILED) 1785 1786 1787#define STROM_ASSERT_ARRAY_SIZE 50 1788 1789 1790/* must be used on a CID before placing it on a HW ring */ 1791#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 1792 (BP_E1HVN(bp) << BNX2X_SWCID_SHIFT) | \ 1793 (x)) 1794 1795#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1796#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1797 1798 1799#define BNX2X_BTR 4 1800#define MAX_SPQ_PENDING 8 1801 1802/* CMNG constants, as derived from system spec calculations */ 1803/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 1804#define DEF_MIN_RATE 100 1805/* resolution of the rate shaping timer - 400 usec */ 1806#define RS_PERIODIC_TIMEOUT_USEC 400 1807/* number of bytes in single QM arbitration cycle - 1808 * coefficient for calculating the fairness timer */ 1809#define QM_ARB_BYTES 160000 1810/* resolution of Min algorithm 1:100 */ 1811#define MIN_RES 100 1812/* how many bytes above threshold for the minimal credit of Min algorithm*/ 1813#define MIN_ABOVE_THRESH 32768 1814/* Fairness algorithm integration time coefficient - 1815 * for calculating the actual Tfair */ 1816#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 1817/* Memory of fairness algorithm . 2 cycles */ 1818#define FAIR_MEM 2 1819 1820 1821#define ATTN_NIG_FOR_FUNC (1L << 8) 1822#define ATTN_SW_TIMER_4_FUNC (1L << 9) 1823#define GPIO_2_FUNC (1L << 10) 1824#define GPIO_3_FUNC (1L << 11) 1825#define GPIO_4_FUNC (1L << 12) 1826#define ATTN_GENERAL_ATTN_1 (1L << 13) 1827#define ATTN_GENERAL_ATTN_2 (1L << 14) 1828#define ATTN_GENERAL_ATTN_3 (1L << 15) 1829#define ATTN_GENERAL_ATTN_4 (1L << 13) 1830#define ATTN_GENERAL_ATTN_5 (1L << 14) 1831#define ATTN_GENERAL_ATTN_6 (1L << 15) 1832 1833#define ATTN_HARD_WIRED_MASK 0xff00 1834#define ATTENTION_ID 4 1835 1836 1837/* stuff added to make the code fit 80Col */ 1838 1839#define BNX2X_PMF_LINK_ASSERT \ 1840 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 1841 1842#define BNX2X_MC_ASSERT_BITS \ 1843 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1844 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1845 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1846 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 1847 1848#define BNX2X_MCP_ASSERT \ 1849 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 1850 1851#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 1852#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 1853 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 1854 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 1855 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 1856 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 1857 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 1858 1859#define HW_INTERRUT_ASSERT_SET_0 \ 1860 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 1861 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 1862 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 1863 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 1864#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 1865 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 1866 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 1867 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 1868 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 1869 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 1870 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 1871#define HW_INTERRUT_ASSERT_SET_1 \ 1872 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 1873 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 1874 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 1875 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 1876 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 1877 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 1878 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 1879 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 1880 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 1881 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 1882 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 1883#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 1884 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 1885 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 1886 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 1887 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 1888 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 1889 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 1890 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 1891 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 1892 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 1893 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 1894 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 1895 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 1896 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 1897 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 1898 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 1899#define HW_INTERRUT_ASSERT_SET_2 \ 1900 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 1901 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 1902 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 1903 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 1904 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 1905#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 1906 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 1907 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 1908 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 1909 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 1910 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 1911 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 1912 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 1913 1914#define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 1915 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 1916 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 1917 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 1918 1919#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 1920 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 1921 1922#define RSS_FLAGS(bp) \ 1923 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ 1924 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ 1925 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ 1926 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ 1927 (bp->multi_mode << \ 1928 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT)) 1929#define MULTI_MASK 0x7f 1930 1931 1932#define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 1933#define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 1934#define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 1935#define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 1936 1937#define DEF_USB_IGU_INDEX_OFF \ 1938 offsetof(struct cstorm_def_status_block_u, igu_index) 1939#define DEF_CSB_IGU_INDEX_OFF \ 1940 offsetof(struct cstorm_def_status_block_c, igu_index) 1941#define DEF_XSB_IGU_INDEX_OFF \ 1942 offsetof(struct xstorm_def_status_block, igu_index) 1943#define DEF_TSB_IGU_INDEX_OFF \ 1944 offsetof(struct tstorm_def_status_block, igu_index) 1945 1946#define DEF_USB_SEGMENT_OFF \ 1947 offsetof(struct cstorm_def_status_block_u, segment) 1948#define DEF_CSB_SEGMENT_OFF \ 1949 offsetof(struct cstorm_def_status_block_c, segment) 1950#define DEF_XSB_SEGMENT_OFF \ 1951 offsetof(struct xstorm_def_status_block, segment) 1952#define DEF_TSB_SEGMENT_OFF \ 1953 offsetof(struct tstorm_def_status_block, segment) 1954 1955#define BNX2X_SP_DSB_INDEX \ 1956 (&bp->def_status_blk->sp_sb.\ 1957 index_values[HC_SP_INDEX_ETH_DEF_CONS]) 1958 1959#define SET_FLAG(value, mask, flag) \ 1960 do {\ 1961 (value) &= ~(mask);\ 1962 (value) |= ((flag) << (mask##_SHIFT));\ 1963 } while (0) 1964 1965#define GET_FLAG(value, mask) \ 1966 (((value) & (mask)) >> (mask##_SHIFT)) 1967 1968#define GET_FIELD(value, fname) \ 1969 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 1970 1971#define CAM_IS_INVALID(x) \ 1972 (GET_FLAG(x.flags, \ 1973 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 1974 (T_ETH_MAC_COMMAND_INVALIDATE)) 1975 1976/* Number of u32 elements in MC hash array */ 1977#define MC_HASH_SIZE 8 1978#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 1979 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 1980 1981 1982#ifndef PXP2_REG_PXP2_INT_STS 1983#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 1984#endif 1985 1986#ifndef ETH_MAX_RX_CLIENTS_E2 1987#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 1988#endif 1989 1990#define BNX2X_VPD_LEN 128 1991#define VENDOR_ID_LEN 4 1992 1993/* Congestion management fairness mode */ 1994#define CMNG_FNS_NONE 0 1995#define CMNG_FNS_MINMAX 1 1996 1997#define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 1998#define HC_SEG_ACCESS_ATTN 4 1999#define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2000 2001static const u32 dmae_reg_go_c[] = { 2002 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2003 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2004 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2005 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2006}; 2007 2008void bnx2x_set_ethtool_ops(struct net_device *netdev); 2009void bnx2x_notify_link_changed(struct bnx2x *bp); 2010#endif /* bnx2x.h */ 2011