bnx2x.h revision 56ad315250bec1cd239c18712e072d1ff1f4aaf3
1/* bnx2x.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 */ 13 14#ifndef BNX2X_H 15#define BNX2X_H 16#include <linux/netdevice.h> 17#include <linux/dma-mapping.h> 18#include <linux/types.h> 19 20/* compilation time flags */ 21 22/* define this to make the driver freeze on error to allow getting debug info 23 * (you will need to reboot afterwards) */ 24/* #define BNX2X_STOP_ON_ERROR */ 25 26#define DRV_MODULE_VERSION "1.72.00-0" 27#define DRV_MODULE_RELDATE "2012/01/26" 28#define BNX2X_BC_VER 0x040200 29 30#if defined(CONFIG_DCB) 31#define BCM_DCBNL 32#endif 33#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) 34#define BCM_CNIC 1 35#include "../cnic_if.h" 36#endif 37 38#ifdef BCM_CNIC 39#define BNX2X_MIN_MSIX_VEC_CNT 3 40#define BNX2X_MSIX_VEC_FP_START 2 41#else 42#define BNX2X_MIN_MSIX_VEC_CNT 2 43#define BNX2X_MSIX_VEC_FP_START 1 44#endif 45 46#include <linux/mdio.h> 47 48#include "bnx2x_reg.h" 49#include "bnx2x_fw_defs.h" 50#include "bnx2x_hsi.h" 51#include "bnx2x_link.h" 52#include "bnx2x_sp.h" 53#include "bnx2x_dcb.h" 54#include "bnx2x_stats.h" 55 56/* error/debug prints */ 57 58#define DRV_MODULE_NAME "bnx2x" 59 60/* for messages that are currently off */ 61#define BNX2X_MSG_OFF 0 62#define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */ 63#define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */ 64#define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */ 65#define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */ 66#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ 67#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ 68 69/* regular debug print */ 70#define DP(__mask, fmt, ...) \ 71do { \ 72 if (bp->msg_enable & (__mask)) \ 73 pr_notice("[%s:%d(%s)]" fmt, \ 74 __func__, __LINE__, \ 75 bp->dev ? (bp->dev->name) : "?", \ 76 ##__VA_ARGS__); \ 77} while (0) 78 79#define DP_CONT(__mask, fmt, ...) \ 80do { \ 81 if (bp->msg_enable & (__mask)) \ 82 pr_cont(fmt, ##__VA_ARGS__); \ 83} while (0) 84 85/* errors debug print */ 86#define BNX2X_DBG_ERR(fmt, ...) \ 87do { \ 88 if (netif_msg_probe(bp)) \ 89 pr_err("[%s:%d(%s)]" fmt, \ 90 __func__, __LINE__, \ 91 bp->dev ? (bp->dev->name) : "?", \ 92 ##__VA_ARGS__); \ 93} while (0) 94 95/* for errors (never masked) */ 96#define BNX2X_ERR(fmt, ...) \ 97do { \ 98 pr_err("[%s:%d(%s)]" fmt, \ 99 __func__, __LINE__, \ 100 bp->dev ? (bp->dev->name) : "?", \ 101 ##__VA_ARGS__); \ 102} while (0) 103 104#define BNX2X_ERROR(fmt, ...) \ 105 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 106 107 108/* before we have a dev->name use dev_info() */ 109#define BNX2X_DEV_INFO(fmt, ...) \ 110do { \ 111 if (netif_msg_probe(bp)) \ 112 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 113} while (0) 114 115#ifdef BNX2X_STOP_ON_ERROR 116void bnx2x_int_disable(struct bnx2x *bp); 117#define bnx2x_panic() \ 118do { \ 119 bp->panic = 1; \ 120 BNX2X_ERR("driver assert\n"); \ 121 bnx2x_int_disable(bp); \ 122 bnx2x_panic_dump(bp); \ 123} while (0) 124#else 125#define bnx2x_panic() \ 126do { \ 127 bp->panic = 1; \ 128 BNX2X_ERR("driver assert\n"); \ 129 bnx2x_panic_dump(bp); \ 130} while (0) 131#endif 132 133#define bnx2x_mc_addr(ha) ((ha)->addr) 134#define bnx2x_uc_addr(ha) ((ha)->addr) 135 136#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) 137#define U64_HI(x) (u32)(((u64)(x)) >> 32) 138#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 139 140 141#define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 142 143#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 144#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 145#define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 146 147#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 148#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 149#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 150 151#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 152#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 153 154#define REG_RD_DMAE(bp, offset, valp, len32) \ 155 do { \ 156 bnx2x_read_dmae(bp, offset, len32);\ 157 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 158 } while (0) 159 160#define REG_WR_DMAE(bp, offset, valp, len32) \ 161 do { \ 162 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 163 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 164 offset, len32); \ 165 } while (0) 166 167#define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 168 REG_WR_DMAE(bp, offset, valp, len32) 169 170#define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 171 do { \ 172 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 173 bnx2x_write_big_buf_wb(bp, addr, len32); \ 174 } while (0) 175 176#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 177 offsetof(struct shmem_region, field)) 178#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 179#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 180 181#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 182 offsetof(struct shmem2_region, field)) 183#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 184#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 185#define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 186 offsetof(struct mf_cfg, field)) 187#define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 188 offsetof(struct mf2_cfg, field)) 189 190#define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 191#define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 192 MF_CFG_ADDR(bp, field), (val)) 193#define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 194 195#define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 196 (SHMEM2_RD((bp), size) > \ 197 offsetof(struct shmem2_region, field))) 198 199#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 200#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 201 202/* SP SB indices */ 203 204/* General SP events - stats query, cfc delete, etc */ 205#define HC_SP_INDEX_ETH_DEF_CONS 3 206 207/* EQ completions */ 208#define HC_SP_INDEX_EQ_CONS 7 209 210/* FCoE L2 connection completions */ 211#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 212#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 213/* iSCSI L2 */ 214#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 215#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 216 217/* Special clients parameters */ 218 219/* SB indices */ 220/* FCoE L2 */ 221#define BNX2X_FCOE_L2_RX_INDEX \ 222 (&bp->def_status_blk->sp_sb.\ 223 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 224 225#define BNX2X_FCOE_L2_TX_INDEX \ 226 (&bp->def_status_blk->sp_sb.\ 227 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 228 229/** 230 * CIDs and CLIDs: 231 * CLIDs below is a CLID for func 0, then the CLID for other 232 * functions will be calculated by the formula: 233 * 234 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 235 * 236 */ 237enum { 238 BNX2X_ISCSI_ETH_CL_ID_IDX, 239 BNX2X_FCOE_ETH_CL_ID_IDX, 240 BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 241}; 242 243#define BNX2X_CNIC_START_ETH_CID 48 244enum { 245 /* iSCSI L2 */ 246 BNX2X_ISCSI_ETH_CID = BNX2X_CNIC_START_ETH_CID, 247 /* FCoE L2 */ 248 BNX2X_FCOE_ETH_CID, 249}; 250 251/** Additional rings budgeting */ 252#ifdef BCM_CNIC 253#define CNIC_PRESENT 1 254#define FCOE_PRESENT 1 255#else 256#define CNIC_PRESENT 0 257#define FCOE_PRESENT 0 258#endif /* BCM_CNIC */ 259#define NON_ETH_CONTEXT_USE (FCOE_PRESENT) 260 261#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 262 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 263 264#define SM_RX_ID 0 265#define SM_TX_ID 1 266 267/* defines for multiple tx priority indices */ 268#define FIRST_TX_ONLY_COS_INDEX 1 269#define FIRST_TX_COS_INDEX 0 270 271/* defines for decodeing the fastpath index and the cos index out of the 272 * transmission queue index 273 */ 274#define MAX_TXQS_PER_COS FP_SB_MAX_E1x 275 276#define TXQ_TO_FP(txq_index) ((txq_index) % MAX_TXQS_PER_COS) 277#define TXQ_TO_COS(txq_index) ((txq_index) / MAX_TXQS_PER_COS) 278 279/* rules for calculating the cids of tx-only connections */ 280#define CID_TO_FP(cid) ((cid) % MAX_TXQS_PER_COS) 281#define CID_COS_TO_TX_ONLY_CID(cid, cos) (cid + cos * MAX_TXQS_PER_COS) 282 283/* fp index inside class of service range */ 284#define FP_COS_TO_TXQ(fp, cos) ((fp)->index + cos * MAX_TXQS_PER_COS) 285 286/* 287 * 0..15 eth cos0 288 * 16..31 eth cos1 if applicable 289 * 32..47 eth cos2 If applicable 290 * fcoe queue follows eth queues (16, 32, 48 depending on cos) 291 */ 292#define MAX_ETH_TXQ_IDX(bp) (MAX_TXQS_PER_COS * (bp)->max_cos) 293#define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp)) 294 295/* fast path */ 296/* 297 * This driver uses new build_skb() API : 298 * RX ring buffer contains pointer to kmalloc() data only, 299 * skb are built only after Hardware filled the frame. 300 */ 301struct sw_rx_bd { 302 u8 *data; 303 DEFINE_DMA_UNMAP_ADDR(mapping); 304}; 305 306struct sw_tx_bd { 307 struct sk_buff *skb; 308 u16 first_bd; 309 u8 flags; 310/* Set on the first BD descriptor when there is a split BD */ 311#define BNX2X_TSO_SPLIT_BD (1<<0) 312}; 313 314struct sw_rx_page { 315 struct page *page; 316 DEFINE_DMA_UNMAP_ADDR(mapping); 317}; 318 319union db_prod { 320 struct doorbell_set_prod data; 321 u32 raw; 322}; 323 324/* dropless fc FW/HW related params */ 325#define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 326#define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 327 ETH_MAX_AGGREGATION_QUEUES_E1 :\ 328 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 329#define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 330#define FW_PREFETCH_CNT 16 331#define DROPLESS_FC_HEADROOM 100 332 333/* MC hsi */ 334#define BCM_PAGE_SHIFT 12 335#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 336#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 337#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 338 339#define PAGES_PER_SGE_SHIFT 0 340#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 341#define SGE_PAGE_SIZE PAGE_SIZE 342#define SGE_PAGE_SHIFT PAGE_SHIFT 343#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) 344 345/* SGE ring related macros */ 346#define NUM_RX_SGE_PAGES 2 347#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 348#define NEXT_PAGE_SGE_DESC_CNT 2 349#define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 350/* RX_SGE_CNT is promised to be a power of 2 */ 351#define RX_SGE_MASK (RX_SGE_CNT - 1) 352#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 353#define MAX_RX_SGE (NUM_RX_SGE - 1) 354#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 355 (MAX_RX_SGE_CNT - 1)) ? \ 356 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 357 (x) + 1) 358#define RX_SGE(x) ((x) & MAX_RX_SGE) 359 360/* 361 * Number of required SGEs is the sum of two: 362 * 1. Number of possible opened aggregations (next packet for 363 * these aggregations will probably consume SGE immidiatelly) 364 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 365 * after placement on BD for new TPA aggregation) 366 * 367 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 368 */ 369#define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 370 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 371#define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 372 MAX_RX_SGE_CNT) 373#define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 374 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 375#define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 376 377/* Manipulate a bit vector defined as an array of u64 */ 378 379/* Number of bits in one sge_mask array element */ 380#define BIT_VEC64_ELEM_SZ 64 381#define BIT_VEC64_ELEM_SHIFT 6 382#define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 383 384 385#define __BIT_VEC64_SET_BIT(el, bit) \ 386 do { \ 387 el = ((el) | ((u64)0x1 << (bit))); \ 388 } while (0) 389 390#define __BIT_VEC64_CLEAR_BIT(el, bit) \ 391 do { \ 392 el = ((el) & (~((u64)0x1 << (bit)))); \ 393 } while (0) 394 395 396#define BIT_VEC64_SET_BIT(vec64, idx) \ 397 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 398 (idx) & BIT_VEC64_ELEM_MASK) 399 400#define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 401 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 402 (idx) & BIT_VEC64_ELEM_MASK) 403 404#define BIT_VEC64_TEST_BIT(vec64, idx) \ 405 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 406 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 407 408/* Creates a bitmask of all ones in less significant bits. 409 idx - index of the most significant bit in the created mask */ 410#define BIT_VEC64_ONES_MASK(idx) \ 411 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 412#define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 413 414/*******************************************************/ 415 416 417 418/* Number of u64 elements in SGE mask array */ 419#define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 420#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 421#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 422 423union host_hc_status_block { 424 /* pointer to fp status block e1x */ 425 struct host_hc_status_block_e1x *e1x_sb; 426 /* pointer to fp status block e2 */ 427 struct host_hc_status_block_e2 *e2_sb; 428}; 429 430struct bnx2x_agg_info { 431 /* 432 * First aggregation buffer is a data buffer, the following - are pages. 433 * We will preallocate the data buffer for each aggregation when 434 * we open the interface and will replace the BD at the consumer 435 * with this one when we receive the TPA_START CQE in order to 436 * keep the Rx BD ring consistent. 437 */ 438 struct sw_rx_bd first_buf; 439 u8 tpa_state; 440#define BNX2X_TPA_START 1 441#define BNX2X_TPA_STOP 2 442#define BNX2X_TPA_ERROR 3 443 u8 placement_offset; 444 u16 parsing_flags; 445 u16 vlan_tag; 446 u16 len_on_bd; 447 u32 rxhash; 448}; 449 450#define Q_STATS_OFFSET32(stat_name) \ 451 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 452 453struct bnx2x_fp_txdata { 454 455 struct sw_tx_bd *tx_buf_ring; 456 457 union eth_tx_bd_types *tx_desc_ring; 458 dma_addr_t tx_desc_mapping; 459 460 u32 cid; 461 462 union db_prod tx_db; 463 464 u16 tx_pkt_prod; 465 u16 tx_pkt_cons; 466 u16 tx_bd_prod; 467 u16 tx_bd_cons; 468 469 unsigned long tx_pkt; 470 471 __le16 *tx_cons_sb; 472 473 int txq_index; 474}; 475 476struct bnx2x_fastpath { 477 struct bnx2x *bp; /* parent */ 478 479#define BNX2X_NAPI_WEIGHT 128 480 struct napi_struct napi; 481 union host_hc_status_block status_blk; 482 /* chip independed shortcuts into sb structure */ 483 __le16 *sb_index_values; 484 __le16 *sb_running_index; 485 /* chip independed shortcut into rx_prods_offset memory */ 486 u32 ustorm_rx_prods_offset; 487 488 u32 rx_buf_size; 489 490 dma_addr_t status_blk_mapping; 491 492 u8 max_cos; /* actual number of active tx coses */ 493 struct bnx2x_fp_txdata txdata[BNX2X_MULTI_TX_COS]; 494 495 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 496 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 497 498 struct eth_rx_bd *rx_desc_ring; 499 dma_addr_t rx_desc_mapping; 500 501 union eth_rx_cqe *rx_comp_ring; 502 dma_addr_t rx_comp_mapping; 503 504 /* SGE ring */ 505 struct eth_rx_sge *rx_sge_ring; 506 dma_addr_t rx_sge_mapping; 507 508 u64 sge_mask[RX_SGE_MASK_LEN]; 509 510 u32 cid; 511 512 __le16 fp_hc_idx; 513 514 u8 index; /* number in fp array */ 515 u8 rx_queue; /* index for skb_record */ 516 u8 cl_id; /* eth client id */ 517 u8 cl_qzone_id; 518 u8 fw_sb_id; /* status block number in FW */ 519 u8 igu_sb_id; /* status block number in HW */ 520 521 u16 rx_bd_prod; 522 u16 rx_bd_cons; 523 u16 rx_comp_prod; 524 u16 rx_comp_cons; 525 u16 rx_sge_prod; 526 /* The last maximal completed SGE */ 527 u16 last_max_sge; 528 __le16 *rx_cons_sb; 529 unsigned long rx_pkt, 530 rx_calls; 531 532 /* TPA related */ 533 struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 534 u8 disable_tpa; 535#ifdef BNX2X_STOP_ON_ERROR 536 u64 tpa_queue_used; 537#endif 538 539 struct tstorm_per_queue_stats old_tclient; 540 struct ustorm_per_queue_stats old_uclient; 541 struct xstorm_per_queue_stats old_xclient; 542 struct bnx2x_eth_q_stats eth_q_stats; 543 struct bnx2x_eth_q_stats_old eth_q_stats_old; 544 545 /* The size is calculated using the following: 546 sizeof name field from netdev structure + 547 4 ('-Xx-' string) + 548 4 (for the digits and to make it DWORD aligned) */ 549#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 550 char name[FP_NAME_SIZE]; 551 552 /* MACs object */ 553 struct bnx2x_vlan_mac_obj mac_obj; 554 555 /* Queue State object */ 556 struct bnx2x_queue_sp_obj q_obj; 557 558}; 559 560#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) 561 562/* Use 2500 as a mini-jumbo MTU for FCoE */ 563#define BNX2X_FCOE_MINI_JUMBO_MTU 2500 564 565/* FCoE L2 `fastpath' entry is right after the eth entries */ 566#define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp) 567#define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX]) 568#define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 569#define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 570 txdata[FIRST_TX_COS_INDEX].var) 571 572 573#define IS_ETH_FP(fp) (fp->index < \ 574 BNX2X_NUM_ETH_QUEUES(fp->bp)) 575#ifdef BCM_CNIC 576#define IS_FCOE_FP(fp) (fp->index == FCOE_IDX) 577#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX) 578#else 579#define IS_FCOE_FP(fp) false 580#define IS_FCOE_IDX(idx) false 581#endif 582 583 584/* MC hsi */ 585#define MAX_FETCH_BD 13 /* HW max BDs per packet */ 586#define RX_COPY_THRESH 92 587 588#define NUM_TX_RINGS 16 589#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 590#define NEXT_PAGE_TX_DESC_CNT 1 591#define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 592#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 593#define MAX_TX_BD (NUM_TX_BD - 1) 594#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 595#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 596 (MAX_TX_DESC_CNT - 1)) ? \ 597 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 598 (x) + 1) 599#define TX_BD(x) ((x) & MAX_TX_BD) 600#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 601 602/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 603#define NUM_RX_RINGS 8 604#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 605#define NEXT_PAGE_RX_DESC_CNT 2 606#define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 607#define RX_DESC_MASK (RX_DESC_CNT - 1) 608#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 609#define MAX_RX_BD (NUM_RX_BD - 1) 610#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 611 612/* dropless fc calculations for BDs 613 * 614 * Number of BDs should as number of buffers in BRB: 615 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 616 * "next" elements on each page 617 */ 618#define NUM_BD_REQ BRB_SIZE(bp) 619#define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 620 MAX_RX_DESC_CNT) 621#define BD_TH_LO(bp) (NUM_BD_REQ + \ 622 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 623 FW_DROP_LEVEL(bp)) 624#define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 625 626#define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 627 628#define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 629 ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 630 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 631#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 632#define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 633#define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 634 MIN_RX_AVAIL)) 635 636#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 637 (MAX_RX_DESC_CNT - 1)) ? \ 638 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 639 (x) + 1) 640#define RX_BD(x) ((x) & MAX_RX_BD) 641 642/* 643 * As long as CQE is X times bigger than BD entry we have to allocate X times 644 * more pages for CQ ring in order to keep it balanced with BD ring 645 */ 646#define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 647#define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 648#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 649#define NEXT_PAGE_RCQ_DESC_CNT 1 650#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 651#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 652#define MAX_RCQ_BD (NUM_RCQ_BD - 1) 653#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 654#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 655 (MAX_RCQ_DESC_CNT - 1)) ? \ 656 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 657 (x) + 1) 658#define RCQ_BD(x) ((x) & MAX_RCQ_BD) 659 660/* dropless fc calculations for RCQs 661 * 662 * Number of RCQs should be as number of buffers in BRB: 663 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 664 * "next" elements on each page 665 */ 666#define NUM_RCQ_REQ BRB_SIZE(bp) 667#define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 668 MAX_RCQ_DESC_CNT) 669#define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 670 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 671 FW_DROP_LEVEL(bp)) 672#define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 673 674 675/* This is needed for determining of last_max */ 676#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 677#define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 678 679 680#define BNX2X_SWCID_SHIFT 17 681#define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 682 683/* used on a CID received from the HW */ 684#define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 685#define CQE_CMD(x) (le32_to_cpu(x) >> \ 686 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 687 688#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 689 le32_to_cpu((bd)->addr_lo)) 690#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 691 692#define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 693#define BNX2X_DB_SHIFT 7 /* 128 bytes*/ 694#if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 695#error "Min DB doorbell stride is 8" 696#endif 697#define DPM_TRIGER_TYPE 0x40 698#define DOORBELL(bp, cid, val) \ 699 do { \ 700 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ 701 DPM_TRIGER_TYPE); \ 702 } while (0) 703 704 705/* TX CSUM helpers */ 706#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 707 skb->csum_offset) 708#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 709 skb->csum_offset)) 710 711#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) 712 713#define XMIT_PLAIN 0 714#define XMIT_CSUM_V4 0x1 715#define XMIT_CSUM_V6 0x2 716#define XMIT_CSUM_TCP 0x4 717#define XMIT_GSO_V4 0x8 718#define XMIT_GSO_V6 0x10 719 720#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) 721#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) 722 723 724/* stuff added to make the code fit 80Col */ 725#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 726#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 727#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 728#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 729#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 730 731#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 732 733#define BNX2X_IP_CSUM_ERR(cqe) \ 734 (!((cqe)->fast_path_cqe.status_flags & \ 735 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \ 736 ((cqe)->fast_path_cqe.type_error_flags & \ 737 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) 738 739#define BNX2X_L4_CSUM_ERR(cqe) \ 740 (!((cqe)->fast_path_cqe.status_flags & \ 741 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \ 742 ((cqe)->fast_path_cqe.type_error_flags & \ 743 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) 744 745#define BNX2X_RX_CSUM_OK(cqe) \ 746 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) 747 748#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 749 (((le16_to_cpu(flags) & \ 750 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 751 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 752 == PRS_FLAG_OVERETH_IPV4) 753#define BNX2X_RX_SUM_FIX(cqe) \ 754 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 755 756 757#define FP_USB_FUNC_OFF \ 758 offsetof(struct cstorm_status_block_u, func) 759#define FP_CSB_FUNC_OFF \ 760 offsetof(struct cstorm_status_block_c, func) 761 762#define HC_INDEX_ETH_RX_CQ_CONS 1 763 764#define HC_INDEX_OOO_TX_CQ_CONS 4 765 766#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 767 768#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 769 770#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 771 772#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 773 774#define BNX2X_RX_SB_INDEX \ 775 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 776 777#define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 778 779#define BNX2X_TX_SB_INDEX_COS0 \ 780 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 781 782/* end of fast path */ 783 784/* common */ 785 786struct bnx2x_common { 787 788 u32 chip_id; 789/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 790#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 791 792#define CHIP_NUM(bp) (bp->common.chip_id >> 16) 793#define CHIP_NUM_57710 0x164e 794#define CHIP_NUM_57711 0x164f 795#define CHIP_NUM_57711E 0x1650 796#define CHIP_NUM_57712 0x1662 797#define CHIP_NUM_57712_MF 0x1663 798#define CHIP_NUM_57713 0x1651 799#define CHIP_NUM_57713E 0x1652 800#define CHIP_NUM_57800 0x168a 801#define CHIP_NUM_57800_MF 0x16a5 802#define CHIP_NUM_57810 0x168e 803#define CHIP_NUM_57810_MF 0x16ae 804#define CHIP_NUM_57840 0x168d 805#define CHIP_NUM_57840_MF 0x16ab 806#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 807#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 808#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 809#define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 810#define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 811#define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 812#define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 813#define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 814#define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 815#define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840) 816#define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF) 817#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 818 CHIP_IS_57711E(bp)) 819#define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 820 CHIP_IS_57712_MF(bp)) 821#define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 822 CHIP_IS_57800_MF(bp) || \ 823 CHIP_IS_57810(bp) || \ 824 CHIP_IS_57810_MF(bp) || \ 825 CHIP_IS_57840(bp) || \ 826 CHIP_IS_57840_MF(bp)) 827#define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 828#define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 829#define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 830 831#define CHIP_REV_SHIFT 12 832#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 833#define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 834#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 835#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 836/* assume maximum 5 revisions */ 837#define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 838/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 839#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 840 !(CHIP_REV_VAL(bp) & 0x00001000)) 841/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 842#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 843 (CHIP_REV_VAL(bp) & 0x00001000)) 844 845#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 846 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 847 848#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 849#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 850#define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 851 (CHIP_REV_SHIFT + 1)) \ 852 << CHIP_REV_SHIFT) 853#define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 854 CHIP_REV_SIM(bp) :\ 855 CHIP_REV_VAL(bp)) 856#define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 857 (CHIP_REV(bp) == CHIP_REV_Bx)) 858#define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 859 (CHIP_REV(bp) == CHIP_REV_Ax)) 860 861 int flash_size; 862#define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 863#define BNX2X_NVRAM_TIMEOUT_COUNT 30000 864#define BNX2X_NVRAM_PAGE_SIZE 256 865 866 u32 shmem_base; 867 u32 shmem2_base; 868 u32 mf_cfg_base; 869 u32 mf2_cfg_base; 870 871 u32 hw_config; 872 873 u32 bc_ver; 874 875 u8 int_block; 876#define INT_BLOCK_HC 0 877#define INT_BLOCK_IGU 1 878#define INT_BLOCK_MODE_NORMAL 0 879#define INT_BLOCK_MODE_BW_COMP 2 880#define CHIP_INT_MODE_IS_NBC(bp) \ 881 (!CHIP_IS_E1x(bp) && \ 882 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 883#define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 884 885 u8 chip_port_mode; 886#define CHIP_4_PORT_MODE 0x0 887#define CHIP_2_PORT_MODE 0x1 888#define CHIP_PORT_MODE_NONE 0x2 889#define CHIP_MODE(bp) (bp->common.chip_port_mode) 890#define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 891 892 u32 boot_mode; 893}; 894 895/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 896#define BNX2X_IGU_STAS_MSG_VF_CNT 64 897#define BNX2X_IGU_STAS_MSG_PF_CNT 4 898 899/* end of common */ 900 901/* port */ 902 903struct bnx2x_port { 904 u32 pmf; 905 906 u32 link_config[LINK_CONFIG_SIZE]; 907 908 u32 supported[LINK_CONFIG_SIZE]; 909/* link settings - missing defines */ 910#define SUPPORTED_2500baseX_Full (1 << 15) 911 912 u32 advertising[LINK_CONFIG_SIZE]; 913/* link settings - missing defines */ 914#define ADVERTISED_2500baseX_Full (1 << 15) 915 916 u32 phy_addr; 917 918 /* used to synchronize phy accesses */ 919 struct mutex phy_mutex; 920 int need_hw_lock; 921 922 u32 port_stx; 923 924 struct nig_stats old_nig_stats; 925}; 926 927/* end of port */ 928 929#define STATS_OFFSET32(stat_name) \ 930 (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 931 932/* slow path */ 933 934/* slow path work-queue */ 935extern struct workqueue_struct *bnx2x_wq; 936 937#define BNX2X_MAX_NUM_OF_VFS 64 938#define BNX2X_VF_ID_INVALID 0xFF 939 940/* 941 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 942 * control by the number of fast-path status blocks supported by the 943 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 944 * status block represents an independent interrupts context that can 945 * serve a regular L2 networking queue. However special L2 queues such 946 * as the FCoE queue do not require a FP-SB and other components like 947 * the CNIC may consume FP-SB reducing the number of possible L2 queues 948 * 949 * If the maximum number of FP-SB available is X then: 950 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 951 * regular L2 queues is Y=X-1 952 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 953 * c. If the FCoE L2 queue is supported the actual number of L2 queues 954 * is Y+1 955 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 956 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 957 * FP interrupt context for the CNIC). 958 * e. The number of HW context (CID count) is always X or X+1 if FCoE 959 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 960 */ 961 962/* fast-path interrupt contexts E1x */ 963#define FP_SB_MAX_E1x 16 964/* fast-path interrupt contexts E2 */ 965#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 966 967union cdu_context { 968 struct eth_context eth; 969 char pad[1024]; 970}; 971 972/* CDU host DB constants */ 973#define CDU_ILT_PAGE_SZ_HW 3 974#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 64K */ 975#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 976 977#ifdef BCM_CNIC 978#define CNIC_ISCSI_CID_MAX 256 979#define CNIC_FCOE_CID_MAX 2048 980#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 981#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 982#endif 983 984#define QM_ILT_PAGE_SZ_HW 0 985#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 986#define QM_CID_ROUND 1024 987 988#ifdef BCM_CNIC 989/* TM (timers) host DB constants */ 990#define TM_ILT_PAGE_SZ_HW 0 991#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 992/* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 993#define TM_CONN_NUM 1024 994#define TM_ILT_SZ (8 * TM_CONN_NUM) 995#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 996 997/* SRC (Searcher) host DB constants */ 998#define SRC_ILT_PAGE_SZ_HW 0 999#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1000#define SRC_HASH_BITS 10 1001#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1002#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1003#define SRC_T2_SZ SRC_ILT_SZ 1004#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1005 1006#endif 1007 1008#define MAX_DMAE_C 8 1009 1010/* DMA memory not used in fastpath */ 1011struct bnx2x_slowpath { 1012 union { 1013 struct mac_configuration_cmd e1x; 1014 struct eth_classify_rules_ramrod_data e2; 1015 } mac_rdata; 1016 1017 1018 union { 1019 struct tstorm_eth_mac_filter_config e1x; 1020 struct eth_filter_rules_ramrod_data e2; 1021 } rx_mode_rdata; 1022 1023 union { 1024 struct mac_configuration_cmd e1; 1025 struct eth_multicast_rules_ramrod_data e2; 1026 } mcast_rdata; 1027 1028 struct eth_rss_update_ramrod_data rss_rdata; 1029 1030 /* Queue State related ramrods are always sent under rtnl_lock */ 1031 union { 1032 struct client_init_ramrod_data init_data; 1033 struct client_update_ramrod_data update_data; 1034 } q_rdata; 1035 1036 union { 1037 struct function_start_data func_start; 1038 /* pfc configuration for DCBX ramrod */ 1039 struct flow_control_configuration pfc_config; 1040 } func_rdata; 1041 1042 /* used by dmae command executer */ 1043 struct dmae_command dmae[MAX_DMAE_C]; 1044 1045 u32 stats_comp; 1046 union mac_stats mac_stats; 1047 struct nig_stats nig_stats; 1048 struct host_port_stats port_stats; 1049 struct host_func_stats func_stats; 1050 1051 u32 wb_comp; 1052 u32 wb_data[4]; 1053 1054 union drv_info_to_mcp drv_info_to_mcp; 1055}; 1056 1057#define bnx2x_sp(bp, var) (&bp->slowpath->var) 1058#define bnx2x_sp_mapping(bp, var) \ 1059 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1060 1061 1062/* attn group wiring */ 1063#define MAX_DYNAMIC_ATTN_GRPS 8 1064 1065struct attn_route { 1066 u32 sig[5]; 1067}; 1068 1069struct iro { 1070 u32 base; 1071 u16 m1; 1072 u16 m2; 1073 u16 m3; 1074 u16 size; 1075}; 1076 1077struct hw_context { 1078 union cdu_context *vcxt; 1079 dma_addr_t cxt_mapping; 1080 size_t size; 1081}; 1082 1083/* forward */ 1084struct bnx2x_ilt; 1085 1086 1087enum bnx2x_recovery_state { 1088 BNX2X_RECOVERY_DONE, 1089 BNX2X_RECOVERY_INIT, 1090 BNX2X_RECOVERY_WAIT, 1091 BNX2X_RECOVERY_FAILED, 1092 BNX2X_RECOVERY_NIC_LOADING 1093}; 1094 1095/* 1096 * Event queue (EQ or event ring) MC hsi 1097 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1098 */ 1099#define NUM_EQ_PAGES 1 1100#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1101#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1102#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1103#define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1104#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1105 1106/* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1107#define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1108 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1109 1110/* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1111#define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1112 1113#define BNX2X_EQ_INDEX \ 1114 (&bp->def_status_blk->sp_sb.\ 1115 index_values[HC_SP_INDEX_EQ_CONS]) 1116 1117/* This is a data that will be used to create a link report message. 1118 * We will keep the data used for the last link report in order 1119 * to prevent reporting the same link parameters twice. 1120 */ 1121struct bnx2x_link_report_data { 1122 u16 line_speed; /* Effective line speed */ 1123 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1124}; 1125 1126enum { 1127 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1128 BNX2X_LINK_REPORT_LINK_DOWN, 1129 BNX2X_LINK_REPORT_RX_FC_ON, 1130 BNX2X_LINK_REPORT_TX_FC_ON, 1131}; 1132 1133enum { 1134 BNX2X_PORT_QUERY_IDX, 1135 BNX2X_PF_QUERY_IDX, 1136 BNX2X_FCOE_QUERY_IDX, 1137 BNX2X_FIRST_QUEUE_QUERY_IDX, 1138}; 1139 1140struct bnx2x_fw_stats_req { 1141 struct stats_query_header hdr; 1142 struct stats_query_entry query[FP_SB_MAX_E1x+ 1143 BNX2X_FIRST_QUEUE_QUERY_IDX]; 1144}; 1145 1146struct bnx2x_fw_stats_data { 1147 struct stats_counter storm_counters; 1148 struct per_port_stats port; 1149 struct per_pf_stats pf; 1150 struct fcoe_statistics_params fcoe; 1151 struct per_queue_stats queue_stats[1]; 1152}; 1153 1154/* Public slow path states */ 1155enum { 1156 BNX2X_SP_RTNL_SETUP_TC, 1157 BNX2X_SP_RTNL_TX_TIMEOUT, 1158 BNX2X_SP_RTNL_FAN_FAILURE, 1159}; 1160 1161 1162struct bnx2x { 1163 /* Fields used in the tx and intr/napi performance paths 1164 * are grouped together in the beginning of the structure 1165 */ 1166 struct bnx2x_fastpath *fp; 1167 void __iomem *regview; 1168 void __iomem *doorbells; 1169 u16 db_size; 1170 1171 u8 pf_num; /* absolute PF number */ 1172 u8 pfid; /* per-path PF number */ 1173 int base_fw_ndsb; /**/ 1174#define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1175#define BP_PORT(bp) (bp->pfid & 1) 1176#define BP_FUNC(bp) (bp->pfid) 1177#define BP_ABS_FUNC(bp) (bp->pf_num) 1178#define BP_VN(bp) ((bp)->pfid >> 1) 1179#define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 1180#define BP_L_ID(bp) (BP_VN(bp) << 2) 1181#define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 1182 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1183#define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1184 1185 struct net_device *dev; 1186 struct pci_dev *pdev; 1187 1188 const struct iro *iro_arr; 1189#define IRO (bp->iro_arr) 1190 1191 enum bnx2x_recovery_state recovery_state; 1192 int is_leader; 1193 struct msix_entry *msix_table; 1194 1195 int tx_ring_size; 1196 1197/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1198#define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1199#define ETH_MIN_PACKET_SIZE 60 1200#define ETH_MAX_PACKET_SIZE 1500 1201#define ETH_MAX_JUMBO_PACKET_SIZE 9600 1202 1203 /* Max supported alignment is 256 (8 shift) */ 1204#define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) 1205 1206 /* FW uses 2 Cache lines Alignment for start packet and size 1207 * 1208 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1209 * at the end of skb->data, to avoid wasting a full cache line. 1210 * This reduces memory use (skb->truesize). 1211 */ 1212#define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1213 1214#define BNX2X_FW_RX_ALIGN_END \ 1215 max(1UL << BNX2X_RX_ALIGN_SHIFT, \ 1216 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1217 1218#define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1219 1220 struct host_sp_status_block *def_status_blk; 1221#define DEF_SB_IGU_ID 16 1222#define DEF_SB_ID HC_SP_SB_ID 1223 __le16 def_idx; 1224 __le16 def_att_idx; 1225 u32 attn_state; 1226 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1227 1228 /* slow path ring */ 1229 struct eth_spe *spq; 1230 dma_addr_t spq_mapping; 1231 u16 spq_prod_idx; 1232 struct eth_spe *spq_prod_bd; 1233 struct eth_spe *spq_last_bd; 1234 __le16 *dsb_sp_prod; 1235 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1236 /* used to synchronize spq accesses */ 1237 spinlock_t spq_lock; 1238 1239 /* event queue */ 1240 union event_ring_elem *eq_ring; 1241 dma_addr_t eq_mapping; 1242 u16 eq_prod; 1243 u16 eq_cons; 1244 __le16 *eq_cons_sb; 1245 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1246 1247 1248 1249 /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1250 u16 stats_pending; 1251 /* Counter for completed statistics ramrods */ 1252 u16 stats_comp; 1253 1254 /* End of fields used in the performance code paths */ 1255 1256 int panic; 1257 int msg_enable; 1258 1259 u32 flags; 1260#define PCIX_FLAG (1 << 0) 1261#define PCI_32BIT_FLAG (1 << 1) 1262#define ONE_PORT_FLAG (1 << 2) 1263#define NO_WOL_FLAG (1 << 3) 1264#define USING_DAC_FLAG (1 << 4) 1265#define USING_MSIX_FLAG (1 << 5) 1266#define USING_MSI_FLAG (1 << 6) 1267#define DISABLE_MSI_FLAG (1 << 7) 1268#define TPA_ENABLE_FLAG (1 << 8) 1269#define NO_MCP_FLAG (1 << 9) 1270 1271#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) 1272#define MF_FUNC_DIS (1 << 11) 1273#define OWN_CNIC_IRQ (1 << 12) 1274#define NO_ISCSI_OOO_FLAG (1 << 13) 1275#define NO_ISCSI_FLAG (1 << 14) 1276#define NO_FCOE_FLAG (1 << 15) 1277#define BC_SUPPORTS_PFC_STATS (1 << 17) 1278 1279#define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1280#define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1281#define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1282 1283 int pm_cap; 1284 int mrrs; 1285 1286 struct delayed_work sp_task; 1287 struct delayed_work sp_rtnl_task; 1288 1289 struct delayed_work period_task; 1290 struct timer_list timer; 1291 int current_interval; 1292 1293 u16 fw_seq; 1294 u16 fw_drv_pulse_wr_seq; 1295 u32 func_stx; 1296 1297 struct link_params link_params; 1298 struct link_vars link_vars; 1299 u32 link_cnt; 1300 struct bnx2x_link_report_data last_reported_link; 1301 1302 struct mdio_if_info mdio; 1303 1304 struct bnx2x_common common; 1305 struct bnx2x_port port; 1306 1307 struct cmng_struct_per_port cmng; 1308 u32 vn_weight_sum; 1309 u32 mf_config[E1HVN_MAX]; 1310 u32 mf2_config[E2_FUNC_MAX]; 1311 u32 path_has_ovlan; /* E3 */ 1312 u16 mf_ov; 1313 u8 mf_mode; 1314#define IS_MF(bp) (bp->mf_mode != 0) 1315#define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1316#define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1317 1318 u8 wol; 1319 1320 int rx_ring_size; 1321 1322 u16 tx_quick_cons_trip_int; 1323 u16 tx_quick_cons_trip; 1324 u16 tx_ticks_int; 1325 u16 tx_ticks; 1326 1327 u16 rx_quick_cons_trip_int; 1328 u16 rx_quick_cons_trip; 1329 u16 rx_ticks_int; 1330 u16 rx_ticks; 1331/* Maximal coalescing timeout in us */ 1332#define BNX2X_MAX_COALESCE_TOUT (0xf0*12) 1333 1334 u32 lin_cnt; 1335 1336 u16 state; 1337#define BNX2X_STATE_CLOSED 0 1338#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1339#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1340#define BNX2X_STATE_OPEN 0x3000 1341#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1342#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1343 1344#define BNX2X_STATE_DIAG 0xe000 1345#define BNX2X_STATE_ERROR 0xf000 1346 1347 int multi_mode; 1348#define BNX2X_MAX_PRIORITY 8 1349#define BNX2X_MAX_ENTRIES_PER_PRI 16 1350#define BNX2X_MAX_COS 3 1351#define BNX2X_MAX_TX_COS 2 1352 int num_queues; 1353 int disable_tpa; 1354 1355 u32 rx_mode; 1356#define BNX2X_RX_MODE_NONE 0 1357#define BNX2X_RX_MODE_NORMAL 1 1358#define BNX2X_RX_MODE_ALLMULTI 2 1359#define BNX2X_RX_MODE_PROMISC 3 1360#define BNX2X_MAX_MULTICAST 64 1361 1362 u8 igu_dsb_id; 1363 u8 igu_base_sb; 1364 u8 igu_sb_cnt; 1365 dma_addr_t def_status_blk_mapping; 1366 1367 struct bnx2x_slowpath *slowpath; 1368 dma_addr_t slowpath_mapping; 1369 1370 /* Total number of FW statistics requests */ 1371 u8 fw_stats_num; 1372 1373 /* 1374 * This is a memory buffer that will contain both statistics 1375 * ramrod request and data. 1376 */ 1377 void *fw_stats; 1378 dma_addr_t fw_stats_mapping; 1379 1380 /* 1381 * FW statistics request shortcut (points at the 1382 * beginning of fw_stats buffer). 1383 */ 1384 struct bnx2x_fw_stats_req *fw_stats_req; 1385 dma_addr_t fw_stats_req_mapping; 1386 int fw_stats_req_sz; 1387 1388 /* 1389 * FW statistics data shortcut (points at the begining of 1390 * fw_stats buffer + fw_stats_req_sz). 1391 */ 1392 struct bnx2x_fw_stats_data *fw_stats_data; 1393 dma_addr_t fw_stats_data_mapping; 1394 int fw_stats_data_sz; 1395 1396 struct hw_context context; 1397 1398 struct bnx2x_ilt *ilt; 1399#define BP_ILT(bp) ((bp)->ilt) 1400#define ILT_MAX_LINES 256 1401/* 1402 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1403 * to CNIC. 1404 */ 1405#define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT) 1406 1407/* 1408 * Maximum CID count that might be required by the bnx2x: 1409 * Max Tss * Max_Tx_Multi_Cos + CNIC L2 Clients (FCoE and iSCSI related) 1410 */ 1411#define BNX2X_L2_CID_COUNT(bp) (MAX_TXQS_PER_COS * BNX2X_MULTI_TX_COS +\ 1412 NON_ETH_CONTEXT_USE + CNIC_PRESENT) 1413#define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1414 ILT_PAGE_CIDS)) 1415#define BNX2X_DB_SIZE(bp) (BNX2X_L2_CID_COUNT(bp) * (1 << BNX2X_DB_SHIFT)) 1416 1417 int qm_cid_count; 1418 1419 int dropless_fc; 1420 1421#ifdef BCM_CNIC 1422 u32 cnic_flags; 1423#define BNX2X_CNIC_FLAG_MAC_SET 1 1424 void *t2; 1425 dma_addr_t t2_mapping; 1426 struct cnic_ops __rcu *cnic_ops; 1427 void *cnic_data; 1428 u32 cnic_tag; 1429 struct cnic_eth_dev cnic_eth_dev; 1430 union host_hc_status_block cnic_sb; 1431 dma_addr_t cnic_sb_mapping; 1432 struct eth_spe *cnic_kwq; 1433 struct eth_spe *cnic_kwq_prod; 1434 struct eth_spe *cnic_kwq_cons; 1435 struct eth_spe *cnic_kwq_last; 1436 u16 cnic_kwq_pending; 1437 u16 cnic_spq_pending; 1438 u8 fip_mac[ETH_ALEN]; 1439 struct mutex cnic_mutex; 1440 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1441 1442 /* Start index of the "special" (CNIC related) L2 cleints */ 1443 u8 cnic_base_cl_id; 1444#endif 1445 1446 int dmae_ready; 1447 /* used to synchronize dmae accesses */ 1448 spinlock_t dmae_lock; 1449 1450 /* used to protect the FW mail box */ 1451 struct mutex fw_mb_mutex; 1452 1453 /* used to synchronize stats collecting */ 1454 int stats_state; 1455 1456 /* used for synchronization of concurrent threads statistics handling */ 1457 spinlock_t stats_lock; 1458 1459 /* used by dmae command loader */ 1460 struct dmae_command stats_dmae; 1461 int executer_idx; 1462 1463 u16 stats_counter; 1464 struct bnx2x_eth_stats eth_stats; 1465 struct bnx2x_eth_stats_old eth_stats_old; 1466 struct bnx2x_net_stats_old net_stats_old; 1467 struct bnx2x_fw_port_stats_old fw_stats_old; 1468 bool stats_init; 1469 1470 struct z_stream_s *strm; 1471 void *gunzip_buf; 1472 dma_addr_t gunzip_mapping; 1473 int gunzip_outlen; 1474#define FW_BUF_SIZE 0x8000 1475#define GUNZIP_BUF(bp) (bp->gunzip_buf) 1476#define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1477#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1478 1479 struct raw_op *init_ops; 1480 /* Init blocks offsets inside init_ops */ 1481 u16 *init_ops_offsets; 1482 /* Data blob - has 32 bit granularity */ 1483 u32 *init_data; 1484 u32 init_mode_flags; 1485#define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1486 /* Zipped PRAM blobs - raw data */ 1487 const u8 *tsem_int_table_data; 1488 const u8 *tsem_pram_data; 1489 const u8 *usem_int_table_data; 1490 const u8 *usem_pram_data; 1491 const u8 *xsem_int_table_data; 1492 const u8 *xsem_pram_data; 1493 const u8 *csem_int_table_data; 1494 const u8 *csem_pram_data; 1495#define INIT_OPS(bp) (bp->init_ops) 1496#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1497#define INIT_DATA(bp) (bp->init_data) 1498#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1499#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1500#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1501#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1502#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1503#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1504#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1505#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1506 1507#define PHY_FW_VER_LEN 20 1508 char fw_ver[32]; 1509 const struct firmware *firmware; 1510 1511 /* DCB support on/off */ 1512 u16 dcb_state; 1513#define BNX2X_DCB_STATE_OFF 0 1514#define BNX2X_DCB_STATE_ON 1 1515 1516 /* DCBX engine mode */ 1517 int dcbx_enabled; 1518#define BNX2X_DCBX_ENABLED_OFF 0 1519#define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1520#define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1521#define BNX2X_DCBX_ENABLED_INVALID (-1) 1522 1523 bool dcbx_mode_uset; 1524 1525 struct bnx2x_config_dcbx_params dcbx_config_params; 1526 struct bnx2x_dcbx_port_params dcbx_port_params; 1527 int dcb_version; 1528 1529 /* CAM credit pools */ 1530 struct bnx2x_credit_pool_obj macs_pool; 1531 1532 /* RX_MODE object */ 1533 struct bnx2x_rx_mode_obj rx_mode_obj; 1534 1535 /* MCAST object */ 1536 struct bnx2x_mcast_obj mcast_obj; 1537 1538 /* RSS configuration object */ 1539 struct bnx2x_rss_config_obj rss_conf_obj; 1540 1541 /* Function State controlling object */ 1542 struct bnx2x_func_sp_obj func_obj; 1543 1544 unsigned long sp_state; 1545 1546 /* operation indication for the sp_rtnl task */ 1547 unsigned long sp_rtnl_state; 1548 1549 /* DCBX Negotation results */ 1550 struct dcbx_features dcbx_local_feat; 1551 u32 dcbx_error; 1552 1553#ifdef BCM_DCBNL 1554 struct dcbx_features dcbx_remote_feat; 1555 u32 dcbx_remote_flags; 1556#endif 1557 u32 pending_max; 1558 1559 /* multiple tx classes of service */ 1560 u8 max_cos; 1561 1562 /* priority to cos mapping */ 1563 u8 prio_to_cos[8]; 1564}; 1565 1566/* Tx queues may be less or equal to Rx queues */ 1567extern int num_queues; 1568#define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 1569#define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE) 1570#define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1571 1572#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1573 1574#define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1575/* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1576 1577#define RSS_IPV4_CAP_MASK \ 1578 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1579 1580#define RSS_IPV4_TCP_CAP_MASK \ 1581 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1582 1583#define RSS_IPV6_CAP_MASK \ 1584 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1585 1586#define RSS_IPV6_TCP_CAP_MASK \ 1587 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1588 1589/* func init flags */ 1590#define FUNC_FLG_RSS 0x0001 1591#define FUNC_FLG_STATS 0x0002 1592/* removed FUNC_FLG_UNMATCHED 0x0004 */ 1593#define FUNC_FLG_TPA 0x0008 1594#define FUNC_FLG_SPQ 0x0010 1595#define FUNC_FLG_LEADING 0x0020 /* PF only */ 1596 1597 1598struct bnx2x_func_init_params { 1599 /* dma */ 1600 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1601 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1602 1603 u16 func_flgs; 1604 u16 func_id; /* abs fid */ 1605 u16 pf_id; 1606 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1607}; 1608 1609#define for_each_eth_queue(bp, var) \ 1610 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1611 1612#define for_each_nondefault_eth_queue(bp, var) \ 1613 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1614 1615#define for_each_queue(bp, var) \ 1616 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1617 if (skip_queue(bp, var)) \ 1618 continue; \ 1619 else 1620 1621/* Skip forwarding FP */ 1622#define for_each_rx_queue(bp, var) \ 1623 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1624 if (skip_rx_queue(bp, var)) \ 1625 continue; \ 1626 else 1627 1628/* Skip OOO FP */ 1629#define for_each_tx_queue(bp, var) \ 1630 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1631 if (skip_tx_queue(bp, var)) \ 1632 continue; \ 1633 else 1634 1635#define for_each_nondefault_queue(bp, var) \ 1636 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1637 if (skip_queue(bp, var)) \ 1638 continue; \ 1639 else 1640 1641#define for_each_cos_in_tx_queue(fp, var) \ 1642 for ((var) = 0; (var) < (fp)->max_cos; (var)++) 1643 1644/* skip rx queue 1645 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1646 */ 1647#define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1648 1649/* skip tx queue 1650 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1651 */ 1652#define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1653 1654#define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1655 1656 1657 1658 1659/** 1660 * bnx2x_set_mac_one - configure a single MAC address 1661 * 1662 * @bp: driver handle 1663 * @mac: MAC to configure 1664 * @obj: MAC object handle 1665 * @set: if 'true' add a new MAC, otherwise - delete 1666 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 1667 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 1668 * 1669 * Configures one MAC according to provided parameters or continues the 1670 * execution of previously scheduled commands if RAMROD_CONT is set in 1671 * ramrod_flags. 1672 * 1673 * Returns zero if operation has successfully completed, a positive value if the 1674 * operation has been successfully scheduled and a negative - if a requested 1675 * operations has failed. 1676 */ 1677int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 1678 struct bnx2x_vlan_mac_obj *obj, bool set, 1679 int mac_type, unsigned long *ramrod_flags); 1680/** 1681 * Deletes all MACs configured for the specific MAC object. 1682 * 1683 * @param bp Function driver instance 1684 * @param mac_obj MAC object to cleanup 1685 * 1686 * @return zero if all MACs were cleaned 1687 */ 1688 1689/** 1690 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 1691 * 1692 * @bp: driver handle 1693 * @mac_obj: MAC object handle 1694 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 1695 * @wait_for_comp: if 'true' block until completion 1696 * 1697 * Deletes all MACs of the specific type (e.g. ETH, UC list). 1698 * 1699 * Returns zero if operation has successfully completed, a positive value if the 1700 * operation has been successfully scheduled and a negative - if a requested 1701 * operations has failed. 1702 */ 1703int bnx2x_del_all_macs(struct bnx2x *bp, 1704 struct bnx2x_vlan_mac_obj *mac_obj, 1705 int mac_type, bool wait_for_comp); 1706 1707/* Init Function API */ 1708void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 1709int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 1710int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1711int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 1712int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1713void bnx2x_read_mf_cfg(struct bnx2x *bp); 1714 1715 1716/* dmae */ 1717void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 1718void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 1719 u32 len32); 1720void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 1721u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 1722u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 1723u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 1724 bool with_comp, u8 comp_type); 1725 1726 1727void bnx2x_calc_fc_adv(struct bnx2x *bp); 1728int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 1729 u32 data_hi, u32 data_lo, int cmd_type); 1730void bnx2x_update_coalesce(struct bnx2x *bp); 1731int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 1732 1733static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 1734 int wait) 1735{ 1736 u32 val; 1737 1738 do { 1739 val = REG_RD(bp, reg); 1740 if (val == expected) 1741 break; 1742 ms -= wait; 1743 msleep(wait); 1744 1745 } while (ms > 0); 1746 1747 return val; 1748} 1749 1750#define BNX2X_ILT_ZALLOC(x, y, size) \ 1751 do { \ 1752 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 1753 if (x) \ 1754 memset(x, 0, size); \ 1755 } while (0) 1756 1757#define BNX2X_ILT_FREE(x, y, size) \ 1758 do { \ 1759 if (x) { \ 1760 dma_free_coherent(&bp->pdev->dev, size, x, y); \ 1761 x = NULL; \ 1762 y = 0; \ 1763 } \ 1764 } while (0) 1765 1766#define ILOG2(x) (ilog2((x))) 1767 1768#define ILT_NUM_PAGE_ENTRIES (3072) 1769/* In 57710/11 we use whole table since we have 8 func 1770 * In 57712 we have only 4 func, but use same size per func, then only half of 1771 * the table in use 1772 */ 1773#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 1774 1775#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 1776/* 1777 * the phys address is shifted right 12 bits and has an added 1778 * 1=valid bit added to the 53rd bit 1779 * then since this is a wide register(TM) 1780 * we split it into two 32 bit writes 1781 */ 1782#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 1783#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 1784 1785/* load/unload mode */ 1786#define LOAD_NORMAL 0 1787#define LOAD_OPEN 1 1788#define LOAD_DIAG 2 1789#define UNLOAD_NORMAL 0 1790#define UNLOAD_CLOSE 1 1791#define UNLOAD_RECOVERY 2 1792 1793 1794/* DMAE command defines */ 1795#define DMAE_TIMEOUT -1 1796#define DMAE_PCI_ERROR -2 /* E2 and onward */ 1797#define DMAE_NOT_RDY -3 1798#define DMAE_PCI_ERR_FLAG 0x80000000 1799 1800#define DMAE_SRC_PCI 0 1801#define DMAE_SRC_GRC 1 1802 1803#define DMAE_DST_NONE 0 1804#define DMAE_DST_PCI 1 1805#define DMAE_DST_GRC 2 1806 1807#define DMAE_COMP_PCI 0 1808#define DMAE_COMP_GRC 1 1809 1810/* E2 and onward - PCI error handling in the completion */ 1811 1812#define DMAE_COMP_REGULAR 0 1813#define DMAE_COM_SET_ERR 1 1814 1815#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 1816 DMAE_COMMAND_SRC_SHIFT) 1817#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 1818 DMAE_COMMAND_SRC_SHIFT) 1819 1820#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 1821 DMAE_COMMAND_DST_SHIFT) 1822#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 1823 DMAE_COMMAND_DST_SHIFT) 1824 1825#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 1826 DMAE_COMMAND_C_DST_SHIFT) 1827#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 1828 DMAE_COMMAND_C_DST_SHIFT) 1829 1830#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 1831 1832#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 1833#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 1834#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 1835#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 1836 1837#define DMAE_CMD_PORT_0 0 1838#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 1839 1840#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 1841#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 1842#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 1843 1844#define DMAE_SRC_PF 0 1845#define DMAE_SRC_VF 1 1846 1847#define DMAE_DST_PF 0 1848#define DMAE_DST_VF 1 1849 1850#define DMAE_C_SRC 0 1851#define DMAE_C_DST 1 1852 1853#define DMAE_LEN32_RD_MAX 0x80 1854#define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 1855 1856#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 1857 indicates eror */ 1858 1859#define MAX_DMAE_C_PER_PORT 8 1860#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 1861 BP_VN(bp)) 1862#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 1863 E1HVN_MAX) 1864 1865/* PCIE link and speed */ 1866#define PCICFG_LINK_WIDTH 0x1f00000 1867#define PCICFG_LINK_WIDTH_SHIFT 20 1868#define PCICFG_LINK_SPEED 0xf0000 1869#define PCICFG_LINK_SPEED_SHIFT 16 1870 1871 1872#define BNX2X_NUM_TESTS 7 1873 1874#define BNX2X_PHY_LOOPBACK 0 1875#define BNX2X_MAC_LOOPBACK 1 1876#define BNX2X_PHY_LOOPBACK_FAILED 1 1877#define BNX2X_MAC_LOOPBACK_FAILED 2 1878#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 1879 BNX2X_PHY_LOOPBACK_FAILED) 1880 1881 1882#define STROM_ASSERT_ARRAY_SIZE 50 1883 1884 1885/* must be used on a CID before placing it on a HW ring */ 1886#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 1887 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 1888 (x)) 1889 1890#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1891#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1892 1893 1894#define BNX2X_BTR 4 1895#define MAX_SPQ_PENDING 8 1896 1897/* CMNG constants, as derived from system spec calculations */ 1898/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 1899#define DEF_MIN_RATE 100 1900/* resolution of the rate shaping timer - 400 usec */ 1901#define RS_PERIODIC_TIMEOUT_USEC 400 1902/* number of bytes in single QM arbitration cycle - 1903 * coefficient for calculating the fairness timer */ 1904#define QM_ARB_BYTES 160000 1905/* resolution of Min algorithm 1:100 */ 1906#define MIN_RES 100 1907/* how many bytes above threshold for the minimal credit of Min algorithm*/ 1908#define MIN_ABOVE_THRESH 32768 1909/* Fairness algorithm integration time coefficient - 1910 * for calculating the actual Tfair */ 1911#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 1912/* Memory of fairness algorithm . 2 cycles */ 1913#define FAIR_MEM 2 1914 1915 1916#define ATTN_NIG_FOR_FUNC (1L << 8) 1917#define ATTN_SW_TIMER_4_FUNC (1L << 9) 1918#define GPIO_2_FUNC (1L << 10) 1919#define GPIO_3_FUNC (1L << 11) 1920#define GPIO_4_FUNC (1L << 12) 1921#define ATTN_GENERAL_ATTN_1 (1L << 13) 1922#define ATTN_GENERAL_ATTN_2 (1L << 14) 1923#define ATTN_GENERAL_ATTN_3 (1L << 15) 1924#define ATTN_GENERAL_ATTN_4 (1L << 13) 1925#define ATTN_GENERAL_ATTN_5 (1L << 14) 1926#define ATTN_GENERAL_ATTN_6 (1L << 15) 1927 1928#define ATTN_HARD_WIRED_MASK 0xff00 1929#define ATTENTION_ID 4 1930 1931 1932/* stuff added to make the code fit 80Col */ 1933 1934#define BNX2X_PMF_LINK_ASSERT \ 1935 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 1936 1937#define BNX2X_MC_ASSERT_BITS \ 1938 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1939 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1940 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1941 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 1942 1943#define BNX2X_MCP_ASSERT \ 1944 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 1945 1946#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 1947#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 1948 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 1949 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 1950 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 1951 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 1952 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 1953 1954#define HW_INTERRUT_ASSERT_SET_0 \ 1955 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 1956 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 1957 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 1958 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 1959#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 1960 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 1961 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 1962 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 1963 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 1964 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 1965 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 1966#define HW_INTERRUT_ASSERT_SET_1 \ 1967 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 1968 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 1969 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 1970 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 1971 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 1972 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 1973 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 1974 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 1975 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 1976 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 1977 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 1978#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 1979 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 1980 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 1981 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 1982 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 1983 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 1984 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 1985 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 1986 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 1987 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 1988 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 1989 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 1990 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 1991 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 1992 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 1993 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 1994#define HW_INTERRUT_ASSERT_SET_2 \ 1995 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 1996 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 1997 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 1998 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 1999 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2000#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2001 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2002 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2003 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2004 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2005 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2006 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2007 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2008 2009#define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2010 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2011 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2012 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2013 2014#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2015 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2016 2017#define MULTI_MASK 0x7f 2018 2019 2020#define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2021#define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2022#define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2023#define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2024 2025#define DEF_USB_IGU_INDEX_OFF \ 2026 offsetof(struct cstorm_def_status_block_u, igu_index) 2027#define DEF_CSB_IGU_INDEX_OFF \ 2028 offsetof(struct cstorm_def_status_block_c, igu_index) 2029#define DEF_XSB_IGU_INDEX_OFF \ 2030 offsetof(struct xstorm_def_status_block, igu_index) 2031#define DEF_TSB_IGU_INDEX_OFF \ 2032 offsetof(struct tstorm_def_status_block, igu_index) 2033 2034#define DEF_USB_SEGMENT_OFF \ 2035 offsetof(struct cstorm_def_status_block_u, segment) 2036#define DEF_CSB_SEGMENT_OFF \ 2037 offsetof(struct cstorm_def_status_block_c, segment) 2038#define DEF_XSB_SEGMENT_OFF \ 2039 offsetof(struct xstorm_def_status_block, segment) 2040#define DEF_TSB_SEGMENT_OFF \ 2041 offsetof(struct tstorm_def_status_block, segment) 2042 2043#define BNX2X_SP_DSB_INDEX \ 2044 (&bp->def_status_blk->sp_sb.\ 2045 index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2046 2047#define SET_FLAG(value, mask, flag) \ 2048 do {\ 2049 (value) &= ~(mask);\ 2050 (value) |= ((flag) << (mask##_SHIFT));\ 2051 } while (0) 2052 2053#define GET_FLAG(value, mask) \ 2054 (((value) & (mask)) >> (mask##_SHIFT)) 2055 2056#define GET_FIELD(value, fname) \ 2057 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 2058 2059#define CAM_IS_INVALID(x) \ 2060 (GET_FLAG(x.flags, \ 2061 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2062 (T_ETH_MAC_COMMAND_INVALIDATE)) 2063 2064/* Number of u32 elements in MC hash array */ 2065#define MC_HASH_SIZE 8 2066#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2067 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2068 2069 2070#ifndef PXP2_REG_PXP2_INT_STS 2071#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2072#endif 2073 2074#ifndef ETH_MAX_RX_CLIENTS_E2 2075#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2076#endif 2077 2078#define BNX2X_VPD_LEN 128 2079#define VENDOR_ID_LEN 4 2080 2081/* Congestion management fairness mode */ 2082#define CMNG_FNS_NONE 0 2083#define CMNG_FNS_MINMAX 1 2084 2085#define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2086#define HC_SEG_ACCESS_ATTN 4 2087#define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2088 2089static const u32 dmae_reg_go_c[] = { 2090 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2091 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2092 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2093 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2094}; 2095 2096void bnx2x_set_ethtool_ops(struct net_device *netdev); 2097void bnx2x_notify_link_changed(struct bnx2x *bp); 2098 2099 2100#define BNX2X_MF_PROTOCOL(bp) \ 2101 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2102 2103#ifdef BCM_CNIC 2104#define BNX2X_IS_MF_PROTOCOL_ISCSI(bp) \ 2105 (BNX2X_MF_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2106 2107#define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_PROTOCOL_ISCSI(bp)) 2108#endif 2109 2110#endif /* bnx2x.h */ 2111