bnx2x_ethtool.c revision adfc5217e9db68d3f0cec8dd847c1a6d3ab549ee
1/* bnx2x_ethtool.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2011 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17#include <linux/ethtool.h> 18#include <linux/netdevice.h> 19#include <linux/types.h> 20#include <linux/sched.h> 21#include <linux/crc32.h> 22 23 24#include "bnx2x.h" 25#include "bnx2x_cmn.h" 26#include "bnx2x_dump.h" 27#include "bnx2x_init.h" 28#include "bnx2x_sp.h" 29 30/* Note: in the format strings below %s is replaced by the queue-name which is 31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string 32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 33 */ 34#define MAX_QUEUE_NAME_LEN 4 35static const struct { 36 long offset; 37 int size; 38 char string[ETH_GSTRING_LEN]; 39} bnx2x_q_stats_arr[] = { 40/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 42 8, "[%s]: rx_ucast_packets" }, 43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 44 8, "[%s]: rx_mcast_packets" }, 45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 46 8, "[%s]: rx_bcast_packets" }, 47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 48 { Q_STATS_OFFSET32(rx_err_discard_pkt), 49 4, "[%s]: rx_phy_ip_err_discards"}, 50 { Q_STATS_OFFSET32(rx_skb_alloc_failed), 51 4, "[%s]: rx_skb_alloc_discard" }, 52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 53 54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 55/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 56 8, "[%s]: tx_ucast_packets" }, 57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 58 8, "[%s]: tx_mcast_packets" }, 59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 60 8, "[%s]: tx_bcast_packets" }, 61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 62 8, "[%s]: tpa_aggregations" }, 63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 64 8, "[%s]: tpa_aggregated_frames"}, 65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"} 66}; 67 68#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 69 70static const struct { 71 long offset; 72 int size; 73 u32 flags; 74#define STATS_FLAGS_PORT 1 75#define STATS_FLAGS_FUNC 2 76#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 77 char string[ETH_GSTRING_LEN]; 78} bnx2x_stats_arr[] = { 79/* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 80 8, STATS_FLAGS_BOTH, "rx_bytes" }, 81 { STATS_OFFSET32(error_bytes_received_hi), 82 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 83 { STATS_OFFSET32(total_unicast_packets_received_hi), 84 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 85 { STATS_OFFSET32(total_multicast_packets_received_hi), 86 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 87 { STATS_OFFSET32(total_broadcast_packets_received_hi), 88 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 89 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 90 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 91 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 92 8, STATS_FLAGS_PORT, "rx_align_errors" }, 93 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 94 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 95 { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 96 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 97/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 98 8, STATS_FLAGS_PORT, "rx_fragments" }, 99 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 100 8, STATS_FLAGS_PORT, "rx_jabbers" }, 101 { STATS_OFFSET32(no_buff_discard_hi), 102 8, STATS_FLAGS_BOTH, "rx_discards" }, 103 { STATS_OFFSET32(mac_filter_discard), 104 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 105 { STATS_OFFSET32(mf_tag_discard), 106 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 107 { STATS_OFFSET32(brb_drop_hi), 108 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 109 { STATS_OFFSET32(brb_truncate_hi), 110 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 111 { STATS_OFFSET32(pause_frames_received_hi), 112 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 113 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 114 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 115 { STATS_OFFSET32(nig_timer_max), 116 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 117/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 118 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, 119 { STATS_OFFSET32(rx_skb_alloc_failed), 120 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, 121 { STATS_OFFSET32(hw_csum_err), 122 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, 123 124 { STATS_OFFSET32(total_bytes_transmitted_hi), 125 8, STATS_FLAGS_BOTH, "tx_bytes" }, 126 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 127 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 128 { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 129 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 130 { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 131 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 132 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 133 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 134 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 135 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 136 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 137 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 138/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 139 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 140 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 141 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 142 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 143 8, STATS_FLAGS_PORT, "tx_deferred" }, 144 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 145 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 146 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 147 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 148 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 149 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 150 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 151 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 152 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 153 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 154 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 155 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 156 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 157 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 158/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 159 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 160 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 161 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 162 { STATS_OFFSET32(etherstatspktsover1522octets_hi), 163 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 164 { STATS_OFFSET32(pause_frames_sent_hi), 165 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 166 { STATS_OFFSET32(total_tpa_aggregations_hi), 167 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 168 { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 169 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 170 { STATS_OFFSET32(total_tpa_bytes_hi), 171 8, STATS_FLAGS_FUNC, "tpa_bytes"} 172}; 173 174#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 175static int bnx2x_get_port_type(struct bnx2x *bp) 176{ 177 int port_type; 178 u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 179 switch (bp->link_params.phy[phy_idx].media_type) { 180 case ETH_PHY_SFP_FIBER: 181 case ETH_PHY_XFP_FIBER: 182 case ETH_PHY_KR: 183 case ETH_PHY_CX4: 184 port_type = PORT_FIBRE; 185 break; 186 case ETH_PHY_DA_TWINAX: 187 port_type = PORT_DA; 188 break; 189 case ETH_PHY_BASE_T: 190 port_type = PORT_TP; 191 break; 192 case ETH_PHY_NOT_PRESENT: 193 port_type = PORT_NONE; 194 break; 195 case ETH_PHY_UNSPECIFIED: 196 default: 197 port_type = PORT_OTHER; 198 break; 199 } 200 return port_type; 201} 202 203static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 204{ 205 struct bnx2x *bp = netdev_priv(dev); 206 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 207 208 /* Dual Media boards present all available port types */ 209 cmd->supported = bp->port.supported[cfg_idx] | 210 (bp->port.supported[cfg_idx ^ 1] & 211 (SUPPORTED_TP | SUPPORTED_FIBRE)); 212 cmd->advertising = bp->port.advertising[cfg_idx]; 213 214 if ((bp->state == BNX2X_STATE_OPEN) && 215 !(bp->flags & MF_FUNC_DIS) && 216 (bp->link_vars.link_up)) { 217 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); 218 cmd->duplex = bp->link_vars.duplex; 219 } else { 220 ethtool_cmd_speed_set( 221 cmd, bp->link_params.req_line_speed[cfg_idx]); 222 cmd->duplex = bp->link_params.req_duplex[cfg_idx]; 223 } 224 225 if (IS_MF(bp)) 226 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); 227 228 cmd->port = bnx2x_get_port_type(bp); 229 230 cmd->phy_address = bp->mdio.prtad; 231 cmd->transceiver = XCVR_INTERNAL; 232 233 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 234 cmd->autoneg = AUTONEG_ENABLE; 235 else 236 cmd->autoneg = AUTONEG_DISABLE; 237 238 cmd->maxtxpkt = 0; 239 cmd->maxrxpkt = 0; 240 241 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n" 242 DP_LEVEL " supported 0x%x advertising 0x%x speed %u\n" 243 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n" 244 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n", 245 cmd->cmd, cmd->supported, cmd->advertising, 246 ethtool_cmd_speed(cmd), 247 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 248 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 249 250 return 0; 251} 252 253static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 254{ 255 struct bnx2x *bp = netdev_priv(dev); 256 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 257 u32 speed; 258 259 if (IS_MF_SD(bp)) 260 return 0; 261 262 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n" 263 " supported 0x%x advertising 0x%x speed %u\n" 264 " duplex %d port %d phy_address %d transceiver %d\n" 265 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 266 cmd->cmd, cmd->supported, cmd->advertising, 267 ethtool_cmd_speed(cmd), 268 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 269 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 270 271 speed = ethtool_cmd_speed(cmd); 272 273 if (IS_MF_SI(bp)) { 274 u32 part; 275 u32 line_speed = bp->link_vars.line_speed; 276 277 /* use 10G if no link detected */ 278 if (!line_speed) 279 line_speed = 10000; 280 281 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 282 BNX2X_DEV_INFO("To set speed BC %X or higher " 283 "is required, please upgrade BC\n", 284 REQ_BC_VER_4_SET_MF_BW); 285 return -EINVAL; 286 } 287 288 part = (speed * 100) / line_speed; 289 290 if (line_speed < speed || !part) { 291 BNX2X_DEV_INFO("Speed setting should be in a range " 292 "from 1%% to 100%% " 293 "of actual line speed\n"); 294 return -EINVAL; 295 } 296 297 if (bp->state != BNX2X_STATE_OPEN) 298 /* store value for following "load" */ 299 bp->pending_max = part; 300 else 301 bnx2x_update_max_mf_config(bp, part); 302 303 return 0; 304 } 305 306 cfg_idx = bnx2x_get_link_cfg_idx(bp); 307 old_multi_phy_config = bp->link_params.multi_phy_config; 308 switch (cmd->port) { 309 case PORT_TP: 310 if (bp->port.supported[cfg_idx] & SUPPORTED_TP) 311 break; /* no port change */ 312 313 if (!(bp->port.supported[0] & SUPPORTED_TP || 314 bp->port.supported[1] & SUPPORTED_TP)) { 315 DP(NETIF_MSG_LINK, "Unsupported port type\n"); 316 return -EINVAL; 317 } 318 bp->link_params.multi_phy_config &= 319 ~PORT_HW_CFG_PHY_SELECTION_MASK; 320 if (bp->link_params.multi_phy_config & 321 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 322 bp->link_params.multi_phy_config |= 323 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 324 else 325 bp->link_params.multi_phy_config |= 326 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 327 break; 328 case PORT_FIBRE: 329 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE) 330 break; /* no port change */ 331 332 if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 333 bp->port.supported[1] & SUPPORTED_FIBRE)) { 334 DP(NETIF_MSG_LINK, "Unsupported port type\n"); 335 return -EINVAL; 336 } 337 bp->link_params.multi_phy_config &= 338 ~PORT_HW_CFG_PHY_SELECTION_MASK; 339 if (bp->link_params.multi_phy_config & 340 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 341 bp->link_params.multi_phy_config |= 342 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 343 else 344 bp->link_params.multi_phy_config |= 345 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 346 break; 347 default: 348 DP(NETIF_MSG_LINK, "Unsupported port type\n"); 349 return -EINVAL; 350 } 351 /* Save new config in case command complete successuly */ 352 new_multi_phy_config = bp->link_params.multi_phy_config; 353 /* Get the new cfg_idx */ 354 cfg_idx = bnx2x_get_link_cfg_idx(bp); 355 /* Restore old config in case command failed */ 356 bp->link_params.multi_phy_config = old_multi_phy_config; 357 DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx); 358 359 if (cmd->autoneg == AUTONEG_ENABLE) { 360 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 361 DP(NETIF_MSG_LINK, "Autoneg not supported\n"); 362 return -EINVAL; 363 } 364 365 /* advertise the requested speed and duplex if supported */ 366 cmd->advertising &= bp->port.supported[cfg_idx]; 367 368 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 369 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL; 370 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg | 371 cmd->advertising); 372 373 } else { /* forced speed */ 374 /* advertise the requested speed and duplex if supported */ 375 switch (speed) { 376 case SPEED_10: 377 if (cmd->duplex == DUPLEX_FULL) { 378 if (!(bp->port.supported[cfg_idx] & 379 SUPPORTED_10baseT_Full)) { 380 DP(NETIF_MSG_LINK, 381 "10M full not supported\n"); 382 return -EINVAL; 383 } 384 385 advertising = (ADVERTISED_10baseT_Full | 386 ADVERTISED_TP); 387 } else { 388 if (!(bp->port.supported[cfg_idx] & 389 SUPPORTED_10baseT_Half)) { 390 DP(NETIF_MSG_LINK, 391 "10M half not supported\n"); 392 return -EINVAL; 393 } 394 395 advertising = (ADVERTISED_10baseT_Half | 396 ADVERTISED_TP); 397 } 398 break; 399 400 case SPEED_100: 401 if (cmd->duplex == DUPLEX_FULL) { 402 if (!(bp->port.supported[cfg_idx] & 403 SUPPORTED_100baseT_Full)) { 404 DP(NETIF_MSG_LINK, 405 "100M full not supported\n"); 406 return -EINVAL; 407 } 408 409 advertising = (ADVERTISED_100baseT_Full | 410 ADVERTISED_TP); 411 } else { 412 if (!(bp->port.supported[cfg_idx] & 413 SUPPORTED_100baseT_Half)) { 414 DP(NETIF_MSG_LINK, 415 "100M half not supported\n"); 416 return -EINVAL; 417 } 418 419 advertising = (ADVERTISED_100baseT_Half | 420 ADVERTISED_TP); 421 } 422 break; 423 424 case SPEED_1000: 425 if (cmd->duplex != DUPLEX_FULL) { 426 DP(NETIF_MSG_LINK, "1G half not supported\n"); 427 return -EINVAL; 428 } 429 430 if (!(bp->port.supported[cfg_idx] & 431 SUPPORTED_1000baseT_Full)) { 432 DP(NETIF_MSG_LINK, "1G full not supported\n"); 433 return -EINVAL; 434 } 435 436 advertising = (ADVERTISED_1000baseT_Full | 437 ADVERTISED_TP); 438 break; 439 440 case SPEED_2500: 441 if (cmd->duplex != DUPLEX_FULL) { 442 DP(NETIF_MSG_LINK, 443 "2.5G half not supported\n"); 444 return -EINVAL; 445 } 446 447 if (!(bp->port.supported[cfg_idx] 448 & SUPPORTED_2500baseX_Full)) { 449 DP(NETIF_MSG_LINK, 450 "2.5G full not supported\n"); 451 return -EINVAL; 452 } 453 454 advertising = (ADVERTISED_2500baseX_Full | 455 ADVERTISED_TP); 456 break; 457 458 case SPEED_10000: 459 if (cmd->duplex != DUPLEX_FULL) { 460 DP(NETIF_MSG_LINK, "10G half not supported\n"); 461 return -EINVAL; 462 } 463 464 if (!(bp->port.supported[cfg_idx] 465 & SUPPORTED_10000baseT_Full)) { 466 DP(NETIF_MSG_LINK, "10G full not supported\n"); 467 return -EINVAL; 468 } 469 470 advertising = (ADVERTISED_10000baseT_Full | 471 ADVERTISED_FIBRE); 472 break; 473 474 default: 475 DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed); 476 return -EINVAL; 477 } 478 479 bp->link_params.req_line_speed[cfg_idx] = speed; 480 bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 481 bp->port.advertising[cfg_idx] = advertising; 482 } 483 484 DP(NETIF_MSG_LINK, "req_line_speed %d\n" 485 DP_LEVEL " req_duplex %d advertising 0x%x\n", 486 bp->link_params.req_line_speed[cfg_idx], 487 bp->link_params.req_duplex[cfg_idx], 488 bp->port.advertising[cfg_idx]); 489 490 /* Set new config */ 491 bp->link_params.multi_phy_config = new_multi_phy_config; 492 if (netif_running(dev)) { 493 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 494 bnx2x_link_set(bp); 495 } 496 497 return 0; 498} 499 500#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE) 501#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE) 502#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE) 503#define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE) 504#define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE) 505 506static inline bool bnx2x_is_reg_online(struct bnx2x *bp, 507 const struct reg_addr *reg_info) 508{ 509 if (CHIP_IS_E1(bp)) 510 return IS_E1_ONLINE(reg_info->info); 511 else if (CHIP_IS_E1H(bp)) 512 return IS_E1H_ONLINE(reg_info->info); 513 else if (CHIP_IS_E2(bp)) 514 return IS_E2_ONLINE(reg_info->info); 515 else if (CHIP_IS_E3A0(bp)) 516 return IS_E3_ONLINE(reg_info->info); 517 else if (CHIP_IS_E3B0(bp)) 518 return IS_E3B0_ONLINE(reg_info->info); 519 else 520 return false; 521} 522 523/******* Paged registers info selectors ********/ 524static inline const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 525{ 526 if (CHIP_IS_E2(bp)) 527 return page_vals_e2; 528 else if (CHIP_IS_E3(bp)) 529 return page_vals_e3; 530 else 531 return NULL; 532} 533 534static inline u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 535{ 536 if (CHIP_IS_E2(bp)) 537 return PAGE_MODE_VALUES_E2; 538 else if (CHIP_IS_E3(bp)) 539 return PAGE_MODE_VALUES_E3; 540 else 541 return 0; 542} 543 544static inline const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 545{ 546 if (CHIP_IS_E2(bp)) 547 return page_write_regs_e2; 548 else if (CHIP_IS_E3(bp)) 549 return page_write_regs_e3; 550 else 551 return NULL; 552} 553 554static inline u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 555{ 556 if (CHIP_IS_E2(bp)) 557 return PAGE_WRITE_REGS_E2; 558 else if (CHIP_IS_E3(bp)) 559 return PAGE_WRITE_REGS_E3; 560 else 561 return 0; 562} 563 564static inline const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 565{ 566 if (CHIP_IS_E2(bp)) 567 return page_read_regs_e2; 568 else if (CHIP_IS_E3(bp)) 569 return page_read_regs_e3; 570 else 571 return NULL; 572} 573 574static inline u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 575{ 576 if (CHIP_IS_E2(bp)) 577 return PAGE_READ_REGS_E2; 578 else if (CHIP_IS_E3(bp)) 579 return PAGE_READ_REGS_E3; 580 else 581 return 0; 582} 583 584static inline int __bnx2x_get_regs_len(struct bnx2x *bp) 585{ 586 int num_pages = __bnx2x_get_page_reg_num(bp); 587 int page_write_num = __bnx2x_get_page_write_num(bp); 588 const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp); 589 int page_read_num = __bnx2x_get_page_read_num(bp); 590 int regdump_len = 0; 591 int i, j, k; 592 593 for (i = 0; i < REGS_COUNT; i++) 594 if (bnx2x_is_reg_online(bp, ®_addrs[i])) 595 regdump_len += reg_addrs[i].size; 596 597 for (i = 0; i < num_pages; i++) 598 for (j = 0; j < page_write_num; j++) 599 for (k = 0; k < page_read_num; k++) 600 if (bnx2x_is_reg_online(bp, &page_read_addr[k])) 601 regdump_len += page_read_addr[k].size; 602 603 return regdump_len; 604} 605 606static int bnx2x_get_regs_len(struct net_device *dev) 607{ 608 struct bnx2x *bp = netdev_priv(dev); 609 int regdump_len = 0; 610 611 regdump_len = __bnx2x_get_regs_len(bp); 612 regdump_len *= 4; 613 regdump_len += sizeof(struct dump_hdr); 614 615 return regdump_len; 616} 617 618/** 619 * bnx2x_read_pages_regs - read "paged" registers 620 * 621 * @bp device handle 622 * @p output buffer 623 * 624 * Reads "paged" memories: memories that may only be read by first writing to a 625 * specific address ("write address") and then reading from a specific address 626 * ("read address"). There may be more than one write address per "page" and 627 * more than one read address per write address. 628 */ 629static inline void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p) 630{ 631 u32 i, j, k, n; 632 /* addresses of the paged registers */ 633 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 634 /* number of paged registers */ 635 int num_pages = __bnx2x_get_page_reg_num(bp); 636 /* write addresses */ 637 const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 638 /* number of write addresses */ 639 int write_num = __bnx2x_get_page_write_num(bp); 640 /* read addresses info */ 641 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 642 /* number of read addresses */ 643 int read_num = __bnx2x_get_page_read_num(bp); 644 645 for (i = 0; i < num_pages; i++) { 646 for (j = 0; j < write_num; j++) { 647 REG_WR(bp, write_addr[j], page_addr[i]); 648 for (k = 0; k < read_num; k++) 649 if (bnx2x_is_reg_online(bp, &read_addr[k])) 650 for (n = 0; n < 651 read_addr[k].size; n++) 652 *p++ = REG_RD(bp, 653 read_addr[k].addr + n*4); 654 } 655 } 656} 657 658static inline void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 659{ 660 u32 i, j; 661 662 /* Read the regular registers */ 663 for (i = 0; i < REGS_COUNT; i++) 664 if (bnx2x_is_reg_online(bp, ®_addrs[i])) 665 for (j = 0; j < reg_addrs[i].size; j++) 666 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 667 668 /* Read "paged" registes */ 669 bnx2x_read_pages_regs(bp, p); 670} 671 672static void bnx2x_get_regs(struct net_device *dev, 673 struct ethtool_regs *regs, void *_p) 674{ 675 u32 *p = _p; 676 struct bnx2x *bp = netdev_priv(dev); 677 struct dump_hdr dump_hdr = {0}; 678 679 regs->version = 0; 680 memset(p, 0, regs->len); 681 682 if (!netif_running(bp->dev)) 683 return; 684 685 /* Disable parity attentions as long as following dump may 686 * cause false alarms by reading never written registers. We 687 * will re-enable parity attentions right after the dump. 688 */ 689 bnx2x_disable_blocks_parity(bp); 690 691 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1; 692 dump_hdr.dump_sign = dump_sign_all; 693 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR); 694 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR); 695 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR); 696 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR); 697 698 if (CHIP_IS_E1(bp)) 699 dump_hdr.info = RI_E1_ONLINE; 700 else if (CHIP_IS_E1H(bp)) 701 dump_hdr.info = RI_E1H_ONLINE; 702 else if (!CHIP_IS_E1x(bp)) 703 dump_hdr.info = RI_E2_ONLINE | 704 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP); 705 706 memcpy(p, &dump_hdr, sizeof(struct dump_hdr)); 707 p += dump_hdr.hdr_size + 1; 708 709 /* Actually read the registers */ 710 __bnx2x_get_regs(bp, p); 711 712 /* Re-enable parity attentions */ 713 bnx2x_clear_blocks_parity(bp); 714 bnx2x_enable_blocks_parity(bp); 715} 716 717static void bnx2x_get_drvinfo(struct net_device *dev, 718 struct ethtool_drvinfo *info) 719{ 720 struct bnx2x *bp = netdev_priv(dev); 721 u8 phy_fw_ver[PHY_FW_VER_LEN]; 722 723 strcpy(info->driver, DRV_MODULE_NAME); 724 strcpy(info->version, DRV_MODULE_VERSION); 725 726 phy_fw_ver[0] = '\0'; 727 if (bp->port.pmf) { 728 bnx2x_acquire_phy_lock(bp); 729 bnx2x_get_ext_phy_fw_version(&bp->link_params, 730 (bp->state != BNX2X_STATE_CLOSED), 731 phy_fw_ver, PHY_FW_VER_LEN); 732 bnx2x_release_phy_lock(bp); 733 } 734 735 strncpy(info->fw_version, bp->fw_ver, 32); 736 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver), 737 "bc %d.%d.%d%s%s", 738 (bp->common.bc_ver & 0xff0000) >> 16, 739 (bp->common.bc_ver & 0xff00) >> 8, 740 (bp->common.bc_ver & 0xff), 741 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver); 742 strcpy(info->bus_info, pci_name(bp->pdev)); 743 info->n_stats = BNX2X_NUM_STATS; 744 info->testinfo_len = BNX2X_NUM_TESTS; 745 info->eedump_len = bp->common.flash_size; 746 info->regdump_len = bnx2x_get_regs_len(dev); 747} 748 749static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 750{ 751 struct bnx2x *bp = netdev_priv(dev); 752 753 if (bp->flags & NO_WOL_FLAG) { 754 wol->supported = 0; 755 wol->wolopts = 0; 756 } else { 757 wol->supported = WAKE_MAGIC; 758 if (bp->wol) 759 wol->wolopts = WAKE_MAGIC; 760 else 761 wol->wolopts = 0; 762 } 763 memset(&wol->sopass, 0, sizeof(wol->sopass)); 764} 765 766static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 767{ 768 struct bnx2x *bp = netdev_priv(dev); 769 770 if (wol->wolopts & ~WAKE_MAGIC) 771 return -EINVAL; 772 773 if (wol->wolopts & WAKE_MAGIC) { 774 if (bp->flags & NO_WOL_FLAG) 775 return -EINVAL; 776 777 bp->wol = 1; 778 } else 779 bp->wol = 0; 780 781 return 0; 782} 783 784static u32 bnx2x_get_msglevel(struct net_device *dev) 785{ 786 struct bnx2x *bp = netdev_priv(dev); 787 788 return bp->msg_enable; 789} 790 791static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 792{ 793 struct bnx2x *bp = netdev_priv(dev); 794 795 if (capable(CAP_NET_ADMIN)) { 796 /* dump MCP trace */ 797 if (level & BNX2X_MSG_MCP) 798 bnx2x_fw_dump_lvl(bp, KERN_INFO); 799 bp->msg_enable = level; 800 } 801} 802 803static int bnx2x_nway_reset(struct net_device *dev) 804{ 805 struct bnx2x *bp = netdev_priv(dev); 806 807 if (!bp->port.pmf) 808 return 0; 809 810 if (netif_running(dev)) { 811 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 812 bnx2x_link_set(bp); 813 } 814 815 return 0; 816} 817 818static u32 bnx2x_get_link(struct net_device *dev) 819{ 820 struct bnx2x *bp = netdev_priv(dev); 821 822 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 823 return 0; 824 825 return bp->link_vars.link_up; 826} 827 828static int bnx2x_get_eeprom_len(struct net_device *dev) 829{ 830 struct bnx2x *bp = netdev_priv(dev); 831 832 return bp->common.flash_size; 833} 834 835static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 836{ 837 int port = BP_PORT(bp); 838 int count, i; 839 u32 val = 0; 840 841 /* adjust timeout for emulation/FPGA */ 842 count = BNX2X_NVRAM_TIMEOUT_COUNT; 843 if (CHIP_REV_IS_SLOW(bp)) 844 count *= 100; 845 846 /* request access to nvram interface */ 847 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 848 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 849 850 for (i = 0; i < count*10; i++) { 851 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 852 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 853 break; 854 855 udelay(5); 856 } 857 858 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 859 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n"); 860 return -EBUSY; 861 } 862 863 return 0; 864} 865 866static int bnx2x_release_nvram_lock(struct bnx2x *bp) 867{ 868 int port = BP_PORT(bp); 869 int count, i; 870 u32 val = 0; 871 872 /* adjust timeout for emulation/FPGA */ 873 count = BNX2X_NVRAM_TIMEOUT_COUNT; 874 if (CHIP_REV_IS_SLOW(bp)) 875 count *= 100; 876 877 /* relinquish nvram interface */ 878 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 879 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 880 881 for (i = 0; i < count*10; i++) { 882 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 883 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 884 break; 885 886 udelay(5); 887 } 888 889 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 890 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n"); 891 return -EBUSY; 892 } 893 894 return 0; 895} 896 897static void bnx2x_enable_nvram_access(struct bnx2x *bp) 898{ 899 u32 val; 900 901 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 902 903 /* enable both bits, even on read */ 904 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 905 (val | MCPR_NVM_ACCESS_ENABLE_EN | 906 MCPR_NVM_ACCESS_ENABLE_WR_EN)); 907} 908 909static void bnx2x_disable_nvram_access(struct bnx2x *bp) 910{ 911 u32 val; 912 913 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 914 915 /* disable both bits, even after read */ 916 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 917 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 918 MCPR_NVM_ACCESS_ENABLE_WR_EN))); 919} 920 921static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 922 u32 cmd_flags) 923{ 924 int count, i, rc; 925 u32 val; 926 927 /* build the command word */ 928 cmd_flags |= MCPR_NVM_COMMAND_DOIT; 929 930 /* need to clear DONE bit separately */ 931 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 932 933 /* address of the NVRAM to read from */ 934 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 935 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 936 937 /* issue a read command */ 938 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 939 940 /* adjust timeout for emulation/FPGA */ 941 count = BNX2X_NVRAM_TIMEOUT_COUNT; 942 if (CHIP_REV_IS_SLOW(bp)) 943 count *= 100; 944 945 /* wait for completion */ 946 *ret_val = 0; 947 rc = -EBUSY; 948 for (i = 0; i < count; i++) { 949 udelay(5); 950 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 951 952 if (val & MCPR_NVM_COMMAND_DONE) { 953 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 954 /* we read nvram data in cpu order 955 * but ethtool sees it as an array of bytes 956 * converting to big-endian will do the work */ 957 *ret_val = cpu_to_be32(val); 958 rc = 0; 959 break; 960 } 961 } 962 963 return rc; 964} 965 966static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 967 int buf_size) 968{ 969 int rc; 970 u32 cmd_flags; 971 __be32 val; 972 973 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 974 DP(BNX2X_MSG_NVM, 975 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 976 offset, buf_size); 977 return -EINVAL; 978 } 979 980 if (offset + buf_size > bp->common.flash_size) { 981 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +" 982 " buf_size (0x%x) > flash_size (0x%x)\n", 983 offset, buf_size, bp->common.flash_size); 984 return -EINVAL; 985 } 986 987 /* request access to nvram interface */ 988 rc = bnx2x_acquire_nvram_lock(bp); 989 if (rc) 990 return rc; 991 992 /* enable access to nvram interface */ 993 bnx2x_enable_nvram_access(bp); 994 995 /* read the first word(s) */ 996 cmd_flags = MCPR_NVM_COMMAND_FIRST; 997 while ((buf_size > sizeof(u32)) && (rc == 0)) { 998 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 999 memcpy(ret_buf, &val, 4); 1000 1001 /* advance to the next dword */ 1002 offset += sizeof(u32); 1003 ret_buf += sizeof(u32); 1004 buf_size -= sizeof(u32); 1005 cmd_flags = 0; 1006 } 1007 1008 if (rc == 0) { 1009 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1010 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1011 memcpy(ret_buf, &val, 4); 1012 } 1013 1014 /* disable access to nvram interface */ 1015 bnx2x_disable_nvram_access(bp); 1016 bnx2x_release_nvram_lock(bp); 1017 1018 return rc; 1019} 1020 1021static int bnx2x_get_eeprom(struct net_device *dev, 1022 struct ethtool_eeprom *eeprom, u8 *eebuf) 1023{ 1024 struct bnx2x *bp = netdev_priv(dev); 1025 int rc; 1026 1027 if (!netif_running(dev)) 1028 return -EAGAIN; 1029 1030 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1031 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1032 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1033 eeprom->len, eeprom->len); 1034 1035 /* parameters already validated in ethtool_get_eeprom */ 1036 1037 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1038 1039 return rc; 1040} 1041 1042static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1043 u32 cmd_flags) 1044{ 1045 int count, i, rc; 1046 1047 /* build the command word */ 1048 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1049 1050 /* need to clear DONE bit separately */ 1051 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1052 1053 /* write the data */ 1054 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1055 1056 /* address of the NVRAM to write to */ 1057 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1058 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1059 1060 /* issue the write command */ 1061 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1062 1063 /* adjust timeout for emulation/FPGA */ 1064 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1065 if (CHIP_REV_IS_SLOW(bp)) 1066 count *= 100; 1067 1068 /* wait for completion */ 1069 rc = -EBUSY; 1070 for (i = 0; i < count; i++) { 1071 udelay(5); 1072 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1073 if (val & MCPR_NVM_COMMAND_DONE) { 1074 rc = 0; 1075 break; 1076 } 1077 } 1078 1079 return rc; 1080} 1081 1082#define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1083 1084static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1085 int buf_size) 1086{ 1087 int rc; 1088 u32 cmd_flags; 1089 u32 align_offset; 1090 __be32 val; 1091 1092 if (offset + buf_size > bp->common.flash_size) { 1093 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +" 1094 " buf_size (0x%x) > flash_size (0x%x)\n", 1095 offset, buf_size, bp->common.flash_size); 1096 return -EINVAL; 1097 } 1098 1099 /* request access to nvram interface */ 1100 rc = bnx2x_acquire_nvram_lock(bp); 1101 if (rc) 1102 return rc; 1103 1104 /* enable access to nvram interface */ 1105 bnx2x_enable_nvram_access(bp); 1106 1107 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1108 align_offset = (offset & ~0x03); 1109 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags); 1110 1111 if (rc == 0) { 1112 val &= ~(0xff << BYTE_OFFSET(offset)); 1113 val |= (*data_buf << BYTE_OFFSET(offset)); 1114 1115 /* nvram data is returned as an array of bytes 1116 * convert it back to cpu order */ 1117 val = be32_to_cpu(val); 1118 1119 rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1120 cmd_flags); 1121 } 1122 1123 /* disable access to nvram interface */ 1124 bnx2x_disable_nvram_access(bp); 1125 bnx2x_release_nvram_lock(bp); 1126 1127 return rc; 1128} 1129 1130static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1131 int buf_size) 1132{ 1133 int rc; 1134 u32 cmd_flags; 1135 u32 val; 1136 u32 written_so_far; 1137 1138 if (buf_size == 1) /* ethtool */ 1139 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1140 1141 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1142 DP(BNX2X_MSG_NVM, 1143 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1144 offset, buf_size); 1145 return -EINVAL; 1146 } 1147 1148 if (offset + buf_size > bp->common.flash_size) { 1149 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +" 1150 " buf_size (0x%x) > flash_size (0x%x)\n", 1151 offset, buf_size, bp->common.flash_size); 1152 return -EINVAL; 1153 } 1154 1155 /* request access to nvram interface */ 1156 rc = bnx2x_acquire_nvram_lock(bp); 1157 if (rc) 1158 return rc; 1159 1160 /* enable access to nvram interface */ 1161 bnx2x_enable_nvram_access(bp); 1162 1163 written_so_far = 0; 1164 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1165 while ((written_so_far < buf_size) && (rc == 0)) { 1166 if (written_so_far == (buf_size - sizeof(u32))) 1167 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1168 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1169 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1170 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1171 cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1172 1173 memcpy(&val, data_buf, 4); 1174 1175 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1176 1177 /* advance to the next dword */ 1178 offset += sizeof(u32); 1179 data_buf += sizeof(u32); 1180 written_so_far += sizeof(u32); 1181 cmd_flags = 0; 1182 } 1183 1184 /* disable access to nvram interface */ 1185 bnx2x_disable_nvram_access(bp); 1186 bnx2x_release_nvram_lock(bp); 1187 1188 return rc; 1189} 1190 1191static int bnx2x_set_eeprom(struct net_device *dev, 1192 struct ethtool_eeprom *eeprom, u8 *eebuf) 1193{ 1194 struct bnx2x *bp = netdev_priv(dev); 1195 int port = BP_PORT(bp); 1196 int rc = 0; 1197 u32 ext_phy_config; 1198 if (!netif_running(dev)) 1199 return -EAGAIN; 1200 1201 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1202 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1203 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1204 eeprom->len, eeprom->len); 1205 1206 /* parameters already validated in ethtool_set_eeprom */ 1207 1208 /* PHY eeprom can be accessed only by the PMF */ 1209 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 1210 !bp->port.pmf) 1211 return -EINVAL; 1212 1213 ext_phy_config = 1214 SHMEM_RD(bp, 1215 dev_info.port_hw_config[port].external_phy_config); 1216 1217 if (eeprom->magic == 0x50485950) { 1218 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1219 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1220 1221 bnx2x_acquire_phy_lock(bp); 1222 rc |= bnx2x_link_reset(&bp->link_params, 1223 &bp->link_vars, 0); 1224 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1225 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1226 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1227 MISC_REGISTERS_GPIO_HIGH, port); 1228 bnx2x_release_phy_lock(bp); 1229 bnx2x_link_report(bp); 1230 1231 } else if (eeprom->magic == 0x50485952) { 1232 /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1233 if (bp->state == BNX2X_STATE_OPEN) { 1234 bnx2x_acquire_phy_lock(bp); 1235 rc |= bnx2x_link_reset(&bp->link_params, 1236 &bp->link_vars, 1); 1237 1238 rc |= bnx2x_phy_init(&bp->link_params, 1239 &bp->link_vars); 1240 bnx2x_release_phy_lock(bp); 1241 bnx2x_calc_fc_adv(bp); 1242 } 1243 } else if (eeprom->magic == 0x53985943) { 1244 /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1245 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1246 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1247 1248 /* DSP Remove Download Mode */ 1249 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1250 MISC_REGISTERS_GPIO_LOW, port); 1251 1252 bnx2x_acquire_phy_lock(bp); 1253 1254 bnx2x_sfx7101_sp_sw_reset(bp, 1255 &bp->link_params.phy[EXT_PHY1]); 1256 1257 /* wait 0.5 sec to allow it to run */ 1258 msleep(500); 1259 bnx2x_ext_phy_hw_reset(bp, port); 1260 msleep(500); 1261 bnx2x_release_phy_lock(bp); 1262 } 1263 } else 1264 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1265 1266 return rc; 1267} 1268 1269static int bnx2x_get_coalesce(struct net_device *dev, 1270 struct ethtool_coalesce *coal) 1271{ 1272 struct bnx2x *bp = netdev_priv(dev); 1273 1274 memset(coal, 0, sizeof(struct ethtool_coalesce)); 1275 1276 coal->rx_coalesce_usecs = bp->rx_ticks; 1277 coal->tx_coalesce_usecs = bp->tx_ticks; 1278 1279 return 0; 1280} 1281 1282static int bnx2x_set_coalesce(struct net_device *dev, 1283 struct ethtool_coalesce *coal) 1284{ 1285 struct bnx2x *bp = netdev_priv(dev); 1286 1287 bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1288 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1289 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1290 1291 bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1292 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1293 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1294 1295 if (netif_running(dev)) 1296 bnx2x_update_coalesce(bp); 1297 1298 return 0; 1299} 1300 1301static void bnx2x_get_ringparam(struct net_device *dev, 1302 struct ethtool_ringparam *ering) 1303{ 1304 struct bnx2x *bp = netdev_priv(dev); 1305 1306 ering->rx_max_pending = MAX_RX_AVAIL; 1307 ering->rx_mini_max_pending = 0; 1308 ering->rx_jumbo_max_pending = 0; 1309 1310 if (bp->rx_ring_size) 1311 ering->rx_pending = bp->rx_ring_size; 1312 else 1313 if (bp->state == BNX2X_STATE_OPEN && bp->num_queues) 1314 ering->rx_pending = MAX_RX_AVAIL/bp->num_queues; 1315 else 1316 ering->rx_pending = MAX_RX_AVAIL; 1317 1318 ering->rx_mini_pending = 0; 1319 ering->rx_jumbo_pending = 0; 1320 1321 ering->tx_max_pending = MAX_TX_AVAIL; 1322 ering->tx_pending = bp->tx_ring_size; 1323} 1324 1325static int bnx2x_set_ringparam(struct net_device *dev, 1326 struct ethtool_ringparam *ering) 1327{ 1328 struct bnx2x *bp = netdev_priv(dev); 1329 1330 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 1331 printk(KERN_ERR "Handling parity error recovery. Try again later\n"); 1332 return -EAGAIN; 1333 } 1334 1335 if ((ering->rx_pending > MAX_RX_AVAIL) || 1336 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1337 MIN_RX_SIZE_TPA)) || 1338 (ering->tx_pending > MAX_TX_AVAIL) || 1339 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) 1340 return -EINVAL; 1341 1342 bp->rx_ring_size = ering->rx_pending; 1343 bp->tx_ring_size = ering->tx_pending; 1344 1345 return bnx2x_reload_if_running(dev); 1346} 1347 1348static void bnx2x_get_pauseparam(struct net_device *dev, 1349 struct ethtool_pauseparam *epause) 1350{ 1351 struct bnx2x *bp = netdev_priv(dev); 1352 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 1353 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1354 BNX2X_FLOW_CTRL_AUTO); 1355 1356 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) == 1357 BNX2X_FLOW_CTRL_RX); 1358 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) == 1359 BNX2X_FLOW_CTRL_TX); 1360 1361 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n" 1362 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n", 1363 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1364} 1365 1366static int bnx2x_set_pauseparam(struct net_device *dev, 1367 struct ethtool_pauseparam *epause) 1368{ 1369 struct bnx2x *bp = netdev_priv(dev); 1370 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1371 if (IS_MF(bp)) 1372 return 0; 1373 1374 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n" 1375 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n", 1376 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1377 1378 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 1379 1380 if (epause->rx_pause) 1381 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 1382 1383 if (epause->tx_pause) 1384 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 1385 1386 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 1387 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 1388 1389 if (epause->autoneg) { 1390 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 1391 DP(NETIF_MSG_LINK, "autoneg not supported\n"); 1392 return -EINVAL; 1393 } 1394 1395 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 1396 bp->link_params.req_flow_ctrl[cfg_idx] = 1397 BNX2X_FLOW_CTRL_AUTO; 1398 } 1399 } 1400 1401 DP(NETIF_MSG_LINK, 1402 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1403 1404 if (netif_running(dev)) { 1405 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1406 bnx2x_link_set(bp); 1407 } 1408 1409 return 0; 1410} 1411 1412static const struct { 1413 char string[ETH_GSTRING_LEN]; 1414} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = { 1415 { "register_test (offline)" }, 1416 { "memory_test (offline)" }, 1417 { "loopback_test (offline)" }, 1418 { "nvram_test (online)" }, 1419 { "interrupt_test (online)" }, 1420 { "link_test (online)" }, 1421 { "idle check (online)" } 1422}; 1423 1424enum { 1425 BNX2X_CHIP_E1_OFST = 0, 1426 BNX2X_CHIP_E1H_OFST, 1427 BNX2X_CHIP_E2_OFST, 1428 BNX2X_CHIP_E3_OFST, 1429 BNX2X_CHIP_E3B0_OFST, 1430 BNX2X_CHIP_MAX_OFST 1431}; 1432 1433#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 1434#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 1435#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 1436#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 1437#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 1438 1439#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 1440#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 1441 1442static int bnx2x_test_registers(struct bnx2x *bp) 1443{ 1444 int idx, i, rc = -ENODEV; 1445 u32 wr_val = 0, hw; 1446 int port = BP_PORT(bp); 1447 static const struct { 1448 u32 hw; 1449 u32 offset0; 1450 u32 offset1; 1451 u32 mask; 1452 } reg_tbl[] = { 1453/* 0 */ { BNX2X_CHIP_MASK_ALL, 1454 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 1455 { BNX2X_CHIP_MASK_ALL, 1456 DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 1457 { BNX2X_CHIP_MASK_E1X, 1458 HC_REG_AGG_INT_0, 4, 0x000003ff }, 1459 { BNX2X_CHIP_MASK_ALL, 1460 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 1461 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 1462 PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 1463 { BNX2X_CHIP_MASK_E3B0, 1464 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 1465 { BNX2X_CHIP_MASK_ALL, 1466 PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 1467 { BNX2X_CHIP_MASK_ALL, 1468 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 1469 { BNX2X_CHIP_MASK_ALL, 1470 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 1471 { BNX2X_CHIP_MASK_ALL, 1472 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 1473/* 10 */ { BNX2X_CHIP_MASK_ALL, 1474 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 1475 { BNX2X_CHIP_MASK_ALL, 1476 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 1477 { BNX2X_CHIP_MASK_ALL, 1478 QM_REG_CONNNUM_0, 4, 0x000fffff }, 1479 { BNX2X_CHIP_MASK_ALL, 1480 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 1481 { BNX2X_CHIP_MASK_ALL, 1482 SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 1483 { BNX2X_CHIP_MASK_ALL, 1484 SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 1485 { BNX2X_CHIP_MASK_ALL, 1486 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 1487 { BNX2X_CHIP_MASK_ALL, 1488 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 1489 { BNX2X_CHIP_MASK_ALL, 1490 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 1491 { BNX2X_CHIP_MASK_ALL, 1492 NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 1493/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1494 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 1495 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1496 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 1497 { BNX2X_CHIP_MASK_ALL, 1498 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 1499 { BNX2X_CHIP_MASK_ALL, 1500 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 1501 { BNX2X_CHIP_MASK_ALL, 1502 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 1503 { BNX2X_CHIP_MASK_ALL, 1504 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 1505 { BNX2X_CHIP_MASK_ALL, 1506 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 1507 { BNX2X_CHIP_MASK_ALL, 1508 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 1509 { BNX2X_CHIP_MASK_ALL, 1510 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 1511 { BNX2X_CHIP_MASK_ALL, 1512 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 1513/* 30 */ { BNX2X_CHIP_MASK_ALL, 1514 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 1515 { BNX2X_CHIP_MASK_ALL, 1516 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 1517 { BNX2X_CHIP_MASK_ALL, 1518 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 1519 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1520 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 1521 { BNX2X_CHIP_MASK_ALL, 1522 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 1523 { BNX2X_CHIP_MASK_ALL, 1524 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 1525 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1526 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 1527 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1528 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 1529 1530 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 1531 }; 1532 1533 if (!netif_running(bp->dev)) 1534 return rc; 1535 1536 if (CHIP_IS_E1(bp)) 1537 hw = BNX2X_CHIP_MASK_E1; 1538 else if (CHIP_IS_E1H(bp)) 1539 hw = BNX2X_CHIP_MASK_E1H; 1540 else if (CHIP_IS_E2(bp)) 1541 hw = BNX2X_CHIP_MASK_E2; 1542 else if (CHIP_IS_E3B0(bp)) 1543 hw = BNX2X_CHIP_MASK_E3B0; 1544 else /* e3 A0 */ 1545 hw = BNX2X_CHIP_MASK_E3; 1546 1547 /* Repeat the test twice: 1548 First by writing 0x00000000, second by writing 0xffffffff */ 1549 for (idx = 0; idx < 2; idx++) { 1550 1551 switch (idx) { 1552 case 0: 1553 wr_val = 0; 1554 break; 1555 case 1: 1556 wr_val = 0xffffffff; 1557 break; 1558 } 1559 1560 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 1561 u32 offset, mask, save_val, val; 1562 if (!(hw & reg_tbl[i].hw)) 1563 continue; 1564 1565 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 1566 mask = reg_tbl[i].mask; 1567 1568 save_val = REG_RD(bp, offset); 1569 1570 REG_WR(bp, offset, wr_val & mask); 1571 1572 val = REG_RD(bp, offset); 1573 1574 /* Restore the original register's value */ 1575 REG_WR(bp, offset, save_val); 1576 1577 /* verify value is as expected */ 1578 if ((val & mask) != (wr_val & mask)) { 1579 DP(NETIF_MSG_HW, 1580 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 1581 offset, val, wr_val, mask); 1582 goto test_reg_exit; 1583 } 1584 } 1585 } 1586 1587 rc = 0; 1588 1589test_reg_exit: 1590 return rc; 1591} 1592 1593static int bnx2x_test_memory(struct bnx2x *bp) 1594{ 1595 int i, j, rc = -ENODEV; 1596 u32 val, index; 1597 static const struct { 1598 u32 offset; 1599 int size; 1600 } mem_tbl[] = { 1601 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 1602 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 1603 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 1604 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 1605 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 1606 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 1607 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 1608 1609 { 0xffffffff, 0 } 1610 }; 1611 1612 static const struct { 1613 char *name; 1614 u32 offset; 1615 u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 1616 } prty_tbl[] = { 1617 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 1618 {0x3ffc0, 0, 0, 0} }, 1619 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 1620 {0x2, 0x2, 0, 0} }, 1621 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 1622 {0, 0, 0, 0} }, 1623 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 1624 {0x3ffc0, 0, 0, 0} }, 1625 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 1626 {0x3ffc0, 0, 0, 0} }, 1627 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 1628 {0x3ffc1, 0, 0, 0} }, 1629 1630 { NULL, 0xffffffff, {0, 0, 0, 0} } 1631 }; 1632 1633 if (!netif_running(bp->dev)) 1634 return rc; 1635 1636 if (CHIP_IS_E1(bp)) 1637 index = BNX2X_CHIP_E1_OFST; 1638 else if (CHIP_IS_E1H(bp)) 1639 index = BNX2X_CHIP_E1H_OFST; 1640 else if (CHIP_IS_E2(bp)) 1641 index = BNX2X_CHIP_E2_OFST; 1642 else /* e3 */ 1643 index = BNX2X_CHIP_E3_OFST; 1644 1645 /* pre-Check the parity status */ 1646 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 1647 val = REG_RD(bp, prty_tbl[i].offset); 1648 if (val & ~(prty_tbl[i].hw_mask[index])) { 1649 DP(NETIF_MSG_HW, 1650 "%s is 0x%x\n", prty_tbl[i].name, val); 1651 goto test_mem_exit; 1652 } 1653 } 1654 1655 /* Go through all the memories */ 1656 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 1657 for (j = 0; j < mem_tbl[i].size; j++) 1658 REG_RD(bp, mem_tbl[i].offset + j*4); 1659 1660 /* Check the parity status */ 1661 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 1662 val = REG_RD(bp, prty_tbl[i].offset); 1663 if (val & ~(prty_tbl[i].hw_mask[index])) { 1664 DP(NETIF_MSG_HW, 1665 "%s is 0x%x\n", prty_tbl[i].name, val); 1666 goto test_mem_exit; 1667 } 1668 } 1669 1670 rc = 0; 1671 1672test_mem_exit: 1673 return rc; 1674} 1675 1676static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 1677{ 1678 int cnt = 1400; 1679 1680 if (link_up) { 1681 while (bnx2x_link_test(bp, is_serdes) && cnt--) 1682 msleep(20); 1683 1684 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 1685 DP(NETIF_MSG_LINK, "Timeout waiting for link up\n"); 1686 } 1687} 1688 1689static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 1690{ 1691 unsigned int pkt_size, num_pkts, i; 1692 struct sk_buff *skb; 1693 unsigned char *packet; 1694 struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 1695 struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 1696 struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0]; 1697 u16 tx_start_idx, tx_idx; 1698 u16 rx_start_idx, rx_idx; 1699 u16 pkt_prod, bd_prod, rx_comp_cons; 1700 struct sw_tx_bd *tx_buf; 1701 struct eth_tx_start_bd *tx_start_bd; 1702 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL; 1703 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL; 1704 dma_addr_t mapping; 1705 union eth_rx_cqe *cqe; 1706 u8 cqe_fp_flags, cqe_fp_type; 1707 struct sw_rx_bd *rx_buf; 1708 u16 len; 1709 int rc = -ENODEV; 1710 1711 /* check the loopback mode */ 1712 switch (loopback_mode) { 1713 case BNX2X_PHY_LOOPBACK: 1714 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) 1715 return -EINVAL; 1716 break; 1717 case BNX2X_MAC_LOOPBACK: 1718 bp->link_params.loopback_mode = CHIP_IS_E3(bp) ? 1719 LOOPBACK_XMAC : LOOPBACK_BMAC; 1720 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 1721 break; 1722 default: 1723 return -EINVAL; 1724 } 1725 1726 /* prepare the loopback packet */ 1727 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 1728 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 1729 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 1730 if (!skb) { 1731 rc = -ENOMEM; 1732 goto test_loopback_exit; 1733 } 1734 packet = skb_put(skb, pkt_size); 1735 memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 1736 memset(packet + ETH_ALEN, 0, ETH_ALEN); 1737 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 1738 for (i = ETH_HLEN; i < pkt_size; i++) 1739 packet[i] = (unsigned char) (i & 0xff); 1740 mapping = dma_map_single(&bp->pdev->dev, skb->data, 1741 skb_headlen(skb), DMA_TO_DEVICE); 1742 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 1743 rc = -ENOMEM; 1744 dev_kfree_skb(skb); 1745 BNX2X_ERR("Unable to map SKB\n"); 1746 goto test_loopback_exit; 1747 } 1748 1749 /* send the loopback packet */ 1750 num_pkts = 0; 1751 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 1752 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 1753 1754 pkt_prod = txdata->tx_pkt_prod++; 1755 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 1756 tx_buf->first_bd = txdata->tx_bd_prod; 1757 tx_buf->skb = skb; 1758 tx_buf->flags = 0; 1759 1760 bd_prod = TX_BD(txdata->tx_bd_prod); 1761 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 1762 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 1763 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 1764 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 1765 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 1766 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 1767 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 1768 SET_FLAG(tx_start_bd->general_data, 1769 ETH_TX_START_BD_ETH_ADDR_TYPE, 1770 UNICAST_ADDRESS); 1771 SET_FLAG(tx_start_bd->general_data, 1772 ETH_TX_START_BD_HDR_NBDS, 1773 1); 1774 1775 /* turn on parsing and get a BD */ 1776 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 1777 1778 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 1779 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 1780 1781 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 1782 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 1783 1784 wmb(); 1785 1786 txdata->tx_db.data.prod += 2; 1787 barrier(); 1788 DOORBELL(bp, txdata->cid, txdata->tx_db.raw); 1789 1790 mmiowb(); 1791 barrier(); 1792 1793 num_pkts++; 1794 txdata->tx_bd_prod += 2; /* start + pbd */ 1795 1796 udelay(100); 1797 1798 tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 1799 if (tx_idx != tx_start_idx + num_pkts) 1800 goto test_loopback_exit; 1801 1802 /* Unlike HC IGU won't generate an interrupt for status block 1803 * updates that have been performed while interrupts were 1804 * disabled. 1805 */ 1806 if (bp->common.int_block == INT_BLOCK_IGU) { 1807 /* Disable local BHes to prevent a dead-lock situation between 1808 * sch_direct_xmit() and bnx2x_run_loopback() (calling 1809 * bnx2x_tx_int()), as both are taking netif_tx_lock(). 1810 */ 1811 local_bh_disable(); 1812 bnx2x_tx_int(bp, txdata); 1813 local_bh_enable(); 1814 } 1815 1816 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 1817 if (rx_idx != rx_start_idx + num_pkts) 1818 goto test_loopback_exit; 1819 1820 rx_comp_cons = le16_to_cpu(fp_rx->rx_comp_cons); 1821 cqe = &fp_rx->rx_comp_ring[RCQ_BD(rx_comp_cons)]; 1822 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 1823 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 1824 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 1825 goto test_loopback_rx_exit; 1826 1827 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len); 1828 if (len != pkt_size) 1829 goto test_loopback_rx_exit; 1830 1831 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 1832 dma_sync_single_for_cpu(&bp->pdev->dev, 1833 dma_unmap_addr(rx_buf, mapping), 1834 fp_rx->rx_buf_size, DMA_FROM_DEVICE); 1835 skb = rx_buf->skb; 1836 skb_reserve(skb, cqe->fast_path_cqe.placement_offset); 1837 for (i = ETH_HLEN; i < pkt_size; i++) 1838 if (*(skb->data + i) != (unsigned char) (i & 0xff)) 1839 goto test_loopback_rx_exit; 1840 1841 rc = 0; 1842 1843test_loopback_rx_exit: 1844 1845 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 1846 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 1847 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 1848 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 1849 1850 /* Update producers */ 1851 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 1852 fp_rx->rx_sge_prod); 1853 1854test_loopback_exit: 1855 bp->link_params.loopback_mode = LOOPBACK_NONE; 1856 1857 return rc; 1858} 1859 1860static int bnx2x_test_loopback(struct bnx2x *bp) 1861{ 1862 int rc = 0, res; 1863 1864 if (BP_NOMCP(bp)) 1865 return rc; 1866 1867 if (!netif_running(bp->dev)) 1868 return BNX2X_LOOPBACK_FAILED; 1869 1870 bnx2x_netif_stop(bp, 1); 1871 bnx2x_acquire_phy_lock(bp); 1872 1873 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 1874 if (res) { 1875 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res); 1876 rc |= BNX2X_PHY_LOOPBACK_FAILED; 1877 } 1878 1879 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 1880 if (res) { 1881 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res); 1882 rc |= BNX2X_MAC_LOOPBACK_FAILED; 1883 } 1884 1885 bnx2x_release_phy_lock(bp); 1886 bnx2x_netif_start(bp); 1887 1888 return rc; 1889} 1890 1891#define CRC32_RESIDUAL 0xdebb20e3 1892 1893static int bnx2x_test_nvram(struct bnx2x *bp) 1894{ 1895 static const struct { 1896 int offset; 1897 int size; 1898 } nvram_tbl[] = { 1899 { 0, 0x14 }, /* bootstrap */ 1900 { 0x14, 0xec }, /* dir */ 1901 { 0x100, 0x350 }, /* manuf_info */ 1902 { 0x450, 0xf0 }, /* feature_info */ 1903 { 0x640, 0x64 }, /* upgrade_key_info */ 1904 { 0x708, 0x70 }, /* manuf_key_info */ 1905 { 0, 0 } 1906 }; 1907 __be32 buf[0x350 / 4]; 1908 u8 *data = (u8 *)buf; 1909 int i, rc; 1910 u32 magic, crc; 1911 1912 if (BP_NOMCP(bp)) 1913 return 0; 1914 1915 rc = bnx2x_nvram_read(bp, 0, data, 4); 1916 if (rc) { 1917 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc); 1918 goto test_nvram_exit; 1919 } 1920 1921 magic = be32_to_cpu(buf[0]); 1922 if (magic != 0x669955aa) { 1923 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic); 1924 rc = -ENODEV; 1925 goto test_nvram_exit; 1926 } 1927 1928 for (i = 0; nvram_tbl[i].size; i++) { 1929 1930 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data, 1931 nvram_tbl[i].size); 1932 if (rc) { 1933 DP(NETIF_MSG_PROBE, 1934 "nvram_tbl[%d] read data (rc %d)\n", i, rc); 1935 goto test_nvram_exit; 1936 } 1937 1938 crc = ether_crc_le(nvram_tbl[i].size, data); 1939 if (crc != CRC32_RESIDUAL) { 1940 DP(NETIF_MSG_PROBE, 1941 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc); 1942 rc = -ENODEV; 1943 goto test_nvram_exit; 1944 } 1945 } 1946 1947test_nvram_exit: 1948 return rc; 1949} 1950 1951/* Send an EMPTY ramrod on the first queue */ 1952static int bnx2x_test_intr(struct bnx2x *bp) 1953{ 1954 struct bnx2x_queue_state_params params = {0}; 1955 1956 if (!netif_running(bp->dev)) 1957 return -ENODEV; 1958 1959 params.q_obj = &bp->fp->q_obj; 1960 params.cmd = BNX2X_Q_CMD_EMPTY; 1961 1962 __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 1963 1964 return bnx2x_queue_state_change(bp, ¶ms); 1965} 1966 1967static void bnx2x_self_test(struct net_device *dev, 1968 struct ethtool_test *etest, u64 *buf) 1969{ 1970 struct bnx2x *bp = netdev_priv(dev); 1971 u8 is_serdes; 1972 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 1973 printk(KERN_ERR "Handling parity error recovery. Try again later\n"); 1974 etest->flags |= ETH_TEST_FL_FAILED; 1975 return; 1976 } 1977 1978 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS); 1979 1980 if (!netif_running(dev)) 1981 return; 1982 1983 /* offline tests are not supported in MF mode */ 1984 if (IS_MF(bp)) 1985 etest->flags &= ~ETH_TEST_FL_OFFLINE; 1986 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 1987 1988 if (etest->flags & ETH_TEST_FL_OFFLINE) { 1989 int port = BP_PORT(bp); 1990 u32 val; 1991 u8 link_up; 1992 1993 /* save current value of input enable for TX port IF */ 1994 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 1995 /* disable input for TX port IF */ 1996 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 1997 1998 link_up = bp->link_vars.link_up; 1999 2000 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 2001 bnx2x_nic_load(bp, LOAD_DIAG); 2002 /* wait until link state is restored */ 2003 bnx2x_wait_for_link(bp, 1, is_serdes); 2004 2005 if (bnx2x_test_registers(bp) != 0) { 2006 buf[0] = 1; 2007 etest->flags |= ETH_TEST_FL_FAILED; 2008 } 2009 if (bnx2x_test_memory(bp) != 0) { 2010 buf[1] = 1; 2011 etest->flags |= ETH_TEST_FL_FAILED; 2012 } 2013 2014 buf[2] = bnx2x_test_loopback(bp); 2015 if (buf[2] != 0) 2016 etest->flags |= ETH_TEST_FL_FAILED; 2017 2018 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 2019 2020 /* restore input for TX port IF */ 2021 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 2022 2023 bnx2x_nic_load(bp, LOAD_NORMAL); 2024 /* wait until link state is restored */ 2025 bnx2x_wait_for_link(bp, link_up, is_serdes); 2026 } 2027 if (bnx2x_test_nvram(bp) != 0) { 2028 buf[3] = 1; 2029 etest->flags |= ETH_TEST_FL_FAILED; 2030 } 2031 if (bnx2x_test_intr(bp) != 0) { 2032 buf[4] = 1; 2033 etest->flags |= ETH_TEST_FL_FAILED; 2034 } 2035 2036 if (bnx2x_link_test(bp, is_serdes) != 0) { 2037 buf[5] = 1; 2038 etest->flags |= ETH_TEST_FL_FAILED; 2039 } 2040 2041#ifdef BNX2X_EXTRA_DEBUG 2042 bnx2x_panic_dump(bp); 2043#endif 2044} 2045 2046#define IS_PORT_STAT(i) \ 2047 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) 2048#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) 2049#define IS_MF_MODE_STAT(bp) \ 2050 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) 2051 2052/* ethtool statistics are displayed for all regular ethernet queues and the 2053 * fcoe L2 queue if not disabled 2054 */ 2055static inline int bnx2x_num_stat_queues(struct bnx2x *bp) 2056{ 2057 return BNX2X_NUM_ETH_QUEUES(bp); 2058} 2059 2060static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 2061{ 2062 struct bnx2x *bp = netdev_priv(dev); 2063 int i, num_stats; 2064 2065 switch (stringset) { 2066 case ETH_SS_STATS: 2067 if (is_multi(bp)) { 2068 num_stats = bnx2x_num_stat_queues(bp) * 2069 BNX2X_NUM_Q_STATS; 2070 if (!IS_MF_MODE_STAT(bp)) 2071 num_stats += BNX2X_NUM_STATS; 2072 } else { 2073 if (IS_MF_MODE_STAT(bp)) { 2074 num_stats = 0; 2075 for (i = 0; i < BNX2X_NUM_STATS; i++) 2076 if (IS_FUNC_STAT(i)) 2077 num_stats++; 2078 } else 2079 num_stats = BNX2X_NUM_STATS; 2080 } 2081 return num_stats; 2082 2083 case ETH_SS_TEST: 2084 return BNX2X_NUM_TESTS; 2085 2086 default: 2087 return -EINVAL; 2088 } 2089} 2090 2091static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 2092{ 2093 struct bnx2x *bp = netdev_priv(dev); 2094 int i, j, k; 2095 char queue_name[MAX_QUEUE_NAME_LEN+1]; 2096 2097 switch (stringset) { 2098 case ETH_SS_STATS: 2099 if (is_multi(bp)) { 2100 k = 0; 2101 for_each_eth_queue(bp, i) { 2102 memset(queue_name, 0, sizeof(queue_name)); 2103 sprintf(queue_name, "%d", i); 2104 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 2105 snprintf(buf + (k + j)*ETH_GSTRING_LEN, 2106 ETH_GSTRING_LEN, 2107 bnx2x_q_stats_arr[j].string, 2108 queue_name); 2109 k += BNX2X_NUM_Q_STATS; 2110 } 2111 if (IS_MF_MODE_STAT(bp)) 2112 break; 2113 for (j = 0; j < BNX2X_NUM_STATS; j++) 2114 strcpy(buf + (k + j)*ETH_GSTRING_LEN, 2115 bnx2x_stats_arr[j].string); 2116 } else { 2117 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 2118 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 2119 continue; 2120 strcpy(buf + j*ETH_GSTRING_LEN, 2121 bnx2x_stats_arr[i].string); 2122 j++; 2123 } 2124 } 2125 break; 2126 2127 case ETH_SS_TEST: 2128 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr)); 2129 break; 2130 } 2131} 2132 2133static void bnx2x_get_ethtool_stats(struct net_device *dev, 2134 struct ethtool_stats *stats, u64 *buf) 2135{ 2136 struct bnx2x *bp = netdev_priv(dev); 2137 u32 *hw_stats, *offset; 2138 int i, j, k; 2139 2140 if (is_multi(bp)) { 2141 k = 0; 2142 for_each_eth_queue(bp, i) { 2143 hw_stats = (u32 *)&bp->fp[i].eth_q_stats; 2144 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 2145 if (bnx2x_q_stats_arr[j].size == 0) { 2146 /* skip this counter */ 2147 buf[k + j] = 0; 2148 continue; 2149 } 2150 offset = (hw_stats + 2151 bnx2x_q_stats_arr[j].offset); 2152 if (bnx2x_q_stats_arr[j].size == 4) { 2153 /* 4-byte counter */ 2154 buf[k + j] = (u64) *offset; 2155 continue; 2156 } 2157 /* 8-byte counter */ 2158 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 2159 } 2160 k += BNX2X_NUM_Q_STATS; 2161 } 2162 if (IS_MF_MODE_STAT(bp)) 2163 return; 2164 hw_stats = (u32 *)&bp->eth_stats; 2165 for (j = 0; j < BNX2X_NUM_STATS; j++) { 2166 if (bnx2x_stats_arr[j].size == 0) { 2167 /* skip this counter */ 2168 buf[k + j] = 0; 2169 continue; 2170 } 2171 offset = (hw_stats + bnx2x_stats_arr[j].offset); 2172 if (bnx2x_stats_arr[j].size == 4) { 2173 /* 4-byte counter */ 2174 buf[k + j] = (u64) *offset; 2175 continue; 2176 } 2177 /* 8-byte counter */ 2178 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 2179 } 2180 } else { 2181 hw_stats = (u32 *)&bp->eth_stats; 2182 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 2183 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 2184 continue; 2185 if (bnx2x_stats_arr[i].size == 0) { 2186 /* skip this counter */ 2187 buf[j] = 0; 2188 j++; 2189 continue; 2190 } 2191 offset = (hw_stats + bnx2x_stats_arr[i].offset); 2192 if (bnx2x_stats_arr[i].size == 4) { 2193 /* 4-byte counter */ 2194 buf[j] = (u64) *offset; 2195 j++; 2196 continue; 2197 } 2198 /* 8-byte counter */ 2199 buf[j] = HILO_U64(*offset, *(offset + 1)); 2200 j++; 2201 } 2202 } 2203} 2204 2205static int bnx2x_set_phys_id(struct net_device *dev, 2206 enum ethtool_phys_id_state state) 2207{ 2208 struct bnx2x *bp = netdev_priv(dev); 2209 2210 if (!netif_running(dev)) 2211 return -EAGAIN; 2212 2213 if (!bp->port.pmf) 2214 return -EOPNOTSUPP; 2215 2216 switch (state) { 2217 case ETHTOOL_ID_ACTIVE: 2218 return 1; /* cycle on/off once per second */ 2219 2220 case ETHTOOL_ID_ON: 2221 bnx2x_set_led(&bp->link_params, &bp->link_vars, 2222 LED_MODE_ON, SPEED_1000); 2223 break; 2224 2225 case ETHTOOL_ID_OFF: 2226 bnx2x_set_led(&bp->link_params, &bp->link_vars, 2227 LED_MODE_FRONT_PANEL_OFF, 0); 2228 2229 break; 2230 2231 case ETHTOOL_ID_INACTIVE: 2232 bnx2x_set_led(&bp->link_params, &bp->link_vars, 2233 LED_MODE_OPER, 2234 bp->link_vars.line_speed); 2235 } 2236 2237 return 0; 2238} 2239 2240static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 2241 void *rules __always_unused) 2242{ 2243 struct bnx2x *bp = netdev_priv(dev); 2244 2245 switch (info->cmd) { 2246 case ETHTOOL_GRXRINGS: 2247 info->data = BNX2X_NUM_ETH_QUEUES(bp); 2248 return 0; 2249 2250 default: 2251 return -EOPNOTSUPP; 2252 } 2253} 2254 2255static int bnx2x_get_rxfh_indir(struct net_device *dev, 2256 struct ethtool_rxfh_indir *indir) 2257{ 2258 struct bnx2x *bp = netdev_priv(dev); 2259 size_t copy_size = 2260 min_t(size_t, indir->size, T_ETH_INDIRECTION_TABLE_SIZE); 2261 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 2262 size_t i; 2263 2264 if (bp->multi_mode == ETH_RSS_MODE_DISABLED) 2265 return -EOPNOTSUPP; 2266 2267 /* Get the current configuration of the RSS indirection table */ 2268 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 2269 2270 /* 2271 * We can't use a memcpy() as an internal storage of an 2272 * indirection table is a u8 array while indir->ring_index 2273 * points to an array of u32. 2274 * 2275 * Indirection table contains the FW Client IDs, so we need to 2276 * align the returned table to the Client ID of the leading RSS 2277 * queue. 2278 */ 2279 for (i = 0; i < copy_size; i++) 2280 indir->ring_index[i] = ind_table[i] - bp->fp->cl_id; 2281 2282 indir->size = T_ETH_INDIRECTION_TABLE_SIZE; 2283 2284 return 0; 2285} 2286 2287static int bnx2x_set_rxfh_indir(struct net_device *dev, 2288 const struct ethtool_rxfh_indir *indir) 2289{ 2290 struct bnx2x *bp = netdev_priv(dev); 2291 size_t i; 2292 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 2293 u32 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp); 2294 2295 if (bp->multi_mode == ETH_RSS_MODE_DISABLED) 2296 return -EOPNOTSUPP; 2297 2298 /* validate the size */ 2299 if (indir->size != T_ETH_INDIRECTION_TABLE_SIZE) 2300 return -EINVAL; 2301 2302 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 2303 /* validate the indices */ 2304 if (indir->ring_index[i] >= num_eth_queues) 2305 return -EINVAL; 2306 /* 2307 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy() 2308 * as an internal storage of an indirection table is a u8 array 2309 * while indir->ring_index points to an array of u32. 2310 * 2311 * Indirection table contains the FW Client IDs, so we need to 2312 * align the received table to the Client ID of the leading RSS 2313 * queue 2314 */ 2315 ind_table[i] = indir->ring_index[i] + bp->fp->cl_id; 2316 } 2317 2318 return bnx2x_config_rss_pf(bp, ind_table, false); 2319} 2320 2321static const struct ethtool_ops bnx2x_ethtool_ops = { 2322 .get_settings = bnx2x_get_settings, 2323 .set_settings = bnx2x_set_settings, 2324 .get_drvinfo = bnx2x_get_drvinfo, 2325 .get_regs_len = bnx2x_get_regs_len, 2326 .get_regs = bnx2x_get_regs, 2327 .get_wol = bnx2x_get_wol, 2328 .set_wol = bnx2x_set_wol, 2329 .get_msglevel = bnx2x_get_msglevel, 2330 .set_msglevel = bnx2x_set_msglevel, 2331 .nway_reset = bnx2x_nway_reset, 2332 .get_link = bnx2x_get_link, 2333 .get_eeprom_len = bnx2x_get_eeprom_len, 2334 .get_eeprom = bnx2x_get_eeprom, 2335 .set_eeprom = bnx2x_set_eeprom, 2336 .get_coalesce = bnx2x_get_coalesce, 2337 .set_coalesce = bnx2x_set_coalesce, 2338 .get_ringparam = bnx2x_get_ringparam, 2339 .set_ringparam = bnx2x_set_ringparam, 2340 .get_pauseparam = bnx2x_get_pauseparam, 2341 .set_pauseparam = bnx2x_set_pauseparam, 2342 .self_test = bnx2x_self_test, 2343 .get_sset_count = bnx2x_get_sset_count, 2344 .get_strings = bnx2x_get_strings, 2345 .set_phys_id = bnx2x_set_phys_id, 2346 .get_ethtool_stats = bnx2x_get_ethtool_stats, 2347 .get_rxnfc = bnx2x_get_rxnfc, 2348 .get_rxfh_indir = bnx2x_get_rxfh_indir, 2349 .set_rxfh_indir = bnx2x_set_rxfh_indir, 2350}; 2351 2352void bnx2x_set_ethtool_ops(struct net_device *netdev) 2353{ 2354 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops); 2355} 2356