bnx2x_ethtool.c revision e52fcb2462ac484e6dd6e68869536609f0216938
1/* bnx2x_ethtool.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2011 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20#include <linux/ethtool.h> 21#include <linux/netdevice.h> 22#include <linux/types.h> 23#include <linux/sched.h> 24#include <linux/crc32.h> 25 26 27#include "bnx2x.h" 28#include "bnx2x_cmn.h" 29#include "bnx2x_dump.h" 30#include "bnx2x_init.h" 31#include "bnx2x_sp.h" 32 33/* Note: in the format strings below %s is replaced by the queue-name which is 34 * either its index or 'fcoe' for the fcoe queue. Make sure the format string 35 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 36 */ 37#define MAX_QUEUE_NAME_LEN 4 38static const struct { 39 long offset; 40 int size; 41 char string[ETH_GSTRING_LEN]; 42} bnx2x_q_stats_arr[] = { 43/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 44 { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 45 8, "[%s]: rx_ucast_packets" }, 46 { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 47 8, "[%s]: rx_mcast_packets" }, 48 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 49 8, "[%s]: rx_bcast_packets" }, 50 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 51 { Q_STATS_OFFSET32(rx_err_discard_pkt), 52 4, "[%s]: rx_phy_ip_err_discards"}, 53 { Q_STATS_OFFSET32(rx_skb_alloc_failed), 54 4, "[%s]: rx_skb_alloc_discard" }, 55 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 56 57 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 58/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 59 8, "[%s]: tx_ucast_packets" }, 60 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 61 8, "[%s]: tx_mcast_packets" }, 62 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 63 8, "[%s]: tx_bcast_packets" }, 64 { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 65 8, "[%s]: tpa_aggregations" }, 66 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 67 8, "[%s]: tpa_aggregated_frames"}, 68 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"} 69}; 70 71#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 72 73static const struct { 74 long offset; 75 int size; 76 u32 flags; 77#define STATS_FLAGS_PORT 1 78#define STATS_FLAGS_FUNC 2 79#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 80 char string[ETH_GSTRING_LEN]; 81} bnx2x_stats_arr[] = { 82/* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 83 8, STATS_FLAGS_BOTH, "rx_bytes" }, 84 { STATS_OFFSET32(error_bytes_received_hi), 85 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 86 { STATS_OFFSET32(total_unicast_packets_received_hi), 87 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 88 { STATS_OFFSET32(total_multicast_packets_received_hi), 89 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 90 { STATS_OFFSET32(total_broadcast_packets_received_hi), 91 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 92 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 93 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 94 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 95 8, STATS_FLAGS_PORT, "rx_align_errors" }, 96 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 97 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 98 { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 99 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 100/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 101 8, STATS_FLAGS_PORT, "rx_fragments" }, 102 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 103 8, STATS_FLAGS_PORT, "rx_jabbers" }, 104 { STATS_OFFSET32(no_buff_discard_hi), 105 8, STATS_FLAGS_BOTH, "rx_discards" }, 106 { STATS_OFFSET32(mac_filter_discard), 107 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 108 { STATS_OFFSET32(mf_tag_discard), 109 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 110 { STATS_OFFSET32(brb_drop_hi), 111 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 112 { STATS_OFFSET32(brb_truncate_hi), 113 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 114 { STATS_OFFSET32(pause_frames_received_hi), 115 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 116 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 117 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 118 { STATS_OFFSET32(nig_timer_max), 119 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 120/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 121 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, 122 { STATS_OFFSET32(rx_skb_alloc_failed), 123 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, 124 { STATS_OFFSET32(hw_csum_err), 125 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, 126 127 { STATS_OFFSET32(total_bytes_transmitted_hi), 128 8, STATS_FLAGS_BOTH, "tx_bytes" }, 129 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 130 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 131 { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 132 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 133 { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 134 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 135 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 136 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 137 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 138 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 139 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 140 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 141/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 142 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 143 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 144 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 145 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 146 8, STATS_FLAGS_PORT, "tx_deferred" }, 147 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 148 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 149 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 150 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 151 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 152 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 153 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 154 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 155 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 156 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 157 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 158 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 159 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 160 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 161/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 162 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 163 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 164 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 165 { STATS_OFFSET32(etherstatspktsover1522octets_hi), 166 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 167 { STATS_OFFSET32(pause_frames_sent_hi), 168 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 169 { STATS_OFFSET32(total_tpa_aggregations_hi), 170 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 171 { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 172 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 173 { STATS_OFFSET32(total_tpa_bytes_hi), 174 8, STATS_FLAGS_FUNC, "tpa_bytes"} 175}; 176 177#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 178static int bnx2x_get_port_type(struct bnx2x *bp) 179{ 180 int port_type; 181 u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 182 switch (bp->link_params.phy[phy_idx].media_type) { 183 case ETH_PHY_SFP_FIBER: 184 case ETH_PHY_XFP_FIBER: 185 case ETH_PHY_KR: 186 case ETH_PHY_CX4: 187 port_type = PORT_FIBRE; 188 break; 189 case ETH_PHY_DA_TWINAX: 190 port_type = PORT_DA; 191 break; 192 case ETH_PHY_BASE_T: 193 port_type = PORT_TP; 194 break; 195 case ETH_PHY_NOT_PRESENT: 196 port_type = PORT_NONE; 197 break; 198 case ETH_PHY_UNSPECIFIED: 199 default: 200 port_type = PORT_OTHER; 201 break; 202 } 203 return port_type; 204} 205 206static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 207{ 208 struct bnx2x *bp = netdev_priv(dev); 209 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 210 211 /* Dual Media boards present all available port types */ 212 cmd->supported = bp->port.supported[cfg_idx] | 213 (bp->port.supported[cfg_idx ^ 1] & 214 (SUPPORTED_TP | SUPPORTED_FIBRE)); 215 cmd->advertising = bp->port.advertising[cfg_idx]; 216 217 if ((bp->state == BNX2X_STATE_OPEN) && 218 !(bp->flags & MF_FUNC_DIS) && 219 (bp->link_vars.link_up)) { 220 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); 221 cmd->duplex = bp->link_vars.duplex; 222 } else { 223 ethtool_cmd_speed_set( 224 cmd, bp->link_params.req_line_speed[cfg_idx]); 225 cmd->duplex = bp->link_params.req_duplex[cfg_idx]; 226 } 227 228 if (IS_MF(bp)) 229 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); 230 231 cmd->port = bnx2x_get_port_type(bp); 232 233 cmd->phy_address = bp->mdio.prtad; 234 cmd->transceiver = XCVR_INTERNAL; 235 236 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 237 cmd->autoneg = AUTONEG_ENABLE; 238 else 239 cmd->autoneg = AUTONEG_DISABLE; 240 241 cmd->maxtxpkt = 0; 242 cmd->maxrxpkt = 0; 243 244 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n" 245 " supported 0x%x advertising 0x%x speed %u\n" 246 " duplex %d port %d phy_address %d transceiver %d\n" 247 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 248 cmd->cmd, cmd->supported, cmd->advertising, 249 ethtool_cmd_speed(cmd), 250 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 251 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 252 253 return 0; 254} 255 256static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 257{ 258 struct bnx2x *bp = netdev_priv(dev); 259 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 260 u32 speed; 261 262 if (IS_MF_SD(bp)) 263 return 0; 264 265 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n" 266 " supported 0x%x advertising 0x%x speed %u\n" 267 " duplex %d port %d phy_address %d transceiver %d\n" 268 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 269 cmd->cmd, cmd->supported, cmd->advertising, 270 ethtool_cmd_speed(cmd), 271 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 272 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 273 274 speed = ethtool_cmd_speed(cmd); 275 276 if (IS_MF_SI(bp)) { 277 u32 part; 278 u32 line_speed = bp->link_vars.line_speed; 279 280 /* use 10G if no link detected */ 281 if (!line_speed) 282 line_speed = 10000; 283 284 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 285 BNX2X_DEV_INFO("To set speed BC %X or higher " 286 "is required, please upgrade BC\n", 287 REQ_BC_VER_4_SET_MF_BW); 288 return -EINVAL; 289 } 290 291 part = (speed * 100) / line_speed; 292 293 if (line_speed < speed || !part) { 294 BNX2X_DEV_INFO("Speed setting should be in a range " 295 "from 1%% to 100%% " 296 "of actual line speed\n"); 297 return -EINVAL; 298 } 299 300 if (bp->state != BNX2X_STATE_OPEN) 301 /* store value for following "load" */ 302 bp->pending_max = part; 303 else 304 bnx2x_update_max_mf_config(bp, part); 305 306 return 0; 307 } 308 309 cfg_idx = bnx2x_get_link_cfg_idx(bp); 310 old_multi_phy_config = bp->link_params.multi_phy_config; 311 switch (cmd->port) { 312 case PORT_TP: 313 if (bp->port.supported[cfg_idx] & SUPPORTED_TP) 314 break; /* no port change */ 315 316 if (!(bp->port.supported[0] & SUPPORTED_TP || 317 bp->port.supported[1] & SUPPORTED_TP)) { 318 DP(NETIF_MSG_LINK, "Unsupported port type\n"); 319 return -EINVAL; 320 } 321 bp->link_params.multi_phy_config &= 322 ~PORT_HW_CFG_PHY_SELECTION_MASK; 323 if (bp->link_params.multi_phy_config & 324 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 325 bp->link_params.multi_phy_config |= 326 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 327 else 328 bp->link_params.multi_phy_config |= 329 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 330 break; 331 case PORT_FIBRE: 332 case PORT_DA: 333 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE) 334 break; /* no port change */ 335 336 if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 337 bp->port.supported[1] & SUPPORTED_FIBRE)) { 338 DP(NETIF_MSG_LINK, "Unsupported port type\n"); 339 return -EINVAL; 340 } 341 bp->link_params.multi_phy_config &= 342 ~PORT_HW_CFG_PHY_SELECTION_MASK; 343 if (bp->link_params.multi_phy_config & 344 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 345 bp->link_params.multi_phy_config |= 346 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 347 else 348 bp->link_params.multi_phy_config |= 349 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 350 break; 351 default: 352 DP(NETIF_MSG_LINK, "Unsupported port type\n"); 353 return -EINVAL; 354 } 355 /* Save new config in case command complete successuly */ 356 new_multi_phy_config = bp->link_params.multi_phy_config; 357 /* Get the new cfg_idx */ 358 cfg_idx = bnx2x_get_link_cfg_idx(bp); 359 /* Restore old config in case command failed */ 360 bp->link_params.multi_phy_config = old_multi_phy_config; 361 DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx); 362 363 if (cmd->autoneg == AUTONEG_ENABLE) { 364 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 365 DP(NETIF_MSG_LINK, "Autoneg not supported\n"); 366 return -EINVAL; 367 } 368 369 /* advertise the requested speed and duplex if supported */ 370 if (cmd->advertising & ~(bp->port.supported[cfg_idx])) { 371 DP(NETIF_MSG_LINK, "Advertisement parameters " 372 "are not supported\n"); 373 return -EINVAL; 374 } 375 376 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 377 bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 378 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 379 cmd->advertising); 380 if (cmd->advertising) { 381 382 bp->link_params.speed_cap_mask[cfg_idx] = 0; 383 if (cmd->advertising & ADVERTISED_10baseT_Half) { 384 bp->link_params.speed_cap_mask[cfg_idx] |= 385 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 386 } 387 if (cmd->advertising & ADVERTISED_10baseT_Full) 388 bp->link_params.speed_cap_mask[cfg_idx] |= 389 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 390 391 if (cmd->advertising & ADVERTISED_100baseT_Full) 392 bp->link_params.speed_cap_mask[cfg_idx] |= 393 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 394 395 if (cmd->advertising & ADVERTISED_100baseT_Half) { 396 bp->link_params.speed_cap_mask[cfg_idx] |= 397 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 398 } 399 if (cmd->advertising & ADVERTISED_1000baseT_Half) { 400 bp->link_params.speed_cap_mask[cfg_idx] |= 401 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 402 } 403 if (cmd->advertising & (ADVERTISED_1000baseT_Full | 404 ADVERTISED_1000baseKX_Full)) 405 bp->link_params.speed_cap_mask[cfg_idx] |= 406 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 407 408 if (cmd->advertising & (ADVERTISED_10000baseT_Full | 409 ADVERTISED_10000baseKX4_Full | 410 ADVERTISED_10000baseKR_Full)) 411 bp->link_params.speed_cap_mask[cfg_idx] |= 412 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 413 } 414 } else { /* forced speed */ 415 /* advertise the requested speed and duplex if supported */ 416 switch (speed) { 417 case SPEED_10: 418 if (cmd->duplex == DUPLEX_FULL) { 419 if (!(bp->port.supported[cfg_idx] & 420 SUPPORTED_10baseT_Full)) { 421 DP(NETIF_MSG_LINK, 422 "10M full not supported\n"); 423 return -EINVAL; 424 } 425 426 advertising = (ADVERTISED_10baseT_Full | 427 ADVERTISED_TP); 428 } else { 429 if (!(bp->port.supported[cfg_idx] & 430 SUPPORTED_10baseT_Half)) { 431 DP(NETIF_MSG_LINK, 432 "10M half not supported\n"); 433 return -EINVAL; 434 } 435 436 advertising = (ADVERTISED_10baseT_Half | 437 ADVERTISED_TP); 438 } 439 break; 440 441 case SPEED_100: 442 if (cmd->duplex == DUPLEX_FULL) { 443 if (!(bp->port.supported[cfg_idx] & 444 SUPPORTED_100baseT_Full)) { 445 DP(NETIF_MSG_LINK, 446 "100M full not supported\n"); 447 return -EINVAL; 448 } 449 450 advertising = (ADVERTISED_100baseT_Full | 451 ADVERTISED_TP); 452 } else { 453 if (!(bp->port.supported[cfg_idx] & 454 SUPPORTED_100baseT_Half)) { 455 DP(NETIF_MSG_LINK, 456 "100M half not supported\n"); 457 return -EINVAL; 458 } 459 460 advertising = (ADVERTISED_100baseT_Half | 461 ADVERTISED_TP); 462 } 463 break; 464 465 case SPEED_1000: 466 if (cmd->duplex != DUPLEX_FULL) { 467 DP(NETIF_MSG_LINK, "1G half not supported\n"); 468 return -EINVAL; 469 } 470 471 if (!(bp->port.supported[cfg_idx] & 472 SUPPORTED_1000baseT_Full)) { 473 DP(NETIF_MSG_LINK, "1G full not supported\n"); 474 return -EINVAL; 475 } 476 477 advertising = (ADVERTISED_1000baseT_Full | 478 ADVERTISED_TP); 479 break; 480 481 case SPEED_2500: 482 if (cmd->duplex != DUPLEX_FULL) { 483 DP(NETIF_MSG_LINK, 484 "2.5G half not supported\n"); 485 return -EINVAL; 486 } 487 488 if (!(bp->port.supported[cfg_idx] 489 & SUPPORTED_2500baseX_Full)) { 490 DP(NETIF_MSG_LINK, 491 "2.5G full not supported\n"); 492 return -EINVAL; 493 } 494 495 advertising = (ADVERTISED_2500baseX_Full | 496 ADVERTISED_TP); 497 break; 498 499 case SPEED_10000: 500 if (cmd->duplex != DUPLEX_FULL) { 501 DP(NETIF_MSG_LINK, "10G half not supported\n"); 502 return -EINVAL; 503 } 504 505 if (!(bp->port.supported[cfg_idx] 506 & SUPPORTED_10000baseT_Full)) { 507 DP(NETIF_MSG_LINK, "10G full not supported\n"); 508 return -EINVAL; 509 } 510 511 advertising = (ADVERTISED_10000baseT_Full | 512 ADVERTISED_FIBRE); 513 break; 514 515 default: 516 DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed); 517 return -EINVAL; 518 } 519 520 bp->link_params.req_line_speed[cfg_idx] = speed; 521 bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 522 bp->port.advertising[cfg_idx] = advertising; 523 } 524 525 DP(NETIF_MSG_LINK, "req_line_speed %d\n" 526 " req_duplex %d advertising 0x%x\n", 527 bp->link_params.req_line_speed[cfg_idx], 528 bp->link_params.req_duplex[cfg_idx], 529 bp->port.advertising[cfg_idx]); 530 531 /* Set new config */ 532 bp->link_params.multi_phy_config = new_multi_phy_config; 533 if (netif_running(dev)) { 534 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 535 bnx2x_link_set(bp); 536 } 537 538 return 0; 539} 540 541#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE) 542#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE) 543#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE) 544#define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE) 545#define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE) 546 547static inline bool bnx2x_is_reg_online(struct bnx2x *bp, 548 const struct reg_addr *reg_info) 549{ 550 if (CHIP_IS_E1(bp)) 551 return IS_E1_ONLINE(reg_info->info); 552 else if (CHIP_IS_E1H(bp)) 553 return IS_E1H_ONLINE(reg_info->info); 554 else if (CHIP_IS_E2(bp)) 555 return IS_E2_ONLINE(reg_info->info); 556 else if (CHIP_IS_E3A0(bp)) 557 return IS_E3_ONLINE(reg_info->info); 558 else if (CHIP_IS_E3B0(bp)) 559 return IS_E3B0_ONLINE(reg_info->info); 560 else 561 return false; 562} 563 564/******* Paged registers info selectors ********/ 565static inline const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 566{ 567 if (CHIP_IS_E2(bp)) 568 return page_vals_e2; 569 else if (CHIP_IS_E3(bp)) 570 return page_vals_e3; 571 else 572 return NULL; 573} 574 575static inline u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 576{ 577 if (CHIP_IS_E2(bp)) 578 return PAGE_MODE_VALUES_E2; 579 else if (CHIP_IS_E3(bp)) 580 return PAGE_MODE_VALUES_E3; 581 else 582 return 0; 583} 584 585static inline const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 586{ 587 if (CHIP_IS_E2(bp)) 588 return page_write_regs_e2; 589 else if (CHIP_IS_E3(bp)) 590 return page_write_regs_e3; 591 else 592 return NULL; 593} 594 595static inline u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 596{ 597 if (CHIP_IS_E2(bp)) 598 return PAGE_WRITE_REGS_E2; 599 else if (CHIP_IS_E3(bp)) 600 return PAGE_WRITE_REGS_E3; 601 else 602 return 0; 603} 604 605static inline const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 606{ 607 if (CHIP_IS_E2(bp)) 608 return page_read_regs_e2; 609 else if (CHIP_IS_E3(bp)) 610 return page_read_regs_e3; 611 else 612 return NULL; 613} 614 615static inline u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 616{ 617 if (CHIP_IS_E2(bp)) 618 return PAGE_READ_REGS_E2; 619 else if (CHIP_IS_E3(bp)) 620 return PAGE_READ_REGS_E3; 621 else 622 return 0; 623} 624 625static inline int __bnx2x_get_regs_len(struct bnx2x *bp) 626{ 627 int num_pages = __bnx2x_get_page_reg_num(bp); 628 int page_write_num = __bnx2x_get_page_write_num(bp); 629 const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp); 630 int page_read_num = __bnx2x_get_page_read_num(bp); 631 int regdump_len = 0; 632 int i, j, k; 633 634 for (i = 0; i < REGS_COUNT; i++) 635 if (bnx2x_is_reg_online(bp, ®_addrs[i])) 636 regdump_len += reg_addrs[i].size; 637 638 for (i = 0; i < num_pages; i++) 639 for (j = 0; j < page_write_num; j++) 640 for (k = 0; k < page_read_num; k++) 641 if (bnx2x_is_reg_online(bp, &page_read_addr[k])) 642 regdump_len += page_read_addr[k].size; 643 644 return regdump_len; 645} 646 647static int bnx2x_get_regs_len(struct net_device *dev) 648{ 649 struct bnx2x *bp = netdev_priv(dev); 650 int regdump_len = 0; 651 652 regdump_len = __bnx2x_get_regs_len(bp); 653 regdump_len *= 4; 654 regdump_len += sizeof(struct dump_hdr); 655 656 return regdump_len; 657} 658 659/** 660 * bnx2x_read_pages_regs - read "paged" registers 661 * 662 * @bp device handle 663 * @p output buffer 664 * 665 * Reads "paged" memories: memories that may only be read by first writing to a 666 * specific address ("write address") and then reading from a specific address 667 * ("read address"). There may be more than one write address per "page" and 668 * more than one read address per write address. 669 */ 670static inline void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p) 671{ 672 u32 i, j, k, n; 673 /* addresses of the paged registers */ 674 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 675 /* number of paged registers */ 676 int num_pages = __bnx2x_get_page_reg_num(bp); 677 /* write addresses */ 678 const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 679 /* number of write addresses */ 680 int write_num = __bnx2x_get_page_write_num(bp); 681 /* read addresses info */ 682 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 683 /* number of read addresses */ 684 int read_num = __bnx2x_get_page_read_num(bp); 685 686 for (i = 0; i < num_pages; i++) { 687 for (j = 0; j < write_num; j++) { 688 REG_WR(bp, write_addr[j], page_addr[i]); 689 for (k = 0; k < read_num; k++) 690 if (bnx2x_is_reg_online(bp, &read_addr[k])) 691 for (n = 0; n < 692 read_addr[k].size; n++) 693 *p++ = REG_RD(bp, 694 read_addr[k].addr + n*4); 695 } 696 } 697} 698 699static inline void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 700{ 701 u32 i, j; 702 703 /* Read the regular registers */ 704 for (i = 0; i < REGS_COUNT; i++) 705 if (bnx2x_is_reg_online(bp, ®_addrs[i])) 706 for (j = 0; j < reg_addrs[i].size; j++) 707 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 708 709 /* Read "paged" registes */ 710 bnx2x_read_pages_regs(bp, p); 711} 712 713static void bnx2x_get_regs(struct net_device *dev, 714 struct ethtool_regs *regs, void *_p) 715{ 716 u32 *p = _p; 717 struct bnx2x *bp = netdev_priv(dev); 718 struct dump_hdr dump_hdr = {0}; 719 720 regs->version = 0; 721 memset(p, 0, regs->len); 722 723 if (!netif_running(bp->dev)) 724 return; 725 726 /* Disable parity attentions as long as following dump may 727 * cause false alarms by reading never written registers. We 728 * will re-enable parity attentions right after the dump. 729 */ 730 bnx2x_disable_blocks_parity(bp); 731 732 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1; 733 dump_hdr.dump_sign = dump_sign_all; 734 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR); 735 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR); 736 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR); 737 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR); 738 739 if (CHIP_IS_E1(bp)) 740 dump_hdr.info = RI_E1_ONLINE; 741 else if (CHIP_IS_E1H(bp)) 742 dump_hdr.info = RI_E1H_ONLINE; 743 else if (!CHIP_IS_E1x(bp)) 744 dump_hdr.info = RI_E2_ONLINE | 745 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP); 746 747 memcpy(p, &dump_hdr, sizeof(struct dump_hdr)); 748 p += dump_hdr.hdr_size + 1; 749 750 /* Actually read the registers */ 751 __bnx2x_get_regs(bp, p); 752 753 /* Re-enable parity attentions */ 754 bnx2x_clear_blocks_parity(bp); 755 bnx2x_enable_blocks_parity(bp); 756} 757 758static void bnx2x_get_drvinfo(struct net_device *dev, 759 struct ethtool_drvinfo *info) 760{ 761 struct bnx2x *bp = netdev_priv(dev); 762 u8 phy_fw_ver[PHY_FW_VER_LEN]; 763 764 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 765 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 766 767 phy_fw_ver[0] = '\0'; 768 if (bp->port.pmf) { 769 bnx2x_acquire_phy_lock(bp); 770 bnx2x_get_ext_phy_fw_version(&bp->link_params, 771 (bp->state != BNX2X_STATE_CLOSED), 772 phy_fw_ver, PHY_FW_VER_LEN); 773 bnx2x_release_phy_lock(bp); 774 } 775 776 strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version)); 777 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver), 778 "bc %d.%d.%d%s%s", 779 (bp->common.bc_ver & 0xff0000) >> 16, 780 (bp->common.bc_ver & 0xff00) >> 8, 781 (bp->common.bc_ver & 0xff), 782 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver); 783 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 784 info->n_stats = BNX2X_NUM_STATS; 785 info->testinfo_len = BNX2X_NUM_TESTS; 786 info->eedump_len = bp->common.flash_size; 787 info->regdump_len = bnx2x_get_regs_len(dev); 788} 789 790static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 791{ 792 struct bnx2x *bp = netdev_priv(dev); 793 794 if (bp->flags & NO_WOL_FLAG) { 795 wol->supported = 0; 796 wol->wolopts = 0; 797 } else { 798 wol->supported = WAKE_MAGIC; 799 if (bp->wol) 800 wol->wolopts = WAKE_MAGIC; 801 else 802 wol->wolopts = 0; 803 } 804 memset(&wol->sopass, 0, sizeof(wol->sopass)); 805} 806 807static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 808{ 809 struct bnx2x *bp = netdev_priv(dev); 810 811 if (wol->wolopts & ~WAKE_MAGIC) 812 return -EINVAL; 813 814 if (wol->wolopts & WAKE_MAGIC) { 815 if (bp->flags & NO_WOL_FLAG) 816 return -EINVAL; 817 818 bp->wol = 1; 819 } else 820 bp->wol = 0; 821 822 return 0; 823} 824 825static u32 bnx2x_get_msglevel(struct net_device *dev) 826{ 827 struct bnx2x *bp = netdev_priv(dev); 828 829 return bp->msg_enable; 830} 831 832static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 833{ 834 struct bnx2x *bp = netdev_priv(dev); 835 836 if (capable(CAP_NET_ADMIN)) { 837 /* dump MCP trace */ 838 if (level & BNX2X_MSG_MCP) 839 bnx2x_fw_dump_lvl(bp, KERN_INFO); 840 bp->msg_enable = level; 841 } 842} 843 844static int bnx2x_nway_reset(struct net_device *dev) 845{ 846 struct bnx2x *bp = netdev_priv(dev); 847 848 if (!bp->port.pmf) 849 return 0; 850 851 if (netif_running(dev)) { 852 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 853 bnx2x_link_set(bp); 854 } 855 856 return 0; 857} 858 859static u32 bnx2x_get_link(struct net_device *dev) 860{ 861 struct bnx2x *bp = netdev_priv(dev); 862 863 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 864 return 0; 865 866 return bp->link_vars.link_up; 867} 868 869static int bnx2x_get_eeprom_len(struct net_device *dev) 870{ 871 struct bnx2x *bp = netdev_priv(dev); 872 873 return bp->common.flash_size; 874} 875 876static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 877{ 878 int port = BP_PORT(bp); 879 int count, i; 880 u32 val = 0; 881 882 /* adjust timeout for emulation/FPGA */ 883 count = BNX2X_NVRAM_TIMEOUT_COUNT; 884 if (CHIP_REV_IS_SLOW(bp)) 885 count *= 100; 886 887 /* request access to nvram interface */ 888 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 889 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 890 891 for (i = 0; i < count*10; i++) { 892 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 893 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 894 break; 895 896 udelay(5); 897 } 898 899 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 900 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n"); 901 return -EBUSY; 902 } 903 904 return 0; 905} 906 907static int bnx2x_release_nvram_lock(struct bnx2x *bp) 908{ 909 int port = BP_PORT(bp); 910 int count, i; 911 u32 val = 0; 912 913 /* adjust timeout for emulation/FPGA */ 914 count = BNX2X_NVRAM_TIMEOUT_COUNT; 915 if (CHIP_REV_IS_SLOW(bp)) 916 count *= 100; 917 918 /* relinquish nvram interface */ 919 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 920 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 921 922 for (i = 0; i < count*10; i++) { 923 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 924 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 925 break; 926 927 udelay(5); 928 } 929 930 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 931 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n"); 932 return -EBUSY; 933 } 934 935 return 0; 936} 937 938static void bnx2x_enable_nvram_access(struct bnx2x *bp) 939{ 940 u32 val; 941 942 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 943 944 /* enable both bits, even on read */ 945 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 946 (val | MCPR_NVM_ACCESS_ENABLE_EN | 947 MCPR_NVM_ACCESS_ENABLE_WR_EN)); 948} 949 950static void bnx2x_disable_nvram_access(struct bnx2x *bp) 951{ 952 u32 val; 953 954 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 955 956 /* disable both bits, even after read */ 957 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 958 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 959 MCPR_NVM_ACCESS_ENABLE_WR_EN))); 960} 961 962static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 963 u32 cmd_flags) 964{ 965 int count, i, rc; 966 u32 val; 967 968 /* build the command word */ 969 cmd_flags |= MCPR_NVM_COMMAND_DOIT; 970 971 /* need to clear DONE bit separately */ 972 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 973 974 /* address of the NVRAM to read from */ 975 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 976 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 977 978 /* issue a read command */ 979 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 980 981 /* adjust timeout for emulation/FPGA */ 982 count = BNX2X_NVRAM_TIMEOUT_COUNT; 983 if (CHIP_REV_IS_SLOW(bp)) 984 count *= 100; 985 986 /* wait for completion */ 987 *ret_val = 0; 988 rc = -EBUSY; 989 for (i = 0; i < count; i++) { 990 udelay(5); 991 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 992 993 if (val & MCPR_NVM_COMMAND_DONE) { 994 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 995 /* we read nvram data in cpu order 996 * but ethtool sees it as an array of bytes 997 * converting to big-endian will do the work */ 998 *ret_val = cpu_to_be32(val); 999 rc = 0; 1000 break; 1001 } 1002 } 1003 1004 return rc; 1005} 1006 1007static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1008 int buf_size) 1009{ 1010 int rc; 1011 u32 cmd_flags; 1012 __be32 val; 1013 1014 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1015 DP(BNX2X_MSG_NVM, 1016 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1017 offset, buf_size); 1018 return -EINVAL; 1019 } 1020 1021 if (offset + buf_size > bp->common.flash_size) { 1022 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +" 1023 " buf_size (0x%x) > flash_size (0x%x)\n", 1024 offset, buf_size, bp->common.flash_size); 1025 return -EINVAL; 1026 } 1027 1028 /* request access to nvram interface */ 1029 rc = bnx2x_acquire_nvram_lock(bp); 1030 if (rc) 1031 return rc; 1032 1033 /* enable access to nvram interface */ 1034 bnx2x_enable_nvram_access(bp); 1035 1036 /* read the first word(s) */ 1037 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1038 while ((buf_size > sizeof(u32)) && (rc == 0)) { 1039 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1040 memcpy(ret_buf, &val, 4); 1041 1042 /* advance to the next dword */ 1043 offset += sizeof(u32); 1044 ret_buf += sizeof(u32); 1045 buf_size -= sizeof(u32); 1046 cmd_flags = 0; 1047 } 1048 1049 if (rc == 0) { 1050 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1051 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1052 memcpy(ret_buf, &val, 4); 1053 } 1054 1055 /* disable access to nvram interface */ 1056 bnx2x_disable_nvram_access(bp); 1057 bnx2x_release_nvram_lock(bp); 1058 1059 return rc; 1060} 1061 1062static int bnx2x_get_eeprom(struct net_device *dev, 1063 struct ethtool_eeprom *eeprom, u8 *eebuf) 1064{ 1065 struct bnx2x *bp = netdev_priv(dev); 1066 int rc; 1067 1068 if (!netif_running(dev)) 1069 return -EAGAIN; 1070 1071 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1072 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1073 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1074 eeprom->len, eeprom->len); 1075 1076 /* parameters already validated in ethtool_get_eeprom */ 1077 1078 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1079 1080 return rc; 1081} 1082 1083static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1084 u32 cmd_flags) 1085{ 1086 int count, i, rc; 1087 1088 /* build the command word */ 1089 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1090 1091 /* need to clear DONE bit separately */ 1092 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1093 1094 /* write the data */ 1095 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1096 1097 /* address of the NVRAM to write to */ 1098 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1099 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1100 1101 /* issue the write command */ 1102 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1103 1104 /* adjust timeout for emulation/FPGA */ 1105 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1106 if (CHIP_REV_IS_SLOW(bp)) 1107 count *= 100; 1108 1109 /* wait for completion */ 1110 rc = -EBUSY; 1111 for (i = 0; i < count; i++) { 1112 udelay(5); 1113 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1114 if (val & MCPR_NVM_COMMAND_DONE) { 1115 rc = 0; 1116 break; 1117 } 1118 } 1119 1120 return rc; 1121} 1122 1123#define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1124 1125static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1126 int buf_size) 1127{ 1128 int rc; 1129 u32 cmd_flags; 1130 u32 align_offset; 1131 __be32 val; 1132 1133 if (offset + buf_size > bp->common.flash_size) { 1134 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +" 1135 " buf_size (0x%x) > flash_size (0x%x)\n", 1136 offset, buf_size, bp->common.flash_size); 1137 return -EINVAL; 1138 } 1139 1140 /* request access to nvram interface */ 1141 rc = bnx2x_acquire_nvram_lock(bp); 1142 if (rc) 1143 return rc; 1144 1145 /* enable access to nvram interface */ 1146 bnx2x_enable_nvram_access(bp); 1147 1148 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1149 align_offset = (offset & ~0x03); 1150 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags); 1151 1152 if (rc == 0) { 1153 val &= ~(0xff << BYTE_OFFSET(offset)); 1154 val |= (*data_buf << BYTE_OFFSET(offset)); 1155 1156 /* nvram data is returned as an array of bytes 1157 * convert it back to cpu order */ 1158 val = be32_to_cpu(val); 1159 1160 rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1161 cmd_flags); 1162 } 1163 1164 /* disable access to nvram interface */ 1165 bnx2x_disable_nvram_access(bp); 1166 bnx2x_release_nvram_lock(bp); 1167 1168 return rc; 1169} 1170 1171static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1172 int buf_size) 1173{ 1174 int rc; 1175 u32 cmd_flags; 1176 u32 val; 1177 u32 written_so_far; 1178 1179 if (buf_size == 1) /* ethtool */ 1180 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1181 1182 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1183 DP(BNX2X_MSG_NVM, 1184 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1185 offset, buf_size); 1186 return -EINVAL; 1187 } 1188 1189 if (offset + buf_size > bp->common.flash_size) { 1190 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +" 1191 " buf_size (0x%x) > flash_size (0x%x)\n", 1192 offset, buf_size, bp->common.flash_size); 1193 return -EINVAL; 1194 } 1195 1196 /* request access to nvram interface */ 1197 rc = bnx2x_acquire_nvram_lock(bp); 1198 if (rc) 1199 return rc; 1200 1201 /* enable access to nvram interface */ 1202 bnx2x_enable_nvram_access(bp); 1203 1204 written_so_far = 0; 1205 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1206 while ((written_so_far < buf_size) && (rc == 0)) { 1207 if (written_so_far == (buf_size - sizeof(u32))) 1208 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1209 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1210 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1211 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1212 cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1213 1214 memcpy(&val, data_buf, 4); 1215 1216 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1217 1218 /* advance to the next dword */ 1219 offset += sizeof(u32); 1220 data_buf += sizeof(u32); 1221 written_so_far += sizeof(u32); 1222 cmd_flags = 0; 1223 } 1224 1225 /* disable access to nvram interface */ 1226 bnx2x_disable_nvram_access(bp); 1227 bnx2x_release_nvram_lock(bp); 1228 1229 return rc; 1230} 1231 1232static int bnx2x_set_eeprom(struct net_device *dev, 1233 struct ethtool_eeprom *eeprom, u8 *eebuf) 1234{ 1235 struct bnx2x *bp = netdev_priv(dev); 1236 int port = BP_PORT(bp); 1237 int rc = 0; 1238 u32 ext_phy_config; 1239 if (!netif_running(dev)) 1240 return -EAGAIN; 1241 1242 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1243 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1244 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1245 eeprom->len, eeprom->len); 1246 1247 /* parameters already validated in ethtool_set_eeprom */ 1248 1249 /* PHY eeprom can be accessed only by the PMF */ 1250 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 1251 !bp->port.pmf) 1252 return -EINVAL; 1253 1254 ext_phy_config = 1255 SHMEM_RD(bp, 1256 dev_info.port_hw_config[port].external_phy_config); 1257 1258 if (eeprom->magic == 0x50485950) { 1259 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1260 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1261 1262 bnx2x_acquire_phy_lock(bp); 1263 rc |= bnx2x_link_reset(&bp->link_params, 1264 &bp->link_vars, 0); 1265 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1266 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1267 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1268 MISC_REGISTERS_GPIO_HIGH, port); 1269 bnx2x_release_phy_lock(bp); 1270 bnx2x_link_report(bp); 1271 1272 } else if (eeprom->magic == 0x50485952) { 1273 /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1274 if (bp->state == BNX2X_STATE_OPEN) { 1275 bnx2x_acquire_phy_lock(bp); 1276 rc |= bnx2x_link_reset(&bp->link_params, 1277 &bp->link_vars, 1); 1278 1279 rc |= bnx2x_phy_init(&bp->link_params, 1280 &bp->link_vars); 1281 bnx2x_release_phy_lock(bp); 1282 bnx2x_calc_fc_adv(bp); 1283 } 1284 } else if (eeprom->magic == 0x53985943) { 1285 /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1286 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1287 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1288 1289 /* DSP Remove Download Mode */ 1290 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1291 MISC_REGISTERS_GPIO_LOW, port); 1292 1293 bnx2x_acquire_phy_lock(bp); 1294 1295 bnx2x_sfx7101_sp_sw_reset(bp, 1296 &bp->link_params.phy[EXT_PHY1]); 1297 1298 /* wait 0.5 sec to allow it to run */ 1299 msleep(500); 1300 bnx2x_ext_phy_hw_reset(bp, port); 1301 msleep(500); 1302 bnx2x_release_phy_lock(bp); 1303 } 1304 } else 1305 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1306 1307 return rc; 1308} 1309 1310static int bnx2x_get_coalesce(struct net_device *dev, 1311 struct ethtool_coalesce *coal) 1312{ 1313 struct bnx2x *bp = netdev_priv(dev); 1314 1315 memset(coal, 0, sizeof(struct ethtool_coalesce)); 1316 1317 coal->rx_coalesce_usecs = bp->rx_ticks; 1318 coal->tx_coalesce_usecs = bp->tx_ticks; 1319 1320 return 0; 1321} 1322 1323static int bnx2x_set_coalesce(struct net_device *dev, 1324 struct ethtool_coalesce *coal) 1325{ 1326 struct bnx2x *bp = netdev_priv(dev); 1327 1328 bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1329 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1330 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1331 1332 bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1333 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1334 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1335 1336 if (netif_running(dev)) 1337 bnx2x_update_coalesce(bp); 1338 1339 return 0; 1340} 1341 1342static void bnx2x_get_ringparam(struct net_device *dev, 1343 struct ethtool_ringparam *ering) 1344{ 1345 struct bnx2x *bp = netdev_priv(dev); 1346 1347 ering->rx_max_pending = MAX_RX_AVAIL; 1348 1349 if (bp->rx_ring_size) 1350 ering->rx_pending = bp->rx_ring_size; 1351 else 1352 ering->rx_pending = MAX_RX_AVAIL; 1353 1354 ering->tx_max_pending = MAX_TX_AVAIL; 1355 ering->tx_pending = bp->tx_ring_size; 1356} 1357 1358static int bnx2x_set_ringparam(struct net_device *dev, 1359 struct ethtool_ringparam *ering) 1360{ 1361 struct bnx2x *bp = netdev_priv(dev); 1362 1363 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 1364 pr_err("Handling parity error recovery. Try again later\n"); 1365 return -EAGAIN; 1366 } 1367 1368 if ((ering->rx_pending > MAX_RX_AVAIL) || 1369 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1370 MIN_RX_SIZE_TPA)) || 1371 (ering->tx_pending > MAX_TX_AVAIL) || 1372 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) 1373 return -EINVAL; 1374 1375 bp->rx_ring_size = ering->rx_pending; 1376 bp->tx_ring_size = ering->tx_pending; 1377 1378 return bnx2x_reload_if_running(dev); 1379} 1380 1381static void bnx2x_get_pauseparam(struct net_device *dev, 1382 struct ethtool_pauseparam *epause) 1383{ 1384 struct bnx2x *bp = netdev_priv(dev); 1385 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 1386 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1387 BNX2X_FLOW_CTRL_AUTO); 1388 1389 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) == 1390 BNX2X_FLOW_CTRL_RX); 1391 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) == 1392 BNX2X_FLOW_CTRL_TX); 1393 1394 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n" 1395 " autoneg %d rx_pause %d tx_pause %d\n", 1396 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1397} 1398 1399static int bnx2x_set_pauseparam(struct net_device *dev, 1400 struct ethtool_pauseparam *epause) 1401{ 1402 struct bnx2x *bp = netdev_priv(dev); 1403 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1404 if (IS_MF(bp)) 1405 return 0; 1406 1407 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n" 1408 " autoneg %d rx_pause %d tx_pause %d\n", 1409 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1410 1411 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 1412 1413 if (epause->rx_pause) 1414 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 1415 1416 if (epause->tx_pause) 1417 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 1418 1419 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 1420 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 1421 1422 if (epause->autoneg) { 1423 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 1424 DP(NETIF_MSG_LINK, "autoneg not supported\n"); 1425 return -EINVAL; 1426 } 1427 1428 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 1429 bp->link_params.req_flow_ctrl[cfg_idx] = 1430 BNX2X_FLOW_CTRL_AUTO; 1431 } 1432 } 1433 1434 DP(NETIF_MSG_LINK, 1435 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1436 1437 if (netif_running(dev)) { 1438 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1439 bnx2x_link_set(bp); 1440 } 1441 1442 return 0; 1443} 1444 1445static const struct { 1446 char string[ETH_GSTRING_LEN]; 1447} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = { 1448 { "register_test (offline)" }, 1449 { "memory_test (offline)" }, 1450 { "loopback_test (offline)" }, 1451 { "nvram_test (online)" }, 1452 { "interrupt_test (online)" }, 1453 { "link_test (online)" }, 1454 { "idle check (online)" } 1455}; 1456 1457enum { 1458 BNX2X_CHIP_E1_OFST = 0, 1459 BNX2X_CHIP_E1H_OFST, 1460 BNX2X_CHIP_E2_OFST, 1461 BNX2X_CHIP_E3_OFST, 1462 BNX2X_CHIP_E3B0_OFST, 1463 BNX2X_CHIP_MAX_OFST 1464}; 1465 1466#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 1467#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 1468#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 1469#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 1470#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 1471 1472#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 1473#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 1474 1475static int bnx2x_test_registers(struct bnx2x *bp) 1476{ 1477 int idx, i, rc = -ENODEV; 1478 u32 wr_val = 0, hw; 1479 int port = BP_PORT(bp); 1480 static const struct { 1481 u32 hw; 1482 u32 offset0; 1483 u32 offset1; 1484 u32 mask; 1485 } reg_tbl[] = { 1486/* 0 */ { BNX2X_CHIP_MASK_ALL, 1487 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 1488 { BNX2X_CHIP_MASK_ALL, 1489 DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 1490 { BNX2X_CHIP_MASK_E1X, 1491 HC_REG_AGG_INT_0, 4, 0x000003ff }, 1492 { BNX2X_CHIP_MASK_ALL, 1493 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 1494 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 1495 PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 1496 { BNX2X_CHIP_MASK_E3B0, 1497 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 1498 { BNX2X_CHIP_MASK_ALL, 1499 PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 1500 { BNX2X_CHIP_MASK_ALL, 1501 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 1502 { BNX2X_CHIP_MASK_ALL, 1503 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 1504 { BNX2X_CHIP_MASK_ALL, 1505 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 1506/* 10 */ { BNX2X_CHIP_MASK_ALL, 1507 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 1508 { BNX2X_CHIP_MASK_ALL, 1509 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 1510 { BNX2X_CHIP_MASK_ALL, 1511 QM_REG_CONNNUM_0, 4, 0x000fffff }, 1512 { BNX2X_CHIP_MASK_ALL, 1513 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 1514 { BNX2X_CHIP_MASK_ALL, 1515 SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 1516 { BNX2X_CHIP_MASK_ALL, 1517 SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 1518 { BNX2X_CHIP_MASK_ALL, 1519 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 1520 { BNX2X_CHIP_MASK_ALL, 1521 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 1522 { BNX2X_CHIP_MASK_ALL, 1523 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 1524 { BNX2X_CHIP_MASK_ALL, 1525 NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 1526/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1527 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 1528 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1529 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 1530 { BNX2X_CHIP_MASK_ALL, 1531 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 1532 { BNX2X_CHIP_MASK_ALL, 1533 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 1534 { BNX2X_CHIP_MASK_ALL, 1535 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 1536 { BNX2X_CHIP_MASK_ALL, 1537 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 1538 { BNX2X_CHIP_MASK_ALL, 1539 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 1540 { BNX2X_CHIP_MASK_ALL, 1541 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 1542 { BNX2X_CHIP_MASK_ALL, 1543 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 1544 { BNX2X_CHIP_MASK_ALL, 1545 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 1546/* 30 */ { BNX2X_CHIP_MASK_ALL, 1547 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 1548 { BNX2X_CHIP_MASK_ALL, 1549 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 1550 { BNX2X_CHIP_MASK_ALL, 1551 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 1552 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1553 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 1554 { BNX2X_CHIP_MASK_ALL, 1555 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 1556 { BNX2X_CHIP_MASK_ALL, 1557 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 1558 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1559 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 1560 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1561 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 1562 1563 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 1564 }; 1565 1566 if (!netif_running(bp->dev)) 1567 return rc; 1568 1569 if (CHIP_IS_E1(bp)) 1570 hw = BNX2X_CHIP_MASK_E1; 1571 else if (CHIP_IS_E1H(bp)) 1572 hw = BNX2X_CHIP_MASK_E1H; 1573 else if (CHIP_IS_E2(bp)) 1574 hw = BNX2X_CHIP_MASK_E2; 1575 else if (CHIP_IS_E3B0(bp)) 1576 hw = BNX2X_CHIP_MASK_E3B0; 1577 else /* e3 A0 */ 1578 hw = BNX2X_CHIP_MASK_E3; 1579 1580 /* Repeat the test twice: 1581 First by writing 0x00000000, second by writing 0xffffffff */ 1582 for (idx = 0; idx < 2; idx++) { 1583 1584 switch (idx) { 1585 case 0: 1586 wr_val = 0; 1587 break; 1588 case 1: 1589 wr_val = 0xffffffff; 1590 break; 1591 } 1592 1593 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 1594 u32 offset, mask, save_val, val; 1595 if (!(hw & reg_tbl[i].hw)) 1596 continue; 1597 1598 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 1599 mask = reg_tbl[i].mask; 1600 1601 save_val = REG_RD(bp, offset); 1602 1603 REG_WR(bp, offset, wr_val & mask); 1604 1605 val = REG_RD(bp, offset); 1606 1607 /* Restore the original register's value */ 1608 REG_WR(bp, offset, save_val); 1609 1610 /* verify value is as expected */ 1611 if ((val & mask) != (wr_val & mask)) { 1612 DP(NETIF_MSG_HW, 1613 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 1614 offset, val, wr_val, mask); 1615 goto test_reg_exit; 1616 } 1617 } 1618 } 1619 1620 rc = 0; 1621 1622test_reg_exit: 1623 return rc; 1624} 1625 1626static int bnx2x_test_memory(struct bnx2x *bp) 1627{ 1628 int i, j, rc = -ENODEV; 1629 u32 val, index; 1630 static const struct { 1631 u32 offset; 1632 int size; 1633 } mem_tbl[] = { 1634 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 1635 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 1636 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 1637 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 1638 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 1639 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 1640 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 1641 1642 { 0xffffffff, 0 } 1643 }; 1644 1645 static const struct { 1646 char *name; 1647 u32 offset; 1648 u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 1649 } prty_tbl[] = { 1650 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 1651 {0x3ffc0, 0, 0, 0} }, 1652 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 1653 {0x2, 0x2, 0, 0} }, 1654 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 1655 {0, 0, 0, 0} }, 1656 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 1657 {0x3ffc0, 0, 0, 0} }, 1658 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 1659 {0x3ffc0, 0, 0, 0} }, 1660 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 1661 {0x3ffc1, 0, 0, 0} }, 1662 1663 { NULL, 0xffffffff, {0, 0, 0, 0} } 1664 }; 1665 1666 if (!netif_running(bp->dev)) 1667 return rc; 1668 1669 if (CHIP_IS_E1(bp)) 1670 index = BNX2X_CHIP_E1_OFST; 1671 else if (CHIP_IS_E1H(bp)) 1672 index = BNX2X_CHIP_E1H_OFST; 1673 else if (CHIP_IS_E2(bp)) 1674 index = BNX2X_CHIP_E2_OFST; 1675 else /* e3 */ 1676 index = BNX2X_CHIP_E3_OFST; 1677 1678 /* pre-Check the parity status */ 1679 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 1680 val = REG_RD(bp, prty_tbl[i].offset); 1681 if (val & ~(prty_tbl[i].hw_mask[index])) { 1682 DP(NETIF_MSG_HW, 1683 "%s is 0x%x\n", prty_tbl[i].name, val); 1684 goto test_mem_exit; 1685 } 1686 } 1687 1688 /* Go through all the memories */ 1689 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 1690 for (j = 0; j < mem_tbl[i].size; j++) 1691 REG_RD(bp, mem_tbl[i].offset + j*4); 1692 1693 /* Check the parity status */ 1694 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 1695 val = REG_RD(bp, prty_tbl[i].offset); 1696 if (val & ~(prty_tbl[i].hw_mask[index])) { 1697 DP(NETIF_MSG_HW, 1698 "%s is 0x%x\n", prty_tbl[i].name, val); 1699 goto test_mem_exit; 1700 } 1701 } 1702 1703 rc = 0; 1704 1705test_mem_exit: 1706 return rc; 1707} 1708 1709static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 1710{ 1711 int cnt = 1400; 1712 1713 if (link_up) { 1714 while (bnx2x_link_test(bp, is_serdes) && cnt--) 1715 msleep(20); 1716 1717 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 1718 DP(NETIF_MSG_LINK, "Timeout waiting for link up\n"); 1719 } 1720} 1721 1722static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 1723{ 1724 unsigned int pkt_size, num_pkts, i; 1725 struct sk_buff *skb; 1726 unsigned char *packet; 1727 struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 1728 struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 1729 struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0]; 1730 u16 tx_start_idx, tx_idx; 1731 u16 rx_start_idx, rx_idx; 1732 u16 pkt_prod, bd_prod, rx_comp_cons; 1733 struct sw_tx_bd *tx_buf; 1734 struct eth_tx_start_bd *tx_start_bd; 1735 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL; 1736 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL; 1737 dma_addr_t mapping; 1738 union eth_rx_cqe *cqe; 1739 u8 cqe_fp_flags, cqe_fp_type; 1740 struct sw_rx_bd *rx_buf; 1741 u16 len; 1742 int rc = -ENODEV; 1743 u8 *data; 1744 1745 /* check the loopback mode */ 1746 switch (loopback_mode) { 1747 case BNX2X_PHY_LOOPBACK: 1748 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) 1749 return -EINVAL; 1750 break; 1751 case BNX2X_MAC_LOOPBACK: 1752 bp->link_params.loopback_mode = CHIP_IS_E3(bp) ? 1753 LOOPBACK_XMAC : LOOPBACK_BMAC; 1754 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 1755 break; 1756 default: 1757 return -EINVAL; 1758 } 1759 1760 /* prepare the loopback packet */ 1761 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 1762 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 1763 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 1764 if (!skb) { 1765 rc = -ENOMEM; 1766 goto test_loopback_exit; 1767 } 1768 packet = skb_put(skb, pkt_size); 1769 memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 1770 memset(packet + ETH_ALEN, 0, ETH_ALEN); 1771 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 1772 for (i = ETH_HLEN; i < pkt_size; i++) 1773 packet[i] = (unsigned char) (i & 0xff); 1774 mapping = dma_map_single(&bp->pdev->dev, skb->data, 1775 skb_headlen(skb), DMA_TO_DEVICE); 1776 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 1777 rc = -ENOMEM; 1778 dev_kfree_skb(skb); 1779 BNX2X_ERR("Unable to map SKB\n"); 1780 goto test_loopback_exit; 1781 } 1782 1783 /* send the loopback packet */ 1784 num_pkts = 0; 1785 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 1786 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 1787 1788 pkt_prod = txdata->tx_pkt_prod++; 1789 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 1790 tx_buf->first_bd = txdata->tx_bd_prod; 1791 tx_buf->skb = skb; 1792 tx_buf->flags = 0; 1793 1794 bd_prod = TX_BD(txdata->tx_bd_prod); 1795 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 1796 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 1797 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 1798 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 1799 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 1800 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 1801 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 1802 SET_FLAG(tx_start_bd->general_data, 1803 ETH_TX_START_BD_ETH_ADDR_TYPE, 1804 UNICAST_ADDRESS); 1805 SET_FLAG(tx_start_bd->general_data, 1806 ETH_TX_START_BD_HDR_NBDS, 1807 1); 1808 1809 /* turn on parsing and get a BD */ 1810 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 1811 1812 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 1813 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 1814 1815 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 1816 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 1817 1818 wmb(); 1819 1820 txdata->tx_db.data.prod += 2; 1821 barrier(); 1822 DOORBELL(bp, txdata->cid, txdata->tx_db.raw); 1823 1824 mmiowb(); 1825 barrier(); 1826 1827 num_pkts++; 1828 txdata->tx_bd_prod += 2; /* start + pbd */ 1829 1830 udelay(100); 1831 1832 tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 1833 if (tx_idx != tx_start_idx + num_pkts) 1834 goto test_loopback_exit; 1835 1836 /* Unlike HC IGU won't generate an interrupt for status block 1837 * updates that have been performed while interrupts were 1838 * disabled. 1839 */ 1840 if (bp->common.int_block == INT_BLOCK_IGU) { 1841 /* Disable local BHes to prevent a dead-lock situation between 1842 * sch_direct_xmit() and bnx2x_run_loopback() (calling 1843 * bnx2x_tx_int()), as both are taking netif_tx_lock(). 1844 */ 1845 local_bh_disable(); 1846 bnx2x_tx_int(bp, txdata); 1847 local_bh_enable(); 1848 } 1849 1850 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 1851 if (rx_idx != rx_start_idx + num_pkts) 1852 goto test_loopback_exit; 1853 1854 rx_comp_cons = le16_to_cpu(fp_rx->rx_comp_cons); 1855 cqe = &fp_rx->rx_comp_ring[RCQ_BD(rx_comp_cons)]; 1856 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 1857 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 1858 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 1859 goto test_loopback_rx_exit; 1860 1861 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len); 1862 if (len != pkt_size) 1863 goto test_loopback_rx_exit; 1864 1865 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 1866 dma_sync_single_for_cpu(&bp->pdev->dev, 1867 dma_unmap_addr(rx_buf, mapping), 1868 fp_rx->rx_buf_size, DMA_FROM_DEVICE); 1869 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 1870 for (i = ETH_HLEN; i < pkt_size; i++) 1871 if (*(data + i) != (unsigned char) (i & 0xff)) 1872 goto test_loopback_rx_exit; 1873 1874 rc = 0; 1875 1876test_loopback_rx_exit: 1877 1878 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 1879 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 1880 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 1881 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 1882 1883 /* Update producers */ 1884 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 1885 fp_rx->rx_sge_prod); 1886 1887test_loopback_exit: 1888 bp->link_params.loopback_mode = LOOPBACK_NONE; 1889 1890 return rc; 1891} 1892 1893static int bnx2x_test_loopback(struct bnx2x *bp) 1894{ 1895 int rc = 0, res; 1896 1897 if (BP_NOMCP(bp)) 1898 return rc; 1899 1900 if (!netif_running(bp->dev)) 1901 return BNX2X_LOOPBACK_FAILED; 1902 1903 bnx2x_netif_stop(bp, 1); 1904 bnx2x_acquire_phy_lock(bp); 1905 1906 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 1907 if (res) { 1908 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res); 1909 rc |= BNX2X_PHY_LOOPBACK_FAILED; 1910 } 1911 1912 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 1913 if (res) { 1914 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res); 1915 rc |= BNX2X_MAC_LOOPBACK_FAILED; 1916 } 1917 1918 bnx2x_release_phy_lock(bp); 1919 bnx2x_netif_start(bp); 1920 1921 return rc; 1922} 1923 1924#define CRC32_RESIDUAL 0xdebb20e3 1925 1926static int bnx2x_test_nvram(struct bnx2x *bp) 1927{ 1928 static const struct { 1929 int offset; 1930 int size; 1931 } nvram_tbl[] = { 1932 { 0, 0x14 }, /* bootstrap */ 1933 { 0x14, 0xec }, /* dir */ 1934 { 0x100, 0x350 }, /* manuf_info */ 1935 { 0x450, 0xf0 }, /* feature_info */ 1936 { 0x640, 0x64 }, /* upgrade_key_info */ 1937 { 0x708, 0x70 }, /* manuf_key_info */ 1938 { 0, 0 } 1939 }; 1940 __be32 buf[0x350 / 4]; 1941 u8 *data = (u8 *)buf; 1942 int i, rc; 1943 u32 magic, crc; 1944 1945 if (BP_NOMCP(bp)) 1946 return 0; 1947 1948 rc = bnx2x_nvram_read(bp, 0, data, 4); 1949 if (rc) { 1950 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc); 1951 goto test_nvram_exit; 1952 } 1953 1954 magic = be32_to_cpu(buf[0]); 1955 if (magic != 0x669955aa) { 1956 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic); 1957 rc = -ENODEV; 1958 goto test_nvram_exit; 1959 } 1960 1961 for (i = 0; nvram_tbl[i].size; i++) { 1962 1963 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data, 1964 nvram_tbl[i].size); 1965 if (rc) { 1966 DP(NETIF_MSG_PROBE, 1967 "nvram_tbl[%d] read data (rc %d)\n", i, rc); 1968 goto test_nvram_exit; 1969 } 1970 1971 crc = ether_crc_le(nvram_tbl[i].size, data); 1972 if (crc != CRC32_RESIDUAL) { 1973 DP(NETIF_MSG_PROBE, 1974 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc); 1975 rc = -ENODEV; 1976 goto test_nvram_exit; 1977 } 1978 } 1979 1980test_nvram_exit: 1981 return rc; 1982} 1983 1984/* Send an EMPTY ramrod on the first queue */ 1985static int bnx2x_test_intr(struct bnx2x *bp) 1986{ 1987 struct bnx2x_queue_state_params params = {0}; 1988 1989 if (!netif_running(bp->dev)) 1990 return -ENODEV; 1991 1992 params.q_obj = &bp->fp->q_obj; 1993 params.cmd = BNX2X_Q_CMD_EMPTY; 1994 1995 __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 1996 1997 return bnx2x_queue_state_change(bp, ¶ms); 1998} 1999 2000static void bnx2x_self_test(struct net_device *dev, 2001 struct ethtool_test *etest, u64 *buf) 2002{ 2003 struct bnx2x *bp = netdev_priv(dev); 2004 u8 is_serdes; 2005 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 2006 pr_err("Handling parity error recovery. Try again later\n"); 2007 etest->flags |= ETH_TEST_FL_FAILED; 2008 return; 2009 } 2010 2011 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS); 2012 2013 if (!netif_running(dev)) 2014 return; 2015 2016 /* offline tests are not supported in MF mode */ 2017 if (IS_MF(bp)) 2018 etest->flags &= ~ETH_TEST_FL_OFFLINE; 2019 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2020 2021 if (etest->flags & ETH_TEST_FL_OFFLINE) { 2022 int port = BP_PORT(bp); 2023 u32 val; 2024 u8 link_up; 2025 2026 /* save current value of input enable for TX port IF */ 2027 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 2028 /* disable input for TX port IF */ 2029 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 2030 2031 link_up = bp->link_vars.link_up; 2032 2033 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 2034 bnx2x_nic_load(bp, LOAD_DIAG); 2035 /* wait until link state is restored */ 2036 bnx2x_wait_for_link(bp, 1, is_serdes); 2037 2038 if (bnx2x_test_registers(bp) != 0) { 2039 buf[0] = 1; 2040 etest->flags |= ETH_TEST_FL_FAILED; 2041 } 2042 if (bnx2x_test_memory(bp) != 0) { 2043 buf[1] = 1; 2044 etest->flags |= ETH_TEST_FL_FAILED; 2045 } 2046 2047 buf[2] = bnx2x_test_loopback(bp); 2048 if (buf[2] != 0) 2049 etest->flags |= ETH_TEST_FL_FAILED; 2050 2051 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 2052 2053 /* restore input for TX port IF */ 2054 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 2055 2056 bnx2x_nic_load(bp, LOAD_NORMAL); 2057 /* wait until link state is restored */ 2058 bnx2x_wait_for_link(bp, link_up, is_serdes); 2059 } 2060 if (bnx2x_test_nvram(bp) != 0) { 2061 buf[3] = 1; 2062 etest->flags |= ETH_TEST_FL_FAILED; 2063 } 2064 if (bnx2x_test_intr(bp) != 0) { 2065 buf[4] = 1; 2066 etest->flags |= ETH_TEST_FL_FAILED; 2067 } 2068 2069 if (bnx2x_link_test(bp, is_serdes) != 0) { 2070 buf[5] = 1; 2071 etest->flags |= ETH_TEST_FL_FAILED; 2072 } 2073 2074#ifdef BNX2X_EXTRA_DEBUG 2075 bnx2x_panic_dump(bp); 2076#endif 2077} 2078 2079#define IS_PORT_STAT(i) \ 2080 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) 2081#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) 2082#define IS_MF_MODE_STAT(bp) \ 2083 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) 2084 2085/* ethtool statistics are displayed for all regular ethernet queues and the 2086 * fcoe L2 queue if not disabled 2087 */ 2088static inline int bnx2x_num_stat_queues(struct bnx2x *bp) 2089{ 2090 return BNX2X_NUM_ETH_QUEUES(bp); 2091} 2092 2093static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 2094{ 2095 struct bnx2x *bp = netdev_priv(dev); 2096 int i, num_stats; 2097 2098 switch (stringset) { 2099 case ETH_SS_STATS: 2100 if (is_multi(bp)) { 2101 num_stats = bnx2x_num_stat_queues(bp) * 2102 BNX2X_NUM_Q_STATS; 2103 if (!IS_MF_MODE_STAT(bp)) 2104 num_stats += BNX2X_NUM_STATS; 2105 } else { 2106 if (IS_MF_MODE_STAT(bp)) { 2107 num_stats = 0; 2108 for (i = 0; i < BNX2X_NUM_STATS; i++) 2109 if (IS_FUNC_STAT(i)) 2110 num_stats++; 2111 } else 2112 num_stats = BNX2X_NUM_STATS; 2113 } 2114 return num_stats; 2115 2116 case ETH_SS_TEST: 2117 return BNX2X_NUM_TESTS; 2118 2119 default: 2120 return -EINVAL; 2121 } 2122} 2123 2124static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 2125{ 2126 struct bnx2x *bp = netdev_priv(dev); 2127 int i, j, k; 2128 char queue_name[MAX_QUEUE_NAME_LEN+1]; 2129 2130 switch (stringset) { 2131 case ETH_SS_STATS: 2132 if (is_multi(bp)) { 2133 k = 0; 2134 for_each_eth_queue(bp, i) { 2135 memset(queue_name, 0, sizeof(queue_name)); 2136 sprintf(queue_name, "%d", i); 2137 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 2138 snprintf(buf + (k + j)*ETH_GSTRING_LEN, 2139 ETH_GSTRING_LEN, 2140 bnx2x_q_stats_arr[j].string, 2141 queue_name); 2142 k += BNX2X_NUM_Q_STATS; 2143 } 2144 if (IS_MF_MODE_STAT(bp)) 2145 break; 2146 for (j = 0; j < BNX2X_NUM_STATS; j++) 2147 strcpy(buf + (k + j)*ETH_GSTRING_LEN, 2148 bnx2x_stats_arr[j].string); 2149 } else { 2150 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 2151 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 2152 continue; 2153 strcpy(buf + j*ETH_GSTRING_LEN, 2154 bnx2x_stats_arr[i].string); 2155 j++; 2156 } 2157 } 2158 break; 2159 2160 case ETH_SS_TEST: 2161 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr)); 2162 break; 2163 } 2164} 2165 2166static void bnx2x_get_ethtool_stats(struct net_device *dev, 2167 struct ethtool_stats *stats, u64 *buf) 2168{ 2169 struct bnx2x *bp = netdev_priv(dev); 2170 u32 *hw_stats, *offset; 2171 int i, j, k; 2172 2173 if (is_multi(bp)) { 2174 k = 0; 2175 for_each_eth_queue(bp, i) { 2176 hw_stats = (u32 *)&bp->fp[i].eth_q_stats; 2177 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 2178 if (bnx2x_q_stats_arr[j].size == 0) { 2179 /* skip this counter */ 2180 buf[k + j] = 0; 2181 continue; 2182 } 2183 offset = (hw_stats + 2184 bnx2x_q_stats_arr[j].offset); 2185 if (bnx2x_q_stats_arr[j].size == 4) { 2186 /* 4-byte counter */ 2187 buf[k + j] = (u64) *offset; 2188 continue; 2189 } 2190 /* 8-byte counter */ 2191 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 2192 } 2193 k += BNX2X_NUM_Q_STATS; 2194 } 2195 if (IS_MF_MODE_STAT(bp)) 2196 return; 2197 hw_stats = (u32 *)&bp->eth_stats; 2198 for (j = 0; j < BNX2X_NUM_STATS; j++) { 2199 if (bnx2x_stats_arr[j].size == 0) { 2200 /* skip this counter */ 2201 buf[k + j] = 0; 2202 continue; 2203 } 2204 offset = (hw_stats + bnx2x_stats_arr[j].offset); 2205 if (bnx2x_stats_arr[j].size == 4) { 2206 /* 4-byte counter */ 2207 buf[k + j] = (u64) *offset; 2208 continue; 2209 } 2210 /* 8-byte counter */ 2211 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 2212 } 2213 } else { 2214 hw_stats = (u32 *)&bp->eth_stats; 2215 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 2216 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 2217 continue; 2218 if (bnx2x_stats_arr[i].size == 0) { 2219 /* skip this counter */ 2220 buf[j] = 0; 2221 j++; 2222 continue; 2223 } 2224 offset = (hw_stats + bnx2x_stats_arr[i].offset); 2225 if (bnx2x_stats_arr[i].size == 4) { 2226 /* 4-byte counter */ 2227 buf[j] = (u64) *offset; 2228 j++; 2229 continue; 2230 } 2231 /* 8-byte counter */ 2232 buf[j] = HILO_U64(*offset, *(offset + 1)); 2233 j++; 2234 } 2235 } 2236} 2237 2238static int bnx2x_set_phys_id(struct net_device *dev, 2239 enum ethtool_phys_id_state state) 2240{ 2241 struct bnx2x *bp = netdev_priv(dev); 2242 2243 if (!netif_running(dev)) 2244 return -EAGAIN; 2245 2246 if (!bp->port.pmf) 2247 return -EOPNOTSUPP; 2248 2249 switch (state) { 2250 case ETHTOOL_ID_ACTIVE: 2251 return 1; /* cycle on/off once per second */ 2252 2253 case ETHTOOL_ID_ON: 2254 bnx2x_set_led(&bp->link_params, &bp->link_vars, 2255 LED_MODE_ON, SPEED_1000); 2256 break; 2257 2258 case ETHTOOL_ID_OFF: 2259 bnx2x_set_led(&bp->link_params, &bp->link_vars, 2260 LED_MODE_FRONT_PANEL_OFF, 0); 2261 2262 break; 2263 2264 case ETHTOOL_ID_INACTIVE: 2265 bnx2x_set_led(&bp->link_params, &bp->link_vars, 2266 LED_MODE_OPER, 2267 bp->link_vars.line_speed); 2268 } 2269 2270 return 0; 2271} 2272 2273static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 2274 u32 *rules __always_unused) 2275{ 2276 struct bnx2x *bp = netdev_priv(dev); 2277 2278 switch (info->cmd) { 2279 case ETHTOOL_GRXRINGS: 2280 info->data = BNX2X_NUM_ETH_QUEUES(bp); 2281 return 0; 2282 2283 default: 2284 return -EOPNOTSUPP; 2285 } 2286} 2287 2288static int bnx2x_get_rxfh_indir(struct net_device *dev, 2289 struct ethtool_rxfh_indir *indir) 2290{ 2291 struct bnx2x *bp = netdev_priv(dev); 2292 size_t copy_size = 2293 min_t(size_t, indir->size, T_ETH_INDIRECTION_TABLE_SIZE); 2294 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 2295 size_t i; 2296 2297 if (bp->multi_mode == ETH_RSS_MODE_DISABLED) 2298 return -EOPNOTSUPP; 2299 2300 /* Get the current configuration of the RSS indirection table */ 2301 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 2302 2303 /* 2304 * We can't use a memcpy() as an internal storage of an 2305 * indirection table is a u8 array while indir->ring_index 2306 * points to an array of u32. 2307 * 2308 * Indirection table contains the FW Client IDs, so we need to 2309 * align the returned table to the Client ID of the leading RSS 2310 * queue. 2311 */ 2312 for (i = 0; i < copy_size; i++) 2313 indir->ring_index[i] = ind_table[i] - bp->fp->cl_id; 2314 2315 indir->size = T_ETH_INDIRECTION_TABLE_SIZE; 2316 2317 return 0; 2318} 2319 2320static int bnx2x_set_rxfh_indir(struct net_device *dev, 2321 const struct ethtool_rxfh_indir *indir) 2322{ 2323 struct bnx2x *bp = netdev_priv(dev); 2324 size_t i; 2325 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 2326 u32 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp); 2327 2328 if (bp->multi_mode == ETH_RSS_MODE_DISABLED) 2329 return -EOPNOTSUPP; 2330 2331 /* validate the size */ 2332 if (indir->size != T_ETH_INDIRECTION_TABLE_SIZE) 2333 return -EINVAL; 2334 2335 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 2336 /* validate the indices */ 2337 if (indir->ring_index[i] >= num_eth_queues) 2338 return -EINVAL; 2339 /* 2340 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy() 2341 * as an internal storage of an indirection table is a u8 array 2342 * while indir->ring_index points to an array of u32. 2343 * 2344 * Indirection table contains the FW Client IDs, so we need to 2345 * align the received table to the Client ID of the leading RSS 2346 * queue 2347 */ 2348 ind_table[i] = indir->ring_index[i] + bp->fp->cl_id; 2349 } 2350 2351 return bnx2x_config_rss_pf(bp, ind_table, false); 2352} 2353 2354static const struct ethtool_ops bnx2x_ethtool_ops = { 2355 .get_settings = bnx2x_get_settings, 2356 .set_settings = bnx2x_set_settings, 2357 .get_drvinfo = bnx2x_get_drvinfo, 2358 .get_regs_len = bnx2x_get_regs_len, 2359 .get_regs = bnx2x_get_regs, 2360 .get_wol = bnx2x_get_wol, 2361 .set_wol = bnx2x_set_wol, 2362 .get_msglevel = bnx2x_get_msglevel, 2363 .set_msglevel = bnx2x_set_msglevel, 2364 .nway_reset = bnx2x_nway_reset, 2365 .get_link = bnx2x_get_link, 2366 .get_eeprom_len = bnx2x_get_eeprom_len, 2367 .get_eeprom = bnx2x_get_eeprom, 2368 .set_eeprom = bnx2x_set_eeprom, 2369 .get_coalesce = bnx2x_get_coalesce, 2370 .set_coalesce = bnx2x_set_coalesce, 2371 .get_ringparam = bnx2x_get_ringparam, 2372 .set_ringparam = bnx2x_set_ringparam, 2373 .get_pauseparam = bnx2x_get_pauseparam, 2374 .set_pauseparam = bnx2x_set_pauseparam, 2375 .self_test = bnx2x_self_test, 2376 .get_sset_count = bnx2x_get_sset_count, 2377 .get_strings = bnx2x_get_strings, 2378 .set_phys_id = bnx2x_set_phys_id, 2379 .get_ethtool_stats = bnx2x_get_ethtool_stats, 2380 .get_rxnfc = bnx2x_get_rxnfc, 2381 .get_rxfh_indir = bnx2x_get_rxfh_indir, 2382 .set_rxfh_indir = bnx2x_set_rxfh_indir, 2383}; 2384 2385void bnx2x_set_ethtool_ops(struct net_device *netdev) 2386{ 2387 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops); 2388} 2389