bnx2x_hsi.h revision 0e898dd7a820c258270af36074427e0bed48c8db
1/* bnx2x_hsi.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2011 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9#ifndef BNX2X_HSI_H 10#define BNX2X_HSI_H 11 12#include "bnx2x_fw_defs.h" 13 14#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 15 16struct license_key { 17 u32 reserved[6]; 18 19 u32 max_iscsi_conn; 20#define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 21#define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0 22#define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 23#define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16 24 25 u32 reserved_a; 26 27 u32 max_fcoe_conn; 28#define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 29#define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0 30#define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 31#define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16 32 33 u32 reserved_b[4]; 34}; 35 36 37#define PORT_0 0 38#define PORT_1 1 39#define PORT_MAX 2 40 41/**************************************************************************** 42 * Shared HW configuration * 43 ****************************************************************************/ 44#define PIN_CFG_NA 0x00000000 45#define PIN_CFG_GPIO0_P0 0x00000001 46#define PIN_CFG_GPIO1_P0 0x00000002 47#define PIN_CFG_GPIO2_P0 0x00000003 48#define PIN_CFG_GPIO3_P0 0x00000004 49#define PIN_CFG_GPIO0_P1 0x00000005 50#define PIN_CFG_GPIO1_P1 0x00000006 51#define PIN_CFG_GPIO2_P1 0x00000007 52#define PIN_CFG_GPIO3_P1 0x00000008 53#define PIN_CFG_EPIO0 0x00000009 54#define PIN_CFG_EPIO1 0x0000000a 55#define PIN_CFG_EPIO2 0x0000000b 56#define PIN_CFG_EPIO3 0x0000000c 57#define PIN_CFG_EPIO4 0x0000000d 58#define PIN_CFG_EPIO5 0x0000000e 59#define PIN_CFG_EPIO6 0x0000000f 60#define PIN_CFG_EPIO7 0x00000010 61#define PIN_CFG_EPIO8 0x00000011 62#define PIN_CFG_EPIO9 0x00000012 63#define PIN_CFG_EPIO10 0x00000013 64#define PIN_CFG_EPIO11 0x00000014 65#define PIN_CFG_EPIO12 0x00000015 66#define PIN_CFG_EPIO13 0x00000016 67#define PIN_CFG_EPIO14 0x00000017 68#define PIN_CFG_EPIO15 0x00000018 69#define PIN_CFG_EPIO16 0x00000019 70#define PIN_CFG_EPIO17 0x0000001a 71#define PIN_CFG_EPIO18 0x0000001b 72#define PIN_CFG_EPIO19 0x0000001c 73#define PIN_CFG_EPIO20 0x0000001d 74#define PIN_CFG_EPIO21 0x0000001e 75#define PIN_CFG_EPIO22 0x0000001f 76#define PIN_CFG_EPIO23 0x00000020 77#define PIN_CFG_EPIO24 0x00000021 78#define PIN_CFG_EPIO25 0x00000022 79#define PIN_CFG_EPIO26 0x00000023 80#define PIN_CFG_EPIO27 0x00000024 81#define PIN_CFG_EPIO28 0x00000025 82#define PIN_CFG_EPIO29 0x00000026 83#define PIN_CFG_EPIO30 0x00000027 84#define PIN_CFG_EPIO31 0x00000028 85 86/* EPIO definition */ 87#define EPIO_CFG_NA 0x00000000 88#define EPIO_CFG_EPIO0 0x00000001 89#define EPIO_CFG_EPIO1 0x00000002 90#define EPIO_CFG_EPIO2 0x00000003 91#define EPIO_CFG_EPIO3 0x00000004 92#define EPIO_CFG_EPIO4 0x00000005 93#define EPIO_CFG_EPIO5 0x00000006 94#define EPIO_CFG_EPIO6 0x00000007 95#define EPIO_CFG_EPIO7 0x00000008 96#define EPIO_CFG_EPIO8 0x00000009 97#define EPIO_CFG_EPIO9 0x0000000a 98#define EPIO_CFG_EPIO10 0x0000000b 99#define EPIO_CFG_EPIO11 0x0000000c 100#define EPIO_CFG_EPIO12 0x0000000d 101#define EPIO_CFG_EPIO13 0x0000000e 102#define EPIO_CFG_EPIO14 0x0000000f 103#define EPIO_CFG_EPIO15 0x00000010 104#define EPIO_CFG_EPIO16 0x00000011 105#define EPIO_CFG_EPIO17 0x00000012 106#define EPIO_CFG_EPIO18 0x00000013 107#define EPIO_CFG_EPIO19 0x00000014 108#define EPIO_CFG_EPIO20 0x00000015 109#define EPIO_CFG_EPIO21 0x00000016 110#define EPIO_CFG_EPIO22 0x00000017 111#define EPIO_CFG_EPIO23 0x00000018 112#define EPIO_CFG_EPIO24 0x00000019 113#define EPIO_CFG_EPIO25 0x0000001a 114#define EPIO_CFG_EPIO26 0x0000001b 115#define EPIO_CFG_EPIO27 0x0000001c 116#define EPIO_CFG_EPIO28 0x0000001d 117#define EPIO_CFG_EPIO29 0x0000001e 118#define EPIO_CFG_EPIO30 0x0000001f 119#define EPIO_CFG_EPIO31 0x00000020 120 121 122struct shared_hw_cfg { /* NVRAM Offset */ 123 /* Up to 16 bytes of NULL-terminated string */ 124 u8 part_num[16]; /* 0x104 */ 125 126 u32 config; /* 0x114 */ 127 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 128 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 129 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 130 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 131 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002 132 133 #define SHARED_HW_CFG_PORT_SWAP 0x00000004 134 135 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 136 137 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 138 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 139 140 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 141 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 142 /* Whatever MFW found in NVM 143 (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 144 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 145 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 146 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 147 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 148 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 149 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 150 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 151 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 152 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 153 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 154 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 155 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 156 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 157 158 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000 159 #define SHARED_HW_CFG_LED_MODE_SHIFT 16 160 #define SHARED_HW_CFG_LED_MAC1 0x00000000 161 #define SHARED_HW_CFG_LED_PHY1 0x00010000 162 #define SHARED_HW_CFG_LED_PHY2 0x00020000 163 #define SHARED_HW_CFG_LED_PHY3 0x00030000 164 #define SHARED_HW_CFG_LED_MAC2 0x00040000 165 #define SHARED_HW_CFG_LED_PHY4 0x00050000 166 #define SHARED_HW_CFG_LED_PHY5 0x00060000 167 #define SHARED_HW_CFG_LED_PHY6 0x00070000 168 #define SHARED_HW_CFG_LED_MAC3 0x00080000 169 #define SHARED_HW_CFG_LED_PHY7 0x00090000 170 #define SHARED_HW_CFG_LED_PHY9 0x000a0000 171 #define SHARED_HW_CFG_LED_PHY11 0x000b0000 172 #define SHARED_HW_CFG_LED_MAC4 0x000c0000 173 #define SHARED_HW_CFG_LED_PHY8 0x000d0000 174 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 175 176 177 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000 178 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24 179 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000 180 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000 181 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000 182 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000 183 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000 184 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000 185 186 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 187 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 188 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 189 190 #define SHARED_HW_CFG_ATC_MASK 0x80000000 191 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 192 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 193 194 u32 config2; /* 0x118 */ 195 /* one time auto detect grace period (in sec) */ 196 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff 197 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0 198 199 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 200 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 201 202 /* The default value for the core clock is 250MHz and it is 203 achieved by setting the clock change to 4 */ 204 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00 205 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9 206 207 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 208 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 209 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 210 211 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 212 213 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000 214 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000 215 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000 216 217 /* Output low when PERST is asserted */ 218 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 219 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 220 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 221 222 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 224 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 225 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 226 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 227 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 228 229 /* The fan failure mechanism is usually related to the PHY type 230 since the power consumption of the board is determined by the PHY. 231 Currently, fan is required for most designs with SFX7101, BCM8727 232 and BCM8481. If a fan is not required for a board which uses one 233 of those PHYs, this field should be set to "Disabled". If a fan is 234 required for a different PHY type, this option should be set to 235 "Enabled". The fan failure indication is expected on SPIO5 */ 236 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 237 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 238 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 239 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 240 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 241 242 /* ASPM Power Management support */ 243 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 244 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 245 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 246 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 247 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 248 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 249 250 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 251 tl_control_0 (register 0x2800) */ 252 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 253 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 254 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 255 256 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000 257 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000 258 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000 259 260 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000 261 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000 262 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000 263 264 /* Set the MDC/MDIO access for the first external phy */ 265 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 272 273 /* Set the MDC/MDIO access for the second external phy */ 274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 281 282 283 u32 power_dissipated; /* 0x11c */ 284 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000 285 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16 286 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000 287 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000 288 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000 289 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000 290 291 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 292 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24 293 294 u32 ump_nc_si_config; /* 0x120 */ 295 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 297 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 298 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 299 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 301 302 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00 303 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8 304 305 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000 306 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16 307 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000 308 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 309 310 u32 board; /* 0x124 */ 311 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 312 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 313 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 314 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 315 /* Use the PIN_CFG_XXX defines on top */ 316 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000 317 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 318 319 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000 320 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 321 322 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000 323 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 324 325 u32 wc_lane_config; /* 0x128 */ 326 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 327 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 328 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 329 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 330 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 331 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 332 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 333 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 334 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 335 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 336 337 /* TX lane Polarity swap */ 338 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 339 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 340 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 341 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 342 /* TX lane Polarity swap */ 343 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 344 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 345 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 346 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 347 348 /* Selects the port layout of the board */ 349 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 357}; 358 359 360/**************************************************************************** 361 * Port HW configuration * 362 ****************************************************************************/ 363struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 364 365 u32 pci_id; 366 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 367 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff 368 369 u32 pci_sub_id; 370 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 371 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff 372 373 u32 power_dissipated; 374 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff 375 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 376 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00 377 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 378 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000 379 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 380 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000 381 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 382 383 u32 power_consumed; 384 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff 385 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 386 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00 387 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 388 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000 389 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 390 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000 391 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 392 393 u32 mac_upper; 394 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff 395 #define PORT_HW_CFG_UPPERMAC_SHIFT 0 396 u32 mac_lower; 397 398 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 399 u32 iscsi_mac_lower; 400 401 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ 402 u32 rdma_mac_lower; 403 404 u32 serdes_config; 405 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff 406 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 407 408 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000 409 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 410 411 412 /* Default values: 2P-64, 4P-32 */ 413 u32 pf_config; /* 0x158 */ 414 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F 415 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0 416 417 /* Default values: 17 */ 418 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00 419 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8 420 421 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000 422 #define PORT_HW_CFG_FLR_ENABLED 0x00010000 423 424 u32 vf_config; /* 0x15C */ 425 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F 426 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0 427 428 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 429 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 430 431 u32 mf_pci_id; /* 0x160 */ 432 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 433 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 434 435 /* Controls the TX laser of the SFP+ module */ 436 u32 sfp_ctrl; /* 0x164 */ 437 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 438 #define PORT_HW_CFG_TX_LASER_SHIFT 0 439 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 440 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 441 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 442 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 443 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 444 445 /* Controls the fault module LED of the SFP+ */ 446 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 447 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 448 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 449 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 450 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 451 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 452 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 453 454 /* The output pin TX_DIS that controls the TX laser of the SFP+ 455 module. Use the PIN_CFG_XXX defines on top */ 456 u32 e3_sfp_ctrl; /* 0x168 */ 457 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 458 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 459 460 /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 461 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 462 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 463 464 /* The input pin MOD_ABS that indicates whether SFP+ module is 465 present or not. Use the PIN_CFG_XXX defines on top */ 466 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 467 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 468 469 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 470 module. Use the PIN_CFG_XXX defines on top */ 471 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 472 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 473 474 /* 475 * The input pin which signals module transmit fault. Use the 476 * PIN_CFG_XXX defines on top 477 */ 478 u32 e3_cmn_pin_cfg; /* 0x16C */ 479 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 480 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 481 482 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 483 top */ 484 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 485 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 486 487 /* 488 * The output pin which powers down the PHY. Use the PIN_CFG_XXX 489 * defines on top 490 */ 491 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 492 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 493 494 /* The output pin values BSC_SEL which selects the I2C for this port 495 in the I2C Mux */ 496 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 497 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 498 499 500 /* 501 * The input pin I_FAULT which indicate over-current has occurred. 502 * Use the PIN_CFG_XXX defines on top 503 */ 504 u32 e3_cmn_pin_cfg1; /* 0x170 */ 505 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 506 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 507 u32 reserved0[7]; /* 0x174 */ 508 509 u32 aeu_int_mask; /* 0x190 */ 510 511 u32 media_type; /* 0x194 */ 512 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 513 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 514 515 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 516 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 517 518 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 519 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 520 521 /* 4 times 16 bits for all 4 lanes. In case external PHY is present 522 (not direct mode), those values will not take effect on the 4 XGXS 523 lanes. For some external PHYs (such as 8706 and 8726) the values 524 will be used to configure the external PHY in those cases, not 525 all 4 values are needed. */ 526 u16 xgxs_config_rx[4]; /* 0x198 */ 527 u16 xgxs_config_tx[4]; /* 0x1A0 */ 528 529 /* For storing FCOE mac on shared memory */ 530 u32 fcoe_fip_mac_upper; 531 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 532 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 533 u32 fcoe_fip_mac_lower; 534 535 u32 fcoe_wwn_port_name_upper; 536 u32 fcoe_wwn_port_name_lower; 537 538 u32 fcoe_wwn_node_name_upper; 539 u32 fcoe_wwn_node_name_lower; 540 541 u32 Reserved1[49]; /* 0x1C0 */ 542 543 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 544 84833 only */ 545 u32 xgbt_phy_cfg; /* 0x284 */ 546 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 547 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 548 549 u32 default_cfg; /* 0x288 */ 550 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 551 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 552 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 553 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 554 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 555 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 556 557 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 558 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 559 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 560 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 561 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 562 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 563 564 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 565 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 566 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 567 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 568 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 569 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 570 571 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 572 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 573 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 574 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 575 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 576 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 577 578 /* When KR link is required to be set to force which is not 579 KR-compliant, this parameter determine what is the trigger for it. 580 When GPIO is selected, low input will force the speed. Currently 581 default speed is 1G. In the future, it may be widen to select the 582 forced speed in with another parameter. Note when force-1G is 583 enabled, it override option 56: Link Speed option. */ 584 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 585 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 586 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 587 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 588 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 589 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 590 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 591 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 592 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 593 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 594 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 595 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 596 /* Enable to determine with which GPIO to reset the external phy */ 597 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 598 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 599 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 600 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 601 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 602 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 603 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 604 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 605 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 606 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 607 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 608 609 /* Enable BAM on KR */ 610 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 611 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 612 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 613 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 614 615 /* Enable Common Mode Sense */ 616 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 617 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 618 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 619 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 620 621 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY, 84833 only */ 622 #define PORT_HW_CFG_RJ45_PR_SWP_MASK 0x00400000 623 #define PORT_HW_CFG_RJ45_PR_SWP_SHIFT 22 624 #define PORT_HW_CFG_RJ45_PR_SWP_DISABLED 0x00000000 625 #define PORT_HW_CFG_RJ45_PR_SWP_ENABLED 0x00400000 626 627 /* Determine the Serdes electrical interface */ 628 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 629 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 630 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 631 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 632 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 633 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 634 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 635 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 636 637 638 u32 speed_capability_mask2; /* 0x28C */ 639 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 640 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 641 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 642 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002 643 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004 644 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 645 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 646 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020 647 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 648 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 649 650 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 651 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 652 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 653 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000 654 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000 655 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 656 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 657 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000 658 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 659 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 660 661 662 /* In the case where two media types (e.g. copper and fiber) are 663 present and electrically active at the same time, PHY Selection 664 will determine which of the two PHYs will be designated as the 665 Active PHY and used for a connection to the network. */ 666 u32 multi_phy_config; /* 0x290 */ 667 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 668 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 669 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 670 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 671 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 672 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 673 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 674 675 /* When enabled, all second phy nvram parameters will be swapped 676 with the first phy parameters */ 677 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 678 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 679 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 680 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 681 682 683 /* Address of the second external phy */ 684 u32 external_phy_config2; /* 0x294 */ 685 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 686 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 687 688 /* The second XGXS external PHY type */ 689 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 690 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 691 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 692 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 693 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 694 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 695 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 696 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 697 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 698 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 699 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 700 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 701 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 702 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 703 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 704 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 705 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 706 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 707 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 708 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 709 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 710 711 712 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 713 8706, 8726 and 8727) not all 4 values are needed. */ 714 u16 xgxs_config2_rx[4]; /* 0x296 */ 715 u16 xgxs_config2_tx[4]; /* 0x2A0 */ 716 717 u32 lane_config; 718 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff 719 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 720 /* AN and forced */ 721 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 722 /* forced only */ 723 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 724 /* forced only */ 725 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 726 /* forced only */ 727 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 728 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff 729 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 730 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00 731 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 732 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000 733 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 734 735 /* Indicate whether to swap the external phy polarity */ 736 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 737 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 738 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 739 740 741 u32 external_phy_config; 742 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff 743 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 744 745 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00 746 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 747 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 748 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 749 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 750 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 751 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 752 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 753 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 754 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 755 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 756 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 757 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 758 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 759 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 760 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 761 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 762 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 763 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 764 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 765 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 766 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 767 768 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000 769 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 770 771 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000 772 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 773 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 774 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 775 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 776 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 777 778 u32 speed_capability_mask; 779 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff 780 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 781 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 782 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 783 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 784 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 785 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 786 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 787 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 788 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 789 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 790 791 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000 792 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 793 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 794 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 795 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 796 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 797 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 798 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 799 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 800 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 801 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 802 803 /* A place to hold the original MAC address as a backup */ 804 u32 backup_mac_upper; /* 0x2B4 */ 805 u32 backup_mac_lower; /* 0x2B8 */ 806 807}; 808 809 810/**************************************************************************** 811 * Shared Feature configuration * 812 ****************************************************************************/ 813struct shared_feat_cfg { /* NVRAM Offset */ 814 815 u32 config; /* 0x450 */ 816 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 817 818 /* Use NVRAM values instead of HW default values */ 819 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 820 0x00000002 821 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 822 0x00000000 823 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 824 0x00000002 825 826 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 827 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 828 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 829 830 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 831 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 832 833 /* Override the OTP back to single function mode. When using GPIO, 834 high means only SF, 0 is according to CLP configuration */ 835 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 836 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 837 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 838 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 839 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 840 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 841 842 /* The interval in seconds between sending LLDP packets. Set to zero 843 to disable the feature */ 844 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000 845 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 846 847 /* The assigned device type ID for LLDP usage */ 848 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000 849 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 850 851}; 852 853 854/**************************************************************************** 855 * Port Feature configuration * 856 ****************************************************************************/ 857struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 858 859 u32 config; 860 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f 861 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 862 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000 863 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001 864 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002 865 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003 866 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004 867 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005 868 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006 869 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007 870 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008 871 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009 872 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a 873 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b 874 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c 875 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d 876 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e 877 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f 878 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0 879 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4 880 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000 881 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010 882 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020 883 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030 884 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040 885 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050 886 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060 887 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070 888 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080 889 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090 890 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0 891 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0 892 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0 893 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0 894 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0 895 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0 896 897 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 898 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 899 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 900 901 #define PORT_FEAT_CFG_AUTOGREEN_MASK 0x00000200 902 #define PORT_FEAT_CFG_AUTOGREEN_SHIFT 9 903 #define PORT_FEAT_CFG_AUTOGREEN_DISABLED 0x00000000 904 #define PORT_FEAT_CFG_AUTOGREEN_ENABLED 0x00000200 905 906 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 907 #define PORT_FEATURE_EN_SIZE_SHIFT 24 908 #define PORT_FEATURE_WOL_ENABLED 0x01000000 909 #define PORT_FEATURE_MBA_ENABLED 0x02000000 910 #define PORT_FEATURE_MFW_ENABLED 0x04000000 911 912 /* Advertise expansion ROM even if MBA is disabled */ 913 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 914 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 915 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 916 917 /* Check the optic vendor via i2c against a list of approved modules 918 in a separate nvram image */ 919 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000 920 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 921 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 922 0x00000000 923 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 924 0x20000000 925 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 926 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 927 928 u32 wol_config; 929 /* Default is used when driver sets to "auto" mode */ 930 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 931 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0 932 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000 933 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001 934 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002 935 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003 936 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004 937 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008 938 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 939 940 u32 mba_config; 941 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 942 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 943 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 944 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 945 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 946 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 947 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 948 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 949 950 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 951 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 952 953 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 954 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 955 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 956 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 957 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 958 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 959 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000 960 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 961 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 962 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 963 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 964 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 965 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 966 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 967 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 968 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 969 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 970 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 971 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 972 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 973 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 974 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 975 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 976 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 977 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000 978 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 979 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 980 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 981 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 982 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 983 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 984 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 985 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000 986 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 987 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 988 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000 989 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000 990 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000 991 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000 992 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000 993 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000 994 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000 995 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000 996 u32 bmc_config; 997 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001 998 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000 999 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001 1000 1001 u32 mba_vlan_cfg; 1002 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff 1003 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 1004 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 1005 1006 u32 resource_cfg; 1007 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001 1008 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002 1009 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004 1010 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008 1011 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010 1012 1013 u32 smbus_config; 1014 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1015 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1016 1017 u32 vf_config; 1018 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f 1019 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1020 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1021 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1022 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1023 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1024 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1025 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1026 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1027 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1028 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1029 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1030 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1031 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1032 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1033 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1034 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1035 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1036 1037 u32 link_config; /* Used as HW defaults for the driver */ 1038 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1039 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1040 /* (forced) low speed switch (< 10G) */ 1041 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1042 /* (forced) high speed switch (>= 10G) */ 1043 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1044 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1045 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1046 1047 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000 1048 #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1049 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1050 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 1051 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 1052 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1053 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1054 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1055 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1056 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1057 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1058 1059 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1060 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1061 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1062 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1063 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1064 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1065 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1066 1067 /* The default for MCP link configuration, 1068 uses the same defines as link_config */ 1069 u32 mfw_wol_link_cfg; 1070 1071 /* The default for the driver of the second external phy, 1072 uses the same defines as link_config */ 1073 u32 link_config2; /* 0x47C */ 1074 1075 /* The default for MCP of the second external phy, 1076 uses the same defines as link_config */ 1077 u32 mfw_wol_link_cfg2; /* 0x480 */ 1078 1079 u32 Reserved2[17]; /* 0x484 */ 1080 1081}; 1082 1083 1084/**************************************************************************** 1085 * Device Information * 1086 ****************************************************************************/ 1087struct shm_dev_info { /* size */ 1088 1089 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1090 1091 struct shared_hw_cfg shared_hw_config; /* 40 */ 1092 1093 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1094 1095 struct shared_feat_cfg shared_feature_config; /* 4 */ 1096 1097 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1098 1099}; 1100 1101 1102#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 1103 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 1104#endif 1105 1106#define FUNC_0 0 1107#define FUNC_1 1 1108#define FUNC_2 2 1109#define FUNC_3 3 1110#define FUNC_4 4 1111#define FUNC_5 5 1112#define FUNC_6 6 1113#define FUNC_7 7 1114#define E1_FUNC_MAX 2 1115#define E1H_FUNC_MAX 8 1116#define E2_FUNC_MAX 4 /* per path */ 1117 1118#define VN_0 0 1119#define VN_1 1 1120#define VN_2 2 1121#define VN_3 3 1122#define E1VN_MAX 1 1123#define E1HVN_MAX 4 1124 1125#define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ 1126/* This value (in milliseconds) determines the frequency of the driver 1127 * issuing the PULSE message code. The firmware monitors this periodic 1128 * pulse to determine when to switch to an OS-absent mode. */ 1129#define DRV_PULSE_PERIOD_MS 250 1130 1131/* This value (in milliseconds) determines how long the driver should 1132 * wait for an acknowledgement from the firmware before timing out. Once 1133 * the firmware has timed out, the driver will assume there is no firmware 1134 * running and there won't be any firmware-driver synchronization during a 1135 * driver reset. */ 1136#define FW_ACK_TIME_OUT_MS 5000 1137 1138#define FW_ACK_POLL_TIME_MS 1 1139 1140#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 1141 1142/* LED Blink rate that will achieve ~15.9Hz */ 1143#define LED_BLINK_RATE_VAL 480 1144 1145/**************************************************************************** 1146 * Driver <-> FW Mailbox * 1147 ****************************************************************************/ 1148struct drv_port_mb { 1149 1150 u32 link_status; 1151 /* Driver should update this field on any link change event */ 1152 1153 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 1154 #define LINK_STATUS_LINK_UP 0x00000001 1155 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 1156 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 1157 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 1158 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 1159 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 1160 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 1161 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 1162 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 1163 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 1164 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 1165 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 1166 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 1167 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 1168 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 1169 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 1170 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) 1171 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) 1172 1173 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 1174 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 1175 1176 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 1177 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 1178 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 1179 1180 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 1181 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 1182 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 1183 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 1184 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 1185 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 1186 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 1187 1188 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 1189 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 1190 1191 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 1192 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 1193 1194 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 1195 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 1196 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 1197 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 1198 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 1199 1200 #define LINK_STATUS_SERDES_LINK 0x00100000 1201 1202 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 1203 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 1204 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 1205 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 1206 1207 #define LINK_STATUS_PFC_ENABLED 0x20000000 1208 1209 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 1210 1211 u32 port_stx; 1212 1213 u32 stat_nig_timer; 1214 1215 /* MCP firmware does not use this field */ 1216 u32 ext_phy_fw_version; 1217 1218}; 1219 1220 1221struct drv_func_mb { 1222 1223 u32 drv_mb_header; 1224 #define DRV_MSG_CODE_MASK 0xffff0000 1225 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1226 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1227 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 1228 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 1229 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 1230 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1231 #define DRV_MSG_CODE_DCC_OK 0x30000000 1232 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 1233 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 1234 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 1235 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 1236 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 1237 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 1238 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 1239 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 1240 /* 1241 * The optic module verification command requires bootcode 1242 * v5.0.6 or later, te specific optic module verification command 1243 * requires bootcode v5.2.12 or later 1244 */ 1245 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 1246 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 1247 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 1248 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 1249 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 1250 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 1251 1252 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 1253 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 1254 1255 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1256 1257 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 1258 #define REQ_BC_VER_4_SET_MF_BW 0x00060202 1259 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 1260 1261 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 1262 1263 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 1264 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 1265 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1266 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1267 1268 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1269 1270 u32 drv_mb_param; 1271 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 1272 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 1273 1274 u32 fw_mb_header; 1275 #define FW_MSG_CODE_MASK 0xffff0000 1276 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 1277 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1278 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1279 /* Load common chip is supported from bc 6.0.0 */ 1280 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 1281 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 1282 1283 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 1284 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1285 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 1286 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 1287 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 1288 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1289 #define FW_MSG_CODE_DCC_DONE 0x30100000 1290 #define FW_MSG_CODE_LLDP_DONE 0x40100000 1291 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 1292 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 1293 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 1294 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 1295 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 1296 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 1297 #define FW_MSG_CODE_NO_KEY 0x80f00000 1298 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 1299 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 1300 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 1301 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 1302 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 1303 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 1304 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 1305 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 1306 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 1307 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1308 1309 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 1310 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 1311 1312 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 1313 1314 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 1315 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 1316 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1317 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1318 1319 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1320 1321 u32 fw_mb_param; 1322 1323 u32 drv_pulse_mb; 1324 #define DRV_PULSE_SEQ_MASK 0x00007fff 1325 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1326 /* 1327 * The system time is in the format of 1328 * (year-2001)*12*32 + month*32 + day. 1329 */ 1330 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1331 /* 1332 * Indicate to the firmware not to go into the 1333 * OS-absent when it is not getting driver pulse. 1334 * This is used for debugging as well for PXE(MBA). 1335 */ 1336 1337 u32 mcp_pulse_mb; 1338 #define MCP_PULSE_SEQ_MASK 0x00007fff 1339 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1340 /* Indicates to the driver not to assert due to lack 1341 * of MCP response */ 1342 #define MCP_EVENT_MASK 0xffff0000 1343 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1344 1345 u32 iscsi_boot_signature; 1346 u32 iscsi_boot_block_offset; 1347 1348 u32 drv_status; 1349 #define DRV_STATUS_PMF 0x00000001 1350 #define DRV_STATUS_VF_DISABLED 0x00000002 1351 #define DRV_STATUS_SET_MF_BW 0x00000004 1352 #define DRV_STATUS_LINK_EVENT 0x00000008 1353 1354 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 1355 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 1356 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 1357 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 1358 #define DRV_STATUS_DCC_RESERVED1 0x00000800 1359 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 1360 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 1361 1362 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 1363 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 1364 1365 u32 virt_mac_upper; 1366 #define VIRT_MAC_SIGN_MASK 0xffff0000 1367 #define VIRT_MAC_SIGNATURE 0x564d0000 1368 u32 virt_mac_lower; 1369 1370}; 1371 1372 1373/**************************************************************************** 1374 * Management firmware state * 1375 ****************************************************************************/ 1376/* Allocate 440 bytes for management firmware */ 1377#define MGMTFW_STATE_WORD_SIZE 110 1378 1379struct mgmtfw_state { 1380 u32 opaque[MGMTFW_STATE_WORD_SIZE]; 1381}; 1382 1383 1384/**************************************************************************** 1385 * Multi-Function configuration * 1386 ****************************************************************************/ 1387struct shared_mf_cfg { 1388 1389 u32 clp_mb; 1390 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 1391 /* set by CLP */ 1392 #define SHARED_MF_CLP_EXIT 0x00000001 1393 /* set by MCP */ 1394 #define SHARED_MF_CLP_EXIT_DONE 0x00010000 1395 1396}; 1397 1398struct port_mf_cfg { 1399 1400 u32 dynamic_cfg; /* device control channel */ 1401 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1402 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 1403 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 1404 1405 u32 reserved[3]; 1406 1407}; 1408 1409struct func_mf_cfg { 1410 1411 u32 config; 1412 /* E/R/I/D */ 1413 /* function 0 of each port cannot be hidden */ 1414 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 1415 1416 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 1417 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 1418 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 1419 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 1420 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 1421 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ 1422 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 1423 1424 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 1425 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 1426 1427 /* PRI */ 1428 /* 0 - low priority, 3 - high priority */ 1429 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 1430 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 1431 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 1432 1433 /* MINBW, MAXBW */ 1434 /* value range - 0..100, increments in 100Mbps */ 1435 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 1436 #define FUNC_MF_CFG_MIN_BW_SHIFT 16 1437 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 1438 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 1439 #define FUNC_MF_CFG_MAX_BW_SHIFT 24 1440 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 1441 1442 u32 mac_upper; /* MAC */ 1443 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 1444 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 1445 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 1446 u32 mac_lower; 1447 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 1448 1449 u32 e1hov_tag; /* VNI */ 1450 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1451 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 1452 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 1453 1454 u32 reserved[2]; 1455}; 1456 1457/* This structure is not applicable and should not be accessed on 57711 */ 1458struct func_ext_cfg { 1459 u32 func_cfg; 1460 #define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF 1461 #define MACP_FUNC_CFG_FLAGS_SHIFT 0 1462 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 1463 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 1464 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 1465 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 1466 1467 u32 iscsi_mac_addr_upper; 1468 u32 iscsi_mac_addr_lower; 1469 1470 u32 fcoe_mac_addr_upper; 1471 u32 fcoe_mac_addr_lower; 1472 1473 u32 fcoe_wwn_port_name_upper; 1474 u32 fcoe_wwn_port_name_lower; 1475 1476 u32 fcoe_wwn_node_name_upper; 1477 u32 fcoe_wwn_node_name_lower; 1478 1479 u32 preserve_data; 1480 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 1481 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 1482 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 1483 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 1484 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 1485 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) 1486}; 1487 1488struct mf_cfg { 1489 1490 struct shared_mf_cfg shared_mf_config; /* 0x4 */ 1491 struct port_mf_cfg port_mf_config[PORT_MAX]; /* 0x10 * 2 = 0x20 */ 1492 /* for all chips, there are 8 mf functions */ 1493 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ 1494 /* 1495 * Extended configuration per function - this array does not exist and 1496 * should not be accessed on 57711 1497 */ 1498 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ 1499}; /* 0x224 */ 1500 1501/**************************************************************************** 1502 * Shared Memory Region * 1503 ****************************************************************************/ 1504struct shmem_region { /* SharedMem Offset (size) */ 1505 1506 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 1507 #define SHR_MEM_FORMAT_REV_MASK 0xff000000 1508 #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 1509 /* validity bits */ 1510 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 1511 #define SHR_MEM_VALIDITY_MB 0x00200000 1512 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 1513 #define SHR_MEM_VALIDITY_RESERVED 0x00000007 1514 /* One licensing bit should be set */ 1515 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 1516 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 1517 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 1518 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 1519 /* Active MFW */ 1520 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 1521 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 1522 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 1523 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 1524 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 1525 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 1526 1527 struct shm_dev_info dev_info; /* 0x8 (0x438) */ 1528 1529 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ 1530 1531 /* FW information (for internal FW use) */ 1532 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ 1533 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 1534 1535 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 1536 1537#ifdef BMAPI 1538 /* This is a variable length array */ 1539 /* the number of function depends on the chip type */ 1540 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1541#else 1542 /* the number of function depends on the chip type */ 1543 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1544#endif /* BMAPI */ 1545 1546}; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 1547 1548/**************************************************************************** 1549 * Shared Memory 2 Region * 1550 ****************************************************************************/ 1551/* The fw_flr_ack is actually built in the following way: */ 1552/* 8 bit: PF ack */ 1553/* 64 bit: VF ack */ 1554/* 8 bit: ios_dis_ack */ 1555/* In order to maintain endianity in the mailbox hsi, we want to keep using */ 1556/* u32. The fw must have the VF right after the PF since this is how it */ 1557/* access arrays(it expects always the VF to reside after the PF, and that */ 1558/* makes the calculation much easier for it. ) */ 1559/* In order to answer both limitations, and keep the struct small, the code */ 1560/* will abuse the structure defined here to achieve the actual partition */ 1561/* above */ 1562/****************************************************************************/ 1563struct fw_flr_ack { 1564 u32 pf_ack; 1565 u32 vf_ack[1]; 1566 u32 iov_dis_ack; 1567}; 1568 1569struct fw_flr_mb { 1570 u32 aggint; 1571 u32 opgen_addr; 1572 struct fw_flr_ack ack; 1573}; 1574 1575/**** SUPPORT FOR SHMEM ARRRAYS *** 1576 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 1577 * define arrays with storage types smaller then unsigned dwords. 1578 * The macros below add generic support for SHMEM arrays with numeric elements 1579 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 1580 * array with individual bit-filed elements accessed using shifts and masks. 1581 * 1582 */ 1583 1584/* eb is the bitwidth of a single element */ 1585#define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 1586#define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 1587 1588/* the bit-position macro allows the used to flip the order of the arrays 1589 * elements on a per byte or word boundary. 1590 * 1591 * example: an array with 8 entries each 4 bit wide. This array will fit into 1592 * a single dword. The diagrmas below show the array order of the nibbles. 1593 * 1594 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: 1595 * 1596 * | | | | 1597 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 1598 * | | | | 1599 * 1600 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 1601 * 1602 * | | | | 1603 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 1604 * | | | | 1605 * 1606 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 1607 * 1608 * | | | | 1609 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 1610 * | | | | 1611 */ 1612#define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 1613 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 1614 (((i)%((fb)/(eb))) * (eb))) 1615 1616#define SHMEM_ARRAY_GET(a, i, eb, fb) \ 1617 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 1618 SHMEM_ARRAY_MASK(eb)) 1619 1620#define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 1621do { \ 1622 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 1623 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1624 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 1625 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1626} while (0) 1627 1628 1629/****START OF DCBX STRUCTURES DECLARATIONS****/ 1630#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 1631#define DCBX_PRI_PG_BITWIDTH 4 1632#define DCBX_PRI_PG_FBITS 8 1633#define DCBX_PRI_PG_GET(a, i) \ 1634 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 1635#define DCBX_PRI_PG_SET(a, i, val) \ 1636 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 1637#define DCBX_MAX_NUM_PG_BW_ENTRIES 8 1638#define DCBX_BW_PG_BITWIDTH 8 1639#define DCBX_PG_BW_GET(a, i) \ 1640 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 1641#define DCBX_PG_BW_SET(a, i, val) \ 1642 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 1643#define DCBX_STRICT_PRI_PG 15 1644#define DCBX_MAX_APP_PROTOCOL 16 1645#define FCOE_APP_IDX 0 1646#define ISCSI_APP_IDX 1 1647#define PREDEFINED_APP_IDX_MAX 2 1648 1649 1650/* Big/Little endian have the same representation. */ 1651struct dcbx_ets_feature { 1652 /* 1653 * For Admin MIB - is this feature supported by the 1654 * driver | For Local MIB - should this feature be enabled. 1655 */ 1656 u32 enabled; 1657 u32 pg_bw_tbl[2]; 1658 u32 pri_pg_tbl[1]; 1659}; 1660 1661/* Driver structure in LE */ 1662struct dcbx_pfc_feature { 1663#ifdef __BIG_ENDIAN 1664 u8 pri_en_bitmap; 1665 #define DCBX_PFC_PRI_0 0x01 1666 #define DCBX_PFC_PRI_1 0x02 1667 #define DCBX_PFC_PRI_2 0x04 1668 #define DCBX_PFC_PRI_3 0x08 1669 #define DCBX_PFC_PRI_4 0x10 1670 #define DCBX_PFC_PRI_5 0x20 1671 #define DCBX_PFC_PRI_6 0x40 1672 #define DCBX_PFC_PRI_7 0x80 1673 u8 pfc_caps; 1674 u8 reserved; 1675 u8 enabled; 1676#elif defined(__LITTLE_ENDIAN) 1677 u8 enabled; 1678 u8 reserved; 1679 u8 pfc_caps; 1680 u8 pri_en_bitmap; 1681 #define DCBX_PFC_PRI_0 0x01 1682 #define DCBX_PFC_PRI_1 0x02 1683 #define DCBX_PFC_PRI_2 0x04 1684 #define DCBX_PFC_PRI_3 0x08 1685 #define DCBX_PFC_PRI_4 0x10 1686 #define DCBX_PFC_PRI_5 0x20 1687 #define DCBX_PFC_PRI_6 0x40 1688 #define DCBX_PFC_PRI_7 0x80 1689#endif 1690}; 1691 1692struct dcbx_app_priority_entry { 1693#ifdef __BIG_ENDIAN 1694 u16 app_id; 1695 u8 pri_bitmap; 1696 u8 appBitfield; 1697 #define DCBX_APP_ENTRY_VALID 0x01 1698 #define DCBX_APP_ENTRY_SF_MASK 0x30 1699 #define DCBX_APP_ENTRY_SF_SHIFT 4 1700 #define DCBX_APP_SF_ETH_TYPE 0x10 1701 #define DCBX_APP_SF_PORT 0x20 1702#elif defined(__LITTLE_ENDIAN) 1703 u8 appBitfield; 1704 #define DCBX_APP_ENTRY_VALID 0x01 1705 #define DCBX_APP_ENTRY_SF_MASK 0x30 1706 #define DCBX_APP_ENTRY_SF_SHIFT 4 1707 #define DCBX_APP_SF_ETH_TYPE 0x10 1708 #define DCBX_APP_SF_PORT 0x20 1709 u8 pri_bitmap; 1710 u16 app_id; 1711#endif 1712}; 1713 1714 1715/* FW structure in BE */ 1716struct dcbx_app_priority_feature { 1717#ifdef __BIG_ENDIAN 1718 u8 reserved; 1719 u8 default_pri; 1720 u8 tc_supported; 1721 u8 enabled; 1722#elif defined(__LITTLE_ENDIAN) 1723 u8 enabled; 1724 u8 tc_supported; 1725 u8 default_pri; 1726 u8 reserved; 1727#endif 1728 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 1729}; 1730 1731/* FW structure in BE */ 1732struct dcbx_features { 1733 /* PG feature */ 1734 struct dcbx_ets_feature ets; 1735 /* PFC feature */ 1736 struct dcbx_pfc_feature pfc; 1737 /* APP feature */ 1738 struct dcbx_app_priority_feature app; 1739}; 1740 1741/* LLDP protocol parameters */ 1742/* FW structure in BE */ 1743struct lldp_params { 1744#ifdef __BIG_ENDIAN 1745 u8 msg_fast_tx_interval; 1746 u8 msg_tx_hold; 1747 u8 msg_tx_interval; 1748 u8 admin_status; 1749 #define LLDP_TX_ONLY 0x01 1750 #define LLDP_RX_ONLY 0x02 1751 #define LLDP_TX_RX 0x03 1752 #define LLDP_DISABLED 0x04 1753 u8 reserved1; 1754 u8 tx_fast; 1755 u8 tx_crd_max; 1756 u8 tx_crd; 1757#elif defined(__LITTLE_ENDIAN) 1758 u8 admin_status; 1759 #define LLDP_TX_ONLY 0x01 1760 #define LLDP_RX_ONLY 0x02 1761 #define LLDP_TX_RX 0x03 1762 #define LLDP_DISABLED 0x04 1763 u8 msg_tx_interval; 1764 u8 msg_tx_hold; 1765 u8 msg_fast_tx_interval; 1766 u8 tx_crd; 1767 u8 tx_crd_max; 1768 u8 tx_fast; 1769 u8 reserved1; 1770#endif 1771 #define REM_CHASSIS_ID_STAT_LEN 4 1772 #define REM_PORT_ID_STAT_LEN 4 1773 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 1774 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 1775 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 1776 u32 peer_port_id[REM_PORT_ID_STAT_LEN]; 1777}; 1778 1779struct lldp_dcbx_stat { 1780 #define LOCAL_CHASSIS_ID_STAT_LEN 2 1781 #define LOCAL_PORT_ID_STAT_LEN 2 1782 /* Holds local Chassis ID 8B payload of constant subtype 4. */ 1783 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 1784 /* Holds local Port ID 8B payload of constant subtype 3. */ 1785 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN]; 1786 /* Number of DCBX frames transmitted. */ 1787 u32 num_tx_dcbx_pkts; 1788 /* Number of DCBX frames received. */ 1789 u32 num_rx_dcbx_pkts; 1790}; 1791 1792/* ADMIN MIB - DCBX local machine default configuration. */ 1793struct lldp_admin_mib { 1794 u32 ver_cfg_flags; 1795 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 1796 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 1797 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 1798 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 1799 #define DCBX_ETS_RECO_VALID 0x00000010 1800 #define DCBX_ETS_WILLING 0x00000020 1801 #define DCBX_PFC_WILLING 0x00000040 1802 #define DCBX_APP_WILLING 0x00000080 1803 #define DCBX_VERSION_CEE 0x00000100 1804 #define DCBX_VERSION_IEEE 0x00000200 1805 #define DCBX_DCBX_ENABLED 0x00000400 1806 #define DCBX_CEE_VERSION_MASK 0x0000f000 1807 #define DCBX_CEE_VERSION_SHIFT 12 1808 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 1809 #define DCBX_CEE_MAX_VERSION_SHIFT 16 1810 struct dcbx_features features; 1811}; 1812 1813/* REMOTE MIB - remote machine DCBX configuration. */ 1814struct lldp_remote_mib { 1815 u32 prefix_seq_num; 1816 u32 flags; 1817 #define DCBX_ETS_TLV_RX 0x00000001 1818 #define DCBX_PFC_TLV_RX 0x00000002 1819 #define DCBX_APP_TLV_RX 0x00000004 1820 #define DCBX_ETS_RX_ERROR 0x00000010 1821 #define DCBX_PFC_RX_ERROR 0x00000020 1822 #define DCBX_APP_RX_ERROR 0x00000040 1823 #define DCBX_ETS_REM_WILLING 0x00000100 1824 #define DCBX_PFC_REM_WILLING 0x00000200 1825 #define DCBX_APP_REM_WILLING 0x00000400 1826 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 1827 #define DCBX_REMOTE_MIB_VALID 0x00002000 1828 struct dcbx_features features; 1829 u32 suffix_seq_num; 1830}; 1831 1832/* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ 1833struct lldp_local_mib { 1834 u32 prefix_seq_num; 1835 /* Indicates if there is mismatch with negotiation results. */ 1836 u32 error; 1837 #define DCBX_LOCAL_ETS_ERROR 0x00000001 1838 #define DCBX_LOCAL_PFC_ERROR 0x00000002 1839 #define DCBX_LOCAL_APP_ERROR 0x00000004 1840 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 1841 #define DCBX_LOCAL_APP_MISMATCH 0x00000020 1842 #define DCBX_REMOTE_MIB_ERROR 0x00000040 1843 struct dcbx_features features; 1844 u32 suffix_seq_num; 1845}; 1846/***END OF DCBX STRUCTURES DECLARATIONS***/ 1847 1848struct ncsi_oem_fcoe_features { 1849 u32 fcoe_features1; 1850 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF 1851 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0 1852 1853 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000 1854 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16 1855 1856 u32 fcoe_features2; 1857 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF 1858 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0 1859 1860 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000 1861 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16 1862 1863 u32 fcoe_features3; 1864 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF 1865 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0 1866 1867 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000 1868 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16 1869 1870 u32 fcoe_features4; 1871 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F 1872 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0 1873}; 1874 1875struct ncsi_oem_data { 1876 u32 driver_version[4]; 1877 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features; 1878}; 1879 1880struct shmem2_region { 1881 1882 u32 size; /* 0x0000 */ 1883 1884 u32 dcc_support; /* 0x0004 */ 1885 #define SHMEM_DCC_SUPPORT_NONE 0x00000000 1886 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 1887 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 1888 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 1889 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 1890 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 1891 1892 u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ 1893 /* 1894 * For backwards compatibility, if the mf_cfg_addr does not exist 1895 * (the size filed is smaller than 0xc) the mf_cfg resides at the 1896 * end of struct shmem_region 1897 */ 1898 u32 mf_cfg_addr; /* 0x0010 */ 1899 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 1900 1901 struct fw_flr_mb flr_mb; /* 0x0014 */ 1902 u32 dcbx_lldp_params_offset; /* 0x0028 */ 1903 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 1904 u32 dcbx_neg_res_offset; /* 0x002c */ 1905 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 1906 u32 dcbx_remote_mib_offset; /* 0x0030 */ 1907 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 1908 /* 1909 * The other shmemX_base_addr holds the other path's shmem address 1910 * required for example in case of common phy init, or for path1 to know 1911 * the address of mcp debug trace which is located in offset from shmem 1912 * of path0 1913 */ 1914 u32 other_shmem_base_addr; /* 0x0034 */ 1915 u32 other_shmem2_base_addr; /* 0x0038 */ 1916 /* 1917 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 1918 * which were disabled/flred 1919 */ 1920 u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ 1921 1922 /* 1923 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 1924 * VFs 1925 */ 1926 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ 1927 1928 u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ 1929 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 1930 1931 /* 1932 * edebug_driver_if field is used to transfer messages between edebug 1933 * app to the driver through shmem2. 1934 * 1935 * message format: 1936 * bits 0-2 - function number / instance of driver to perform request 1937 * bits 3-5 - op code / is_ack? 1938 * bits 6-63 - data 1939 */ 1940 u32 edebug_driver_if[2]; /* 0x0068 */ 1941 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 1942 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 1943 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 1944 1945 u32 nvm_retain_bitmap_addr; /* 0x0070 */ 1946 1947 u32 reserved1; /* 0x0074 */ 1948 1949 u32 reserved2[E2_FUNC_MAX]; 1950 1951 u32 reserved3[E2_FUNC_MAX];/* 0x0088 */ 1952 u32 reserved4[E2_FUNC_MAX];/* 0x0098 */ 1953 1954 u32 swim_base_addr; /* 0x0108 */ 1955 u32 swim_funcs; 1956 u32 swim_main_cb; 1957 1958 u32 reserved5[2]; 1959 1960 /* generic flags controlled by the driver */ 1961 u32 drv_flags; 1962 #define DRV_FLAGS_DCB_CONFIGURED 0x1 1963 1964 /* pointer to extended dev_info shared data copied from nvm image */ 1965 u32 extended_dev_info_shared_addr; 1966 u32 ncsi_oem_data_addr; 1967 1968 u32 ocsd_host_addr; 1969 u32 ocbb_host_addr; 1970 u32 ocsd_req_update_interval; 1971}; 1972 1973 1974struct emac_stats { 1975 u32 rx_stat_ifhcinoctets; 1976 u32 rx_stat_ifhcinbadoctets; 1977 u32 rx_stat_etherstatsfragments; 1978 u32 rx_stat_ifhcinucastpkts; 1979 u32 rx_stat_ifhcinmulticastpkts; 1980 u32 rx_stat_ifhcinbroadcastpkts; 1981 u32 rx_stat_dot3statsfcserrors; 1982 u32 rx_stat_dot3statsalignmenterrors; 1983 u32 rx_stat_dot3statscarriersenseerrors; 1984 u32 rx_stat_xonpauseframesreceived; 1985 u32 rx_stat_xoffpauseframesreceived; 1986 u32 rx_stat_maccontrolframesreceived; 1987 u32 rx_stat_xoffstateentered; 1988 u32 rx_stat_dot3statsframestoolong; 1989 u32 rx_stat_etherstatsjabbers; 1990 u32 rx_stat_etherstatsundersizepkts; 1991 u32 rx_stat_etherstatspkts64octets; 1992 u32 rx_stat_etherstatspkts65octetsto127octets; 1993 u32 rx_stat_etherstatspkts128octetsto255octets; 1994 u32 rx_stat_etherstatspkts256octetsto511octets; 1995 u32 rx_stat_etherstatspkts512octetsto1023octets; 1996 u32 rx_stat_etherstatspkts1024octetsto1522octets; 1997 u32 rx_stat_etherstatspktsover1522octets; 1998 1999 u32 rx_stat_falsecarriererrors; 2000 2001 u32 tx_stat_ifhcoutoctets; 2002 u32 tx_stat_ifhcoutbadoctets; 2003 u32 tx_stat_etherstatscollisions; 2004 u32 tx_stat_outxonsent; 2005 u32 tx_stat_outxoffsent; 2006 u32 tx_stat_flowcontroldone; 2007 u32 tx_stat_dot3statssinglecollisionframes; 2008 u32 tx_stat_dot3statsmultiplecollisionframes; 2009 u32 tx_stat_dot3statsdeferredtransmissions; 2010 u32 tx_stat_dot3statsexcessivecollisions; 2011 u32 tx_stat_dot3statslatecollisions; 2012 u32 tx_stat_ifhcoutucastpkts; 2013 u32 tx_stat_ifhcoutmulticastpkts; 2014 u32 tx_stat_ifhcoutbroadcastpkts; 2015 u32 tx_stat_etherstatspkts64octets; 2016 u32 tx_stat_etherstatspkts65octetsto127octets; 2017 u32 tx_stat_etherstatspkts128octetsto255octets; 2018 u32 tx_stat_etherstatspkts256octetsto511octets; 2019 u32 tx_stat_etherstatspkts512octetsto1023octets; 2020 u32 tx_stat_etherstatspkts1024octetsto1522octets; 2021 u32 tx_stat_etherstatspktsover1522octets; 2022 u32 tx_stat_dot3statsinternalmactransmiterrors; 2023}; 2024 2025 2026struct bmac1_stats { 2027 u32 tx_stat_gtpkt_lo; 2028 u32 tx_stat_gtpkt_hi; 2029 u32 tx_stat_gtxpf_lo; 2030 u32 tx_stat_gtxpf_hi; 2031 u32 tx_stat_gtfcs_lo; 2032 u32 tx_stat_gtfcs_hi; 2033 u32 tx_stat_gtmca_lo; 2034 u32 tx_stat_gtmca_hi; 2035 u32 tx_stat_gtbca_lo; 2036 u32 tx_stat_gtbca_hi; 2037 u32 tx_stat_gtfrg_lo; 2038 u32 tx_stat_gtfrg_hi; 2039 u32 tx_stat_gtovr_lo; 2040 u32 tx_stat_gtovr_hi; 2041 u32 tx_stat_gt64_lo; 2042 u32 tx_stat_gt64_hi; 2043 u32 tx_stat_gt127_lo; 2044 u32 tx_stat_gt127_hi; 2045 u32 tx_stat_gt255_lo; 2046 u32 tx_stat_gt255_hi; 2047 u32 tx_stat_gt511_lo; 2048 u32 tx_stat_gt511_hi; 2049 u32 tx_stat_gt1023_lo; 2050 u32 tx_stat_gt1023_hi; 2051 u32 tx_stat_gt1518_lo; 2052 u32 tx_stat_gt1518_hi; 2053 u32 tx_stat_gt2047_lo; 2054 u32 tx_stat_gt2047_hi; 2055 u32 tx_stat_gt4095_lo; 2056 u32 tx_stat_gt4095_hi; 2057 u32 tx_stat_gt9216_lo; 2058 u32 tx_stat_gt9216_hi; 2059 u32 tx_stat_gt16383_lo; 2060 u32 tx_stat_gt16383_hi; 2061 u32 tx_stat_gtmax_lo; 2062 u32 tx_stat_gtmax_hi; 2063 u32 tx_stat_gtufl_lo; 2064 u32 tx_stat_gtufl_hi; 2065 u32 tx_stat_gterr_lo; 2066 u32 tx_stat_gterr_hi; 2067 u32 tx_stat_gtbyt_lo; 2068 u32 tx_stat_gtbyt_hi; 2069 2070 u32 rx_stat_gr64_lo; 2071 u32 rx_stat_gr64_hi; 2072 u32 rx_stat_gr127_lo; 2073 u32 rx_stat_gr127_hi; 2074 u32 rx_stat_gr255_lo; 2075 u32 rx_stat_gr255_hi; 2076 u32 rx_stat_gr511_lo; 2077 u32 rx_stat_gr511_hi; 2078 u32 rx_stat_gr1023_lo; 2079 u32 rx_stat_gr1023_hi; 2080 u32 rx_stat_gr1518_lo; 2081 u32 rx_stat_gr1518_hi; 2082 u32 rx_stat_gr2047_lo; 2083 u32 rx_stat_gr2047_hi; 2084 u32 rx_stat_gr4095_lo; 2085 u32 rx_stat_gr4095_hi; 2086 u32 rx_stat_gr9216_lo; 2087 u32 rx_stat_gr9216_hi; 2088 u32 rx_stat_gr16383_lo; 2089 u32 rx_stat_gr16383_hi; 2090 u32 rx_stat_grmax_lo; 2091 u32 rx_stat_grmax_hi; 2092 u32 rx_stat_grpkt_lo; 2093 u32 rx_stat_grpkt_hi; 2094 u32 rx_stat_grfcs_lo; 2095 u32 rx_stat_grfcs_hi; 2096 u32 rx_stat_grmca_lo; 2097 u32 rx_stat_grmca_hi; 2098 u32 rx_stat_grbca_lo; 2099 u32 rx_stat_grbca_hi; 2100 u32 rx_stat_grxcf_lo; 2101 u32 rx_stat_grxcf_hi; 2102 u32 rx_stat_grxpf_lo; 2103 u32 rx_stat_grxpf_hi; 2104 u32 rx_stat_grxuo_lo; 2105 u32 rx_stat_grxuo_hi; 2106 u32 rx_stat_grjbr_lo; 2107 u32 rx_stat_grjbr_hi; 2108 u32 rx_stat_grovr_lo; 2109 u32 rx_stat_grovr_hi; 2110 u32 rx_stat_grflr_lo; 2111 u32 rx_stat_grflr_hi; 2112 u32 rx_stat_grmeg_lo; 2113 u32 rx_stat_grmeg_hi; 2114 u32 rx_stat_grmeb_lo; 2115 u32 rx_stat_grmeb_hi; 2116 u32 rx_stat_grbyt_lo; 2117 u32 rx_stat_grbyt_hi; 2118 u32 rx_stat_grund_lo; 2119 u32 rx_stat_grund_hi; 2120 u32 rx_stat_grfrg_lo; 2121 u32 rx_stat_grfrg_hi; 2122 u32 rx_stat_grerb_lo; 2123 u32 rx_stat_grerb_hi; 2124 u32 rx_stat_grfre_lo; 2125 u32 rx_stat_grfre_hi; 2126 u32 rx_stat_gripj_lo; 2127 u32 rx_stat_gripj_hi; 2128}; 2129 2130struct bmac2_stats { 2131 u32 tx_stat_gtpk_lo; /* gtpok */ 2132 u32 tx_stat_gtpk_hi; /* gtpok */ 2133 u32 tx_stat_gtxpf_lo; /* gtpf */ 2134 u32 tx_stat_gtxpf_hi; /* gtpf */ 2135 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */ 2136 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */ 2137 u32 tx_stat_gtfcs_lo; 2138 u32 tx_stat_gtfcs_hi; 2139 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */ 2140 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */ 2141 u32 tx_stat_gtmca_lo; 2142 u32 tx_stat_gtmca_hi; 2143 u32 tx_stat_gtbca_lo; 2144 u32 tx_stat_gtbca_hi; 2145 u32 tx_stat_gtovr_lo; 2146 u32 tx_stat_gtovr_hi; 2147 u32 tx_stat_gtfrg_lo; 2148 u32 tx_stat_gtfrg_hi; 2149 u32 tx_stat_gtpkt1_lo; /* gtpkt */ 2150 u32 tx_stat_gtpkt1_hi; /* gtpkt */ 2151 u32 tx_stat_gt64_lo; 2152 u32 tx_stat_gt64_hi; 2153 u32 tx_stat_gt127_lo; 2154 u32 tx_stat_gt127_hi; 2155 u32 tx_stat_gt255_lo; 2156 u32 tx_stat_gt255_hi; 2157 u32 tx_stat_gt511_lo; 2158 u32 tx_stat_gt511_hi; 2159 u32 tx_stat_gt1023_lo; 2160 u32 tx_stat_gt1023_hi; 2161 u32 tx_stat_gt1518_lo; 2162 u32 tx_stat_gt1518_hi; 2163 u32 tx_stat_gt2047_lo; 2164 u32 tx_stat_gt2047_hi; 2165 u32 tx_stat_gt4095_lo; 2166 u32 tx_stat_gt4095_hi; 2167 u32 tx_stat_gt9216_lo; 2168 u32 tx_stat_gt9216_hi; 2169 u32 tx_stat_gt16383_lo; 2170 u32 tx_stat_gt16383_hi; 2171 u32 tx_stat_gtmax_lo; 2172 u32 tx_stat_gtmax_hi; 2173 u32 tx_stat_gtufl_lo; 2174 u32 tx_stat_gtufl_hi; 2175 u32 tx_stat_gterr_lo; 2176 u32 tx_stat_gterr_hi; 2177 u32 tx_stat_gtbyt_lo; 2178 u32 tx_stat_gtbyt_hi; 2179 2180 u32 rx_stat_gr64_lo; 2181 u32 rx_stat_gr64_hi; 2182 u32 rx_stat_gr127_lo; 2183 u32 rx_stat_gr127_hi; 2184 u32 rx_stat_gr255_lo; 2185 u32 rx_stat_gr255_hi; 2186 u32 rx_stat_gr511_lo; 2187 u32 rx_stat_gr511_hi; 2188 u32 rx_stat_gr1023_lo; 2189 u32 rx_stat_gr1023_hi; 2190 u32 rx_stat_gr1518_lo; 2191 u32 rx_stat_gr1518_hi; 2192 u32 rx_stat_gr2047_lo; 2193 u32 rx_stat_gr2047_hi; 2194 u32 rx_stat_gr4095_lo; 2195 u32 rx_stat_gr4095_hi; 2196 u32 rx_stat_gr9216_lo; 2197 u32 rx_stat_gr9216_hi; 2198 u32 rx_stat_gr16383_lo; 2199 u32 rx_stat_gr16383_hi; 2200 u32 rx_stat_grmax_lo; 2201 u32 rx_stat_grmax_hi; 2202 u32 rx_stat_grpkt_lo; 2203 u32 rx_stat_grpkt_hi; 2204 u32 rx_stat_grfcs_lo; 2205 u32 rx_stat_grfcs_hi; 2206 u32 rx_stat_gruca_lo; 2207 u32 rx_stat_gruca_hi; 2208 u32 rx_stat_grmca_lo; 2209 u32 rx_stat_grmca_hi; 2210 u32 rx_stat_grbca_lo; 2211 u32 rx_stat_grbca_hi; 2212 u32 rx_stat_grxpf_lo; /* grpf */ 2213 u32 rx_stat_grxpf_hi; /* grpf */ 2214 u32 rx_stat_grpp_lo; 2215 u32 rx_stat_grpp_hi; 2216 u32 rx_stat_grxuo_lo; /* gruo */ 2217 u32 rx_stat_grxuo_hi; /* gruo */ 2218 u32 rx_stat_grjbr_lo; 2219 u32 rx_stat_grjbr_hi; 2220 u32 rx_stat_grovr_lo; 2221 u32 rx_stat_grovr_hi; 2222 u32 rx_stat_grxcf_lo; /* grcf */ 2223 u32 rx_stat_grxcf_hi; /* grcf */ 2224 u32 rx_stat_grflr_lo; 2225 u32 rx_stat_grflr_hi; 2226 u32 rx_stat_grpok_lo; 2227 u32 rx_stat_grpok_hi; 2228 u32 rx_stat_grmeg_lo; 2229 u32 rx_stat_grmeg_hi; 2230 u32 rx_stat_grmeb_lo; 2231 u32 rx_stat_grmeb_hi; 2232 u32 rx_stat_grbyt_lo; 2233 u32 rx_stat_grbyt_hi; 2234 u32 rx_stat_grund_lo; 2235 u32 rx_stat_grund_hi; 2236 u32 rx_stat_grfrg_lo; 2237 u32 rx_stat_grfrg_hi; 2238 u32 rx_stat_grerb_lo; /* grerrbyt */ 2239 u32 rx_stat_grerb_hi; /* grerrbyt */ 2240 u32 rx_stat_grfre_lo; /* grfrerr */ 2241 u32 rx_stat_grfre_hi; /* grfrerr */ 2242 u32 rx_stat_gripj_lo; 2243 u32 rx_stat_gripj_hi; 2244}; 2245 2246struct mstat_stats { 2247 struct { 2248 /* OTE MSTAT on E3 has a bug where this register's contents are 2249 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp 2250 */ 2251 u32 tx_gtxpok_lo; 2252 u32 tx_gtxpok_hi; 2253 u32 tx_gtxpf_lo; 2254 u32 tx_gtxpf_hi; 2255 u32 tx_gtxpp_lo; 2256 u32 tx_gtxpp_hi; 2257 u32 tx_gtfcs_lo; 2258 u32 tx_gtfcs_hi; 2259 u32 tx_gtuca_lo; 2260 u32 tx_gtuca_hi; 2261 u32 tx_gtmca_lo; 2262 u32 tx_gtmca_hi; 2263 u32 tx_gtgca_lo; 2264 u32 tx_gtgca_hi; 2265 u32 tx_gtpkt_lo; 2266 u32 tx_gtpkt_hi; 2267 u32 tx_gt64_lo; 2268 u32 tx_gt64_hi; 2269 u32 tx_gt127_lo; 2270 u32 tx_gt127_hi; 2271 u32 tx_gt255_lo; 2272 u32 tx_gt255_hi; 2273 u32 tx_gt511_lo; 2274 u32 tx_gt511_hi; 2275 u32 tx_gt1023_lo; 2276 u32 tx_gt1023_hi; 2277 u32 tx_gt1518_lo; 2278 u32 tx_gt1518_hi; 2279 u32 tx_gt2047_lo; 2280 u32 tx_gt2047_hi; 2281 u32 tx_gt4095_lo; 2282 u32 tx_gt4095_hi; 2283 u32 tx_gt9216_lo; 2284 u32 tx_gt9216_hi; 2285 u32 tx_gt16383_lo; 2286 u32 tx_gt16383_hi; 2287 u32 tx_gtufl_lo; 2288 u32 tx_gtufl_hi; 2289 u32 tx_gterr_lo; 2290 u32 tx_gterr_hi; 2291 u32 tx_gtbyt_lo; 2292 u32 tx_gtbyt_hi; 2293 u32 tx_collisions_lo; 2294 u32 tx_collisions_hi; 2295 u32 tx_singlecollision_lo; 2296 u32 tx_singlecollision_hi; 2297 u32 tx_multiplecollisions_lo; 2298 u32 tx_multiplecollisions_hi; 2299 u32 tx_deferred_lo; 2300 u32 tx_deferred_hi; 2301 u32 tx_excessivecollisions_lo; 2302 u32 tx_excessivecollisions_hi; 2303 u32 tx_latecollisions_lo; 2304 u32 tx_latecollisions_hi; 2305 } stats_tx; 2306 2307 struct { 2308 u32 rx_gr64_lo; 2309 u32 rx_gr64_hi; 2310 u32 rx_gr127_lo; 2311 u32 rx_gr127_hi; 2312 u32 rx_gr255_lo; 2313 u32 rx_gr255_hi; 2314 u32 rx_gr511_lo; 2315 u32 rx_gr511_hi; 2316 u32 rx_gr1023_lo; 2317 u32 rx_gr1023_hi; 2318 u32 rx_gr1518_lo; 2319 u32 rx_gr1518_hi; 2320 u32 rx_gr2047_lo; 2321 u32 rx_gr2047_hi; 2322 u32 rx_gr4095_lo; 2323 u32 rx_gr4095_hi; 2324 u32 rx_gr9216_lo; 2325 u32 rx_gr9216_hi; 2326 u32 rx_gr16383_lo; 2327 u32 rx_gr16383_hi; 2328 u32 rx_grpkt_lo; 2329 u32 rx_grpkt_hi; 2330 u32 rx_grfcs_lo; 2331 u32 rx_grfcs_hi; 2332 u32 rx_gruca_lo; 2333 u32 rx_gruca_hi; 2334 u32 rx_grmca_lo; 2335 u32 rx_grmca_hi; 2336 u32 rx_grbca_lo; 2337 u32 rx_grbca_hi; 2338 u32 rx_grxpf_lo; 2339 u32 rx_grxpf_hi; 2340 u32 rx_grxpp_lo; 2341 u32 rx_grxpp_hi; 2342 u32 rx_grxuo_lo; 2343 u32 rx_grxuo_hi; 2344 u32 rx_grovr_lo; 2345 u32 rx_grovr_hi; 2346 u32 rx_grxcf_lo; 2347 u32 rx_grxcf_hi; 2348 u32 rx_grflr_lo; 2349 u32 rx_grflr_hi; 2350 u32 rx_grpok_lo; 2351 u32 rx_grpok_hi; 2352 u32 rx_grbyt_lo; 2353 u32 rx_grbyt_hi; 2354 u32 rx_grund_lo; 2355 u32 rx_grund_hi; 2356 u32 rx_grfrg_lo; 2357 u32 rx_grfrg_hi; 2358 u32 rx_grerb_lo; 2359 u32 rx_grerb_hi; 2360 u32 rx_grfre_lo; 2361 u32 rx_grfre_hi; 2362 2363 u32 rx_alignmenterrors_lo; 2364 u32 rx_alignmenterrors_hi; 2365 u32 rx_falsecarrier_lo; 2366 u32 rx_falsecarrier_hi; 2367 u32 rx_llfcmsgcnt_lo; 2368 u32 rx_llfcmsgcnt_hi; 2369 } stats_rx; 2370}; 2371 2372union mac_stats { 2373 struct emac_stats emac_stats; 2374 struct bmac1_stats bmac1_stats; 2375 struct bmac2_stats bmac2_stats; 2376 struct mstat_stats mstat_stats; 2377}; 2378 2379 2380struct mac_stx { 2381 /* in_bad_octets */ 2382 u32 rx_stat_ifhcinbadoctets_hi; 2383 u32 rx_stat_ifhcinbadoctets_lo; 2384 2385 /* out_bad_octets */ 2386 u32 tx_stat_ifhcoutbadoctets_hi; 2387 u32 tx_stat_ifhcoutbadoctets_lo; 2388 2389 /* crc_receive_errors */ 2390 u32 rx_stat_dot3statsfcserrors_hi; 2391 u32 rx_stat_dot3statsfcserrors_lo; 2392 /* alignment_errors */ 2393 u32 rx_stat_dot3statsalignmenterrors_hi; 2394 u32 rx_stat_dot3statsalignmenterrors_lo; 2395 /* carrier_sense_errors */ 2396 u32 rx_stat_dot3statscarriersenseerrors_hi; 2397 u32 rx_stat_dot3statscarriersenseerrors_lo; 2398 /* false_carrier_detections */ 2399 u32 rx_stat_falsecarriererrors_hi; 2400 u32 rx_stat_falsecarriererrors_lo; 2401 2402 /* runt_packets_received */ 2403 u32 rx_stat_etherstatsundersizepkts_hi; 2404 u32 rx_stat_etherstatsundersizepkts_lo; 2405 /* jabber_packets_received */ 2406 u32 rx_stat_dot3statsframestoolong_hi; 2407 u32 rx_stat_dot3statsframestoolong_lo; 2408 2409 /* error_runt_packets_received */ 2410 u32 rx_stat_etherstatsfragments_hi; 2411 u32 rx_stat_etherstatsfragments_lo; 2412 /* error_jabber_packets_received */ 2413 u32 rx_stat_etherstatsjabbers_hi; 2414 u32 rx_stat_etherstatsjabbers_lo; 2415 2416 /* control_frames_received */ 2417 u32 rx_stat_maccontrolframesreceived_hi; 2418 u32 rx_stat_maccontrolframesreceived_lo; 2419 u32 rx_stat_mac_xpf_hi; 2420 u32 rx_stat_mac_xpf_lo; 2421 u32 rx_stat_mac_xcf_hi; 2422 u32 rx_stat_mac_xcf_lo; 2423 2424 /* xoff_state_entered */ 2425 u32 rx_stat_xoffstateentered_hi; 2426 u32 rx_stat_xoffstateentered_lo; 2427 /* pause_xon_frames_received */ 2428 u32 rx_stat_xonpauseframesreceived_hi; 2429 u32 rx_stat_xonpauseframesreceived_lo; 2430 /* pause_xoff_frames_received */ 2431 u32 rx_stat_xoffpauseframesreceived_hi; 2432 u32 rx_stat_xoffpauseframesreceived_lo; 2433 /* pause_xon_frames_transmitted */ 2434 u32 tx_stat_outxonsent_hi; 2435 u32 tx_stat_outxonsent_lo; 2436 /* pause_xoff_frames_transmitted */ 2437 u32 tx_stat_outxoffsent_hi; 2438 u32 tx_stat_outxoffsent_lo; 2439 /* flow_control_done */ 2440 u32 tx_stat_flowcontroldone_hi; 2441 u32 tx_stat_flowcontroldone_lo; 2442 2443 /* ether_stats_collisions */ 2444 u32 tx_stat_etherstatscollisions_hi; 2445 u32 tx_stat_etherstatscollisions_lo; 2446 /* single_collision_transmit_frames */ 2447 u32 tx_stat_dot3statssinglecollisionframes_hi; 2448 u32 tx_stat_dot3statssinglecollisionframes_lo; 2449 /* multiple_collision_transmit_frames */ 2450 u32 tx_stat_dot3statsmultiplecollisionframes_hi; 2451 u32 tx_stat_dot3statsmultiplecollisionframes_lo; 2452 /* deferred_transmissions */ 2453 u32 tx_stat_dot3statsdeferredtransmissions_hi; 2454 u32 tx_stat_dot3statsdeferredtransmissions_lo; 2455 /* excessive_collision_frames */ 2456 u32 tx_stat_dot3statsexcessivecollisions_hi; 2457 u32 tx_stat_dot3statsexcessivecollisions_lo; 2458 /* late_collision_frames */ 2459 u32 tx_stat_dot3statslatecollisions_hi; 2460 u32 tx_stat_dot3statslatecollisions_lo; 2461 2462 /* frames_transmitted_64_bytes */ 2463 u32 tx_stat_etherstatspkts64octets_hi; 2464 u32 tx_stat_etherstatspkts64octets_lo; 2465 /* frames_transmitted_65_127_bytes */ 2466 u32 tx_stat_etherstatspkts65octetsto127octets_hi; 2467 u32 tx_stat_etherstatspkts65octetsto127octets_lo; 2468 /* frames_transmitted_128_255_bytes */ 2469 u32 tx_stat_etherstatspkts128octetsto255octets_hi; 2470 u32 tx_stat_etherstatspkts128octetsto255octets_lo; 2471 /* frames_transmitted_256_511_bytes */ 2472 u32 tx_stat_etherstatspkts256octetsto511octets_hi; 2473 u32 tx_stat_etherstatspkts256octetsto511octets_lo; 2474 /* frames_transmitted_512_1023_bytes */ 2475 u32 tx_stat_etherstatspkts512octetsto1023octets_hi; 2476 u32 tx_stat_etherstatspkts512octetsto1023octets_lo; 2477 /* frames_transmitted_1024_1522_bytes */ 2478 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; 2479 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; 2480 /* frames_transmitted_1523_9022_bytes */ 2481 u32 tx_stat_etherstatspktsover1522octets_hi; 2482 u32 tx_stat_etherstatspktsover1522octets_lo; 2483 u32 tx_stat_mac_2047_hi; 2484 u32 tx_stat_mac_2047_lo; 2485 u32 tx_stat_mac_4095_hi; 2486 u32 tx_stat_mac_4095_lo; 2487 u32 tx_stat_mac_9216_hi; 2488 u32 tx_stat_mac_9216_lo; 2489 u32 tx_stat_mac_16383_hi; 2490 u32 tx_stat_mac_16383_lo; 2491 2492 /* internal_mac_transmit_errors */ 2493 u32 tx_stat_dot3statsinternalmactransmiterrors_hi; 2494 u32 tx_stat_dot3statsinternalmactransmiterrors_lo; 2495 2496 /* if_out_discards */ 2497 u32 tx_stat_mac_ufl_hi; 2498 u32 tx_stat_mac_ufl_lo; 2499}; 2500 2501 2502#define MAC_STX_IDX_MAX 2 2503 2504struct host_port_stats { 2505 u32 host_port_stats_counter; 2506 2507 struct mac_stx mac_stx[MAC_STX_IDX_MAX]; 2508 2509 u32 brb_drop_hi; 2510 u32 brb_drop_lo; 2511 2512 u32 not_used; /* obsolete */ 2513 u32 pfc_frames_tx_hi; 2514 u32 pfc_frames_tx_lo; 2515 u32 pfc_frames_rx_hi; 2516 u32 pfc_frames_rx_lo; 2517}; 2518 2519 2520struct host_func_stats { 2521 u32 host_func_stats_start; 2522 2523 u32 total_bytes_received_hi; 2524 u32 total_bytes_received_lo; 2525 2526 u32 total_bytes_transmitted_hi; 2527 u32 total_bytes_transmitted_lo; 2528 2529 u32 total_unicast_packets_received_hi; 2530 u32 total_unicast_packets_received_lo; 2531 2532 u32 total_multicast_packets_received_hi; 2533 u32 total_multicast_packets_received_lo; 2534 2535 u32 total_broadcast_packets_received_hi; 2536 u32 total_broadcast_packets_received_lo; 2537 2538 u32 total_unicast_packets_transmitted_hi; 2539 u32 total_unicast_packets_transmitted_lo; 2540 2541 u32 total_multicast_packets_transmitted_hi; 2542 u32 total_multicast_packets_transmitted_lo; 2543 2544 u32 total_broadcast_packets_transmitted_hi; 2545 u32 total_broadcast_packets_transmitted_lo; 2546 2547 u32 valid_bytes_received_hi; 2548 u32 valid_bytes_received_lo; 2549 2550 u32 host_func_stats_end; 2551}; 2552 2553/* VIC definitions */ 2554#define VICSTATST_UIF_INDEX 2 2555 2556#define BCM_5710_FW_MAJOR_VERSION 7 2557#define BCM_5710_FW_MINOR_VERSION 0 2558#define BCM_5710_FW_REVISION_VERSION 29 2559#define BCM_5710_FW_ENGINEERING_VERSION 0 2560#define BCM_5710_FW_COMPILE_FLAGS 1 2561 2562 2563/* 2564 * attention bits 2565 */ 2566struct atten_sp_status_block { 2567 __le32 attn_bits; 2568 __le32 attn_bits_ack; 2569 u8 status_block_id; 2570 u8 reserved0; 2571 __le16 attn_bits_index; 2572 __le32 reserved1; 2573}; 2574 2575 2576/* 2577 * The eth aggregative context of Cstorm 2578 */ 2579struct cstorm_eth_ag_context { 2580 u32 __reserved0[10]; 2581}; 2582 2583 2584/* 2585 * dmae command structure 2586 */ 2587struct dmae_command { 2588 u32 opcode; 2589#define DMAE_COMMAND_SRC (0x1<<0) 2590#define DMAE_COMMAND_SRC_SHIFT 0 2591#define DMAE_COMMAND_DST (0x3<<1) 2592#define DMAE_COMMAND_DST_SHIFT 1 2593#define DMAE_COMMAND_C_DST (0x1<<3) 2594#define DMAE_COMMAND_C_DST_SHIFT 3 2595#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) 2596#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 2597#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) 2598#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 2599#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) 2600#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 2601#define DMAE_COMMAND_ENDIANITY (0x3<<9) 2602#define DMAE_COMMAND_ENDIANITY_SHIFT 9 2603#define DMAE_COMMAND_PORT (0x1<<11) 2604#define DMAE_COMMAND_PORT_SHIFT 11 2605#define DMAE_COMMAND_CRC_RESET (0x1<<12) 2606#define DMAE_COMMAND_CRC_RESET_SHIFT 12 2607#define DMAE_COMMAND_SRC_RESET (0x1<<13) 2608#define DMAE_COMMAND_SRC_RESET_SHIFT 13 2609#define DMAE_COMMAND_DST_RESET (0x1<<14) 2610#define DMAE_COMMAND_DST_RESET_SHIFT 14 2611#define DMAE_COMMAND_E1HVN (0x3<<15) 2612#define DMAE_COMMAND_E1HVN_SHIFT 15 2613#define DMAE_COMMAND_DST_VN (0x3<<17) 2614#define DMAE_COMMAND_DST_VN_SHIFT 17 2615#define DMAE_COMMAND_C_FUNC (0x1<<19) 2616#define DMAE_COMMAND_C_FUNC_SHIFT 19 2617#define DMAE_COMMAND_ERR_POLICY (0x3<<20) 2618#define DMAE_COMMAND_ERR_POLICY_SHIFT 20 2619#define DMAE_COMMAND_RESERVED0 (0x3FF<<22) 2620#define DMAE_COMMAND_RESERVED0_SHIFT 22 2621 u32 src_addr_lo; 2622 u32 src_addr_hi; 2623 u32 dst_addr_lo; 2624 u32 dst_addr_hi; 2625#if defined(__BIG_ENDIAN) 2626 u16 opcode_iov; 2627#define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2628#define DMAE_COMMAND_SRC_VFID_SHIFT 0 2629#define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2630#define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2631#define DMAE_COMMAND_RESERVED1 (0x1<<7) 2632#define DMAE_COMMAND_RESERVED1_SHIFT 7 2633#define DMAE_COMMAND_DST_VFID (0x3F<<8) 2634#define DMAE_COMMAND_DST_VFID_SHIFT 8 2635#define DMAE_COMMAND_DST_VFPF (0x1<<14) 2636#define DMAE_COMMAND_DST_VFPF_SHIFT 14 2637#define DMAE_COMMAND_RESERVED2 (0x1<<15) 2638#define DMAE_COMMAND_RESERVED2_SHIFT 15 2639 u16 len; 2640#elif defined(__LITTLE_ENDIAN) 2641 u16 len; 2642 u16 opcode_iov; 2643#define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2644#define DMAE_COMMAND_SRC_VFID_SHIFT 0 2645#define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2646#define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2647#define DMAE_COMMAND_RESERVED1 (0x1<<7) 2648#define DMAE_COMMAND_RESERVED1_SHIFT 7 2649#define DMAE_COMMAND_DST_VFID (0x3F<<8) 2650#define DMAE_COMMAND_DST_VFID_SHIFT 8 2651#define DMAE_COMMAND_DST_VFPF (0x1<<14) 2652#define DMAE_COMMAND_DST_VFPF_SHIFT 14 2653#define DMAE_COMMAND_RESERVED2 (0x1<<15) 2654#define DMAE_COMMAND_RESERVED2_SHIFT 15 2655#endif 2656 u32 comp_addr_lo; 2657 u32 comp_addr_hi; 2658 u32 comp_val; 2659 u32 crc32; 2660 u32 crc32_c; 2661#if defined(__BIG_ENDIAN) 2662 u16 crc16_c; 2663 u16 crc16; 2664#elif defined(__LITTLE_ENDIAN) 2665 u16 crc16; 2666 u16 crc16_c; 2667#endif 2668#if defined(__BIG_ENDIAN) 2669 u16 reserved3; 2670 u16 crc_t10; 2671#elif defined(__LITTLE_ENDIAN) 2672 u16 crc_t10; 2673 u16 reserved3; 2674#endif 2675#if defined(__BIG_ENDIAN) 2676 u16 xsum8; 2677 u16 xsum16; 2678#elif defined(__LITTLE_ENDIAN) 2679 u16 xsum16; 2680 u16 xsum8; 2681#endif 2682}; 2683 2684 2685/* 2686 * common data for all protocols 2687 */ 2688struct doorbell_hdr { 2689 u8 header; 2690#define DOORBELL_HDR_RX (0x1<<0) 2691#define DOORBELL_HDR_RX_SHIFT 0 2692#define DOORBELL_HDR_DB_TYPE (0x1<<1) 2693#define DOORBELL_HDR_DB_TYPE_SHIFT 1 2694#define DOORBELL_HDR_DPM_SIZE (0x3<<2) 2695#define DOORBELL_HDR_DPM_SIZE_SHIFT 2 2696#define DOORBELL_HDR_CONN_TYPE (0xF<<4) 2697#define DOORBELL_HDR_CONN_TYPE_SHIFT 4 2698}; 2699 2700/* 2701 * Ethernet doorbell 2702 */ 2703struct eth_tx_doorbell { 2704#if defined(__BIG_ENDIAN) 2705 u16 npackets; 2706 u8 params; 2707#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 2708#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 2709#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 2710#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 2711#define ETH_TX_DOORBELL_SPARE (0x1<<7) 2712#define ETH_TX_DOORBELL_SPARE_SHIFT 7 2713 struct doorbell_hdr hdr; 2714#elif defined(__LITTLE_ENDIAN) 2715 struct doorbell_hdr hdr; 2716 u8 params; 2717#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 2718#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 2719#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 2720#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 2721#define ETH_TX_DOORBELL_SPARE (0x1<<7) 2722#define ETH_TX_DOORBELL_SPARE_SHIFT 7 2723 u16 npackets; 2724#endif 2725}; 2726 2727 2728/* 2729 * 3 lines. status block 2730 */ 2731struct hc_status_block_e1x { 2732 __le16 index_values[HC_SB_MAX_INDICES_E1X]; 2733 __le16 running_index[HC_SB_MAX_SM]; 2734 __le32 rsrv[11]; 2735}; 2736 2737/* 2738 * host status block 2739 */ 2740struct host_hc_status_block_e1x { 2741 struct hc_status_block_e1x sb; 2742}; 2743 2744 2745/* 2746 * 3 lines. status block 2747 */ 2748struct hc_status_block_e2 { 2749 __le16 index_values[HC_SB_MAX_INDICES_E2]; 2750 __le16 running_index[HC_SB_MAX_SM]; 2751 __le32 reserved[11]; 2752}; 2753 2754/* 2755 * host status block 2756 */ 2757struct host_hc_status_block_e2 { 2758 struct hc_status_block_e2 sb; 2759}; 2760 2761 2762/* 2763 * 5 lines. slow-path status block 2764 */ 2765struct hc_sp_status_block { 2766 __le16 index_values[HC_SP_SB_MAX_INDICES]; 2767 __le16 running_index; 2768 __le16 rsrv; 2769 u32 rsrv1; 2770}; 2771 2772/* 2773 * host status block 2774 */ 2775struct host_sp_status_block { 2776 struct atten_sp_status_block atten_status_block; 2777 struct hc_sp_status_block sp_sb; 2778}; 2779 2780 2781/* 2782 * IGU driver acknowledgment register 2783 */ 2784struct igu_ack_register { 2785#if defined(__BIG_ENDIAN) 2786 u16 sb_id_and_flags; 2787#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 2788#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 2789#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 2790#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 2791#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 2792#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 2793#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 2794#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 2795#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 2796#define IGU_ACK_REGISTER_RESERVED_SHIFT 11 2797 u16 status_block_index; 2798#elif defined(__LITTLE_ENDIAN) 2799 u16 status_block_index; 2800 u16 sb_id_and_flags; 2801#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 2802#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 2803#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 2804#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 2805#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 2806#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 2807#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 2808#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 2809#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 2810#define IGU_ACK_REGISTER_RESERVED_SHIFT 11 2811#endif 2812}; 2813 2814 2815/* 2816 * IGU driver acknowledgement register 2817 */ 2818struct igu_backward_compatible { 2819 u32 sb_id_and_flags; 2820#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) 2821#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 2822#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) 2823#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 2824#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) 2825#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 2826#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) 2827#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 2828#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) 2829#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 2830#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) 2831#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 2832 u32 reserved_2; 2833}; 2834 2835 2836/* 2837 * IGU driver acknowledgement register 2838 */ 2839struct igu_regular { 2840 u32 sb_id_and_flags; 2841#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) 2842#define IGU_REGULAR_SB_INDEX_SHIFT 0 2843#define IGU_REGULAR_RESERVED0 (0x1<<20) 2844#define IGU_REGULAR_RESERVED0_SHIFT 20 2845#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) 2846#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 2847#define IGU_REGULAR_BUPDATE (0x1<<24) 2848#define IGU_REGULAR_BUPDATE_SHIFT 24 2849#define IGU_REGULAR_ENABLE_INT (0x3<<25) 2850#define IGU_REGULAR_ENABLE_INT_SHIFT 25 2851#define IGU_REGULAR_RESERVED_1 (0x1<<27) 2852#define IGU_REGULAR_RESERVED_1_SHIFT 27 2853#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) 2854#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 2855#define IGU_REGULAR_CLEANUP_SET (0x1<<30) 2856#define IGU_REGULAR_CLEANUP_SET_SHIFT 30 2857#define IGU_REGULAR_BCLEANUP (0x1<<31) 2858#define IGU_REGULAR_BCLEANUP_SHIFT 31 2859 u32 reserved_2; 2860}; 2861 2862/* 2863 * IGU driver acknowledgement register 2864 */ 2865union igu_consprod_reg { 2866 struct igu_regular regular; 2867 struct igu_backward_compatible backward_compatible; 2868}; 2869 2870 2871/* 2872 * Igu control commands 2873 */ 2874enum igu_ctrl_cmd { 2875 IGU_CTRL_CMD_TYPE_RD, 2876 IGU_CTRL_CMD_TYPE_WR, 2877 MAX_IGU_CTRL_CMD 2878}; 2879 2880 2881/* 2882 * Control register for the IGU command register 2883 */ 2884struct igu_ctrl_reg { 2885 u32 ctrl_data; 2886#define IGU_CTRL_REG_ADDRESS (0xFFF<<0) 2887#define IGU_CTRL_REG_ADDRESS_SHIFT 0 2888#define IGU_CTRL_REG_FID (0x7F<<12) 2889#define IGU_CTRL_REG_FID_SHIFT 12 2890#define IGU_CTRL_REG_RESERVED (0x1<<19) 2891#define IGU_CTRL_REG_RESERVED_SHIFT 19 2892#define IGU_CTRL_REG_TYPE (0x1<<20) 2893#define IGU_CTRL_REG_TYPE_SHIFT 20 2894#define IGU_CTRL_REG_UNUSED (0x7FF<<21) 2895#define IGU_CTRL_REG_UNUSED_SHIFT 21 2896}; 2897 2898 2899/* 2900 * Igu interrupt command 2901 */ 2902enum igu_int_cmd { 2903 IGU_INT_ENABLE, 2904 IGU_INT_DISABLE, 2905 IGU_INT_NOP, 2906 IGU_INT_NOP2, 2907 MAX_IGU_INT_CMD 2908}; 2909 2910 2911/* 2912 * Igu segments 2913 */ 2914enum igu_seg_access { 2915 IGU_SEG_ACCESS_NORM, 2916 IGU_SEG_ACCESS_DEF, 2917 IGU_SEG_ACCESS_ATTN, 2918 MAX_IGU_SEG_ACCESS 2919}; 2920 2921 2922/* 2923 * Parser parsing flags field 2924 */ 2925struct parsing_flags { 2926 __le16 flags; 2927#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) 2928#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 2929#define PARSING_FLAGS_VLAN (0x1<<1) 2930#define PARSING_FLAGS_VLAN_SHIFT 1 2931#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) 2932#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 2933#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) 2934#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 2935#define PARSING_FLAGS_IP_OPTIONS (0x1<<5) 2936#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 2937#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) 2938#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 2939#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) 2940#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 2941#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) 2942#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 2943#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) 2944#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 2945#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) 2946#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 2947#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) 2948#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 2949#define PARSING_FLAGS_LLC_SNAP (0x1<<13) 2950#define PARSING_FLAGS_LLC_SNAP_SHIFT 13 2951#define PARSING_FLAGS_RESERVED0 (0x3<<14) 2952#define PARSING_FLAGS_RESERVED0_SHIFT 14 2953}; 2954 2955 2956/* 2957 * Parsing flags for TCP ACK type 2958 */ 2959enum prs_flags_ack_type { 2960 PRS_FLAG_PUREACK_PIGGY, 2961 PRS_FLAG_PUREACK_PURE, 2962 MAX_PRS_FLAGS_ACK_TYPE 2963}; 2964 2965 2966/* 2967 * Parsing flags for Ethernet address type 2968 */ 2969enum prs_flags_eth_addr_type { 2970 PRS_FLAG_ETHTYPE_NON_UNICAST, 2971 PRS_FLAG_ETHTYPE_UNICAST, 2972 MAX_PRS_FLAGS_ETH_ADDR_TYPE 2973}; 2974 2975 2976/* 2977 * Parsing flags for over-ethernet protocol 2978 */ 2979enum prs_flags_over_eth { 2980 PRS_FLAG_OVERETH_UNKNOWN, 2981 PRS_FLAG_OVERETH_IPV4, 2982 PRS_FLAG_OVERETH_IPV6, 2983 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, 2984 MAX_PRS_FLAGS_OVER_ETH 2985}; 2986 2987 2988/* 2989 * Parsing flags for over-IP protocol 2990 */ 2991enum prs_flags_over_ip { 2992 PRS_FLAG_OVERIP_UNKNOWN, 2993 PRS_FLAG_OVERIP_TCP, 2994 PRS_FLAG_OVERIP_UDP, 2995 MAX_PRS_FLAGS_OVER_IP 2996}; 2997 2998 2999/* 3000 * SDM operation gen command (generate aggregative interrupt) 3001 */ 3002struct sdm_op_gen { 3003 __le32 command; 3004#define SDM_OP_GEN_COMP_PARAM (0x1F<<0) 3005#define SDM_OP_GEN_COMP_PARAM_SHIFT 0 3006#define SDM_OP_GEN_COMP_TYPE (0x7<<5) 3007#define SDM_OP_GEN_COMP_TYPE_SHIFT 5 3008#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) 3009#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 3010#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) 3011#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 3012#define SDM_OP_GEN_RESERVED (0x7FFF<<17) 3013#define SDM_OP_GEN_RESERVED_SHIFT 17 3014}; 3015 3016 3017/* 3018 * Timers connection context 3019 */ 3020struct timers_block_context { 3021 u32 __reserved_0; 3022 u32 __reserved_1; 3023 u32 __reserved_2; 3024 u32 flags; 3025#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) 3026#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 3027#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) 3028#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 3029#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) 3030#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 3031}; 3032 3033 3034/* 3035 * The eth aggregative context of Tstorm 3036 */ 3037struct tstorm_eth_ag_context { 3038 u32 __reserved0[14]; 3039}; 3040 3041 3042/* 3043 * The eth aggregative context of Ustorm 3044 */ 3045struct ustorm_eth_ag_context { 3046 u32 __reserved0; 3047#if defined(__BIG_ENDIAN) 3048 u8 cdu_usage; 3049 u8 __reserved2; 3050 u16 __reserved1; 3051#elif defined(__LITTLE_ENDIAN) 3052 u16 __reserved1; 3053 u8 __reserved2; 3054 u8 cdu_usage; 3055#endif 3056 u32 __reserved3[6]; 3057}; 3058 3059 3060/* 3061 * The eth aggregative context of Xstorm 3062 */ 3063struct xstorm_eth_ag_context { 3064 u32 reserved0; 3065#if defined(__BIG_ENDIAN) 3066 u8 cdu_reserved; 3067 u8 reserved2; 3068 u16 reserved1; 3069#elif defined(__LITTLE_ENDIAN) 3070 u16 reserved1; 3071 u8 reserved2; 3072 u8 cdu_reserved; 3073#endif 3074 u32 reserved3[30]; 3075}; 3076 3077 3078/* 3079 * doorbell message sent to the chip 3080 */ 3081struct doorbell { 3082#if defined(__BIG_ENDIAN) 3083 u16 zero_fill2; 3084 u8 zero_fill1; 3085 struct doorbell_hdr header; 3086#elif defined(__LITTLE_ENDIAN) 3087 struct doorbell_hdr header; 3088 u8 zero_fill1; 3089 u16 zero_fill2; 3090#endif 3091}; 3092 3093 3094/* 3095 * doorbell message sent to the chip 3096 */ 3097struct doorbell_set_prod { 3098#if defined(__BIG_ENDIAN) 3099 u16 prod; 3100 u8 zero_fill1; 3101 struct doorbell_hdr header; 3102#elif defined(__LITTLE_ENDIAN) 3103 struct doorbell_hdr header; 3104 u8 zero_fill1; 3105 u16 prod; 3106#endif 3107}; 3108 3109 3110struct regpair { 3111 __le32 lo; 3112 __le32 hi; 3113}; 3114 3115 3116/* 3117 * Classify rule opcodes in E2/E3 3118 */ 3119enum classify_rule { 3120 CLASSIFY_RULE_OPCODE_MAC, 3121 CLASSIFY_RULE_OPCODE_VLAN, 3122 CLASSIFY_RULE_OPCODE_PAIR, 3123 MAX_CLASSIFY_RULE 3124}; 3125 3126 3127/* 3128 * Classify rule types in E2/E3 3129 */ 3130enum classify_rule_action_type { 3131 CLASSIFY_RULE_REMOVE, 3132 CLASSIFY_RULE_ADD, 3133 MAX_CLASSIFY_RULE_ACTION_TYPE 3134}; 3135 3136 3137/* 3138 * client init ramrod data 3139 */ 3140struct client_init_general_data { 3141 u8 client_id; 3142 u8 statistics_counter_id; 3143 u8 statistics_en_flg; 3144 u8 is_fcoe_flg; 3145 u8 activate_flg; 3146 u8 sp_client_id; 3147 __le16 mtu; 3148 u8 statistics_zero_flg; 3149 u8 func_id; 3150 u8 cos; 3151 u8 traffic_type; 3152 u32 reserved0; 3153}; 3154 3155 3156/* 3157 * client init rx data 3158 */ 3159struct client_init_rx_data { 3160 u8 tpa_en; 3161#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) 3162#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 3163#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) 3164#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 3165#define CLIENT_INIT_RX_DATA_RESERVED5 (0x3F<<2) 3166#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 2 3167 u8 vmqueue_mode_en_flg; 3168 u8 extra_data_over_sgl_en_flg; 3169 u8 cache_line_alignment_log_size; 3170 u8 enable_dynamic_hc; 3171 u8 max_sges_for_packet; 3172 u8 client_qzone_id; 3173 u8 drop_ip_cs_err_flg; 3174 u8 drop_tcp_cs_err_flg; 3175 u8 drop_ttl0_flg; 3176 u8 drop_udp_cs_err_flg; 3177 u8 inner_vlan_removal_enable_flg; 3178 u8 outer_vlan_removal_enable_flg; 3179 u8 status_block_id; 3180 u8 rx_sb_index_number; 3181 u8 reserved0; 3182 u8 max_tpa_queues; 3183 u8 silent_vlan_removal_flg; 3184 __le16 max_bytes_on_bd; 3185 __le16 sge_buff_size; 3186 u8 approx_mcast_engine_id; 3187 u8 rss_engine_id; 3188 struct regpair bd_page_base; 3189 struct regpair sge_page_base; 3190 struct regpair cqe_page_base; 3191 u8 is_leading_rss; 3192 u8 is_approx_mcast; 3193 __le16 max_agg_size; 3194 __le16 state; 3195#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) 3196#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 3197#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) 3198#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 3199#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3200#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3201#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) 3202#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 3203#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) 3204#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 3205#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) 3206#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 3207#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) 3208#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 3209#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) 3210#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 3211 __le16 cqe_pause_thr_low; 3212 __le16 cqe_pause_thr_high; 3213 __le16 bd_pause_thr_low; 3214 __le16 bd_pause_thr_high; 3215 __le16 sge_pause_thr_low; 3216 __le16 sge_pause_thr_high; 3217 __le16 rx_cos_mask; 3218 __le16 silent_vlan_value; 3219 __le16 silent_vlan_mask; 3220 __le32 reserved6[2]; 3221}; 3222 3223/* 3224 * client init tx data 3225 */ 3226struct client_init_tx_data { 3227 u8 enforce_security_flg; 3228 u8 tx_status_block_id; 3229 u8 tx_sb_index_number; 3230 u8 tss_leading_client_id; 3231 u8 tx_switching_flg; 3232 u8 anti_spoofing_flg; 3233 __le16 default_vlan; 3234 struct regpair tx_bd_page_base; 3235 __le16 state; 3236#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) 3237#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 3238#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) 3239#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 3240#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) 3241#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 3242#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) 3243#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 3244#define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4) 3245#define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4 3246 u8 default_vlan_flg; 3247 u8 reserved2; 3248 __le32 reserved3; 3249}; 3250 3251/* 3252 * client init ramrod data 3253 */ 3254struct client_init_ramrod_data { 3255 struct client_init_general_data general; 3256 struct client_init_rx_data rx; 3257 struct client_init_tx_data tx; 3258}; 3259 3260 3261/* 3262 * client update ramrod data 3263 */ 3264struct client_update_ramrod_data { 3265 u8 client_id; 3266 u8 func_id; 3267 u8 inner_vlan_removal_enable_flg; 3268 u8 inner_vlan_removal_change_flg; 3269 u8 outer_vlan_removal_enable_flg; 3270 u8 outer_vlan_removal_change_flg; 3271 u8 anti_spoofing_enable_flg; 3272 u8 anti_spoofing_change_flg; 3273 u8 activate_flg; 3274 u8 activate_change_flg; 3275 __le16 default_vlan; 3276 u8 default_vlan_enable_flg; 3277 u8 default_vlan_change_flg; 3278 __le16 silent_vlan_value; 3279 __le16 silent_vlan_mask; 3280 u8 silent_vlan_removal_flg; 3281 u8 silent_vlan_change_flg; 3282 __le32 echo; 3283}; 3284 3285 3286/* 3287 * The eth storm context of Cstorm 3288 */ 3289struct cstorm_eth_st_context { 3290 u32 __reserved0[4]; 3291}; 3292 3293 3294struct double_regpair { 3295 u32 regpair0_lo; 3296 u32 regpair0_hi; 3297 u32 regpair1_lo; 3298 u32 regpair1_hi; 3299}; 3300 3301 3302/* 3303 * Ethernet address typesm used in ethernet tx BDs 3304 */ 3305enum eth_addr_type { 3306 UNKNOWN_ADDRESS, 3307 UNICAST_ADDRESS, 3308 MULTICAST_ADDRESS, 3309 BROADCAST_ADDRESS, 3310 MAX_ETH_ADDR_TYPE 3311}; 3312 3313 3314/* 3315 * 3316 */ 3317struct eth_classify_cmd_header { 3318 u8 cmd_general_data; 3319#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) 3320#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 3321#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) 3322#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 3323#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) 3324#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 3325#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) 3326#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 3327#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) 3328#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 3329 u8 func_id; 3330 u8 client_id; 3331 u8 reserved1; 3332}; 3333 3334 3335/* 3336 * header for eth classification config ramrod 3337 */ 3338struct eth_classify_header { 3339 u8 rule_cnt; 3340 u8 reserved0; 3341 __le16 reserved1; 3342 __le32 echo; 3343}; 3344 3345 3346/* 3347 * Command for adding/removing a MAC classification rule 3348 */ 3349struct eth_classify_mac_cmd { 3350 struct eth_classify_cmd_header header; 3351 __le32 reserved0; 3352 __le16 mac_lsb; 3353 __le16 mac_mid; 3354 __le16 mac_msb; 3355 __le16 reserved1; 3356}; 3357 3358 3359/* 3360 * Command for adding/removing a MAC-VLAN pair classification rule 3361 */ 3362struct eth_classify_pair_cmd { 3363 struct eth_classify_cmd_header header; 3364 __le32 reserved0; 3365 __le16 mac_lsb; 3366 __le16 mac_mid; 3367 __le16 mac_msb; 3368 __le16 vlan; 3369}; 3370 3371 3372/* 3373 * Command for adding/removing a VLAN classification rule 3374 */ 3375struct eth_classify_vlan_cmd { 3376 struct eth_classify_cmd_header header; 3377 __le32 reserved0; 3378 __le32 reserved1; 3379 __le16 reserved2; 3380 __le16 vlan; 3381}; 3382 3383/* 3384 * union for eth classification rule 3385 */ 3386union eth_classify_rule_cmd { 3387 struct eth_classify_mac_cmd mac; 3388 struct eth_classify_vlan_cmd vlan; 3389 struct eth_classify_pair_cmd pair; 3390}; 3391 3392/* 3393 * parameters for eth classification configuration ramrod 3394 */ 3395struct eth_classify_rules_ramrod_data { 3396 struct eth_classify_header header; 3397 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3398}; 3399 3400 3401/* 3402 * The data contain client ID need to the ramrod 3403 */ 3404struct eth_common_ramrod_data { 3405 __le32 client_id; 3406 __le32 reserved1; 3407}; 3408 3409 3410/* 3411 * The eth storm context of Ustorm 3412 */ 3413struct ustorm_eth_st_context { 3414 u32 reserved0[52]; 3415}; 3416 3417/* 3418 * The eth storm context of Tstorm 3419 */ 3420struct tstorm_eth_st_context { 3421 u32 __reserved0[28]; 3422}; 3423 3424/* 3425 * The eth storm context of Xstorm 3426 */ 3427struct xstorm_eth_st_context { 3428 u32 reserved0[60]; 3429}; 3430 3431/* 3432 * Ethernet connection context 3433 */ 3434struct eth_context { 3435 struct ustorm_eth_st_context ustorm_st_context; 3436 struct tstorm_eth_st_context tstorm_st_context; 3437 struct xstorm_eth_ag_context xstorm_ag_context; 3438 struct tstorm_eth_ag_context tstorm_ag_context; 3439 struct cstorm_eth_ag_context cstorm_ag_context; 3440 struct ustorm_eth_ag_context ustorm_ag_context; 3441 struct timers_block_context timers_context; 3442 struct xstorm_eth_st_context xstorm_st_context; 3443 struct cstorm_eth_st_context cstorm_st_context; 3444}; 3445 3446 3447/* 3448 * union for sgl and raw data. 3449 */ 3450union eth_sgl_or_raw_data { 3451 __le16 sgl[8]; 3452 u32 raw_data[4]; 3453}; 3454 3455/* 3456 * eth FP end aggregation CQE parameters struct 3457 */ 3458struct eth_end_agg_rx_cqe { 3459 u8 type_error_flags; 3460#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) 3461#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 3462#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) 3463#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 3464#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) 3465#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 3466 u8 reserved1; 3467 u8 queue_index; 3468 u8 reserved2; 3469 __le32 timestamp_delta; 3470 __le16 num_of_coalesced_segs; 3471 __le16 pkt_len; 3472 u8 pure_ack_count; 3473 u8 reserved3; 3474 __le16 reserved4; 3475 union eth_sgl_or_raw_data sgl_or_raw_data; 3476 __le32 reserved5[8]; 3477}; 3478 3479 3480/* 3481 * regular eth FP CQE parameters struct 3482 */ 3483struct eth_fast_path_rx_cqe { 3484 u8 type_error_flags; 3485#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) 3486#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 3487#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) 3488#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 3489#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) 3490#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 3491#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) 3492#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 3493#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) 3494#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 3495#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) 3496#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6 3497 u8 status_flags; 3498#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) 3499#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 3500#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) 3501#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 3502#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) 3503#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 3504#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) 3505#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 3506#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) 3507#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 3508#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) 3509#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 3510 u8 queue_index; 3511 u8 placement_offset; 3512 __le32 rss_hash_result; 3513 __le16 vlan_tag; 3514 __le16 pkt_len; 3515 __le16 len_on_bd; 3516 struct parsing_flags pars_flags; 3517 union eth_sgl_or_raw_data sgl_or_raw_data; 3518 __le32 reserved1[8]; 3519}; 3520 3521 3522/* 3523 * Command for setting classification flags for a client 3524 */ 3525struct eth_filter_rules_cmd { 3526 u8 cmd_general_data; 3527#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) 3528#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 3529#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) 3530#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 3531#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) 3532#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 3533 u8 func_id; 3534 u8 client_id; 3535 u8 reserved1; 3536 __le16 state; 3537#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) 3538#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 3539#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) 3540#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 3541#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3542#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3543#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) 3544#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 3545#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) 3546#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 3547#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) 3548#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 3549#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) 3550#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 3551#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) 3552#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 3553 __le16 reserved3; 3554 struct regpair reserved4; 3555}; 3556 3557 3558/* 3559 * parameters for eth classification filters ramrod 3560 */ 3561struct eth_filter_rules_ramrod_data { 3562 struct eth_classify_header header; 3563 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; 3564}; 3565 3566 3567/* 3568 * parameters for eth classification configuration ramrod 3569 */ 3570struct eth_general_rules_ramrod_data { 3571 struct eth_classify_header header; 3572 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3573}; 3574 3575 3576/* 3577 * The data for Halt ramrod 3578 */ 3579struct eth_halt_ramrod_data { 3580 __le32 client_id; 3581 __le32 reserved0; 3582}; 3583 3584 3585/* 3586 * Command for setting multicast classification for a client 3587 */ 3588struct eth_multicast_rules_cmd { 3589 u8 cmd_general_data; 3590#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) 3591#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 3592#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) 3593#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 3594#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) 3595#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 3596#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) 3597#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 3598 u8 func_id; 3599 u8 bin_id; 3600 u8 engine_id; 3601 __le32 reserved2; 3602 struct regpair reserved3; 3603}; 3604 3605 3606/* 3607 * parameters for multicast classification ramrod 3608 */ 3609struct eth_multicast_rules_ramrod_data { 3610 struct eth_classify_header header; 3611 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; 3612}; 3613 3614 3615/* 3616 * Place holder for ramrods protocol specific data 3617 */ 3618struct ramrod_data { 3619 __le32 data_lo; 3620 __le32 data_hi; 3621}; 3622 3623/* 3624 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) 3625 */ 3626union eth_ramrod_data { 3627 struct ramrod_data general; 3628}; 3629 3630 3631/* 3632 * RSS toeplitz hash type, as reported in CQE 3633 */ 3634enum eth_rss_hash_type { 3635 DEFAULT_HASH_TYPE, 3636 IPV4_HASH_TYPE, 3637 TCP_IPV4_HASH_TYPE, 3638 IPV6_HASH_TYPE, 3639 TCP_IPV6_HASH_TYPE, 3640 VLAN_PRI_HASH_TYPE, 3641 E1HOV_PRI_HASH_TYPE, 3642 DSCP_HASH_TYPE, 3643 MAX_ETH_RSS_HASH_TYPE 3644}; 3645 3646 3647/* 3648 * Ethernet RSS mode 3649 */ 3650enum eth_rss_mode { 3651 ETH_RSS_MODE_DISABLED, 3652 ETH_RSS_MODE_REGULAR, 3653 ETH_RSS_MODE_VLAN_PRI, 3654 ETH_RSS_MODE_E1HOV_PRI, 3655 ETH_RSS_MODE_IP_DSCP, 3656 MAX_ETH_RSS_MODE 3657}; 3658 3659 3660/* 3661 * parameters for RSS update ramrod (E2) 3662 */ 3663struct eth_rss_update_ramrod_data { 3664 u8 rss_engine_id; 3665 u8 capabilities; 3666#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) 3667#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 3668#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) 3669#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 3670#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) 3671#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 3672#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) 3673#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3 3674#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) 3675#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 3676#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) 3677#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 3678#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<6) 3679#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 6 3680#define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0 (0x1<<7) 3681#define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0_SHIFT 7 3682 u8 rss_result_mask; 3683 u8 rss_mode; 3684 __le32 __reserved2; 3685 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE]; 3686 __le32 rss_key[T_ETH_RSS_KEY]; 3687 __le32 echo; 3688 __le32 reserved3; 3689}; 3690 3691 3692/* 3693 * The eth Rx Buffer Descriptor 3694 */ 3695struct eth_rx_bd { 3696 __le32 addr_lo; 3697 __le32 addr_hi; 3698}; 3699 3700 3701/* 3702 * Eth Rx Cqe structure- general structure for ramrods 3703 */ 3704struct common_ramrod_eth_rx_cqe { 3705 u8 ramrod_type; 3706#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) 3707#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 3708#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) 3709#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 3710#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) 3711#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 3712 u8 conn_type; 3713 __le16 reserved1; 3714 __le32 conn_and_cmd_data; 3715#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) 3716#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 3717#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) 3718#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 3719 struct ramrod_data protocol_data; 3720 __le32 echo; 3721 __le32 reserved2[11]; 3722}; 3723 3724/* 3725 * Rx Last CQE in page (in ETH) 3726 */ 3727struct eth_rx_cqe_next_page { 3728 __le32 addr_lo; 3729 __le32 addr_hi; 3730 __le32 reserved[14]; 3731}; 3732 3733/* 3734 * union for all eth rx cqe types (fix their sizes) 3735 */ 3736union eth_rx_cqe { 3737 struct eth_fast_path_rx_cqe fast_path_cqe; 3738 struct common_ramrod_eth_rx_cqe ramrod_cqe; 3739 struct eth_rx_cqe_next_page next_page_cqe; 3740 struct eth_end_agg_rx_cqe end_agg_cqe; 3741}; 3742 3743 3744/* 3745 * Values for RX ETH CQE type field 3746 */ 3747enum eth_rx_cqe_type { 3748 RX_ETH_CQE_TYPE_ETH_FASTPATH, 3749 RX_ETH_CQE_TYPE_ETH_RAMROD, 3750 RX_ETH_CQE_TYPE_ETH_START_AGG, 3751 RX_ETH_CQE_TYPE_ETH_STOP_AGG, 3752 MAX_ETH_RX_CQE_TYPE 3753}; 3754 3755 3756/* 3757 * Type of SGL/Raw field in ETH RX fast path CQE 3758 */ 3759enum eth_rx_fp_sel { 3760 ETH_FP_CQE_REGULAR, 3761 ETH_FP_CQE_RAW, 3762 MAX_ETH_RX_FP_SEL 3763}; 3764 3765 3766/* 3767 * The eth Rx SGE Descriptor 3768 */ 3769struct eth_rx_sge { 3770 __le32 addr_lo; 3771 __le32 addr_hi; 3772}; 3773 3774 3775/* 3776 * common data for all protocols 3777 */ 3778struct spe_hdr { 3779 __le32 conn_and_cmd_data; 3780#define SPE_HDR_CID (0xFFFFFF<<0) 3781#define SPE_HDR_CID_SHIFT 0 3782#define SPE_HDR_CMD_ID (0xFF<<24) 3783#define SPE_HDR_CMD_ID_SHIFT 24 3784 __le16 type; 3785#define SPE_HDR_CONN_TYPE (0xFF<<0) 3786#define SPE_HDR_CONN_TYPE_SHIFT 0 3787#define SPE_HDR_FUNCTION_ID (0xFF<<8) 3788#define SPE_HDR_FUNCTION_ID_SHIFT 8 3789 __le16 reserved1; 3790}; 3791 3792/* 3793 * specific data for ethernet slow path element 3794 */ 3795union eth_specific_data { 3796 u8 protocol_data[8]; 3797 struct regpair client_update_ramrod_data; 3798 struct regpair client_init_ramrod_init_data; 3799 struct eth_halt_ramrod_data halt_ramrod_data; 3800 struct regpair update_data_addr; 3801 struct eth_common_ramrod_data common_ramrod_data; 3802 struct regpair classify_cfg_addr; 3803 struct regpair filter_cfg_addr; 3804 struct regpair mcast_cfg_addr; 3805}; 3806 3807/* 3808 * Ethernet slow path element 3809 */ 3810struct eth_spe { 3811 struct spe_hdr hdr; 3812 union eth_specific_data data; 3813}; 3814 3815 3816/* 3817 * Ethernet command ID for slow path elements 3818 */ 3819enum eth_spqe_cmd_id { 3820 RAMROD_CMD_ID_ETH_UNUSED, 3821 RAMROD_CMD_ID_ETH_CLIENT_SETUP, 3822 RAMROD_CMD_ID_ETH_HALT, 3823 RAMROD_CMD_ID_ETH_FORWARD_SETUP, 3824 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP, 3825 RAMROD_CMD_ID_ETH_CLIENT_UPDATE, 3826 RAMROD_CMD_ID_ETH_EMPTY, 3827 RAMROD_CMD_ID_ETH_TERMINATE, 3828 RAMROD_CMD_ID_ETH_TPA_UPDATE, 3829 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES, 3830 RAMROD_CMD_ID_ETH_FILTER_RULES, 3831 RAMROD_CMD_ID_ETH_MULTICAST_RULES, 3832 RAMROD_CMD_ID_ETH_RSS_UPDATE, 3833 RAMROD_CMD_ID_ETH_SET_MAC, 3834 MAX_ETH_SPQE_CMD_ID 3835}; 3836 3837 3838/* 3839 * eth tpa update command 3840 */ 3841enum eth_tpa_update_command { 3842 TPA_UPDATE_NONE_COMMAND, 3843 TPA_UPDATE_ENABLE_COMMAND, 3844 TPA_UPDATE_DISABLE_COMMAND, 3845 MAX_ETH_TPA_UPDATE_COMMAND 3846}; 3847 3848 3849/* 3850 * Tx regular BD structure 3851 */ 3852struct eth_tx_bd { 3853 __le32 addr_lo; 3854 __le32 addr_hi; 3855 __le16 total_pkt_bytes; 3856 __le16 nbytes; 3857 u8 reserved[4]; 3858}; 3859 3860 3861/* 3862 * structure for easy accessibility to assembler 3863 */ 3864struct eth_tx_bd_flags { 3865 u8 as_bitfield; 3866#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) 3867#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 3868#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) 3869#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 3870#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) 3871#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 3872#define ETH_TX_BD_FLAGS_START_BD (0x1<<4) 3873#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 3874#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) 3875#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 3876#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) 3877#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 3878#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) 3879#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 3880}; 3881 3882/* 3883 * The eth Tx Buffer Descriptor 3884 */ 3885struct eth_tx_start_bd { 3886 __le32 addr_lo; 3887 __le32 addr_hi; 3888 __le16 nbd; 3889 __le16 nbytes; 3890 __le16 vlan_or_ethertype; 3891 struct eth_tx_bd_flags bd_flags; 3892 u8 general_data; 3893#define ETH_TX_START_BD_HDR_NBDS (0xF<<0) 3894#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 3895#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) 3896#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 3897#define ETH_TX_START_BD_RESREVED (0x1<<5) 3898#define ETH_TX_START_BD_RESREVED_SHIFT 5 3899#define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6) 3900#define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6 3901}; 3902 3903/* 3904 * Tx parsing BD structure for ETH E1/E1h 3905 */ 3906struct eth_tx_parse_bd_e1x { 3907 u8 global_data; 3908#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) 3909#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 3910#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4) 3911#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4 3912#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5) 3913#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5 3914#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6) 3915#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6 3916#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7) 3917#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7 3918 u8 tcp_flags; 3919#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) 3920#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 3921#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) 3922#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 3923#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) 3924#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 3925#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) 3926#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 3927#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) 3928#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 3929#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) 3930#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 3931#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) 3932#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 3933#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) 3934#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 3935 u8 ip_hlen_w; 3936 s8 reserved; 3937 __le16 total_hlen_w; 3938 __le16 tcp_pseudo_csum; 3939 __le16 lso_mss; 3940 __le16 ip_id; 3941 __le32 tcp_send_seq; 3942}; 3943 3944/* 3945 * Tx parsing BD structure for ETH E2 3946 */ 3947struct eth_tx_parse_bd_e2 { 3948 __le16 dst_mac_addr_lo; 3949 __le16 dst_mac_addr_mid; 3950 __le16 dst_mac_addr_hi; 3951 __le16 src_mac_addr_lo; 3952 __le16 src_mac_addr_mid; 3953 __le16 src_mac_addr_hi; 3954 __le32 parsing_data; 3955#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0) 3956#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0 3957#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13) 3958#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13 3959#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17) 3960#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17 3961#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31) 3962#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31 3963}; 3964 3965/* 3966 * The last BD in the BD memory will hold a pointer to the next BD memory 3967 */ 3968struct eth_tx_next_bd { 3969 __le32 addr_lo; 3970 __le32 addr_hi; 3971 u8 reserved[8]; 3972}; 3973 3974/* 3975 * union for 4 Bd types 3976 */ 3977union eth_tx_bd_types { 3978 struct eth_tx_start_bd start_bd; 3979 struct eth_tx_bd reg_bd; 3980 struct eth_tx_parse_bd_e1x parse_bd_e1x; 3981 struct eth_tx_parse_bd_e2 parse_bd_e2; 3982 struct eth_tx_next_bd next_bd; 3983}; 3984 3985/* 3986 * array of 13 bds as appears in the eth xstorm context 3987 */ 3988struct eth_tx_bds_array { 3989 union eth_tx_bd_types bds[13]; 3990}; 3991 3992 3993/* 3994 * VLAN mode on TX BDs 3995 */ 3996enum eth_tx_vlan_type { 3997 X_ETH_NO_VLAN, 3998 X_ETH_OUTBAND_VLAN, 3999 X_ETH_INBAND_VLAN, 4000 X_ETH_FW_ADDED_VLAN, 4001 MAX_ETH_TX_VLAN_TYPE 4002}; 4003 4004 4005/* 4006 * Ethernet VLAN filtering mode in E1x 4007 */ 4008enum eth_vlan_filter_mode { 4009 ETH_VLAN_FILTER_ANY_VLAN, 4010 ETH_VLAN_FILTER_SPECIFIC_VLAN, 4011 ETH_VLAN_FILTER_CLASSIFY, 4012 MAX_ETH_VLAN_FILTER_MODE 4013}; 4014 4015 4016/* 4017 * MAC filtering configuration command header 4018 */ 4019struct mac_configuration_hdr { 4020 u8 length; 4021 u8 offset; 4022 __le16 client_id; 4023 __le32 echo; 4024}; 4025 4026/* 4027 * MAC address in list for ramrod 4028 */ 4029struct mac_configuration_entry { 4030 __le16 lsb_mac_addr; 4031 __le16 middle_mac_addr; 4032 __le16 msb_mac_addr; 4033 __le16 vlan_id; 4034 u8 pf_id; 4035 u8 flags; 4036#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) 4037#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 4038#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) 4039#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 4040#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) 4041#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 4042#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) 4043#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 4044#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) 4045#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 4046#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) 4047#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 4048 __le16 reserved0; 4049 __le32 clients_bit_vector; 4050}; 4051 4052/* 4053 * MAC filtering configuration command 4054 */ 4055struct mac_configuration_cmd { 4056 struct mac_configuration_hdr hdr; 4057 struct mac_configuration_entry config_table[64]; 4058}; 4059 4060 4061/* 4062 * Set-MAC command type (in E1x) 4063 */ 4064enum set_mac_action_type { 4065 T_ETH_MAC_COMMAND_INVALIDATE, 4066 T_ETH_MAC_COMMAND_SET, 4067 MAX_SET_MAC_ACTION_TYPE 4068}; 4069 4070 4071/* 4072 * tpa update ramrod data 4073 */ 4074struct tpa_update_ramrod_data { 4075 u8 update_ipv4; 4076 u8 update_ipv6; 4077 u8 client_id; 4078 u8 max_tpa_queues; 4079 u8 max_sges_for_packet; 4080 u8 complete_on_both_clients; 4081 __le16 reserved1; 4082 __le16 sge_buff_size; 4083 __le16 max_agg_size; 4084 __le32 sge_page_base_lo; 4085 __le32 sge_page_base_hi; 4086 __le16 sge_pause_thr_low; 4087 __le16 sge_pause_thr_high; 4088}; 4089 4090 4091/* 4092 * approximate-match multicast filtering for E1H per function in Tstorm 4093 */ 4094struct tstorm_eth_approximate_match_multicast_filtering { 4095 u32 mcast_add_hash_bit_array[8]; 4096}; 4097 4098 4099/* 4100 * Common configuration parameters per function in Tstorm 4101 */ 4102struct tstorm_eth_function_common_config { 4103 __le16 config_flags; 4104#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) 4105#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 4106#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) 4107#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 4108#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) 4109#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 4110#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) 4111#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 4112#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) 4113#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 4114#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) 4115#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 4116#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) 4117#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 4118 u8 rss_result_mask; 4119 u8 reserved1; 4120 __le16 vlan_id[2]; 4121}; 4122 4123 4124/* 4125 * MAC filtering configuration parameters per port in Tstorm 4126 */ 4127struct tstorm_eth_mac_filter_config { 4128 __le32 ucast_drop_all; 4129 __le32 ucast_accept_all; 4130 __le32 mcast_drop_all; 4131 __le32 mcast_accept_all; 4132 __le32 bcast_accept_all; 4133 __le32 vlan_filter[2]; 4134 __le32 unmatched_unicast; 4135}; 4136 4137 4138/* 4139 * tx only queue init ramrod data 4140 */ 4141struct tx_queue_init_ramrod_data { 4142 struct client_init_general_data general; 4143 struct client_init_tx_data tx; 4144}; 4145 4146 4147/* 4148 * Three RX producers for ETH 4149 */ 4150struct ustorm_eth_rx_producers { 4151#if defined(__BIG_ENDIAN) 4152 u16 bd_prod; 4153 u16 cqe_prod; 4154#elif defined(__LITTLE_ENDIAN) 4155 u16 cqe_prod; 4156 u16 bd_prod; 4157#endif 4158#if defined(__BIG_ENDIAN) 4159 u16 reserved; 4160 u16 sge_prod; 4161#elif defined(__LITTLE_ENDIAN) 4162 u16 sge_prod; 4163 u16 reserved; 4164#endif 4165}; 4166 4167 4168/* 4169 * cfc delete event data 4170 */ 4171struct cfc_del_event_data { 4172 u32 cid; 4173 u32 reserved0; 4174 u32 reserved1; 4175}; 4176 4177 4178/* 4179 * per-port SAFC demo variables 4180 */ 4181struct cmng_flags_per_port { 4182 u32 cmng_enables; 4183#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) 4184#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 4185#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) 4186#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 4187#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) 4188#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 4189#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) 4190#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 4191#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) 4192#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 4193 u32 __reserved1; 4194}; 4195 4196 4197/* 4198 * per-port rate shaping variables 4199 */ 4200struct rate_shaping_vars_per_port { 4201 u32 rs_periodic_timeout; 4202 u32 rs_threshold; 4203}; 4204 4205/* 4206 * per-port fairness variables 4207 */ 4208struct fairness_vars_per_port { 4209 u32 upper_bound; 4210 u32 fair_threshold; 4211 u32 fairness_timeout; 4212 u32 reserved0; 4213}; 4214 4215/* 4216 * per-port SAFC variables 4217 */ 4218struct safc_struct_per_port { 4219#if defined(__BIG_ENDIAN) 4220 u16 __reserved1; 4221 u8 __reserved0; 4222 u8 safc_timeout_usec; 4223#elif defined(__LITTLE_ENDIAN) 4224 u8 safc_timeout_usec; 4225 u8 __reserved0; 4226 u16 __reserved1; 4227#endif 4228 u8 cos_to_traffic_types[MAX_COS_NUMBER]; 4229 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; 4230}; 4231 4232/* 4233 * Per-port congestion management variables 4234 */ 4235struct cmng_struct_per_port { 4236 struct rate_shaping_vars_per_port rs_vars; 4237 struct fairness_vars_per_port fair_vars; 4238 struct safc_struct_per_port safc_vars; 4239 struct cmng_flags_per_port flags; 4240}; 4241 4242 4243/* 4244 * Protocol-common command ID for slow path elements 4245 */ 4246enum common_spqe_cmd_id { 4247 RAMROD_CMD_ID_COMMON_UNUSED, 4248 RAMROD_CMD_ID_COMMON_FUNCTION_START, 4249 RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 4250 RAMROD_CMD_ID_COMMON_CFC_DEL, 4251 RAMROD_CMD_ID_COMMON_CFC_DEL_WB, 4252 RAMROD_CMD_ID_COMMON_STAT_QUERY, 4253 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 4254 RAMROD_CMD_ID_COMMON_START_TRAFFIC, 4255 RAMROD_CMD_ID_COMMON_RESERVED1, 4256 RAMROD_CMD_ID_COMMON_RESERVED2, 4257 MAX_COMMON_SPQE_CMD_ID 4258}; 4259 4260 4261/* 4262 * Per-protocol connection types 4263 */ 4264enum connection_type { 4265 ETH_CONNECTION_TYPE, 4266 TOE_CONNECTION_TYPE, 4267 RDMA_CONNECTION_TYPE, 4268 ISCSI_CONNECTION_TYPE, 4269 FCOE_CONNECTION_TYPE, 4270 RESERVED_CONNECTION_TYPE_0, 4271 RESERVED_CONNECTION_TYPE_1, 4272 RESERVED_CONNECTION_TYPE_2, 4273 NONE_CONNECTION_TYPE, 4274 MAX_CONNECTION_TYPE 4275}; 4276 4277 4278/* 4279 * Cos modes 4280 */ 4281enum cos_mode { 4282 OVERRIDE_COS, 4283 STATIC_COS, 4284 FW_WRR, 4285 MAX_COS_MODE 4286}; 4287 4288 4289/* 4290 * Dynamic HC counters set by the driver 4291 */ 4292struct hc_dynamic_drv_counter { 4293 u32 val[HC_SB_MAX_DYNAMIC_INDICES]; 4294}; 4295 4296/* 4297 * zone A per-queue data 4298 */ 4299struct cstorm_queue_zone_data { 4300 struct hc_dynamic_drv_counter hc_dyn_drv_cnt; 4301 struct regpair reserved[2]; 4302}; 4303 4304 4305/* 4306 * Vf-PF channel data in cstorm ram (non-triggered zone) 4307 */ 4308struct vf_pf_channel_zone_data { 4309 u32 msg_addr_lo; 4310 u32 msg_addr_hi; 4311}; 4312 4313/* 4314 * zone for VF non-triggered data 4315 */ 4316struct non_trigger_vf_zone { 4317 struct vf_pf_channel_zone_data vf_pf_channel; 4318}; 4319 4320/* 4321 * Vf-PF channel trigger zone in cstorm ram 4322 */ 4323struct vf_pf_channel_zone_trigger { 4324 u8 addr_valid; 4325}; 4326 4327/* 4328 * zone that triggers the in-bound interrupt 4329 */ 4330struct trigger_vf_zone { 4331#if defined(__BIG_ENDIAN) 4332 u16 reserved1; 4333 u8 reserved0; 4334 struct vf_pf_channel_zone_trigger vf_pf_channel; 4335#elif defined(__LITTLE_ENDIAN) 4336 struct vf_pf_channel_zone_trigger vf_pf_channel; 4337 u8 reserved0; 4338 u16 reserved1; 4339#endif 4340 u32 reserved2; 4341}; 4342 4343/* 4344 * zone B per-VF data 4345 */ 4346struct cstorm_vf_zone_data { 4347 struct non_trigger_vf_zone non_trigger; 4348 struct trigger_vf_zone trigger; 4349}; 4350 4351 4352/* 4353 * Dynamic host coalescing init parameters, per state machine 4354 */ 4355struct dynamic_hc_sm_config { 4356 u32 threshold[3]; 4357 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES]; 4358 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES]; 4359 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES]; 4360 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES]; 4361 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES]; 4362}; 4363 4364/* 4365 * Dynamic host coalescing init parameters 4366 */ 4367struct dynamic_hc_config { 4368 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM]; 4369}; 4370 4371 4372struct e2_integ_data { 4373#if defined(__BIG_ENDIAN) 4374 u8 flags; 4375#define E2_INTEG_DATA_TESTING_EN (0x1<<0) 4376#define E2_INTEG_DATA_TESTING_EN_SHIFT 0 4377#define E2_INTEG_DATA_LB_TX (0x1<<1) 4378#define E2_INTEG_DATA_LB_TX_SHIFT 1 4379#define E2_INTEG_DATA_COS_TX (0x1<<2) 4380#define E2_INTEG_DATA_COS_TX_SHIFT 2 4381#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 4382#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 4383#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 4384#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 4385#define E2_INTEG_DATA_RESERVED (0x7<<5) 4386#define E2_INTEG_DATA_RESERVED_SHIFT 5 4387 u8 cos; 4388 u8 voq; 4389 u8 pbf_queue; 4390#elif defined(__LITTLE_ENDIAN) 4391 u8 pbf_queue; 4392 u8 voq; 4393 u8 cos; 4394 u8 flags; 4395#define E2_INTEG_DATA_TESTING_EN (0x1<<0) 4396#define E2_INTEG_DATA_TESTING_EN_SHIFT 0 4397#define E2_INTEG_DATA_LB_TX (0x1<<1) 4398#define E2_INTEG_DATA_LB_TX_SHIFT 1 4399#define E2_INTEG_DATA_COS_TX (0x1<<2) 4400#define E2_INTEG_DATA_COS_TX_SHIFT 2 4401#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 4402#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 4403#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 4404#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 4405#define E2_INTEG_DATA_RESERVED (0x7<<5) 4406#define E2_INTEG_DATA_RESERVED_SHIFT 5 4407#endif 4408#if defined(__BIG_ENDIAN) 4409 u16 reserved3; 4410 u8 reserved2; 4411 u8 ramEn; 4412#elif defined(__LITTLE_ENDIAN) 4413 u8 ramEn; 4414 u8 reserved2; 4415 u16 reserved3; 4416#endif 4417}; 4418 4419 4420/* 4421 * set mac event data 4422 */ 4423struct eth_event_data { 4424 u32 echo; 4425 u32 reserved0; 4426 u32 reserved1; 4427}; 4428 4429 4430/* 4431 * pf-vf event data 4432 */ 4433struct vf_pf_event_data { 4434 u8 vf_id; 4435 u8 reserved0; 4436 u16 reserved1; 4437 u32 msg_addr_lo; 4438 u32 msg_addr_hi; 4439}; 4440 4441/* 4442 * VF FLR event data 4443 */ 4444struct vf_flr_event_data { 4445 u8 vf_id; 4446 u8 reserved0; 4447 u16 reserved1; 4448 u32 reserved2; 4449 u32 reserved3; 4450}; 4451 4452/* 4453 * malicious VF event data 4454 */ 4455struct malicious_vf_event_data { 4456 u8 vf_id; 4457 u8 reserved0; 4458 u16 reserved1; 4459 u32 reserved2; 4460 u32 reserved3; 4461}; 4462 4463/* 4464 * union for all event ring message types 4465 */ 4466union event_data { 4467 struct vf_pf_event_data vf_pf_event; 4468 struct eth_event_data eth_event; 4469 struct cfc_del_event_data cfc_del_event; 4470 struct vf_flr_event_data vf_flr_event; 4471 struct malicious_vf_event_data malicious_vf_event; 4472}; 4473 4474 4475/* 4476 * per PF event ring data 4477 */ 4478struct event_ring_data { 4479 struct regpair base_addr; 4480#if defined(__BIG_ENDIAN) 4481 u8 index_id; 4482 u8 sb_id; 4483 u16 producer; 4484#elif defined(__LITTLE_ENDIAN) 4485 u16 producer; 4486 u8 sb_id; 4487 u8 index_id; 4488#endif 4489 u32 reserved0; 4490}; 4491 4492 4493/* 4494 * event ring message element (each element is 128 bits) 4495 */ 4496struct event_ring_msg { 4497 u8 opcode; 4498 u8 error; 4499 u16 reserved1; 4500 union event_data data; 4501}; 4502 4503/* 4504 * event ring next page element (128 bits) 4505 */ 4506struct event_ring_next { 4507 struct regpair addr; 4508 u32 reserved[2]; 4509}; 4510 4511/* 4512 * union for event ring element types (each element is 128 bits) 4513 */ 4514union event_ring_elem { 4515 struct event_ring_msg message; 4516 struct event_ring_next next_page; 4517}; 4518 4519 4520/* 4521 * Common event ring opcodes 4522 */ 4523enum event_ring_opcode { 4524 EVENT_RING_OPCODE_VF_PF_CHANNEL, 4525 EVENT_RING_OPCODE_FUNCTION_START, 4526 EVENT_RING_OPCODE_FUNCTION_STOP, 4527 EVENT_RING_OPCODE_CFC_DEL, 4528 EVENT_RING_OPCODE_CFC_DEL_WB, 4529 EVENT_RING_OPCODE_STAT_QUERY, 4530 EVENT_RING_OPCODE_STOP_TRAFFIC, 4531 EVENT_RING_OPCODE_START_TRAFFIC, 4532 EVENT_RING_OPCODE_VF_FLR, 4533 EVENT_RING_OPCODE_MALICIOUS_VF, 4534 EVENT_RING_OPCODE_FORWARD_SETUP, 4535 EVENT_RING_OPCODE_RSS_UPDATE_RULES, 4536 EVENT_RING_OPCODE_RESERVED1, 4537 EVENT_RING_OPCODE_RESERVED2, 4538 EVENT_RING_OPCODE_SET_MAC, 4539 EVENT_RING_OPCODE_CLASSIFICATION_RULES, 4540 EVENT_RING_OPCODE_FILTERS_RULES, 4541 EVENT_RING_OPCODE_MULTICAST_RULES, 4542 MAX_EVENT_RING_OPCODE 4543}; 4544 4545 4546/* 4547 * Modes for fairness algorithm 4548 */ 4549enum fairness_mode { 4550 FAIRNESS_COS_WRR_MODE, 4551 FAIRNESS_COS_ETS_MODE, 4552 MAX_FAIRNESS_MODE 4553}; 4554 4555 4556/* 4557 * per-vnic fairness variables 4558 */ 4559struct fairness_vars_per_vn { 4560 u32 cos_credit_delta[MAX_COS_NUMBER]; 4561 u32 vn_credit_delta; 4562 u32 __reserved0; 4563}; 4564 4565 4566/* 4567 * Priority and cos 4568 */ 4569struct priority_cos { 4570 u8 priority; 4571 u8 cos; 4572 __le16 reserved1; 4573}; 4574 4575/* 4576 * The data for flow control configuration 4577 */ 4578struct flow_control_configuration { 4579 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 4580 u8 dcb_enabled; 4581 u8 dcb_version; 4582 u8 dont_add_pri_0_en; 4583 u8 reserved1; 4584 __le32 reserved2; 4585}; 4586 4587 4588/* 4589 * 4590 */ 4591struct function_start_data { 4592 __le16 function_mode; 4593 __le16 sd_vlan_tag; 4594 u16 reserved; 4595 u8 path_id; 4596 u8 network_cos_mode; 4597}; 4598 4599 4600/* 4601 * FW version stored in the Xstorm RAM 4602 */ 4603struct fw_version { 4604#if defined(__BIG_ENDIAN) 4605 u8 engineering; 4606 u8 revision; 4607 u8 minor; 4608 u8 major; 4609#elif defined(__LITTLE_ENDIAN) 4610 u8 major; 4611 u8 minor; 4612 u8 revision; 4613 u8 engineering; 4614#endif 4615 u32 flags; 4616#define FW_VERSION_OPTIMIZED (0x1<<0) 4617#define FW_VERSION_OPTIMIZED_SHIFT 0 4618#define FW_VERSION_BIG_ENDIEN (0x1<<1) 4619#define FW_VERSION_BIG_ENDIEN_SHIFT 1 4620#define FW_VERSION_CHIP_VERSION (0x3<<2) 4621#define FW_VERSION_CHIP_VERSION_SHIFT 2 4622#define __FW_VERSION_RESERVED (0xFFFFFFF<<4) 4623#define __FW_VERSION_RESERVED_SHIFT 4 4624}; 4625 4626 4627/* 4628 * Dynamic Host-Coalescing - Driver(host) counters 4629 */ 4630struct hc_dynamic_sb_drv_counters { 4631 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES]; 4632}; 4633 4634 4635/* 4636 * 2 bytes. configuration/state parameters for a single protocol index 4637 */ 4638struct hc_index_data { 4639#if defined(__BIG_ENDIAN) 4640 u8 flags; 4641#define HC_INDEX_DATA_SM_ID (0x1<<0) 4642#define HC_INDEX_DATA_SM_ID_SHIFT 0 4643#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 4644#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 4645#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 4646#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 4647#define HC_INDEX_DATA_RESERVE (0x1F<<3) 4648#define HC_INDEX_DATA_RESERVE_SHIFT 3 4649 u8 timeout; 4650#elif defined(__LITTLE_ENDIAN) 4651 u8 timeout; 4652 u8 flags; 4653#define HC_INDEX_DATA_SM_ID (0x1<<0) 4654#define HC_INDEX_DATA_SM_ID_SHIFT 0 4655#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 4656#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 4657#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 4658#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 4659#define HC_INDEX_DATA_RESERVE (0x1F<<3) 4660#define HC_INDEX_DATA_RESERVE_SHIFT 3 4661#endif 4662}; 4663 4664 4665/* 4666 * HC state-machine 4667 */ 4668struct hc_status_block_sm { 4669#if defined(__BIG_ENDIAN) 4670 u8 igu_seg_id; 4671 u8 igu_sb_id; 4672 u8 timer_value; 4673 u8 __flags; 4674#elif defined(__LITTLE_ENDIAN) 4675 u8 __flags; 4676 u8 timer_value; 4677 u8 igu_sb_id; 4678 u8 igu_seg_id; 4679#endif 4680 u32 time_to_expire; 4681}; 4682 4683/* 4684 * hold PCI identification variables- used in various places in firmware 4685 */ 4686struct pci_entity { 4687#if defined(__BIG_ENDIAN) 4688 u8 vf_valid; 4689 u8 vf_id; 4690 u8 vnic_id; 4691 u8 pf_id; 4692#elif defined(__LITTLE_ENDIAN) 4693 u8 pf_id; 4694 u8 vnic_id; 4695 u8 vf_id; 4696 u8 vf_valid; 4697#endif 4698}; 4699 4700/* 4701 * The fast-path status block meta-data, common to all chips 4702 */ 4703struct hc_sb_data { 4704 struct regpair host_sb_addr; 4705 struct hc_status_block_sm state_machine[HC_SB_MAX_SM]; 4706 struct pci_entity p_func; 4707#if defined(__BIG_ENDIAN) 4708 u8 rsrv0; 4709 u8 state; 4710 u8 dhc_qzone_id; 4711 u8 same_igu_sb_1b; 4712#elif defined(__LITTLE_ENDIAN) 4713 u8 same_igu_sb_1b; 4714 u8 dhc_qzone_id; 4715 u8 state; 4716 u8 rsrv0; 4717#endif 4718 struct regpair rsrv1[2]; 4719}; 4720 4721 4722/* 4723 * Segment types for host coaslescing 4724 */ 4725enum hc_segment { 4726 HC_REGULAR_SEGMENT, 4727 HC_DEFAULT_SEGMENT, 4728 MAX_HC_SEGMENT 4729}; 4730 4731 4732/* 4733 * The fast-path status block meta-data 4734 */ 4735struct hc_sp_status_block_data { 4736 struct regpair host_sb_addr; 4737#if defined(__BIG_ENDIAN) 4738 u8 rsrv1; 4739 u8 state; 4740 u8 igu_seg_id; 4741 u8 igu_sb_id; 4742#elif defined(__LITTLE_ENDIAN) 4743 u8 igu_sb_id; 4744 u8 igu_seg_id; 4745 u8 state; 4746 u8 rsrv1; 4747#endif 4748 struct pci_entity p_func; 4749}; 4750 4751 4752/* 4753 * The fast-path status block meta-data 4754 */ 4755struct hc_status_block_data_e1x { 4756 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]; 4757 struct hc_sb_data common; 4758}; 4759 4760 4761/* 4762 * The fast-path status block meta-data 4763 */ 4764struct hc_status_block_data_e2 { 4765 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]; 4766 struct hc_sb_data common; 4767}; 4768 4769 4770/* 4771 * IGU block operartion modes (in Everest2) 4772 */ 4773enum igu_mode { 4774 HC_IGU_BC_MODE, 4775 HC_IGU_NBC_MODE, 4776 MAX_IGU_MODE 4777}; 4778 4779 4780/* 4781 * IP versions 4782 */ 4783enum ip_ver { 4784 IP_V4, 4785 IP_V6, 4786 MAX_IP_VER 4787}; 4788 4789 4790/* 4791 * Multi-function modes 4792 */ 4793enum mf_mode { 4794 SINGLE_FUNCTION, 4795 MULTI_FUNCTION_SD, 4796 MULTI_FUNCTION_SI, 4797 MULTI_FUNCTION_RESERVED, 4798 MAX_MF_MODE 4799}; 4800 4801/* 4802 * Protocol-common statistics collected by the Tstorm (per pf) 4803 */ 4804struct tstorm_per_pf_stats { 4805 struct regpair rcv_error_bytes; 4806}; 4807 4808/* 4809 * 4810 */ 4811struct per_pf_stats { 4812 struct tstorm_per_pf_stats tstorm_pf_statistics; 4813}; 4814 4815 4816/* 4817 * Protocol-common statistics collected by the Tstorm (per port) 4818 */ 4819struct tstorm_per_port_stats { 4820 __le32 mac_discard; 4821 __le32 mac_filter_discard; 4822 __le32 brb_truncate_discard; 4823 __le32 mf_tag_discard; 4824 __le32 packet_drop; 4825 __le32 reserved; 4826}; 4827 4828/* 4829 * 4830 */ 4831struct per_port_stats { 4832 struct tstorm_per_port_stats tstorm_port_statistics; 4833}; 4834 4835 4836/* 4837 * Protocol-common statistics collected by the Tstorm (per client) 4838 */ 4839struct tstorm_per_queue_stats { 4840 struct regpair rcv_ucast_bytes; 4841 __le32 rcv_ucast_pkts; 4842 __le32 checksum_discard; 4843 struct regpair rcv_bcast_bytes; 4844 __le32 rcv_bcast_pkts; 4845 __le32 pkts_too_big_discard; 4846 struct regpair rcv_mcast_bytes; 4847 __le32 rcv_mcast_pkts; 4848 __le32 ttl0_discard; 4849 __le16 no_buff_discard; 4850 __le16 reserved0; 4851 __le32 reserved1; 4852}; 4853 4854/* 4855 * Protocol-common statistics collected by the Ustorm (per client) 4856 */ 4857struct ustorm_per_queue_stats { 4858 struct regpair ucast_no_buff_bytes; 4859 struct regpair mcast_no_buff_bytes; 4860 struct regpair bcast_no_buff_bytes; 4861 __le32 ucast_no_buff_pkts; 4862 __le32 mcast_no_buff_pkts; 4863 __le32 bcast_no_buff_pkts; 4864 __le32 coalesced_pkts; 4865 struct regpair coalesced_bytes; 4866 __le32 coalesced_events; 4867 __le32 coalesced_aborts; 4868}; 4869 4870/* 4871 * Protocol-common statistics collected by the Xstorm (per client) 4872 */ 4873struct xstorm_per_queue_stats { 4874 struct regpair ucast_bytes_sent; 4875 struct regpair mcast_bytes_sent; 4876 struct regpair bcast_bytes_sent; 4877 __le32 ucast_pkts_sent; 4878 __le32 mcast_pkts_sent; 4879 __le32 bcast_pkts_sent; 4880 __le32 error_drop_pkts; 4881}; 4882 4883/* 4884 * 4885 */ 4886struct per_queue_stats { 4887 struct tstorm_per_queue_stats tstorm_queue_statistics; 4888 struct ustorm_per_queue_stats ustorm_queue_statistics; 4889 struct xstorm_per_queue_stats xstorm_queue_statistics; 4890}; 4891 4892 4893/* 4894 * FW version stored in first line of pram 4895 */ 4896struct pram_fw_version { 4897 u8 major; 4898 u8 minor; 4899 u8 revision; 4900 u8 engineering; 4901 u8 flags; 4902#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) 4903#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 4904#define PRAM_FW_VERSION_STORM_ID (0x3<<1) 4905#define PRAM_FW_VERSION_STORM_ID_SHIFT 1 4906#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) 4907#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 4908#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) 4909#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 4910#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) 4911#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 4912}; 4913 4914 4915/* 4916 * Ethernet slow path element 4917 */ 4918union protocol_common_specific_data { 4919 u8 protocol_data[8]; 4920 struct regpair phy_address; 4921 struct regpair mac_config_addr; 4922}; 4923 4924/* 4925 * The send queue element 4926 */ 4927struct protocol_common_spe { 4928 struct spe_hdr hdr; 4929 union protocol_common_specific_data data; 4930}; 4931 4932 4933/* 4934 * a single rate shaping counter. can be used as protocol or vnic counter 4935 */ 4936struct rate_shaping_counter { 4937 u32 quota; 4938#if defined(__BIG_ENDIAN) 4939 u16 __reserved0; 4940 u16 rate; 4941#elif defined(__LITTLE_ENDIAN) 4942 u16 rate; 4943 u16 __reserved0; 4944#endif 4945}; 4946 4947 4948/* 4949 * per-vnic rate shaping variables 4950 */ 4951struct rate_shaping_vars_per_vn { 4952 struct rate_shaping_counter vn_counter; 4953}; 4954 4955 4956/* 4957 * The send queue element 4958 */ 4959struct slow_path_element { 4960 struct spe_hdr hdr; 4961 struct regpair protocol_data; 4962}; 4963 4964 4965/* 4966 * Protocol-common statistics counter 4967 */ 4968struct stats_counter { 4969 __le16 xstats_counter; 4970 __le16 reserved0; 4971 __le32 reserved1; 4972 __le16 tstats_counter; 4973 __le16 reserved2; 4974 __le32 reserved3; 4975 __le16 ustats_counter; 4976 __le16 reserved4; 4977 __le32 reserved5; 4978 __le16 cstats_counter; 4979 __le16 reserved6; 4980 __le32 reserved7; 4981}; 4982 4983 4984/* 4985 * 4986 */ 4987struct stats_query_entry { 4988 u8 kind; 4989 u8 index; 4990 __le16 funcID; 4991 __le32 reserved; 4992 struct regpair address; 4993}; 4994 4995/* 4996 * statistic command 4997 */ 4998struct stats_query_cmd_group { 4999 struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 5000}; 5001 5002 5003/* 5004 * statistic command header 5005 */ 5006struct stats_query_header { 5007 u8 cmd_num; 5008 u8 reserved0; 5009 __le16 drv_stats_counter; 5010 __le32 reserved1; 5011 struct regpair stats_counters_addrs; 5012}; 5013 5014 5015/* 5016 * Types of statistcis query entry 5017 */ 5018enum stats_query_type { 5019 STATS_TYPE_QUEUE, 5020 STATS_TYPE_PORT, 5021 STATS_TYPE_PF, 5022 STATS_TYPE_TOE, 5023 STATS_TYPE_FCOE, 5024 MAX_STATS_QUERY_TYPE 5025}; 5026 5027 5028/* 5029 * Indicate of the function status block state 5030 */ 5031enum status_block_state { 5032 SB_DISABLED, 5033 SB_ENABLED, 5034 SB_CLEANED, 5035 MAX_STATUS_BLOCK_STATE 5036}; 5037 5038 5039/* 5040 * Storm IDs (including attentions for IGU related enums) 5041 */ 5042enum storm_id { 5043 USTORM_ID, 5044 CSTORM_ID, 5045 XSTORM_ID, 5046 TSTORM_ID, 5047 ATTENTION_ID, 5048 MAX_STORM_ID 5049}; 5050 5051 5052/* 5053 * Taffic types used in ETS and flow control algorithms 5054 */ 5055enum traffic_type { 5056 LLFC_TRAFFIC_TYPE_NW, 5057 LLFC_TRAFFIC_TYPE_FCOE, 5058 LLFC_TRAFFIC_TYPE_ISCSI, 5059 MAX_TRAFFIC_TYPE 5060}; 5061 5062 5063/* 5064 * zone A per-queue data 5065 */ 5066struct tstorm_queue_zone_data { 5067 struct regpair reserved[4]; 5068}; 5069 5070 5071/* 5072 * zone B per-VF data 5073 */ 5074struct tstorm_vf_zone_data { 5075 struct regpair reserved; 5076}; 5077 5078 5079/* 5080 * zone A per-queue data 5081 */ 5082struct ustorm_queue_zone_data { 5083 struct ustorm_eth_rx_producers eth_rx_producers; 5084 struct regpair reserved[3]; 5085}; 5086 5087 5088/* 5089 * zone B per-VF data 5090 */ 5091struct ustorm_vf_zone_data { 5092 struct regpair reserved; 5093}; 5094 5095 5096/* 5097 * data per VF-PF channel 5098 */ 5099struct vf_pf_channel_data { 5100#if defined(__BIG_ENDIAN) 5101 u16 reserved0; 5102 u8 valid; 5103 u8 state; 5104#elif defined(__LITTLE_ENDIAN) 5105 u8 state; 5106 u8 valid; 5107 u16 reserved0; 5108#endif 5109 u32 reserved1; 5110}; 5111 5112 5113/* 5114 * State of VF-PF channel 5115 */ 5116enum vf_pf_channel_state { 5117 VF_PF_CHANNEL_STATE_READY, 5118 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK, 5119 MAX_VF_PF_CHANNEL_STATE 5120}; 5121 5122 5123/* 5124 * zone A per-queue data 5125 */ 5126struct xstorm_queue_zone_data { 5127 struct regpair reserved[4]; 5128}; 5129 5130 5131/* 5132 * zone B per-VF data 5133 */ 5134struct xstorm_vf_zone_data { 5135 struct regpair reserved; 5136}; 5137 5138#endif /* BNX2X_HSI_H */ 5139