bnx2x_hsi.h revision 910b220290a4568ebf7ecc368bd3d1d8236d2335
1/* bnx2x_hsi.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9#ifndef BNX2X_HSI_H 10#define BNX2X_HSI_H 11 12#include "bnx2x_fw_defs.h" 13 14#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 15 16struct license_key { 17 u32 reserved[6]; 18 19 u32 max_iscsi_conn; 20#define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 21#define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0 22#define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 23#define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16 24 25 u32 reserved_a; 26 27 u32 max_fcoe_conn; 28#define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 29#define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0 30#define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 31#define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16 32 33 u32 reserved_b[4]; 34}; 35 36 37#define PORT_0 0 38#define PORT_1 1 39#define PORT_MAX 2 40#define NVM_PATH_MAX 2 41 42/**************************************************************************** 43 * Shared HW configuration * 44 ****************************************************************************/ 45#define PIN_CFG_NA 0x00000000 46#define PIN_CFG_GPIO0_P0 0x00000001 47#define PIN_CFG_GPIO1_P0 0x00000002 48#define PIN_CFG_GPIO2_P0 0x00000003 49#define PIN_CFG_GPIO3_P0 0x00000004 50#define PIN_CFG_GPIO0_P1 0x00000005 51#define PIN_CFG_GPIO1_P1 0x00000006 52#define PIN_CFG_GPIO2_P1 0x00000007 53#define PIN_CFG_GPIO3_P1 0x00000008 54#define PIN_CFG_EPIO0 0x00000009 55#define PIN_CFG_EPIO1 0x0000000a 56#define PIN_CFG_EPIO2 0x0000000b 57#define PIN_CFG_EPIO3 0x0000000c 58#define PIN_CFG_EPIO4 0x0000000d 59#define PIN_CFG_EPIO5 0x0000000e 60#define PIN_CFG_EPIO6 0x0000000f 61#define PIN_CFG_EPIO7 0x00000010 62#define PIN_CFG_EPIO8 0x00000011 63#define PIN_CFG_EPIO9 0x00000012 64#define PIN_CFG_EPIO10 0x00000013 65#define PIN_CFG_EPIO11 0x00000014 66#define PIN_CFG_EPIO12 0x00000015 67#define PIN_CFG_EPIO13 0x00000016 68#define PIN_CFG_EPIO14 0x00000017 69#define PIN_CFG_EPIO15 0x00000018 70#define PIN_CFG_EPIO16 0x00000019 71#define PIN_CFG_EPIO17 0x0000001a 72#define PIN_CFG_EPIO18 0x0000001b 73#define PIN_CFG_EPIO19 0x0000001c 74#define PIN_CFG_EPIO20 0x0000001d 75#define PIN_CFG_EPIO21 0x0000001e 76#define PIN_CFG_EPIO22 0x0000001f 77#define PIN_CFG_EPIO23 0x00000020 78#define PIN_CFG_EPIO24 0x00000021 79#define PIN_CFG_EPIO25 0x00000022 80#define PIN_CFG_EPIO26 0x00000023 81#define PIN_CFG_EPIO27 0x00000024 82#define PIN_CFG_EPIO28 0x00000025 83#define PIN_CFG_EPIO29 0x00000026 84#define PIN_CFG_EPIO30 0x00000027 85#define PIN_CFG_EPIO31 0x00000028 86 87/* EPIO definition */ 88#define EPIO_CFG_NA 0x00000000 89#define EPIO_CFG_EPIO0 0x00000001 90#define EPIO_CFG_EPIO1 0x00000002 91#define EPIO_CFG_EPIO2 0x00000003 92#define EPIO_CFG_EPIO3 0x00000004 93#define EPIO_CFG_EPIO4 0x00000005 94#define EPIO_CFG_EPIO5 0x00000006 95#define EPIO_CFG_EPIO6 0x00000007 96#define EPIO_CFG_EPIO7 0x00000008 97#define EPIO_CFG_EPIO8 0x00000009 98#define EPIO_CFG_EPIO9 0x0000000a 99#define EPIO_CFG_EPIO10 0x0000000b 100#define EPIO_CFG_EPIO11 0x0000000c 101#define EPIO_CFG_EPIO12 0x0000000d 102#define EPIO_CFG_EPIO13 0x0000000e 103#define EPIO_CFG_EPIO14 0x0000000f 104#define EPIO_CFG_EPIO15 0x00000010 105#define EPIO_CFG_EPIO16 0x00000011 106#define EPIO_CFG_EPIO17 0x00000012 107#define EPIO_CFG_EPIO18 0x00000013 108#define EPIO_CFG_EPIO19 0x00000014 109#define EPIO_CFG_EPIO20 0x00000015 110#define EPIO_CFG_EPIO21 0x00000016 111#define EPIO_CFG_EPIO22 0x00000017 112#define EPIO_CFG_EPIO23 0x00000018 113#define EPIO_CFG_EPIO24 0x00000019 114#define EPIO_CFG_EPIO25 0x0000001a 115#define EPIO_CFG_EPIO26 0x0000001b 116#define EPIO_CFG_EPIO27 0x0000001c 117#define EPIO_CFG_EPIO28 0x0000001d 118#define EPIO_CFG_EPIO29 0x0000001e 119#define EPIO_CFG_EPIO30 0x0000001f 120#define EPIO_CFG_EPIO31 0x00000020 121 122 123struct shared_hw_cfg { /* NVRAM Offset */ 124 /* Up to 16 bytes of NULL-terminated string */ 125 u8 part_num[16]; /* 0x104 */ 126 127 u32 config; /* 0x114 */ 128 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 129 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 130 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 131 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 132 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002 133 134 #define SHARED_HW_CFG_PORT_SWAP 0x00000004 135 136 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 137 138 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 139 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 140 141 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 142 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 143 /* Whatever MFW found in NVM 144 (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 145 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 146 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 147 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 148 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 149 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 150 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 151 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 152 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 153 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 154 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 155 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 156 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 157 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 158 159 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000 160 #define SHARED_HW_CFG_LED_MODE_SHIFT 16 161 #define SHARED_HW_CFG_LED_MAC1 0x00000000 162 #define SHARED_HW_CFG_LED_PHY1 0x00010000 163 #define SHARED_HW_CFG_LED_PHY2 0x00020000 164 #define SHARED_HW_CFG_LED_PHY3 0x00030000 165 #define SHARED_HW_CFG_LED_MAC2 0x00040000 166 #define SHARED_HW_CFG_LED_PHY4 0x00050000 167 #define SHARED_HW_CFG_LED_PHY5 0x00060000 168 #define SHARED_HW_CFG_LED_PHY6 0x00070000 169 #define SHARED_HW_CFG_LED_MAC3 0x00080000 170 #define SHARED_HW_CFG_LED_PHY7 0x00090000 171 #define SHARED_HW_CFG_LED_PHY9 0x000a0000 172 #define SHARED_HW_CFG_LED_PHY11 0x000b0000 173 #define SHARED_HW_CFG_LED_MAC4 0x000c0000 174 #define SHARED_HW_CFG_LED_PHY8 0x000d0000 175 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 176 177 178 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000 179 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24 180 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000 181 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000 182 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000 183 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000 184 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000 185 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000 186 187 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 188 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 189 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 190 191 #define SHARED_HW_CFG_ATC_MASK 0x80000000 192 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 193 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 194 195 u32 config2; /* 0x118 */ 196 /* one time auto detect grace period (in sec) */ 197 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff 198 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0 199 200 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 201 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 202 203 /* The default value for the core clock is 250MHz and it is 204 achieved by setting the clock change to 4 */ 205 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00 206 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9 207 208 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 209 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 210 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 211 212 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 213 214 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000 215 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000 216 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000 217 218 /* Output low when PERST is asserted */ 219 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 220 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 221 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 222 223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 224 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 225 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 226 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 227 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 228 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 229 230 /* The fan failure mechanism is usually related to the PHY type 231 since the power consumption of the board is determined by the PHY. 232 Currently, fan is required for most designs with SFX7101, BCM8727 233 and BCM8481. If a fan is not required for a board which uses one 234 of those PHYs, this field should be set to "Disabled". If a fan is 235 required for a different PHY type, this option should be set to 236 "Enabled". The fan failure indication is expected on SPIO5 */ 237 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 238 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 239 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 240 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 241 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 242 243 /* ASPM Power Management support */ 244 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 245 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 246 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 247 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 248 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 249 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 250 251 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 252 tl_control_0 (register 0x2800) */ 253 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 254 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 255 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 256 257 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000 258 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000 259 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000 260 261 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000 262 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000 263 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000 264 265 /* Set the MDC/MDIO access for the first external phy */ 266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 273 274 /* Set the MDC/MDIO access for the second external phy */ 275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 281 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 282 283 284 u32 power_dissipated; /* 0x11c */ 285 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000 286 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16 287 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000 288 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000 289 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000 290 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000 291 292 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 293 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24 294 295 u32 ump_nc_si_config; /* 0x120 */ 296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 297 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 298 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 299 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 301 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 302 303 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00 304 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8 305 306 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000 307 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16 308 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000 309 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 310 311 u32 board; /* 0x124 */ 312 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 313 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 314 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 315 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 316 /* Use the PIN_CFG_XXX defines on top */ 317 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000 318 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 319 320 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000 321 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 322 323 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000 324 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 325 326 u32 wc_lane_config; /* 0x128 */ 327 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 328 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 329 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 330 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 331 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 332 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 333 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 334 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 335 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 336 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 337 338 /* TX lane Polarity swap */ 339 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 340 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 341 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 342 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 343 /* TX lane Polarity swap */ 344 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 345 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 346 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 347 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 348 349 /* Selects the port layout of the board */ 350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 357 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 358}; 359 360 361/**************************************************************************** 362 * Port HW configuration * 363 ****************************************************************************/ 364struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 365 366 u32 pci_id; 367 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 368 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff 369 370 u32 pci_sub_id; 371 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 372 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff 373 374 u32 power_dissipated; 375 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff 376 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 377 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00 378 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 379 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000 380 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 381 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000 382 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 383 384 u32 power_consumed; 385 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff 386 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 387 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00 388 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 389 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000 390 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 391 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000 392 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 393 394 u32 mac_upper; 395 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff 396 #define PORT_HW_CFG_UPPERMAC_SHIFT 0 397 u32 mac_lower; 398 399 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 400 u32 iscsi_mac_lower; 401 402 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ 403 u32 rdma_mac_lower; 404 405 u32 serdes_config; 406 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff 407 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 408 409 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000 410 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 411 412 413 /* Default values: 2P-64, 4P-32 */ 414 u32 pf_config; /* 0x158 */ 415 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F 416 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0 417 418 /* Default values: 17 */ 419 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00 420 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8 421 422 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000 423 #define PORT_HW_CFG_FLR_ENABLED 0x00010000 424 425 u32 vf_config; /* 0x15C */ 426 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F 427 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0 428 429 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 430 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 431 432 u32 mf_pci_id; /* 0x160 */ 433 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 434 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 435 436 /* Controls the TX laser of the SFP+ module */ 437 u32 sfp_ctrl; /* 0x164 */ 438 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 439 #define PORT_HW_CFG_TX_LASER_SHIFT 0 440 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 441 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 442 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 443 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 444 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 445 446 /* Controls the fault module LED of the SFP+ */ 447 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 448 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 449 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 450 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 451 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 452 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 453 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 454 455 /* The output pin TX_DIS that controls the TX laser of the SFP+ 456 module. Use the PIN_CFG_XXX defines on top */ 457 u32 e3_sfp_ctrl; /* 0x168 */ 458 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 459 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 460 461 /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 462 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 463 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 464 465 /* The input pin MOD_ABS that indicates whether SFP+ module is 466 present or not. Use the PIN_CFG_XXX defines on top */ 467 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 468 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 469 470 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 471 module. Use the PIN_CFG_XXX defines on top */ 472 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 473 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 474 475 /* 476 * The input pin which signals module transmit fault. Use the 477 * PIN_CFG_XXX defines on top 478 */ 479 u32 e3_cmn_pin_cfg; /* 0x16C */ 480 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 481 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 482 483 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 484 top */ 485 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 486 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 487 488 /* 489 * The output pin which powers down the PHY. Use the PIN_CFG_XXX 490 * defines on top 491 */ 492 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 493 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 494 495 /* The output pin values BSC_SEL which selects the I2C for this port 496 in the I2C Mux */ 497 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 498 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 499 500 501 /* 502 * The input pin I_FAULT which indicate over-current has occurred. 503 * Use the PIN_CFG_XXX defines on top 504 */ 505 u32 e3_cmn_pin_cfg1; /* 0x170 */ 506 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 507 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 508 u32 reserved0[7]; /* 0x174 */ 509 510 u32 aeu_int_mask; /* 0x190 */ 511 512 u32 media_type; /* 0x194 */ 513 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 514 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 515 516 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 517 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 518 519 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 520 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 521 522 /* 4 times 16 bits for all 4 lanes. In case external PHY is present 523 (not direct mode), those values will not take effect on the 4 XGXS 524 lanes. For some external PHYs (such as 8706 and 8726) the values 525 will be used to configure the external PHY in those cases, not 526 all 4 values are needed. */ 527 u16 xgxs_config_rx[4]; /* 0x198 */ 528 u16 xgxs_config_tx[4]; /* 0x1A0 */ 529 530 /* For storing FCOE mac on shared memory */ 531 u32 fcoe_fip_mac_upper; 532 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 533 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 534 u32 fcoe_fip_mac_lower; 535 536 u32 fcoe_wwn_port_name_upper; 537 u32 fcoe_wwn_port_name_lower; 538 539 u32 fcoe_wwn_node_name_upper; 540 u32 fcoe_wwn_node_name_lower; 541 542 u32 Reserved1[49]; /* 0x1C0 */ 543 544 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 545 84833 only */ 546 u32 xgbt_phy_cfg; /* 0x284 */ 547 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 548 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 549 550 u32 default_cfg; /* 0x288 */ 551 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 552 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 553 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 554 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 555 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 556 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 557 558 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 559 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 560 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 561 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 562 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 563 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 564 565 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 566 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 567 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 568 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 569 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 570 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 571 572 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 573 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 574 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 575 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 576 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 577 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 578 579 /* When KR link is required to be set to force which is not 580 KR-compliant, this parameter determine what is the trigger for it. 581 When GPIO is selected, low input will force the speed. Currently 582 default speed is 1G. In the future, it may be widen to select the 583 forced speed in with another parameter. Note when force-1G is 584 enabled, it override option 56: Link Speed option. */ 585 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 586 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 587 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 588 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 589 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 590 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 591 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 592 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 593 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 594 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 595 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 596 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 597 /* Enable to determine with which GPIO to reset the external phy */ 598 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 599 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 600 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 601 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 602 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 603 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 604 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 605 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 606 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 607 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 608 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 609 610 /* Enable BAM on KR */ 611 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 612 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 613 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 614 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 615 616 /* Enable Common Mode Sense */ 617 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 618 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 619 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 620 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 621 622 /* Determine the Serdes electrical interface */ 623 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 624 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 625 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 626 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 627 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 628 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 629 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 630 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 631 632 633 u32 speed_capability_mask2; /* 0x28C */ 634 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 635 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 636 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 637 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002 638 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004 639 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 640 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 641 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020 642 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 643 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 644 645 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 646 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 647 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 648 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000 649 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000 650 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 651 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 652 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000 653 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 654 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 655 656 657 /* In the case where two media types (e.g. copper and fiber) are 658 present and electrically active at the same time, PHY Selection 659 will determine which of the two PHYs will be designated as the 660 Active PHY and used for a connection to the network. */ 661 u32 multi_phy_config; /* 0x290 */ 662 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 663 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 664 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 665 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 666 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 667 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 668 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 669 670 /* When enabled, all second phy nvram parameters will be swapped 671 with the first phy parameters */ 672 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 673 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 674 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 675 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 676 677 678 /* Address of the second external phy */ 679 u32 external_phy_config2; /* 0x294 */ 680 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 681 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 682 683 /* The second XGXS external PHY type */ 684 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 685 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 686 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 687 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 688 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 689 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 690 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 691 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 692 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 693 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 694 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 695 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 696 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 697 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 698 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 699 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 700 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 701 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 702 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 703 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 704 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 705 706 707 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 708 8706, 8726 and 8727) not all 4 values are needed. */ 709 u16 xgxs_config2_rx[4]; /* 0x296 */ 710 u16 xgxs_config2_tx[4]; /* 0x2A0 */ 711 712 u32 lane_config; 713 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff 714 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 715 /* AN and forced */ 716 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 717 /* forced only */ 718 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 719 /* forced only */ 720 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 721 /* forced only */ 722 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 723 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff 724 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 725 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00 726 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 727 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000 728 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 729 730 /* Indicate whether to swap the external phy polarity */ 731 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 732 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 733 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 734 735 736 u32 external_phy_config; 737 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff 738 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 739 740 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00 741 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 742 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 743 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 744 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 745 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 746 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 747 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 748 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 749 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 750 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 751 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 752 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 753 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 754 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 755 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 756 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 757 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 758 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 759 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 760 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 761 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 762 763 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000 764 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 765 766 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000 767 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 768 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 769 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 770 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 771 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 772 773 u32 speed_capability_mask; 774 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff 775 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 776 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 777 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 778 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 779 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 780 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 781 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 782 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 783 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 784 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 785 786 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000 787 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 788 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 789 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 790 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 791 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 792 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 793 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 794 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 795 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 796 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 797 798 /* A place to hold the original MAC address as a backup */ 799 u32 backup_mac_upper; /* 0x2B4 */ 800 u32 backup_mac_lower; /* 0x2B8 */ 801 802}; 803 804 805/**************************************************************************** 806 * Shared Feature configuration * 807 ****************************************************************************/ 808struct shared_feat_cfg { /* NVRAM Offset */ 809 810 u32 config; /* 0x450 */ 811 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 812 813 /* Use NVRAM values instead of HW default values */ 814 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 815 0x00000002 816 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 817 0x00000000 818 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 819 0x00000002 820 821 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 822 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 823 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 824 825 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 826 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 827 828 /* Override the OTP back to single function mode. When using GPIO, 829 high means only SF, 0 is according to CLP configuration */ 830 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 831 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 832 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 833 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 834 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 835 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 836 837 /* The interval in seconds between sending LLDP packets. Set to zero 838 to disable the feature */ 839 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000 840 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 841 842 /* The assigned device type ID for LLDP usage */ 843 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000 844 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 845 846}; 847 848 849/**************************************************************************** 850 * Port Feature configuration * 851 ****************************************************************************/ 852struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 853 854 u32 config; 855 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f 856 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 857 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000 858 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001 859 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002 860 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003 861 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004 862 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005 863 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006 864 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007 865 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008 866 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009 867 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a 868 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b 869 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c 870 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d 871 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e 872 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f 873 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0 874 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4 875 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000 876 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010 877 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020 878 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030 879 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040 880 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050 881 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060 882 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070 883 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080 884 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090 885 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0 886 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0 887 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0 888 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0 889 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0 890 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0 891 892 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 893 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 894 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 895 896 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 897 #define PORT_FEATURE_EN_SIZE_SHIFT 24 898 #define PORT_FEATURE_WOL_ENABLED 0x01000000 899 #define PORT_FEATURE_MBA_ENABLED 0x02000000 900 #define PORT_FEATURE_MFW_ENABLED 0x04000000 901 902 /* Advertise expansion ROM even if MBA is disabled */ 903 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 904 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 905 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 906 907 /* Check the optic vendor via i2c against a list of approved modules 908 in a separate nvram image */ 909 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000 910 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 911 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 912 0x00000000 913 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 914 0x20000000 915 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 916 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 917 918 u32 wol_config; 919 /* Default is used when driver sets to "auto" mode */ 920 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 921 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0 922 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000 923 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001 924 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002 925 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003 926 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004 927 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008 928 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 929 930 u32 mba_config; 931 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 932 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 933 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 934 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 935 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 936 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 937 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 938 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 939 940 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 941 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 942 943 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 944 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 945 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 946 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 947 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 948 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 949 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000 950 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 951 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 952 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 953 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 954 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 955 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 956 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 957 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 958 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 959 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 960 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 961 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 962 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 963 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 964 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 965 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 966 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 967 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000 968 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 969 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 970 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 971 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 972 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 973 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 974 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 975 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000 976 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 977 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 978 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000 979 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000 980 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000 981 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000 982 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000 983 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000 984 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000 985 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000 986 u32 bmc_config; 987 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001 988 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000 989 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001 990 991 u32 mba_vlan_cfg; 992 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff 993 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 994 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 995 996 u32 resource_cfg; 997 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001 998 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002 999 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004 1000 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008 1001 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010 1002 1003 u32 smbus_config; 1004 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1005 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1006 1007 u32 vf_config; 1008 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f 1009 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1010 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1011 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1012 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1013 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1014 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1015 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1016 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1017 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1018 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1019 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1020 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1021 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1022 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1023 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1024 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1025 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1026 1027 u32 link_config; /* Used as HW defaults for the driver */ 1028 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1029 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1030 /* (forced) low speed switch (< 10G) */ 1031 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1032 /* (forced) high speed switch (>= 10G) */ 1033 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1034 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1035 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1036 1037 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000 1038 #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1039 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1040 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 1041 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 1042 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1043 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1044 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1045 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1046 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1047 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1048 1049 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1050 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1051 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1052 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1053 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1054 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1055 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1056 1057 /* The default for MCP link configuration, 1058 uses the same defines as link_config */ 1059 u32 mfw_wol_link_cfg; 1060 1061 /* The default for the driver of the second external phy, 1062 uses the same defines as link_config */ 1063 u32 link_config2; /* 0x47C */ 1064 1065 /* The default for MCP of the second external phy, 1066 uses the same defines as link_config */ 1067 u32 mfw_wol_link_cfg2; /* 0x480 */ 1068 1069 u32 Reserved2[17]; /* 0x484 */ 1070 1071}; 1072 1073 1074/**************************************************************************** 1075 * Device Information * 1076 ****************************************************************************/ 1077struct shm_dev_info { /* size */ 1078 1079 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1080 1081 struct shared_hw_cfg shared_hw_config; /* 40 */ 1082 1083 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1084 1085 struct shared_feat_cfg shared_feature_config; /* 4 */ 1086 1087 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1088 1089}; 1090 1091 1092#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 1093 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 1094#endif 1095 1096#define FUNC_0 0 1097#define FUNC_1 1 1098#define FUNC_2 2 1099#define FUNC_3 3 1100#define FUNC_4 4 1101#define FUNC_5 5 1102#define FUNC_6 6 1103#define FUNC_7 7 1104#define E1_FUNC_MAX 2 1105#define E1H_FUNC_MAX 8 1106#define E2_FUNC_MAX 4 /* per path */ 1107 1108#define VN_0 0 1109#define VN_1 1 1110#define VN_2 2 1111#define VN_3 3 1112#define E1VN_MAX 1 1113#define E1HVN_MAX 4 1114 1115#define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ 1116/* This value (in milliseconds) determines the frequency of the driver 1117 * issuing the PULSE message code. The firmware monitors this periodic 1118 * pulse to determine when to switch to an OS-absent mode. */ 1119#define DRV_PULSE_PERIOD_MS 250 1120 1121/* This value (in milliseconds) determines how long the driver should 1122 * wait for an acknowledgement from the firmware before timing out. Once 1123 * the firmware has timed out, the driver will assume there is no firmware 1124 * running and there won't be any firmware-driver synchronization during a 1125 * driver reset. */ 1126#define FW_ACK_TIME_OUT_MS 5000 1127 1128#define FW_ACK_POLL_TIME_MS 1 1129 1130#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 1131 1132/**************************************************************************** 1133 * Driver <-> FW Mailbox * 1134 ****************************************************************************/ 1135struct drv_port_mb { 1136 1137 u32 link_status; 1138 /* Driver should update this field on any link change event */ 1139 1140 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 1141 #define LINK_STATUS_LINK_UP 0x00000001 1142 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 1143 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 1144 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 1145 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 1146 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 1147 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 1148 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 1149 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 1150 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 1151 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 1152 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 1153 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 1154 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 1155 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 1156 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 1157 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) 1158 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) 1159 1160 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 1161 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 1162 1163 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 1164 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 1165 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 1166 1167 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 1168 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 1169 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 1170 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 1171 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 1172 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 1173 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 1174 1175 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 1176 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 1177 1178 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 1179 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 1180 1181 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 1182 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 1183 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 1184 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 1185 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 1186 1187 #define LINK_STATUS_SERDES_LINK 0x00100000 1188 1189 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 1190 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 1191 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 1192 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 1193 1194 #define LINK_STATUS_PFC_ENABLED 0x20000000 1195 1196 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 1197 1198 u32 port_stx; 1199 1200 u32 stat_nig_timer; 1201 1202 /* MCP firmware does not use this field */ 1203 u32 ext_phy_fw_version; 1204 1205}; 1206 1207 1208struct drv_func_mb { 1209 1210 u32 drv_mb_header; 1211 #define DRV_MSG_CODE_MASK 0xffff0000 1212 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1213 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1214 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 1215 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 1216 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 1217 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1218 #define DRV_MSG_CODE_DCC_OK 0x30000000 1219 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 1220 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 1221 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 1222 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 1223 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 1224 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 1225 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 1226 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 1227 /* 1228 * The optic module verification command requires bootcode 1229 * v5.0.6 or later, te specific optic module verification command 1230 * requires bootcode v5.2.12 or later 1231 */ 1232 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 1233 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 1234 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 1235 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 1236 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 1237 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 1238 1239 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 1240 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 1241 1242 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1243 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 1244 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 1245 1246 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 1247 #define REQ_BC_VER_4_SET_MF_BW 0x00060202 1248 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 1249 1250 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 1251 1252 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 1253 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 1254 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1255 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1256 1257 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1258 1259 u32 drv_mb_param; 1260 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 1261 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 1262 1263 u32 fw_mb_header; 1264 #define FW_MSG_CODE_MASK 0xffff0000 1265 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 1266 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1267 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1268 /* Load common chip is supported from bc 6.0.0 */ 1269 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 1270 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 1271 1272 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 1273 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1274 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 1275 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 1276 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 1277 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1278 #define FW_MSG_CODE_DCC_DONE 0x30100000 1279 #define FW_MSG_CODE_LLDP_DONE 0x40100000 1280 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 1281 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 1282 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 1283 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 1284 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 1285 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 1286 #define FW_MSG_CODE_NO_KEY 0x80f00000 1287 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 1288 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 1289 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 1290 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 1291 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 1292 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 1293 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 1294 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 1295 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 1296 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1297 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 1298 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 1299 1300 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 1301 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 1302 1303 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 1304 1305 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 1306 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 1307 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1308 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1309 1310 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1311 1312 u32 fw_mb_param; 1313 1314 u32 drv_pulse_mb; 1315 #define DRV_PULSE_SEQ_MASK 0x00007fff 1316 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1317 /* 1318 * The system time is in the format of 1319 * (year-2001)*12*32 + month*32 + day. 1320 */ 1321 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1322 /* 1323 * Indicate to the firmware not to go into the 1324 * OS-absent when it is not getting driver pulse. 1325 * This is used for debugging as well for PXE(MBA). 1326 */ 1327 1328 u32 mcp_pulse_mb; 1329 #define MCP_PULSE_SEQ_MASK 0x00007fff 1330 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1331 /* Indicates to the driver not to assert due to lack 1332 * of MCP response */ 1333 #define MCP_EVENT_MASK 0xffff0000 1334 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1335 1336 u32 iscsi_boot_signature; 1337 u32 iscsi_boot_block_offset; 1338 1339 u32 drv_status; 1340 #define DRV_STATUS_PMF 0x00000001 1341 #define DRV_STATUS_VF_DISABLED 0x00000002 1342 #define DRV_STATUS_SET_MF_BW 0x00000004 1343 #define DRV_STATUS_LINK_EVENT 0x00000008 1344 1345 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 1346 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 1347 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 1348 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 1349 #define DRV_STATUS_DCC_RESERVED1 0x00000800 1350 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 1351 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 1352 1353 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 1354 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 1355 #define DRV_STATUS_DRV_INFO_REQ 0x04000000 1356 1357 u32 virt_mac_upper; 1358 #define VIRT_MAC_SIGN_MASK 0xffff0000 1359 #define VIRT_MAC_SIGNATURE 0x564d0000 1360 u32 virt_mac_lower; 1361 1362}; 1363 1364 1365/**************************************************************************** 1366 * Management firmware state * 1367 ****************************************************************************/ 1368/* Allocate 440 bytes for management firmware */ 1369#define MGMTFW_STATE_WORD_SIZE 110 1370 1371struct mgmtfw_state { 1372 u32 opaque[MGMTFW_STATE_WORD_SIZE]; 1373}; 1374 1375 1376/**************************************************************************** 1377 * Multi-Function configuration * 1378 ****************************************************************************/ 1379struct shared_mf_cfg { 1380 1381 u32 clp_mb; 1382 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 1383 /* set by CLP */ 1384 #define SHARED_MF_CLP_EXIT 0x00000001 1385 /* set by MCP */ 1386 #define SHARED_MF_CLP_EXIT_DONE 0x00010000 1387 1388}; 1389 1390struct port_mf_cfg { 1391 1392 u32 dynamic_cfg; /* device control channel */ 1393 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1394 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 1395 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 1396 1397 u32 reserved[1]; 1398 1399}; 1400 1401struct func_mf_cfg { 1402 1403 u32 config; 1404 /* E/R/I/D */ 1405 /* function 0 of each port cannot be hidden */ 1406 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 1407 1408 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 1409 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 1410 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 1411 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 1412 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 1413 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ 1414 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 1415 1416 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 1417 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 1418 1419 /* PRI */ 1420 /* 0 - low priority, 3 - high priority */ 1421 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 1422 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 1423 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 1424 1425 /* MINBW, MAXBW */ 1426 /* value range - 0..100, increments in 100Mbps */ 1427 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 1428 #define FUNC_MF_CFG_MIN_BW_SHIFT 16 1429 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 1430 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 1431 #define FUNC_MF_CFG_MAX_BW_SHIFT 24 1432 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 1433 1434 u32 mac_upper; /* MAC */ 1435 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 1436 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 1437 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 1438 u32 mac_lower; 1439 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 1440 1441 u32 e1hov_tag; /* VNI */ 1442 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1443 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 1444 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 1445 1446 u32 reserved[2]; 1447}; 1448 1449/* This structure is not applicable and should not be accessed on 57711 */ 1450struct func_ext_cfg { 1451 u32 func_cfg; 1452 #define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF 1453 #define MACP_FUNC_CFG_FLAGS_SHIFT 0 1454 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 1455 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 1456 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 1457 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 1458 1459 u32 iscsi_mac_addr_upper; 1460 u32 iscsi_mac_addr_lower; 1461 1462 u32 fcoe_mac_addr_upper; 1463 u32 fcoe_mac_addr_lower; 1464 1465 u32 fcoe_wwn_port_name_upper; 1466 u32 fcoe_wwn_port_name_lower; 1467 1468 u32 fcoe_wwn_node_name_upper; 1469 u32 fcoe_wwn_node_name_lower; 1470 1471 u32 preserve_data; 1472 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 1473 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 1474 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 1475 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 1476 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 1477 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) 1478}; 1479 1480struct mf_cfg { 1481 1482 struct shared_mf_cfg shared_mf_config; /* 0x4 */ 1483 /* 0x8*2*2=0x20 */ 1484 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; 1485 /* for all chips, there are 8 mf functions */ 1486 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ 1487 /* 1488 * Extended configuration per function - this array does not exist and 1489 * should not be accessed on 57711 1490 */ 1491 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ 1492}; /* 0x224 */ 1493 1494/**************************************************************************** 1495 * Shared Memory Region * 1496 ****************************************************************************/ 1497struct shmem_region { /* SharedMem Offset (size) */ 1498 1499 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 1500 #define SHR_MEM_FORMAT_REV_MASK 0xff000000 1501 #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 1502 /* validity bits */ 1503 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 1504 #define SHR_MEM_VALIDITY_MB 0x00200000 1505 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 1506 #define SHR_MEM_VALIDITY_RESERVED 0x00000007 1507 /* One licensing bit should be set */ 1508 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 1509 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 1510 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 1511 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 1512 /* Active MFW */ 1513 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 1514 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 1515 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 1516 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 1517 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 1518 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 1519 1520 struct shm_dev_info dev_info; /* 0x8 (0x438) */ 1521 1522 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ 1523 1524 /* FW information (for internal FW use) */ 1525 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ 1526 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 1527 1528 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 1529 1530#ifdef BMAPI 1531 /* This is a variable length array */ 1532 /* the number of function depends on the chip type */ 1533 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1534#else 1535 /* the number of function depends on the chip type */ 1536 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1537#endif /* BMAPI */ 1538 1539}; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 1540 1541/**************************************************************************** 1542 * Shared Memory 2 Region * 1543 ****************************************************************************/ 1544/* The fw_flr_ack is actually built in the following way: */ 1545/* 8 bit: PF ack */ 1546/* 64 bit: VF ack */ 1547/* 8 bit: ios_dis_ack */ 1548/* In order to maintain endianity in the mailbox hsi, we want to keep using */ 1549/* u32. The fw must have the VF right after the PF since this is how it */ 1550/* access arrays(it expects always the VF to reside after the PF, and that */ 1551/* makes the calculation much easier for it. ) */ 1552/* In order to answer both limitations, and keep the struct small, the code */ 1553/* will abuse the structure defined here to achieve the actual partition */ 1554/* above */ 1555/****************************************************************************/ 1556struct fw_flr_ack { 1557 u32 pf_ack; 1558 u32 vf_ack[1]; 1559 u32 iov_dis_ack; 1560}; 1561 1562struct fw_flr_mb { 1563 u32 aggint; 1564 u32 opgen_addr; 1565 struct fw_flr_ack ack; 1566}; 1567 1568/**** SUPPORT FOR SHMEM ARRRAYS *** 1569 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 1570 * define arrays with storage types smaller then unsigned dwords. 1571 * The macros below add generic support for SHMEM arrays with numeric elements 1572 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 1573 * array with individual bit-filed elements accessed using shifts and masks. 1574 * 1575 */ 1576 1577/* eb is the bitwidth of a single element */ 1578#define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 1579#define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 1580 1581/* the bit-position macro allows the used to flip the order of the arrays 1582 * elements on a per byte or word boundary. 1583 * 1584 * example: an array with 8 entries each 4 bit wide. This array will fit into 1585 * a single dword. The diagrmas below show the array order of the nibbles. 1586 * 1587 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: 1588 * 1589 * | | | | 1590 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 1591 * | | | | 1592 * 1593 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 1594 * 1595 * | | | | 1596 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 1597 * | | | | 1598 * 1599 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 1600 * 1601 * | | | | 1602 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 1603 * | | | | 1604 */ 1605#define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 1606 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 1607 (((i)%((fb)/(eb))) * (eb))) 1608 1609#define SHMEM_ARRAY_GET(a, i, eb, fb) \ 1610 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 1611 SHMEM_ARRAY_MASK(eb)) 1612 1613#define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 1614do { \ 1615 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 1616 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1617 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 1618 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1619} while (0) 1620 1621 1622/****START OF DCBX STRUCTURES DECLARATIONS****/ 1623#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 1624#define DCBX_PRI_PG_BITWIDTH 4 1625#define DCBX_PRI_PG_FBITS 8 1626#define DCBX_PRI_PG_GET(a, i) \ 1627 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 1628#define DCBX_PRI_PG_SET(a, i, val) \ 1629 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 1630#define DCBX_MAX_NUM_PG_BW_ENTRIES 8 1631#define DCBX_BW_PG_BITWIDTH 8 1632#define DCBX_PG_BW_GET(a, i) \ 1633 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 1634#define DCBX_PG_BW_SET(a, i, val) \ 1635 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 1636#define DCBX_STRICT_PRI_PG 15 1637#define DCBX_MAX_APP_PROTOCOL 16 1638#define FCOE_APP_IDX 0 1639#define ISCSI_APP_IDX 1 1640#define PREDEFINED_APP_IDX_MAX 2 1641 1642 1643/* Big/Little endian have the same representation. */ 1644struct dcbx_ets_feature { 1645 /* 1646 * For Admin MIB - is this feature supported by the 1647 * driver | For Local MIB - should this feature be enabled. 1648 */ 1649 u32 enabled; 1650 u32 pg_bw_tbl[2]; 1651 u32 pri_pg_tbl[1]; 1652}; 1653 1654/* Driver structure in LE */ 1655struct dcbx_pfc_feature { 1656#ifdef __BIG_ENDIAN 1657 u8 pri_en_bitmap; 1658 #define DCBX_PFC_PRI_0 0x01 1659 #define DCBX_PFC_PRI_1 0x02 1660 #define DCBX_PFC_PRI_2 0x04 1661 #define DCBX_PFC_PRI_3 0x08 1662 #define DCBX_PFC_PRI_4 0x10 1663 #define DCBX_PFC_PRI_5 0x20 1664 #define DCBX_PFC_PRI_6 0x40 1665 #define DCBX_PFC_PRI_7 0x80 1666 u8 pfc_caps; 1667 u8 reserved; 1668 u8 enabled; 1669#elif defined(__LITTLE_ENDIAN) 1670 u8 enabled; 1671 u8 reserved; 1672 u8 pfc_caps; 1673 u8 pri_en_bitmap; 1674 #define DCBX_PFC_PRI_0 0x01 1675 #define DCBX_PFC_PRI_1 0x02 1676 #define DCBX_PFC_PRI_2 0x04 1677 #define DCBX_PFC_PRI_3 0x08 1678 #define DCBX_PFC_PRI_4 0x10 1679 #define DCBX_PFC_PRI_5 0x20 1680 #define DCBX_PFC_PRI_6 0x40 1681 #define DCBX_PFC_PRI_7 0x80 1682#endif 1683}; 1684 1685struct dcbx_app_priority_entry { 1686#ifdef __BIG_ENDIAN 1687 u16 app_id; 1688 u8 pri_bitmap; 1689 u8 appBitfield; 1690 #define DCBX_APP_ENTRY_VALID 0x01 1691 #define DCBX_APP_ENTRY_SF_MASK 0x30 1692 #define DCBX_APP_ENTRY_SF_SHIFT 4 1693 #define DCBX_APP_SF_ETH_TYPE 0x10 1694 #define DCBX_APP_SF_PORT 0x20 1695#elif defined(__LITTLE_ENDIAN) 1696 u8 appBitfield; 1697 #define DCBX_APP_ENTRY_VALID 0x01 1698 #define DCBX_APP_ENTRY_SF_MASK 0x30 1699 #define DCBX_APP_ENTRY_SF_SHIFT 4 1700 #define DCBX_APP_SF_ETH_TYPE 0x10 1701 #define DCBX_APP_SF_PORT 0x20 1702 u8 pri_bitmap; 1703 u16 app_id; 1704#endif 1705}; 1706 1707 1708/* FW structure in BE */ 1709struct dcbx_app_priority_feature { 1710#ifdef __BIG_ENDIAN 1711 u8 reserved; 1712 u8 default_pri; 1713 u8 tc_supported; 1714 u8 enabled; 1715#elif defined(__LITTLE_ENDIAN) 1716 u8 enabled; 1717 u8 tc_supported; 1718 u8 default_pri; 1719 u8 reserved; 1720#endif 1721 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 1722}; 1723 1724/* FW structure in BE */ 1725struct dcbx_features { 1726 /* PG feature */ 1727 struct dcbx_ets_feature ets; 1728 /* PFC feature */ 1729 struct dcbx_pfc_feature pfc; 1730 /* APP feature */ 1731 struct dcbx_app_priority_feature app; 1732}; 1733 1734/* LLDP protocol parameters */ 1735/* FW structure in BE */ 1736struct lldp_params { 1737#ifdef __BIG_ENDIAN 1738 u8 msg_fast_tx_interval; 1739 u8 msg_tx_hold; 1740 u8 msg_tx_interval; 1741 u8 admin_status; 1742 #define LLDP_TX_ONLY 0x01 1743 #define LLDP_RX_ONLY 0x02 1744 #define LLDP_TX_RX 0x03 1745 #define LLDP_DISABLED 0x04 1746 u8 reserved1; 1747 u8 tx_fast; 1748 u8 tx_crd_max; 1749 u8 tx_crd; 1750#elif defined(__LITTLE_ENDIAN) 1751 u8 admin_status; 1752 #define LLDP_TX_ONLY 0x01 1753 #define LLDP_RX_ONLY 0x02 1754 #define LLDP_TX_RX 0x03 1755 #define LLDP_DISABLED 0x04 1756 u8 msg_tx_interval; 1757 u8 msg_tx_hold; 1758 u8 msg_fast_tx_interval; 1759 u8 tx_crd; 1760 u8 tx_crd_max; 1761 u8 tx_fast; 1762 u8 reserved1; 1763#endif 1764 #define REM_CHASSIS_ID_STAT_LEN 4 1765 #define REM_PORT_ID_STAT_LEN 4 1766 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 1767 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 1768 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 1769 u32 peer_port_id[REM_PORT_ID_STAT_LEN]; 1770}; 1771 1772struct lldp_dcbx_stat { 1773 #define LOCAL_CHASSIS_ID_STAT_LEN 2 1774 #define LOCAL_PORT_ID_STAT_LEN 2 1775 /* Holds local Chassis ID 8B payload of constant subtype 4. */ 1776 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 1777 /* Holds local Port ID 8B payload of constant subtype 3. */ 1778 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN]; 1779 /* Number of DCBX frames transmitted. */ 1780 u32 num_tx_dcbx_pkts; 1781 /* Number of DCBX frames received. */ 1782 u32 num_rx_dcbx_pkts; 1783}; 1784 1785/* ADMIN MIB - DCBX local machine default configuration. */ 1786struct lldp_admin_mib { 1787 u32 ver_cfg_flags; 1788 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 1789 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 1790 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 1791 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 1792 #define DCBX_ETS_RECO_VALID 0x00000010 1793 #define DCBX_ETS_WILLING 0x00000020 1794 #define DCBX_PFC_WILLING 0x00000040 1795 #define DCBX_APP_WILLING 0x00000080 1796 #define DCBX_VERSION_CEE 0x00000100 1797 #define DCBX_VERSION_IEEE 0x00000200 1798 #define DCBX_DCBX_ENABLED 0x00000400 1799 #define DCBX_CEE_VERSION_MASK 0x0000f000 1800 #define DCBX_CEE_VERSION_SHIFT 12 1801 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 1802 #define DCBX_CEE_MAX_VERSION_SHIFT 16 1803 struct dcbx_features features; 1804}; 1805 1806/* REMOTE MIB - remote machine DCBX configuration. */ 1807struct lldp_remote_mib { 1808 u32 prefix_seq_num; 1809 u32 flags; 1810 #define DCBX_ETS_TLV_RX 0x00000001 1811 #define DCBX_PFC_TLV_RX 0x00000002 1812 #define DCBX_APP_TLV_RX 0x00000004 1813 #define DCBX_ETS_RX_ERROR 0x00000010 1814 #define DCBX_PFC_RX_ERROR 0x00000020 1815 #define DCBX_APP_RX_ERROR 0x00000040 1816 #define DCBX_ETS_REM_WILLING 0x00000100 1817 #define DCBX_PFC_REM_WILLING 0x00000200 1818 #define DCBX_APP_REM_WILLING 0x00000400 1819 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 1820 #define DCBX_REMOTE_MIB_VALID 0x00002000 1821 struct dcbx_features features; 1822 u32 suffix_seq_num; 1823}; 1824 1825/* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ 1826struct lldp_local_mib { 1827 u32 prefix_seq_num; 1828 /* Indicates if there is mismatch with negotiation results. */ 1829 u32 error; 1830 #define DCBX_LOCAL_ETS_ERROR 0x00000001 1831 #define DCBX_LOCAL_PFC_ERROR 0x00000002 1832 #define DCBX_LOCAL_APP_ERROR 0x00000004 1833 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 1834 #define DCBX_LOCAL_APP_MISMATCH 0x00000020 1835 #define DCBX_REMOTE_MIB_ERROR 0x00000040 1836 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 1837 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 1838 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 1839 struct dcbx_features features; 1840 u32 suffix_seq_num; 1841}; 1842/***END OF DCBX STRUCTURES DECLARATIONS***/ 1843 1844struct ncsi_oem_fcoe_features { 1845 u32 fcoe_features1; 1846 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF 1847 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0 1848 1849 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000 1850 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16 1851 1852 u32 fcoe_features2; 1853 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF 1854 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0 1855 1856 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000 1857 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16 1858 1859 u32 fcoe_features3; 1860 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF 1861 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0 1862 1863 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000 1864 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16 1865 1866 u32 fcoe_features4; 1867 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F 1868 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0 1869}; 1870 1871struct ncsi_oem_data { 1872 u32 driver_version[4]; 1873 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features; 1874}; 1875 1876struct shmem2_region { 1877 1878 u32 size; /* 0x0000 */ 1879 1880 u32 dcc_support; /* 0x0004 */ 1881 #define SHMEM_DCC_SUPPORT_NONE 0x00000000 1882 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 1883 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 1884 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 1885 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 1886 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 1887 1888 u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ 1889 /* 1890 * For backwards compatibility, if the mf_cfg_addr does not exist 1891 * (the size filed is smaller than 0xc) the mf_cfg resides at the 1892 * end of struct shmem_region 1893 */ 1894 u32 mf_cfg_addr; /* 0x0010 */ 1895 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 1896 1897 struct fw_flr_mb flr_mb; /* 0x0014 */ 1898 u32 dcbx_lldp_params_offset; /* 0x0028 */ 1899 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 1900 u32 dcbx_neg_res_offset; /* 0x002c */ 1901 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 1902 u32 dcbx_remote_mib_offset; /* 0x0030 */ 1903 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 1904 /* 1905 * The other shmemX_base_addr holds the other path's shmem address 1906 * required for example in case of common phy init, or for path1 to know 1907 * the address of mcp debug trace which is located in offset from shmem 1908 * of path0 1909 */ 1910 u32 other_shmem_base_addr; /* 0x0034 */ 1911 u32 other_shmem2_base_addr; /* 0x0038 */ 1912 /* 1913 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 1914 * which were disabled/flred 1915 */ 1916 u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ 1917 1918 /* 1919 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 1920 * VFs 1921 */ 1922 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ 1923 1924 u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ 1925 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 1926 1927 /* 1928 * edebug_driver_if field is used to transfer messages between edebug 1929 * app to the driver through shmem2. 1930 * 1931 * message format: 1932 * bits 0-2 - function number / instance of driver to perform request 1933 * bits 3-5 - op code / is_ack? 1934 * bits 6-63 - data 1935 */ 1936 u32 edebug_driver_if[2]; /* 0x0068 */ 1937 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 1938 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 1939 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 1940 1941 u32 nvm_retain_bitmap_addr; /* 0x0070 */ 1942 1943 u32 reserved1; /* 0x0074 */ 1944 1945 u32 reserved2[E2_FUNC_MAX]; 1946 1947 u32 reserved3[E2_FUNC_MAX];/* 0x0088 */ 1948 u32 reserved4[E2_FUNC_MAX];/* 0x0098 */ 1949 1950 u32 swim_base_addr; /* 0x0108 */ 1951 u32 swim_funcs; 1952 u32 swim_main_cb; 1953 1954 u32 reserved5[2]; 1955 1956 /* generic flags controlled by the driver */ 1957 u32 drv_flags; 1958 #define DRV_FLAGS_DCB_CONFIGURED 0x1 1959 1960 /* pointer to extended dev_info shared data copied from nvm image */ 1961 u32 extended_dev_info_shared_addr; 1962 u32 ncsi_oem_data_addr; 1963 1964 u32 ocsd_host_addr; /* initialized by option ROM */ 1965 u32 ocbb_host_addr; /* initialized by option ROM */ 1966 u32 ocsd_req_update_interval; /* initialized by option ROM */ 1967 u32 temperature_in_half_celsius; 1968 u32 glob_struct_in_host; 1969 1970 u32 dcbx_neg_res_ext_offset; 1971#define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 1972 1973 u32 drv_capabilities_flag[E2_FUNC_MAX]; 1974#define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 1975#define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 1976#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 1977#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 1978 1979 u32 extended_dev_info_shared_cfg_size; 1980 1981 u32 dcbx_en[PORT_MAX]; 1982 1983 /* The offset points to the multi threaded meta structure */ 1984 u32 multi_thread_data_offset; 1985 1986 /* address of DMAable host address holding values from the drivers */ 1987 u32 drv_info_host_addr_lo; 1988 u32 drv_info_host_addr_hi; 1989 1990 /* general values written by the MFW (such as current version) */ 1991 u32 drv_info_control; 1992#define DRV_INFO_CONTROL_VER_MASK 0x000000ff 1993#define DRV_INFO_CONTROL_VER_SHIFT 0 1994#define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 1995#define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 1996 u32 ibft_host_addr; /* initialized by option ROM */ 1997}; 1998 1999 2000struct emac_stats { 2001 u32 rx_stat_ifhcinoctets; 2002 u32 rx_stat_ifhcinbadoctets; 2003 u32 rx_stat_etherstatsfragments; 2004 u32 rx_stat_ifhcinucastpkts; 2005 u32 rx_stat_ifhcinmulticastpkts; 2006 u32 rx_stat_ifhcinbroadcastpkts; 2007 u32 rx_stat_dot3statsfcserrors; 2008 u32 rx_stat_dot3statsalignmenterrors; 2009 u32 rx_stat_dot3statscarriersenseerrors; 2010 u32 rx_stat_xonpauseframesreceived; 2011 u32 rx_stat_xoffpauseframesreceived; 2012 u32 rx_stat_maccontrolframesreceived; 2013 u32 rx_stat_xoffstateentered; 2014 u32 rx_stat_dot3statsframestoolong; 2015 u32 rx_stat_etherstatsjabbers; 2016 u32 rx_stat_etherstatsundersizepkts; 2017 u32 rx_stat_etherstatspkts64octets; 2018 u32 rx_stat_etherstatspkts65octetsto127octets; 2019 u32 rx_stat_etherstatspkts128octetsto255octets; 2020 u32 rx_stat_etherstatspkts256octetsto511octets; 2021 u32 rx_stat_etherstatspkts512octetsto1023octets; 2022 u32 rx_stat_etherstatspkts1024octetsto1522octets; 2023 u32 rx_stat_etherstatspktsover1522octets; 2024 2025 u32 rx_stat_falsecarriererrors; 2026 2027 u32 tx_stat_ifhcoutoctets; 2028 u32 tx_stat_ifhcoutbadoctets; 2029 u32 tx_stat_etherstatscollisions; 2030 u32 tx_stat_outxonsent; 2031 u32 tx_stat_outxoffsent; 2032 u32 tx_stat_flowcontroldone; 2033 u32 tx_stat_dot3statssinglecollisionframes; 2034 u32 tx_stat_dot3statsmultiplecollisionframes; 2035 u32 tx_stat_dot3statsdeferredtransmissions; 2036 u32 tx_stat_dot3statsexcessivecollisions; 2037 u32 tx_stat_dot3statslatecollisions; 2038 u32 tx_stat_ifhcoutucastpkts; 2039 u32 tx_stat_ifhcoutmulticastpkts; 2040 u32 tx_stat_ifhcoutbroadcastpkts; 2041 u32 tx_stat_etherstatspkts64octets; 2042 u32 tx_stat_etherstatspkts65octetsto127octets; 2043 u32 tx_stat_etherstatspkts128octetsto255octets; 2044 u32 tx_stat_etherstatspkts256octetsto511octets; 2045 u32 tx_stat_etherstatspkts512octetsto1023octets; 2046 u32 tx_stat_etherstatspkts1024octetsto1522octets; 2047 u32 tx_stat_etherstatspktsover1522octets; 2048 u32 tx_stat_dot3statsinternalmactransmiterrors; 2049}; 2050 2051 2052struct bmac1_stats { 2053 u32 tx_stat_gtpkt_lo; 2054 u32 tx_stat_gtpkt_hi; 2055 u32 tx_stat_gtxpf_lo; 2056 u32 tx_stat_gtxpf_hi; 2057 u32 tx_stat_gtfcs_lo; 2058 u32 tx_stat_gtfcs_hi; 2059 u32 tx_stat_gtmca_lo; 2060 u32 tx_stat_gtmca_hi; 2061 u32 tx_stat_gtbca_lo; 2062 u32 tx_stat_gtbca_hi; 2063 u32 tx_stat_gtfrg_lo; 2064 u32 tx_stat_gtfrg_hi; 2065 u32 tx_stat_gtovr_lo; 2066 u32 tx_stat_gtovr_hi; 2067 u32 tx_stat_gt64_lo; 2068 u32 tx_stat_gt64_hi; 2069 u32 tx_stat_gt127_lo; 2070 u32 tx_stat_gt127_hi; 2071 u32 tx_stat_gt255_lo; 2072 u32 tx_stat_gt255_hi; 2073 u32 tx_stat_gt511_lo; 2074 u32 tx_stat_gt511_hi; 2075 u32 tx_stat_gt1023_lo; 2076 u32 tx_stat_gt1023_hi; 2077 u32 tx_stat_gt1518_lo; 2078 u32 tx_stat_gt1518_hi; 2079 u32 tx_stat_gt2047_lo; 2080 u32 tx_stat_gt2047_hi; 2081 u32 tx_stat_gt4095_lo; 2082 u32 tx_stat_gt4095_hi; 2083 u32 tx_stat_gt9216_lo; 2084 u32 tx_stat_gt9216_hi; 2085 u32 tx_stat_gt16383_lo; 2086 u32 tx_stat_gt16383_hi; 2087 u32 tx_stat_gtmax_lo; 2088 u32 tx_stat_gtmax_hi; 2089 u32 tx_stat_gtufl_lo; 2090 u32 tx_stat_gtufl_hi; 2091 u32 tx_stat_gterr_lo; 2092 u32 tx_stat_gterr_hi; 2093 u32 tx_stat_gtbyt_lo; 2094 u32 tx_stat_gtbyt_hi; 2095 2096 u32 rx_stat_gr64_lo; 2097 u32 rx_stat_gr64_hi; 2098 u32 rx_stat_gr127_lo; 2099 u32 rx_stat_gr127_hi; 2100 u32 rx_stat_gr255_lo; 2101 u32 rx_stat_gr255_hi; 2102 u32 rx_stat_gr511_lo; 2103 u32 rx_stat_gr511_hi; 2104 u32 rx_stat_gr1023_lo; 2105 u32 rx_stat_gr1023_hi; 2106 u32 rx_stat_gr1518_lo; 2107 u32 rx_stat_gr1518_hi; 2108 u32 rx_stat_gr2047_lo; 2109 u32 rx_stat_gr2047_hi; 2110 u32 rx_stat_gr4095_lo; 2111 u32 rx_stat_gr4095_hi; 2112 u32 rx_stat_gr9216_lo; 2113 u32 rx_stat_gr9216_hi; 2114 u32 rx_stat_gr16383_lo; 2115 u32 rx_stat_gr16383_hi; 2116 u32 rx_stat_grmax_lo; 2117 u32 rx_stat_grmax_hi; 2118 u32 rx_stat_grpkt_lo; 2119 u32 rx_stat_grpkt_hi; 2120 u32 rx_stat_grfcs_lo; 2121 u32 rx_stat_grfcs_hi; 2122 u32 rx_stat_grmca_lo; 2123 u32 rx_stat_grmca_hi; 2124 u32 rx_stat_grbca_lo; 2125 u32 rx_stat_grbca_hi; 2126 u32 rx_stat_grxcf_lo; 2127 u32 rx_stat_grxcf_hi; 2128 u32 rx_stat_grxpf_lo; 2129 u32 rx_stat_grxpf_hi; 2130 u32 rx_stat_grxuo_lo; 2131 u32 rx_stat_grxuo_hi; 2132 u32 rx_stat_grjbr_lo; 2133 u32 rx_stat_grjbr_hi; 2134 u32 rx_stat_grovr_lo; 2135 u32 rx_stat_grovr_hi; 2136 u32 rx_stat_grflr_lo; 2137 u32 rx_stat_grflr_hi; 2138 u32 rx_stat_grmeg_lo; 2139 u32 rx_stat_grmeg_hi; 2140 u32 rx_stat_grmeb_lo; 2141 u32 rx_stat_grmeb_hi; 2142 u32 rx_stat_grbyt_lo; 2143 u32 rx_stat_grbyt_hi; 2144 u32 rx_stat_grund_lo; 2145 u32 rx_stat_grund_hi; 2146 u32 rx_stat_grfrg_lo; 2147 u32 rx_stat_grfrg_hi; 2148 u32 rx_stat_grerb_lo; 2149 u32 rx_stat_grerb_hi; 2150 u32 rx_stat_grfre_lo; 2151 u32 rx_stat_grfre_hi; 2152 u32 rx_stat_gripj_lo; 2153 u32 rx_stat_gripj_hi; 2154}; 2155 2156struct bmac2_stats { 2157 u32 tx_stat_gtpk_lo; /* gtpok */ 2158 u32 tx_stat_gtpk_hi; /* gtpok */ 2159 u32 tx_stat_gtxpf_lo; /* gtpf */ 2160 u32 tx_stat_gtxpf_hi; /* gtpf */ 2161 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */ 2162 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */ 2163 u32 tx_stat_gtfcs_lo; 2164 u32 tx_stat_gtfcs_hi; 2165 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */ 2166 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */ 2167 u32 tx_stat_gtmca_lo; 2168 u32 tx_stat_gtmca_hi; 2169 u32 tx_stat_gtbca_lo; 2170 u32 tx_stat_gtbca_hi; 2171 u32 tx_stat_gtovr_lo; 2172 u32 tx_stat_gtovr_hi; 2173 u32 tx_stat_gtfrg_lo; 2174 u32 tx_stat_gtfrg_hi; 2175 u32 tx_stat_gtpkt1_lo; /* gtpkt */ 2176 u32 tx_stat_gtpkt1_hi; /* gtpkt */ 2177 u32 tx_stat_gt64_lo; 2178 u32 tx_stat_gt64_hi; 2179 u32 tx_stat_gt127_lo; 2180 u32 tx_stat_gt127_hi; 2181 u32 tx_stat_gt255_lo; 2182 u32 tx_stat_gt255_hi; 2183 u32 tx_stat_gt511_lo; 2184 u32 tx_stat_gt511_hi; 2185 u32 tx_stat_gt1023_lo; 2186 u32 tx_stat_gt1023_hi; 2187 u32 tx_stat_gt1518_lo; 2188 u32 tx_stat_gt1518_hi; 2189 u32 tx_stat_gt2047_lo; 2190 u32 tx_stat_gt2047_hi; 2191 u32 tx_stat_gt4095_lo; 2192 u32 tx_stat_gt4095_hi; 2193 u32 tx_stat_gt9216_lo; 2194 u32 tx_stat_gt9216_hi; 2195 u32 tx_stat_gt16383_lo; 2196 u32 tx_stat_gt16383_hi; 2197 u32 tx_stat_gtmax_lo; 2198 u32 tx_stat_gtmax_hi; 2199 u32 tx_stat_gtufl_lo; 2200 u32 tx_stat_gtufl_hi; 2201 u32 tx_stat_gterr_lo; 2202 u32 tx_stat_gterr_hi; 2203 u32 tx_stat_gtbyt_lo; 2204 u32 tx_stat_gtbyt_hi; 2205 2206 u32 rx_stat_gr64_lo; 2207 u32 rx_stat_gr64_hi; 2208 u32 rx_stat_gr127_lo; 2209 u32 rx_stat_gr127_hi; 2210 u32 rx_stat_gr255_lo; 2211 u32 rx_stat_gr255_hi; 2212 u32 rx_stat_gr511_lo; 2213 u32 rx_stat_gr511_hi; 2214 u32 rx_stat_gr1023_lo; 2215 u32 rx_stat_gr1023_hi; 2216 u32 rx_stat_gr1518_lo; 2217 u32 rx_stat_gr1518_hi; 2218 u32 rx_stat_gr2047_lo; 2219 u32 rx_stat_gr2047_hi; 2220 u32 rx_stat_gr4095_lo; 2221 u32 rx_stat_gr4095_hi; 2222 u32 rx_stat_gr9216_lo; 2223 u32 rx_stat_gr9216_hi; 2224 u32 rx_stat_gr16383_lo; 2225 u32 rx_stat_gr16383_hi; 2226 u32 rx_stat_grmax_lo; 2227 u32 rx_stat_grmax_hi; 2228 u32 rx_stat_grpkt_lo; 2229 u32 rx_stat_grpkt_hi; 2230 u32 rx_stat_grfcs_lo; 2231 u32 rx_stat_grfcs_hi; 2232 u32 rx_stat_gruca_lo; 2233 u32 rx_stat_gruca_hi; 2234 u32 rx_stat_grmca_lo; 2235 u32 rx_stat_grmca_hi; 2236 u32 rx_stat_grbca_lo; 2237 u32 rx_stat_grbca_hi; 2238 u32 rx_stat_grxpf_lo; /* grpf */ 2239 u32 rx_stat_grxpf_hi; /* grpf */ 2240 u32 rx_stat_grpp_lo; 2241 u32 rx_stat_grpp_hi; 2242 u32 rx_stat_grxuo_lo; /* gruo */ 2243 u32 rx_stat_grxuo_hi; /* gruo */ 2244 u32 rx_stat_grjbr_lo; 2245 u32 rx_stat_grjbr_hi; 2246 u32 rx_stat_grovr_lo; 2247 u32 rx_stat_grovr_hi; 2248 u32 rx_stat_grxcf_lo; /* grcf */ 2249 u32 rx_stat_grxcf_hi; /* grcf */ 2250 u32 rx_stat_grflr_lo; 2251 u32 rx_stat_grflr_hi; 2252 u32 rx_stat_grpok_lo; 2253 u32 rx_stat_grpok_hi; 2254 u32 rx_stat_grmeg_lo; 2255 u32 rx_stat_grmeg_hi; 2256 u32 rx_stat_grmeb_lo; 2257 u32 rx_stat_grmeb_hi; 2258 u32 rx_stat_grbyt_lo; 2259 u32 rx_stat_grbyt_hi; 2260 u32 rx_stat_grund_lo; 2261 u32 rx_stat_grund_hi; 2262 u32 rx_stat_grfrg_lo; 2263 u32 rx_stat_grfrg_hi; 2264 u32 rx_stat_grerb_lo; /* grerrbyt */ 2265 u32 rx_stat_grerb_hi; /* grerrbyt */ 2266 u32 rx_stat_grfre_lo; /* grfrerr */ 2267 u32 rx_stat_grfre_hi; /* grfrerr */ 2268 u32 rx_stat_gripj_lo; 2269 u32 rx_stat_gripj_hi; 2270}; 2271 2272struct mstat_stats { 2273 struct { 2274 /* OTE MSTAT on E3 has a bug where this register's contents are 2275 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp 2276 */ 2277 u32 tx_gtxpok_lo; 2278 u32 tx_gtxpok_hi; 2279 u32 tx_gtxpf_lo; 2280 u32 tx_gtxpf_hi; 2281 u32 tx_gtxpp_lo; 2282 u32 tx_gtxpp_hi; 2283 u32 tx_gtfcs_lo; 2284 u32 tx_gtfcs_hi; 2285 u32 tx_gtuca_lo; 2286 u32 tx_gtuca_hi; 2287 u32 tx_gtmca_lo; 2288 u32 tx_gtmca_hi; 2289 u32 tx_gtgca_lo; 2290 u32 tx_gtgca_hi; 2291 u32 tx_gtpkt_lo; 2292 u32 tx_gtpkt_hi; 2293 u32 tx_gt64_lo; 2294 u32 tx_gt64_hi; 2295 u32 tx_gt127_lo; 2296 u32 tx_gt127_hi; 2297 u32 tx_gt255_lo; 2298 u32 tx_gt255_hi; 2299 u32 tx_gt511_lo; 2300 u32 tx_gt511_hi; 2301 u32 tx_gt1023_lo; 2302 u32 tx_gt1023_hi; 2303 u32 tx_gt1518_lo; 2304 u32 tx_gt1518_hi; 2305 u32 tx_gt2047_lo; 2306 u32 tx_gt2047_hi; 2307 u32 tx_gt4095_lo; 2308 u32 tx_gt4095_hi; 2309 u32 tx_gt9216_lo; 2310 u32 tx_gt9216_hi; 2311 u32 tx_gt16383_lo; 2312 u32 tx_gt16383_hi; 2313 u32 tx_gtufl_lo; 2314 u32 tx_gtufl_hi; 2315 u32 tx_gterr_lo; 2316 u32 tx_gterr_hi; 2317 u32 tx_gtbyt_lo; 2318 u32 tx_gtbyt_hi; 2319 u32 tx_collisions_lo; 2320 u32 tx_collisions_hi; 2321 u32 tx_singlecollision_lo; 2322 u32 tx_singlecollision_hi; 2323 u32 tx_multiplecollisions_lo; 2324 u32 tx_multiplecollisions_hi; 2325 u32 tx_deferred_lo; 2326 u32 tx_deferred_hi; 2327 u32 tx_excessivecollisions_lo; 2328 u32 tx_excessivecollisions_hi; 2329 u32 tx_latecollisions_lo; 2330 u32 tx_latecollisions_hi; 2331 } stats_tx; 2332 2333 struct { 2334 u32 rx_gr64_lo; 2335 u32 rx_gr64_hi; 2336 u32 rx_gr127_lo; 2337 u32 rx_gr127_hi; 2338 u32 rx_gr255_lo; 2339 u32 rx_gr255_hi; 2340 u32 rx_gr511_lo; 2341 u32 rx_gr511_hi; 2342 u32 rx_gr1023_lo; 2343 u32 rx_gr1023_hi; 2344 u32 rx_gr1518_lo; 2345 u32 rx_gr1518_hi; 2346 u32 rx_gr2047_lo; 2347 u32 rx_gr2047_hi; 2348 u32 rx_gr4095_lo; 2349 u32 rx_gr4095_hi; 2350 u32 rx_gr9216_lo; 2351 u32 rx_gr9216_hi; 2352 u32 rx_gr16383_lo; 2353 u32 rx_gr16383_hi; 2354 u32 rx_grpkt_lo; 2355 u32 rx_grpkt_hi; 2356 u32 rx_grfcs_lo; 2357 u32 rx_grfcs_hi; 2358 u32 rx_gruca_lo; 2359 u32 rx_gruca_hi; 2360 u32 rx_grmca_lo; 2361 u32 rx_grmca_hi; 2362 u32 rx_grbca_lo; 2363 u32 rx_grbca_hi; 2364 u32 rx_grxpf_lo; 2365 u32 rx_grxpf_hi; 2366 u32 rx_grxpp_lo; 2367 u32 rx_grxpp_hi; 2368 u32 rx_grxuo_lo; 2369 u32 rx_grxuo_hi; 2370 u32 rx_grovr_lo; 2371 u32 rx_grovr_hi; 2372 u32 rx_grxcf_lo; 2373 u32 rx_grxcf_hi; 2374 u32 rx_grflr_lo; 2375 u32 rx_grflr_hi; 2376 u32 rx_grpok_lo; 2377 u32 rx_grpok_hi; 2378 u32 rx_grbyt_lo; 2379 u32 rx_grbyt_hi; 2380 u32 rx_grund_lo; 2381 u32 rx_grund_hi; 2382 u32 rx_grfrg_lo; 2383 u32 rx_grfrg_hi; 2384 u32 rx_grerb_lo; 2385 u32 rx_grerb_hi; 2386 u32 rx_grfre_lo; 2387 u32 rx_grfre_hi; 2388 2389 u32 rx_alignmenterrors_lo; 2390 u32 rx_alignmenterrors_hi; 2391 u32 rx_falsecarrier_lo; 2392 u32 rx_falsecarrier_hi; 2393 u32 rx_llfcmsgcnt_lo; 2394 u32 rx_llfcmsgcnt_hi; 2395 } stats_rx; 2396}; 2397 2398union mac_stats { 2399 struct emac_stats emac_stats; 2400 struct bmac1_stats bmac1_stats; 2401 struct bmac2_stats bmac2_stats; 2402 struct mstat_stats mstat_stats; 2403}; 2404 2405 2406struct mac_stx { 2407 /* in_bad_octets */ 2408 u32 rx_stat_ifhcinbadoctets_hi; 2409 u32 rx_stat_ifhcinbadoctets_lo; 2410 2411 /* out_bad_octets */ 2412 u32 tx_stat_ifhcoutbadoctets_hi; 2413 u32 tx_stat_ifhcoutbadoctets_lo; 2414 2415 /* crc_receive_errors */ 2416 u32 rx_stat_dot3statsfcserrors_hi; 2417 u32 rx_stat_dot3statsfcserrors_lo; 2418 /* alignment_errors */ 2419 u32 rx_stat_dot3statsalignmenterrors_hi; 2420 u32 rx_stat_dot3statsalignmenterrors_lo; 2421 /* carrier_sense_errors */ 2422 u32 rx_stat_dot3statscarriersenseerrors_hi; 2423 u32 rx_stat_dot3statscarriersenseerrors_lo; 2424 /* false_carrier_detections */ 2425 u32 rx_stat_falsecarriererrors_hi; 2426 u32 rx_stat_falsecarriererrors_lo; 2427 2428 /* runt_packets_received */ 2429 u32 rx_stat_etherstatsundersizepkts_hi; 2430 u32 rx_stat_etherstatsundersizepkts_lo; 2431 /* jabber_packets_received */ 2432 u32 rx_stat_dot3statsframestoolong_hi; 2433 u32 rx_stat_dot3statsframestoolong_lo; 2434 2435 /* error_runt_packets_received */ 2436 u32 rx_stat_etherstatsfragments_hi; 2437 u32 rx_stat_etherstatsfragments_lo; 2438 /* error_jabber_packets_received */ 2439 u32 rx_stat_etherstatsjabbers_hi; 2440 u32 rx_stat_etherstatsjabbers_lo; 2441 2442 /* control_frames_received */ 2443 u32 rx_stat_maccontrolframesreceived_hi; 2444 u32 rx_stat_maccontrolframesreceived_lo; 2445 u32 rx_stat_mac_xpf_hi; 2446 u32 rx_stat_mac_xpf_lo; 2447 u32 rx_stat_mac_xcf_hi; 2448 u32 rx_stat_mac_xcf_lo; 2449 2450 /* xoff_state_entered */ 2451 u32 rx_stat_xoffstateentered_hi; 2452 u32 rx_stat_xoffstateentered_lo; 2453 /* pause_xon_frames_received */ 2454 u32 rx_stat_xonpauseframesreceived_hi; 2455 u32 rx_stat_xonpauseframesreceived_lo; 2456 /* pause_xoff_frames_received */ 2457 u32 rx_stat_xoffpauseframesreceived_hi; 2458 u32 rx_stat_xoffpauseframesreceived_lo; 2459 /* pause_xon_frames_transmitted */ 2460 u32 tx_stat_outxonsent_hi; 2461 u32 tx_stat_outxonsent_lo; 2462 /* pause_xoff_frames_transmitted */ 2463 u32 tx_stat_outxoffsent_hi; 2464 u32 tx_stat_outxoffsent_lo; 2465 /* flow_control_done */ 2466 u32 tx_stat_flowcontroldone_hi; 2467 u32 tx_stat_flowcontroldone_lo; 2468 2469 /* ether_stats_collisions */ 2470 u32 tx_stat_etherstatscollisions_hi; 2471 u32 tx_stat_etherstatscollisions_lo; 2472 /* single_collision_transmit_frames */ 2473 u32 tx_stat_dot3statssinglecollisionframes_hi; 2474 u32 tx_stat_dot3statssinglecollisionframes_lo; 2475 /* multiple_collision_transmit_frames */ 2476 u32 tx_stat_dot3statsmultiplecollisionframes_hi; 2477 u32 tx_stat_dot3statsmultiplecollisionframes_lo; 2478 /* deferred_transmissions */ 2479 u32 tx_stat_dot3statsdeferredtransmissions_hi; 2480 u32 tx_stat_dot3statsdeferredtransmissions_lo; 2481 /* excessive_collision_frames */ 2482 u32 tx_stat_dot3statsexcessivecollisions_hi; 2483 u32 tx_stat_dot3statsexcessivecollisions_lo; 2484 /* late_collision_frames */ 2485 u32 tx_stat_dot3statslatecollisions_hi; 2486 u32 tx_stat_dot3statslatecollisions_lo; 2487 2488 /* frames_transmitted_64_bytes */ 2489 u32 tx_stat_etherstatspkts64octets_hi; 2490 u32 tx_stat_etherstatspkts64octets_lo; 2491 /* frames_transmitted_65_127_bytes */ 2492 u32 tx_stat_etherstatspkts65octetsto127octets_hi; 2493 u32 tx_stat_etherstatspkts65octetsto127octets_lo; 2494 /* frames_transmitted_128_255_bytes */ 2495 u32 tx_stat_etherstatspkts128octetsto255octets_hi; 2496 u32 tx_stat_etherstatspkts128octetsto255octets_lo; 2497 /* frames_transmitted_256_511_bytes */ 2498 u32 tx_stat_etherstatspkts256octetsto511octets_hi; 2499 u32 tx_stat_etherstatspkts256octetsto511octets_lo; 2500 /* frames_transmitted_512_1023_bytes */ 2501 u32 tx_stat_etherstatspkts512octetsto1023octets_hi; 2502 u32 tx_stat_etherstatspkts512octetsto1023octets_lo; 2503 /* frames_transmitted_1024_1522_bytes */ 2504 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; 2505 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; 2506 /* frames_transmitted_1523_9022_bytes */ 2507 u32 tx_stat_etherstatspktsover1522octets_hi; 2508 u32 tx_stat_etherstatspktsover1522octets_lo; 2509 u32 tx_stat_mac_2047_hi; 2510 u32 tx_stat_mac_2047_lo; 2511 u32 tx_stat_mac_4095_hi; 2512 u32 tx_stat_mac_4095_lo; 2513 u32 tx_stat_mac_9216_hi; 2514 u32 tx_stat_mac_9216_lo; 2515 u32 tx_stat_mac_16383_hi; 2516 u32 tx_stat_mac_16383_lo; 2517 2518 /* internal_mac_transmit_errors */ 2519 u32 tx_stat_dot3statsinternalmactransmiterrors_hi; 2520 u32 tx_stat_dot3statsinternalmactransmiterrors_lo; 2521 2522 /* if_out_discards */ 2523 u32 tx_stat_mac_ufl_hi; 2524 u32 tx_stat_mac_ufl_lo; 2525}; 2526 2527 2528#define MAC_STX_IDX_MAX 2 2529 2530struct host_port_stats { 2531 u32 host_port_stats_counter; 2532 2533 struct mac_stx mac_stx[MAC_STX_IDX_MAX]; 2534 2535 u32 brb_drop_hi; 2536 u32 brb_drop_lo; 2537 2538 u32 not_used; /* obsolete */ 2539 u32 pfc_frames_tx_hi; 2540 u32 pfc_frames_tx_lo; 2541 u32 pfc_frames_rx_hi; 2542 u32 pfc_frames_rx_lo; 2543}; 2544 2545 2546struct host_func_stats { 2547 u32 host_func_stats_start; 2548 2549 u32 total_bytes_received_hi; 2550 u32 total_bytes_received_lo; 2551 2552 u32 total_bytes_transmitted_hi; 2553 u32 total_bytes_transmitted_lo; 2554 2555 u32 total_unicast_packets_received_hi; 2556 u32 total_unicast_packets_received_lo; 2557 2558 u32 total_multicast_packets_received_hi; 2559 u32 total_multicast_packets_received_lo; 2560 2561 u32 total_broadcast_packets_received_hi; 2562 u32 total_broadcast_packets_received_lo; 2563 2564 u32 total_unicast_packets_transmitted_hi; 2565 u32 total_unicast_packets_transmitted_lo; 2566 2567 u32 total_multicast_packets_transmitted_hi; 2568 u32 total_multicast_packets_transmitted_lo; 2569 2570 u32 total_broadcast_packets_transmitted_hi; 2571 u32 total_broadcast_packets_transmitted_lo; 2572 2573 u32 valid_bytes_received_hi; 2574 u32 valid_bytes_received_lo; 2575 2576 u32 host_func_stats_end; 2577}; 2578 2579/* VIC definitions */ 2580#define VICSTATST_UIF_INDEX 2 2581 2582/* current drv_info version */ 2583#define DRV_INFO_CUR_VER 1 2584 2585/* drv_info op codes supported */ 2586enum drv_info_opcode { 2587 ETH_STATS_OPCODE, 2588 FCOE_STATS_OPCODE, 2589 ISCSI_STATS_OPCODE 2590}; 2591 2592#define ETH_STAT_INFO_VERSION_LEN 12 2593/* Per PCI Function Ethernet Statistics required from the driver */ 2594struct eth_stats_info { 2595 /* Function's Driver Version. padded to 12 */ 2596 u8 version[ETH_STAT_INFO_VERSION_LEN]; 2597 /* Locally Admin Addr. BigEndian EIU48. Actual size is 6 bytes */ 2598 u8 mac_local[8]; 2599 u8 mac_add1[8]; /* Additional Programmed MAC Addr 1. */ 2600 u8 mac_add2[8]; /* Additional Programmed MAC Addr 2. */ 2601 u32 mtu_size; /* MTU Size. Note : Negotiated MTU */ 2602 u32 feature_flags; /* Feature_Flags. */ 2603#define FEATURE_ETH_CHKSUM_OFFLOAD_MASK 0x01 2604#define FEATURE_ETH_LSO_MASK 0x02 2605#define FEATURE_ETH_BOOTMODE_MASK 0x1C 2606#define FEATURE_ETH_BOOTMODE_SHIFT 2 2607#define FEATURE_ETH_BOOTMODE_NONE (0x0 << 2) 2608#define FEATURE_ETH_BOOTMODE_PXE (0x1 << 2) 2609#define FEATURE_ETH_BOOTMODE_ISCSI (0x2 << 2) 2610#define FEATURE_ETH_BOOTMODE_FCOE (0x3 << 2) 2611#define FEATURE_ETH_TOE_MASK 0x20 2612 u32 lso_max_size; /* LSO MaxOffloadSize. */ 2613 u32 lso_min_seg_cnt; /* LSO MinSegmentCount. */ 2614 /* Num Offloaded Connections TCP_IPv4. */ 2615 u32 ipv4_ofld_cnt; 2616 /* Num Offloaded Connections TCP_IPv6. */ 2617 u32 ipv6_ofld_cnt; 2618 u32 promiscuous_mode; /* Promiscuous Mode. non-zero true */ 2619 u32 txq_size; /* TX Descriptors Queue Size */ 2620 u32 rxq_size; /* RX Descriptors Queue Size */ 2621 /* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */ 2622 u32 txq_avg_depth; 2623 /* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */ 2624 u32 rxq_avg_depth; 2625 /* IOV_Offload. 0=none; 1=MultiQueue, 2=VEB 3= VEPA*/ 2626 u32 iov_offload; 2627 /* Number of NetQueue/VMQ Config'd. */ 2628 u32 netq_cnt; 2629 u32 vf_cnt; /* Num VF assigned to this PF. */ 2630}; 2631 2632/* Per PCI Function FCOE Statistics required from the driver */ 2633struct fcoe_stats_info { 2634 u8 version[12]; /* Function's Driver Version. */ 2635 u8 mac_local[8]; /* Locally Admin Addr. */ 2636 u8 mac_add1[8]; /* Additional Programmed MAC Addr 1. */ 2637 u8 mac_add2[8]; /* Additional Programmed MAC Addr 2. */ 2638 /* QoS Priority (per 802.1p). 0-7255 */ 2639 u32 qos_priority; 2640 u32 txq_size; /* FCoE TX Descriptors Queue Size. */ 2641 u32 rxq_size; /* FCoE RX Descriptors Queue Size. */ 2642 /* FCoE TX Descriptor Queue Avg Depth. */ 2643 u32 txq_avg_depth; 2644 /* FCoE RX Descriptors Queue Avg Depth. */ 2645 u32 rxq_avg_depth; 2646 u32 rx_frames_lo; /* FCoE RX Frames received. */ 2647 u32 rx_frames_hi; /* FCoE RX Frames received. */ 2648 u32 rx_bytes_lo; /* FCoE RX Bytes received. */ 2649 u32 rx_bytes_hi; /* FCoE RX Bytes received. */ 2650 u32 tx_frames_lo; /* FCoE TX Frames sent. */ 2651 u32 tx_frames_hi; /* FCoE TX Frames sent. */ 2652 u32 tx_bytes_lo; /* FCoE TX Bytes sent. */ 2653 u32 tx_bytes_hi; /* FCoE TX Bytes sent. */ 2654}; 2655 2656/* Per PCI Function iSCSI Statistics required from the driver*/ 2657struct iscsi_stats_info { 2658 u8 version[12]; /* Function's Driver Version. */ 2659 u8 mac_local[8]; /* Locally Admin iSCSI MAC Addr. */ 2660 u8 mac_add1[8]; /* Additional Programmed MAC Addr 1. */ 2661 /* QoS Priority (per 802.1p). 0-7255 */ 2662 u32 qos_priority; 2663 u8 initiator_name[64]; /* iSCSI Boot Initiator Node name. */ 2664 u8 ww_port_name[64]; /* iSCSI World wide port name */ 2665 u8 boot_target_name[64];/* iSCSI Boot Target Name. */ 2666 u8 boot_target_ip[16]; /* iSCSI Boot Target IP. */ 2667 u32 boot_target_portal; /* iSCSI Boot Target Portal. */ 2668 u8 boot_init_ip[16]; /* iSCSI Boot Initiator IP Address. */ 2669 u32 max_frame_size; /* Max Frame Size. bytes */ 2670 u32 txq_size; /* PDU TX Descriptors Queue Size. */ 2671 u32 rxq_size; /* PDU RX Descriptors Queue Size. */ 2672 u32 txq_avg_depth; /* PDU TX Descriptor Queue Avg Depth. */ 2673 u32 rxq_avg_depth; /* PDU RX Descriptors Queue Avg Depth. */ 2674 u32 rx_pdus_lo; /* iSCSI PDUs received. */ 2675 u32 rx_pdus_hi; /* iSCSI PDUs received. */ 2676 u32 rx_bytes_lo; /* iSCSI RX Bytes received. */ 2677 u32 rx_bytes_hi; /* iSCSI RX Bytes received. */ 2678 u32 tx_pdus_lo; /* iSCSI PDUs sent. */ 2679 u32 tx_pdus_hi; /* iSCSI PDUs sent. */ 2680 u32 tx_bytes_lo; /* iSCSI PDU TX Bytes sent. */ 2681 u32 tx_bytes_hi; /* iSCSI PDU TX Bytes sent. */ 2682 u32 pcp_prior_map_tbl; /* C-PCP to S-PCP Priority MapTable. 2683 * 9 nibbles, the position of each nibble 2684 * represents the C-PCP value, the value 2685 * of the nibble = S-PCP value. 2686 */ 2687}; 2688 2689union drv_info_to_mcp { 2690 struct eth_stats_info ether_stat; 2691 struct fcoe_stats_info fcoe_stat; 2692 struct iscsi_stats_info iscsi_stat; 2693}; 2694#define BCM_5710_FW_MAJOR_VERSION 7 2695#define BCM_5710_FW_MINOR_VERSION 2 2696#define BCM_5710_FW_REVISION_VERSION 16 2697#define BCM_5710_FW_ENGINEERING_VERSION 0 2698#define BCM_5710_FW_COMPILE_FLAGS 1 2699 2700 2701/* 2702 * attention bits 2703 */ 2704struct atten_sp_status_block { 2705 __le32 attn_bits; 2706 __le32 attn_bits_ack; 2707 u8 status_block_id; 2708 u8 reserved0; 2709 __le16 attn_bits_index; 2710 __le32 reserved1; 2711}; 2712 2713 2714/* 2715 * The eth aggregative context of Cstorm 2716 */ 2717struct cstorm_eth_ag_context { 2718 u32 __reserved0[10]; 2719}; 2720 2721 2722/* 2723 * dmae command structure 2724 */ 2725struct dmae_command { 2726 u32 opcode; 2727#define DMAE_COMMAND_SRC (0x1<<0) 2728#define DMAE_COMMAND_SRC_SHIFT 0 2729#define DMAE_COMMAND_DST (0x3<<1) 2730#define DMAE_COMMAND_DST_SHIFT 1 2731#define DMAE_COMMAND_C_DST (0x1<<3) 2732#define DMAE_COMMAND_C_DST_SHIFT 3 2733#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) 2734#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 2735#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) 2736#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 2737#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) 2738#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 2739#define DMAE_COMMAND_ENDIANITY (0x3<<9) 2740#define DMAE_COMMAND_ENDIANITY_SHIFT 9 2741#define DMAE_COMMAND_PORT (0x1<<11) 2742#define DMAE_COMMAND_PORT_SHIFT 11 2743#define DMAE_COMMAND_CRC_RESET (0x1<<12) 2744#define DMAE_COMMAND_CRC_RESET_SHIFT 12 2745#define DMAE_COMMAND_SRC_RESET (0x1<<13) 2746#define DMAE_COMMAND_SRC_RESET_SHIFT 13 2747#define DMAE_COMMAND_DST_RESET (0x1<<14) 2748#define DMAE_COMMAND_DST_RESET_SHIFT 14 2749#define DMAE_COMMAND_E1HVN (0x3<<15) 2750#define DMAE_COMMAND_E1HVN_SHIFT 15 2751#define DMAE_COMMAND_DST_VN (0x3<<17) 2752#define DMAE_COMMAND_DST_VN_SHIFT 17 2753#define DMAE_COMMAND_C_FUNC (0x1<<19) 2754#define DMAE_COMMAND_C_FUNC_SHIFT 19 2755#define DMAE_COMMAND_ERR_POLICY (0x3<<20) 2756#define DMAE_COMMAND_ERR_POLICY_SHIFT 20 2757#define DMAE_COMMAND_RESERVED0 (0x3FF<<22) 2758#define DMAE_COMMAND_RESERVED0_SHIFT 22 2759 u32 src_addr_lo; 2760 u32 src_addr_hi; 2761 u32 dst_addr_lo; 2762 u32 dst_addr_hi; 2763#if defined(__BIG_ENDIAN) 2764 u16 opcode_iov; 2765#define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2766#define DMAE_COMMAND_SRC_VFID_SHIFT 0 2767#define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2768#define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2769#define DMAE_COMMAND_RESERVED1 (0x1<<7) 2770#define DMAE_COMMAND_RESERVED1_SHIFT 7 2771#define DMAE_COMMAND_DST_VFID (0x3F<<8) 2772#define DMAE_COMMAND_DST_VFID_SHIFT 8 2773#define DMAE_COMMAND_DST_VFPF (0x1<<14) 2774#define DMAE_COMMAND_DST_VFPF_SHIFT 14 2775#define DMAE_COMMAND_RESERVED2 (0x1<<15) 2776#define DMAE_COMMAND_RESERVED2_SHIFT 15 2777 u16 len; 2778#elif defined(__LITTLE_ENDIAN) 2779 u16 len; 2780 u16 opcode_iov; 2781#define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2782#define DMAE_COMMAND_SRC_VFID_SHIFT 0 2783#define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2784#define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2785#define DMAE_COMMAND_RESERVED1 (0x1<<7) 2786#define DMAE_COMMAND_RESERVED1_SHIFT 7 2787#define DMAE_COMMAND_DST_VFID (0x3F<<8) 2788#define DMAE_COMMAND_DST_VFID_SHIFT 8 2789#define DMAE_COMMAND_DST_VFPF (0x1<<14) 2790#define DMAE_COMMAND_DST_VFPF_SHIFT 14 2791#define DMAE_COMMAND_RESERVED2 (0x1<<15) 2792#define DMAE_COMMAND_RESERVED2_SHIFT 15 2793#endif 2794 u32 comp_addr_lo; 2795 u32 comp_addr_hi; 2796 u32 comp_val; 2797 u32 crc32; 2798 u32 crc32_c; 2799#if defined(__BIG_ENDIAN) 2800 u16 crc16_c; 2801 u16 crc16; 2802#elif defined(__LITTLE_ENDIAN) 2803 u16 crc16; 2804 u16 crc16_c; 2805#endif 2806#if defined(__BIG_ENDIAN) 2807 u16 reserved3; 2808 u16 crc_t10; 2809#elif defined(__LITTLE_ENDIAN) 2810 u16 crc_t10; 2811 u16 reserved3; 2812#endif 2813#if defined(__BIG_ENDIAN) 2814 u16 xsum8; 2815 u16 xsum16; 2816#elif defined(__LITTLE_ENDIAN) 2817 u16 xsum16; 2818 u16 xsum8; 2819#endif 2820}; 2821 2822 2823/* 2824 * common data for all protocols 2825 */ 2826struct doorbell_hdr { 2827 u8 header; 2828#define DOORBELL_HDR_RX (0x1<<0) 2829#define DOORBELL_HDR_RX_SHIFT 0 2830#define DOORBELL_HDR_DB_TYPE (0x1<<1) 2831#define DOORBELL_HDR_DB_TYPE_SHIFT 1 2832#define DOORBELL_HDR_DPM_SIZE (0x3<<2) 2833#define DOORBELL_HDR_DPM_SIZE_SHIFT 2 2834#define DOORBELL_HDR_CONN_TYPE (0xF<<4) 2835#define DOORBELL_HDR_CONN_TYPE_SHIFT 4 2836}; 2837 2838/* 2839 * Ethernet doorbell 2840 */ 2841struct eth_tx_doorbell { 2842#if defined(__BIG_ENDIAN) 2843 u16 npackets; 2844 u8 params; 2845#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 2846#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 2847#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 2848#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 2849#define ETH_TX_DOORBELL_SPARE (0x1<<7) 2850#define ETH_TX_DOORBELL_SPARE_SHIFT 7 2851 struct doorbell_hdr hdr; 2852#elif defined(__LITTLE_ENDIAN) 2853 struct doorbell_hdr hdr; 2854 u8 params; 2855#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 2856#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 2857#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 2858#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 2859#define ETH_TX_DOORBELL_SPARE (0x1<<7) 2860#define ETH_TX_DOORBELL_SPARE_SHIFT 7 2861 u16 npackets; 2862#endif 2863}; 2864 2865 2866/* 2867 * 3 lines. status block 2868 */ 2869struct hc_status_block_e1x { 2870 __le16 index_values[HC_SB_MAX_INDICES_E1X]; 2871 __le16 running_index[HC_SB_MAX_SM]; 2872 __le32 rsrv[11]; 2873}; 2874 2875/* 2876 * host status block 2877 */ 2878struct host_hc_status_block_e1x { 2879 struct hc_status_block_e1x sb; 2880}; 2881 2882 2883/* 2884 * 3 lines. status block 2885 */ 2886struct hc_status_block_e2 { 2887 __le16 index_values[HC_SB_MAX_INDICES_E2]; 2888 __le16 running_index[HC_SB_MAX_SM]; 2889 __le32 reserved[11]; 2890}; 2891 2892/* 2893 * host status block 2894 */ 2895struct host_hc_status_block_e2 { 2896 struct hc_status_block_e2 sb; 2897}; 2898 2899 2900/* 2901 * 5 lines. slow-path status block 2902 */ 2903struct hc_sp_status_block { 2904 __le16 index_values[HC_SP_SB_MAX_INDICES]; 2905 __le16 running_index; 2906 __le16 rsrv; 2907 u32 rsrv1; 2908}; 2909 2910/* 2911 * host status block 2912 */ 2913struct host_sp_status_block { 2914 struct atten_sp_status_block atten_status_block; 2915 struct hc_sp_status_block sp_sb; 2916}; 2917 2918 2919/* 2920 * IGU driver acknowledgment register 2921 */ 2922struct igu_ack_register { 2923#if defined(__BIG_ENDIAN) 2924 u16 sb_id_and_flags; 2925#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 2926#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 2927#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 2928#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 2929#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 2930#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 2931#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 2932#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 2933#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 2934#define IGU_ACK_REGISTER_RESERVED_SHIFT 11 2935 u16 status_block_index; 2936#elif defined(__LITTLE_ENDIAN) 2937 u16 status_block_index; 2938 u16 sb_id_and_flags; 2939#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 2940#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 2941#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 2942#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 2943#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 2944#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 2945#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 2946#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 2947#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 2948#define IGU_ACK_REGISTER_RESERVED_SHIFT 11 2949#endif 2950}; 2951 2952 2953/* 2954 * IGU driver acknowledgement register 2955 */ 2956struct igu_backward_compatible { 2957 u32 sb_id_and_flags; 2958#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) 2959#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 2960#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) 2961#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 2962#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) 2963#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 2964#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) 2965#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 2966#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) 2967#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 2968#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) 2969#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 2970 u32 reserved_2; 2971}; 2972 2973 2974/* 2975 * IGU driver acknowledgement register 2976 */ 2977struct igu_regular { 2978 u32 sb_id_and_flags; 2979#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) 2980#define IGU_REGULAR_SB_INDEX_SHIFT 0 2981#define IGU_REGULAR_RESERVED0 (0x1<<20) 2982#define IGU_REGULAR_RESERVED0_SHIFT 20 2983#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) 2984#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 2985#define IGU_REGULAR_BUPDATE (0x1<<24) 2986#define IGU_REGULAR_BUPDATE_SHIFT 24 2987#define IGU_REGULAR_ENABLE_INT (0x3<<25) 2988#define IGU_REGULAR_ENABLE_INT_SHIFT 25 2989#define IGU_REGULAR_RESERVED_1 (0x1<<27) 2990#define IGU_REGULAR_RESERVED_1_SHIFT 27 2991#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) 2992#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 2993#define IGU_REGULAR_CLEANUP_SET (0x1<<30) 2994#define IGU_REGULAR_CLEANUP_SET_SHIFT 30 2995#define IGU_REGULAR_BCLEANUP (0x1<<31) 2996#define IGU_REGULAR_BCLEANUP_SHIFT 31 2997 u32 reserved_2; 2998}; 2999 3000/* 3001 * IGU driver acknowledgement register 3002 */ 3003union igu_consprod_reg { 3004 struct igu_regular regular; 3005 struct igu_backward_compatible backward_compatible; 3006}; 3007 3008 3009/* 3010 * Igu control commands 3011 */ 3012enum igu_ctrl_cmd { 3013 IGU_CTRL_CMD_TYPE_RD, 3014 IGU_CTRL_CMD_TYPE_WR, 3015 MAX_IGU_CTRL_CMD 3016}; 3017 3018 3019/* 3020 * Control register for the IGU command register 3021 */ 3022struct igu_ctrl_reg { 3023 u32 ctrl_data; 3024#define IGU_CTRL_REG_ADDRESS (0xFFF<<0) 3025#define IGU_CTRL_REG_ADDRESS_SHIFT 0 3026#define IGU_CTRL_REG_FID (0x7F<<12) 3027#define IGU_CTRL_REG_FID_SHIFT 12 3028#define IGU_CTRL_REG_RESERVED (0x1<<19) 3029#define IGU_CTRL_REG_RESERVED_SHIFT 19 3030#define IGU_CTRL_REG_TYPE (0x1<<20) 3031#define IGU_CTRL_REG_TYPE_SHIFT 20 3032#define IGU_CTRL_REG_UNUSED (0x7FF<<21) 3033#define IGU_CTRL_REG_UNUSED_SHIFT 21 3034}; 3035 3036 3037/* 3038 * Igu interrupt command 3039 */ 3040enum igu_int_cmd { 3041 IGU_INT_ENABLE, 3042 IGU_INT_DISABLE, 3043 IGU_INT_NOP, 3044 IGU_INT_NOP2, 3045 MAX_IGU_INT_CMD 3046}; 3047 3048 3049/* 3050 * Igu segments 3051 */ 3052enum igu_seg_access { 3053 IGU_SEG_ACCESS_NORM, 3054 IGU_SEG_ACCESS_DEF, 3055 IGU_SEG_ACCESS_ATTN, 3056 MAX_IGU_SEG_ACCESS 3057}; 3058 3059 3060/* 3061 * Parser parsing flags field 3062 */ 3063struct parsing_flags { 3064 __le16 flags; 3065#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) 3066#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 3067#define PARSING_FLAGS_VLAN (0x1<<1) 3068#define PARSING_FLAGS_VLAN_SHIFT 1 3069#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) 3070#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 3071#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) 3072#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 3073#define PARSING_FLAGS_IP_OPTIONS (0x1<<5) 3074#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 3075#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) 3076#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 3077#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) 3078#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 3079#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) 3080#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 3081#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) 3082#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 3083#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) 3084#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 3085#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) 3086#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 3087#define PARSING_FLAGS_LLC_SNAP (0x1<<13) 3088#define PARSING_FLAGS_LLC_SNAP_SHIFT 13 3089#define PARSING_FLAGS_RESERVED0 (0x3<<14) 3090#define PARSING_FLAGS_RESERVED0_SHIFT 14 3091}; 3092 3093 3094/* 3095 * Parsing flags for TCP ACK type 3096 */ 3097enum prs_flags_ack_type { 3098 PRS_FLAG_PUREACK_PIGGY, 3099 PRS_FLAG_PUREACK_PURE, 3100 MAX_PRS_FLAGS_ACK_TYPE 3101}; 3102 3103 3104/* 3105 * Parsing flags for Ethernet address type 3106 */ 3107enum prs_flags_eth_addr_type { 3108 PRS_FLAG_ETHTYPE_NON_UNICAST, 3109 PRS_FLAG_ETHTYPE_UNICAST, 3110 MAX_PRS_FLAGS_ETH_ADDR_TYPE 3111}; 3112 3113 3114/* 3115 * Parsing flags for over-ethernet protocol 3116 */ 3117enum prs_flags_over_eth { 3118 PRS_FLAG_OVERETH_UNKNOWN, 3119 PRS_FLAG_OVERETH_IPV4, 3120 PRS_FLAG_OVERETH_IPV6, 3121 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, 3122 MAX_PRS_FLAGS_OVER_ETH 3123}; 3124 3125 3126/* 3127 * Parsing flags for over-IP protocol 3128 */ 3129enum prs_flags_over_ip { 3130 PRS_FLAG_OVERIP_UNKNOWN, 3131 PRS_FLAG_OVERIP_TCP, 3132 PRS_FLAG_OVERIP_UDP, 3133 MAX_PRS_FLAGS_OVER_IP 3134}; 3135 3136 3137/* 3138 * SDM operation gen command (generate aggregative interrupt) 3139 */ 3140struct sdm_op_gen { 3141 __le32 command; 3142#define SDM_OP_GEN_COMP_PARAM (0x1F<<0) 3143#define SDM_OP_GEN_COMP_PARAM_SHIFT 0 3144#define SDM_OP_GEN_COMP_TYPE (0x7<<5) 3145#define SDM_OP_GEN_COMP_TYPE_SHIFT 5 3146#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) 3147#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 3148#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) 3149#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 3150#define SDM_OP_GEN_RESERVED (0x7FFF<<17) 3151#define SDM_OP_GEN_RESERVED_SHIFT 17 3152}; 3153 3154 3155/* 3156 * Timers connection context 3157 */ 3158struct timers_block_context { 3159 u32 __reserved_0; 3160 u32 __reserved_1; 3161 u32 __reserved_2; 3162 u32 flags; 3163#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) 3164#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 3165#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) 3166#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 3167#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) 3168#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 3169}; 3170 3171 3172/* 3173 * The eth aggregative context of Tstorm 3174 */ 3175struct tstorm_eth_ag_context { 3176 u32 __reserved0[14]; 3177}; 3178 3179 3180/* 3181 * The eth aggregative context of Ustorm 3182 */ 3183struct ustorm_eth_ag_context { 3184 u32 __reserved0; 3185#if defined(__BIG_ENDIAN) 3186 u8 cdu_usage; 3187 u8 __reserved2; 3188 u16 __reserved1; 3189#elif defined(__LITTLE_ENDIAN) 3190 u16 __reserved1; 3191 u8 __reserved2; 3192 u8 cdu_usage; 3193#endif 3194 u32 __reserved3[6]; 3195}; 3196 3197 3198/* 3199 * The eth aggregative context of Xstorm 3200 */ 3201struct xstorm_eth_ag_context { 3202 u32 reserved0; 3203#if defined(__BIG_ENDIAN) 3204 u8 cdu_reserved; 3205 u8 reserved2; 3206 u16 reserved1; 3207#elif defined(__LITTLE_ENDIAN) 3208 u16 reserved1; 3209 u8 reserved2; 3210 u8 cdu_reserved; 3211#endif 3212 u32 reserved3[30]; 3213}; 3214 3215 3216/* 3217 * doorbell message sent to the chip 3218 */ 3219struct doorbell { 3220#if defined(__BIG_ENDIAN) 3221 u16 zero_fill2; 3222 u8 zero_fill1; 3223 struct doorbell_hdr header; 3224#elif defined(__LITTLE_ENDIAN) 3225 struct doorbell_hdr header; 3226 u8 zero_fill1; 3227 u16 zero_fill2; 3228#endif 3229}; 3230 3231 3232/* 3233 * doorbell message sent to the chip 3234 */ 3235struct doorbell_set_prod { 3236#if defined(__BIG_ENDIAN) 3237 u16 prod; 3238 u8 zero_fill1; 3239 struct doorbell_hdr header; 3240#elif defined(__LITTLE_ENDIAN) 3241 struct doorbell_hdr header; 3242 u8 zero_fill1; 3243 u16 prod; 3244#endif 3245}; 3246 3247 3248struct regpair { 3249 __le32 lo; 3250 __le32 hi; 3251}; 3252 3253 3254/* 3255 * Classify rule opcodes in E2/E3 3256 */ 3257enum classify_rule { 3258 CLASSIFY_RULE_OPCODE_MAC, 3259 CLASSIFY_RULE_OPCODE_VLAN, 3260 CLASSIFY_RULE_OPCODE_PAIR, 3261 MAX_CLASSIFY_RULE 3262}; 3263 3264 3265/* 3266 * Classify rule types in E2/E3 3267 */ 3268enum classify_rule_action_type { 3269 CLASSIFY_RULE_REMOVE, 3270 CLASSIFY_RULE_ADD, 3271 MAX_CLASSIFY_RULE_ACTION_TYPE 3272}; 3273 3274 3275/* 3276 * client init ramrod data 3277 */ 3278struct client_init_general_data { 3279 u8 client_id; 3280 u8 statistics_counter_id; 3281 u8 statistics_en_flg; 3282 u8 is_fcoe_flg; 3283 u8 activate_flg; 3284 u8 sp_client_id; 3285 __le16 mtu; 3286 u8 statistics_zero_flg; 3287 u8 func_id; 3288 u8 cos; 3289 u8 traffic_type; 3290 u32 reserved0; 3291}; 3292 3293 3294/* 3295 * client init rx data 3296 */ 3297struct client_init_rx_data { 3298 u8 tpa_en; 3299#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) 3300#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 3301#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) 3302#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 3303#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) 3304#define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 3305#define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) 3306#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3 3307 u8 vmqueue_mode_en_flg; 3308 u8 extra_data_over_sgl_en_flg; 3309 u8 cache_line_alignment_log_size; 3310 u8 enable_dynamic_hc; 3311 u8 max_sges_for_packet; 3312 u8 client_qzone_id; 3313 u8 drop_ip_cs_err_flg; 3314 u8 drop_tcp_cs_err_flg; 3315 u8 drop_ttl0_flg; 3316 u8 drop_udp_cs_err_flg; 3317 u8 inner_vlan_removal_enable_flg; 3318 u8 outer_vlan_removal_enable_flg; 3319 u8 status_block_id; 3320 u8 rx_sb_index_number; 3321 u8 dont_verify_rings_pause_thr_flg; 3322 u8 max_tpa_queues; 3323 u8 silent_vlan_removal_flg; 3324 __le16 max_bytes_on_bd; 3325 __le16 sge_buff_size; 3326 u8 approx_mcast_engine_id; 3327 u8 rss_engine_id; 3328 struct regpair bd_page_base; 3329 struct regpair sge_page_base; 3330 struct regpair cqe_page_base; 3331 u8 is_leading_rss; 3332 u8 is_approx_mcast; 3333 __le16 max_agg_size; 3334 __le16 state; 3335#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) 3336#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 3337#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) 3338#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 3339#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3340#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3341#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) 3342#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 3343#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) 3344#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 3345#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) 3346#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 3347#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) 3348#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 3349#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) 3350#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 3351 __le16 cqe_pause_thr_low; 3352 __le16 cqe_pause_thr_high; 3353 __le16 bd_pause_thr_low; 3354 __le16 bd_pause_thr_high; 3355 __le16 sge_pause_thr_low; 3356 __le16 sge_pause_thr_high; 3357 __le16 rx_cos_mask; 3358 __le16 silent_vlan_value; 3359 __le16 silent_vlan_mask; 3360 __le32 reserved6[2]; 3361}; 3362 3363/* 3364 * client init tx data 3365 */ 3366struct client_init_tx_data { 3367 u8 enforce_security_flg; 3368 u8 tx_status_block_id; 3369 u8 tx_sb_index_number; 3370 u8 tss_leading_client_id; 3371 u8 tx_switching_flg; 3372 u8 anti_spoofing_flg; 3373 __le16 default_vlan; 3374 struct regpair tx_bd_page_base; 3375 __le16 state; 3376#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) 3377#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 3378#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) 3379#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 3380#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) 3381#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 3382#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) 3383#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 3384#define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4) 3385#define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4 3386 u8 default_vlan_flg; 3387 u8 reserved2; 3388 __le32 reserved3; 3389}; 3390 3391/* 3392 * client init ramrod data 3393 */ 3394struct client_init_ramrod_data { 3395 struct client_init_general_data general; 3396 struct client_init_rx_data rx; 3397 struct client_init_tx_data tx; 3398}; 3399 3400 3401/* 3402 * client update ramrod data 3403 */ 3404struct client_update_ramrod_data { 3405 u8 client_id; 3406 u8 func_id; 3407 u8 inner_vlan_removal_enable_flg; 3408 u8 inner_vlan_removal_change_flg; 3409 u8 outer_vlan_removal_enable_flg; 3410 u8 outer_vlan_removal_change_flg; 3411 u8 anti_spoofing_enable_flg; 3412 u8 anti_spoofing_change_flg; 3413 u8 activate_flg; 3414 u8 activate_change_flg; 3415 __le16 default_vlan; 3416 u8 default_vlan_enable_flg; 3417 u8 default_vlan_change_flg; 3418 __le16 silent_vlan_value; 3419 __le16 silent_vlan_mask; 3420 u8 silent_vlan_removal_flg; 3421 u8 silent_vlan_change_flg; 3422 __le32 echo; 3423}; 3424 3425 3426/* 3427 * The eth storm context of Cstorm 3428 */ 3429struct cstorm_eth_st_context { 3430 u32 __reserved0[4]; 3431}; 3432 3433 3434struct double_regpair { 3435 u32 regpair0_lo; 3436 u32 regpair0_hi; 3437 u32 regpair1_lo; 3438 u32 regpair1_hi; 3439}; 3440 3441 3442/* 3443 * Ethernet address typesm used in ethernet tx BDs 3444 */ 3445enum eth_addr_type { 3446 UNKNOWN_ADDRESS, 3447 UNICAST_ADDRESS, 3448 MULTICAST_ADDRESS, 3449 BROADCAST_ADDRESS, 3450 MAX_ETH_ADDR_TYPE 3451}; 3452 3453 3454/* 3455 * 3456 */ 3457struct eth_classify_cmd_header { 3458 u8 cmd_general_data; 3459#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) 3460#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 3461#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) 3462#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 3463#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) 3464#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 3465#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) 3466#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 3467#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) 3468#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 3469 u8 func_id; 3470 u8 client_id; 3471 u8 reserved1; 3472}; 3473 3474 3475/* 3476 * header for eth classification config ramrod 3477 */ 3478struct eth_classify_header { 3479 u8 rule_cnt; 3480 u8 reserved0; 3481 __le16 reserved1; 3482 __le32 echo; 3483}; 3484 3485 3486/* 3487 * Command for adding/removing a MAC classification rule 3488 */ 3489struct eth_classify_mac_cmd { 3490 struct eth_classify_cmd_header header; 3491 __le32 reserved0; 3492 __le16 mac_lsb; 3493 __le16 mac_mid; 3494 __le16 mac_msb; 3495 __le16 reserved1; 3496}; 3497 3498 3499/* 3500 * Command for adding/removing a MAC-VLAN pair classification rule 3501 */ 3502struct eth_classify_pair_cmd { 3503 struct eth_classify_cmd_header header; 3504 __le32 reserved0; 3505 __le16 mac_lsb; 3506 __le16 mac_mid; 3507 __le16 mac_msb; 3508 __le16 vlan; 3509}; 3510 3511 3512/* 3513 * Command for adding/removing a VLAN classification rule 3514 */ 3515struct eth_classify_vlan_cmd { 3516 struct eth_classify_cmd_header header; 3517 __le32 reserved0; 3518 __le32 reserved1; 3519 __le16 reserved2; 3520 __le16 vlan; 3521}; 3522 3523/* 3524 * union for eth classification rule 3525 */ 3526union eth_classify_rule_cmd { 3527 struct eth_classify_mac_cmd mac; 3528 struct eth_classify_vlan_cmd vlan; 3529 struct eth_classify_pair_cmd pair; 3530}; 3531 3532/* 3533 * parameters for eth classification configuration ramrod 3534 */ 3535struct eth_classify_rules_ramrod_data { 3536 struct eth_classify_header header; 3537 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3538}; 3539 3540 3541/* 3542 * The data contain client ID need to the ramrod 3543 */ 3544struct eth_common_ramrod_data { 3545 __le32 client_id; 3546 __le32 reserved1; 3547}; 3548 3549 3550/* 3551 * The eth storm context of Ustorm 3552 */ 3553struct ustorm_eth_st_context { 3554 u32 reserved0[52]; 3555}; 3556 3557/* 3558 * The eth storm context of Tstorm 3559 */ 3560struct tstorm_eth_st_context { 3561 u32 __reserved0[28]; 3562}; 3563 3564/* 3565 * The eth storm context of Xstorm 3566 */ 3567struct xstorm_eth_st_context { 3568 u32 reserved0[60]; 3569}; 3570 3571/* 3572 * Ethernet connection context 3573 */ 3574struct eth_context { 3575 struct ustorm_eth_st_context ustorm_st_context; 3576 struct tstorm_eth_st_context tstorm_st_context; 3577 struct xstorm_eth_ag_context xstorm_ag_context; 3578 struct tstorm_eth_ag_context tstorm_ag_context; 3579 struct cstorm_eth_ag_context cstorm_ag_context; 3580 struct ustorm_eth_ag_context ustorm_ag_context; 3581 struct timers_block_context timers_context; 3582 struct xstorm_eth_st_context xstorm_st_context; 3583 struct cstorm_eth_st_context cstorm_st_context; 3584}; 3585 3586 3587/* 3588 * union for sgl and raw data. 3589 */ 3590union eth_sgl_or_raw_data { 3591 __le16 sgl[8]; 3592 u32 raw_data[4]; 3593}; 3594 3595/* 3596 * eth FP end aggregation CQE parameters struct 3597 */ 3598struct eth_end_agg_rx_cqe { 3599 u8 type_error_flags; 3600#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) 3601#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 3602#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) 3603#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 3604#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) 3605#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 3606 u8 reserved1; 3607 u8 queue_index; 3608 u8 reserved2; 3609 __le32 timestamp_delta; 3610 __le16 num_of_coalesced_segs; 3611 __le16 pkt_len; 3612 u8 pure_ack_count; 3613 u8 reserved3; 3614 __le16 reserved4; 3615 union eth_sgl_or_raw_data sgl_or_raw_data; 3616 __le32 reserved5[8]; 3617}; 3618 3619 3620/* 3621 * regular eth FP CQE parameters struct 3622 */ 3623struct eth_fast_path_rx_cqe { 3624 u8 type_error_flags; 3625#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) 3626#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 3627#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) 3628#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 3629#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) 3630#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 3631#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) 3632#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 3633#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) 3634#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 3635#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) 3636#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6 3637 u8 status_flags; 3638#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) 3639#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 3640#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) 3641#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 3642#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) 3643#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 3644#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) 3645#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 3646#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) 3647#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 3648#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) 3649#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 3650 u8 queue_index; 3651 u8 placement_offset; 3652 __le32 rss_hash_result; 3653 __le16 vlan_tag; 3654 __le16 pkt_len_or_gro_seg_len; 3655 __le16 len_on_bd; 3656 struct parsing_flags pars_flags; 3657 union eth_sgl_or_raw_data sgl_or_raw_data; 3658 __le32 reserved1[8]; 3659}; 3660 3661 3662/* 3663 * Command for setting classification flags for a client 3664 */ 3665struct eth_filter_rules_cmd { 3666 u8 cmd_general_data; 3667#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) 3668#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 3669#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) 3670#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 3671#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) 3672#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 3673 u8 func_id; 3674 u8 client_id; 3675 u8 reserved1; 3676 __le16 state; 3677#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) 3678#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 3679#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) 3680#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 3681#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3682#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3683#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) 3684#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 3685#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) 3686#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 3687#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) 3688#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 3689#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) 3690#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 3691#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) 3692#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 3693 __le16 reserved3; 3694 struct regpair reserved4; 3695}; 3696 3697 3698/* 3699 * parameters for eth classification filters ramrod 3700 */ 3701struct eth_filter_rules_ramrod_data { 3702 struct eth_classify_header header; 3703 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; 3704}; 3705 3706 3707/* 3708 * parameters for eth classification configuration ramrod 3709 */ 3710struct eth_general_rules_ramrod_data { 3711 struct eth_classify_header header; 3712 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3713}; 3714 3715 3716/* 3717 * The data for Halt ramrod 3718 */ 3719struct eth_halt_ramrod_data { 3720 __le32 client_id; 3721 __le32 reserved0; 3722}; 3723 3724 3725/* 3726 * Command for setting multicast classification for a client 3727 */ 3728struct eth_multicast_rules_cmd { 3729 u8 cmd_general_data; 3730#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) 3731#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 3732#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) 3733#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 3734#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) 3735#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 3736#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) 3737#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 3738 u8 func_id; 3739 u8 bin_id; 3740 u8 engine_id; 3741 __le32 reserved2; 3742 struct regpair reserved3; 3743}; 3744 3745 3746/* 3747 * parameters for multicast classification ramrod 3748 */ 3749struct eth_multicast_rules_ramrod_data { 3750 struct eth_classify_header header; 3751 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; 3752}; 3753 3754 3755/* 3756 * Place holder for ramrods protocol specific data 3757 */ 3758struct ramrod_data { 3759 __le32 data_lo; 3760 __le32 data_hi; 3761}; 3762 3763/* 3764 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) 3765 */ 3766union eth_ramrod_data { 3767 struct ramrod_data general; 3768}; 3769 3770 3771/* 3772 * RSS toeplitz hash type, as reported in CQE 3773 */ 3774enum eth_rss_hash_type { 3775 DEFAULT_HASH_TYPE, 3776 IPV4_HASH_TYPE, 3777 TCP_IPV4_HASH_TYPE, 3778 IPV6_HASH_TYPE, 3779 TCP_IPV6_HASH_TYPE, 3780 VLAN_PRI_HASH_TYPE, 3781 E1HOV_PRI_HASH_TYPE, 3782 DSCP_HASH_TYPE, 3783 MAX_ETH_RSS_HASH_TYPE 3784}; 3785 3786 3787/* 3788 * Ethernet RSS mode 3789 */ 3790enum eth_rss_mode { 3791 ETH_RSS_MODE_DISABLED, 3792 ETH_RSS_MODE_REGULAR, 3793 ETH_RSS_MODE_VLAN_PRI, 3794 ETH_RSS_MODE_E1HOV_PRI, 3795 ETH_RSS_MODE_IP_DSCP, 3796 MAX_ETH_RSS_MODE 3797}; 3798 3799 3800/* 3801 * parameters for RSS update ramrod (E2) 3802 */ 3803struct eth_rss_update_ramrod_data { 3804 u8 rss_engine_id; 3805 u8 capabilities; 3806#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) 3807#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 3808#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) 3809#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 3810#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) 3811#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 3812#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) 3813#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3 3814#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) 3815#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 3816#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) 3817#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 3818#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<6) 3819#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 6 3820#define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0 (0x1<<7) 3821#define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0_SHIFT 7 3822 u8 rss_result_mask; 3823 u8 rss_mode; 3824 __le32 __reserved2; 3825 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE]; 3826 __le32 rss_key[T_ETH_RSS_KEY]; 3827 __le32 echo; 3828 __le32 reserved3; 3829}; 3830 3831 3832/* 3833 * The eth Rx Buffer Descriptor 3834 */ 3835struct eth_rx_bd { 3836 __le32 addr_lo; 3837 __le32 addr_hi; 3838}; 3839 3840 3841/* 3842 * Eth Rx Cqe structure- general structure for ramrods 3843 */ 3844struct common_ramrod_eth_rx_cqe { 3845 u8 ramrod_type; 3846#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) 3847#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 3848#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) 3849#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 3850#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) 3851#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 3852 u8 conn_type; 3853 __le16 reserved1; 3854 __le32 conn_and_cmd_data; 3855#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) 3856#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 3857#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) 3858#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 3859 struct ramrod_data protocol_data; 3860 __le32 echo; 3861 __le32 reserved2[11]; 3862}; 3863 3864/* 3865 * Rx Last CQE in page (in ETH) 3866 */ 3867struct eth_rx_cqe_next_page { 3868 __le32 addr_lo; 3869 __le32 addr_hi; 3870 __le32 reserved[14]; 3871}; 3872 3873/* 3874 * union for all eth rx cqe types (fix their sizes) 3875 */ 3876union eth_rx_cqe { 3877 struct eth_fast_path_rx_cqe fast_path_cqe; 3878 struct common_ramrod_eth_rx_cqe ramrod_cqe; 3879 struct eth_rx_cqe_next_page next_page_cqe; 3880 struct eth_end_agg_rx_cqe end_agg_cqe; 3881}; 3882 3883 3884/* 3885 * Values for RX ETH CQE type field 3886 */ 3887enum eth_rx_cqe_type { 3888 RX_ETH_CQE_TYPE_ETH_FASTPATH, 3889 RX_ETH_CQE_TYPE_ETH_RAMROD, 3890 RX_ETH_CQE_TYPE_ETH_START_AGG, 3891 RX_ETH_CQE_TYPE_ETH_STOP_AGG, 3892 MAX_ETH_RX_CQE_TYPE 3893}; 3894 3895 3896/* 3897 * Type of SGL/Raw field in ETH RX fast path CQE 3898 */ 3899enum eth_rx_fp_sel { 3900 ETH_FP_CQE_REGULAR, 3901 ETH_FP_CQE_RAW, 3902 MAX_ETH_RX_FP_SEL 3903}; 3904 3905 3906/* 3907 * The eth Rx SGE Descriptor 3908 */ 3909struct eth_rx_sge { 3910 __le32 addr_lo; 3911 __le32 addr_hi; 3912}; 3913 3914 3915/* 3916 * common data for all protocols 3917 */ 3918struct spe_hdr { 3919 __le32 conn_and_cmd_data; 3920#define SPE_HDR_CID (0xFFFFFF<<0) 3921#define SPE_HDR_CID_SHIFT 0 3922#define SPE_HDR_CMD_ID (0xFF<<24) 3923#define SPE_HDR_CMD_ID_SHIFT 24 3924 __le16 type; 3925#define SPE_HDR_CONN_TYPE (0xFF<<0) 3926#define SPE_HDR_CONN_TYPE_SHIFT 0 3927#define SPE_HDR_FUNCTION_ID (0xFF<<8) 3928#define SPE_HDR_FUNCTION_ID_SHIFT 8 3929 __le16 reserved1; 3930}; 3931 3932/* 3933 * specific data for ethernet slow path element 3934 */ 3935union eth_specific_data { 3936 u8 protocol_data[8]; 3937 struct regpair client_update_ramrod_data; 3938 struct regpair client_init_ramrod_init_data; 3939 struct eth_halt_ramrod_data halt_ramrod_data; 3940 struct regpair update_data_addr; 3941 struct eth_common_ramrod_data common_ramrod_data; 3942 struct regpair classify_cfg_addr; 3943 struct regpair filter_cfg_addr; 3944 struct regpair mcast_cfg_addr; 3945}; 3946 3947/* 3948 * Ethernet slow path element 3949 */ 3950struct eth_spe { 3951 struct spe_hdr hdr; 3952 union eth_specific_data data; 3953}; 3954 3955 3956/* 3957 * Ethernet command ID for slow path elements 3958 */ 3959enum eth_spqe_cmd_id { 3960 RAMROD_CMD_ID_ETH_UNUSED, 3961 RAMROD_CMD_ID_ETH_CLIENT_SETUP, 3962 RAMROD_CMD_ID_ETH_HALT, 3963 RAMROD_CMD_ID_ETH_FORWARD_SETUP, 3964 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP, 3965 RAMROD_CMD_ID_ETH_CLIENT_UPDATE, 3966 RAMROD_CMD_ID_ETH_EMPTY, 3967 RAMROD_CMD_ID_ETH_TERMINATE, 3968 RAMROD_CMD_ID_ETH_TPA_UPDATE, 3969 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES, 3970 RAMROD_CMD_ID_ETH_FILTER_RULES, 3971 RAMROD_CMD_ID_ETH_MULTICAST_RULES, 3972 RAMROD_CMD_ID_ETH_RSS_UPDATE, 3973 RAMROD_CMD_ID_ETH_SET_MAC, 3974 MAX_ETH_SPQE_CMD_ID 3975}; 3976 3977 3978/* 3979 * eth tpa update command 3980 */ 3981enum eth_tpa_update_command { 3982 TPA_UPDATE_NONE_COMMAND, 3983 TPA_UPDATE_ENABLE_COMMAND, 3984 TPA_UPDATE_DISABLE_COMMAND, 3985 MAX_ETH_TPA_UPDATE_COMMAND 3986}; 3987 3988 3989/* 3990 * Tx regular BD structure 3991 */ 3992struct eth_tx_bd { 3993 __le32 addr_lo; 3994 __le32 addr_hi; 3995 __le16 total_pkt_bytes; 3996 __le16 nbytes; 3997 u8 reserved[4]; 3998}; 3999 4000 4001/* 4002 * structure for easy accessibility to assembler 4003 */ 4004struct eth_tx_bd_flags { 4005 u8 as_bitfield; 4006#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) 4007#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 4008#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) 4009#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 4010#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) 4011#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 4012#define ETH_TX_BD_FLAGS_START_BD (0x1<<4) 4013#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 4014#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) 4015#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 4016#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) 4017#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 4018#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) 4019#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 4020}; 4021 4022/* 4023 * The eth Tx Buffer Descriptor 4024 */ 4025struct eth_tx_start_bd { 4026 __le32 addr_lo; 4027 __le32 addr_hi; 4028 __le16 nbd; 4029 __le16 nbytes; 4030 __le16 vlan_or_ethertype; 4031 struct eth_tx_bd_flags bd_flags; 4032 u8 general_data; 4033#define ETH_TX_START_BD_HDR_NBDS (0xF<<0) 4034#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 4035#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) 4036#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 4037#define ETH_TX_START_BD_RESREVED (0x1<<5) 4038#define ETH_TX_START_BD_RESREVED_SHIFT 5 4039#define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6) 4040#define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6 4041}; 4042 4043/* 4044 * Tx parsing BD structure for ETH E1/E1h 4045 */ 4046struct eth_tx_parse_bd_e1x { 4047 u8 global_data; 4048#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) 4049#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 4050#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4) 4051#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4 4052#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5) 4053#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5 4054#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6) 4055#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6 4056#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7) 4057#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7 4058 u8 tcp_flags; 4059#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) 4060#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 4061#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) 4062#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 4063#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) 4064#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 4065#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) 4066#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 4067#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) 4068#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 4069#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) 4070#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 4071#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) 4072#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 4073#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) 4074#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 4075 u8 ip_hlen_w; 4076 s8 reserved; 4077 __le16 total_hlen_w; 4078 __le16 tcp_pseudo_csum; 4079 __le16 lso_mss; 4080 __le16 ip_id; 4081 __le32 tcp_send_seq; 4082}; 4083 4084/* 4085 * Tx parsing BD structure for ETH E2 4086 */ 4087struct eth_tx_parse_bd_e2 { 4088 __le16 dst_mac_addr_lo; 4089 __le16 dst_mac_addr_mid; 4090 __le16 dst_mac_addr_hi; 4091 __le16 src_mac_addr_lo; 4092 __le16 src_mac_addr_mid; 4093 __le16 src_mac_addr_hi; 4094 __le32 parsing_data; 4095#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0) 4096#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0 4097#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13) 4098#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13 4099#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17) 4100#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17 4101#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31) 4102#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31 4103}; 4104 4105/* 4106 * The last BD in the BD memory will hold a pointer to the next BD memory 4107 */ 4108struct eth_tx_next_bd { 4109 __le32 addr_lo; 4110 __le32 addr_hi; 4111 u8 reserved[8]; 4112}; 4113 4114/* 4115 * union for 4 Bd types 4116 */ 4117union eth_tx_bd_types { 4118 struct eth_tx_start_bd start_bd; 4119 struct eth_tx_bd reg_bd; 4120 struct eth_tx_parse_bd_e1x parse_bd_e1x; 4121 struct eth_tx_parse_bd_e2 parse_bd_e2; 4122 struct eth_tx_next_bd next_bd; 4123}; 4124 4125/* 4126 * array of 13 bds as appears in the eth xstorm context 4127 */ 4128struct eth_tx_bds_array { 4129 union eth_tx_bd_types bds[13]; 4130}; 4131 4132 4133/* 4134 * VLAN mode on TX BDs 4135 */ 4136enum eth_tx_vlan_type { 4137 X_ETH_NO_VLAN, 4138 X_ETH_OUTBAND_VLAN, 4139 X_ETH_INBAND_VLAN, 4140 X_ETH_FW_ADDED_VLAN, 4141 MAX_ETH_TX_VLAN_TYPE 4142}; 4143 4144 4145/* 4146 * Ethernet VLAN filtering mode in E1x 4147 */ 4148enum eth_vlan_filter_mode { 4149 ETH_VLAN_FILTER_ANY_VLAN, 4150 ETH_VLAN_FILTER_SPECIFIC_VLAN, 4151 ETH_VLAN_FILTER_CLASSIFY, 4152 MAX_ETH_VLAN_FILTER_MODE 4153}; 4154 4155 4156/* 4157 * MAC filtering configuration command header 4158 */ 4159struct mac_configuration_hdr { 4160 u8 length; 4161 u8 offset; 4162 __le16 client_id; 4163 __le32 echo; 4164}; 4165 4166/* 4167 * MAC address in list for ramrod 4168 */ 4169struct mac_configuration_entry { 4170 __le16 lsb_mac_addr; 4171 __le16 middle_mac_addr; 4172 __le16 msb_mac_addr; 4173 __le16 vlan_id; 4174 u8 pf_id; 4175 u8 flags; 4176#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) 4177#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 4178#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) 4179#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 4180#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) 4181#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 4182#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) 4183#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 4184#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) 4185#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 4186#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) 4187#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 4188 __le16 reserved0; 4189 __le32 clients_bit_vector; 4190}; 4191 4192/* 4193 * MAC filtering configuration command 4194 */ 4195struct mac_configuration_cmd { 4196 struct mac_configuration_hdr hdr; 4197 struct mac_configuration_entry config_table[64]; 4198}; 4199 4200 4201/* 4202 * Set-MAC command type (in E1x) 4203 */ 4204enum set_mac_action_type { 4205 T_ETH_MAC_COMMAND_INVALIDATE, 4206 T_ETH_MAC_COMMAND_SET, 4207 MAX_SET_MAC_ACTION_TYPE 4208}; 4209 4210 4211/* 4212 * Ethernet TPA Modes 4213 */ 4214enum tpa_mode { 4215 TPA_LRO, 4216 TPA_GRO, 4217 MAX_TPA_MODE}; 4218 4219 4220/* 4221 * tpa update ramrod data 4222 */ 4223struct tpa_update_ramrod_data { 4224 u8 update_ipv4; 4225 u8 update_ipv6; 4226 u8 client_id; 4227 u8 max_tpa_queues; 4228 u8 max_sges_for_packet; 4229 u8 complete_on_both_clients; 4230 u8 dont_verify_rings_pause_thr_flg; 4231 u8 tpa_mode; 4232 __le16 sge_buff_size; 4233 __le16 max_agg_size; 4234 __le32 sge_page_base_lo; 4235 __le32 sge_page_base_hi; 4236 __le16 sge_pause_thr_low; 4237 __le16 sge_pause_thr_high; 4238}; 4239 4240 4241/* 4242 * approximate-match multicast filtering for E1H per function in Tstorm 4243 */ 4244struct tstorm_eth_approximate_match_multicast_filtering { 4245 u32 mcast_add_hash_bit_array[8]; 4246}; 4247 4248 4249/* 4250 * Common configuration parameters per function in Tstorm 4251 */ 4252struct tstorm_eth_function_common_config { 4253 __le16 config_flags; 4254#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) 4255#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 4256#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) 4257#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 4258#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) 4259#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 4260#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) 4261#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 4262#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) 4263#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 4264#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) 4265#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 4266#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) 4267#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 4268 u8 rss_result_mask; 4269 u8 reserved1; 4270 __le16 vlan_id[2]; 4271}; 4272 4273 4274/* 4275 * MAC filtering configuration parameters per port in Tstorm 4276 */ 4277struct tstorm_eth_mac_filter_config { 4278 __le32 ucast_drop_all; 4279 __le32 ucast_accept_all; 4280 __le32 mcast_drop_all; 4281 __le32 mcast_accept_all; 4282 __le32 bcast_accept_all; 4283 __le32 vlan_filter[2]; 4284 __le32 unmatched_unicast; 4285}; 4286 4287 4288/* 4289 * tx only queue init ramrod data 4290 */ 4291struct tx_queue_init_ramrod_data { 4292 struct client_init_general_data general; 4293 struct client_init_tx_data tx; 4294}; 4295 4296 4297/* 4298 * Three RX producers for ETH 4299 */ 4300struct ustorm_eth_rx_producers { 4301#if defined(__BIG_ENDIAN) 4302 u16 bd_prod; 4303 u16 cqe_prod; 4304#elif defined(__LITTLE_ENDIAN) 4305 u16 cqe_prod; 4306 u16 bd_prod; 4307#endif 4308#if defined(__BIG_ENDIAN) 4309 u16 reserved; 4310 u16 sge_prod; 4311#elif defined(__LITTLE_ENDIAN) 4312 u16 sge_prod; 4313 u16 reserved; 4314#endif 4315}; 4316 4317 4318/* 4319 * FCoE RX statistics parameters section#0 4320 */ 4321struct fcoe_rx_stat_params_section0 { 4322 __le32 fcoe_rx_pkt_cnt; 4323 __le32 fcoe_rx_byte_cnt; 4324}; 4325 4326 4327/* 4328 * FCoE RX statistics parameters section#1 4329 */ 4330struct fcoe_rx_stat_params_section1 { 4331 __le32 fcoe_ver_cnt; 4332 __le32 fcoe_rx_drop_pkt_cnt; 4333}; 4334 4335 4336/* 4337 * FCoE RX statistics parameters section#2 4338 */ 4339struct fcoe_rx_stat_params_section2 { 4340 __le32 fc_crc_cnt; 4341 __le32 eofa_del_cnt; 4342 __le32 miss_frame_cnt; 4343 __le32 seq_timeout_cnt; 4344 __le32 drop_seq_cnt; 4345 __le32 fcoe_rx_drop_pkt_cnt; 4346 __le32 fcp_rx_pkt_cnt; 4347 __le32 reserved0; 4348}; 4349 4350 4351/* 4352 * FCoE TX statistics parameters 4353 */ 4354struct fcoe_tx_stat_params { 4355 __le32 fcoe_tx_pkt_cnt; 4356 __le32 fcoe_tx_byte_cnt; 4357 __le32 fcp_tx_pkt_cnt; 4358 __le32 reserved0; 4359}; 4360 4361/* 4362 * FCoE statistics parameters 4363 */ 4364struct fcoe_statistics_params { 4365 struct fcoe_tx_stat_params tx_stat; 4366 struct fcoe_rx_stat_params_section0 rx_stat0; 4367 struct fcoe_rx_stat_params_section1 rx_stat1; 4368 struct fcoe_rx_stat_params_section2 rx_stat2; 4369}; 4370 4371 4372/* 4373 * cfc delete event data 4374*/ 4375struct cfc_del_event_data { 4376 u32 cid; 4377 u32 reserved0; 4378 u32 reserved1; 4379}; 4380 4381 4382/* 4383 * per-port SAFC demo variables 4384 */ 4385struct cmng_flags_per_port { 4386 u32 cmng_enables; 4387#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) 4388#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 4389#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) 4390#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 4391#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) 4392#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 4393#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) 4394#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 4395#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) 4396#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 4397 u32 __reserved1; 4398}; 4399 4400 4401/* 4402 * per-port rate shaping variables 4403 */ 4404struct rate_shaping_vars_per_port { 4405 u32 rs_periodic_timeout; 4406 u32 rs_threshold; 4407}; 4408 4409/* 4410 * per-port fairness variables 4411 */ 4412struct fairness_vars_per_port { 4413 u32 upper_bound; 4414 u32 fair_threshold; 4415 u32 fairness_timeout; 4416 u32 reserved0; 4417}; 4418 4419/* 4420 * per-port SAFC variables 4421 */ 4422struct safc_struct_per_port { 4423#if defined(__BIG_ENDIAN) 4424 u16 __reserved1; 4425 u8 __reserved0; 4426 u8 safc_timeout_usec; 4427#elif defined(__LITTLE_ENDIAN) 4428 u8 safc_timeout_usec; 4429 u8 __reserved0; 4430 u16 __reserved1; 4431#endif 4432 u8 cos_to_traffic_types[MAX_COS_NUMBER]; 4433 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; 4434}; 4435 4436/* 4437 * Per-port congestion management variables 4438 */ 4439struct cmng_struct_per_port { 4440 struct rate_shaping_vars_per_port rs_vars; 4441 struct fairness_vars_per_port fair_vars; 4442 struct safc_struct_per_port safc_vars; 4443 struct cmng_flags_per_port flags; 4444}; 4445 4446 4447/* 4448 * Protocol-common command ID for slow path elements 4449 */ 4450enum common_spqe_cmd_id { 4451 RAMROD_CMD_ID_COMMON_UNUSED, 4452 RAMROD_CMD_ID_COMMON_FUNCTION_START, 4453 RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 4454 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 4455 RAMROD_CMD_ID_COMMON_CFC_DEL, 4456 RAMROD_CMD_ID_COMMON_CFC_DEL_WB, 4457 RAMROD_CMD_ID_COMMON_STAT_QUERY, 4458 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 4459 RAMROD_CMD_ID_COMMON_START_TRAFFIC, 4460 RAMROD_CMD_ID_COMMON_RESERVED1, 4461 MAX_COMMON_SPQE_CMD_ID 4462}; 4463 4464 4465/* 4466 * Per-protocol connection types 4467 */ 4468enum connection_type { 4469 ETH_CONNECTION_TYPE, 4470 TOE_CONNECTION_TYPE, 4471 RDMA_CONNECTION_TYPE, 4472 ISCSI_CONNECTION_TYPE, 4473 FCOE_CONNECTION_TYPE, 4474 RESERVED_CONNECTION_TYPE_0, 4475 RESERVED_CONNECTION_TYPE_1, 4476 RESERVED_CONNECTION_TYPE_2, 4477 NONE_CONNECTION_TYPE, 4478 MAX_CONNECTION_TYPE 4479}; 4480 4481 4482/* 4483 * Cos modes 4484 */ 4485enum cos_mode { 4486 OVERRIDE_COS, 4487 STATIC_COS, 4488 FW_WRR, 4489 MAX_COS_MODE 4490}; 4491 4492 4493/* 4494 * Dynamic HC counters set by the driver 4495 */ 4496struct hc_dynamic_drv_counter { 4497 u32 val[HC_SB_MAX_DYNAMIC_INDICES]; 4498}; 4499 4500/* 4501 * zone A per-queue data 4502 */ 4503struct cstorm_queue_zone_data { 4504 struct hc_dynamic_drv_counter hc_dyn_drv_cnt; 4505 struct regpair reserved[2]; 4506}; 4507 4508 4509/* 4510 * Vf-PF channel data in cstorm ram (non-triggered zone) 4511 */ 4512struct vf_pf_channel_zone_data { 4513 u32 msg_addr_lo; 4514 u32 msg_addr_hi; 4515}; 4516 4517/* 4518 * zone for VF non-triggered data 4519 */ 4520struct non_trigger_vf_zone { 4521 struct vf_pf_channel_zone_data vf_pf_channel; 4522}; 4523 4524/* 4525 * Vf-PF channel trigger zone in cstorm ram 4526 */ 4527struct vf_pf_channel_zone_trigger { 4528 u8 addr_valid; 4529}; 4530 4531/* 4532 * zone that triggers the in-bound interrupt 4533 */ 4534struct trigger_vf_zone { 4535#if defined(__BIG_ENDIAN) 4536 u16 reserved1; 4537 u8 reserved0; 4538 struct vf_pf_channel_zone_trigger vf_pf_channel; 4539#elif defined(__LITTLE_ENDIAN) 4540 struct vf_pf_channel_zone_trigger vf_pf_channel; 4541 u8 reserved0; 4542 u16 reserved1; 4543#endif 4544 u32 reserved2; 4545}; 4546 4547/* 4548 * zone B per-VF data 4549 */ 4550struct cstorm_vf_zone_data { 4551 struct non_trigger_vf_zone non_trigger; 4552 struct trigger_vf_zone trigger; 4553}; 4554 4555 4556/* 4557 * Dynamic host coalescing init parameters, per state machine 4558 */ 4559struct dynamic_hc_sm_config { 4560 u32 threshold[3]; 4561 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES]; 4562 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES]; 4563 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES]; 4564 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES]; 4565 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES]; 4566}; 4567 4568/* 4569 * Dynamic host coalescing init parameters 4570 */ 4571struct dynamic_hc_config { 4572 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM]; 4573}; 4574 4575 4576struct e2_integ_data { 4577#if defined(__BIG_ENDIAN) 4578 u8 flags; 4579#define E2_INTEG_DATA_TESTING_EN (0x1<<0) 4580#define E2_INTEG_DATA_TESTING_EN_SHIFT 0 4581#define E2_INTEG_DATA_LB_TX (0x1<<1) 4582#define E2_INTEG_DATA_LB_TX_SHIFT 1 4583#define E2_INTEG_DATA_COS_TX (0x1<<2) 4584#define E2_INTEG_DATA_COS_TX_SHIFT 2 4585#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 4586#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 4587#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 4588#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 4589#define E2_INTEG_DATA_RESERVED (0x7<<5) 4590#define E2_INTEG_DATA_RESERVED_SHIFT 5 4591 u8 cos; 4592 u8 voq; 4593 u8 pbf_queue; 4594#elif defined(__LITTLE_ENDIAN) 4595 u8 pbf_queue; 4596 u8 voq; 4597 u8 cos; 4598 u8 flags; 4599#define E2_INTEG_DATA_TESTING_EN (0x1<<0) 4600#define E2_INTEG_DATA_TESTING_EN_SHIFT 0 4601#define E2_INTEG_DATA_LB_TX (0x1<<1) 4602#define E2_INTEG_DATA_LB_TX_SHIFT 1 4603#define E2_INTEG_DATA_COS_TX (0x1<<2) 4604#define E2_INTEG_DATA_COS_TX_SHIFT 2 4605#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 4606#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 4607#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 4608#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 4609#define E2_INTEG_DATA_RESERVED (0x7<<5) 4610#define E2_INTEG_DATA_RESERVED_SHIFT 5 4611#endif 4612#if defined(__BIG_ENDIAN) 4613 u16 reserved3; 4614 u8 reserved2; 4615 u8 ramEn; 4616#elif defined(__LITTLE_ENDIAN) 4617 u8 ramEn; 4618 u8 reserved2; 4619 u16 reserved3; 4620#endif 4621}; 4622 4623 4624/* 4625 * set mac event data 4626 */ 4627struct eth_event_data { 4628 u32 echo; 4629 u32 reserved0; 4630 u32 reserved1; 4631}; 4632 4633 4634/* 4635 * pf-vf event data 4636 */ 4637struct vf_pf_event_data { 4638 u8 vf_id; 4639 u8 reserved0; 4640 u16 reserved1; 4641 u32 msg_addr_lo; 4642 u32 msg_addr_hi; 4643}; 4644 4645/* 4646 * VF FLR event data 4647 */ 4648struct vf_flr_event_data { 4649 u8 vf_id; 4650 u8 reserved0; 4651 u16 reserved1; 4652 u32 reserved2; 4653 u32 reserved3; 4654}; 4655 4656/* 4657 * malicious VF event data 4658 */ 4659struct malicious_vf_event_data { 4660 u8 vf_id; 4661 u8 reserved0; 4662 u16 reserved1; 4663 u32 reserved2; 4664 u32 reserved3; 4665}; 4666 4667/* 4668 * union for all event ring message types 4669 */ 4670union event_data { 4671 struct vf_pf_event_data vf_pf_event; 4672 struct eth_event_data eth_event; 4673 struct cfc_del_event_data cfc_del_event; 4674 struct vf_flr_event_data vf_flr_event; 4675 struct malicious_vf_event_data malicious_vf_event; 4676}; 4677 4678 4679/* 4680 * per PF event ring data 4681 */ 4682struct event_ring_data { 4683 struct regpair base_addr; 4684#if defined(__BIG_ENDIAN) 4685 u8 index_id; 4686 u8 sb_id; 4687 u16 producer; 4688#elif defined(__LITTLE_ENDIAN) 4689 u16 producer; 4690 u8 sb_id; 4691 u8 index_id; 4692#endif 4693 u32 reserved0; 4694}; 4695 4696 4697/* 4698 * event ring message element (each element is 128 bits) 4699 */ 4700struct event_ring_msg { 4701 u8 opcode; 4702 u8 error; 4703 u16 reserved1; 4704 union event_data data; 4705}; 4706 4707/* 4708 * event ring next page element (128 bits) 4709 */ 4710struct event_ring_next { 4711 struct regpair addr; 4712 u32 reserved[2]; 4713}; 4714 4715/* 4716 * union for event ring element types (each element is 128 bits) 4717 */ 4718union event_ring_elem { 4719 struct event_ring_msg message; 4720 struct event_ring_next next_page; 4721}; 4722 4723 4724/* 4725 * Common event ring opcodes 4726 */ 4727enum event_ring_opcode { 4728 EVENT_RING_OPCODE_VF_PF_CHANNEL, 4729 EVENT_RING_OPCODE_FUNCTION_START, 4730 EVENT_RING_OPCODE_FUNCTION_STOP, 4731 EVENT_RING_OPCODE_CFC_DEL, 4732 EVENT_RING_OPCODE_CFC_DEL_WB, 4733 EVENT_RING_OPCODE_STAT_QUERY, 4734 EVENT_RING_OPCODE_STOP_TRAFFIC, 4735 EVENT_RING_OPCODE_START_TRAFFIC, 4736 EVENT_RING_OPCODE_VF_FLR, 4737 EVENT_RING_OPCODE_MALICIOUS_VF, 4738 EVENT_RING_OPCODE_FORWARD_SETUP, 4739 EVENT_RING_OPCODE_RSS_UPDATE_RULES, 4740 EVENT_RING_OPCODE_FUNCTION_UPDATE, 4741 EVENT_RING_OPCODE_RESERVED1, 4742 EVENT_RING_OPCODE_SET_MAC, 4743 EVENT_RING_OPCODE_CLASSIFICATION_RULES, 4744 EVENT_RING_OPCODE_FILTERS_RULES, 4745 EVENT_RING_OPCODE_MULTICAST_RULES, 4746 MAX_EVENT_RING_OPCODE 4747}; 4748 4749 4750/* 4751 * Modes for fairness algorithm 4752 */ 4753enum fairness_mode { 4754 FAIRNESS_COS_WRR_MODE, 4755 FAIRNESS_COS_ETS_MODE, 4756 MAX_FAIRNESS_MODE 4757}; 4758 4759 4760/* 4761 * per-vnic fairness variables 4762 */ 4763struct fairness_vars_per_vn { 4764 u32 cos_credit_delta[MAX_COS_NUMBER]; 4765 u32 vn_credit_delta; 4766 u32 __reserved0; 4767}; 4768 4769 4770/* 4771 * Priority and cos 4772 */ 4773struct priority_cos { 4774 u8 priority; 4775 u8 cos; 4776 __le16 reserved1; 4777}; 4778 4779/* 4780 * The data for flow control configuration 4781 */ 4782struct flow_control_configuration { 4783 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 4784 u8 dcb_enabled; 4785 u8 dcb_version; 4786 u8 dont_add_pri_0_en; 4787 u8 reserved1; 4788 __le32 reserved2; 4789}; 4790 4791 4792/* 4793 * 4794 */ 4795struct function_start_data { 4796 __le16 function_mode; 4797 __le16 sd_vlan_tag; 4798 u16 reserved; 4799 u8 path_id; 4800 u8 network_cos_mode; 4801}; 4802 4803 4804/* 4805 * FW version stored in the Xstorm RAM 4806 */ 4807struct fw_version { 4808#if defined(__BIG_ENDIAN) 4809 u8 engineering; 4810 u8 revision; 4811 u8 minor; 4812 u8 major; 4813#elif defined(__LITTLE_ENDIAN) 4814 u8 major; 4815 u8 minor; 4816 u8 revision; 4817 u8 engineering; 4818#endif 4819 u32 flags; 4820#define FW_VERSION_OPTIMIZED (0x1<<0) 4821#define FW_VERSION_OPTIMIZED_SHIFT 0 4822#define FW_VERSION_BIG_ENDIEN (0x1<<1) 4823#define FW_VERSION_BIG_ENDIEN_SHIFT 1 4824#define FW_VERSION_CHIP_VERSION (0x3<<2) 4825#define FW_VERSION_CHIP_VERSION_SHIFT 2 4826#define __FW_VERSION_RESERVED (0xFFFFFFF<<4) 4827#define __FW_VERSION_RESERVED_SHIFT 4 4828}; 4829 4830 4831/* 4832 * Dynamic Host-Coalescing - Driver(host) counters 4833 */ 4834struct hc_dynamic_sb_drv_counters { 4835 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES]; 4836}; 4837 4838 4839/* 4840 * 2 bytes. configuration/state parameters for a single protocol index 4841 */ 4842struct hc_index_data { 4843#if defined(__BIG_ENDIAN) 4844 u8 flags; 4845#define HC_INDEX_DATA_SM_ID (0x1<<0) 4846#define HC_INDEX_DATA_SM_ID_SHIFT 0 4847#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 4848#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 4849#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 4850#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 4851#define HC_INDEX_DATA_RESERVE (0x1F<<3) 4852#define HC_INDEX_DATA_RESERVE_SHIFT 3 4853 u8 timeout; 4854#elif defined(__LITTLE_ENDIAN) 4855 u8 timeout; 4856 u8 flags; 4857#define HC_INDEX_DATA_SM_ID (0x1<<0) 4858#define HC_INDEX_DATA_SM_ID_SHIFT 0 4859#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 4860#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 4861#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 4862#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 4863#define HC_INDEX_DATA_RESERVE (0x1F<<3) 4864#define HC_INDEX_DATA_RESERVE_SHIFT 3 4865#endif 4866}; 4867 4868 4869/* 4870 * HC state-machine 4871 */ 4872struct hc_status_block_sm { 4873#if defined(__BIG_ENDIAN) 4874 u8 igu_seg_id; 4875 u8 igu_sb_id; 4876 u8 timer_value; 4877 u8 __flags; 4878#elif defined(__LITTLE_ENDIAN) 4879 u8 __flags; 4880 u8 timer_value; 4881 u8 igu_sb_id; 4882 u8 igu_seg_id; 4883#endif 4884 u32 time_to_expire; 4885}; 4886 4887/* 4888 * hold PCI identification variables- used in various places in firmware 4889 */ 4890struct pci_entity { 4891#if defined(__BIG_ENDIAN) 4892 u8 vf_valid; 4893 u8 vf_id; 4894 u8 vnic_id; 4895 u8 pf_id; 4896#elif defined(__LITTLE_ENDIAN) 4897 u8 pf_id; 4898 u8 vnic_id; 4899 u8 vf_id; 4900 u8 vf_valid; 4901#endif 4902}; 4903 4904/* 4905 * The fast-path status block meta-data, common to all chips 4906 */ 4907struct hc_sb_data { 4908 struct regpair host_sb_addr; 4909 struct hc_status_block_sm state_machine[HC_SB_MAX_SM]; 4910 struct pci_entity p_func; 4911#if defined(__BIG_ENDIAN) 4912 u8 rsrv0; 4913 u8 state; 4914 u8 dhc_qzone_id; 4915 u8 same_igu_sb_1b; 4916#elif defined(__LITTLE_ENDIAN) 4917 u8 same_igu_sb_1b; 4918 u8 dhc_qzone_id; 4919 u8 state; 4920 u8 rsrv0; 4921#endif 4922 struct regpair rsrv1[2]; 4923}; 4924 4925 4926/* 4927 * Segment types for host coaslescing 4928 */ 4929enum hc_segment { 4930 HC_REGULAR_SEGMENT, 4931 HC_DEFAULT_SEGMENT, 4932 MAX_HC_SEGMENT 4933}; 4934 4935 4936/* 4937 * The fast-path status block meta-data 4938 */ 4939struct hc_sp_status_block_data { 4940 struct regpair host_sb_addr; 4941#if defined(__BIG_ENDIAN) 4942 u8 rsrv1; 4943 u8 state; 4944 u8 igu_seg_id; 4945 u8 igu_sb_id; 4946#elif defined(__LITTLE_ENDIAN) 4947 u8 igu_sb_id; 4948 u8 igu_seg_id; 4949 u8 state; 4950 u8 rsrv1; 4951#endif 4952 struct pci_entity p_func; 4953}; 4954 4955 4956/* 4957 * The fast-path status block meta-data 4958 */ 4959struct hc_status_block_data_e1x { 4960 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]; 4961 struct hc_sb_data common; 4962}; 4963 4964 4965/* 4966 * The fast-path status block meta-data 4967 */ 4968struct hc_status_block_data_e2 { 4969 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]; 4970 struct hc_sb_data common; 4971}; 4972 4973 4974/* 4975 * IGU block operartion modes (in Everest2) 4976 */ 4977enum igu_mode { 4978 HC_IGU_BC_MODE, 4979 HC_IGU_NBC_MODE, 4980 MAX_IGU_MODE 4981}; 4982 4983 4984/* 4985 * IP versions 4986 */ 4987enum ip_ver { 4988 IP_V4, 4989 IP_V6, 4990 MAX_IP_VER 4991}; 4992 4993 4994/* 4995 * Multi-function modes 4996 */ 4997enum mf_mode { 4998 SINGLE_FUNCTION, 4999 MULTI_FUNCTION_SD, 5000 MULTI_FUNCTION_SI, 5001 MULTI_FUNCTION_RESERVED, 5002 MAX_MF_MODE 5003}; 5004 5005/* 5006 * Protocol-common statistics collected by the Tstorm (per pf) 5007 */ 5008struct tstorm_per_pf_stats { 5009 struct regpair rcv_error_bytes; 5010}; 5011 5012/* 5013 * 5014 */ 5015struct per_pf_stats { 5016 struct tstorm_per_pf_stats tstorm_pf_statistics; 5017}; 5018 5019 5020/* 5021 * Protocol-common statistics collected by the Tstorm (per port) 5022 */ 5023struct tstorm_per_port_stats { 5024 __le32 mac_discard; 5025 __le32 mac_filter_discard; 5026 __le32 brb_truncate_discard; 5027 __le32 mf_tag_discard; 5028 __le32 packet_drop; 5029 __le32 reserved; 5030}; 5031 5032/* 5033 * 5034 */ 5035struct per_port_stats { 5036 struct tstorm_per_port_stats tstorm_port_statistics; 5037}; 5038 5039 5040/* 5041 * Protocol-common statistics collected by the Tstorm (per client) 5042 */ 5043struct tstorm_per_queue_stats { 5044 struct regpair rcv_ucast_bytes; 5045 __le32 rcv_ucast_pkts; 5046 __le32 checksum_discard; 5047 struct regpair rcv_bcast_bytes; 5048 __le32 rcv_bcast_pkts; 5049 __le32 pkts_too_big_discard; 5050 struct regpair rcv_mcast_bytes; 5051 __le32 rcv_mcast_pkts; 5052 __le32 ttl0_discard; 5053 __le16 no_buff_discard; 5054 __le16 reserved0; 5055 __le32 reserved1; 5056}; 5057 5058/* 5059 * Protocol-common statistics collected by the Ustorm (per client) 5060 */ 5061struct ustorm_per_queue_stats { 5062 struct regpair ucast_no_buff_bytes; 5063 struct regpair mcast_no_buff_bytes; 5064 struct regpair bcast_no_buff_bytes; 5065 __le32 ucast_no_buff_pkts; 5066 __le32 mcast_no_buff_pkts; 5067 __le32 bcast_no_buff_pkts; 5068 __le32 coalesced_pkts; 5069 struct regpair coalesced_bytes; 5070 __le32 coalesced_events; 5071 __le32 coalesced_aborts; 5072}; 5073 5074/* 5075 * Protocol-common statistics collected by the Xstorm (per client) 5076 */ 5077struct xstorm_per_queue_stats { 5078 struct regpair ucast_bytes_sent; 5079 struct regpair mcast_bytes_sent; 5080 struct regpair bcast_bytes_sent; 5081 __le32 ucast_pkts_sent; 5082 __le32 mcast_pkts_sent; 5083 __le32 bcast_pkts_sent; 5084 __le32 error_drop_pkts; 5085}; 5086 5087/* 5088 * 5089 */ 5090struct per_queue_stats { 5091 struct tstorm_per_queue_stats tstorm_queue_statistics; 5092 struct ustorm_per_queue_stats ustorm_queue_statistics; 5093 struct xstorm_per_queue_stats xstorm_queue_statistics; 5094}; 5095 5096 5097/* 5098 * FW version stored in first line of pram 5099 */ 5100struct pram_fw_version { 5101 u8 major; 5102 u8 minor; 5103 u8 revision; 5104 u8 engineering; 5105 u8 flags; 5106#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) 5107#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 5108#define PRAM_FW_VERSION_STORM_ID (0x3<<1) 5109#define PRAM_FW_VERSION_STORM_ID_SHIFT 1 5110#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) 5111#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 5112#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) 5113#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 5114#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) 5115#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 5116}; 5117 5118 5119/* 5120 * Ethernet slow path element 5121 */ 5122union protocol_common_specific_data { 5123 u8 protocol_data[8]; 5124 struct regpair phy_address; 5125 struct regpair mac_config_addr; 5126}; 5127 5128/* 5129 * The send queue element 5130 */ 5131struct protocol_common_spe { 5132 struct spe_hdr hdr; 5133 union protocol_common_specific_data data; 5134}; 5135 5136 5137/* 5138 * a single rate shaping counter. can be used as protocol or vnic counter 5139 */ 5140struct rate_shaping_counter { 5141 u32 quota; 5142#if defined(__BIG_ENDIAN) 5143 u16 __reserved0; 5144 u16 rate; 5145#elif defined(__LITTLE_ENDIAN) 5146 u16 rate; 5147 u16 __reserved0; 5148#endif 5149}; 5150 5151 5152/* 5153 * per-vnic rate shaping variables 5154 */ 5155struct rate_shaping_vars_per_vn { 5156 struct rate_shaping_counter vn_counter; 5157}; 5158 5159 5160/* 5161 * The send queue element 5162 */ 5163struct slow_path_element { 5164 struct spe_hdr hdr; 5165 struct regpair protocol_data; 5166}; 5167 5168 5169/* 5170 * Protocol-common statistics counter 5171 */ 5172struct stats_counter { 5173 __le16 xstats_counter; 5174 __le16 reserved0; 5175 __le32 reserved1; 5176 __le16 tstats_counter; 5177 __le16 reserved2; 5178 __le32 reserved3; 5179 __le16 ustats_counter; 5180 __le16 reserved4; 5181 __le32 reserved5; 5182 __le16 cstats_counter; 5183 __le16 reserved6; 5184 __le32 reserved7; 5185}; 5186 5187 5188/* 5189 * 5190 */ 5191struct stats_query_entry { 5192 u8 kind; 5193 u8 index; 5194 __le16 funcID; 5195 __le32 reserved; 5196 struct regpair address; 5197}; 5198 5199/* 5200 * statistic command 5201 */ 5202struct stats_query_cmd_group { 5203 struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 5204}; 5205 5206 5207/* 5208 * statistic command header 5209 */ 5210struct stats_query_header { 5211 u8 cmd_num; 5212 u8 reserved0; 5213 __le16 drv_stats_counter; 5214 __le32 reserved1; 5215 struct regpair stats_counters_addrs; 5216}; 5217 5218 5219/* 5220 * Types of statistcis query entry 5221 */ 5222enum stats_query_type { 5223 STATS_TYPE_QUEUE, 5224 STATS_TYPE_PORT, 5225 STATS_TYPE_PF, 5226 STATS_TYPE_TOE, 5227 STATS_TYPE_FCOE, 5228 MAX_STATS_QUERY_TYPE 5229}; 5230 5231 5232/* 5233 * Indicate of the function status block state 5234 */ 5235enum status_block_state { 5236 SB_DISABLED, 5237 SB_ENABLED, 5238 SB_CLEANED, 5239 MAX_STATUS_BLOCK_STATE 5240}; 5241 5242 5243/* 5244 * Storm IDs (including attentions for IGU related enums) 5245 */ 5246enum storm_id { 5247 USTORM_ID, 5248 CSTORM_ID, 5249 XSTORM_ID, 5250 TSTORM_ID, 5251 ATTENTION_ID, 5252 MAX_STORM_ID 5253}; 5254 5255 5256/* 5257 * Taffic types used in ETS and flow control algorithms 5258 */ 5259enum traffic_type { 5260 LLFC_TRAFFIC_TYPE_NW, 5261 LLFC_TRAFFIC_TYPE_FCOE, 5262 LLFC_TRAFFIC_TYPE_ISCSI, 5263 MAX_TRAFFIC_TYPE 5264}; 5265 5266 5267/* 5268 * zone A per-queue data 5269 */ 5270struct tstorm_queue_zone_data { 5271 struct regpair reserved[4]; 5272}; 5273 5274 5275/* 5276 * zone B per-VF data 5277 */ 5278struct tstorm_vf_zone_data { 5279 struct regpair reserved; 5280}; 5281 5282 5283/* 5284 * zone A per-queue data 5285 */ 5286struct ustorm_queue_zone_data { 5287 struct ustorm_eth_rx_producers eth_rx_producers; 5288 struct regpair reserved[3]; 5289}; 5290 5291 5292/* 5293 * zone B per-VF data 5294 */ 5295struct ustorm_vf_zone_data { 5296 struct regpair reserved; 5297}; 5298 5299 5300/* 5301 * data per VF-PF channel 5302 */ 5303struct vf_pf_channel_data { 5304#if defined(__BIG_ENDIAN) 5305 u16 reserved0; 5306 u8 valid; 5307 u8 state; 5308#elif defined(__LITTLE_ENDIAN) 5309 u8 state; 5310 u8 valid; 5311 u16 reserved0; 5312#endif 5313 u32 reserved1; 5314}; 5315 5316 5317/* 5318 * State of VF-PF channel 5319 */ 5320enum vf_pf_channel_state { 5321 VF_PF_CHANNEL_STATE_READY, 5322 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK, 5323 MAX_VF_PF_CHANNEL_STATE 5324}; 5325 5326 5327/* 5328 * zone A per-queue data 5329 */ 5330struct xstorm_queue_zone_data { 5331 struct regpair reserved[4]; 5332}; 5333 5334 5335/* 5336 * zone B per-VF data 5337 */ 5338struct xstorm_vf_zone_data { 5339 struct regpair reserved; 5340}; 5341 5342#endif /* BNX2X_HSI_H */ 5343