bnx2x_main.c revision 127d0a198a310970b31866af8bbb6d4b1068e546
1/* bnx2x_main.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2011 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20#include <linux/module.h> 21#include <linux/moduleparam.h> 22#include <linux/kernel.h> 23#include <linux/device.h> /* for dev_info() */ 24#include <linux/timer.h> 25#include <linux/errno.h> 26#include <linux/ioport.h> 27#include <linux/slab.h> 28#include <linux/interrupt.h> 29#include <linux/pci.h> 30#include <linux/init.h> 31#include <linux/netdevice.h> 32#include <linux/etherdevice.h> 33#include <linux/skbuff.h> 34#include <linux/dma-mapping.h> 35#include <linux/bitops.h> 36#include <linux/irq.h> 37#include <linux/delay.h> 38#include <asm/byteorder.h> 39#include <linux/time.h> 40#include <linux/ethtool.h> 41#include <linux/mii.h> 42#include <linux/if.h> 43#include <linux/if_vlan.h> 44#include <net/ip.h> 45#include <net/ipv6.h> 46#include <net/tcp.h> 47#include <net/checksum.h> 48#include <net/ip6_checksum.h> 49#include <linux/workqueue.h> 50#include <linux/crc32.h> 51#include <linux/crc32c.h> 52#include <linux/prefetch.h> 53#include <linux/zlib.h> 54#include <linux/io.h> 55#include <linux/stringify.h> 56#include <linux/vmalloc.h> 57 58#include "bnx2x.h" 59#include "bnx2x_init.h" 60#include "bnx2x_init_ops.h" 61#include "bnx2x_cmn.h" 62#include "bnx2x_dcb.h" 63#include "bnx2x_sp.h" 64 65#include <linux/firmware.h> 66#include "bnx2x_fw_file_hdr.h" 67/* FW files */ 68#define FW_FILE_VERSION \ 69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 72 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 73#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 74#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 75#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 76 77/* Time in jiffies before concluding the transmitter is hung */ 78#define TX_TIMEOUT (5*HZ) 79 80static char version[] __devinitdata = 81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " 82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 83 84MODULE_AUTHOR("Eliezer Tamir"); 85MODULE_DESCRIPTION("Broadcom NetXtreme II " 86 "BCM57710/57711/57711E/" 87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 88 "57840/57840_MF Driver"); 89MODULE_LICENSE("GPL"); 90MODULE_VERSION(DRV_MODULE_VERSION); 91MODULE_FIRMWARE(FW_FILE_NAME_E1); 92MODULE_FIRMWARE(FW_FILE_NAME_E1H); 93MODULE_FIRMWARE(FW_FILE_NAME_E2); 94 95static int multi_mode = 1; 96module_param(multi_mode, int, 0); 97MODULE_PARM_DESC(multi_mode, " Multi queue mode " 98 "(0 Disable; 1 Enable (default))"); 99 100int num_queues; 101module_param(num_queues, int, 0); 102MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1" 103 " (default is as a number of CPUs)"); 104 105static int disable_tpa; 106module_param(disable_tpa, int, 0); 107MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 108 109#define INT_MODE_INTx 1 110#define INT_MODE_MSI 2 111static int int_mode; 112module_param(int_mode, int, 0); 113MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 114 "(1 INT#x; 2 MSI)"); 115 116static int dropless_fc; 117module_param(dropless_fc, int, 0); 118MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 119 120static int mrrs = -1; 121module_param(mrrs, int, 0); 122MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 123 124static int debug; 125module_param(debug, int, 0); 126MODULE_PARM_DESC(debug, " Default debug msglevel"); 127 128 129 130struct workqueue_struct *bnx2x_wq; 131 132enum bnx2x_board_type { 133 BCM57710 = 0, 134 BCM57711, 135 BCM57711E, 136 BCM57712, 137 BCM57712_MF, 138 BCM57800, 139 BCM57800_MF, 140 BCM57810, 141 BCM57810_MF, 142 BCM57840, 143 BCM57840_MF 144}; 145 146/* indexed by board_type, above */ 147static struct { 148 char *name; 149} board_info[] __devinitdata = { 150 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, 151 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, 152 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, 153 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, 154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, 155 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, 156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, 157 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, 158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, 159 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, 160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit " 161 "Ethernet Multi Function"} 162}; 163 164#ifndef PCI_DEVICE_ID_NX2_57710 165#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 166#endif 167#ifndef PCI_DEVICE_ID_NX2_57711 168#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 169#endif 170#ifndef PCI_DEVICE_ID_NX2_57711E 171#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 172#endif 173#ifndef PCI_DEVICE_ID_NX2_57712 174#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 175#endif 176#ifndef PCI_DEVICE_ID_NX2_57712_MF 177#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 178#endif 179#ifndef PCI_DEVICE_ID_NX2_57800 180#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 181#endif 182#ifndef PCI_DEVICE_ID_NX2_57800_MF 183#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 184#endif 185#ifndef PCI_DEVICE_ID_NX2_57810 186#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 187#endif 188#ifndef PCI_DEVICE_ID_NX2_57810_MF 189#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 190#endif 191#ifndef PCI_DEVICE_ID_NX2_57840 192#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 193#endif 194#ifndef PCI_DEVICE_ID_NX2_57840_MF 195#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 196#endif 197static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { 198 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, 208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 209 { 0 } 210}; 211 212MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 213 214/**************************************************************************** 215* General service functions 216****************************************************************************/ 217 218static inline void __storm_memset_dma_mapping(struct bnx2x *bp, 219 u32 addr, dma_addr_t mapping) 220{ 221 REG_WR(bp, addr, U64_LO(mapping)); 222 REG_WR(bp, addr + 4, U64_HI(mapping)); 223} 224 225static inline void storm_memset_spq_addr(struct bnx2x *bp, 226 dma_addr_t mapping, u16 abs_fid) 227{ 228 u32 addr = XSEM_REG_FAST_MEMORY + 229 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 230 231 __storm_memset_dma_mapping(bp, addr, mapping); 232} 233 234static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 235 u16 pf_id) 236{ 237 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 238 pf_id); 239 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 240 pf_id); 241 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 242 pf_id); 243 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 244 pf_id); 245} 246 247static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 248 u8 enable) 249{ 250 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 251 enable); 252 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 253 enable); 254 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 255 enable); 256 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 257 enable); 258} 259 260static inline void storm_memset_eq_data(struct bnx2x *bp, 261 struct event_ring_data *eq_data, 262 u16 pfid) 263{ 264 size_t size = sizeof(struct event_ring_data); 265 266 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 267 268 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 269} 270 271static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 272 u16 pfid) 273{ 274 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 275 REG_WR16(bp, addr, eq_prod); 276} 277 278/* used only at init 279 * locking is done by mcp 280 */ 281static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 282{ 283 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 284 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 285 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 286 PCICFG_VENDOR_ID_OFFSET); 287} 288 289static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 290{ 291 u32 val; 292 293 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 294 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 295 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 296 PCICFG_VENDOR_ID_OFFSET); 297 298 return val; 299} 300 301#define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 302#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 303#define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 304#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 305#define DMAE_DP_DST_NONE "dst_addr [none]" 306 307static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, 308 int msglvl) 309{ 310 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 311 312 switch (dmae->opcode & DMAE_COMMAND_DST) { 313 case DMAE_CMD_DST_PCI: 314 if (src_type == DMAE_CMD_SRC_PCI) 315 DP(msglvl, "DMAE: opcode 0x%08x\n" 316 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 317 "comp_addr [%x:%08x], comp_val 0x%08x\n", 318 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 319 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 320 dmae->comp_addr_hi, dmae->comp_addr_lo, 321 dmae->comp_val); 322 else 323 DP(msglvl, "DMAE: opcode 0x%08x\n" 324 "src [%08x], len [%d*4], dst [%x:%08x]\n" 325 "comp_addr [%x:%08x], comp_val 0x%08x\n", 326 dmae->opcode, dmae->src_addr_lo >> 2, 327 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 328 dmae->comp_addr_hi, dmae->comp_addr_lo, 329 dmae->comp_val); 330 break; 331 case DMAE_CMD_DST_GRC: 332 if (src_type == DMAE_CMD_SRC_PCI) 333 DP(msglvl, "DMAE: opcode 0x%08x\n" 334 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 335 "comp_addr [%x:%08x], comp_val 0x%08x\n", 336 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 337 dmae->len, dmae->dst_addr_lo >> 2, 338 dmae->comp_addr_hi, dmae->comp_addr_lo, 339 dmae->comp_val); 340 else 341 DP(msglvl, "DMAE: opcode 0x%08x\n" 342 "src [%08x], len [%d*4], dst [%08x]\n" 343 "comp_addr [%x:%08x], comp_val 0x%08x\n", 344 dmae->opcode, dmae->src_addr_lo >> 2, 345 dmae->len, dmae->dst_addr_lo >> 2, 346 dmae->comp_addr_hi, dmae->comp_addr_lo, 347 dmae->comp_val); 348 break; 349 default: 350 if (src_type == DMAE_CMD_SRC_PCI) 351 DP(msglvl, "DMAE: opcode 0x%08x\n" 352 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 353 "comp_addr [%x:%08x] comp_val 0x%08x\n", 354 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 355 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 356 dmae->comp_val); 357 else 358 DP(msglvl, "DMAE: opcode 0x%08x\n" 359 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 360 "comp_addr [%x:%08x] comp_val 0x%08x\n", 361 dmae->opcode, dmae->src_addr_lo >> 2, 362 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 363 dmae->comp_val); 364 break; 365 } 366 367} 368 369/* copy command into DMAE command memory and set DMAE command go */ 370void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 371{ 372 u32 cmd_offset; 373 int i; 374 375 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 376 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 377 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 378 379 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n", 380 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); 381 } 382 REG_WR(bp, dmae_reg_go_c[idx], 1); 383} 384 385u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 386{ 387 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 388 DMAE_CMD_C_ENABLE); 389} 390 391u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 392{ 393 return opcode & ~DMAE_CMD_SRC_RESET; 394} 395 396u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 397 bool with_comp, u8 comp_type) 398{ 399 u32 opcode = 0; 400 401 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 402 (dst_type << DMAE_COMMAND_DST_SHIFT)); 403 404 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 405 406 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 407 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | 408 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 409 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 410 411#ifdef __BIG_ENDIAN 412 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 413#else 414 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 415#endif 416 if (with_comp) 417 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 418 return opcode; 419} 420 421static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 422 struct dmae_command *dmae, 423 u8 src_type, u8 dst_type) 424{ 425 memset(dmae, 0, sizeof(struct dmae_command)); 426 427 /* set the opcode */ 428 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 429 true, DMAE_COMP_PCI); 430 431 /* fill in the completion parameters */ 432 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 433 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 434 dmae->comp_val = DMAE_COMP_VAL; 435} 436 437/* issue a dmae command over the init-channel and wailt for completion */ 438static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, 439 struct dmae_command *dmae) 440{ 441 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 442 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 443 int rc = 0; 444 445 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n", 446 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 447 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 448 449 /* 450 * Lock the dmae channel. Disable BHs to prevent a dead-lock 451 * as long as this code is called both from syscall context and 452 * from ndo_set_rx_mode() flow that may be called from BH. 453 */ 454 spin_lock_bh(&bp->dmae_lock); 455 456 /* reset completion */ 457 *wb_comp = 0; 458 459 /* post the command on the channel used for initializations */ 460 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 461 462 /* wait for completion */ 463 udelay(5); 464 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 465 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); 466 467 if (!cnt) { 468 BNX2X_ERR("DMAE timeout!\n"); 469 rc = DMAE_TIMEOUT; 470 goto unlock; 471 } 472 cnt--; 473 udelay(50); 474 } 475 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 476 BNX2X_ERR("DMAE PCI error!\n"); 477 rc = DMAE_PCI_ERROR; 478 } 479 480 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n", 481 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 482 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 483 484unlock: 485 spin_unlock_bh(&bp->dmae_lock); 486 return rc; 487} 488 489void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 490 u32 len32) 491{ 492 struct dmae_command dmae; 493 494 if (!bp->dmae_ready) { 495 u32 *data = bnx2x_sp(bp, wb_data[0]); 496 497 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)" 498 " using indirect\n", dst_addr, len32); 499 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 500 return; 501 } 502 503 /* set opcode and fixed command fields */ 504 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 505 506 /* fill in addresses and len */ 507 dmae.src_addr_lo = U64_LO(dma_addr); 508 dmae.src_addr_hi = U64_HI(dma_addr); 509 dmae.dst_addr_lo = dst_addr >> 2; 510 dmae.dst_addr_hi = 0; 511 dmae.len = len32; 512 513 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 514 515 /* issue the command and wait for completion */ 516 bnx2x_issue_dmae_with_comp(bp, &dmae); 517} 518 519void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 520{ 521 struct dmae_command dmae; 522 523 if (!bp->dmae_ready) { 524 u32 *data = bnx2x_sp(bp, wb_data[0]); 525 int i; 526 527 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)" 528 " using indirect\n", src_addr, len32); 529 for (i = 0; i < len32; i++) 530 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 531 return; 532 } 533 534 /* set opcode and fixed command fields */ 535 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 536 537 /* fill in addresses and len */ 538 dmae.src_addr_lo = src_addr >> 2; 539 dmae.src_addr_hi = 0; 540 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 541 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 542 dmae.len = len32; 543 544 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 545 546 /* issue the command and wait for completion */ 547 bnx2x_issue_dmae_with_comp(bp, &dmae); 548} 549 550static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 551 u32 addr, u32 len) 552{ 553 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 554 int offset = 0; 555 556 while (len > dmae_wr_max) { 557 bnx2x_write_dmae(bp, phys_addr + offset, 558 addr + offset, dmae_wr_max); 559 offset += dmae_wr_max * 4; 560 len -= dmae_wr_max; 561 } 562 563 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 564} 565 566/* used only for slowpath so not inlined */ 567static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo) 568{ 569 u32 wb_write[2]; 570 571 wb_write[0] = val_hi; 572 wb_write[1] = val_lo; 573 REG_WR_DMAE(bp, reg, wb_write, 2); 574} 575 576#ifdef USE_WB_RD 577static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg) 578{ 579 u32 wb_data[2]; 580 581 REG_RD_DMAE(bp, reg, wb_data, 2); 582 583 return HILO_U64(wb_data[0], wb_data[1]); 584} 585#endif 586 587static int bnx2x_mc_assert(struct bnx2x *bp) 588{ 589 char last_idx; 590 int i, rc = 0; 591 u32 row0, row1, row2, row3; 592 593 /* XSTORM */ 594 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + 595 XSTORM_ASSERT_LIST_INDEX_OFFSET); 596 if (last_idx) 597 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 598 599 /* print the asserts */ 600 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 601 602 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + 603 XSTORM_ASSERT_LIST_OFFSET(i)); 604 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + 605 XSTORM_ASSERT_LIST_OFFSET(i) + 4); 606 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + 607 XSTORM_ASSERT_LIST_OFFSET(i) + 8); 608 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + 609 XSTORM_ASSERT_LIST_OFFSET(i) + 12); 610 611 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 612 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x" 613 " 0x%08x 0x%08x 0x%08x\n", 614 i, row3, row2, row1, row0); 615 rc++; 616 } else { 617 break; 618 } 619 } 620 621 /* TSTORM */ 622 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + 623 TSTORM_ASSERT_LIST_INDEX_OFFSET); 624 if (last_idx) 625 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 626 627 /* print the asserts */ 628 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 629 630 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + 631 TSTORM_ASSERT_LIST_OFFSET(i)); 632 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + 633 TSTORM_ASSERT_LIST_OFFSET(i) + 4); 634 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + 635 TSTORM_ASSERT_LIST_OFFSET(i) + 8); 636 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + 637 TSTORM_ASSERT_LIST_OFFSET(i) + 12); 638 639 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 640 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x" 641 " 0x%08x 0x%08x 0x%08x\n", 642 i, row3, row2, row1, row0); 643 rc++; 644 } else { 645 break; 646 } 647 } 648 649 /* CSTORM */ 650 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + 651 CSTORM_ASSERT_LIST_INDEX_OFFSET); 652 if (last_idx) 653 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 654 655 /* print the asserts */ 656 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 657 658 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + 659 CSTORM_ASSERT_LIST_OFFSET(i)); 660 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + 661 CSTORM_ASSERT_LIST_OFFSET(i) + 4); 662 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + 663 CSTORM_ASSERT_LIST_OFFSET(i) + 8); 664 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + 665 CSTORM_ASSERT_LIST_OFFSET(i) + 12); 666 667 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 668 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x" 669 " 0x%08x 0x%08x 0x%08x\n", 670 i, row3, row2, row1, row0); 671 rc++; 672 } else { 673 break; 674 } 675 } 676 677 /* USTORM */ 678 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + 679 USTORM_ASSERT_LIST_INDEX_OFFSET); 680 if (last_idx) 681 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 682 683 /* print the asserts */ 684 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 685 686 row0 = REG_RD(bp, BAR_USTRORM_INTMEM + 687 USTORM_ASSERT_LIST_OFFSET(i)); 688 row1 = REG_RD(bp, BAR_USTRORM_INTMEM + 689 USTORM_ASSERT_LIST_OFFSET(i) + 4); 690 row2 = REG_RD(bp, BAR_USTRORM_INTMEM + 691 USTORM_ASSERT_LIST_OFFSET(i) + 8); 692 row3 = REG_RD(bp, BAR_USTRORM_INTMEM + 693 USTORM_ASSERT_LIST_OFFSET(i) + 12); 694 695 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 696 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x" 697 " 0x%08x 0x%08x 0x%08x\n", 698 i, row3, row2, row1, row0); 699 rc++; 700 } else { 701 break; 702 } 703 } 704 705 return rc; 706} 707 708void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 709{ 710 u32 addr, val; 711 u32 mark, offset; 712 __be32 data[9]; 713 int word; 714 u32 trace_shmem_base; 715 if (BP_NOMCP(bp)) { 716 BNX2X_ERR("NO MCP - can not dump\n"); 717 return; 718 } 719 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 720 (bp->common.bc_ver & 0xff0000) >> 16, 721 (bp->common.bc_ver & 0xff00) >> 8, 722 (bp->common.bc_ver & 0xff)); 723 724 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 725 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 726 printk("%s" "MCP PC at 0x%x\n", lvl, val); 727 728 if (BP_PATH(bp) == 0) 729 trace_shmem_base = bp->common.shmem_base; 730 else 731 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 732 addr = trace_shmem_base - 0x0800 + 4; 733 mark = REG_RD(bp, addr); 734 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 735 + ((mark + 0x3) & ~0x3) - 0x08000000; 736 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 737 738 printk("%s", lvl); 739 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { 740 for (word = 0; word < 8; word++) 741 data[word] = htonl(REG_RD(bp, offset + 4*word)); 742 data[8] = 0x0; 743 pr_cont("%s", (char *)data); 744 } 745 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 746 for (word = 0; word < 8; word++) 747 data[word] = htonl(REG_RD(bp, offset + 4*word)); 748 data[8] = 0x0; 749 pr_cont("%s", (char *)data); 750 } 751 printk("%s" "end of fw dump\n", lvl); 752} 753 754static inline void bnx2x_fw_dump(struct bnx2x *bp) 755{ 756 bnx2x_fw_dump_lvl(bp, KERN_ERR); 757} 758 759void bnx2x_panic_dump(struct bnx2x *bp) 760{ 761 int i; 762 u16 j; 763 struct hc_sp_status_block_data sp_sb_data; 764 int func = BP_FUNC(bp); 765#ifdef BNX2X_STOP_ON_ERROR 766 u16 start = 0, end = 0; 767 u8 cos; 768#endif 769 770 bp->stats_state = STATS_STATE_DISABLED; 771 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 772 773 BNX2X_ERR("begin crash dump -----------------\n"); 774 775 /* Indices */ 776 /* Common */ 777 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)" 778 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 779 bp->def_idx, bp->def_att_idx, bp->attn_state, 780 bp->spq_prod_idx, bp->stats_counter); 781 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 782 bp->def_status_blk->atten_status_block.attn_bits, 783 bp->def_status_blk->atten_status_block.attn_bits_ack, 784 bp->def_status_blk->atten_status_block.status_block_id, 785 bp->def_status_blk->atten_status_block.attn_bits_index); 786 BNX2X_ERR(" def ("); 787 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 788 pr_cont("0x%x%s", 789 bp->def_status_blk->sp_sb.index_values[i], 790 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 791 792 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 793 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + 794 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 795 i*sizeof(u32)); 796 797 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 798 sp_sb_data.igu_sb_id, 799 sp_sb_data.igu_seg_id, 800 sp_sb_data.p_func.pf_id, 801 sp_sb_data.p_func.vnic_id, 802 sp_sb_data.p_func.vf_id, 803 sp_sb_data.p_func.vf_valid, 804 sp_sb_data.state); 805 806 807 for_each_eth_queue(bp, i) { 808 struct bnx2x_fastpath *fp = &bp->fp[i]; 809 int loop; 810 struct hc_status_block_data_e2 sb_data_e2; 811 struct hc_status_block_data_e1x sb_data_e1x; 812 struct hc_status_block_sm *hc_sm_p = 813 CHIP_IS_E1x(bp) ? 814 sb_data_e1x.common.state_machine : 815 sb_data_e2.common.state_machine; 816 struct hc_index_data *hc_index_p = 817 CHIP_IS_E1x(bp) ? 818 sb_data_e1x.index_data : 819 sb_data_e2.index_data; 820 u8 data_size, cos; 821 u32 *sb_data_p; 822 struct bnx2x_fp_txdata txdata; 823 824 /* Rx */ 825 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)" 826 " rx_comp_prod(0x%x)" 827 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 828 i, fp->rx_bd_prod, fp->rx_bd_cons, 829 fp->rx_comp_prod, 830 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 831 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)" 832 " fp_hc_idx(0x%x)\n", 833 fp->rx_sge_prod, fp->last_max_sge, 834 le16_to_cpu(fp->fp_hc_idx)); 835 836 /* Tx */ 837 for_each_cos_in_tx_queue(fp, cos) 838 { 839 txdata = fp->txdata[cos]; 840 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)" 841 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)" 842 " *tx_cons_sb(0x%x)\n", 843 i, txdata.tx_pkt_prod, 844 txdata.tx_pkt_cons, txdata.tx_bd_prod, 845 txdata.tx_bd_cons, 846 le16_to_cpu(*txdata.tx_cons_sb)); 847 } 848 849 loop = CHIP_IS_E1x(bp) ? 850 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 851 852 /* host sb data */ 853 854#ifdef BCM_CNIC 855 if (IS_FCOE_FP(fp)) 856 continue; 857#endif 858 BNX2X_ERR(" run indexes ("); 859 for (j = 0; j < HC_SB_MAX_SM; j++) 860 pr_cont("0x%x%s", 861 fp->sb_running_index[j], 862 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 863 864 BNX2X_ERR(" indexes ("); 865 for (j = 0; j < loop; j++) 866 pr_cont("0x%x%s", 867 fp->sb_index_values[j], 868 (j == loop - 1) ? ")" : " "); 869 /* fw sb data */ 870 data_size = CHIP_IS_E1x(bp) ? 871 sizeof(struct hc_status_block_data_e1x) : 872 sizeof(struct hc_status_block_data_e2); 873 data_size /= sizeof(u32); 874 sb_data_p = CHIP_IS_E1x(bp) ? 875 (u32 *)&sb_data_e1x : 876 (u32 *)&sb_data_e2; 877 /* copy sb data in here */ 878 for (j = 0; j < data_size; j++) 879 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 880 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 881 j * sizeof(u32)); 882 883 if (!CHIP_IS_E1x(bp)) { 884 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 885 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 886 "state(0x%x)\n", 887 sb_data_e2.common.p_func.pf_id, 888 sb_data_e2.common.p_func.vf_id, 889 sb_data_e2.common.p_func.vf_valid, 890 sb_data_e2.common.p_func.vnic_id, 891 sb_data_e2.common.same_igu_sb_1b, 892 sb_data_e2.common.state); 893 } else { 894 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 895 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 896 "state(0x%x)\n", 897 sb_data_e1x.common.p_func.pf_id, 898 sb_data_e1x.common.p_func.vf_id, 899 sb_data_e1x.common.p_func.vf_valid, 900 sb_data_e1x.common.p_func.vnic_id, 901 sb_data_e1x.common.same_igu_sb_1b, 902 sb_data_e1x.common.state); 903 } 904 905 /* SB_SMs data */ 906 for (j = 0; j < HC_SB_MAX_SM; j++) { 907 pr_cont("SM[%d] __flags (0x%x) " 908 "igu_sb_id (0x%x) igu_seg_id(0x%x) " 909 "time_to_expire (0x%x) " 910 "timer_value(0x%x)\n", j, 911 hc_sm_p[j].__flags, 912 hc_sm_p[j].igu_sb_id, 913 hc_sm_p[j].igu_seg_id, 914 hc_sm_p[j].time_to_expire, 915 hc_sm_p[j].timer_value); 916 } 917 918 /* Indecies data */ 919 for (j = 0; j < loop; j++) { 920 pr_cont("INDEX[%d] flags (0x%x) " 921 "timeout (0x%x)\n", j, 922 hc_index_p[j].flags, 923 hc_index_p[j].timeout); 924 } 925 } 926 927#ifdef BNX2X_STOP_ON_ERROR 928 /* Rings */ 929 /* Rx */ 930 for_each_rx_queue(bp, i) { 931 struct bnx2x_fastpath *fp = &bp->fp[i]; 932 933 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 934 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 935 for (j = start; j != end; j = RX_BD(j + 1)) { 936 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 937 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 938 939 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 940 i, j, rx_bd[1], rx_bd[0], sw_bd->data); 941 } 942 943 start = RX_SGE(fp->rx_sge_prod); 944 end = RX_SGE(fp->last_max_sge); 945 for (j = start; j != end; j = RX_SGE(j + 1)) { 946 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 947 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 948 949 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 950 i, j, rx_sge[1], rx_sge[0], sw_page->page); 951 } 952 953 start = RCQ_BD(fp->rx_comp_cons - 10); 954 end = RCQ_BD(fp->rx_comp_cons + 503); 955 for (j = start; j != end; j = RCQ_BD(j + 1)) { 956 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 957 958 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 959 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 960 } 961 } 962 963 /* Tx */ 964 for_each_tx_queue(bp, i) { 965 struct bnx2x_fastpath *fp = &bp->fp[i]; 966 for_each_cos_in_tx_queue(fp, cos) { 967 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; 968 969 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 970 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 971 for (j = start; j != end; j = TX_BD(j + 1)) { 972 struct sw_tx_bd *sw_bd = 973 &txdata->tx_buf_ring[j]; 974 975 BNX2X_ERR("fp%d: txdata %d, " 976 "packet[%x]=[%p,%x]\n", 977 i, cos, j, sw_bd->skb, 978 sw_bd->first_bd); 979 } 980 981 start = TX_BD(txdata->tx_bd_cons - 10); 982 end = TX_BD(txdata->tx_bd_cons + 254); 983 for (j = start; j != end; j = TX_BD(j + 1)) { 984 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 985 986 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=" 987 "[%x:%x:%x:%x]\n", 988 i, cos, j, tx_bd[0], tx_bd[1], 989 tx_bd[2], tx_bd[3]); 990 } 991 } 992 } 993#endif 994 bnx2x_fw_dump(bp); 995 bnx2x_mc_assert(bp); 996 BNX2X_ERR("end crash dump -----------------\n"); 997} 998 999/* 1000 * FLR Support for E2 1001 * 1002 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 1003 * initialization. 1004 */ 1005#define FLR_WAIT_USEC 10000 /* 10 miliseconds */ 1006#define FLR_WAIT_INTERAVAL 50 /* usec */ 1007#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */ 1008 1009struct pbf_pN_buf_regs { 1010 int pN; 1011 u32 init_crd; 1012 u32 crd; 1013 u32 crd_freed; 1014}; 1015 1016struct pbf_pN_cmd_regs { 1017 int pN; 1018 u32 lines_occup; 1019 u32 lines_freed; 1020}; 1021 1022static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1023 struct pbf_pN_buf_regs *regs, 1024 u32 poll_count) 1025{ 1026 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1027 u32 cur_cnt = poll_count; 1028 1029 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1030 crd = crd_start = REG_RD(bp, regs->crd); 1031 init_crd = REG_RD(bp, regs->init_crd); 1032 1033 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1034 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1035 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1036 1037 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1038 (init_crd - crd_start))) { 1039 if (cur_cnt--) { 1040 udelay(FLR_WAIT_INTERAVAL); 1041 crd = REG_RD(bp, regs->crd); 1042 crd_freed = REG_RD(bp, regs->crd_freed); 1043 } else { 1044 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1045 regs->pN); 1046 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1047 regs->pN, crd); 1048 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1049 regs->pN, crd_freed); 1050 break; 1051 } 1052 } 1053 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1054 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN); 1055} 1056 1057static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1058 struct pbf_pN_cmd_regs *regs, 1059 u32 poll_count) 1060{ 1061 u32 occup, to_free, freed, freed_start; 1062 u32 cur_cnt = poll_count; 1063 1064 occup = to_free = REG_RD(bp, regs->lines_occup); 1065 freed = freed_start = REG_RD(bp, regs->lines_freed); 1066 1067 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1068 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1069 1070 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1071 if (cur_cnt--) { 1072 udelay(FLR_WAIT_INTERAVAL); 1073 occup = REG_RD(bp, regs->lines_occup); 1074 freed = REG_RD(bp, regs->lines_freed); 1075 } else { 1076 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1077 regs->pN); 1078 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1079 regs->pN, occup); 1080 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1081 regs->pN, freed); 1082 break; 1083 } 1084 } 1085 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1086 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN); 1087} 1088 1089static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1090 u32 expected, u32 poll_count) 1091{ 1092 u32 cur_cnt = poll_count; 1093 u32 val; 1094 1095 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1096 udelay(FLR_WAIT_INTERAVAL); 1097 1098 return val; 1099} 1100 1101static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1102 char *msg, u32 poll_cnt) 1103{ 1104 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1105 if (val != 0) { 1106 BNX2X_ERR("%s usage count=%d\n", msg, val); 1107 return 1; 1108 } 1109 return 0; 1110} 1111 1112static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1113{ 1114 /* adjust polling timeout */ 1115 if (CHIP_REV_IS_EMUL(bp)) 1116 return FLR_POLL_CNT * 2000; 1117 1118 if (CHIP_REV_IS_FPGA(bp)) 1119 return FLR_POLL_CNT * 120; 1120 1121 return FLR_POLL_CNT; 1122} 1123 1124static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1125{ 1126 struct pbf_pN_cmd_regs cmd_regs[] = { 1127 {0, (CHIP_IS_E3B0(bp)) ? 1128 PBF_REG_TQ_OCCUPANCY_Q0 : 1129 PBF_REG_P0_TQ_OCCUPANCY, 1130 (CHIP_IS_E3B0(bp)) ? 1131 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1132 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1133 {1, (CHIP_IS_E3B0(bp)) ? 1134 PBF_REG_TQ_OCCUPANCY_Q1 : 1135 PBF_REG_P1_TQ_OCCUPANCY, 1136 (CHIP_IS_E3B0(bp)) ? 1137 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1138 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1139 {4, (CHIP_IS_E3B0(bp)) ? 1140 PBF_REG_TQ_OCCUPANCY_LB_Q : 1141 PBF_REG_P4_TQ_OCCUPANCY, 1142 (CHIP_IS_E3B0(bp)) ? 1143 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1144 PBF_REG_P4_TQ_LINES_FREED_CNT} 1145 }; 1146 1147 struct pbf_pN_buf_regs buf_regs[] = { 1148 {0, (CHIP_IS_E3B0(bp)) ? 1149 PBF_REG_INIT_CRD_Q0 : 1150 PBF_REG_P0_INIT_CRD , 1151 (CHIP_IS_E3B0(bp)) ? 1152 PBF_REG_CREDIT_Q0 : 1153 PBF_REG_P0_CREDIT, 1154 (CHIP_IS_E3B0(bp)) ? 1155 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1156 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1157 {1, (CHIP_IS_E3B0(bp)) ? 1158 PBF_REG_INIT_CRD_Q1 : 1159 PBF_REG_P1_INIT_CRD, 1160 (CHIP_IS_E3B0(bp)) ? 1161 PBF_REG_CREDIT_Q1 : 1162 PBF_REG_P1_CREDIT, 1163 (CHIP_IS_E3B0(bp)) ? 1164 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1165 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1166 {4, (CHIP_IS_E3B0(bp)) ? 1167 PBF_REG_INIT_CRD_LB_Q : 1168 PBF_REG_P4_INIT_CRD, 1169 (CHIP_IS_E3B0(bp)) ? 1170 PBF_REG_CREDIT_LB_Q : 1171 PBF_REG_P4_CREDIT, 1172 (CHIP_IS_E3B0(bp)) ? 1173 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1174 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1175 }; 1176 1177 int i; 1178 1179 /* Verify the command queues are flushed P0, P1, P4 */ 1180 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1181 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1182 1183 1184 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1185 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1186 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1187} 1188 1189#define OP_GEN_PARAM(param) \ 1190 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1191 1192#define OP_GEN_TYPE(type) \ 1193 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1194 1195#define OP_GEN_AGG_VECT(index) \ 1196 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1197 1198 1199static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, 1200 u32 poll_cnt) 1201{ 1202 struct sdm_op_gen op_gen = {0}; 1203 1204 u32 comp_addr = BAR_CSTRORM_INTMEM + 1205 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1206 int ret = 0; 1207 1208 if (REG_RD(bp, comp_addr)) { 1209 BNX2X_ERR("Cleanup complete is not 0\n"); 1210 return 1; 1211 } 1212 1213 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1214 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1215 op_gen.command |= OP_GEN_AGG_VECT(clnup_func); 1216 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1217 1218 DP(BNX2X_MSG_SP, "FW Final cleanup\n"); 1219 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); 1220 1221 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1222 BNX2X_ERR("FW final cleanup did not succeed\n"); 1223 ret = 1; 1224 } 1225 /* Zero completion for nxt FLR */ 1226 REG_WR(bp, comp_addr, 0); 1227 1228 return ret; 1229} 1230 1231static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1232{ 1233 int pos; 1234 u16 status; 1235 1236 pos = pci_pcie_cap(dev); 1237 if (!pos) 1238 return false; 1239 1240 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 1241 return status & PCI_EXP_DEVSTA_TRPND; 1242} 1243 1244/* PF FLR specific routines 1245*/ 1246static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1247{ 1248 1249 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1250 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1251 CFC_REG_NUM_LCIDS_INSIDE_PF, 1252 "CFC PF usage counter timed out", 1253 poll_cnt)) 1254 return 1; 1255 1256 1257 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1258 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1259 DORQ_REG_PF_USAGE_CNT, 1260 "DQ PF usage counter timed out", 1261 poll_cnt)) 1262 return 1; 1263 1264 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1265 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1266 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1267 "QM PF usage counter timed out", 1268 poll_cnt)) 1269 return 1; 1270 1271 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1272 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1273 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1274 "Timers VNIC usage counter timed out", 1275 poll_cnt)) 1276 return 1; 1277 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1278 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1279 "Timers NUM_SCANS usage counter timed out", 1280 poll_cnt)) 1281 return 1; 1282 1283 /* Wait DMAE PF usage counter to zero */ 1284 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1285 dmae_reg_go_c[INIT_DMAE_C(bp)], 1286 "DMAE dommand register timed out", 1287 poll_cnt)) 1288 return 1; 1289 1290 return 0; 1291} 1292 1293static void bnx2x_hw_enable_status(struct bnx2x *bp) 1294{ 1295 u32 val; 1296 1297 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1298 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1299 1300 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1301 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1302 1303 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1304 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1305 1306 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1307 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1308 1309 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1310 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1311 1312 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1313 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1314 1315 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1316 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1317 1318 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1319 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1320 val); 1321} 1322 1323static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1324{ 1325 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1326 1327 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1328 1329 /* Re-enable PF target read access */ 1330 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1331 1332 /* Poll HW usage counters */ 1333 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1334 return -EBUSY; 1335 1336 /* Zero the igu 'trailing edge' and 'leading edge' */ 1337 1338 /* Send the FW cleanup command */ 1339 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1340 return -EBUSY; 1341 1342 /* ATC cleanup */ 1343 1344 /* Verify TX hw is flushed */ 1345 bnx2x_tx_hw_flushed(bp, poll_cnt); 1346 1347 /* Wait 100ms (not adjusted according to platform) */ 1348 msleep(100); 1349 1350 /* Verify no pending pci transactions */ 1351 if (bnx2x_is_pcie_pending(bp->pdev)) 1352 BNX2X_ERR("PCIE Transactions still pending\n"); 1353 1354 /* Debug */ 1355 bnx2x_hw_enable_status(bp); 1356 1357 /* 1358 * Master enable - Due to WB DMAE writes performed before this 1359 * register is re-initialized as part of the regular function init 1360 */ 1361 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1362 1363 return 0; 1364} 1365 1366static void bnx2x_hc_int_enable(struct bnx2x *bp) 1367{ 1368 int port = BP_PORT(bp); 1369 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1370 u32 val = REG_RD(bp, addr); 1371 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1372 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1373 1374 if (msix) { 1375 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1376 HC_CONFIG_0_REG_INT_LINE_EN_0); 1377 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1378 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1379 } else if (msi) { 1380 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1381 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1382 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1383 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1384 } else { 1385 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1386 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1387 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1388 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1389 1390 if (!CHIP_IS_E1(bp)) { 1391 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1392 val, port, addr); 1393 1394 REG_WR(bp, addr, val); 1395 1396 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1397 } 1398 } 1399 1400 if (CHIP_IS_E1(bp)) 1401 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1402 1403 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", 1404 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1405 1406 REG_WR(bp, addr, val); 1407 /* 1408 * Ensure that HC_CONFIG is written before leading/trailing edge config 1409 */ 1410 mmiowb(); 1411 barrier(); 1412 1413 if (!CHIP_IS_E1(bp)) { 1414 /* init leading/trailing edge */ 1415 if (IS_MF(bp)) { 1416 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1417 if (bp->port.pmf) 1418 /* enable nig and gpio3 attention */ 1419 val |= 0x1100; 1420 } else 1421 val = 0xffff; 1422 1423 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1424 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1425 } 1426 1427 /* Make sure that interrupts are indeed enabled from here on */ 1428 mmiowb(); 1429} 1430 1431static void bnx2x_igu_int_enable(struct bnx2x *bp) 1432{ 1433 u32 val; 1434 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1435 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1436 1437 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1438 1439 if (msix) { 1440 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1441 IGU_PF_CONF_SINGLE_ISR_EN); 1442 val |= (IGU_PF_CONF_FUNC_EN | 1443 IGU_PF_CONF_MSI_MSIX_EN | 1444 IGU_PF_CONF_ATTN_BIT_EN); 1445 } else if (msi) { 1446 val &= ~IGU_PF_CONF_INT_LINE_EN; 1447 val |= (IGU_PF_CONF_FUNC_EN | 1448 IGU_PF_CONF_MSI_MSIX_EN | 1449 IGU_PF_CONF_ATTN_BIT_EN | 1450 IGU_PF_CONF_SINGLE_ISR_EN); 1451 } else { 1452 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1453 val |= (IGU_PF_CONF_FUNC_EN | 1454 IGU_PF_CONF_INT_LINE_EN | 1455 IGU_PF_CONF_ATTN_BIT_EN | 1456 IGU_PF_CONF_SINGLE_ISR_EN); 1457 } 1458 1459 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n", 1460 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1461 1462 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1463 1464 barrier(); 1465 1466 /* init leading/trailing edge */ 1467 if (IS_MF(bp)) { 1468 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1469 if (bp->port.pmf) 1470 /* enable nig and gpio3 attention */ 1471 val |= 0x1100; 1472 } else 1473 val = 0xffff; 1474 1475 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1476 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1477 1478 /* Make sure that interrupts are indeed enabled from here on */ 1479 mmiowb(); 1480} 1481 1482void bnx2x_int_enable(struct bnx2x *bp) 1483{ 1484 if (bp->common.int_block == INT_BLOCK_HC) 1485 bnx2x_hc_int_enable(bp); 1486 else 1487 bnx2x_igu_int_enable(bp); 1488} 1489 1490static void bnx2x_hc_int_disable(struct bnx2x *bp) 1491{ 1492 int port = BP_PORT(bp); 1493 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1494 u32 val = REG_RD(bp, addr); 1495 1496 /* 1497 * in E1 we must use only PCI configuration space to disable 1498 * MSI/MSIX capablility 1499 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 1500 */ 1501 if (CHIP_IS_E1(bp)) { 1502 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 1503 * Use mask register to prevent from HC sending interrupts 1504 * after we exit the function 1505 */ 1506 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 1507 1508 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1509 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1510 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1511 } else 1512 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1513 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1514 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1515 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1516 1517 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1518 val, port, addr); 1519 1520 /* flush all outstanding writes */ 1521 mmiowb(); 1522 1523 REG_WR(bp, addr, val); 1524 if (REG_RD(bp, addr) != val) 1525 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1526} 1527 1528static void bnx2x_igu_int_disable(struct bnx2x *bp) 1529{ 1530 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1531 1532 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 1533 IGU_PF_CONF_INT_LINE_EN | 1534 IGU_PF_CONF_ATTN_BIT_EN); 1535 1536 DP(NETIF_MSG_INTR, "write %x to IGU\n", val); 1537 1538 /* flush all outstanding writes */ 1539 mmiowb(); 1540 1541 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1542 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 1543 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1544} 1545 1546void bnx2x_int_disable(struct bnx2x *bp) 1547{ 1548 if (bp->common.int_block == INT_BLOCK_HC) 1549 bnx2x_hc_int_disable(bp); 1550 else 1551 bnx2x_igu_int_disable(bp); 1552} 1553 1554void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1555{ 1556 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1557 int i, offset; 1558 1559 if (disable_hw) 1560 /* prevent the HW from sending interrupts */ 1561 bnx2x_int_disable(bp); 1562 1563 /* make sure all ISRs are done */ 1564 if (msix) { 1565 synchronize_irq(bp->msix_table[0].vector); 1566 offset = 1; 1567#ifdef BCM_CNIC 1568 offset++; 1569#endif 1570 for_each_eth_queue(bp, i) 1571 synchronize_irq(bp->msix_table[offset++].vector); 1572 } else 1573 synchronize_irq(bp->pdev->irq); 1574 1575 /* make sure sp_task is not running */ 1576 cancel_delayed_work(&bp->sp_task); 1577 cancel_delayed_work(&bp->period_task); 1578 flush_workqueue(bnx2x_wq); 1579} 1580 1581/* fast path */ 1582 1583/* 1584 * General service functions 1585 */ 1586 1587/* Return true if succeeded to acquire the lock */ 1588static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1589{ 1590 u32 lock_status; 1591 u32 resource_bit = (1 << resource); 1592 int func = BP_FUNC(bp); 1593 u32 hw_lock_control_reg; 1594 1595 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource); 1596 1597 /* Validating that the resource is within range */ 1598 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1599 DP(NETIF_MSG_HW, 1600 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1601 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1602 return false; 1603 } 1604 1605 if (func <= 5) 1606 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1607 else 1608 hw_lock_control_reg = 1609 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1610 1611 /* Try to acquire the lock */ 1612 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1613 lock_status = REG_RD(bp, hw_lock_control_reg); 1614 if (lock_status & resource_bit) 1615 return true; 1616 1617 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource); 1618 return false; 1619} 1620 1621/** 1622 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1623 * 1624 * @bp: driver handle 1625 * 1626 * Returns the recovery leader resource id according to the engine this function 1627 * belongs to. Currently only only 2 engines is supported. 1628 */ 1629static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1630{ 1631 if (BP_PATH(bp)) 1632 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1633 else 1634 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1635} 1636 1637/** 1638 * bnx2x_trylock_leader_lock- try to aquire a leader lock. 1639 * 1640 * @bp: driver handle 1641 * 1642 * Tries to aquire a leader lock for cuurent engine. 1643 */ 1644static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1645{ 1646 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1647} 1648 1649#ifdef BCM_CNIC 1650static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1651#endif 1652 1653void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1654{ 1655 struct bnx2x *bp = fp->bp; 1656 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1657 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1658 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1659 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj; 1660 1661 DP(BNX2X_MSG_SP, 1662 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1663 fp->index, cid, command, bp->state, 1664 rr_cqe->ramrod_cqe.ramrod_type); 1665 1666 switch (command) { 1667 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1668 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1669 drv_cmd = BNX2X_Q_CMD_UPDATE; 1670 break; 1671 1672 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1673 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1674 drv_cmd = BNX2X_Q_CMD_SETUP; 1675 break; 1676 1677 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1678 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1679 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1680 break; 1681 1682 case (RAMROD_CMD_ID_ETH_HALT): 1683 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1684 drv_cmd = BNX2X_Q_CMD_HALT; 1685 break; 1686 1687 case (RAMROD_CMD_ID_ETH_TERMINATE): 1688 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); 1689 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1690 break; 1691 1692 case (RAMROD_CMD_ID_ETH_EMPTY): 1693 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1694 drv_cmd = BNX2X_Q_CMD_EMPTY; 1695 break; 1696 1697 default: 1698 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1699 command, fp->index); 1700 return; 1701 } 1702 1703 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1704 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1705 /* q_obj->complete_cmd() failure means that this was 1706 * an unexpected completion. 1707 * 1708 * In this case we don't want to increase the bp->spq_left 1709 * because apparently we haven't sent this command the first 1710 * place. 1711 */ 1712#ifdef BNX2X_STOP_ON_ERROR 1713 bnx2x_panic(); 1714#else 1715 return; 1716#endif 1717 1718 smp_mb__before_atomic_inc(); 1719 atomic_inc(&bp->cq_spq_left); 1720 /* push the change in bp->spq_left and towards the memory */ 1721 smp_mb__after_atomic_inc(); 1722 1723 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1724 1725 return; 1726} 1727 1728void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 1729 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) 1730{ 1731 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; 1732 1733 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, 1734 start); 1735} 1736 1737irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1738{ 1739 struct bnx2x *bp = netdev_priv(dev_instance); 1740 u16 status = bnx2x_ack_int(bp); 1741 u16 mask; 1742 int i; 1743 u8 cos; 1744 1745 /* Return here if interrupt is shared and it's not for us */ 1746 if (unlikely(status == 0)) { 1747 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1748 return IRQ_NONE; 1749 } 1750 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1751 1752#ifdef BNX2X_STOP_ON_ERROR 1753 if (unlikely(bp->panic)) 1754 return IRQ_HANDLED; 1755#endif 1756 1757 for_each_eth_queue(bp, i) { 1758 struct bnx2x_fastpath *fp = &bp->fp[i]; 1759 1760 mask = 0x2 << (fp->index + CNIC_PRESENT); 1761 if (status & mask) { 1762 /* Handle Rx or Tx according to SB id */ 1763 prefetch(fp->rx_cons_sb); 1764 for_each_cos_in_tx_queue(fp, cos) 1765 prefetch(fp->txdata[cos].tx_cons_sb); 1766 prefetch(&fp->sb_running_index[SM_RX_ID]); 1767 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 1768 status &= ~mask; 1769 } 1770 } 1771 1772#ifdef BCM_CNIC 1773 mask = 0x2; 1774 if (status & (mask | 0x1)) { 1775 struct cnic_ops *c_ops = NULL; 1776 1777 if (likely(bp->state == BNX2X_STATE_OPEN)) { 1778 rcu_read_lock(); 1779 c_ops = rcu_dereference(bp->cnic_ops); 1780 if (c_ops) 1781 c_ops->cnic_handler(bp->cnic_data, NULL); 1782 rcu_read_unlock(); 1783 } 1784 1785 status &= ~mask; 1786 } 1787#endif 1788 1789 if (unlikely(status & 0x1)) { 1790 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1791 1792 status &= ~0x1; 1793 if (!status) 1794 return IRQ_HANDLED; 1795 } 1796 1797 if (unlikely(status)) 1798 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1799 status); 1800 1801 return IRQ_HANDLED; 1802} 1803 1804/* Link */ 1805 1806/* 1807 * General service functions 1808 */ 1809 1810int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 1811{ 1812 u32 lock_status; 1813 u32 resource_bit = (1 << resource); 1814 int func = BP_FUNC(bp); 1815 u32 hw_lock_control_reg; 1816 int cnt; 1817 1818 /* Validating that the resource is within range */ 1819 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1820 DP(NETIF_MSG_HW, 1821 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1822 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1823 return -EINVAL; 1824 } 1825 1826 if (func <= 5) { 1827 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1828 } else { 1829 hw_lock_control_reg = 1830 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1831 } 1832 1833 /* Validating that the resource is not already taken */ 1834 lock_status = REG_RD(bp, hw_lock_control_reg); 1835 if (lock_status & resource_bit) { 1836 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1837 lock_status, resource_bit); 1838 return -EEXIST; 1839 } 1840 1841 /* Try for 5 second every 5ms */ 1842 for (cnt = 0; cnt < 1000; cnt++) { 1843 /* Try to acquire the lock */ 1844 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1845 lock_status = REG_RD(bp, hw_lock_control_reg); 1846 if (lock_status & resource_bit) 1847 return 0; 1848 1849 msleep(5); 1850 } 1851 DP(NETIF_MSG_HW, "Timeout\n"); 1852 return -EAGAIN; 1853} 1854 1855int bnx2x_release_leader_lock(struct bnx2x *bp) 1856{ 1857 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1858} 1859 1860int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 1861{ 1862 u32 lock_status; 1863 u32 resource_bit = (1 << resource); 1864 int func = BP_FUNC(bp); 1865 u32 hw_lock_control_reg; 1866 1867 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource); 1868 1869 /* Validating that the resource is within range */ 1870 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1871 DP(NETIF_MSG_HW, 1872 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1873 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1874 return -EINVAL; 1875 } 1876 1877 if (func <= 5) { 1878 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1879 } else { 1880 hw_lock_control_reg = 1881 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1882 } 1883 1884 /* Validating that the resource is currently taken */ 1885 lock_status = REG_RD(bp, hw_lock_control_reg); 1886 if (!(lock_status & resource_bit)) { 1887 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1888 lock_status, resource_bit); 1889 return -EFAULT; 1890 } 1891 1892 REG_WR(bp, hw_lock_control_reg, resource_bit); 1893 return 0; 1894} 1895 1896 1897int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 1898{ 1899 /* The GPIO should be swapped if swap register is set and active */ 1900 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1901 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1902 int gpio_shift = gpio_num + 1903 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1904 u32 gpio_mask = (1 << gpio_shift); 1905 u32 gpio_reg; 1906 int value; 1907 1908 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1909 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1910 return -EINVAL; 1911 } 1912 1913 /* read GPIO value */ 1914 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1915 1916 /* get the requested pin value */ 1917 if ((gpio_reg & gpio_mask) == gpio_mask) 1918 value = 1; 1919 else 1920 value = 0; 1921 1922 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); 1923 1924 return value; 1925} 1926 1927int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 1928{ 1929 /* The GPIO should be swapped if swap register is set and active */ 1930 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1931 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1932 int gpio_shift = gpio_num + 1933 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1934 u32 gpio_mask = (1 << gpio_shift); 1935 u32 gpio_reg; 1936 1937 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1938 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1939 return -EINVAL; 1940 } 1941 1942 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1943 /* read GPIO and mask except the float bits */ 1944 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 1945 1946 switch (mode) { 1947 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1948 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n", 1949 gpio_num, gpio_shift); 1950 /* clear FLOAT and set CLR */ 1951 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1952 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 1953 break; 1954 1955 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 1956 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n", 1957 gpio_num, gpio_shift); 1958 /* clear FLOAT and set SET */ 1959 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1960 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 1961 break; 1962 1963 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 1964 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", 1965 gpio_num, gpio_shift); 1966 /* set FLOAT */ 1967 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1968 break; 1969 1970 default: 1971 break; 1972 } 1973 1974 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 1975 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1976 1977 return 0; 1978} 1979 1980int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 1981{ 1982 u32 gpio_reg = 0; 1983 int rc = 0; 1984 1985 /* Any port swapping should be handled by caller. */ 1986 1987 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1988 /* read GPIO and mask except the float bits */ 1989 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1990 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 1991 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 1992 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 1993 1994 switch (mode) { 1995 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1996 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 1997 /* set CLR */ 1998 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 1999 break; 2000 2001 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2002 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 2003 /* set SET */ 2004 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2005 break; 2006 2007 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2008 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2009 /* set FLOAT */ 2010 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2011 break; 2012 2013 default: 2014 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2015 rc = -EINVAL; 2016 break; 2017 } 2018 2019 if (rc == 0) 2020 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2021 2022 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2023 2024 return rc; 2025} 2026 2027int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2028{ 2029 /* The GPIO should be swapped if swap register is set and active */ 2030 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2031 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2032 int gpio_shift = gpio_num + 2033 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2034 u32 gpio_mask = (1 << gpio_shift); 2035 u32 gpio_reg; 2036 2037 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2038 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2039 return -EINVAL; 2040 } 2041 2042 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2043 /* read GPIO int */ 2044 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2045 2046 switch (mode) { 2047 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2048 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> " 2049 "output low\n", gpio_num, gpio_shift); 2050 /* clear SET and set CLR */ 2051 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2052 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2053 break; 2054 2055 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2056 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> " 2057 "output high\n", gpio_num, gpio_shift); 2058 /* clear CLR and set SET */ 2059 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2060 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2061 break; 2062 2063 default: 2064 break; 2065 } 2066 2067 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2068 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2069 2070 return 0; 2071} 2072 2073static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) 2074{ 2075 u32 spio_mask = (1 << spio_num); 2076 u32 spio_reg; 2077 2078 if ((spio_num < MISC_REGISTERS_SPIO_4) || 2079 (spio_num > MISC_REGISTERS_SPIO_7)) { 2080 BNX2X_ERR("Invalid SPIO %d\n", spio_num); 2081 return -EINVAL; 2082 } 2083 2084 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2085 /* read SPIO and mask except the float bits */ 2086 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); 2087 2088 switch (mode) { 2089 case MISC_REGISTERS_SPIO_OUTPUT_LOW: 2090 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); 2091 /* clear FLOAT and set CLR */ 2092 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2093 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); 2094 break; 2095 2096 case MISC_REGISTERS_SPIO_OUTPUT_HIGH: 2097 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); 2098 /* clear FLOAT and set SET */ 2099 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2100 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); 2101 break; 2102 2103 case MISC_REGISTERS_SPIO_INPUT_HI_Z: 2104 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num); 2105 /* set FLOAT */ 2106 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2107 break; 2108 2109 default: 2110 break; 2111 } 2112 2113 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2114 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2115 2116 return 0; 2117} 2118 2119void bnx2x_calc_fc_adv(struct bnx2x *bp) 2120{ 2121 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2122 switch (bp->link_vars.ieee_fc & 2123 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2124 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 2125 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2126 ADVERTISED_Pause); 2127 break; 2128 2129 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2130 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2131 ADVERTISED_Pause); 2132 break; 2133 2134 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2135 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2136 break; 2137 2138 default: 2139 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2140 ADVERTISED_Pause); 2141 break; 2142 } 2143} 2144 2145u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2146{ 2147 if (!BP_NOMCP(bp)) { 2148 u8 rc; 2149 int cfx_idx = bnx2x_get_link_cfg_idx(bp); 2150 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2151 /* 2152 * Initialize link parameters structure variables 2153 * It is recommended to turn off RX FC for jumbo frames 2154 * for better performance 2155 */ 2156 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2157 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2158 else 2159 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2160 2161 bnx2x_acquire_phy_lock(bp); 2162 2163 if (load_mode == LOAD_DIAG) { 2164 struct link_params *lp = &bp->link_params; 2165 lp->loopback_mode = LOOPBACK_XGXS; 2166 /* do PHY loopback at 10G speed, if possible */ 2167 if (lp->req_line_speed[cfx_idx] < SPEED_10000) { 2168 if (lp->speed_cap_mask[cfx_idx] & 2169 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2170 lp->req_line_speed[cfx_idx] = 2171 SPEED_10000; 2172 else 2173 lp->req_line_speed[cfx_idx] = 2174 SPEED_1000; 2175 } 2176 } 2177 2178 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2179 2180 bnx2x_release_phy_lock(bp); 2181 2182 bnx2x_calc_fc_adv(bp); 2183 2184 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { 2185 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2186 bnx2x_link_report(bp); 2187 } else 2188 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2189 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2190 return rc; 2191 } 2192 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2193 return -EINVAL; 2194} 2195 2196void bnx2x_link_set(struct bnx2x *bp) 2197{ 2198 if (!BP_NOMCP(bp)) { 2199 bnx2x_acquire_phy_lock(bp); 2200 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2201 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2202 bnx2x_release_phy_lock(bp); 2203 2204 bnx2x_calc_fc_adv(bp); 2205 } else 2206 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2207} 2208 2209static void bnx2x__link_reset(struct bnx2x *bp) 2210{ 2211 if (!BP_NOMCP(bp)) { 2212 bnx2x_acquire_phy_lock(bp); 2213 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2214 bnx2x_release_phy_lock(bp); 2215 } else 2216 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2217} 2218 2219u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2220{ 2221 u8 rc = 0; 2222 2223 if (!BP_NOMCP(bp)) { 2224 bnx2x_acquire_phy_lock(bp); 2225 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2226 is_serdes); 2227 bnx2x_release_phy_lock(bp); 2228 } else 2229 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2230 2231 return rc; 2232} 2233 2234static void bnx2x_init_port_minmax(struct bnx2x *bp) 2235{ 2236 u32 r_param = bp->link_vars.line_speed / 8; 2237 u32 fair_periodic_timeout_usec; 2238 u32 t_fair; 2239 2240 memset(&(bp->cmng.rs_vars), 0, 2241 sizeof(struct rate_shaping_vars_per_port)); 2242 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port)); 2243 2244 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ 2245 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4; 2246 2247 /* this is the threshold below which no timer arming will occur 2248 1.25 coefficient is for the threshold to be a little bigger 2249 than the real time, to compensate for timer in-accuracy */ 2250 bp->cmng.rs_vars.rs_threshold = 2251 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; 2252 2253 /* resolution of fairness timer */ 2254 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; 2255 /* for 10G it is 1000usec. for 1G it is 10000usec. */ 2256 t_fair = T_FAIR_COEF / bp->link_vars.line_speed; 2257 2258 /* this is the threshold below which we won't arm the timer anymore */ 2259 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES; 2260 2261 /* we multiply by 1e3/8 to get bytes/msec. 2262 We don't want the credits to pass a credit 2263 of the t_fair*FAIR_MEM (algorithm resolution) */ 2264 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM; 2265 /* since each tick is 4 usec */ 2266 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4; 2267} 2268 2269/* Calculates the sum of vn_min_rates. 2270 It's needed for further normalizing of the min_rates. 2271 Returns: 2272 sum of vn_min_rates. 2273 or 2274 0 - if all the min_rates are 0. 2275 In the later case fainess algorithm should be deactivated. 2276 If not all min_rates are zero then those that are zeroes will be set to 1. 2277 */ 2278static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) 2279{ 2280 int all_zero = 1; 2281 int vn; 2282 2283 bp->vn_weight_sum = 0; 2284 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2285 u32 vn_cfg = bp->mf_config[vn]; 2286 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2287 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2288 2289 /* Skip hidden vns */ 2290 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2291 continue; 2292 2293 /* If min rate is zero - set it to 1 */ 2294 if (!vn_min_rate) 2295 vn_min_rate = DEF_MIN_RATE; 2296 else 2297 all_zero = 0; 2298 2299 bp->vn_weight_sum += vn_min_rate; 2300 } 2301 2302 /* if ETS or all min rates are zeros - disable fairness */ 2303 if (BNX2X_IS_ETS_ENABLED(bp)) { 2304 bp->cmng.flags.cmng_enables &= 2305 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2306 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2307 } else if (all_zero) { 2308 bp->cmng.flags.cmng_enables &= 2309 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2310 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2311 " fairness will be disabled\n"); 2312 } else 2313 bp->cmng.flags.cmng_enables |= 2314 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2315} 2316 2317static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) 2318{ 2319 struct rate_shaping_vars_per_vn m_rs_vn; 2320 struct fairness_vars_per_vn m_fair_vn; 2321 u32 vn_cfg = bp->mf_config[vn]; 2322 int func = func_by_vn(bp, vn); 2323 u16 vn_min_rate, vn_max_rate; 2324 int i; 2325 2326 /* If function is hidden - set min and max to zeroes */ 2327 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 2328 vn_min_rate = 0; 2329 vn_max_rate = 0; 2330 2331 } else { 2332 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2333 2334 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2335 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2336 /* If fairness is enabled (not all min rates are zeroes) and 2337 if current min rate is zero - set it to 1. 2338 This is a requirement of the algorithm. */ 2339 if (bp->vn_weight_sum && (vn_min_rate == 0)) 2340 vn_min_rate = DEF_MIN_RATE; 2341 2342 if (IS_MF_SI(bp)) 2343 /* maxCfg in percents of linkspeed */ 2344 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2345 else 2346 /* maxCfg is absolute in 100Mb units */ 2347 vn_max_rate = maxCfg * 100; 2348 } 2349 2350 DP(NETIF_MSG_IFUP, 2351 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n", 2352 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); 2353 2354 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn)); 2355 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); 2356 2357 /* global vn counter - maximal Mbps for this vn */ 2358 m_rs_vn.vn_counter.rate = vn_max_rate; 2359 2360 /* quota - number of bytes transmitted in this period */ 2361 m_rs_vn.vn_counter.quota = 2362 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8; 2363 2364 if (bp->vn_weight_sum) { 2365 /* credit for each period of the fairness algorithm: 2366 number of bytes in T_FAIR (the vn share the port rate). 2367 vn_weight_sum should not be larger than 10000, thus 2368 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater 2369 than zero */ 2370 m_fair_vn.vn_credit_delta = 2371 max_t(u32, (vn_min_rate * (T_FAIR_COEF / 2372 (8 * bp->vn_weight_sum))), 2373 (bp->cmng.fair_vars.fair_threshold + 2374 MIN_ABOVE_THRESH)); 2375 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n", 2376 m_fair_vn.vn_credit_delta); 2377 } 2378 2379 /* Store it to internal memory */ 2380 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++) 2381 REG_WR(bp, BAR_XSTRORM_INTMEM + 2382 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4, 2383 ((u32 *)(&m_rs_vn))[i]); 2384 2385 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++) 2386 REG_WR(bp, BAR_XSTRORM_INTMEM + 2387 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4, 2388 ((u32 *)(&m_fair_vn))[i]); 2389} 2390 2391static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2392{ 2393 if (CHIP_REV_IS_SLOW(bp)) 2394 return CMNG_FNS_NONE; 2395 if (IS_MF(bp)) 2396 return CMNG_FNS_MINMAX; 2397 2398 return CMNG_FNS_NONE; 2399} 2400 2401void bnx2x_read_mf_cfg(struct bnx2x *bp) 2402{ 2403 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2404 2405 if (BP_NOMCP(bp)) 2406 return; /* what should be the default bvalue in this case */ 2407 2408 /* For 2 port configuration the absolute function number formula 2409 * is: 2410 * abs_func = 2 * vn + BP_PORT + BP_PATH 2411 * 2412 * and there are 4 functions per port 2413 * 2414 * For 4 port configuration it is 2415 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2416 * 2417 * and there are 2 functions per port 2418 */ 2419 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2420 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2421 2422 if (func >= E1H_FUNC_MAX) 2423 break; 2424 2425 bp->mf_config[vn] = 2426 MF_CFG_RD(bp, func_mf_config[func].config); 2427 } 2428} 2429 2430static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2431{ 2432 2433 if (cmng_type == CMNG_FNS_MINMAX) { 2434 int vn; 2435 2436 /* clear cmng_enables */ 2437 bp->cmng.flags.cmng_enables = 0; 2438 2439 /* read mf conf from shmem */ 2440 if (read_cfg) 2441 bnx2x_read_mf_cfg(bp); 2442 2443 /* Init rate shaping and fairness contexts */ 2444 bnx2x_init_port_minmax(bp); 2445 2446 /* vn_weight_sum and enable fairness if not 0 */ 2447 bnx2x_calc_vn_weight_sum(bp); 2448 2449 /* calculate and set min-max rate for each vn */ 2450 if (bp->port.pmf) 2451 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) 2452 bnx2x_init_vn_minmax(bp, vn); 2453 2454 /* always enable rate shaping and fairness */ 2455 bp->cmng.flags.cmng_enables |= 2456 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2457 if (!bp->vn_weight_sum) 2458 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2459 " fairness will be disabled\n"); 2460 return; 2461 } 2462 2463 /* rate shaping and fairness are disabled */ 2464 DP(NETIF_MSG_IFUP, 2465 "rate shaping and fairness are disabled\n"); 2466} 2467 2468/* This function is called upon link interrupt */ 2469static void bnx2x_link_attn(struct bnx2x *bp) 2470{ 2471 /* Make sure that we are synced with the current statistics */ 2472 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2473 2474 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2475 2476 if (bp->link_vars.link_up) { 2477 2478 /* dropless flow control */ 2479 if (!CHIP_IS_E1(bp) && bp->dropless_fc) { 2480 int port = BP_PORT(bp); 2481 u32 pause_enabled = 0; 2482 2483 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2484 pause_enabled = 1; 2485 2486 REG_WR(bp, BAR_USTRORM_INTMEM + 2487 USTORM_ETH_PAUSE_ENABLED_OFFSET(port), 2488 pause_enabled); 2489 } 2490 2491 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2492 struct host_port_stats *pstats; 2493 2494 pstats = bnx2x_sp(bp, port_stats); 2495 /* reset old mac stats */ 2496 memset(&(pstats->mac_stx[0]), 0, 2497 sizeof(struct mac_stx)); 2498 } 2499 if (bp->state == BNX2X_STATE_OPEN) 2500 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2501 } 2502 2503 if (bp->link_vars.link_up && bp->link_vars.line_speed) { 2504 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2505 2506 if (cmng_fns != CMNG_FNS_NONE) { 2507 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2508 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2509 } else 2510 /* rate shaping and fairness are disabled */ 2511 DP(NETIF_MSG_IFUP, 2512 "single function mode without fairness\n"); 2513 } 2514 2515 __bnx2x_link_report(bp); 2516 2517 if (IS_MF(bp)) 2518 bnx2x_link_sync_notify(bp); 2519} 2520 2521void bnx2x__link_status_update(struct bnx2x *bp) 2522{ 2523 if (bp->state != BNX2X_STATE_OPEN) 2524 return; 2525 2526 /* read updated dcb configuration */ 2527 bnx2x_dcbx_pmf_update(bp); 2528 2529 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2530 2531 if (bp->link_vars.link_up) 2532 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2533 else 2534 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2535 2536 /* indicate link status */ 2537 bnx2x_link_report(bp); 2538} 2539 2540static void bnx2x_pmf_update(struct bnx2x *bp) 2541{ 2542 int port = BP_PORT(bp); 2543 u32 val; 2544 2545 bp->port.pmf = 1; 2546 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf); 2547 2548 /* 2549 * We need the mb() to ensure the ordering between the writing to 2550 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2551 */ 2552 smp_mb(); 2553 2554 /* queue a periodic task */ 2555 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2556 2557 bnx2x_dcbx_pmf_update(bp); 2558 2559 /* enable nig attention */ 2560 val = (0xff0f | (1 << (BP_VN(bp) + 4))); 2561 if (bp->common.int_block == INT_BLOCK_HC) { 2562 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 2563 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 2564 } else if (!CHIP_IS_E1x(bp)) { 2565 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 2566 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 2567 } 2568 2569 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 2570} 2571 2572/* end of Link */ 2573 2574/* slow path */ 2575 2576/* 2577 * General service functions 2578 */ 2579 2580/* send the MCP a request, block until there is a reply */ 2581u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 2582{ 2583 int mb_idx = BP_FW_MB_IDX(bp); 2584 u32 seq; 2585 u32 rc = 0; 2586 u32 cnt = 1; 2587 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 2588 2589 mutex_lock(&bp->fw_mb_mutex); 2590 seq = ++bp->fw_seq; 2591 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 2592 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 2593 2594 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 2595 (command | seq), param); 2596 2597 do { 2598 /* let the FW do it's magic ... */ 2599 msleep(delay); 2600 2601 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 2602 2603 /* Give the FW up to 5 second (500*10ms) */ 2604 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2605 2606 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 2607 cnt*delay, rc, seq); 2608 2609 /* is this a reply to our command? */ 2610 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 2611 rc &= FW_MSG_CODE_MASK; 2612 else { 2613 /* FW BUG! */ 2614 BNX2X_ERR("FW failed to respond!\n"); 2615 bnx2x_fw_dump(bp); 2616 rc = 0; 2617 } 2618 mutex_unlock(&bp->fw_mb_mutex); 2619 2620 return rc; 2621} 2622 2623 2624void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 2625{ 2626 if (CHIP_IS_E1x(bp)) { 2627 struct tstorm_eth_function_common_config tcfg = {0}; 2628 2629 storm_memset_func_cfg(bp, &tcfg, p->func_id); 2630 } 2631 2632 /* Enable the function in the FW */ 2633 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 2634 storm_memset_func_en(bp, p->func_id, 1); 2635 2636 /* spq */ 2637 if (p->func_flgs & FUNC_FLG_SPQ) { 2638 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 2639 REG_WR(bp, XSEM_REG_FAST_MEMORY + 2640 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 2641 } 2642} 2643 2644/** 2645 * bnx2x_get_tx_only_flags - Return common flags 2646 * 2647 * @bp device handle 2648 * @fp queue handle 2649 * @zero_stats TRUE if statistics zeroing is needed 2650 * 2651 * Return the flags that are common for the Tx-only and not normal connections. 2652 */ 2653static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 2654 struct bnx2x_fastpath *fp, 2655 bool zero_stats) 2656{ 2657 unsigned long flags = 0; 2658 2659 /* PF driver will always initialize the Queue to an ACTIVE state */ 2660 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 2661 2662 /* tx only connections collect statistics (on the same index as the 2663 * parent connection). The statistics are zeroed when the parent 2664 * connection is initialized. 2665 */ 2666 2667 __set_bit(BNX2X_Q_FLG_STATS, &flags); 2668 if (zero_stats) 2669 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 2670 2671 2672 return flags; 2673} 2674 2675static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 2676 struct bnx2x_fastpath *fp, 2677 bool leading) 2678{ 2679 unsigned long flags = 0; 2680 2681 /* calculate other queue flags */ 2682 if (IS_MF_SD(bp)) 2683 __set_bit(BNX2X_Q_FLG_OV, &flags); 2684 2685 if (IS_FCOE_FP(fp)) 2686 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 2687 2688 if (!fp->disable_tpa) { 2689 __set_bit(BNX2X_Q_FLG_TPA, &flags); 2690 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 2691 } 2692 2693 if (leading) { 2694 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 2695 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 2696 } 2697 2698 /* Always set HW VLAN stripping */ 2699 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 2700 2701 2702 return flags | bnx2x_get_common_flags(bp, fp, true); 2703} 2704 2705static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 2706 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 2707 u8 cos) 2708{ 2709 gen_init->stat_id = bnx2x_stats_id(fp); 2710 gen_init->spcl_id = fp->cl_id; 2711 2712 /* Always use mini-jumbo MTU for FCoE L2 ring */ 2713 if (IS_FCOE_FP(fp)) 2714 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 2715 else 2716 gen_init->mtu = bp->dev->mtu; 2717 2718 gen_init->cos = cos; 2719} 2720 2721static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 2722 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 2723 struct bnx2x_rxq_setup_params *rxq_init) 2724{ 2725 u8 max_sge = 0; 2726 u16 sge_sz = 0; 2727 u16 tpa_agg_size = 0; 2728 2729 if (!fp->disable_tpa) { 2730 pause->sge_th_lo = SGE_TH_LO(bp); 2731 pause->sge_th_hi = SGE_TH_HI(bp); 2732 2733 /* validate SGE ring has enough to cross high threshold */ 2734 WARN_ON(bp->dropless_fc && 2735 pause->sge_th_hi + FW_PREFETCH_CNT > 2736 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); 2737 2738 tpa_agg_size = min_t(u32, 2739 (min_t(u32, 8, MAX_SKB_FRAGS) * 2740 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); 2741 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 2742 SGE_PAGE_SHIFT; 2743 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 2744 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 2745 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, 2746 0xffff); 2747 } 2748 2749 /* pause - not for e1 */ 2750 if (!CHIP_IS_E1(bp)) { 2751 pause->bd_th_lo = BD_TH_LO(bp); 2752 pause->bd_th_hi = BD_TH_HI(bp); 2753 2754 pause->rcq_th_lo = RCQ_TH_LO(bp); 2755 pause->rcq_th_hi = RCQ_TH_HI(bp); 2756 /* 2757 * validate that rings have enough entries to cross 2758 * high thresholds 2759 */ 2760 WARN_ON(bp->dropless_fc && 2761 pause->bd_th_hi + FW_PREFETCH_CNT > 2762 bp->rx_ring_size); 2763 WARN_ON(bp->dropless_fc && 2764 pause->rcq_th_hi + FW_PREFETCH_CNT > 2765 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); 2766 2767 pause->pri_map = 1; 2768 } 2769 2770 /* rxq setup */ 2771 rxq_init->dscr_map = fp->rx_desc_mapping; 2772 rxq_init->sge_map = fp->rx_sge_mapping; 2773 rxq_init->rcq_map = fp->rx_comp_mapping; 2774 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 2775 2776 /* This should be a maximum number of data bytes that may be 2777 * placed on the BD (not including paddings). 2778 */ 2779 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - 2780 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; 2781 2782 rxq_init->cl_qzone_id = fp->cl_qzone_id; 2783 rxq_init->tpa_agg_sz = tpa_agg_size; 2784 rxq_init->sge_buf_sz = sge_sz; 2785 rxq_init->max_sges_pkt = max_sge; 2786 rxq_init->rss_engine_id = BP_FUNC(bp); 2787 2788 /* Maximum number or simultaneous TPA aggregation for this Queue. 2789 * 2790 * For PF Clients it should be the maximum avaliable number. 2791 * VF driver(s) may want to define it to a smaller value. 2792 */ 2793 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); 2794 2795 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 2796 rxq_init->fw_sb_id = fp->fw_sb_id; 2797 2798 if (IS_FCOE_FP(fp)) 2799 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 2800 else 2801 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 2802} 2803 2804static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 2805 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 2806 u8 cos) 2807{ 2808 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping; 2809 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 2810 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 2811 txq_init->fw_sb_id = fp->fw_sb_id; 2812 2813 /* 2814 * set the tss leading client id for TX classfication == 2815 * leading RSS client id 2816 */ 2817 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 2818 2819 if (IS_FCOE_FP(fp)) { 2820 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 2821 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 2822 } 2823} 2824 2825static void bnx2x_pf_init(struct bnx2x *bp) 2826{ 2827 struct bnx2x_func_init_params func_init = {0}; 2828 struct event_ring_data eq_data = { {0} }; 2829 u16 flags; 2830 2831 if (!CHIP_IS_E1x(bp)) { 2832 /* reset IGU PF statistics: MSIX + ATTN */ 2833 /* PF */ 2834 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2835 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2836 (CHIP_MODE_IS_4_PORT(bp) ? 2837 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2838 /* ATTN */ 2839 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2840 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2841 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 2842 (CHIP_MODE_IS_4_PORT(bp) ? 2843 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2844 } 2845 2846 /* function setup flags */ 2847 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 2848 2849 /* This flag is relevant for E1x only. 2850 * E2 doesn't have a TPA configuration in a function level. 2851 */ 2852 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; 2853 2854 func_init.func_flgs = flags; 2855 func_init.pf_id = BP_FUNC(bp); 2856 func_init.func_id = BP_FUNC(bp); 2857 func_init.spq_map = bp->spq_mapping; 2858 func_init.spq_prod = bp->spq_prod_idx; 2859 2860 bnx2x_func_init(bp, &func_init); 2861 2862 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 2863 2864 /* 2865 * Congestion management values depend on the link rate 2866 * There is no active link so initial link rate is set to 10 Gbps. 2867 * When the link comes up The congestion management values are 2868 * re-calculated according to the actual link rate. 2869 */ 2870 bp->link_vars.line_speed = SPEED_10000; 2871 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 2872 2873 /* Only the PMF sets the HW */ 2874 if (bp->port.pmf) 2875 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2876 2877 /* init Event Queue */ 2878 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 2879 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 2880 eq_data.producer = bp->eq_prod; 2881 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 2882 eq_data.sb_id = DEF_SB_ID; 2883 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 2884} 2885 2886 2887static void bnx2x_e1h_disable(struct bnx2x *bp) 2888{ 2889 int port = BP_PORT(bp); 2890 2891 bnx2x_tx_disable(bp); 2892 2893 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 2894} 2895 2896static void bnx2x_e1h_enable(struct bnx2x *bp) 2897{ 2898 int port = BP_PORT(bp); 2899 2900 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 2901 2902 /* Tx queue should be only reenabled */ 2903 netif_tx_wake_all_queues(bp->dev); 2904 2905 /* 2906 * Should not call netif_carrier_on since it will be called if the link 2907 * is up when checking for link state 2908 */ 2909} 2910 2911#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 2912 2913static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) 2914{ 2915 struct eth_stats_info *ether_stat = 2916 &bp->slowpath->drv_info_to_mcp.ether_stat; 2917 2918 /* leave last char as NULL */ 2919 memcpy(ether_stat->version, DRV_MODULE_VERSION, 2920 ETH_STAT_INFO_VERSION_LEN - 1); 2921 2922 bp->fp[0].mac_obj.get_n_elements(bp, &bp->fp[0].mac_obj, 2923 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 2924 ether_stat->mac_local); 2925 2926 ether_stat->mtu_size = bp->dev->mtu; 2927 2928 if (bp->dev->features & NETIF_F_RXCSUM) 2929 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 2930 if (bp->dev->features & NETIF_F_TSO) 2931 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 2932 ether_stat->feature_flags |= bp->common.boot_mode; 2933 2934 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; 2935 2936 ether_stat->txq_size = bp->tx_ring_size; 2937 ether_stat->rxq_size = bp->rx_ring_size; 2938} 2939 2940static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) 2941{ 2942#ifdef BCM_CNIC 2943 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 2944 struct fcoe_stats_info *fcoe_stat = 2945 &bp->slowpath->drv_info_to_mcp.fcoe_stat; 2946 2947 memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN); 2948 2949 fcoe_stat->qos_priority = 2950 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; 2951 2952 /* insert FCoE stats from ramrod response */ 2953 if (!NO_FCOE(bp)) { 2954 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = 2955 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2956 tstorm_queue_statistics; 2957 2958 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = 2959 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2960 xstorm_queue_statistics; 2961 2962 struct fcoe_statistics_params *fw_fcoe_stat = 2963 &bp->fw_stats_data->fcoe; 2964 2965 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo, 2966 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); 2967 2968 ADD_64(fcoe_stat->rx_bytes_hi, 2969 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, 2970 fcoe_stat->rx_bytes_lo, 2971 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); 2972 2973 ADD_64(fcoe_stat->rx_bytes_hi, 2974 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, 2975 fcoe_stat->rx_bytes_lo, 2976 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); 2977 2978 ADD_64(fcoe_stat->rx_bytes_hi, 2979 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, 2980 fcoe_stat->rx_bytes_lo, 2981 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); 2982 2983 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2984 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); 2985 2986 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2987 fcoe_q_tstorm_stats->rcv_ucast_pkts); 2988 2989 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2990 fcoe_q_tstorm_stats->rcv_bcast_pkts); 2991 2992 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2993 fcoe_q_tstorm_stats->rcv_mcast_pkts); 2994 2995 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo, 2996 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); 2997 2998 ADD_64(fcoe_stat->tx_bytes_hi, 2999 fcoe_q_xstorm_stats->ucast_bytes_sent.hi, 3000 fcoe_stat->tx_bytes_lo, 3001 fcoe_q_xstorm_stats->ucast_bytes_sent.lo); 3002 3003 ADD_64(fcoe_stat->tx_bytes_hi, 3004 fcoe_q_xstorm_stats->bcast_bytes_sent.hi, 3005 fcoe_stat->tx_bytes_lo, 3006 fcoe_q_xstorm_stats->bcast_bytes_sent.lo); 3007 3008 ADD_64(fcoe_stat->tx_bytes_hi, 3009 fcoe_q_xstorm_stats->mcast_bytes_sent.hi, 3010 fcoe_stat->tx_bytes_lo, 3011 fcoe_q_xstorm_stats->mcast_bytes_sent.lo); 3012 3013 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3014 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); 3015 3016 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3017 fcoe_q_xstorm_stats->ucast_pkts_sent); 3018 3019 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3020 fcoe_q_xstorm_stats->bcast_pkts_sent); 3021 3022 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3023 fcoe_q_xstorm_stats->mcast_pkts_sent); 3024 } 3025 3026 /* ask L5 driver to add data to the struct */ 3027 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); 3028#endif 3029} 3030 3031static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) 3032{ 3033#ifdef BCM_CNIC 3034 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3035 struct iscsi_stats_info *iscsi_stat = 3036 &bp->slowpath->drv_info_to_mcp.iscsi_stat; 3037 3038 memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); 3039 3040 iscsi_stat->qos_priority = 3041 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; 3042 3043 /* ask L5 driver to add data to the struct */ 3044 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); 3045#endif 3046} 3047 3048/* called due to MCP event (on pmf): 3049 * reread new bandwidth configuration 3050 * configure FW 3051 * notify others function about the change 3052 */ 3053static inline void bnx2x_config_mf_bw(struct bnx2x *bp) 3054{ 3055 if (bp->link_vars.link_up) { 3056 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 3057 bnx2x_link_sync_notify(bp); 3058 } 3059 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3060} 3061 3062static inline void bnx2x_set_mf_bw(struct bnx2x *bp) 3063{ 3064 bnx2x_config_mf_bw(bp); 3065 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 3066} 3067 3068static void bnx2x_handle_drv_info_req(struct bnx2x *bp) 3069{ 3070 enum drv_info_opcode op_code; 3071 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); 3072 3073 /* if drv_info version supported by MFW doesn't match - send NACK */ 3074 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 3075 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3076 return; 3077 } 3078 3079 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 3080 DRV_INFO_CONTROL_OP_CODE_SHIFT; 3081 3082 memset(&bp->slowpath->drv_info_to_mcp, 0, 3083 sizeof(union drv_info_to_mcp)); 3084 3085 switch (op_code) { 3086 case ETH_STATS_OPCODE: 3087 bnx2x_drv_info_ether_stat(bp); 3088 break; 3089 case FCOE_STATS_OPCODE: 3090 bnx2x_drv_info_fcoe_stat(bp); 3091 break; 3092 case ISCSI_STATS_OPCODE: 3093 bnx2x_drv_info_iscsi_stat(bp); 3094 break; 3095 default: 3096 /* if op code isn't supported - send NACK */ 3097 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3098 return; 3099 } 3100 3101 /* if we got drv_info attn from MFW then these fields are defined in 3102 * shmem2 for sure 3103 */ 3104 SHMEM2_WR(bp, drv_info_host_addr_lo, 3105 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3106 SHMEM2_WR(bp, drv_info_host_addr_hi, 3107 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3108 3109 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); 3110} 3111 3112static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) 3113{ 3114 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); 3115 3116 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 3117 3118 /* 3119 * This is the only place besides the function initialization 3120 * where the bp->flags can change so it is done without any 3121 * locks 3122 */ 3123 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 3124 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n"); 3125 bp->flags |= MF_FUNC_DIS; 3126 3127 bnx2x_e1h_disable(bp); 3128 } else { 3129 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); 3130 bp->flags &= ~MF_FUNC_DIS; 3131 3132 bnx2x_e1h_enable(bp); 3133 } 3134 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 3135 } 3136 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 3137 bnx2x_config_mf_bw(bp); 3138 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 3139 } 3140 3141 /* Report results to MCP */ 3142 if (dcc_event) 3143 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); 3144 else 3145 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); 3146} 3147 3148/* must be called under the spq lock */ 3149static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 3150{ 3151 struct eth_spe *next_spe = bp->spq_prod_bd; 3152 3153 if (bp->spq_prod_bd == bp->spq_last_bd) { 3154 bp->spq_prod_bd = bp->spq; 3155 bp->spq_prod_idx = 0; 3156 DP(NETIF_MSG_TIMER, "end of spq\n"); 3157 } else { 3158 bp->spq_prod_bd++; 3159 bp->spq_prod_idx++; 3160 } 3161 return next_spe; 3162} 3163 3164/* must be called under the spq lock */ 3165static inline void bnx2x_sp_prod_update(struct bnx2x *bp) 3166{ 3167 int func = BP_FUNC(bp); 3168 3169 /* 3170 * Make sure that BD data is updated before writing the producer: 3171 * BD data is written to the memory, the producer is read from the 3172 * memory, thus we need a full memory barrier to ensure the ordering. 3173 */ 3174 mb(); 3175 3176 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3177 bp->spq_prod_idx); 3178 mmiowb(); 3179} 3180 3181/** 3182 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3183 * 3184 * @cmd: command to check 3185 * @cmd_type: command type 3186 */ 3187static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3188{ 3189 if ((cmd_type == NONE_CONNECTION_TYPE) || 3190 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3191 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3192 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3193 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3194 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3195 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3196 return true; 3197 else 3198 return false; 3199 3200} 3201 3202 3203/** 3204 * bnx2x_sp_post - place a single command on an SP ring 3205 * 3206 * @bp: driver handle 3207 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3208 * @cid: SW CID the command is related to 3209 * @data_hi: command private data address (high 32 bits) 3210 * @data_lo: command private data address (low 32 bits) 3211 * @cmd_type: command type (e.g. NONE, ETH) 3212 * 3213 * SP data is handled as if it's always an address pair, thus data fields are 3214 * not swapped to little endian in upper functions. Instead this function swaps 3215 * data as if it's two u32 fields. 3216 */ 3217int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3218 u32 data_hi, u32 data_lo, int cmd_type) 3219{ 3220 struct eth_spe *spe; 3221 u16 type; 3222 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3223 3224#ifdef BNX2X_STOP_ON_ERROR 3225 if (unlikely(bp->panic)) 3226 return -EIO; 3227#endif 3228 3229 spin_lock_bh(&bp->spq_lock); 3230 3231 if (common) { 3232 if (!atomic_read(&bp->eq_spq_left)) { 3233 BNX2X_ERR("BUG! EQ ring full!\n"); 3234 spin_unlock_bh(&bp->spq_lock); 3235 bnx2x_panic(); 3236 return -EBUSY; 3237 } 3238 } else if (!atomic_read(&bp->cq_spq_left)) { 3239 BNX2X_ERR("BUG! SPQ ring full!\n"); 3240 spin_unlock_bh(&bp->spq_lock); 3241 bnx2x_panic(); 3242 return -EBUSY; 3243 } 3244 3245 spe = bnx2x_sp_get_next(bp); 3246 3247 /* CID needs port number to be encoded int it */ 3248 spe->hdr.conn_and_cmd_data = 3249 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3250 HW_CID(bp, cid)); 3251 3252 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; 3253 3254 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3255 SPE_HDR_FUNCTION_ID); 3256 3257 spe->hdr.type = cpu_to_le16(type); 3258 3259 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3260 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3261 3262 /* 3263 * It's ok if the actual decrement is issued towards the memory 3264 * somewhere between the spin_lock and spin_unlock. Thus no 3265 * more explict memory barrier is needed. 3266 */ 3267 if (common) 3268 atomic_dec(&bp->eq_spq_left); 3269 else 3270 atomic_dec(&bp->cq_spq_left); 3271 3272 3273 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/, 3274 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) " 3275 "type(0x%x) left (CQ, EQ) (%x,%x)\n", 3276 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3277 (u32)(U64_LO(bp->spq_mapping) + 3278 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3279 HW_CID(bp, cid), data_hi, data_lo, type, 3280 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3281 3282 bnx2x_sp_prod_update(bp); 3283 spin_unlock_bh(&bp->spq_lock); 3284 return 0; 3285} 3286 3287/* acquire split MCP access lock register */ 3288static int bnx2x_acquire_alr(struct bnx2x *bp) 3289{ 3290 u32 j, val; 3291 int rc = 0; 3292 3293 might_sleep(); 3294 for (j = 0; j < 1000; j++) { 3295 val = (1UL << 31); 3296 REG_WR(bp, GRCBASE_MCP + 0x9c, val); 3297 val = REG_RD(bp, GRCBASE_MCP + 0x9c); 3298 if (val & (1L << 31)) 3299 break; 3300 3301 msleep(5); 3302 } 3303 if (!(val & (1L << 31))) { 3304 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3305 rc = -EBUSY; 3306 } 3307 3308 return rc; 3309} 3310 3311/* release split MCP access lock register */ 3312static void bnx2x_release_alr(struct bnx2x *bp) 3313{ 3314 REG_WR(bp, GRCBASE_MCP + 0x9c, 0); 3315} 3316 3317#define BNX2X_DEF_SB_ATT_IDX 0x0001 3318#define BNX2X_DEF_SB_IDX 0x0002 3319 3320static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3321{ 3322 struct host_sp_status_block *def_sb = bp->def_status_blk; 3323 u16 rc = 0; 3324 3325 barrier(); /* status block is written to by the chip */ 3326 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3327 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 3328 rc |= BNX2X_DEF_SB_ATT_IDX; 3329 } 3330 3331 if (bp->def_idx != def_sb->sp_sb.running_index) { 3332 bp->def_idx = def_sb->sp_sb.running_index; 3333 rc |= BNX2X_DEF_SB_IDX; 3334 } 3335 3336 /* Do not reorder: indecies reading should complete before handling */ 3337 barrier(); 3338 return rc; 3339} 3340 3341/* 3342 * slow path service functions 3343 */ 3344 3345static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 3346{ 3347 int port = BP_PORT(bp); 3348 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 3349 MISC_REG_AEU_MASK_ATTN_FUNC_0; 3350 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 3351 NIG_REG_MASK_INTERRUPT_PORT0; 3352 u32 aeu_mask; 3353 u32 nig_mask = 0; 3354 u32 reg_addr; 3355 3356 if (bp->attn_state & asserted) 3357 BNX2X_ERR("IGU ERROR\n"); 3358 3359 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3360 aeu_mask = REG_RD(bp, aeu_addr); 3361 3362 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 3363 aeu_mask, asserted); 3364 aeu_mask &= ~(asserted & 0x3ff); 3365 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 3366 3367 REG_WR(bp, aeu_addr, aeu_mask); 3368 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3369 3370 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 3371 bp->attn_state |= asserted; 3372 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 3373 3374 if (asserted & ATTN_HARD_WIRED_MASK) { 3375 if (asserted & ATTN_NIG_FOR_FUNC) { 3376 3377 bnx2x_acquire_phy_lock(bp); 3378 3379 /* save nig interrupt mask */ 3380 nig_mask = REG_RD(bp, nig_int_mask_addr); 3381 3382 /* If nig_mask is not set, no need to call the update 3383 * function. 3384 */ 3385 if (nig_mask) { 3386 REG_WR(bp, nig_int_mask_addr, 0); 3387 3388 bnx2x_link_attn(bp); 3389 } 3390 3391 /* handle unicore attn? */ 3392 } 3393 if (asserted & ATTN_SW_TIMER_4_FUNC) 3394 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 3395 3396 if (asserted & GPIO_2_FUNC) 3397 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 3398 3399 if (asserted & GPIO_3_FUNC) 3400 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 3401 3402 if (asserted & GPIO_4_FUNC) 3403 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 3404 3405 if (port == 0) { 3406 if (asserted & ATTN_GENERAL_ATTN_1) { 3407 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 3408 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 3409 } 3410 if (asserted & ATTN_GENERAL_ATTN_2) { 3411 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 3412 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 3413 } 3414 if (asserted & ATTN_GENERAL_ATTN_3) { 3415 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 3416 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 3417 } 3418 } else { 3419 if (asserted & ATTN_GENERAL_ATTN_4) { 3420 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 3421 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 3422 } 3423 if (asserted & ATTN_GENERAL_ATTN_5) { 3424 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 3425 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 3426 } 3427 if (asserted & ATTN_GENERAL_ATTN_6) { 3428 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 3429 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 3430 } 3431 } 3432 3433 } /* if hardwired */ 3434 3435 if (bp->common.int_block == INT_BLOCK_HC) 3436 reg_addr = (HC_REG_COMMAND_REG + port*32 + 3437 COMMAND_REG_ATTN_BITS_SET); 3438 else 3439 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 3440 3441 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 3442 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 3443 REG_WR(bp, reg_addr, asserted); 3444 3445 /* now set back the mask */ 3446 if (asserted & ATTN_NIG_FOR_FUNC) { 3447 REG_WR(bp, nig_int_mask_addr, nig_mask); 3448 bnx2x_release_phy_lock(bp); 3449 } 3450} 3451 3452static inline void bnx2x_fan_failure(struct bnx2x *bp) 3453{ 3454 int port = BP_PORT(bp); 3455 u32 ext_phy_config; 3456 /* mark the failure */ 3457 ext_phy_config = 3458 SHMEM_RD(bp, 3459 dev_info.port_hw_config[port].external_phy_config); 3460 3461 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 3462 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 3463 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 3464 ext_phy_config); 3465 3466 /* log the failure */ 3467 netdev_err(bp->dev, "Fan Failure on Network Controller has caused" 3468 " the driver to shutdown the card to prevent permanent" 3469 " damage. Please contact OEM Support for assistance\n"); 3470 3471 /* 3472 * Scheudle device reset (unload) 3473 * This is due to some boards consuming sufficient power when driver is 3474 * up to overheat if fan fails. 3475 */ 3476 smp_mb__before_clear_bit(); 3477 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); 3478 smp_mb__after_clear_bit(); 3479 schedule_delayed_work(&bp->sp_rtnl_task, 0); 3480 3481} 3482 3483static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 3484{ 3485 int port = BP_PORT(bp); 3486 int reg_offset; 3487 u32 val; 3488 3489 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 3490 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 3491 3492 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 3493 3494 val = REG_RD(bp, reg_offset); 3495 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 3496 REG_WR(bp, reg_offset, val); 3497 3498 BNX2X_ERR("SPIO5 hw attention\n"); 3499 3500 /* Fan failure attention */ 3501 bnx2x_hw_reset_phy(&bp->link_params); 3502 bnx2x_fan_failure(bp); 3503 } 3504 3505 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 3506 bnx2x_acquire_phy_lock(bp); 3507 bnx2x_handle_module_detect_int(&bp->link_params); 3508 bnx2x_release_phy_lock(bp); 3509 } 3510 3511 if (attn & HW_INTERRUT_ASSERT_SET_0) { 3512 3513 val = REG_RD(bp, reg_offset); 3514 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 3515 REG_WR(bp, reg_offset, val); 3516 3517 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 3518 (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); 3519 bnx2x_panic(); 3520 } 3521} 3522 3523static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 3524{ 3525 u32 val; 3526 3527 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 3528 3529 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 3530 BNX2X_ERR("DB hw attention 0x%x\n", val); 3531 /* DORQ discard attention */ 3532 if (val & 0x2) 3533 BNX2X_ERR("FATAL error from DORQ\n"); 3534 } 3535 3536 if (attn & HW_INTERRUT_ASSERT_SET_1) { 3537 3538 int port = BP_PORT(bp); 3539 int reg_offset; 3540 3541 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 3542 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 3543 3544 val = REG_RD(bp, reg_offset); 3545 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 3546 REG_WR(bp, reg_offset, val); 3547 3548 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 3549 (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); 3550 bnx2x_panic(); 3551 } 3552} 3553 3554static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 3555{ 3556 u32 val; 3557 3558 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 3559 3560 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 3561 BNX2X_ERR("CFC hw attention 0x%x\n", val); 3562 /* CFC error attention */ 3563 if (val & 0x2) 3564 BNX2X_ERR("FATAL error from CFC\n"); 3565 } 3566 3567 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 3568 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 3569 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 3570 /* RQ_USDMDP_FIFO_OVERFLOW */ 3571 if (val & 0x18000) 3572 BNX2X_ERR("FATAL error from PXP\n"); 3573 3574 if (!CHIP_IS_E1x(bp)) { 3575 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 3576 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 3577 } 3578 } 3579 3580 if (attn & HW_INTERRUT_ASSERT_SET_2) { 3581 3582 int port = BP_PORT(bp); 3583 int reg_offset; 3584 3585 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 3586 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 3587 3588 val = REG_RD(bp, reg_offset); 3589 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 3590 REG_WR(bp, reg_offset, val); 3591 3592 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 3593 (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); 3594 bnx2x_panic(); 3595 } 3596} 3597 3598static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 3599{ 3600 u32 val; 3601 3602 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 3603 3604 if (attn & BNX2X_PMF_LINK_ASSERT) { 3605 int func = BP_FUNC(bp); 3606 3607 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 3608 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 3609 func_mf_config[BP_ABS_FUNC(bp)].config); 3610 val = SHMEM_RD(bp, 3611 func_mb[BP_FW_MB_IDX(bp)].drv_status); 3612 if (val & DRV_STATUS_DCC_EVENT_MASK) 3613 bnx2x_dcc_event(bp, 3614 (val & DRV_STATUS_DCC_EVENT_MASK)); 3615 3616 if (val & DRV_STATUS_SET_MF_BW) 3617 bnx2x_set_mf_bw(bp); 3618 3619 if (val & DRV_STATUS_DRV_INFO_REQ) 3620 bnx2x_handle_drv_info_req(bp); 3621 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 3622 bnx2x_pmf_update(bp); 3623 3624 if (bp->port.pmf && 3625 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 3626 bp->dcbx_enabled > 0) 3627 /* start dcbx state machine */ 3628 bnx2x_dcbx_set_params(bp, 3629 BNX2X_DCBX_STATE_NEG_RECEIVED); 3630 if (bp->link_vars.periodic_flags & 3631 PERIODIC_FLAGS_LINK_EVENT) { 3632 /* sync with link */ 3633 bnx2x_acquire_phy_lock(bp); 3634 bp->link_vars.periodic_flags &= 3635 ~PERIODIC_FLAGS_LINK_EVENT; 3636 bnx2x_release_phy_lock(bp); 3637 if (IS_MF(bp)) 3638 bnx2x_link_sync_notify(bp); 3639 bnx2x_link_report(bp); 3640 } 3641 /* Always call it here: bnx2x_link_report() will 3642 * prevent the link indication duplication. 3643 */ 3644 bnx2x__link_status_update(bp); 3645 } else if (attn & BNX2X_MC_ASSERT_BITS) { 3646 3647 BNX2X_ERR("MC assert!\n"); 3648 bnx2x_mc_assert(bp); 3649 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 3650 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 3651 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 3652 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 3653 bnx2x_panic(); 3654 3655 } else if (attn & BNX2X_MCP_ASSERT) { 3656 3657 BNX2X_ERR("MCP assert!\n"); 3658 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 3659 bnx2x_fw_dump(bp); 3660 3661 } else 3662 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 3663 } 3664 3665 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 3666 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 3667 if (attn & BNX2X_GRC_TIMEOUT) { 3668 val = CHIP_IS_E1(bp) ? 0 : 3669 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 3670 BNX2X_ERR("GRC time-out 0x%08x\n", val); 3671 } 3672 if (attn & BNX2X_GRC_RSV) { 3673 val = CHIP_IS_E1(bp) ? 0 : 3674 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 3675 BNX2X_ERR("GRC reserved 0x%08x\n", val); 3676 } 3677 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 3678 } 3679} 3680 3681/* 3682 * Bits map: 3683 * 0-7 - Engine0 load counter. 3684 * 8-15 - Engine1 load counter. 3685 * 16 - Engine0 RESET_IN_PROGRESS bit. 3686 * 17 - Engine1 RESET_IN_PROGRESS bit. 3687 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 3688 * on the engine 3689 * 19 - Engine1 ONE_IS_LOADED. 3690 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 3691 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 3692 * just the one belonging to its engine). 3693 * 3694 */ 3695#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 3696 3697#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 3698#define BNX2X_PATH0_LOAD_CNT_SHIFT 0 3699#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 3700#define BNX2X_PATH1_LOAD_CNT_SHIFT 8 3701#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 3702#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 3703#define BNX2X_GLOBAL_RESET_BIT 0x00040000 3704 3705/* 3706 * Set the GLOBAL_RESET bit. 3707 * 3708 * Should be run under rtnl lock 3709 */ 3710void bnx2x_set_reset_global(struct bnx2x *bp) 3711{ 3712 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3713 3714 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 3715 barrier(); 3716 mmiowb(); 3717} 3718 3719/* 3720 * Clear the GLOBAL_RESET bit. 3721 * 3722 * Should be run under rtnl lock 3723 */ 3724static inline void bnx2x_clear_reset_global(struct bnx2x *bp) 3725{ 3726 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3727 3728 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 3729 barrier(); 3730 mmiowb(); 3731} 3732 3733/* 3734 * Checks the GLOBAL_RESET bit. 3735 * 3736 * should be run under rtnl lock 3737 */ 3738static inline bool bnx2x_reset_is_global(struct bnx2x *bp) 3739{ 3740 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3741 3742 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 3743 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 3744} 3745 3746/* 3747 * Clear RESET_IN_PROGRESS bit for the current engine. 3748 * 3749 * Should be run under rtnl lock 3750 */ 3751static inline void bnx2x_set_reset_done(struct bnx2x *bp) 3752{ 3753 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3754 u32 bit = BP_PATH(bp) ? 3755 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3756 3757 /* Clear the bit */ 3758 val &= ~bit; 3759 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3760 barrier(); 3761 mmiowb(); 3762} 3763 3764/* 3765 * Set RESET_IN_PROGRESS for the current engine. 3766 * 3767 * should be run under rtnl lock 3768 */ 3769void bnx2x_set_reset_in_progress(struct bnx2x *bp) 3770{ 3771 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3772 u32 bit = BP_PATH(bp) ? 3773 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3774 3775 /* Set the bit */ 3776 val |= bit; 3777 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3778 barrier(); 3779 mmiowb(); 3780} 3781 3782/* 3783 * Checks the RESET_IN_PROGRESS bit for the given engine. 3784 * should be run under rtnl lock 3785 */ 3786bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 3787{ 3788 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3789 u32 bit = engine ? 3790 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3791 3792 /* return false if bit is set */ 3793 return (val & bit) ? false : true; 3794} 3795 3796/* 3797 * Increment the load counter for the current engine. 3798 * 3799 * should be run under rtnl lock 3800 */ 3801void bnx2x_inc_load_cnt(struct bnx2x *bp) 3802{ 3803 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3804 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3805 BNX2X_PATH0_LOAD_CNT_MASK; 3806 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3807 BNX2X_PATH0_LOAD_CNT_SHIFT; 3808 3809 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3810 3811 /* get the current counter value */ 3812 val1 = (val & mask) >> shift; 3813 3814 /* increment... */ 3815 val1++; 3816 3817 /* clear the old value */ 3818 val &= ~mask; 3819 3820 /* set the new one */ 3821 val |= ((val1 << shift) & mask); 3822 3823 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3824 barrier(); 3825 mmiowb(); 3826} 3827 3828/** 3829 * bnx2x_dec_load_cnt - decrement the load counter 3830 * 3831 * @bp: driver handle 3832 * 3833 * Should be run under rtnl lock. 3834 * Decrements the load counter for the current engine. Returns 3835 * the new counter value. 3836 */ 3837u32 bnx2x_dec_load_cnt(struct bnx2x *bp) 3838{ 3839 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3840 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3841 BNX2X_PATH0_LOAD_CNT_MASK; 3842 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3843 BNX2X_PATH0_LOAD_CNT_SHIFT; 3844 3845 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3846 3847 /* get the current counter value */ 3848 val1 = (val & mask) >> shift; 3849 3850 /* decrement... */ 3851 val1--; 3852 3853 /* clear the old value */ 3854 val &= ~mask; 3855 3856 /* set the new one */ 3857 val |= ((val1 << shift) & mask); 3858 3859 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3860 barrier(); 3861 mmiowb(); 3862 3863 return val1; 3864} 3865 3866/* 3867 * Read the load counter for the current engine. 3868 * 3869 * should be run under rtnl lock 3870 */ 3871static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine) 3872{ 3873 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 3874 BNX2X_PATH0_LOAD_CNT_MASK); 3875 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3876 BNX2X_PATH0_LOAD_CNT_SHIFT); 3877 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3878 3879 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val); 3880 3881 val = (val & mask) >> shift; 3882 3883 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val); 3884 3885 return val; 3886} 3887 3888/* 3889 * Reset the load counter for the current engine. 3890 * 3891 * should be run under rtnl lock 3892 */ 3893static inline void bnx2x_clear_load_cnt(struct bnx2x *bp) 3894{ 3895 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3896 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3897 BNX2X_PATH0_LOAD_CNT_MASK); 3898 3899 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); 3900} 3901 3902static inline void _print_next_block(int idx, const char *blk) 3903{ 3904 pr_cont("%s%s", idx ? ", " : "", blk); 3905} 3906 3907static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, 3908 bool print) 3909{ 3910 int i = 0; 3911 u32 cur_bit = 0; 3912 for (i = 0; sig; i++) { 3913 cur_bit = ((u32)0x1 << i); 3914 if (sig & cur_bit) { 3915 switch (cur_bit) { 3916 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 3917 if (print) 3918 _print_next_block(par_num++, "BRB"); 3919 break; 3920 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 3921 if (print) 3922 _print_next_block(par_num++, "PARSER"); 3923 break; 3924 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 3925 if (print) 3926 _print_next_block(par_num++, "TSDM"); 3927 break; 3928 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 3929 if (print) 3930 _print_next_block(par_num++, 3931 "SEARCHER"); 3932 break; 3933 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 3934 if (print) 3935 _print_next_block(par_num++, "TCM"); 3936 break; 3937 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 3938 if (print) 3939 _print_next_block(par_num++, "TSEMI"); 3940 break; 3941 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 3942 if (print) 3943 _print_next_block(par_num++, "XPB"); 3944 break; 3945 } 3946 3947 /* Clear the bit */ 3948 sig &= ~cur_bit; 3949 } 3950 } 3951 3952 return par_num; 3953} 3954 3955static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, 3956 bool *global, bool print) 3957{ 3958 int i = 0; 3959 u32 cur_bit = 0; 3960 for (i = 0; sig; i++) { 3961 cur_bit = ((u32)0x1 << i); 3962 if (sig & cur_bit) { 3963 switch (cur_bit) { 3964 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 3965 if (print) 3966 _print_next_block(par_num++, "PBF"); 3967 break; 3968 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 3969 if (print) 3970 _print_next_block(par_num++, "QM"); 3971 break; 3972 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 3973 if (print) 3974 _print_next_block(par_num++, "TM"); 3975 break; 3976 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 3977 if (print) 3978 _print_next_block(par_num++, "XSDM"); 3979 break; 3980 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 3981 if (print) 3982 _print_next_block(par_num++, "XCM"); 3983 break; 3984 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 3985 if (print) 3986 _print_next_block(par_num++, "XSEMI"); 3987 break; 3988 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 3989 if (print) 3990 _print_next_block(par_num++, 3991 "DOORBELLQ"); 3992 break; 3993 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 3994 if (print) 3995 _print_next_block(par_num++, "NIG"); 3996 break; 3997 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 3998 if (print) 3999 _print_next_block(par_num++, 4000 "VAUX PCI CORE"); 4001 *global = true; 4002 break; 4003 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 4004 if (print) 4005 _print_next_block(par_num++, "DEBUG"); 4006 break; 4007 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 4008 if (print) 4009 _print_next_block(par_num++, "USDM"); 4010 break; 4011 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 4012 if (print) 4013 _print_next_block(par_num++, "UCM"); 4014 break; 4015 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 4016 if (print) 4017 _print_next_block(par_num++, "USEMI"); 4018 break; 4019 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 4020 if (print) 4021 _print_next_block(par_num++, "UPB"); 4022 break; 4023 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 4024 if (print) 4025 _print_next_block(par_num++, "CSDM"); 4026 break; 4027 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 4028 if (print) 4029 _print_next_block(par_num++, "CCM"); 4030 break; 4031 } 4032 4033 /* Clear the bit */ 4034 sig &= ~cur_bit; 4035 } 4036 } 4037 4038 return par_num; 4039} 4040 4041static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, 4042 bool print) 4043{ 4044 int i = 0; 4045 u32 cur_bit = 0; 4046 for (i = 0; sig; i++) { 4047 cur_bit = ((u32)0x1 << i); 4048 if (sig & cur_bit) { 4049 switch (cur_bit) { 4050 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 4051 if (print) 4052 _print_next_block(par_num++, "CSEMI"); 4053 break; 4054 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 4055 if (print) 4056 _print_next_block(par_num++, "PXP"); 4057 break; 4058 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 4059 if (print) 4060 _print_next_block(par_num++, 4061 "PXPPCICLOCKCLIENT"); 4062 break; 4063 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 4064 if (print) 4065 _print_next_block(par_num++, "CFC"); 4066 break; 4067 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 4068 if (print) 4069 _print_next_block(par_num++, "CDU"); 4070 break; 4071 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 4072 if (print) 4073 _print_next_block(par_num++, "DMAE"); 4074 break; 4075 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 4076 if (print) 4077 _print_next_block(par_num++, "IGU"); 4078 break; 4079 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 4080 if (print) 4081 _print_next_block(par_num++, "MISC"); 4082 break; 4083 } 4084 4085 /* Clear the bit */ 4086 sig &= ~cur_bit; 4087 } 4088 } 4089 4090 return par_num; 4091} 4092 4093static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, 4094 bool *global, bool print) 4095{ 4096 int i = 0; 4097 u32 cur_bit = 0; 4098 for (i = 0; sig; i++) { 4099 cur_bit = ((u32)0x1 << i); 4100 if (sig & cur_bit) { 4101 switch (cur_bit) { 4102 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 4103 if (print) 4104 _print_next_block(par_num++, "MCP ROM"); 4105 *global = true; 4106 break; 4107 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 4108 if (print) 4109 _print_next_block(par_num++, 4110 "MCP UMP RX"); 4111 *global = true; 4112 break; 4113 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 4114 if (print) 4115 _print_next_block(par_num++, 4116 "MCP UMP TX"); 4117 *global = true; 4118 break; 4119 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 4120 if (print) 4121 _print_next_block(par_num++, 4122 "MCP SCPAD"); 4123 *global = true; 4124 break; 4125 } 4126 4127 /* Clear the bit */ 4128 sig &= ~cur_bit; 4129 } 4130 } 4131 4132 return par_num; 4133} 4134 4135static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, 4136 bool print) 4137{ 4138 int i = 0; 4139 u32 cur_bit = 0; 4140 for (i = 0; sig; i++) { 4141 cur_bit = ((u32)0x1 << i); 4142 if (sig & cur_bit) { 4143 switch (cur_bit) { 4144 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 4145 if (print) 4146 _print_next_block(par_num++, "PGLUE_B"); 4147 break; 4148 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 4149 if (print) 4150 _print_next_block(par_num++, "ATC"); 4151 break; 4152 } 4153 4154 /* Clear the bit */ 4155 sig &= ~cur_bit; 4156 } 4157 } 4158 4159 return par_num; 4160} 4161 4162static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4163 u32 *sig) 4164{ 4165 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4166 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4167 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4168 (sig[3] & HW_PRTY_ASSERT_SET_3) || 4169 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4170 int par_num = 0; 4171 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: " 4172 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x " 4173 "[4]:0x%08x\n", 4174 sig[0] & HW_PRTY_ASSERT_SET_0, 4175 sig[1] & HW_PRTY_ASSERT_SET_1, 4176 sig[2] & HW_PRTY_ASSERT_SET_2, 4177 sig[3] & HW_PRTY_ASSERT_SET_3, 4178 sig[4] & HW_PRTY_ASSERT_SET_4); 4179 if (print) 4180 netdev_err(bp->dev, 4181 "Parity errors detected in blocks: "); 4182 par_num = bnx2x_check_blocks_with_parity0( 4183 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); 4184 par_num = bnx2x_check_blocks_with_parity1( 4185 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); 4186 par_num = bnx2x_check_blocks_with_parity2( 4187 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); 4188 par_num = bnx2x_check_blocks_with_parity3( 4189 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); 4190 par_num = bnx2x_check_blocks_with_parity4( 4191 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); 4192 4193 if (print) 4194 pr_cont("\n"); 4195 4196 return true; 4197 } else 4198 return false; 4199} 4200 4201/** 4202 * bnx2x_chk_parity_attn - checks for parity attentions. 4203 * 4204 * @bp: driver handle 4205 * @global: true if there was a global attention 4206 * @print: show parity attention in syslog 4207 */ 4208bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 4209{ 4210 struct attn_route attn = { {0} }; 4211 int port = BP_PORT(bp); 4212 4213 attn.sig[0] = REG_RD(bp, 4214 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 4215 port*4); 4216 attn.sig[1] = REG_RD(bp, 4217 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 4218 port*4); 4219 attn.sig[2] = REG_RD(bp, 4220 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 4221 port*4); 4222 attn.sig[3] = REG_RD(bp, 4223 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 4224 port*4); 4225 4226 if (!CHIP_IS_E1x(bp)) 4227 attn.sig[4] = REG_RD(bp, 4228 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 4229 port*4); 4230 4231 return bnx2x_parity_attn(bp, global, print, attn.sig); 4232} 4233 4234 4235static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 4236{ 4237 u32 val; 4238 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 4239 4240 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 4241 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 4242 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 4243 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4244 "ADDRESS_ERROR\n"); 4245 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 4246 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4247 "INCORRECT_RCV_BEHAVIOR\n"); 4248 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 4249 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4250 "WAS_ERROR_ATTN\n"); 4251 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 4252 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4253 "VF_LENGTH_VIOLATION_ATTN\n"); 4254 if (val & 4255 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 4256 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4257 "VF_GRC_SPACE_VIOLATION_ATTN\n"); 4258 if (val & 4259 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 4260 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4261 "VF_MSIX_BAR_VIOLATION_ATTN\n"); 4262 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 4263 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4264 "TCPL_ERROR_ATTN\n"); 4265 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 4266 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4267 "TCPL_IN_TWO_RCBS_ATTN\n"); 4268 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 4269 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4270 "CSSNOOP_FIFO_OVERFLOW\n"); 4271 } 4272 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 4273 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 4274 BNX2X_ERR("ATC hw attention 0x%x\n", val); 4275 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 4276 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 4277 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 4278 BNX2X_ERR("ATC_ATC_INT_STS_REG" 4279 "_ATC_TCPL_TO_NOT_PEND\n"); 4280 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 4281 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4282 "ATC_GPA_MULTIPLE_HITS\n"); 4283 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 4284 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4285 "ATC_RCPL_TO_EMPTY_CNT\n"); 4286 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 4287 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 4288 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 4289 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4290 "ATC_IREQ_LESS_THAN_STU\n"); 4291 } 4292 4293 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4294 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 4295 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 4296 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4297 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 4298 } 4299 4300} 4301 4302static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 4303{ 4304 struct attn_route attn, *group_mask; 4305 int port = BP_PORT(bp); 4306 int index; 4307 u32 reg_addr; 4308 u32 val; 4309 u32 aeu_mask; 4310 bool global = false; 4311 4312 /* need to take HW lock because MCP or other port might also 4313 try to handle this event */ 4314 bnx2x_acquire_alr(bp); 4315 4316 if (bnx2x_chk_parity_attn(bp, &global, true)) { 4317#ifndef BNX2X_STOP_ON_ERROR 4318 bp->recovery_state = BNX2X_RECOVERY_INIT; 4319 schedule_delayed_work(&bp->sp_rtnl_task, 0); 4320 /* Disable HW interrupts */ 4321 bnx2x_int_disable(bp); 4322 /* In case of parity errors don't handle attentions so that 4323 * other function would "see" parity errors. 4324 */ 4325#else 4326 bnx2x_panic(); 4327#endif 4328 bnx2x_release_alr(bp); 4329 return; 4330 } 4331 4332 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 4333 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 4334 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 4335 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 4336 if (!CHIP_IS_E1x(bp)) 4337 attn.sig[4] = 4338 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 4339 else 4340 attn.sig[4] = 0; 4341 4342 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 4343 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 4344 4345 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4346 if (deasserted & (1 << index)) { 4347 group_mask = &bp->attn_group[index]; 4348 4349 DP(NETIF_MSG_HW, "group[%d]: %08x %08x " 4350 "%08x %08x %08x\n", 4351 index, 4352 group_mask->sig[0], group_mask->sig[1], 4353 group_mask->sig[2], group_mask->sig[3], 4354 group_mask->sig[4]); 4355 4356 bnx2x_attn_int_deasserted4(bp, 4357 attn.sig[4] & group_mask->sig[4]); 4358 bnx2x_attn_int_deasserted3(bp, 4359 attn.sig[3] & group_mask->sig[3]); 4360 bnx2x_attn_int_deasserted1(bp, 4361 attn.sig[1] & group_mask->sig[1]); 4362 bnx2x_attn_int_deasserted2(bp, 4363 attn.sig[2] & group_mask->sig[2]); 4364 bnx2x_attn_int_deasserted0(bp, 4365 attn.sig[0] & group_mask->sig[0]); 4366 } 4367 } 4368 4369 bnx2x_release_alr(bp); 4370 4371 if (bp->common.int_block == INT_BLOCK_HC) 4372 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4373 COMMAND_REG_ATTN_BITS_CLR); 4374 else 4375 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 4376 4377 val = ~deasserted; 4378 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 4379 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4380 REG_WR(bp, reg_addr, val); 4381 4382 if (~bp->attn_state & deasserted) 4383 BNX2X_ERR("IGU ERROR\n"); 4384 4385 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4386 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4387 4388 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4389 aeu_mask = REG_RD(bp, reg_addr); 4390 4391 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 4392 aeu_mask, deasserted); 4393 aeu_mask |= (deasserted & 0x3ff); 4394 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4395 4396 REG_WR(bp, reg_addr, aeu_mask); 4397 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4398 4399 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4400 bp->attn_state &= ~deasserted; 4401 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4402} 4403 4404static void bnx2x_attn_int(struct bnx2x *bp) 4405{ 4406 /* read local copy of bits */ 4407 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 4408 attn_bits); 4409 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 4410 attn_bits_ack); 4411 u32 attn_state = bp->attn_state; 4412 4413 /* look for changed bits */ 4414 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 4415 u32 deasserted = ~attn_bits & attn_ack & attn_state; 4416 4417 DP(NETIF_MSG_HW, 4418 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 4419 attn_bits, attn_ack, asserted, deasserted); 4420 4421 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 4422 BNX2X_ERR("BAD attention state\n"); 4423 4424 /* handle bits that were raised */ 4425 if (asserted) 4426 bnx2x_attn_int_asserted(bp, asserted); 4427 4428 if (deasserted) 4429 bnx2x_attn_int_deasserted(bp, deasserted); 4430} 4431 4432void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 4433 u16 index, u8 op, u8 update) 4434{ 4435 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 4436 4437 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 4438 igu_addr); 4439} 4440 4441static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 4442{ 4443 /* No memory barriers */ 4444 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 4445 mmiowb(); /* keep prod updates ordered */ 4446} 4447 4448#ifdef BCM_CNIC 4449static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 4450 union event_ring_elem *elem) 4451{ 4452 u8 err = elem->message.error; 4453 4454 if (!bp->cnic_eth_dev.starting_cid || 4455 (cid < bp->cnic_eth_dev.starting_cid && 4456 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 4457 return 1; 4458 4459 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 4460 4461 if (unlikely(err)) { 4462 4463 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 4464 cid); 4465 bnx2x_panic_dump(bp); 4466 } 4467 bnx2x_cnic_cfc_comp(bp, cid, err); 4468 return 0; 4469} 4470#endif 4471 4472static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 4473{ 4474 struct bnx2x_mcast_ramrod_params rparam; 4475 int rc; 4476 4477 memset(&rparam, 0, sizeof(rparam)); 4478 4479 rparam.mcast_obj = &bp->mcast_obj; 4480 4481 netif_addr_lock_bh(bp->dev); 4482 4483 /* Clear pending state for the last command */ 4484 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 4485 4486 /* If there are pending mcast commands - send them */ 4487 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 4488 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 4489 if (rc < 0) 4490 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 4491 rc); 4492 } 4493 4494 netif_addr_unlock_bh(bp->dev); 4495} 4496 4497static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp, 4498 union event_ring_elem *elem) 4499{ 4500 unsigned long ramrod_flags = 0; 4501 int rc = 0; 4502 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; 4503 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 4504 4505 /* Always push next commands out, don't wait here */ 4506 __set_bit(RAMROD_CONT, &ramrod_flags); 4507 4508 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 4509 case BNX2X_FILTER_MAC_PENDING: 4510#ifdef BCM_CNIC 4511 if (cid == BNX2X_ISCSI_ETH_CID) 4512 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 4513 else 4514#endif 4515 vlan_mac_obj = &bp->fp[cid].mac_obj; 4516 4517 break; 4518 case BNX2X_FILTER_MCAST_PENDING: 4519 /* This is only relevant for 57710 where multicast MACs are 4520 * configured as unicast MACs using the same ramrod. 4521 */ 4522 bnx2x_handle_mcast_eqe(bp); 4523 return; 4524 default: 4525 BNX2X_ERR("Unsupported classification command: %d\n", 4526 elem->message.data.eth_event.echo); 4527 return; 4528 } 4529 4530 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 4531 4532 if (rc < 0) 4533 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 4534 else if (rc > 0) 4535 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 4536 4537} 4538 4539#ifdef BCM_CNIC 4540static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 4541#endif 4542 4543static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 4544{ 4545 netif_addr_lock_bh(bp->dev); 4546 4547 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 4548 4549 /* Send rx_mode command again if was requested */ 4550 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 4551 bnx2x_set_storm_rx_mode(bp); 4552#ifdef BCM_CNIC 4553 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 4554 &bp->sp_state)) 4555 bnx2x_set_iscsi_eth_rx_mode(bp, true); 4556 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 4557 &bp->sp_state)) 4558 bnx2x_set_iscsi_eth_rx_mode(bp, false); 4559#endif 4560 4561 netif_addr_unlock_bh(bp->dev); 4562} 4563 4564static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 4565 struct bnx2x *bp, u32 cid) 4566{ 4567 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 4568#ifdef BCM_CNIC 4569 if (cid == BNX2X_FCOE_ETH_CID) 4570 return &bnx2x_fcoe(bp, q_obj); 4571 else 4572#endif 4573 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj); 4574} 4575 4576static void bnx2x_eq_int(struct bnx2x *bp) 4577{ 4578 u16 hw_cons, sw_cons, sw_prod; 4579 union event_ring_elem *elem; 4580 u32 cid; 4581 u8 opcode; 4582 int spqe_cnt = 0; 4583 struct bnx2x_queue_sp_obj *q_obj; 4584 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 4585 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 4586 4587 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 4588 4589 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 4590 * when we get the the next-page we nned to adjust so the loop 4591 * condition below will be met. The next element is the size of a 4592 * regular element and hence incrementing by 1 4593 */ 4594 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 4595 hw_cons++; 4596 4597 /* This function may never run in parallel with itself for a 4598 * specific bp, thus there is no need in "paired" read memory 4599 * barrier here. 4600 */ 4601 sw_cons = bp->eq_cons; 4602 sw_prod = bp->eq_prod; 4603 4604 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 4605 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 4606 4607 for (; sw_cons != hw_cons; 4608 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 4609 4610 4611 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 4612 4613 cid = SW_CID(elem->message.data.cfc_del_event.cid); 4614 opcode = elem->message.opcode; 4615 4616 4617 /* handle eq element */ 4618 switch (opcode) { 4619 case EVENT_RING_OPCODE_STAT_QUERY: 4620 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n", 4621 bp->stats_comp++); 4622 /* nothing to do with stats comp */ 4623 goto next_spqe; 4624 4625 case EVENT_RING_OPCODE_CFC_DEL: 4626 /* handle according to cid range */ 4627 /* 4628 * we may want to verify here that the bp state is 4629 * HALTING 4630 */ 4631 DP(BNX2X_MSG_SP, 4632 "got delete ramrod for MULTI[%d]\n", cid); 4633#ifdef BCM_CNIC 4634 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 4635 goto next_spqe; 4636#endif 4637 q_obj = bnx2x_cid_to_q_obj(bp, cid); 4638 4639 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 4640 break; 4641 4642 4643 4644 goto next_spqe; 4645 4646 case EVENT_RING_OPCODE_STOP_TRAFFIC: 4647 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n"); 4648 if (f_obj->complete_cmd(bp, f_obj, 4649 BNX2X_F_CMD_TX_STOP)) 4650 break; 4651 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 4652 goto next_spqe; 4653 4654 case EVENT_RING_OPCODE_START_TRAFFIC: 4655 DP(BNX2X_MSG_SP, "got START TRAFFIC\n"); 4656 if (f_obj->complete_cmd(bp, f_obj, 4657 BNX2X_F_CMD_TX_START)) 4658 break; 4659 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 4660 goto next_spqe; 4661 case EVENT_RING_OPCODE_FUNCTION_START: 4662 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n"); 4663 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 4664 break; 4665 4666 goto next_spqe; 4667 4668 case EVENT_RING_OPCODE_FUNCTION_STOP: 4669 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n"); 4670 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 4671 break; 4672 4673 goto next_spqe; 4674 } 4675 4676 switch (opcode | bp->state) { 4677 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4678 BNX2X_STATE_OPEN): 4679 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4680 BNX2X_STATE_OPENING_WAIT4_PORT): 4681 cid = elem->message.data.eth_event.echo & 4682 BNX2X_SWCID_MASK; 4683 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 4684 cid); 4685 rss_raw->clear_pending(rss_raw); 4686 break; 4687 4688 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 4689 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 4690 case (EVENT_RING_OPCODE_SET_MAC | 4691 BNX2X_STATE_CLOSING_WAIT4_HALT): 4692 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4693 BNX2X_STATE_OPEN): 4694 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4695 BNX2X_STATE_DIAG): 4696 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4697 BNX2X_STATE_CLOSING_WAIT4_HALT): 4698 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); 4699 bnx2x_handle_classification_eqe(bp, elem); 4700 break; 4701 4702 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4703 BNX2X_STATE_OPEN): 4704 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4705 BNX2X_STATE_DIAG): 4706 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4707 BNX2X_STATE_CLOSING_WAIT4_HALT): 4708 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 4709 bnx2x_handle_mcast_eqe(bp); 4710 break; 4711 4712 case (EVENT_RING_OPCODE_FILTERS_RULES | 4713 BNX2X_STATE_OPEN): 4714 case (EVENT_RING_OPCODE_FILTERS_RULES | 4715 BNX2X_STATE_DIAG): 4716 case (EVENT_RING_OPCODE_FILTERS_RULES | 4717 BNX2X_STATE_CLOSING_WAIT4_HALT): 4718 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 4719 bnx2x_handle_rx_mode_eqe(bp); 4720 break; 4721 default: 4722 /* unknown event log error and continue */ 4723 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 4724 elem->message.opcode, bp->state); 4725 } 4726next_spqe: 4727 spqe_cnt++; 4728 } /* for */ 4729 4730 smp_mb__before_atomic_inc(); 4731 atomic_add(spqe_cnt, &bp->eq_spq_left); 4732 4733 bp->eq_cons = sw_cons; 4734 bp->eq_prod = sw_prod; 4735 /* Make sure that above mem writes were issued towards the memory */ 4736 smp_wmb(); 4737 4738 /* update producer */ 4739 bnx2x_update_eq_prod(bp, bp->eq_prod); 4740} 4741 4742static void bnx2x_sp_task(struct work_struct *work) 4743{ 4744 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 4745 u16 status; 4746 4747 status = bnx2x_update_dsb_idx(bp); 4748/* if (status == 0) */ 4749/* BNX2X_ERR("spurious slowpath interrupt!\n"); */ 4750 4751 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status); 4752 4753 /* HW attentions */ 4754 if (status & BNX2X_DEF_SB_ATT_IDX) { 4755 bnx2x_attn_int(bp); 4756 status &= ~BNX2X_DEF_SB_ATT_IDX; 4757 } 4758 4759 /* SP events: STAT_QUERY and others */ 4760 if (status & BNX2X_DEF_SB_IDX) { 4761#ifdef BCM_CNIC 4762 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 4763 4764 if ((!NO_FCOE(bp)) && 4765 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 4766 /* 4767 * Prevent local bottom-halves from running as 4768 * we are going to change the local NAPI list. 4769 */ 4770 local_bh_disable(); 4771 napi_schedule(&bnx2x_fcoe(bp, napi)); 4772 local_bh_enable(); 4773 } 4774#endif 4775 /* Handle EQ completions */ 4776 bnx2x_eq_int(bp); 4777 4778 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 4779 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 4780 4781 status &= ~BNX2X_DEF_SB_IDX; 4782 } 4783 4784 if (unlikely(status)) 4785 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 4786 status); 4787 4788 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 4789 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 4790} 4791 4792irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 4793{ 4794 struct net_device *dev = dev_instance; 4795 struct bnx2x *bp = netdev_priv(dev); 4796 4797 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 4798 IGU_INT_DISABLE, 0); 4799 4800#ifdef BNX2X_STOP_ON_ERROR 4801 if (unlikely(bp->panic)) 4802 return IRQ_HANDLED; 4803#endif 4804 4805#ifdef BCM_CNIC 4806 { 4807 struct cnic_ops *c_ops; 4808 4809 rcu_read_lock(); 4810 c_ops = rcu_dereference(bp->cnic_ops); 4811 if (c_ops) 4812 c_ops->cnic_handler(bp->cnic_data, NULL); 4813 rcu_read_unlock(); 4814 } 4815#endif 4816 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 4817 4818 return IRQ_HANDLED; 4819} 4820 4821/* end of slow path */ 4822 4823 4824void bnx2x_drv_pulse(struct bnx2x *bp) 4825{ 4826 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 4827 bp->fw_drv_pulse_wr_seq); 4828} 4829 4830 4831static void bnx2x_timer(unsigned long data) 4832{ 4833 struct bnx2x *bp = (struct bnx2x *) data; 4834 4835 if (!netif_running(bp->dev)) 4836 return; 4837 4838 if (!BP_NOMCP(bp)) { 4839 int mb_idx = BP_FW_MB_IDX(bp); 4840 u32 drv_pulse; 4841 u32 mcp_pulse; 4842 4843 ++bp->fw_drv_pulse_wr_seq; 4844 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 4845 /* TBD - add SYSTEM_TIME */ 4846 drv_pulse = bp->fw_drv_pulse_wr_seq; 4847 bnx2x_drv_pulse(bp); 4848 4849 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 4850 MCP_PULSE_SEQ_MASK); 4851 /* The delta between driver pulse and mcp response 4852 * should be 1 (before mcp response) or 0 (after mcp response) 4853 */ 4854 if ((drv_pulse != mcp_pulse) && 4855 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 4856 /* someone lost a heartbeat... */ 4857 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 4858 drv_pulse, mcp_pulse); 4859 } 4860 } 4861 4862 if (bp->state == BNX2X_STATE_OPEN) 4863 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 4864 4865 mod_timer(&bp->timer, jiffies + bp->current_interval); 4866} 4867 4868/* end of Statistics */ 4869 4870/* nic init */ 4871 4872/* 4873 * nic init service functions 4874 */ 4875 4876static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 4877{ 4878 u32 i; 4879 if (!(len%4) && !(addr%4)) 4880 for (i = 0; i < len; i += 4) 4881 REG_WR(bp, addr + i, fill); 4882 else 4883 for (i = 0; i < len; i++) 4884 REG_WR8(bp, addr + i, fill); 4885 4886} 4887 4888/* helper: writes FP SP data to FW - data_size in dwords */ 4889static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 4890 int fw_sb_id, 4891 u32 *sb_data_p, 4892 u32 data_size) 4893{ 4894 int index; 4895 for (index = 0; index < data_size; index++) 4896 REG_WR(bp, BAR_CSTRORM_INTMEM + 4897 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 4898 sizeof(u32)*index, 4899 *(sb_data_p + index)); 4900} 4901 4902static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 4903{ 4904 u32 *sb_data_p; 4905 u32 data_size = 0; 4906 struct hc_status_block_data_e2 sb_data_e2; 4907 struct hc_status_block_data_e1x sb_data_e1x; 4908 4909 /* disable the function first */ 4910 if (!CHIP_IS_E1x(bp)) { 4911 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 4912 sb_data_e2.common.state = SB_DISABLED; 4913 sb_data_e2.common.p_func.vf_valid = false; 4914 sb_data_p = (u32 *)&sb_data_e2; 4915 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 4916 } else { 4917 memset(&sb_data_e1x, 0, 4918 sizeof(struct hc_status_block_data_e1x)); 4919 sb_data_e1x.common.state = SB_DISABLED; 4920 sb_data_e1x.common.p_func.vf_valid = false; 4921 sb_data_p = (u32 *)&sb_data_e1x; 4922 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 4923 } 4924 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 4925 4926 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4927 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 4928 CSTORM_STATUS_BLOCK_SIZE); 4929 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4930 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 4931 CSTORM_SYNC_BLOCK_SIZE); 4932} 4933 4934/* helper: writes SP SB data to FW */ 4935static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 4936 struct hc_sp_status_block_data *sp_sb_data) 4937{ 4938 int func = BP_FUNC(bp); 4939 int i; 4940 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 4941 REG_WR(bp, BAR_CSTRORM_INTMEM + 4942 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 4943 i*sizeof(u32), 4944 *((u32 *)sp_sb_data + i)); 4945} 4946 4947static inline void bnx2x_zero_sp_sb(struct bnx2x *bp) 4948{ 4949 int func = BP_FUNC(bp); 4950 struct hc_sp_status_block_data sp_sb_data; 4951 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 4952 4953 sp_sb_data.state = SB_DISABLED; 4954 sp_sb_data.p_func.vf_valid = false; 4955 4956 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 4957 4958 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4959 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 4960 CSTORM_SP_STATUS_BLOCK_SIZE); 4961 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4962 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 4963 CSTORM_SP_SYNC_BLOCK_SIZE); 4964 4965} 4966 4967 4968static inline 4969void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 4970 int igu_sb_id, int igu_seg_id) 4971{ 4972 hc_sm->igu_sb_id = igu_sb_id; 4973 hc_sm->igu_seg_id = igu_seg_id; 4974 hc_sm->timer_value = 0xFF; 4975 hc_sm->time_to_expire = 0xFFFFFFFF; 4976} 4977 4978 4979/* allocates state machine ids. */ 4980static inline 4981void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) 4982{ 4983 /* zero out state machine indices */ 4984 /* rx indices */ 4985 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 4986 4987 /* tx indices */ 4988 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 4989 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 4990 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 4991 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 4992 4993 /* map indices */ 4994 /* rx indices */ 4995 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 4996 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4997 4998 /* tx indices */ 4999 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 5000 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5001 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 5002 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5003 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 5004 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5005 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 5006 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5007} 5008 5009static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 5010 u8 vf_valid, int fw_sb_id, int igu_sb_id) 5011{ 5012 int igu_seg_id; 5013 5014 struct hc_status_block_data_e2 sb_data_e2; 5015 struct hc_status_block_data_e1x sb_data_e1x; 5016 struct hc_status_block_sm *hc_sm_p; 5017 int data_size; 5018 u32 *sb_data_p; 5019 5020 if (CHIP_INT_MODE_IS_BC(bp)) 5021 igu_seg_id = HC_SEG_ACCESS_NORM; 5022 else 5023 igu_seg_id = IGU_SEG_ACCESS_NORM; 5024 5025 bnx2x_zero_fp_sb(bp, fw_sb_id); 5026 5027 if (!CHIP_IS_E1x(bp)) { 5028 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5029 sb_data_e2.common.state = SB_ENABLED; 5030 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 5031 sb_data_e2.common.p_func.vf_id = vfid; 5032 sb_data_e2.common.p_func.vf_valid = vf_valid; 5033 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 5034 sb_data_e2.common.same_igu_sb_1b = true; 5035 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 5036 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 5037 hc_sm_p = sb_data_e2.common.state_machine; 5038 sb_data_p = (u32 *)&sb_data_e2; 5039 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5040 bnx2x_map_sb_state_machines(sb_data_e2.index_data); 5041 } else { 5042 memset(&sb_data_e1x, 0, 5043 sizeof(struct hc_status_block_data_e1x)); 5044 sb_data_e1x.common.state = SB_ENABLED; 5045 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 5046 sb_data_e1x.common.p_func.vf_id = 0xff; 5047 sb_data_e1x.common.p_func.vf_valid = false; 5048 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 5049 sb_data_e1x.common.same_igu_sb_1b = true; 5050 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 5051 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 5052 hc_sm_p = sb_data_e1x.common.state_machine; 5053 sb_data_p = (u32 *)&sb_data_e1x; 5054 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5055 bnx2x_map_sb_state_machines(sb_data_e1x.index_data); 5056 } 5057 5058 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 5059 igu_sb_id, igu_seg_id); 5060 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 5061 igu_sb_id, igu_seg_id); 5062 5063 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id); 5064 5065 /* write indecies to HW */ 5066 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5067} 5068 5069static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 5070 u16 tx_usec, u16 rx_usec) 5071{ 5072 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 5073 false, rx_usec); 5074 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5075 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 5076 tx_usec); 5077 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5078 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 5079 tx_usec); 5080 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5081 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 5082 tx_usec); 5083} 5084 5085static void bnx2x_init_def_sb(struct bnx2x *bp) 5086{ 5087 struct host_sp_status_block *def_sb = bp->def_status_blk; 5088 dma_addr_t mapping = bp->def_status_blk_mapping; 5089 int igu_sp_sb_index; 5090 int igu_seg_id; 5091 int port = BP_PORT(bp); 5092 int func = BP_FUNC(bp); 5093 int reg_offset, reg_offset_en5; 5094 u64 section; 5095 int index; 5096 struct hc_sp_status_block_data sp_sb_data; 5097 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5098 5099 if (CHIP_INT_MODE_IS_BC(bp)) { 5100 igu_sp_sb_index = DEF_SB_IGU_ID; 5101 igu_seg_id = HC_SEG_ACCESS_DEF; 5102 } else { 5103 igu_sp_sb_index = bp->igu_dsb_id; 5104 igu_seg_id = IGU_SEG_ACCESS_DEF; 5105 } 5106 5107 /* ATTN */ 5108 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5109 atten_status_block); 5110 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 5111 5112 bp->attn_state = 0; 5113 5114 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 5115 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 5116 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 5117 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); 5118 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 5119 int sindex; 5120 /* take care of sig[0]..sig[4] */ 5121 for (sindex = 0; sindex < 4; sindex++) 5122 bp->attn_group[index].sig[sindex] = 5123 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 5124 5125 if (!CHIP_IS_E1x(bp)) 5126 /* 5127 * enable5 is separate from the rest of the registers, 5128 * and therefore the address skip is 4 5129 * and not 16 between the different groups 5130 */ 5131 bp->attn_group[index].sig[4] = REG_RD(bp, 5132 reg_offset_en5 + 0x4*index); 5133 else 5134 bp->attn_group[index].sig[4] = 0; 5135 } 5136 5137 if (bp->common.int_block == INT_BLOCK_HC) { 5138 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 5139 HC_REG_ATTN_MSG0_ADDR_L); 5140 5141 REG_WR(bp, reg_offset, U64_LO(section)); 5142 REG_WR(bp, reg_offset + 4, U64_HI(section)); 5143 } else if (!CHIP_IS_E1x(bp)) { 5144 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 5145 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 5146 } 5147 5148 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5149 sp_sb); 5150 5151 bnx2x_zero_sp_sb(bp); 5152 5153 sp_sb_data.state = SB_ENABLED; 5154 sp_sb_data.host_sb_addr.lo = U64_LO(section); 5155 sp_sb_data.host_sb_addr.hi = U64_HI(section); 5156 sp_sb_data.igu_sb_id = igu_sp_sb_index; 5157 sp_sb_data.igu_seg_id = igu_seg_id; 5158 sp_sb_data.p_func.pf_id = func; 5159 sp_sb_data.p_func.vnic_id = BP_VN(bp); 5160 sp_sb_data.p_func.vf_id = 0xff; 5161 5162 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5163 5164 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 5165} 5166 5167void bnx2x_update_coalesce(struct bnx2x *bp) 5168{ 5169 int i; 5170 5171 for_each_eth_queue(bp, i) 5172 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 5173 bp->tx_ticks, bp->rx_ticks); 5174} 5175 5176static void bnx2x_init_sp_ring(struct bnx2x *bp) 5177{ 5178 spin_lock_init(&bp->spq_lock); 5179 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 5180 5181 bp->spq_prod_idx = 0; 5182 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 5183 bp->spq_prod_bd = bp->spq; 5184 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 5185} 5186 5187static void bnx2x_init_eq_ring(struct bnx2x *bp) 5188{ 5189 int i; 5190 for (i = 1; i <= NUM_EQ_PAGES; i++) { 5191 union event_ring_elem *elem = 5192 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 5193 5194 elem->next_page.addr.hi = 5195 cpu_to_le32(U64_HI(bp->eq_mapping + 5196 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 5197 elem->next_page.addr.lo = 5198 cpu_to_le32(U64_LO(bp->eq_mapping + 5199 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 5200 } 5201 bp->eq_cons = 0; 5202 bp->eq_prod = NUM_EQ_DESC; 5203 bp->eq_cons_sb = BNX2X_EQ_INDEX; 5204 /* we want a warning message before it gets rought... */ 5205 atomic_set(&bp->eq_spq_left, 5206 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 5207} 5208 5209 5210/* called with netif_addr_lock_bh() */ 5211void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 5212 unsigned long rx_mode_flags, 5213 unsigned long rx_accept_flags, 5214 unsigned long tx_accept_flags, 5215 unsigned long ramrod_flags) 5216{ 5217 struct bnx2x_rx_mode_ramrod_params ramrod_param; 5218 int rc; 5219 5220 memset(&ramrod_param, 0, sizeof(ramrod_param)); 5221 5222 /* Prepare ramrod parameters */ 5223 ramrod_param.cid = 0; 5224 ramrod_param.cl_id = cl_id; 5225 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 5226 ramrod_param.func_id = BP_FUNC(bp); 5227 5228 ramrod_param.pstate = &bp->sp_state; 5229 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 5230 5231 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 5232 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 5233 5234 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5235 5236 ramrod_param.ramrod_flags = ramrod_flags; 5237 ramrod_param.rx_mode_flags = rx_mode_flags; 5238 5239 ramrod_param.rx_accept_flags = rx_accept_flags; 5240 ramrod_param.tx_accept_flags = tx_accept_flags; 5241 5242 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 5243 if (rc < 0) { 5244 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 5245 return; 5246 } 5247} 5248 5249/* called with netif_addr_lock_bh() */ 5250void bnx2x_set_storm_rx_mode(struct bnx2x *bp) 5251{ 5252 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 5253 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 5254 5255#ifdef BCM_CNIC 5256 if (!NO_FCOE(bp)) 5257 5258 /* Configure rx_mode of FCoE Queue */ 5259 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 5260#endif 5261 5262 switch (bp->rx_mode) { 5263 case BNX2X_RX_MODE_NONE: 5264 /* 5265 * 'drop all' supersedes any accept flags that may have been 5266 * passed to the function. 5267 */ 5268 break; 5269 case BNX2X_RX_MODE_NORMAL: 5270 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5271 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); 5272 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5273 5274 /* internal switching mode */ 5275 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5276 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); 5277 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5278 5279 break; 5280 case BNX2X_RX_MODE_ALLMULTI: 5281 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5282 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5283 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5284 5285 /* internal switching mode */ 5286 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5287 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5288 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5289 5290 break; 5291 case BNX2X_RX_MODE_PROMISC: 5292 /* According to deffinition of SI mode, iface in promisc mode 5293 * should receive matched and unmatched (in resolution of port) 5294 * unicast packets. 5295 */ 5296 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); 5297 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5298 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5299 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5300 5301 /* internal switching mode */ 5302 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5303 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5304 5305 if (IS_MF_SI(bp)) 5306 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); 5307 else 5308 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5309 5310 break; 5311 default: 5312 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); 5313 return; 5314 } 5315 5316 if (bp->rx_mode != BNX2X_RX_MODE_NONE) { 5317 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); 5318 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); 5319 } 5320 5321 __set_bit(RAMROD_RX, &ramrod_flags); 5322 __set_bit(RAMROD_TX, &ramrod_flags); 5323 5324 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, 5325 tx_accept_flags, ramrod_flags); 5326} 5327 5328static void bnx2x_init_internal_common(struct bnx2x *bp) 5329{ 5330 int i; 5331 5332 if (IS_MF_SI(bp)) 5333 /* 5334 * In switch independent mode, the TSTORM needs to accept 5335 * packets that failed classification, since approximate match 5336 * mac addresses aren't written to NIG LLH 5337 */ 5338 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5339 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); 5340 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ 5341 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5342 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); 5343 5344 /* Zero this manually as its initialization is 5345 currently missing in the initTool */ 5346 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 5347 REG_WR(bp, BAR_USTRORM_INTMEM + 5348 USTORM_AGG_DATA_OFFSET + i * 4, 0); 5349 if (!CHIP_IS_E1x(bp)) { 5350 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 5351 CHIP_INT_MODE_IS_BC(bp) ? 5352 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 5353 } 5354} 5355 5356static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 5357{ 5358 switch (load_code) { 5359 case FW_MSG_CODE_DRV_LOAD_COMMON: 5360 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5361 bnx2x_init_internal_common(bp); 5362 /* no break */ 5363 5364 case FW_MSG_CODE_DRV_LOAD_PORT: 5365 /* nothing to do */ 5366 /* no break */ 5367 5368 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5369 /* internal memory per function is 5370 initialized inside bnx2x_pf_init */ 5371 break; 5372 5373 default: 5374 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5375 break; 5376 } 5377} 5378 5379static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 5380{ 5381 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; 5382} 5383 5384static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 5385{ 5386 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; 5387} 5388 5389static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 5390{ 5391 if (CHIP_IS_E1x(fp->bp)) 5392 return BP_L_ID(fp->bp) + fp->index; 5393 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 5394 return bnx2x_fp_igu_sb_id(fp); 5395} 5396 5397static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 5398{ 5399 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 5400 u8 cos; 5401 unsigned long q_type = 0; 5402 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 5403 fp->rx_queue = fp_idx; 5404 fp->cid = fp_idx; 5405 fp->cl_id = bnx2x_fp_cl_id(fp); 5406 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 5407 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 5408 /* qZone id equals to FW (per path) client id */ 5409 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 5410 5411 /* init shortcut */ 5412 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 5413 /* Setup SB indicies */ 5414 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 5415 5416 /* Configure Queue State object */ 5417 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 5418 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 5419 5420 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 5421 5422 /* init tx data */ 5423 for_each_cos_in_tx_queue(fp, cos) { 5424 bnx2x_init_txdata(bp, &fp->txdata[cos], 5425 CID_COS_TO_TX_ONLY_CID(fp->cid, cos), 5426 FP_COS_TO_TXQ(fp, cos), 5427 BNX2X_TX_SB_INDEX_BASE + cos); 5428 cids[cos] = fp->txdata[cos].cid; 5429 } 5430 5431 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos, 5432 BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 5433 bnx2x_sp_mapping(bp, q_rdata), q_type); 5434 5435 /** 5436 * Configure classification DBs: Always enable Tx switching 5437 */ 5438 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 5439 5440 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) " 5441 "cl_id %d fw_sb %d igu_sb %d\n", 5442 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 5443 fp->igu_sb_id); 5444 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 5445 fp->fw_sb_id, fp->igu_sb_id); 5446 5447 bnx2x_update_fpsb_idx(fp); 5448} 5449 5450void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) 5451{ 5452 int i; 5453 5454 for_each_eth_queue(bp, i) 5455 bnx2x_init_eth_fp(bp, i); 5456#ifdef BCM_CNIC 5457 if (!NO_FCOE(bp)) 5458 bnx2x_init_fcoe_fp(bp); 5459 5460 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 5461 BNX2X_VF_ID_INVALID, false, 5462 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 5463 5464#endif 5465 5466 /* Initialize MOD_ABS interrupts */ 5467 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 5468 bp->common.shmem_base, bp->common.shmem2_base, 5469 BP_PORT(bp)); 5470 /* ensure status block indices were read */ 5471 rmb(); 5472 5473 bnx2x_init_def_sb(bp); 5474 bnx2x_update_dsb_idx(bp); 5475 bnx2x_init_rx_rings(bp); 5476 bnx2x_init_tx_rings(bp); 5477 bnx2x_init_sp_ring(bp); 5478 bnx2x_init_eq_ring(bp); 5479 bnx2x_init_internal(bp, load_code); 5480 bnx2x_pf_init(bp); 5481 bnx2x_stats_init(bp); 5482 5483 /* flush all before enabling interrupts */ 5484 mb(); 5485 mmiowb(); 5486 5487 bnx2x_int_enable(bp); 5488 5489 /* Check for SPIO5 */ 5490 bnx2x_attn_int_deasserted0(bp, 5491 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 5492 AEU_INPUTS_ATTN_BITS_SPIO5); 5493} 5494 5495/* end of nic init */ 5496 5497/* 5498 * gzip service functions 5499 */ 5500 5501static int bnx2x_gunzip_init(struct bnx2x *bp) 5502{ 5503 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 5504 &bp->gunzip_mapping, GFP_KERNEL); 5505 if (bp->gunzip_buf == NULL) 5506 goto gunzip_nomem1; 5507 5508 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 5509 if (bp->strm == NULL) 5510 goto gunzip_nomem2; 5511 5512 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 5513 if (bp->strm->workspace == NULL) 5514 goto gunzip_nomem3; 5515 5516 return 0; 5517 5518gunzip_nomem3: 5519 kfree(bp->strm); 5520 bp->strm = NULL; 5521 5522gunzip_nomem2: 5523 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5524 bp->gunzip_mapping); 5525 bp->gunzip_buf = NULL; 5526 5527gunzip_nomem1: 5528 netdev_err(bp->dev, "Cannot allocate firmware buffer for" 5529 " un-compression\n"); 5530 return -ENOMEM; 5531} 5532 5533static void bnx2x_gunzip_end(struct bnx2x *bp) 5534{ 5535 if (bp->strm) { 5536 vfree(bp->strm->workspace); 5537 kfree(bp->strm); 5538 bp->strm = NULL; 5539 } 5540 5541 if (bp->gunzip_buf) { 5542 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5543 bp->gunzip_mapping); 5544 bp->gunzip_buf = NULL; 5545 } 5546} 5547 5548static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 5549{ 5550 int n, rc; 5551 5552 /* check gzip header */ 5553 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 5554 BNX2X_ERR("Bad gzip header\n"); 5555 return -EINVAL; 5556 } 5557 5558 n = 10; 5559 5560#define FNAME 0x8 5561 5562 if (zbuf[3] & FNAME) 5563 while ((zbuf[n++] != 0) && (n < len)); 5564 5565 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 5566 bp->strm->avail_in = len - n; 5567 bp->strm->next_out = bp->gunzip_buf; 5568 bp->strm->avail_out = FW_BUF_SIZE; 5569 5570 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 5571 if (rc != Z_OK) 5572 return rc; 5573 5574 rc = zlib_inflate(bp->strm, Z_FINISH); 5575 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 5576 netdev_err(bp->dev, "Firmware decompression error: %s\n", 5577 bp->strm->msg); 5578 5579 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 5580 if (bp->gunzip_outlen & 0x3) 5581 netdev_err(bp->dev, "Firmware decompression error:" 5582 " gunzip_outlen (%d) not aligned\n", 5583 bp->gunzip_outlen); 5584 bp->gunzip_outlen >>= 2; 5585 5586 zlib_inflateEnd(bp->strm); 5587 5588 if (rc == Z_STREAM_END) 5589 return 0; 5590 5591 return rc; 5592} 5593 5594/* nic load/unload */ 5595 5596/* 5597 * General service functions 5598 */ 5599 5600/* send a NIG loopback debug packet */ 5601static void bnx2x_lb_pckt(struct bnx2x *bp) 5602{ 5603 u32 wb_write[3]; 5604 5605 /* Ethernet source and destination addresses */ 5606 wb_write[0] = 0x55555555; 5607 wb_write[1] = 0x55555555; 5608 wb_write[2] = 0x20; /* SOP */ 5609 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5610 5611 /* NON-IP protocol */ 5612 wb_write[0] = 0x09000000; 5613 wb_write[1] = 0x55555555; 5614 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 5615 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5616} 5617 5618/* some of the internal memories 5619 * are not directly readable from the driver 5620 * to test them we send debug packets 5621 */ 5622static int bnx2x_int_mem_test(struct bnx2x *bp) 5623{ 5624 int factor; 5625 int count, i; 5626 u32 val = 0; 5627 5628 if (CHIP_REV_IS_FPGA(bp)) 5629 factor = 120; 5630 else if (CHIP_REV_IS_EMUL(bp)) 5631 factor = 200; 5632 else 5633 factor = 1; 5634 5635 /* Disable inputs of parser neighbor blocks */ 5636 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5637 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5638 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5639 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5640 5641 /* Write 0 to parser credits for CFC search request */ 5642 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5643 5644 /* send Ethernet packet */ 5645 bnx2x_lb_pckt(bp); 5646 5647 /* TODO do i reset NIG statistic? */ 5648 /* Wait until NIG register shows 1 packet of size 0x10 */ 5649 count = 1000 * factor; 5650 while (count) { 5651 5652 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5653 val = *bnx2x_sp(bp, wb_data[0]); 5654 if (val == 0x10) 5655 break; 5656 5657 msleep(10); 5658 count--; 5659 } 5660 if (val != 0x10) { 5661 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5662 return -1; 5663 } 5664 5665 /* Wait until PRS register shows 1 packet */ 5666 count = 1000 * factor; 5667 while (count) { 5668 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5669 if (val == 1) 5670 break; 5671 5672 msleep(10); 5673 count--; 5674 } 5675 if (val != 0x1) { 5676 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5677 return -2; 5678 } 5679 5680 /* Reset and init BRB, PRS */ 5681 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5682 msleep(50); 5683 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5684 msleep(50); 5685 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5686 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5687 5688 DP(NETIF_MSG_HW, "part2\n"); 5689 5690 /* Disable inputs of parser neighbor blocks */ 5691 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5692 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5693 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5694 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5695 5696 /* Write 0 to parser credits for CFC search request */ 5697 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5698 5699 /* send 10 Ethernet packets */ 5700 for (i = 0; i < 10; i++) 5701 bnx2x_lb_pckt(bp); 5702 5703 /* Wait until NIG register shows 10 + 1 5704 packets of size 11*0x10 = 0xb0 */ 5705 count = 1000 * factor; 5706 while (count) { 5707 5708 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5709 val = *bnx2x_sp(bp, wb_data[0]); 5710 if (val == 0xb0) 5711 break; 5712 5713 msleep(10); 5714 count--; 5715 } 5716 if (val != 0xb0) { 5717 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5718 return -3; 5719 } 5720 5721 /* Wait until PRS register shows 2 packets */ 5722 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5723 if (val != 2) 5724 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5725 5726 /* Write 1 to parser credits for CFC search request */ 5727 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 5728 5729 /* Wait until PRS register shows 3 packets */ 5730 msleep(10 * factor); 5731 /* Wait until NIG register shows 1 packet of size 0x10 */ 5732 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5733 if (val != 3) 5734 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5735 5736 /* clear NIG EOP FIFO */ 5737 for (i = 0; i < 11; i++) 5738 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 5739 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 5740 if (val != 1) { 5741 BNX2X_ERR("clear of NIG failed\n"); 5742 return -4; 5743 } 5744 5745 /* Reset and init BRB, PRS, NIG */ 5746 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5747 msleep(50); 5748 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5749 msleep(50); 5750 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5751 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5752#ifndef BCM_CNIC 5753 /* set NIC mode */ 5754 REG_WR(bp, PRS_REG_NIC_MODE, 1); 5755#endif 5756 5757 /* Enable inputs of parser neighbor blocks */ 5758 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 5759 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 5760 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 5761 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 5762 5763 DP(NETIF_MSG_HW, "done\n"); 5764 5765 return 0; /* OK */ 5766} 5767 5768static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 5769{ 5770 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 5771 if (!CHIP_IS_E1x(bp)) 5772 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 5773 else 5774 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 5775 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 5776 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 5777 /* 5778 * mask read length error interrupts in brb for parser 5779 * (parsing unit and 'checksum and crc' unit) 5780 * these errors are legal (PU reads fixed length and CAC can cause 5781 * read length error on truncated packets) 5782 */ 5783 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 5784 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 5785 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 5786 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 5787 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 5788 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 5789/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 5790/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 5791 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 5792 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 5793 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 5794/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 5795/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 5796 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 5797 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 5798 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 5799 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 5800/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 5801/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 5802 5803 if (CHIP_REV_IS_FPGA(bp)) 5804 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); 5805 else if (!CHIP_IS_E1x(bp)) 5806 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 5807 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF 5808 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT 5809 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN 5810 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED 5811 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); 5812 else 5813 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); 5814 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 5815 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 5816 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 5817/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 5818 5819 if (!CHIP_IS_E1x(bp)) 5820 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 5821 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 5822 5823 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 5824 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 5825/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 5826 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 5827} 5828 5829static void bnx2x_reset_common(struct bnx2x *bp) 5830{ 5831 u32 val = 0x1400; 5832 5833 /* reset_common */ 5834 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 5835 0xd3ffff7f); 5836 5837 if (CHIP_IS_E3(bp)) { 5838 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 5839 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 5840 } 5841 5842 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); 5843} 5844 5845static void bnx2x_setup_dmae(struct bnx2x *bp) 5846{ 5847 bp->dmae_ready = 0; 5848 spin_lock_init(&bp->dmae_lock); 5849} 5850 5851static void bnx2x_init_pxp(struct bnx2x *bp) 5852{ 5853 u16 devctl; 5854 int r_order, w_order; 5855 5856 pci_read_config_word(bp->pdev, 5857 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); 5858 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); 5859 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 5860 if (bp->mrrs == -1) 5861 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); 5862 else { 5863 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); 5864 r_order = bp->mrrs; 5865 } 5866 5867 bnx2x_init_pxp_arb(bp, r_order, w_order); 5868} 5869 5870static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 5871{ 5872 int is_required; 5873 u32 val; 5874 int port; 5875 5876 if (BP_NOMCP(bp)) 5877 return; 5878 5879 is_required = 0; 5880 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 5881 SHARED_HW_CFG_FAN_FAILURE_MASK; 5882 5883 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) 5884 is_required = 1; 5885 5886 /* 5887 * The fan failure mechanism is usually related to the PHY type since 5888 * the power consumption of the board is affected by the PHY. Currently, 5889 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 5890 */ 5891 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 5892 for (port = PORT_0; port < PORT_MAX; port++) { 5893 is_required |= 5894 bnx2x_fan_failure_det_req( 5895 bp, 5896 bp->common.shmem_base, 5897 bp->common.shmem2_base, 5898 port); 5899 } 5900 5901 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 5902 5903 if (is_required == 0) 5904 return; 5905 5906 /* Fan failure is indicated by SPIO 5 */ 5907 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, 5908 MISC_REGISTERS_SPIO_INPUT_HI_Z); 5909 5910 /* set to active low mode */ 5911 val = REG_RD(bp, MISC_REG_SPIO_INT); 5912 val |= ((1 << MISC_REGISTERS_SPIO_5) << 5913 MISC_REGISTERS_SPIO_INT_OLD_SET_POS); 5914 REG_WR(bp, MISC_REG_SPIO_INT, val); 5915 5916 /* enable interrupt to signal the IGU */ 5917 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 5918 val |= (1 << MISC_REGISTERS_SPIO_5); 5919 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 5920} 5921 5922static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) 5923{ 5924 u32 offset = 0; 5925 5926 if (CHIP_IS_E1(bp)) 5927 return; 5928 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) 5929 return; 5930 5931 switch (BP_ABS_FUNC(bp)) { 5932 case 0: 5933 offset = PXP2_REG_PGL_PRETEND_FUNC_F0; 5934 break; 5935 case 1: 5936 offset = PXP2_REG_PGL_PRETEND_FUNC_F1; 5937 break; 5938 case 2: 5939 offset = PXP2_REG_PGL_PRETEND_FUNC_F2; 5940 break; 5941 case 3: 5942 offset = PXP2_REG_PGL_PRETEND_FUNC_F3; 5943 break; 5944 case 4: 5945 offset = PXP2_REG_PGL_PRETEND_FUNC_F4; 5946 break; 5947 case 5: 5948 offset = PXP2_REG_PGL_PRETEND_FUNC_F5; 5949 break; 5950 case 6: 5951 offset = PXP2_REG_PGL_PRETEND_FUNC_F6; 5952 break; 5953 case 7: 5954 offset = PXP2_REG_PGL_PRETEND_FUNC_F7; 5955 break; 5956 default: 5957 return; 5958 } 5959 5960 REG_WR(bp, offset, pretend_func_num); 5961 REG_RD(bp, offset); 5962 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); 5963} 5964 5965void bnx2x_pf_disable(struct bnx2x *bp) 5966{ 5967 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 5968 val &= ~IGU_PF_CONF_FUNC_EN; 5969 5970 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 5971 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 5972 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); 5973} 5974 5975static inline void bnx2x__common_init_phy(struct bnx2x *bp) 5976{ 5977 u32 shmem_base[2], shmem2_base[2]; 5978 shmem_base[0] = bp->common.shmem_base; 5979 shmem2_base[0] = bp->common.shmem2_base; 5980 if (!CHIP_IS_E1x(bp)) { 5981 shmem_base[1] = 5982 SHMEM2_RD(bp, other_shmem_base_addr); 5983 shmem2_base[1] = 5984 SHMEM2_RD(bp, other_shmem2_base_addr); 5985 } 5986 bnx2x_acquire_phy_lock(bp); 5987 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, 5988 bp->common.chip_id); 5989 bnx2x_release_phy_lock(bp); 5990} 5991 5992/** 5993 * bnx2x_init_hw_common - initialize the HW at the COMMON phase. 5994 * 5995 * @bp: driver handle 5996 */ 5997static int bnx2x_init_hw_common(struct bnx2x *bp) 5998{ 5999 u32 val; 6000 6001 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp)); 6002 6003 /* 6004 * take the UNDI lock to protect undi_unload flow from accessing 6005 * registers while we're resetting the chip 6006 */ 6007 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6008 6009 bnx2x_reset_common(bp); 6010 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 6011 6012 val = 0xfffc; 6013 if (CHIP_IS_E3(bp)) { 6014 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 6015 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 6016 } 6017 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 6018 6019 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6020 6021 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 6022 6023 if (!CHIP_IS_E1x(bp)) { 6024 u8 abs_func_id; 6025 6026 /** 6027 * 4-port mode or 2-port mode we need to turn of master-enable 6028 * for everyone, after that, turn it back on for self. 6029 * so, we disregard multi-function or not, and always disable 6030 * for all functions on the given path, this means 0,2,4,6 for 6031 * path 0 and 1,3,5,7 for path 1 6032 */ 6033 for (abs_func_id = BP_PATH(bp); 6034 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { 6035 if (abs_func_id == BP_ABS_FUNC(bp)) { 6036 REG_WR(bp, 6037 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 6038 1); 6039 continue; 6040 } 6041 6042 bnx2x_pretend_func(bp, abs_func_id); 6043 /* clear pf enable */ 6044 bnx2x_pf_disable(bp); 6045 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6046 } 6047 } 6048 6049 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); 6050 if (CHIP_IS_E1(bp)) { 6051 /* enable HW interrupt from PXP on USDM overflow 6052 bit 16 on INT_MASK_0 */ 6053 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 6054 } 6055 6056 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); 6057 bnx2x_init_pxp(bp); 6058 6059#ifdef __BIG_ENDIAN 6060 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); 6061 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); 6062 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 6063 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 6064 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 6065 /* make sure this value is 0 */ 6066 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); 6067 6068/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ 6069 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); 6070 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); 6071 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); 6072 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 6073#endif 6074 6075 bnx2x_ilt_init_page_size(bp, INITOP_SET); 6076 6077 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 6078 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 6079 6080 /* let the HW do it's magic ... */ 6081 msleep(100); 6082 /* finish PXP init */ 6083 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); 6084 if (val != 1) { 6085 BNX2X_ERR("PXP2 CFG failed\n"); 6086 return -EBUSY; 6087 } 6088 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); 6089 if (val != 1) { 6090 BNX2X_ERR("PXP2 RD_INIT failed\n"); 6091 return -EBUSY; 6092 } 6093 6094 /* Timers bug workaround E2 only. We need to set the entire ILT to 6095 * have entries with value "0" and valid bit on. 6096 * This needs to be done by the first PF that is loaded in a path 6097 * (i.e. common phase) 6098 */ 6099 if (!CHIP_IS_E1x(bp)) { 6100/* In E2 there is a bug in the timers block that can cause function 6 / 7 6101 * (i.e. vnic3) to start even if it is marked as "scan-off". 6102 * This occurs when a different function (func2,3) is being marked 6103 * as "scan-off". Real-life scenario for example: if a driver is being 6104 * load-unloaded while func6,7 are down. This will cause the timer to access 6105 * the ilt, translate to a logical address and send a request to read/write. 6106 * Since the ilt for the function that is down is not valid, this will cause 6107 * a translation error which is unrecoverable. 6108 * The Workaround is intended to make sure that when this happens nothing fatal 6109 * will occur. The workaround: 6110 * 1. First PF driver which loads on a path will: 6111 * a. After taking the chip out of reset, by using pretend, 6112 * it will write "0" to the following registers of 6113 * the other vnics. 6114 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6115 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 6116 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 6117 * And for itself it will write '1' to 6118 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 6119 * dmae-operations (writing to pram for example.) 6120 * note: can be done for only function 6,7 but cleaner this 6121 * way. 6122 * b. Write zero+valid to the entire ILT. 6123 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 6124 * VNIC3 (of that port). The range allocated will be the 6125 * entire ILT. This is needed to prevent ILT range error. 6126 * 2. Any PF driver load flow: 6127 * a. ILT update with the physical addresses of the allocated 6128 * logical pages. 6129 * b. Wait 20msec. - note that this timeout is needed to make 6130 * sure there are no requests in one of the PXP internal 6131 * queues with "old" ILT addresses. 6132 * c. PF enable in the PGLC. 6133 * d. Clear the was_error of the PF in the PGLC. (could have 6134 * occured while driver was down) 6135 * e. PF enable in the CFC (WEAK + STRONG) 6136 * f. Timers scan enable 6137 * 3. PF driver unload flow: 6138 * a. Clear the Timers scan_en. 6139 * b. Polling for scan_on=0 for that PF. 6140 * c. Clear the PF enable bit in the PXP. 6141 * d. Clear the PF enable in the CFC (WEAK + STRONG) 6142 * e. Write zero+valid to all ILT entries (The valid bit must 6143 * stay set) 6144 * f. If this is VNIC 3 of a port then also init 6145 * first_timers_ilt_entry to zero and last_timers_ilt_entry 6146 * to the last enrty in the ILT. 6147 * 6148 * Notes: 6149 * Currently the PF error in the PGLC is non recoverable. 6150 * In the future the there will be a recovery routine for this error. 6151 * Currently attention is masked. 6152 * Having an MCP lock on the load/unload process does not guarantee that 6153 * there is no Timer disable during Func6/7 enable. This is because the 6154 * Timers scan is currently being cleared by the MCP on FLR. 6155 * Step 2.d can be done only for PF6/7 and the driver can also check if 6156 * there is error before clearing it. But the flow above is simpler and 6157 * more general. 6158 * All ILT entries are written by zero+valid and not just PF6/7 6159 * ILT entries since in the future the ILT entries allocation for 6160 * PF-s might be dynamic. 6161 */ 6162 struct ilt_client_info ilt_cli; 6163 struct bnx2x_ilt ilt; 6164 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 6165 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); 6166 6167 /* initialize dummy TM client */ 6168 ilt_cli.start = 0; 6169 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 6170 ilt_cli.client_num = ILT_CLIENT_TM; 6171 6172 /* Step 1: set zeroes to all ilt page entries with valid bit on 6173 * Step 2: set the timers first/last ilt entry to point 6174 * to the entire range to prevent ILT range error for 3rd/4th 6175 * vnic (this code assumes existance of the vnic) 6176 * 6177 * both steps performed by call to bnx2x_ilt_client_init_op() 6178 * with dummy TM client 6179 * 6180 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 6181 * and his brother are split registers 6182 */ 6183 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); 6184 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); 6185 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6186 6187 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); 6188 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); 6189 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 6190 } 6191 6192 6193 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 6194 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 6195 6196 if (!CHIP_IS_E1x(bp)) { 6197 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : 6198 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); 6199 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); 6200 6201 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); 6202 6203 /* let the HW do it's magic ... */ 6204 do { 6205 msleep(200); 6206 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); 6207 } while (factor-- && (val != 1)); 6208 6209 if (val != 1) { 6210 BNX2X_ERR("ATC_INIT failed\n"); 6211 return -EBUSY; 6212 } 6213 } 6214 6215 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); 6216 6217 /* clean the DMAE memory */ 6218 bp->dmae_ready = 1; 6219 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); 6220 6221 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); 6222 6223 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); 6224 6225 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); 6226 6227 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); 6228 6229 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); 6230 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); 6231 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); 6232 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); 6233 6234 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); 6235 6236 6237 /* QM queues pointers table */ 6238 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); 6239 6240 /* soft reset pulse */ 6241 REG_WR(bp, QM_REG_SOFT_RESET, 1); 6242 REG_WR(bp, QM_REG_SOFT_RESET, 0); 6243 6244#ifdef BCM_CNIC 6245 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); 6246#endif 6247 6248 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); 6249 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); 6250 if (!CHIP_REV_IS_SLOW(bp)) 6251 /* enable hw interrupt from doorbell Q */ 6252 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6253 6254 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6255 6256 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6257 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 6258 6259 if (!CHIP_IS_E1(bp)) 6260 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); 6261 6262 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) 6263 /* Bit-map indicating which L2 hdrs may appear 6264 * after the basic Ethernet header 6265 */ 6266 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 6267 bp->path_has_ovlan ? 7 : 6); 6268 6269 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); 6270 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); 6271 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); 6272 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); 6273 6274 if (!CHIP_IS_E1x(bp)) { 6275 /* reset VFC memories */ 6276 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6277 VFC_MEMORIES_RST_REG_CAM_RST | 6278 VFC_MEMORIES_RST_REG_RAM_RST); 6279 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6280 VFC_MEMORIES_RST_REG_CAM_RST | 6281 VFC_MEMORIES_RST_REG_RAM_RST); 6282 6283 msleep(20); 6284 } 6285 6286 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); 6287 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); 6288 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); 6289 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); 6290 6291 /* sync semi rtc */ 6292 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6293 0x80000000); 6294 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 6295 0x80000000); 6296 6297 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); 6298 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); 6299 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); 6300 6301 if (!CHIP_IS_E1x(bp)) 6302 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 6303 bp->path_has_ovlan ? 7 : 6); 6304 6305 REG_WR(bp, SRC_REG_SOFT_RST, 1); 6306 6307 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); 6308 6309#ifdef BCM_CNIC 6310 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 6311 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 6312 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); 6313 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); 6314 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); 6315 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 6316 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); 6317 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 6318 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); 6319 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); 6320#endif 6321 REG_WR(bp, SRC_REG_SOFT_RST, 0); 6322 6323 if (sizeof(union cdu_context) != 1024) 6324 /* we currently assume that a context is 1024 bytes */ 6325 dev_alert(&bp->pdev->dev, "please adjust the size " 6326 "of cdu_context(%ld)\n", 6327 (long)sizeof(union cdu_context)); 6328 6329 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 6330 val = (4 << 24) + (0 << 12) + 1024; 6331 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); 6332 6333 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); 6334 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); 6335 /* enable context validation interrupt from CFC */ 6336 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6337 6338 /* set the thresholds to prevent CFC/CDU race */ 6339 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 6340 6341 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); 6342 6343 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) 6344 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); 6345 6346 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); 6347 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); 6348 6349 /* Reset PCIE errors for debug */ 6350 REG_WR(bp, 0x2814, 0xffffffff); 6351 REG_WR(bp, 0x3820, 0xffffffff); 6352 6353 if (!CHIP_IS_E1x(bp)) { 6354 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 6355 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 6356 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 6357 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 6358 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 6359 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 6360 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 6361 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 6362 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 6363 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 6364 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 6365 } 6366 6367 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); 6368 if (!CHIP_IS_E1(bp)) { 6369 /* in E3 this done in per-port section */ 6370 if (!CHIP_IS_E3(bp)) 6371 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6372 } 6373 if (CHIP_IS_E1H(bp)) 6374 /* not applicable for E2 (and above ...) */ 6375 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); 6376 6377 if (CHIP_REV_IS_SLOW(bp)) 6378 msleep(200); 6379 6380 /* finish CFC init */ 6381 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); 6382 if (val != 1) { 6383 BNX2X_ERR("CFC LL_INIT failed\n"); 6384 return -EBUSY; 6385 } 6386 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); 6387 if (val != 1) { 6388 BNX2X_ERR("CFC AC_INIT failed\n"); 6389 return -EBUSY; 6390 } 6391 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 6392 if (val != 1) { 6393 BNX2X_ERR("CFC CAM_INIT failed\n"); 6394 return -EBUSY; 6395 } 6396 REG_WR(bp, CFC_REG_DEBUG0, 0); 6397 6398 if (CHIP_IS_E1(bp)) { 6399 /* read NIG statistic 6400 to see if this is our first up since powerup */ 6401 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6402 val = *bnx2x_sp(bp, wb_data[0]); 6403 6404 /* do internal memory self test */ 6405 if ((val == 0) && bnx2x_int_mem_test(bp)) { 6406 BNX2X_ERR("internal mem self test failed\n"); 6407 return -EBUSY; 6408 } 6409 } 6410 6411 bnx2x_setup_fan_failure_detection(bp); 6412 6413 /* clear PXP2 attentions */ 6414 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 6415 6416 bnx2x_enable_blocks_attention(bp); 6417 bnx2x_enable_blocks_parity(bp); 6418 6419 if (!BP_NOMCP(bp)) { 6420 if (CHIP_IS_E1x(bp)) 6421 bnx2x__common_init_phy(bp); 6422 } else 6423 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 6424 6425 return 0; 6426} 6427 6428/** 6429 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. 6430 * 6431 * @bp: driver handle 6432 */ 6433static int bnx2x_init_hw_common_chip(struct bnx2x *bp) 6434{ 6435 int rc = bnx2x_init_hw_common(bp); 6436 6437 if (rc) 6438 return rc; 6439 6440 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 6441 if (!BP_NOMCP(bp)) 6442 bnx2x__common_init_phy(bp); 6443 6444 return 0; 6445} 6446 6447static int bnx2x_init_hw_port(struct bnx2x *bp) 6448{ 6449 int port = BP_PORT(bp); 6450 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 6451 u32 low, high; 6452 u32 val; 6453 6454 bnx2x__link_reset(bp); 6455 6456 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port); 6457 6458 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 6459 6460 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6461 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6462 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6463 6464 /* Timers bug workaround: disables the pf_master bit in pglue at 6465 * common phase, we need to enable it here before any dmae access are 6466 * attempted. Therefore we manually added the enable-master to the 6467 * port phase (it also happens in the function phase) 6468 */ 6469 if (!CHIP_IS_E1x(bp)) 6470 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6471 6472 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6473 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6474 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6475 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6476 6477 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6478 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6479 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6480 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6481 6482 /* QM cid (connection) count */ 6483 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); 6484 6485#ifdef BCM_CNIC 6486 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6487 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 6488 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 6489#endif 6490 6491 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6492 6493 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { 6494 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6495 6496 if (IS_MF(bp)) 6497 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 6498 else if (bp->dev->mtu > 4096) { 6499 if (bp->flags & ONE_PORT_FLAG) 6500 low = 160; 6501 else { 6502 val = bp->dev->mtu; 6503 /* (24*1024 + val*4)/256 */ 6504 low = 96 + (val/64) + 6505 ((val % 64) ? 1 : 0); 6506 } 6507 } else 6508 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 6509 high = low + 56; /* 14*1024/256 */ 6510 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 6511 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 6512 } 6513 6514 if (CHIP_MODE_IS_4_PORT(bp)) 6515 REG_WR(bp, (BP_PORT(bp) ? 6516 BRB1_REG_MAC_GUARANTIED_1 : 6517 BRB1_REG_MAC_GUARANTIED_0), 40); 6518 6519 6520 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6521 if (CHIP_IS_E3B0(bp)) 6522 /* Ovlan exists only if we are in multi-function + 6523 * switch-dependent mode, in switch-independent there 6524 * is no ovlan headers 6525 */ 6526 REG_WR(bp, BP_PORT(bp) ? 6527 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 6528 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 6529 (bp->path_has_ovlan ? 7 : 6)); 6530 6531 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6532 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6533 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6534 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6535 6536 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6537 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6538 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6539 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6540 6541 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6542 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6543 6544 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6545 6546 if (CHIP_IS_E1x(bp)) { 6547 /* configure PBF to work without PAUSE mtu 9000 */ 6548 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 6549 6550 /* update threshold */ 6551 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 6552 /* update init credit */ 6553 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 6554 6555 /* probe changes */ 6556 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 6557 udelay(50); 6558 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 6559 } 6560 6561#ifdef BCM_CNIC 6562 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6563#endif 6564 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6565 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6566 6567 if (CHIP_IS_E1(bp)) { 6568 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6569 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6570 } 6571 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6572 6573 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6574 6575 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6576 /* init aeu_mask_attn_func_0/1: 6577 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 6578 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 6579 * bits 4-7 are used for "per vn group attention" */ 6580 val = IS_MF(bp) ? 0xF7 : 0x7; 6581 /* Enable DCBX attention for all but E1 */ 6582 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 6583 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 6584 6585 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6586 6587 if (!CHIP_IS_E1x(bp)) { 6588 /* Bit-map indicating which L2 hdrs may appear after the 6589 * basic Ethernet header 6590 */ 6591 REG_WR(bp, BP_PORT(bp) ? 6592 NIG_REG_P1_HDRS_AFTER_BASIC : 6593 NIG_REG_P0_HDRS_AFTER_BASIC, 6594 IS_MF_SD(bp) ? 7 : 6); 6595 6596 if (CHIP_IS_E3(bp)) 6597 REG_WR(bp, BP_PORT(bp) ? 6598 NIG_REG_LLH1_MF_MODE : 6599 NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6600 } 6601 if (!CHIP_IS_E3(bp)) 6602 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 6603 6604 if (!CHIP_IS_E1(bp)) { 6605 /* 0x2 disable mf_ov, 0x1 enable */ 6606 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 6607 (IS_MF_SD(bp) ? 0x1 : 0x2)); 6608 6609 if (!CHIP_IS_E1x(bp)) { 6610 val = 0; 6611 switch (bp->mf_mode) { 6612 case MULTI_FUNCTION_SD: 6613 val = 1; 6614 break; 6615 case MULTI_FUNCTION_SI: 6616 val = 2; 6617 break; 6618 } 6619 6620 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : 6621 NIG_REG_LLH0_CLS_TYPE), val); 6622 } 6623 { 6624 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 6625 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 6626 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 6627 } 6628 } 6629 6630 6631 /* If SPIO5 is set to generate interrupts, enable it for this port */ 6632 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6633 if (val & (1 << MISC_REGISTERS_SPIO_5)) { 6634 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 6635 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 6636 val = REG_RD(bp, reg_addr); 6637 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 6638 REG_WR(bp, reg_addr, val); 6639 } 6640 6641 return 0; 6642} 6643 6644static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 6645{ 6646 int reg; 6647 6648 if (CHIP_IS_E1(bp)) 6649 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 6650 else 6651 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 6652 6653 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr)); 6654} 6655 6656static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) 6657{ 6658 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); 6659} 6660 6661static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) 6662{ 6663 u32 i, base = FUNC_ILT_BASE(func); 6664 for (i = base; i < base + ILT_PER_FUNC; i++) 6665 bnx2x_ilt_wr(bp, i, 0); 6666} 6667 6668static int bnx2x_init_hw_func(struct bnx2x *bp) 6669{ 6670 int port = BP_PORT(bp); 6671 int func = BP_FUNC(bp); 6672 int init_phase = PHASE_PF0 + func; 6673 struct bnx2x_ilt *ilt = BP_ILT(bp); 6674 u16 cdu_ilt_start; 6675 u32 addr, val; 6676 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 6677 int i, main_mem_width; 6678 6679 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func); 6680 6681 /* FLR cleanup - hmmm */ 6682 if (!CHIP_IS_E1x(bp)) 6683 bnx2x_pf_flr_clnup(bp); 6684 6685 /* set MSI reconfigure capability */ 6686 if (bp->common.int_block == INT_BLOCK_HC) { 6687 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 6688 val = REG_RD(bp, addr); 6689 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 6690 REG_WR(bp, addr, val); 6691 } 6692 6693 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6694 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6695 6696 ilt = BP_ILT(bp); 6697 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 6698 6699 for (i = 0; i < L2_ILT_LINES(bp); i++) { 6700 ilt->lines[cdu_ilt_start + i].page = 6701 bp->context.vcxt + (ILT_PAGE_CIDS * i); 6702 ilt->lines[cdu_ilt_start + i].page_mapping = 6703 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i); 6704 /* cdu ilt pages are allocated manually so there's no need to 6705 set the size */ 6706 } 6707 bnx2x_ilt_init_op(bp, INITOP_SET); 6708 6709#ifdef BCM_CNIC 6710 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); 6711 6712 /* T1 hash bits value determines the T1 number of entries */ 6713 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 6714#endif 6715 6716#ifndef BCM_CNIC 6717 /* set NIC mode */ 6718 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6719#endif /* BCM_CNIC */ 6720 6721 if (!CHIP_IS_E1x(bp)) { 6722 u32 pf_conf = IGU_PF_CONF_FUNC_EN; 6723 6724 /* Turn on a single ISR mode in IGU if driver is going to use 6725 * INT#x or MSI 6726 */ 6727 if (!(bp->flags & USING_MSIX_FLAG)) 6728 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 6729 /* 6730 * Timers workaround bug: function init part. 6731 * Need to wait 20msec after initializing ILT, 6732 * needed to make sure there are no requests in 6733 * one of the PXP internal queues with "old" ILT addresses 6734 */ 6735 msleep(20); 6736 /* 6737 * Master enable - Due to WB DMAE writes performed before this 6738 * register is re-initialized as part of the regular function 6739 * init 6740 */ 6741 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6742 /* Enable the function in IGU */ 6743 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); 6744 } 6745 6746 bp->dmae_ready = 1; 6747 6748 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6749 6750 if (!CHIP_IS_E1x(bp)) 6751 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); 6752 6753 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6754 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6755 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6756 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6757 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6758 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6759 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6760 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6761 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6762 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6763 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6764 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6765 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6766 6767 if (!CHIP_IS_E1x(bp)) 6768 REG_WR(bp, QM_REG_PF_EN, 1); 6769 6770 if (!CHIP_IS_E1x(bp)) { 6771 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6772 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6773 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6774 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6775 } 6776 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6777 6778 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6779 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6780 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6781 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6782 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6783 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6784 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6785 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6786 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6787 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6788 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6789 if (!CHIP_IS_E1x(bp)) 6790 REG_WR(bp, PBF_REG_DISABLE_PF, 0); 6791 6792 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6793 6794 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6795 6796 if (!CHIP_IS_E1x(bp)) 6797 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); 6798 6799 if (IS_MF(bp)) { 6800 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 6801 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); 6802 } 6803 6804 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6805 6806 /* HC init per function */ 6807 if (bp->common.int_block == INT_BLOCK_HC) { 6808 if (CHIP_IS_E1H(bp)) { 6809 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6810 6811 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6812 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6813 } 6814 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6815 6816 } else { 6817 int num_segs, sb_idx, prod_offset; 6818 6819 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6820 6821 if (!CHIP_IS_E1x(bp)) { 6822 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 6823 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 6824 } 6825 6826 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6827 6828 if (!CHIP_IS_E1x(bp)) { 6829 int dsb_idx = 0; 6830 /** 6831 * Producer memory: 6832 * E2 mode: address 0-135 match to the mapping memory; 6833 * 136 - PF0 default prod; 137 - PF1 default prod; 6834 * 138 - PF2 default prod; 139 - PF3 default prod; 6835 * 140 - PF0 attn prod; 141 - PF1 attn prod; 6836 * 142 - PF2 attn prod; 143 - PF3 attn prod; 6837 * 144-147 reserved. 6838 * 6839 * E1.5 mode - In backward compatible mode; 6840 * for non default SB; each even line in the memory 6841 * holds the U producer and each odd line hold 6842 * the C producer. The first 128 producers are for 6843 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 6844 * producers are for the DSB for each PF. 6845 * Each PF has five segments: (the order inside each 6846 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 6847 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 6848 * 144-147 attn prods; 6849 */ 6850 /* non-default-status-blocks */ 6851 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6852 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 6853 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { 6854 prod_offset = (bp->igu_base_sb + sb_idx) * 6855 num_segs; 6856 6857 for (i = 0; i < num_segs; i++) { 6858 addr = IGU_REG_PROD_CONS_MEMORY + 6859 (prod_offset + i) * 4; 6860 REG_WR(bp, addr, 0); 6861 } 6862 /* send consumer update with value 0 */ 6863 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, 6864 USTORM_ID, 0, IGU_INT_NOP, 1); 6865 bnx2x_igu_clear_sb(bp, 6866 bp->igu_base_sb + sb_idx); 6867 } 6868 6869 /* default-status-blocks */ 6870 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6871 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 6872 6873 if (CHIP_MODE_IS_4_PORT(bp)) 6874 dsb_idx = BP_FUNC(bp); 6875 else 6876 dsb_idx = BP_VN(bp); 6877 6878 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 6879 IGU_BC_BASE_DSB_PROD + dsb_idx : 6880 IGU_NORM_BASE_DSB_PROD + dsb_idx); 6881 6882 /* 6883 * igu prods come in chunks of E1HVN_MAX (4) - 6884 * does not matters what is the current chip mode 6885 */ 6886 for (i = 0; i < (num_segs * E1HVN_MAX); 6887 i += E1HVN_MAX) { 6888 addr = IGU_REG_PROD_CONS_MEMORY + 6889 (prod_offset + i)*4; 6890 REG_WR(bp, addr, 0); 6891 } 6892 /* send consumer update with 0 */ 6893 if (CHIP_INT_MODE_IS_BC(bp)) { 6894 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6895 USTORM_ID, 0, IGU_INT_NOP, 1); 6896 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6897 CSTORM_ID, 0, IGU_INT_NOP, 1); 6898 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6899 XSTORM_ID, 0, IGU_INT_NOP, 1); 6900 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6901 TSTORM_ID, 0, IGU_INT_NOP, 1); 6902 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6903 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6904 } else { 6905 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6906 USTORM_ID, 0, IGU_INT_NOP, 1); 6907 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6908 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6909 } 6910 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); 6911 6912 /* !!! these should become driver const once 6913 rf-tool supports split-68 const */ 6914 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 6915 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 6916 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 6917 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 6918 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 6919 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 6920 } 6921 } 6922 6923 /* Reset PCIE errors for debug */ 6924 REG_WR(bp, 0x2114, 0xffffffff); 6925 REG_WR(bp, 0x2120, 0xffffffff); 6926 6927 if (CHIP_IS_E1x(bp)) { 6928 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 6929 main_mem_base = HC_REG_MAIN_MEMORY + 6930 BP_PORT(bp) * (main_mem_size * 4); 6931 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 6932 main_mem_width = 8; 6933 6934 val = REG_RD(bp, main_mem_prty_clr); 6935 if (val) 6936 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC " 6937 "block during " 6938 "function init (0x%x)!\n", val); 6939 6940 /* Clear "false" parity errors in MSI-X table */ 6941 for (i = main_mem_base; 6942 i < main_mem_base + main_mem_size * 4; 6943 i += main_mem_width) { 6944 bnx2x_read_dmae(bp, i, main_mem_width / 4); 6945 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), 6946 i, main_mem_width / 4); 6947 } 6948 /* Clear HC parity attention */ 6949 REG_RD(bp, main_mem_prty_clr); 6950 } 6951 6952#ifdef BNX2X_STOP_ON_ERROR 6953 /* Enable STORMs SP logging */ 6954 REG_WR8(bp, BAR_USTRORM_INTMEM + 6955 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6956 REG_WR8(bp, BAR_TSTRORM_INTMEM + 6957 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6958 REG_WR8(bp, BAR_CSTRORM_INTMEM + 6959 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6960 REG_WR8(bp, BAR_XSTRORM_INTMEM + 6961 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6962#endif 6963 6964 bnx2x_phy_probe(&bp->link_params); 6965 6966 return 0; 6967} 6968 6969 6970void bnx2x_free_mem(struct bnx2x *bp) 6971{ 6972 /* fastpath */ 6973 bnx2x_free_fp_mem(bp); 6974 /* end of fastpath */ 6975 6976 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 6977 sizeof(struct host_sp_status_block)); 6978 6979 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 6980 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 6981 6982 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 6983 sizeof(struct bnx2x_slowpath)); 6984 6985 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping, 6986 bp->context.size); 6987 6988 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); 6989 6990 BNX2X_FREE(bp->ilt->lines); 6991 6992#ifdef BCM_CNIC 6993 if (!CHIP_IS_E1x(bp)) 6994 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, 6995 sizeof(struct host_hc_status_block_e2)); 6996 else 6997 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, 6998 sizeof(struct host_hc_status_block_e1x)); 6999 7000 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 7001#endif 7002 7003 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 7004 7005 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, 7006 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7007} 7008 7009static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) 7010{ 7011 int num_groups; 7012 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1; 7013 7014 /* number of queues for statistics is number of eth queues + FCoE */ 7015 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats; 7016 7017 /* Total number of FW statistics requests = 7018 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats + 7019 * num of queues 7020 */ 7021 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats; 7022 7023 7024 /* Request is built from stats_query_header and an array of 7025 * stats_query_cmd_group each of which contains 7026 * STATS_QUERY_CMD_COUNT rules. The real number or requests is 7027 * configured in the stats_query_header. 7028 */ 7029 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) + 7030 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0); 7031 7032 bp->fw_stats_req_sz = sizeof(struct stats_query_header) + 7033 num_groups * sizeof(struct stats_query_cmd_group); 7034 7035 /* Data for statistics requests + stats_conter 7036 * 7037 * stats_counter holds per-STORM counters that are incremented 7038 * when STORM has finished with the current request. 7039 * 7040 * memory for FCoE offloaded statistics are counted anyway, 7041 * even if they will not be sent. 7042 */ 7043 bp->fw_stats_data_sz = sizeof(struct per_port_stats) + 7044 sizeof(struct per_pf_stats) + 7045 sizeof(struct fcoe_statistics_params) + 7046 sizeof(struct per_queue_stats) * num_queue_stats + 7047 sizeof(struct stats_counter); 7048 7049 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, 7050 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7051 7052 /* Set shortcuts */ 7053 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; 7054 bp->fw_stats_req_mapping = bp->fw_stats_mapping; 7055 7056 bp->fw_stats_data = (struct bnx2x_fw_stats_data *) 7057 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); 7058 7059 bp->fw_stats_data_mapping = bp->fw_stats_mapping + 7060 bp->fw_stats_req_sz; 7061 return 0; 7062 7063alloc_mem_err: 7064 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 7065 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7066 return -ENOMEM; 7067} 7068 7069 7070int bnx2x_alloc_mem(struct bnx2x *bp) 7071{ 7072#ifdef BCM_CNIC 7073 if (!CHIP_IS_E1x(bp)) 7074 /* size = the status block + ramrod buffers */ 7075 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, 7076 sizeof(struct host_hc_status_block_e2)); 7077 else 7078 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, 7079 sizeof(struct host_hc_status_block_e1x)); 7080 7081 /* allocate searcher T2 table */ 7082 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); 7083#endif 7084 7085 7086 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, 7087 sizeof(struct host_sp_status_block)); 7088 7089 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, 7090 sizeof(struct bnx2x_slowpath)); 7091 7092 /* Allocated memory for FW statistics */ 7093 if (bnx2x_alloc_fw_stats_mem(bp)) 7094 goto alloc_mem_err; 7095 7096 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); 7097 7098 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping, 7099 bp->context.size); 7100 7101 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); 7102 7103 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) 7104 goto alloc_mem_err; 7105 7106 /* Slow path ring */ 7107 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); 7108 7109 /* EQ */ 7110 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, 7111 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7112 7113 7114 /* fastpath */ 7115 /* need to be done at the end, since it's self adjusting to amount 7116 * of memory available for RSS queues 7117 */ 7118 if (bnx2x_alloc_fp_mem(bp)) 7119 goto alloc_mem_err; 7120 return 0; 7121 7122alloc_mem_err: 7123 bnx2x_free_mem(bp); 7124 return -ENOMEM; 7125} 7126 7127/* 7128 * Init service functions 7129 */ 7130 7131int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 7132 struct bnx2x_vlan_mac_obj *obj, bool set, 7133 int mac_type, unsigned long *ramrod_flags) 7134{ 7135 int rc; 7136 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 7137 7138 memset(&ramrod_param, 0, sizeof(ramrod_param)); 7139 7140 /* Fill general parameters */ 7141 ramrod_param.vlan_mac_obj = obj; 7142 ramrod_param.ramrod_flags = *ramrod_flags; 7143 7144 /* Fill a user request section if needed */ 7145 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 7146 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 7147 7148 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 7149 7150 /* Set the command: ADD or DEL */ 7151 if (set) 7152 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 7153 else 7154 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 7155 } 7156 7157 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 7158 if (rc < 0) 7159 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); 7160 return rc; 7161} 7162 7163int bnx2x_del_all_macs(struct bnx2x *bp, 7164 struct bnx2x_vlan_mac_obj *mac_obj, 7165 int mac_type, bool wait_for_comp) 7166{ 7167 int rc; 7168 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 7169 7170 /* Wait for completion of requested */ 7171 if (wait_for_comp) 7172 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7173 7174 /* Set the mac type of addresses we want to clear */ 7175 __set_bit(mac_type, &vlan_mac_flags); 7176 7177 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); 7178 if (rc < 0) 7179 BNX2X_ERR("Failed to delete MACs: %d\n", rc); 7180 7181 return rc; 7182} 7183 7184int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) 7185{ 7186 unsigned long ramrod_flags = 0; 7187 7188#ifdef BCM_CNIC 7189 if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_ISCSI_SD(bp)) { 7190 DP(NETIF_MSG_IFUP, "Ignoring Zero MAC for iSCSI SD mode\n"); 7191 return 0; 7192 } 7193#endif 7194 7195 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); 7196 7197 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7198 /* Eth MAC is set on RSS leading client (fp[0]) */ 7199 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set, 7200 BNX2X_ETH_MAC, &ramrod_flags); 7201} 7202 7203int bnx2x_setup_leading(struct bnx2x *bp) 7204{ 7205 return bnx2x_setup_queue(bp, &bp->fp[0], 1); 7206} 7207 7208/** 7209 * bnx2x_set_int_mode - configure interrupt mode 7210 * 7211 * @bp: driver handle 7212 * 7213 * In case of MSI-X it will also try to enable MSI-X. 7214 */ 7215static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) 7216{ 7217 switch (int_mode) { 7218 case INT_MODE_MSI: 7219 bnx2x_enable_msi(bp); 7220 /* falling through... */ 7221 case INT_MODE_INTx: 7222 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7223 DP(NETIF_MSG_IFUP, "set number of queues to 1\n"); 7224 break; 7225 default: 7226 /* Set number of queues according to bp->multi_mode value */ 7227 bnx2x_set_num_queues(bp); 7228 7229 DP(NETIF_MSG_IFUP, "set number of queues to %d\n", 7230 bp->num_queues); 7231 7232 /* if we can't use MSI-X we only need one fp, 7233 * so try to enable MSI-X with the requested number of fp's 7234 * and fallback to MSI or legacy INTx with one fp 7235 */ 7236 if (bnx2x_enable_msix(bp)) { 7237 /* failed to enable MSI-X */ 7238 if (bp->multi_mode) 7239 DP(NETIF_MSG_IFUP, 7240 "Multi requested but failed to " 7241 "enable MSI-X (%d), " 7242 "set number of queues to %d\n", 7243 bp->num_queues, 7244 1 + NON_ETH_CONTEXT_USE); 7245 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7246 7247 /* Try to enable MSI */ 7248 if (!(bp->flags & DISABLE_MSI_FLAG)) 7249 bnx2x_enable_msi(bp); 7250 } 7251 break; 7252 } 7253} 7254 7255/* must be called prioir to any HW initializations */ 7256static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) 7257{ 7258 return L2_ILT_LINES(bp); 7259} 7260 7261void bnx2x_ilt_set_info(struct bnx2x *bp) 7262{ 7263 struct ilt_client_info *ilt_client; 7264 struct bnx2x_ilt *ilt = BP_ILT(bp); 7265 u16 line = 0; 7266 7267 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); 7268 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); 7269 7270 /* CDU */ 7271 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 7272 ilt_client->client_num = ILT_CLIENT_CDU; 7273 ilt_client->page_size = CDU_ILT_PAGE_SZ; 7274 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 7275 ilt_client->start = line; 7276 line += bnx2x_cid_ilt_lines(bp); 7277#ifdef BCM_CNIC 7278 line += CNIC_ILT_LINES; 7279#endif 7280 ilt_client->end = line - 1; 7281 7282 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, " 7283 "flags 0x%x, hw psz %d\n", 7284 ilt_client->start, 7285 ilt_client->end, 7286 ilt_client->page_size, 7287 ilt_client->flags, 7288 ilog2(ilt_client->page_size >> 12)); 7289 7290 /* QM */ 7291 if (QM_INIT(bp->qm_cid_count)) { 7292 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 7293 ilt_client->client_num = ILT_CLIENT_QM; 7294 ilt_client->page_size = QM_ILT_PAGE_SZ; 7295 ilt_client->flags = 0; 7296 ilt_client->start = line; 7297 7298 /* 4 bytes for each cid */ 7299 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 7300 QM_ILT_PAGE_SZ); 7301 7302 ilt_client->end = line - 1; 7303 7304 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, " 7305 "flags 0x%x, hw psz %d\n", 7306 ilt_client->start, 7307 ilt_client->end, 7308 ilt_client->page_size, 7309 ilt_client->flags, 7310 ilog2(ilt_client->page_size >> 12)); 7311 7312 } 7313 /* SRC */ 7314 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 7315#ifdef BCM_CNIC 7316 ilt_client->client_num = ILT_CLIENT_SRC; 7317 ilt_client->page_size = SRC_ILT_PAGE_SZ; 7318 ilt_client->flags = 0; 7319 ilt_client->start = line; 7320 line += SRC_ILT_LINES; 7321 ilt_client->end = line - 1; 7322 7323 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, " 7324 "flags 0x%x, hw psz %d\n", 7325 ilt_client->start, 7326 ilt_client->end, 7327 ilt_client->page_size, 7328 ilt_client->flags, 7329 ilog2(ilt_client->page_size >> 12)); 7330 7331#else 7332 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7333#endif 7334 7335 /* TM */ 7336 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 7337#ifdef BCM_CNIC 7338 ilt_client->client_num = ILT_CLIENT_TM; 7339 ilt_client->page_size = TM_ILT_PAGE_SZ; 7340 ilt_client->flags = 0; 7341 ilt_client->start = line; 7342 line += TM_ILT_LINES; 7343 ilt_client->end = line - 1; 7344 7345 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, " 7346 "flags 0x%x, hw psz %d\n", 7347 ilt_client->start, 7348 ilt_client->end, 7349 ilt_client->page_size, 7350 ilt_client->flags, 7351 ilog2(ilt_client->page_size >> 12)); 7352 7353#else 7354 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7355#endif 7356 BUG_ON(line > ILT_MAX_LINES); 7357} 7358 7359/** 7360 * bnx2x_pf_q_prep_init - prepare INIT transition parameters 7361 * 7362 * @bp: driver handle 7363 * @fp: pointer to fastpath 7364 * @init_params: pointer to parameters structure 7365 * 7366 * parameters configured: 7367 * - HC configuration 7368 * - Queue's CDU context 7369 */ 7370static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp, 7371 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) 7372{ 7373 7374 u8 cos; 7375 /* FCoE Queue uses Default SB, thus has no HC capabilities */ 7376 if (!IS_FCOE_FP(fp)) { 7377 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); 7378 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); 7379 7380 /* If HC is supporterd, enable host coalescing in the transition 7381 * to INIT state. 7382 */ 7383 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); 7384 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); 7385 7386 /* HC rate */ 7387 init_params->rx.hc_rate = bp->rx_ticks ? 7388 (1000000 / bp->rx_ticks) : 0; 7389 init_params->tx.hc_rate = bp->tx_ticks ? 7390 (1000000 / bp->tx_ticks) : 0; 7391 7392 /* FW SB ID */ 7393 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = 7394 fp->fw_sb_id; 7395 7396 /* 7397 * CQ index among the SB indices: FCoE clients uses the default 7398 * SB, therefore it's different. 7399 */ 7400 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 7401 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 7402 } 7403 7404 /* set maximum number of COSs supported by this queue */ 7405 init_params->max_cos = fp->max_cos; 7406 7407 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n", 7408 fp->index, init_params->max_cos); 7409 7410 /* set the context pointers queue object */ 7411 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) 7412 init_params->cxts[cos] = 7413 &bp->context.vcxt[fp->txdata[cos].cid].eth; 7414} 7415 7416int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7417 struct bnx2x_queue_state_params *q_params, 7418 struct bnx2x_queue_setup_tx_only_params *tx_only_params, 7419 int tx_index, bool leading) 7420{ 7421 memset(tx_only_params, 0, sizeof(*tx_only_params)); 7422 7423 /* Set the command */ 7424 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 7425 7426 /* Set tx-only QUEUE flags: don't zero statistics */ 7427 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); 7428 7429 /* choose the index of the cid to send the slow path on */ 7430 tx_only_params->cid_index = tx_index; 7431 7432 /* Set general TX_ONLY_SETUP parameters */ 7433 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); 7434 7435 /* Set Tx TX_ONLY_SETUP parameters */ 7436 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 7437 7438 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:" 7439 "cos %d, primary cid %d, cid %d, " 7440 "client id %d, sp-client id %d, flags %lx\n", 7441 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 7442 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 7443 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 7444 7445 /* send the ramrod */ 7446 return bnx2x_queue_state_change(bp, q_params); 7447} 7448 7449 7450/** 7451 * bnx2x_setup_queue - setup queue 7452 * 7453 * @bp: driver handle 7454 * @fp: pointer to fastpath 7455 * @leading: is leading 7456 * 7457 * This function performs 2 steps in a Queue state machine 7458 * actually: 1) RESET->INIT 2) INIT->SETUP 7459 */ 7460 7461int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7462 bool leading) 7463{ 7464 struct bnx2x_queue_state_params q_params = {0}; 7465 struct bnx2x_queue_setup_params *setup_params = 7466 &q_params.params.setup; 7467 struct bnx2x_queue_setup_tx_only_params *tx_only_params = 7468 &q_params.params.tx_only; 7469 int rc; 7470 u8 tx_index; 7471 7472 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index); 7473 7474 /* reset IGU state skip FCoE L2 queue */ 7475 if (!IS_FCOE_FP(fp)) 7476 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, 7477 IGU_INT_ENABLE, 0); 7478 7479 q_params.q_obj = &fp->q_obj; 7480 /* We want to wait for completion in this context */ 7481 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7482 7483 /* Prepare the INIT parameters */ 7484 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); 7485 7486 /* Set the command */ 7487 q_params.cmd = BNX2X_Q_CMD_INIT; 7488 7489 /* Change the state to INIT */ 7490 rc = bnx2x_queue_state_change(bp, &q_params); 7491 if (rc) { 7492 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); 7493 return rc; 7494 } 7495 7496 DP(BNX2X_MSG_SP, "init complete\n"); 7497 7498 7499 /* Now move the Queue to the SETUP state... */ 7500 memset(setup_params, 0, sizeof(*setup_params)); 7501 7502 /* Set QUEUE flags */ 7503 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); 7504 7505 /* Set general SETUP parameters */ 7506 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, 7507 FIRST_TX_COS_INDEX); 7508 7509 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, 7510 &setup_params->rxq_params); 7511 7512 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, 7513 FIRST_TX_COS_INDEX); 7514 7515 /* Set the command */ 7516 q_params.cmd = BNX2X_Q_CMD_SETUP; 7517 7518 /* Change the state to SETUP */ 7519 rc = bnx2x_queue_state_change(bp, &q_params); 7520 if (rc) { 7521 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); 7522 return rc; 7523 } 7524 7525 /* loop through the relevant tx-only indices */ 7526 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7527 tx_index < fp->max_cos; 7528 tx_index++) { 7529 7530 /* prepare and send tx-only ramrod*/ 7531 rc = bnx2x_setup_tx_only(bp, fp, &q_params, 7532 tx_only_params, tx_index, leading); 7533 if (rc) { 7534 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", 7535 fp->index, tx_index); 7536 return rc; 7537 } 7538 } 7539 7540 return rc; 7541} 7542 7543static int bnx2x_stop_queue(struct bnx2x *bp, int index) 7544{ 7545 struct bnx2x_fastpath *fp = &bp->fp[index]; 7546 struct bnx2x_fp_txdata *txdata; 7547 struct bnx2x_queue_state_params q_params = {0}; 7548 int rc, tx_index; 7549 7550 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid); 7551 7552 q_params.q_obj = &fp->q_obj; 7553 /* We want to wait for completion in this context */ 7554 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7555 7556 7557 /* close tx-only connections */ 7558 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7559 tx_index < fp->max_cos; 7560 tx_index++){ 7561 7562 /* ascertain this is a normal queue*/ 7563 txdata = &fp->txdata[tx_index]; 7564 7565 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n", 7566 txdata->txq_index); 7567 7568 /* send halt terminate on tx-only connection */ 7569 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7570 memset(&q_params.params.terminate, 0, 7571 sizeof(q_params.params.terminate)); 7572 q_params.params.terminate.cid_index = tx_index; 7573 7574 rc = bnx2x_queue_state_change(bp, &q_params); 7575 if (rc) 7576 return rc; 7577 7578 /* send halt terminate on tx-only connection */ 7579 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7580 memset(&q_params.params.cfc_del, 0, 7581 sizeof(q_params.params.cfc_del)); 7582 q_params.params.cfc_del.cid_index = tx_index; 7583 rc = bnx2x_queue_state_change(bp, &q_params); 7584 if (rc) 7585 return rc; 7586 } 7587 /* Stop the primary connection: */ 7588 /* ...halt the connection */ 7589 q_params.cmd = BNX2X_Q_CMD_HALT; 7590 rc = bnx2x_queue_state_change(bp, &q_params); 7591 if (rc) 7592 return rc; 7593 7594 /* ...terminate the connection */ 7595 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7596 memset(&q_params.params.terminate, 0, 7597 sizeof(q_params.params.terminate)); 7598 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 7599 rc = bnx2x_queue_state_change(bp, &q_params); 7600 if (rc) 7601 return rc; 7602 /* ...delete cfc entry */ 7603 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7604 memset(&q_params.params.cfc_del, 0, 7605 sizeof(q_params.params.cfc_del)); 7606 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 7607 return bnx2x_queue_state_change(bp, &q_params); 7608} 7609 7610 7611static void bnx2x_reset_func(struct bnx2x *bp) 7612{ 7613 int port = BP_PORT(bp); 7614 int func = BP_FUNC(bp); 7615 int i; 7616 7617 /* Disable the function in the FW */ 7618 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 7619 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 7620 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 7621 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 7622 7623 /* FP SBs */ 7624 for_each_eth_queue(bp, i) { 7625 struct bnx2x_fastpath *fp = &bp->fp[i]; 7626 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7627 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 7628 SB_DISABLED); 7629 } 7630 7631#ifdef BCM_CNIC 7632 /* CNIC SB */ 7633 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7634 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), 7635 SB_DISABLED); 7636#endif 7637 /* SP SB */ 7638 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7639 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 7640 SB_DISABLED); 7641 7642 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) 7643 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 7644 0); 7645 7646 /* Configure IGU */ 7647 if (bp->common.int_block == INT_BLOCK_HC) { 7648 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7649 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7650 } else { 7651 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 7652 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 7653 } 7654 7655#ifdef BCM_CNIC 7656 /* Disable Timer scan */ 7657 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 7658 /* 7659 * Wait for at least 10ms and up to 2 second for the timers scan to 7660 * complete 7661 */ 7662 for (i = 0; i < 200; i++) { 7663 msleep(10); 7664 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) 7665 break; 7666 } 7667#endif 7668 /* Clear ILT */ 7669 bnx2x_clear_func_ilt(bp, func); 7670 7671 /* Timers workaround bug for E2: if this is vnic-3, 7672 * we need to set the entire ilt range for this timers. 7673 */ 7674 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { 7675 struct ilt_client_info ilt_cli; 7676 /* use dummy TM client */ 7677 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 7678 ilt_cli.start = 0; 7679 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 7680 ilt_cli.client_num = ILT_CLIENT_TM; 7681 7682 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); 7683 } 7684 7685 /* this assumes that reset_port() called before reset_func()*/ 7686 if (!CHIP_IS_E1x(bp)) 7687 bnx2x_pf_disable(bp); 7688 7689 bp->dmae_ready = 0; 7690} 7691 7692static void bnx2x_reset_port(struct bnx2x *bp) 7693{ 7694 int port = BP_PORT(bp); 7695 u32 val; 7696 7697 /* Reset physical Link */ 7698 bnx2x__link_reset(bp); 7699 7700 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 7701 7702 /* Do not rcv packets to BRB */ 7703 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 7704 /* Do not direct rcv packets that are not for MCP to the BRB */ 7705 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 7706 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 7707 7708 /* Configure AEU */ 7709 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 7710 7711 msleep(100); 7712 /* Check for BRB port occupancy */ 7713 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 7714 if (val) 7715 DP(NETIF_MSG_IFDOWN, 7716 "BRB1 is not empty %d blocks are occupied\n", val); 7717 7718 /* TODO: Close Doorbell port? */ 7719} 7720 7721static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) 7722{ 7723 struct bnx2x_func_state_params func_params = {0}; 7724 7725 /* Prepare parameters for function state transitions */ 7726 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7727 7728 func_params.f_obj = &bp->func_obj; 7729 func_params.cmd = BNX2X_F_CMD_HW_RESET; 7730 7731 func_params.params.hw_init.load_phase = load_code; 7732 7733 return bnx2x_func_state_change(bp, &func_params); 7734} 7735 7736static inline int bnx2x_func_stop(struct bnx2x *bp) 7737{ 7738 struct bnx2x_func_state_params func_params = {0}; 7739 int rc; 7740 7741 /* Prepare parameters for function state transitions */ 7742 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7743 func_params.f_obj = &bp->func_obj; 7744 func_params.cmd = BNX2X_F_CMD_STOP; 7745 7746 /* 7747 * Try to stop the function the 'good way'. If fails (in case 7748 * of a parity error during bnx2x_chip_cleanup()) and we are 7749 * not in a debug mode, perform a state transaction in order to 7750 * enable further HW_RESET transaction. 7751 */ 7752 rc = bnx2x_func_state_change(bp, &func_params); 7753 if (rc) { 7754#ifdef BNX2X_STOP_ON_ERROR 7755 return rc; 7756#else 7757 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry " 7758 "transaction\n"); 7759 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 7760 return bnx2x_func_state_change(bp, &func_params); 7761#endif 7762 } 7763 7764 return 0; 7765} 7766 7767/** 7768 * bnx2x_send_unload_req - request unload mode from the MCP. 7769 * 7770 * @bp: driver handle 7771 * @unload_mode: requested function's unload mode 7772 * 7773 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 7774 */ 7775u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 7776{ 7777 u32 reset_code = 0; 7778 int port = BP_PORT(bp); 7779 7780 /* Select the UNLOAD request mode */ 7781 if (unload_mode == UNLOAD_NORMAL) 7782 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7783 7784 else if (bp->flags & NO_WOL_FLAG) 7785 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 7786 7787 else if (bp->wol) { 7788 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 7789 u8 *mac_addr = bp->dev->dev_addr; 7790 u32 val; 7791 u16 pmc; 7792 7793 /* The mac address is written to entries 1-4 to 7794 * preserve entry 0 which is used by the PMF 7795 */ 7796 u8 entry = (BP_VN(bp) + 1)*8; 7797 7798 val = (mac_addr[0] << 8) | mac_addr[1]; 7799 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 7800 7801 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 7802 (mac_addr[4] << 8) | mac_addr[5]; 7803 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 7804 7805 /* Enable the PME and clear the status */ 7806 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); 7807 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; 7808 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); 7809 7810 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 7811 7812 } else 7813 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7814 7815 /* Send the request to the MCP */ 7816 if (!BP_NOMCP(bp)) 7817 reset_code = bnx2x_fw_command(bp, reset_code, 0); 7818 else { 7819 int path = BP_PATH(bp); 7820 7821 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] " 7822 "%d, %d, %d\n", 7823 path, load_count[path][0], load_count[path][1], 7824 load_count[path][2]); 7825 load_count[path][0]--; 7826 load_count[path][1 + port]--; 7827 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] " 7828 "%d, %d, %d\n", 7829 path, load_count[path][0], load_count[path][1], 7830 load_count[path][2]); 7831 if (load_count[path][0] == 0) 7832 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 7833 else if (load_count[path][1 + port] == 0) 7834 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 7835 else 7836 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 7837 } 7838 7839 return reset_code; 7840} 7841 7842/** 7843 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 7844 * 7845 * @bp: driver handle 7846 */ 7847void bnx2x_send_unload_done(struct bnx2x *bp) 7848{ 7849 /* Report UNLOAD_DONE to MCP */ 7850 if (!BP_NOMCP(bp)) 7851 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 7852} 7853 7854static inline int bnx2x_func_wait_started(struct bnx2x *bp) 7855{ 7856 int tout = 50; 7857 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 7858 7859 if (!bp->port.pmf) 7860 return 0; 7861 7862 /* 7863 * (assumption: No Attention from MCP at this stage) 7864 * PMF probably in the middle of TXdisable/enable transaction 7865 * 1. Sync IRS for default SB 7866 * 2. Sync SP queue - this guarantes us that attention handling started 7867 * 3. Wait, that TXdisable/enable transaction completes 7868 * 7869 * 1+2 guranty that if DCBx attention was scheduled it already changed 7870 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy 7871 * received complettion for the transaction the state is TX_STOPPED. 7872 * State will return to STARTED after completion of TX_STOPPED-->STARTED 7873 * transaction. 7874 */ 7875 7876 /* make sure default SB ISR is done */ 7877 if (msix) 7878 synchronize_irq(bp->msix_table[0].vector); 7879 else 7880 synchronize_irq(bp->pdev->irq); 7881 7882 flush_workqueue(bnx2x_wq); 7883 7884 while (bnx2x_func_get_state(bp, &bp->func_obj) != 7885 BNX2X_F_STATE_STARTED && tout--) 7886 msleep(20); 7887 7888 if (bnx2x_func_get_state(bp, &bp->func_obj) != 7889 BNX2X_F_STATE_STARTED) { 7890#ifdef BNX2X_STOP_ON_ERROR 7891 return -EBUSY; 7892#else 7893 /* 7894 * Failed to complete the transaction in a "good way" 7895 * Force both transactions with CLR bit 7896 */ 7897 struct bnx2x_func_state_params func_params = {0}; 7898 7899 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! " 7900 "Forcing STARTED-->TX_ST0PPED-->STARTED\n"); 7901 7902 func_params.f_obj = &bp->func_obj; 7903 __set_bit(RAMROD_DRV_CLR_ONLY, 7904 &func_params.ramrod_flags); 7905 7906 /* STARTED-->TX_ST0PPED */ 7907 func_params.cmd = BNX2X_F_CMD_TX_STOP; 7908 bnx2x_func_state_change(bp, &func_params); 7909 7910 /* TX_ST0PPED-->STARTED */ 7911 func_params.cmd = BNX2X_F_CMD_TX_START; 7912 return bnx2x_func_state_change(bp, &func_params); 7913#endif 7914 } 7915 7916 return 0; 7917} 7918 7919void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) 7920{ 7921 int port = BP_PORT(bp); 7922 int i, rc = 0; 7923 u8 cos; 7924 struct bnx2x_mcast_ramrod_params rparam = {0}; 7925 u32 reset_code; 7926 7927 /* Wait until tx fastpath tasks complete */ 7928 for_each_tx_queue(bp, i) { 7929 struct bnx2x_fastpath *fp = &bp->fp[i]; 7930 7931 for_each_cos_in_tx_queue(fp, cos) 7932 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]); 7933#ifdef BNX2X_STOP_ON_ERROR 7934 if (rc) 7935 return; 7936#endif 7937 } 7938 7939 /* Give HW time to discard old tx messages */ 7940 usleep_range(1000, 1000); 7941 7942 /* Clean all ETH MACs */ 7943 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false); 7944 if (rc < 0) 7945 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); 7946 7947 /* Clean up UC list */ 7948 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, 7949 true); 7950 if (rc < 0) 7951 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: " 7952 "%d\n", rc); 7953 7954 /* Disable LLH */ 7955 if (!CHIP_IS_E1(bp)) 7956 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 7957 7958 /* Set "drop all" (stop Rx). 7959 * We need to take a netif_addr_lock() here in order to prevent 7960 * a race between the completion code and this code. 7961 */ 7962 netif_addr_lock_bh(bp->dev); 7963 /* Schedule the rx_mode command */ 7964 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 7965 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 7966 else 7967 bnx2x_set_storm_rx_mode(bp); 7968 7969 /* Cleanup multicast configuration */ 7970 rparam.mcast_obj = &bp->mcast_obj; 7971 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 7972 if (rc < 0) 7973 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); 7974 7975 netif_addr_unlock_bh(bp->dev); 7976 7977 7978 7979 /* 7980 * Send the UNLOAD_REQUEST to the MCP. This will return if 7981 * this function should perform FUNC, PORT or COMMON HW 7982 * reset. 7983 */ 7984 reset_code = bnx2x_send_unload_req(bp, unload_mode); 7985 7986 /* 7987 * (assumption: No Attention from MCP at this stage) 7988 * PMF probably in the middle of TXdisable/enable transaction 7989 */ 7990 rc = bnx2x_func_wait_started(bp); 7991 if (rc) { 7992 BNX2X_ERR("bnx2x_func_wait_started failed\n"); 7993#ifdef BNX2X_STOP_ON_ERROR 7994 return; 7995#endif 7996 } 7997 7998 /* Close multi and leading connections 7999 * Completions for ramrods are collected in a synchronous way 8000 */ 8001 for_each_queue(bp, i) 8002 if (bnx2x_stop_queue(bp, i)) 8003#ifdef BNX2X_STOP_ON_ERROR 8004 return; 8005#else 8006 goto unload_error; 8007#endif 8008 /* If SP settings didn't get completed so far - something 8009 * very wrong has happen. 8010 */ 8011 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) 8012 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); 8013 8014#ifndef BNX2X_STOP_ON_ERROR 8015unload_error: 8016#endif 8017 rc = bnx2x_func_stop(bp); 8018 if (rc) { 8019 BNX2X_ERR("Function stop failed!\n"); 8020#ifdef BNX2X_STOP_ON_ERROR 8021 return; 8022#endif 8023 } 8024 8025 /* Disable HW interrupts, NAPI */ 8026 bnx2x_netif_stop(bp, 1); 8027 8028 /* Release IRQs */ 8029 bnx2x_free_irq(bp); 8030 8031 /* Reset the chip */ 8032 rc = bnx2x_reset_hw(bp, reset_code); 8033 if (rc) 8034 BNX2X_ERR("HW_RESET failed\n"); 8035 8036 8037 /* Report UNLOAD_DONE to MCP */ 8038 bnx2x_send_unload_done(bp); 8039} 8040 8041void bnx2x_disable_close_the_gate(struct bnx2x *bp) 8042{ 8043 u32 val; 8044 8045 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n"); 8046 8047 if (CHIP_IS_E1(bp)) { 8048 int port = BP_PORT(bp); 8049 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8050 MISC_REG_AEU_MASK_ATTN_FUNC_0; 8051 8052 val = REG_RD(bp, addr); 8053 val &= ~(0x300); 8054 REG_WR(bp, addr, val); 8055 } else { 8056 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); 8057 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 8058 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 8059 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); 8060 } 8061} 8062 8063/* Close gates #2, #3 and #4: */ 8064static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 8065{ 8066 u32 val; 8067 8068 /* Gates #2 and #4a are closed/opened for "not E1" only */ 8069 if (!CHIP_IS_E1(bp)) { 8070 /* #4 */ 8071 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 8072 /* #2 */ 8073 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 8074 } 8075 8076 /* #3 */ 8077 if (CHIP_IS_E1x(bp)) { 8078 /* Prevent interrupts from HC on both ports */ 8079 val = REG_RD(bp, HC_REG_CONFIG_1); 8080 REG_WR(bp, HC_REG_CONFIG_1, 8081 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 8082 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 8083 8084 val = REG_RD(bp, HC_REG_CONFIG_0); 8085 REG_WR(bp, HC_REG_CONFIG_0, 8086 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 8087 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 8088 } else { 8089 /* Prevent incomming interrupts in IGU */ 8090 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 8091 8092 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, 8093 (!close) ? 8094 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 8095 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 8096 } 8097 8098 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n", 8099 close ? "closing" : "opening"); 8100 mmiowb(); 8101} 8102 8103#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ 8104 8105static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) 8106{ 8107 /* Do some magic... */ 8108 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8109 *magic_val = val & SHARED_MF_CLP_MAGIC; 8110 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 8111} 8112 8113/** 8114 * bnx2x_clp_reset_done - restore the value of the `magic' bit. 8115 * 8116 * @bp: driver handle 8117 * @magic_val: old value of the `magic' bit. 8118 */ 8119static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 8120{ 8121 /* Restore the `magic' bit value... */ 8122 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8123 MF_CFG_WR(bp, shared_mf_config.clp_mb, 8124 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 8125} 8126 8127/** 8128 * bnx2x_reset_mcp_prep - prepare for MCP reset. 8129 * 8130 * @bp: driver handle 8131 * @magic_val: old value of 'magic' bit. 8132 * 8133 * Takes care of CLP configurations. 8134 */ 8135static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 8136{ 8137 u32 shmem; 8138 u32 validity_offset; 8139 8140 DP(NETIF_MSG_HW, "Starting\n"); 8141 8142 /* Set `magic' bit in order to save MF config */ 8143 if (!CHIP_IS_E1(bp)) 8144 bnx2x_clp_reset_prep(bp, magic_val); 8145 8146 /* Get shmem offset */ 8147 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8148 validity_offset = offsetof(struct shmem_region, validity_map[0]); 8149 8150 /* Clear validity map flags */ 8151 if (shmem > 0) 8152 REG_WR(bp, shmem + validity_offset, 0); 8153} 8154 8155#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 8156#define MCP_ONE_TIMEOUT 100 /* 100 ms */ 8157 8158/** 8159 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT 8160 * 8161 * @bp: driver handle 8162 */ 8163static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) 8164{ 8165 /* special handling for emulation and FPGA, 8166 wait 10 times longer */ 8167 if (CHIP_REV_IS_SLOW(bp)) 8168 msleep(MCP_ONE_TIMEOUT*10); 8169 else 8170 msleep(MCP_ONE_TIMEOUT); 8171} 8172 8173/* 8174 * initializes bp->common.shmem_base and waits for validity signature to appear 8175 */ 8176static int bnx2x_init_shmem(struct bnx2x *bp) 8177{ 8178 int cnt = 0; 8179 u32 val = 0; 8180 8181 do { 8182 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8183 if (bp->common.shmem_base) { 8184 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 8185 if (val & SHR_MEM_VALIDITY_MB) 8186 return 0; 8187 } 8188 8189 bnx2x_mcp_wait_one(bp); 8190 8191 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 8192 8193 BNX2X_ERR("BAD MCP validity signature\n"); 8194 8195 return -ENODEV; 8196} 8197 8198static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 8199{ 8200 int rc = bnx2x_init_shmem(bp); 8201 8202 /* Restore the `magic' bit value */ 8203 if (!CHIP_IS_E1(bp)) 8204 bnx2x_clp_reset_done(bp, magic_val); 8205 8206 return rc; 8207} 8208 8209static void bnx2x_pxp_prep(struct bnx2x *bp) 8210{ 8211 if (!CHIP_IS_E1(bp)) { 8212 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 8213 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 8214 mmiowb(); 8215 } 8216} 8217 8218/* 8219 * Reset the whole chip except for: 8220 * - PCIE core 8221 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by 8222 * one reset bit) 8223 * - IGU 8224 * - MISC (including AEU) 8225 * - GRC 8226 * - RBCN, RBCP 8227 */ 8228static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) 8229{ 8230 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 8231 u32 global_bits2, stay_reset2; 8232 8233 /* 8234 * Bits that have to be set in reset_mask2 if we want to reset 'global' 8235 * (per chip) blocks. 8236 */ 8237 global_bits2 = 8238 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 8239 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 8240 8241 /* Don't reset the following blocks */ 8242 not_reset_mask1 = 8243 MISC_REGISTERS_RESET_REG_1_RST_HC | 8244 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 8245 MISC_REGISTERS_RESET_REG_1_RST_PXP; 8246 8247 not_reset_mask2 = 8248 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 8249 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 8250 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 8251 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 8252 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 8253 MISC_REGISTERS_RESET_REG_2_RST_GRC | 8254 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 8255 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 8256 MISC_REGISTERS_RESET_REG_2_RST_ATC | 8257 MISC_REGISTERS_RESET_REG_2_PGLC; 8258 8259 /* 8260 * Keep the following blocks in reset: 8261 * - all xxMACs are handled by the bnx2x_link code. 8262 */ 8263 stay_reset2 = 8264 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 8265 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 8266 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 8267 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 8268 MISC_REGISTERS_RESET_REG_2_UMAC0 | 8269 MISC_REGISTERS_RESET_REG_2_UMAC1 | 8270 MISC_REGISTERS_RESET_REG_2_XMAC | 8271 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 8272 8273 /* Full reset masks according to the chip */ 8274 reset_mask1 = 0xffffffff; 8275 8276 if (CHIP_IS_E1(bp)) 8277 reset_mask2 = 0xffff; 8278 else if (CHIP_IS_E1H(bp)) 8279 reset_mask2 = 0x1ffff; 8280 else if (CHIP_IS_E2(bp)) 8281 reset_mask2 = 0xfffff; 8282 else /* CHIP_IS_E3 */ 8283 reset_mask2 = 0x3ffffff; 8284 8285 /* Don't reset global blocks unless we need to */ 8286 if (!global) 8287 reset_mask2 &= ~global_bits2; 8288 8289 /* 8290 * In case of attention in the QM, we need to reset PXP 8291 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 8292 * because otherwise QM reset would release 'close the gates' shortly 8293 * before resetting the PXP, then the PSWRQ would send a write 8294 * request to PGLUE. Then when PXP is reset, PGLUE would try to 8295 * read the payload data from PSWWR, but PSWWR would not 8296 * respond. The write queue in PGLUE would stuck, dmae commands 8297 * would not return. Therefore it's important to reset the second 8298 * reset register (containing the 8299 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 8300 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 8301 * bit). 8302 */ 8303 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8304 reset_mask2 & (~not_reset_mask2)); 8305 8306 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8307 reset_mask1 & (~not_reset_mask1)); 8308 8309 barrier(); 8310 mmiowb(); 8311 8312 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 8313 reset_mask2 & (~stay_reset2)); 8314 8315 barrier(); 8316 mmiowb(); 8317 8318 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 8319 mmiowb(); 8320} 8321 8322/** 8323 * bnx2x_er_poll_igu_vq - poll for pending writes bit. 8324 * It should get cleared in no more than 1s. 8325 * 8326 * @bp: driver handle 8327 * 8328 * It should get cleared in no more than 1s. Returns 0 if 8329 * pending writes bit gets cleared. 8330 */ 8331static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) 8332{ 8333 u32 cnt = 1000; 8334 u32 pend_bits = 0; 8335 8336 do { 8337 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); 8338 8339 if (pend_bits == 0) 8340 break; 8341 8342 usleep_range(1000, 1000); 8343 } while (cnt-- > 0); 8344 8345 if (cnt <= 0) { 8346 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", 8347 pend_bits); 8348 return -EBUSY; 8349 } 8350 8351 return 0; 8352} 8353 8354static int bnx2x_process_kill(struct bnx2x *bp, bool global) 8355{ 8356 int cnt = 1000; 8357 u32 val = 0; 8358 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 8359 8360 8361 /* Empty the Tetris buffer, wait for 1s */ 8362 do { 8363 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); 8364 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); 8365 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); 8366 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); 8367 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); 8368 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 8369 ((port_is_idle_0 & 0x1) == 0x1) && 8370 ((port_is_idle_1 & 0x1) == 0x1) && 8371 (pgl_exp_rom2 == 0xffffffff)) 8372 break; 8373 usleep_range(1000, 1000); 8374 } while (cnt-- > 0); 8375 8376 if (cnt <= 0) { 8377 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there" 8378 " are still" 8379 " outstanding read requests after 1s!\n"); 8380 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x," 8381 " port_is_idle_0=0x%08x," 8382 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 8383 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 8384 pgl_exp_rom2); 8385 return -EAGAIN; 8386 } 8387 8388 barrier(); 8389 8390 /* Close gates #2, #3 and #4 */ 8391 bnx2x_set_234_gates(bp, true); 8392 8393 /* Poll for IGU VQs for 57712 and newer chips */ 8394 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) 8395 return -EAGAIN; 8396 8397 8398 /* TBD: Indicate that "process kill" is in progress to MCP */ 8399 8400 /* Clear "unprepared" bit */ 8401 REG_WR(bp, MISC_REG_UNPREPARED, 0); 8402 barrier(); 8403 8404 /* Make sure all is written to the chip before the reset */ 8405 mmiowb(); 8406 8407 /* Wait for 1ms to empty GLUE and PCI-E core queues, 8408 * PSWHST, GRC and PSWRD Tetris buffer. 8409 */ 8410 usleep_range(1000, 1000); 8411 8412 /* Prepare to chip reset: */ 8413 /* MCP */ 8414 if (global) 8415 bnx2x_reset_mcp_prep(bp, &val); 8416 8417 /* PXP */ 8418 bnx2x_pxp_prep(bp); 8419 barrier(); 8420 8421 /* reset the chip */ 8422 bnx2x_process_kill_chip_reset(bp, global); 8423 barrier(); 8424 8425 /* Recover after reset: */ 8426 /* MCP */ 8427 if (global && bnx2x_reset_mcp_comp(bp, val)) 8428 return -EAGAIN; 8429 8430 /* TBD: Add resetting the NO_MCP mode DB here */ 8431 8432 /* PXP */ 8433 bnx2x_pxp_prep(bp); 8434 8435 /* Open the gates #2, #3 and #4 */ 8436 bnx2x_set_234_gates(bp, false); 8437 8438 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a 8439 * reset state, re-enable attentions. */ 8440 8441 return 0; 8442} 8443 8444int bnx2x_leader_reset(struct bnx2x *bp) 8445{ 8446 int rc = 0; 8447 bool global = bnx2x_reset_is_global(bp); 8448 8449 /* Try to recover after the failure */ 8450 if (bnx2x_process_kill(bp, global)) { 8451 netdev_err(bp->dev, "Something bad had happen on engine %d! " 8452 "Aii!\n", BP_PATH(bp)); 8453 rc = -EAGAIN; 8454 goto exit_leader_reset; 8455 } 8456 8457 /* 8458 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver 8459 * state. 8460 */ 8461 bnx2x_set_reset_done(bp); 8462 if (global) 8463 bnx2x_clear_reset_global(bp); 8464 8465exit_leader_reset: 8466 bp->is_leader = 0; 8467 bnx2x_release_leader_lock(bp); 8468 smp_mb(); 8469 return rc; 8470} 8471 8472static inline void bnx2x_recovery_failed(struct bnx2x *bp) 8473{ 8474 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); 8475 8476 /* Disconnect this device */ 8477 netif_device_detach(bp->dev); 8478 8479 /* 8480 * Block ifup for all function on this engine until "process kill" 8481 * or power cycle. 8482 */ 8483 bnx2x_set_reset_in_progress(bp); 8484 8485 /* Shut down the power */ 8486 bnx2x_set_power_state(bp, PCI_D3hot); 8487 8488 bp->recovery_state = BNX2X_RECOVERY_FAILED; 8489 8490 smp_mb(); 8491} 8492 8493/* 8494 * Assumption: runs under rtnl lock. This together with the fact 8495 * that it's called only from bnx2x_sp_rtnl() ensure that it 8496 * will never be called when netif_running(bp->dev) is false. 8497 */ 8498static void bnx2x_parity_recover(struct bnx2x *bp) 8499{ 8500 bool global = false; 8501 8502 DP(NETIF_MSG_HW, "Handling parity\n"); 8503 while (1) { 8504 switch (bp->recovery_state) { 8505 case BNX2X_RECOVERY_INIT: 8506 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 8507 bnx2x_chk_parity_attn(bp, &global, false); 8508 8509 /* Try to get a LEADER_LOCK HW lock */ 8510 if (bnx2x_trylock_leader_lock(bp)) { 8511 bnx2x_set_reset_in_progress(bp); 8512 /* 8513 * Check if there is a global attention and if 8514 * there was a global attention, set the global 8515 * reset bit. 8516 */ 8517 8518 if (global) 8519 bnx2x_set_reset_global(bp); 8520 8521 bp->is_leader = 1; 8522 } 8523 8524 /* Stop the driver */ 8525 /* If interface has been removed - break */ 8526 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) 8527 return; 8528 8529 bp->recovery_state = BNX2X_RECOVERY_WAIT; 8530 8531 /* 8532 * Reset MCP command sequence number and MCP mail box 8533 * sequence as we are going to reset the MCP. 8534 */ 8535 if (global) { 8536 bp->fw_seq = 0; 8537 bp->fw_drv_pulse_wr_seq = 0; 8538 } 8539 8540 /* Ensure "is_leader", MCP command sequence and 8541 * "recovery_state" update values are seen on other 8542 * CPUs. 8543 */ 8544 smp_mb(); 8545 break; 8546 8547 case BNX2X_RECOVERY_WAIT: 8548 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 8549 if (bp->is_leader) { 8550 int other_engine = BP_PATH(bp) ? 0 : 1; 8551 u32 other_load_counter = 8552 bnx2x_get_load_cnt(bp, other_engine); 8553 u32 load_counter = 8554 bnx2x_get_load_cnt(bp, BP_PATH(bp)); 8555 global = bnx2x_reset_is_global(bp); 8556 8557 /* 8558 * In case of a parity in a global block, let 8559 * the first leader that performs a 8560 * leader_reset() reset the global blocks in 8561 * order to clear global attentions. Otherwise 8562 * the the gates will remain closed for that 8563 * engine. 8564 */ 8565 if (load_counter || 8566 (global && other_load_counter)) { 8567 /* Wait until all other functions get 8568 * down. 8569 */ 8570 schedule_delayed_work(&bp->sp_rtnl_task, 8571 HZ/10); 8572 return; 8573 } else { 8574 /* If all other functions got down - 8575 * try to bring the chip back to 8576 * normal. In any case it's an exit 8577 * point for a leader. 8578 */ 8579 if (bnx2x_leader_reset(bp)) { 8580 bnx2x_recovery_failed(bp); 8581 return; 8582 } 8583 8584 /* If we are here, means that the 8585 * leader has succeeded and doesn't 8586 * want to be a leader any more. Try 8587 * to continue as a none-leader. 8588 */ 8589 break; 8590 } 8591 } else { /* non-leader */ 8592 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { 8593 /* Try to get a LEADER_LOCK HW lock as 8594 * long as a former leader may have 8595 * been unloaded by the user or 8596 * released a leadership by another 8597 * reason. 8598 */ 8599 if (bnx2x_trylock_leader_lock(bp)) { 8600 /* I'm a leader now! Restart a 8601 * switch case. 8602 */ 8603 bp->is_leader = 1; 8604 break; 8605 } 8606 8607 schedule_delayed_work(&bp->sp_rtnl_task, 8608 HZ/10); 8609 return; 8610 8611 } else { 8612 /* 8613 * If there was a global attention, wait 8614 * for it to be cleared. 8615 */ 8616 if (bnx2x_reset_is_global(bp)) { 8617 schedule_delayed_work( 8618 &bp->sp_rtnl_task, 8619 HZ/10); 8620 return; 8621 } 8622 8623 if (bnx2x_nic_load(bp, LOAD_NORMAL)) 8624 bnx2x_recovery_failed(bp); 8625 else { 8626 bp->recovery_state = 8627 BNX2X_RECOVERY_DONE; 8628 smp_mb(); 8629 } 8630 8631 return; 8632 } 8633 } 8634 default: 8635 return; 8636 } 8637 } 8638} 8639 8640/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is 8641 * scheduled on a general queue in order to prevent a dead lock. 8642 */ 8643static void bnx2x_sp_rtnl_task(struct work_struct *work) 8644{ 8645 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); 8646 8647 rtnl_lock(); 8648 8649 if (!netif_running(bp->dev)) 8650 goto sp_rtnl_exit; 8651 8652 /* if stop on error is defined no recovery flows should be executed */ 8653#ifdef BNX2X_STOP_ON_ERROR 8654 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined " 8655 "so reset not done to allow debug dump,\n" 8656 "you will need to reboot when done\n"); 8657 goto sp_rtnl_not_reset; 8658#endif 8659 8660 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { 8661 /* 8662 * Clear all pending SP commands as we are going to reset the 8663 * function anyway. 8664 */ 8665 bp->sp_rtnl_state = 0; 8666 smp_mb(); 8667 8668 bnx2x_parity_recover(bp); 8669 8670 goto sp_rtnl_exit; 8671 } 8672 8673 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { 8674 /* 8675 * Clear all pending SP commands as we are going to reset the 8676 * function anyway. 8677 */ 8678 bp->sp_rtnl_state = 0; 8679 smp_mb(); 8680 8681 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 8682 bnx2x_nic_load(bp, LOAD_NORMAL); 8683 8684 goto sp_rtnl_exit; 8685 } 8686#ifdef BNX2X_STOP_ON_ERROR 8687sp_rtnl_not_reset: 8688#endif 8689 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) 8690 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); 8691 8692 /* 8693 * in case of fan failure we need to reset id if the "stop on error" 8694 * debug flag is set, since we trying to prevent permanent overheating 8695 * damage 8696 */ 8697 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { 8698 DP(BNX2X_MSG_SP, "fan failure detected. Unloading driver\n"); 8699 netif_device_detach(bp->dev); 8700 bnx2x_close(bp->dev); 8701 } 8702 8703sp_rtnl_exit: 8704 rtnl_unlock(); 8705} 8706 8707/* end of nic load/unload */ 8708 8709static void bnx2x_period_task(struct work_struct *work) 8710{ 8711 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); 8712 8713 if (!netif_running(bp->dev)) 8714 goto period_task_exit; 8715 8716 if (CHIP_REV_IS_SLOW(bp)) { 8717 BNX2X_ERR("period task called on emulation, ignoring\n"); 8718 goto period_task_exit; 8719 } 8720 8721 bnx2x_acquire_phy_lock(bp); 8722 /* 8723 * The barrier is needed to ensure the ordering between the writing to 8724 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and 8725 * the reading here. 8726 */ 8727 smp_mb(); 8728 if (bp->port.pmf) { 8729 bnx2x_period_func(&bp->link_params, &bp->link_vars); 8730 8731 /* Re-queue task in 1 sec */ 8732 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); 8733 } 8734 8735 bnx2x_release_phy_lock(bp); 8736period_task_exit: 8737 return; 8738} 8739 8740/* 8741 * Init service functions 8742 */ 8743 8744static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) 8745{ 8746 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; 8747 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; 8748 return base + (BP_ABS_FUNC(bp)) * stride; 8749} 8750 8751static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) 8752{ 8753 u32 reg = bnx2x_get_pretend_reg(bp); 8754 8755 /* Flush all outstanding writes */ 8756 mmiowb(); 8757 8758 /* Pretend to be function 0 */ 8759 REG_WR(bp, reg, 0); 8760 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ 8761 8762 /* From now we are in the "like-E1" mode */ 8763 bnx2x_int_disable(bp); 8764 8765 /* Flush all outstanding writes */ 8766 mmiowb(); 8767 8768 /* Restore the original function */ 8769 REG_WR(bp, reg, BP_ABS_FUNC(bp)); 8770 REG_RD(bp, reg); 8771} 8772 8773static inline void bnx2x_undi_int_disable(struct bnx2x *bp) 8774{ 8775 if (CHIP_IS_E1(bp)) 8776 bnx2x_int_disable(bp); 8777 else 8778 bnx2x_undi_int_disable_e1h(bp); 8779} 8780 8781static void __devinit bnx2x_undi_unload(struct bnx2x *bp) 8782{ 8783 u32 val; 8784 8785 /* Check if there is any driver already loaded */ 8786 val = REG_RD(bp, MISC_REG_UNPREPARED); 8787 if (val == 0x1) { 8788 8789 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8790 /* 8791 * Check if it is the UNDI driver 8792 * UNDI driver initializes CID offset for normal bell to 0x7 8793 */ 8794 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 8795 if (val == 0x7) { 8796 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8797 /* save our pf_num */ 8798 int orig_pf_num = bp->pf_num; 8799 int port; 8800 u32 swap_en, swap_val, value; 8801 8802 /* clear the UNDI indication */ 8803 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 8804 8805 BNX2X_DEV_INFO("UNDI is active! reset device\n"); 8806 8807 /* try unload UNDI on port 0 */ 8808 bp->pf_num = 0; 8809 bp->fw_seq = 8810 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8811 DRV_MSG_SEQ_NUMBER_MASK); 8812 reset_code = bnx2x_fw_command(bp, reset_code, 0); 8813 8814 /* if UNDI is loaded on the other port */ 8815 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { 8816 8817 /* send "DONE" for previous unload */ 8818 bnx2x_fw_command(bp, 8819 DRV_MSG_CODE_UNLOAD_DONE, 0); 8820 8821 /* unload UNDI on port 1 */ 8822 bp->pf_num = 1; 8823 bp->fw_seq = 8824 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8825 DRV_MSG_SEQ_NUMBER_MASK); 8826 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8827 8828 bnx2x_fw_command(bp, reset_code, 0); 8829 } 8830 8831 bnx2x_undi_int_disable(bp); 8832 port = BP_PORT(bp); 8833 8834 /* close input traffic and wait for it */ 8835 /* Do not rcv packets to BRB */ 8836 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK : 8837 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0); 8838 /* Do not direct rcv packets that are not for MCP to 8839 * the BRB */ 8840 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 8841 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 8842 /* clear AEU */ 8843 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8844 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0); 8845 msleep(10); 8846 8847 /* save NIG port swap info */ 8848 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 8849 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 8850 /* reset device */ 8851 REG_WR(bp, 8852 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8853 0xd3ffffff); 8854 8855 value = 0x1400; 8856 if (CHIP_IS_E3(bp)) { 8857 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 8858 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 8859 } 8860 8861 REG_WR(bp, 8862 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8863 value); 8864 8865 /* take the NIG out of reset and restore swap values */ 8866 REG_WR(bp, 8867 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 8868 MISC_REGISTERS_RESET_REG_1_RST_NIG); 8869 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val); 8870 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en); 8871 8872 /* send unload done to the MCP */ 8873 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 8874 8875 /* restore our func and fw_seq */ 8876 bp->pf_num = orig_pf_num; 8877 bp->fw_seq = 8878 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8879 DRV_MSG_SEQ_NUMBER_MASK); 8880 } 8881 8882 /* now it's safe to release the lock */ 8883 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8884 } 8885} 8886 8887static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) 8888{ 8889 u32 val, val2, val3, val4, id, boot_mode; 8890 u16 pmc; 8891 8892 /* Get the chip revision id and number. */ 8893 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 8894 val = REG_RD(bp, MISC_REG_CHIP_NUM); 8895 id = ((val & 0xffff) << 16); 8896 val = REG_RD(bp, MISC_REG_CHIP_REV); 8897 id |= ((val & 0xf) << 12); 8898 val = REG_RD(bp, MISC_REG_CHIP_METAL); 8899 id |= ((val & 0xff) << 4); 8900 val = REG_RD(bp, MISC_REG_BOND_ID); 8901 id |= (val & 0xf); 8902 bp->common.chip_id = id; 8903 8904 /* Set doorbell size */ 8905 bp->db_size = (1 << BNX2X_DB_SHIFT); 8906 8907 if (!CHIP_IS_E1x(bp)) { 8908 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 8909 if ((val & 1) == 0) 8910 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); 8911 else 8912 val = (val >> 1) & 1; 8913 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : 8914 "2_PORT_MODE"); 8915 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : 8916 CHIP_2_PORT_MODE; 8917 8918 if (CHIP_MODE_IS_4_PORT(bp)) 8919 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ 8920 else 8921 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ 8922 } else { 8923 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ 8924 bp->pfid = bp->pf_num; /* 0..7 */ 8925 } 8926 8927 bp->link_params.chip_id = bp->common.chip_id; 8928 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 8929 8930 val = (REG_RD(bp, 0x2874) & 0x55); 8931 if ((bp->common.chip_id & 0x1) || 8932 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { 8933 bp->flags |= ONE_PORT_FLAG; 8934 BNX2X_DEV_INFO("single port device\n"); 8935 } 8936 8937 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); 8938 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << 8939 (val & MCPR_NVM_CFG4_FLASH_SIZE)); 8940 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 8941 bp->common.flash_size, bp->common.flash_size); 8942 8943 bnx2x_init_shmem(bp); 8944 8945 8946 8947 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? 8948 MISC_REG_GENERIC_CR_1 : 8949 MISC_REG_GENERIC_CR_0)); 8950 8951 bp->link_params.shmem_base = bp->common.shmem_base; 8952 bp->link_params.shmem2_base = bp->common.shmem2_base; 8953 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 8954 bp->common.shmem_base, bp->common.shmem2_base); 8955 8956 if (!bp->common.shmem_base) { 8957 BNX2X_DEV_INFO("MCP not active\n"); 8958 bp->flags |= NO_MCP_FLAG; 8959 return; 8960 } 8961 8962 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 8963 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 8964 8965 bp->link_params.hw_led_mode = ((bp->common.hw_config & 8966 SHARED_HW_CFG_LED_MODE_MASK) >> 8967 SHARED_HW_CFG_LED_MODE_SHIFT); 8968 8969 bp->link_params.feature_config_flags = 0; 8970 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); 8971 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) 8972 bp->link_params.feature_config_flags |= 8973 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 8974 else 8975 bp->link_params.feature_config_flags &= 8976 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 8977 8978 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 8979 bp->common.bc_ver = val; 8980 BNX2X_DEV_INFO("bc_ver %X\n", val); 8981 if (val < BNX2X_BC_VER) { 8982 /* for now only warn 8983 * later we might need to enforce this */ 8984 BNX2X_ERR("This driver needs bc_ver %X but found %X, " 8985 "please upgrade BC\n", BNX2X_BC_VER, val); 8986 } 8987 bp->link_params.feature_config_flags |= 8988 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 8989 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 8990 8991 bp->link_params.feature_config_flags |= 8992 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? 8993 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; 8994 8995 bp->link_params.feature_config_flags |= 8996 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? 8997 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; 8998 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? 8999 BC_SUPPORTS_PFC_STATS : 0; 9000 9001 boot_mode = SHMEM_RD(bp, 9002 dev_info.port_feature_config[BP_PORT(bp)].mba_config) & 9003 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; 9004 switch (boot_mode) { 9005 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: 9006 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; 9007 break; 9008 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: 9009 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; 9010 break; 9011 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: 9012 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; 9013 break; 9014 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: 9015 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; 9016 break; 9017 } 9018 9019 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); 9020 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; 9021 9022 BNX2X_DEV_INFO("%sWoL capable\n", 9023 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 9024 9025 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 9026 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 9027 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); 9028 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); 9029 9030 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", 9031 val, val2, val3, val4); 9032} 9033 9034#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 9035#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 9036 9037static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) 9038{ 9039 int pfid = BP_FUNC(bp); 9040 int igu_sb_id; 9041 u32 val; 9042 u8 fid, igu_sb_cnt = 0; 9043 9044 bp->igu_base_sb = 0xff; 9045 if (CHIP_INT_MODE_IS_BC(bp)) { 9046 int vn = BP_VN(bp); 9047 igu_sb_cnt = bp->igu_sb_cnt; 9048 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 9049 FP_SB_MAX_E1x; 9050 9051 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + 9052 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); 9053 9054 return; 9055 } 9056 9057 /* IGU in normal mode - read CAM */ 9058 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 9059 igu_sb_id++) { 9060 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 9061 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 9062 continue; 9063 fid = IGU_FID(val); 9064 if ((fid & IGU_FID_ENCODE_IS_PF)) { 9065 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) 9066 continue; 9067 if (IGU_VEC(val) == 0) 9068 /* default status block */ 9069 bp->igu_dsb_id = igu_sb_id; 9070 else { 9071 if (bp->igu_base_sb == 0xff) 9072 bp->igu_base_sb = igu_sb_id; 9073 igu_sb_cnt++; 9074 } 9075 } 9076 } 9077 9078#ifdef CONFIG_PCI_MSI 9079 /* 9080 * It's expected that number of CAM entries for this functions is equal 9081 * to the number evaluated based on the MSI-X table size. We want a 9082 * harsh warning if these values are different! 9083 */ 9084 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); 9085#endif 9086 9087 if (igu_sb_cnt == 0) 9088 BNX2X_ERR("CAM configuration error\n"); 9089} 9090 9091static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, 9092 u32 switch_cfg) 9093{ 9094 int cfg_size = 0, idx, port = BP_PORT(bp); 9095 9096 /* Aggregation of supported attributes of all external phys */ 9097 bp->port.supported[0] = 0; 9098 bp->port.supported[1] = 0; 9099 switch (bp->link_params.num_phys) { 9100 case 1: 9101 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; 9102 cfg_size = 1; 9103 break; 9104 case 2: 9105 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; 9106 cfg_size = 1; 9107 break; 9108 case 3: 9109 if (bp->link_params.multi_phy_config & 9110 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 9111 bp->port.supported[1] = 9112 bp->link_params.phy[EXT_PHY1].supported; 9113 bp->port.supported[0] = 9114 bp->link_params.phy[EXT_PHY2].supported; 9115 } else { 9116 bp->port.supported[0] = 9117 bp->link_params.phy[EXT_PHY1].supported; 9118 bp->port.supported[1] = 9119 bp->link_params.phy[EXT_PHY2].supported; 9120 } 9121 cfg_size = 2; 9122 break; 9123 } 9124 9125 if (!(bp->port.supported[0] || bp->port.supported[1])) { 9126 BNX2X_ERR("NVRAM config error. BAD phy config." 9127 "PHY1 config 0x%x, PHY2 config 0x%x\n", 9128 SHMEM_RD(bp, 9129 dev_info.port_hw_config[port].external_phy_config), 9130 SHMEM_RD(bp, 9131 dev_info.port_hw_config[port].external_phy_config2)); 9132 return; 9133 } 9134 9135 if (CHIP_IS_E3(bp)) 9136 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); 9137 else { 9138 switch (switch_cfg) { 9139 case SWITCH_CFG_1G: 9140 bp->port.phy_addr = REG_RD( 9141 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 9142 break; 9143 case SWITCH_CFG_10G: 9144 bp->port.phy_addr = REG_RD( 9145 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 9146 break; 9147 default: 9148 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 9149 bp->port.link_config[0]); 9150 return; 9151 } 9152 } 9153 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 9154 /* mask what we support according to speed_cap_mask per configuration */ 9155 for (idx = 0; idx < cfg_size; idx++) { 9156 if (!(bp->link_params.speed_cap_mask[idx] & 9157 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 9158 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; 9159 9160 if (!(bp->link_params.speed_cap_mask[idx] & 9161 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 9162 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; 9163 9164 if (!(bp->link_params.speed_cap_mask[idx] & 9165 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 9166 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; 9167 9168 if (!(bp->link_params.speed_cap_mask[idx] & 9169 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 9170 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; 9171 9172 if (!(bp->link_params.speed_cap_mask[idx] & 9173 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 9174 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | 9175 SUPPORTED_1000baseT_Full); 9176 9177 if (!(bp->link_params.speed_cap_mask[idx] & 9178 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 9179 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; 9180 9181 if (!(bp->link_params.speed_cap_mask[idx] & 9182 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 9183 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; 9184 9185 } 9186 9187 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], 9188 bp->port.supported[1]); 9189} 9190 9191static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) 9192{ 9193 u32 link_config, idx, cfg_size = 0; 9194 bp->port.advertising[0] = 0; 9195 bp->port.advertising[1] = 0; 9196 switch (bp->link_params.num_phys) { 9197 case 1: 9198 case 2: 9199 cfg_size = 1; 9200 break; 9201 case 3: 9202 cfg_size = 2; 9203 break; 9204 } 9205 for (idx = 0; idx < cfg_size; idx++) { 9206 bp->link_params.req_duplex[idx] = DUPLEX_FULL; 9207 link_config = bp->port.link_config[idx]; 9208 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 9209 case PORT_FEATURE_LINK_SPEED_AUTO: 9210 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { 9211 bp->link_params.req_line_speed[idx] = 9212 SPEED_AUTO_NEG; 9213 bp->port.advertising[idx] |= 9214 bp->port.supported[idx]; 9215 } else { 9216 /* force 10G, no AN */ 9217 bp->link_params.req_line_speed[idx] = 9218 SPEED_10000; 9219 bp->port.advertising[idx] |= 9220 (ADVERTISED_10000baseT_Full | 9221 ADVERTISED_FIBRE); 9222 continue; 9223 } 9224 break; 9225 9226 case PORT_FEATURE_LINK_SPEED_10M_FULL: 9227 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { 9228 bp->link_params.req_line_speed[idx] = 9229 SPEED_10; 9230 bp->port.advertising[idx] |= 9231 (ADVERTISED_10baseT_Full | 9232 ADVERTISED_TP); 9233 } else { 9234 BNX2X_ERR("NVRAM config error. " 9235 "Invalid link_config 0x%x" 9236 " speed_cap_mask 0x%x\n", 9237 link_config, 9238 bp->link_params.speed_cap_mask[idx]); 9239 return; 9240 } 9241 break; 9242 9243 case PORT_FEATURE_LINK_SPEED_10M_HALF: 9244 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { 9245 bp->link_params.req_line_speed[idx] = 9246 SPEED_10; 9247 bp->link_params.req_duplex[idx] = 9248 DUPLEX_HALF; 9249 bp->port.advertising[idx] |= 9250 (ADVERTISED_10baseT_Half | 9251 ADVERTISED_TP); 9252 } else { 9253 BNX2X_ERR("NVRAM config error. " 9254 "Invalid link_config 0x%x" 9255 " speed_cap_mask 0x%x\n", 9256 link_config, 9257 bp->link_params.speed_cap_mask[idx]); 9258 return; 9259 } 9260 break; 9261 9262 case PORT_FEATURE_LINK_SPEED_100M_FULL: 9263 if (bp->port.supported[idx] & 9264 SUPPORTED_100baseT_Full) { 9265 bp->link_params.req_line_speed[idx] = 9266 SPEED_100; 9267 bp->port.advertising[idx] |= 9268 (ADVERTISED_100baseT_Full | 9269 ADVERTISED_TP); 9270 } else { 9271 BNX2X_ERR("NVRAM config error. " 9272 "Invalid link_config 0x%x" 9273 " speed_cap_mask 0x%x\n", 9274 link_config, 9275 bp->link_params.speed_cap_mask[idx]); 9276 return; 9277 } 9278 break; 9279 9280 case PORT_FEATURE_LINK_SPEED_100M_HALF: 9281 if (bp->port.supported[idx] & 9282 SUPPORTED_100baseT_Half) { 9283 bp->link_params.req_line_speed[idx] = 9284 SPEED_100; 9285 bp->link_params.req_duplex[idx] = 9286 DUPLEX_HALF; 9287 bp->port.advertising[idx] |= 9288 (ADVERTISED_100baseT_Half | 9289 ADVERTISED_TP); 9290 } else { 9291 BNX2X_ERR("NVRAM config error. " 9292 "Invalid link_config 0x%x" 9293 " speed_cap_mask 0x%x\n", 9294 link_config, 9295 bp->link_params.speed_cap_mask[idx]); 9296 return; 9297 } 9298 break; 9299 9300 case PORT_FEATURE_LINK_SPEED_1G: 9301 if (bp->port.supported[idx] & 9302 SUPPORTED_1000baseT_Full) { 9303 bp->link_params.req_line_speed[idx] = 9304 SPEED_1000; 9305 bp->port.advertising[idx] |= 9306 (ADVERTISED_1000baseT_Full | 9307 ADVERTISED_TP); 9308 } else { 9309 BNX2X_ERR("NVRAM config error. " 9310 "Invalid link_config 0x%x" 9311 " speed_cap_mask 0x%x\n", 9312 link_config, 9313 bp->link_params.speed_cap_mask[idx]); 9314 return; 9315 } 9316 break; 9317 9318 case PORT_FEATURE_LINK_SPEED_2_5G: 9319 if (bp->port.supported[idx] & 9320 SUPPORTED_2500baseX_Full) { 9321 bp->link_params.req_line_speed[idx] = 9322 SPEED_2500; 9323 bp->port.advertising[idx] |= 9324 (ADVERTISED_2500baseX_Full | 9325 ADVERTISED_TP); 9326 } else { 9327 BNX2X_ERR("NVRAM config error. " 9328 "Invalid link_config 0x%x" 9329 " speed_cap_mask 0x%x\n", 9330 link_config, 9331 bp->link_params.speed_cap_mask[idx]); 9332 return; 9333 } 9334 break; 9335 9336 case PORT_FEATURE_LINK_SPEED_10G_CX4: 9337 if (bp->port.supported[idx] & 9338 SUPPORTED_10000baseT_Full) { 9339 bp->link_params.req_line_speed[idx] = 9340 SPEED_10000; 9341 bp->port.advertising[idx] |= 9342 (ADVERTISED_10000baseT_Full | 9343 ADVERTISED_FIBRE); 9344 } else { 9345 BNX2X_ERR("NVRAM config error. " 9346 "Invalid link_config 0x%x" 9347 " speed_cap_mask 0x%x\n", 9348 link_config, 9349 bp->link_params.speed_cap_mask[idx]); 9350 return; 9351 } 9352 break; 9353 case PORT_FEATURE_LINK_SPEED_20G: 9354 bp->link_params.req_line_speed[idx] = SPEED_20000; 9355 9356 break; 9357 default: 9358 BNX2X_ERR("NVRAM config error. " 9359 "BAD link speed link_config 0x%x\n", 9360 link_config); 9361 bp->link_params.req_line_speed[idx] = 9362 SPEED_AUTO_NEG; 9363 bp->port.advertising[idx] = 9364 bp->port.supported[idx]; 9365 break; 9366 } 9367 9368 bp->link_params.req_flow_ctrl[idx] = (link_config & 9369 PORT_FEATURE_FLOW_CONTROL_MASK); 9370 if ((bp->link_params.req_flow_ctrl[idx] == 9371 BNX2X_FLOW_CTRL_AUTO) && 9372 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { 9373 bp->link_params.req_flow_ctrl[idx] = 9374 BNX2X_FLOW_CTRL_NONE; 9375 } 9376 9377 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl" 9378 " 0x%x advertising 0x%x\n", 9379 bp->link_params.req_line_speed[idx], 9380 bp->link_params.req_duplex[idx], 9381 bp->link_params.req_flow_ctrl[idx], 9382 bp->port.advertising[idx]); 9383 } 9384} 9385 9386static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 9387{ 9388 mac_hi = cpu_to_be16(mac_hi); 9389 mac_lo = cpu_to_be32(mac_lo); 9390 memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); 9391 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); 9392} 9393 9394static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) 9395{ 9396 int port = BP_PORT(bp); 9397 u32 config; 9398 u32 ext_phy_type, ext_phy_config; 9399 9400 bp->link_params.bp = bp; 9401 bp->link_params.port = port; 9402 9403 bp->link_params.lane_config = 9404 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 9405 9406 bp->link_params.speed_cap_mask[0] = 9407 SHMEM_RD(bp, 9408 dev_info.port_hw_config[port].speed_capability_mask); 9409 bp->link_params.speed_cap_mask[1] = 9410 SHMEM_RD(bp, 9411 dev_info.port_hw_config[port].speed_capability_mask2); 9412 bp->port.link_config[0] = 9413 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 9414 9415 bp->port.link_config[1] = 9416 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); 9417 9418 bp->link_params.multi_phy_config = 9419 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); 9420 /* If the device is capable of WoL, set the default state according 9421 * to the HW 9422 */ 9423 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 9424 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 9425 (config & PORT_FEATURE_WOL_ENABLED)); 9426 9427 BNX2X_DEV_INFO("lane_config 0x%08x " 9428 "speed_cap_mask0 0x%08x link_config0 0x%08x\n", 9429 bp->link_params.lane_config, 9430 bp->link_params.speed_cap_mask[0], 9431 bp->port.link_config[0]); 9432 9433 bp->link_params.switch_cfg = (bp->port.link_config[0] & 9434 PORT_FEATURE_CONNECTED_SWITCH_MASK); 9435 bnx2x_phy_probe(&bp->link_params); 9436 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 9437 9438 bnx2x_link_settings_requested(bp); 9439 9440 /* 9441 * If connected directly, work with the internal PHY, otherwise, work 9442 * with the external PHY 9443 */ 9444 ext_phy_config = 9445 SHMEM_RD(bp, 9446 dev_info.port_hw_config[port].external_phy_config); 9447 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 9448 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 9449 bp->mdio.prtad = bp->port.phy_addr; 9450 9451 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 9452 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 9453 bp->mdio.prtad = 9454 XGXS_EXT_PHY_ADDR(ext_phy_config); 9455 9456 /* 9457 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) 9458 * In MF mode, it is set to cover self test cases 9459 */ 9460 if (IS_MF(bp)) 9461 bp->port.need_hw_lock = 1; 9462 else 9463 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, 9464 bp->common.shmem_base, 9465 bp->common.shmem2_base); 9466} 9467 9468void bnx2x_get_iscsi_info(struct bnx2x *bp) 9469{ 9470#ifdef BCM_CNIC 9471 int port = BP_PORT(bp); 9472 9473 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9474 drv_lic_key[port].max_iscsi_conn); 9475 9476 /* Get the number of maximum allowed iSCSI connections */ 9477 bp->cnic_eth_dev.max_iscsi_conn = 9478 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> 9479 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; 9480 9481 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", 9482 bp->cnic_eth_dev.max_iscsi_conn); 9483 9484 /* 9485 * If maximum allowed number of connections is zero - 9486 * disable the feature. 9487 */ 9488 if (!bp->cnic_eth_dev.max_iscsi_conn) 9489 bp->flags |= NO_ISCSI_FLAG; 9490#else 9491 bp->flags |= NO_ISCSI_FLAG; 9492#endif 9493} 9494 9495static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp) 9496{ 9497#ifdef BCM_CNIC 9498 int port = BP_PORT(bp); 9499 int func = BP_ABS_FUNC(bp); 9500 9501 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9502 drv_lic_key[port].max_fcoe_conn); 9503 9504 /* Get the number of maximum allowed FCoE connections */ 9505 bp->cnic_eth_dev.max_fcoe_conn = 9506 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> 9507 BNX2X_MAX_FCOE_INIT_CONN_SHIFT; 9508 9509 /* Read the WWN: */ 9510 if (!IS_MF(bp)) { 9511 /* Port info */ 9512 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9513 SHMEM_RD(bp, 9514 dev_info.port_hw_config[port]. 9515 fcoe_wwn_port_name_upper); 9516 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9517 SHMEM_RD(bp, 9518 dev_info.port_hw_config[port]. 9519 fcoe_wwn_port_name_lower); 9520 9521 /* Node info */ 9522 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9523 SHMEM_RD(bp, 9524 dev_info.port_hw_config[port]. 9525 fcoe_wwn_node_name_upper); 9526 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9527 SHMEM_RD(bp, 9528 dev_info.port_hw_config[port]. 9529 fcoe_wwn_node_name_lower); 9530 } else if (!IS_MF_SD(bp)) { 9531 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9532 9533 /* 9534 * Read the WWN info only if the FCoE feature is enabled for 9535 * this function. 9536 */ 9537 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9538 /* Port info */ 9539 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9540 MF_CFG_RD(bp, func_ext_config[func]. 9541 fcoe_wwn_port_name_upper); 9542 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9543 MF_CFG_RD(bp, func_ext_config[func]. 9544 fcoe_wwn_port_name_lower); 9545 9546 /* Node info */ 9547 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9548 MF_CFG_RD(bp, func_ext_config[func]. 9549 fcoe_wwn_node_name_upper); 9550 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9551 MF_CFG_RD(bp, func_ext_config[func]. 9552 fcoe_wwn_node_name_lower); 9553 } 9554 } 9555 9556 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); 9557 9558 /* 9559 * If maximum allowed number of connections is zero - 9560 * disable the feature. 9561 */ 9562 if (!bp->cnic_eth_dev.max_fcoe_conn) 9563 bp->flags |= NO_FCOE_FLAG; 9564#else 9565 bp->flags |= NO_FCOE_FLAG; 9566#endif 9567} 9568 9569static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) 9570{ 9571 /* 9572 * iSCSI may be dynamically disabled but reading 9573 * info here we will decrease memory usage by driver 9574 * if the feature is disabled for good 9575 */ 9576 bnx2x_get_iscsi_info(bp); 9577 bnx2x_get_fcoe_info(bp); 9578} 9579 9580static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) 9581{ 9582 u32 val, val2; 9583 int func = BP_ABS_FUNC(bp); 9584 int port = BP_PORT(bp); 9585#ifdef BCM_CNIC 9586 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; 9587 u8 *fip_mac = bp->fip_mac; 9588#endif 9589 9590 /* Zero primary MAC configuration */ 9591 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9592 9593 if (BP_NOMCP(bp)) { 9594 BNX2X_ERROR("warning: random MAC workaround active\n"); 9595 random_ether_addr(bp->dev->dev_addr); 9596 } else if (IS_MF(bp)) { 9597 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 9598 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); 9599 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && 9600 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) 9601 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9602 9603#ifdef BCM_CNIC 9604 /* 9605 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or 9606 * FCoE MAC then the appropriate feature should be disabled. 9607 */ 9608 if (IS_MF_SI(bp)) { 9609 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9610 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 9611 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9612 iscsi_mac_addr_upper); 9613 val = MF_CFG_RD(bp, func_ext_config[func]. 9614 iscsi_mac_addr_lower); 9615 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9616 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9617 iscsi_mac); 9618 } else 9619 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 9620 9621 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9622 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9623 fcoe_mac_addr_upper); 9624 val = MF_CFG_RD(bp, func_ext_config[func]. 9625 fcoe_mac_addr_lower); 9626 bnx2x_set_mac_buf(fip_mac, val, val2); 9627 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n", 9628 fip_mac); 9629 9630 } else 9631 bp->flags |= NO_FCOE_FLAG; 9632 } else { /* SD mode */ 9633 if (BNX2X_IS_MF_PROTOCOL_ISCSI(bp)) { 9634 /* use primary mac as iscsi mac */ 9635 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); 9636 /* Zero primary MAC configuration */ 9637 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9638 9639 BNX2X_DEV_INFO("SD ISCSI MODE\n"); 9640 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9641 iscsi_mac); 9642 } 9643 } 9644#endif 9645 } else { 9646 /* in SF read MACs from port configuration */ 9647 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 9648 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 9649 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9650 9651#ifdef BCM_CNIC 9652 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9653 iscsi_mac_upper); 9654 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9655 iscsi_mac_lower); 9656 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9657 9658 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9659 fcoe_fip_mac_upper); 9660 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9661 fcoe_fip_mac_lower); 9662 bnx2x_set_mac_buf(fip_mac, val, val2); 9663#endif 9664 } 9665 9666 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 9667 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); 9668 9669#ifdef BCM_CNIC 9670 /* Set the FCoE MAC in MF_SD mode */ 9671 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp)) 9672 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); 9673 9674 /* Disable iSCSI if MAC configuration is 9675 * invalid. 9676 */ 9677 if (!is_valid_ether_addr(iscsi_mac)) { 9678 bp->flags |= NO_ISCSI_FLAG; 9679 memset(iscsi_mac, 0, ETH_ALEN); 9680 } 9681 9682 /* Disable FCoE if MAC configuration is 9683 * invalid. 9684 */ 9685 if (!is_valid_ether_addr(fip_mac)) { 9686 bp->flags |= NO_FCOE_FLAG; 9687 memset(bp->fip_mac, 0, ETH_ALEN); 9688 } 9689#endif 9690 9691 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) 9692 dev_err(&bp->pdev->dev, 9693 "bad Ethernet MAC address configuration: " 9694 "%pM, change it manually before bringing up " 9695 "the appropriate network interface\n", 9696 bp->dev->dev_addr); 9697} 9698 9699static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) 9700{ 9701 int /*abs*/func = BP_ABS_FUNC(bp); 9702 int vn; 9703 u32 val = 0; 9704 int rc = 0; 9705 9706 bnx2x_get_common_hwinfo(bp); 9707 9708 /* 9709 * initialize IGU parameters 9710 */ 9711 if (CHIP_IS_E1x(bp)) { 9712 bp->common.int_block = INT_BLOCK_HC; 9713 9714 bp->igu_dsb_id = DEF_SB_IGU_ID; 9715 bp->igu_base_sb = 0; 9716 } else { 9717 bp->common.int_block = INT_BLOCK_IGU; 9718 9719 /* do not allow device reset during IGU info preocessing */ 9720 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9721 9722 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 9723 9724 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9725 int tout = 5000; 9726 9727 BNX2X_DEV_INFO("FORCING Normal Mode\n"); 9728 9729 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 9730 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); 9731 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); 9732 9733 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9734 tout--; 9735 usleep_range(1000, 1000); 9736 } 9737 9738 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9739 dev_err(&bp->pdev->dev, 9740 "FORCING Normal Mode failed!!!\n"); 9741 return -EPERM; 9742 } 9743 } 9744 9745 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9746 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); 9747 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; 9748 } else 9749 BNX2X_DEV_INFO("IGU Normal Mode\n"); 9750 9751 bnx2x_get_igu_cam_info(bp); 9752 9753 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9754 } 9755 9756 /* 9757 * set base FW non-default (fast path) status block id, this value is 9758 * used to initialize the fw_sb_id saved on the fp/queue structure to 9759 * determine the id used by the FW. 9760 */ 9761 if (CHIP_IS_E1x(bp)) 9762 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); 9763 else /* 9764 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of 9765 * the same queue are indicated on the same IGU SB). So we prefer 9766 * FW and IGU SBs to be the same value. 9767 */ 9768 bp->base_fw_ndsb = bp->igu_base_sb; 9769 9770 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" 9771 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, 9772 bp->igu_sb_cnt, bp->base_fw_ndsb); 9773 9774 /* 9775 * Initialize MF configuration 9776 */ 9777 9778 bp->mf_ov = 0; 9779 bp->mf_mode = 0; 9780 vn = BP_VN(bp); 9781 9782 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 9783 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 9784 bp->common.shmem2_base, SHMEM2_RD(bp, size), 9785 (u32)offsetof(struct shmem2_region, mf_cfg_addr)); 9786 9787 if (SHMEM2_HAS(bp, mf_cfg_addr)) 9788 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); 9789 else 9790 bp->common.mf_cfg_base = bp->common.shmem_base + 9791 offsetof(struct shmem_region, func_mb) + 9792 E1H_FUNC_MAX * sizeof(struct drv_func_mb); 9793 /* 9794 * get mf configuration: 9795 * 1. existence of MF configuration 9796 * 2. MAC address must be legal (check only upper bytes) 9797 * for Switch-Independent mode; 9798 * OVLAN must be legal for Switch-Dependent mode 9799 * 3. SF_MODE configures specific MF mode 9800 */ 9801 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9802 /* get mf configuration */ 9803 val = SHMEM_RD(bp, 9804 dev_info.shared_feature_config.config); 9805 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; 9806 9807 switch (val) { 9808 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 9809 val = MF_CFG_RD(bp, func_mf_config[func]. 9810 mac_upper); 9811 /* check for legal mac (upper bytes)*/ 9812 if (val != 0xffff) { 9813 bp->mf_mode = MULTI_FUNCTION_SI; 9814 bp->mf_config[vn] = MF_CFG_RD(bp, 9815 func_mf_config[func].config); 9816 } else 9817 BNX2X_DEV_INFO("illegal MAC address " 9818 "for SI\n"); 9819 break; 9820 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 9821 /* get OV configuration */ 9822 val = MF_CFG_RD(bp, 9823 func_mf_config[FUNC_0].e1hov_tag); 9824 val &= FUNC_MF_CFG_E1HOV_TAG_MASK; 9825 9826 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9827 bp->mf_mode = MULTI_FUNCTION_SD; 9828 bp->mf_config[vn] = MF_CFG_RD(bp, 9829 func_mf_config[func].config); 9830 } else 9831 BNX2X_DEV_INFO("illegal OV for SD\n"); 9832 break; 9833 default: 9834 /* Unknown configuration: reset mf_config */ 9835 bp->mf_config[vn] = 0; 9836 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val); 9837 } 9838 } 9839 9840 BNX2X_DEV_INFO("%s function mode\n", 9841 IS_MF(bp) ? "multi" : "single"); 9842 9843 switch (bp->mf_mode) { 9844 case MULTI_FUNCTION_SD: 9845 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 9846 FUNC_MF_CFG_E1HOV_TAG_MASK; 9847 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9848 bp->mf_ov = val; 9849 bp->path_has_ovlan = true; 9850 9851 BNX2X_DEV_INFO("MF OV for func %d is %d " 9852 "(0x%04x)\n", func, bp->mf_ov, 9853 bp->mf_ov); 9854 } else { 9855 dev_err(&bp->pdev->dev, 9856 "No valid MF OV for func %d, " 9857 "aborting\n", func); 9858 return -EPERM; 9859 } 9860 break; 9861 case MULTI_FUNCTION_SI: 9862 BNX2X_DEV_INFO("func %d is in MF " 9863 "switch-independent mode\n", func); 9864 break; 9865 default: 9866 if (vn) { 9867 dev_err(&bp->pdev->dev, 9868 "VN %d is in a single function mode, " 9869 "aborting\n", vn); 9870 return -EPERM; 9871 } 9872 break; 9873 } 9874 9875 /* check if other port on the path needs ovlan: 9876 * Since MF configuration is shared between ports 9877 * Possible mixed modes are only 9878 * {SF, SI} {SF, SD} {SD, SF} {SI, SF} 9879 */ 9880 if (CHIP_MODE_IS_4_PORT(bp) && 9881 !bp->path_has_ovlan && 9882 !IS_MF(bp) && 9883 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9884 u8 other_port = !BP_PORT(bp); 9885 u8 other_func = BP_PATH(bp) + 2*other_port; 9886 val = MF_CFG_RD(bp, 9887 func_mf_config[other_func].e1hov_tag); 9888 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) 9889 bp->path_has_ovlan = true; 9890 } 9891 } 9892 9893 /* adjust igu_sb_cnt to MF for E1x */ 9894 if (CHIP_IS_E1x(bp) && IS_MF(bp)) 9895 bp->igu_sb_cnt /= E1HVN_MAX; 9896 9897 /* port info */ 9898 bnx2x_get_port_hwinfo(bp); 9899 9900 /* Get MAC addresses */ 9901 bnx2x_get_mac_hwinfo(bp); 9902 9903 bnx2x_get_cnic_info(bp); 9904 9905 /* Get current FW pulse sequence */ 9906 if (!BP_NOMCP(bp)) { 9907 int mb_idx = BP_FW_MB_IDX(bp); 9908 9909 bp->fw_drv_pulse_wr_seq = 9910 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) & 9911 DRV_PULSE_SEQ_MASK); 9912 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq); 9913 } 9914 9915 return rc; 9916} 9917 9918static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) 9919{ 9920 int cnt, i, block_end, rodi; 9921 char vpd_start[BNX2X_VPD_LEN+1]; 9922 char str_id_reg[VENDOR_ID_LEN+1]; 9923 char str_id_cap[VENDOR_ID_LEN+1]; 9924 char *vpd_data; 9925 char *vpd_extended_data = NULL; 9926 u8 len; 9927 9928 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); 9929 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); 9930 9931 if (cnt < BNX2X_VPD_LEN) 9932 goto out_not_found; 9933 9934 /* VPD RO tag should be first tag after identifier string, hence 9935 * we should be able to find it in first BNX2X_VPD_LEN chars 9936 */ 9937 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, 9938 PCI_VPD_LRDT_RO_DATA); 9939 if (i < 0) 9940 goto out_not_found; 9941 9942 block_end = i + PCI_VPD_LRDT_TAG_SIZE + 9943 pci_vpd_lrdt_size(&vpd_start[i]); 9944 9945 i += PCI_VPD_LRDT_TAG_SIZE; 9946 9947 if (block_end > BNX2X_VPD_LEN) { 9948 vpd_extended_data = kmalloc(block_end, GFP_KERNEL); 9949 if (vpd_extended_data == NULL) 9950 goto out_not_found; 9951 9952 /* read rest of vpd image into vpd_extended_data */ 9953 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); 9954 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, 9955 block_end - BNX2X_VPD_LEN, 9956 vpd_extended_data + BNX2X_VPD_LEN); 9957 if (cnt < (block_end - BNX2X_VPD_LEN)) 9958 goto out_not_found; 9959 vpd_data = vpd_extended_data; 9960 } else 9961 vpd_data = vpd_start; 9962 9963 /* now vpd_data holds full vpd content in both cases */ 9964 9965 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 9966 PCI_VPD_RO_KEYWORD_MFR_ID); 9967 if (rodi < 0) 9968 goto out_not_found; 9969 9970 len = pci_vpd_info_field_size(&vpd_data[rodi]); 9971 9972 if (len != VENDOR_ID_LEN) 9973 goto out_not_found; 9974 9975 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 9976 9977 /* vendor specific info */ 9978 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); 9979 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); 9980 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || 9981 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { 9982 9983 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 9984 PCI_VPD_RO_KEYWORD_VENDOR0); 9985 if (rodi >= 0) { 9986 len = pci_vpd_info_field_size(&vpd_data[rodi]); 9987 9988 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 9989 9990 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { 9991 memcpy(bp->fw_ver, &vpd_data[rodi], len); 9992 bp->fw_ver[len] = ' '; 9993 } 9994 } 9995 kfree(vpd_extended_data); 9996 return; 9997 } 9998out_not_found: 9999 kfree(vpd_extended_data); 10000 return; 10001} 10002 10003static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) 10004{ 10005 u32 flags = 0; 10006 10007 if (CHIP_REV_IS_FPGA(bp)) 10008 SET_FLAGS(flags, MODE_FPGA); 10009 else if (CHIP_REV_IS_EMUL(bp)) 10010 SET_FLAGS(flags, MODE_EMUL); 10011 else 10012 SET_FLAGS(flags, MODE_ASIC); 10013 10014 if (CHIP_MODE_IS_4_PORT(bp)) 10015 SET_FLAGS(flags, MODE_PORT4); 10016 else 10017 SET_FLAGS(flags, MODE_PORT2); 10018 10019 if (CHIP_IS_E2(bp)) 10020 SET_FLAGS(flags, MODE_E2); 10021 else if (CHIP_IS_E3(bp)) { 10022 SET_FLAGS(flags, MODE_E3); 10023 if (CHIP_REV(bp) == CHIP_REV_Ax) 10024 SET_FLAGS(flags, MODE_E3_A0); 10025 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ 10026 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 10027 } 10028 10029 if (IS_MF(bp)) { 10030 SET_FLAGS(flags, MODE_MF); 10031 switch (bp->mf_mode) { 10032 case MULTI_FUNCTION_SD: 10033 SET_FLAGS(flags, MODE_MF_SD); 10034 break; 10035 case MULTI_FUNCTION_SI: 10036 SET_FLAGS(flags, MODE_MF_SI); 10037 break; 10038 } 10039 } else 10040 SET_FLAGS(flags, MODE_SF); 10041 10042#if defined(__LITTLE_ENDIAN) 10043 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 10044#else /*(__BIG_ENDIAN)*/ 10045 SET_FLAGS(flags, MODE_BIG_ENDIAN); 10046#endif 10047 INIT_MODE_FLAGS(bp) = flags; 10048} 10049 10050static int __devinit bnx2x_init_bp(struct bnx2x *bp) 10051{ 10052 int func; 10053 int rc; 10054 10055 mutex_init(&bp->port.phy_mutex); 10056 mutex_init(&bp->fw_mb_mutex); 10057 spin_lock_init(&bp->stats_lock); 10058#ifdef BCM_CNIC 10059 mutex_init(&bp->cnic_mutex); 10060#endif 10061 10062 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); 10063 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); 10064 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); 10065 rc = bnx2x_get_hwinfo(bp); 10066 if (rc) 10067 return rc; 10068 10069 bnx2x_set_modes_bitmap(bp); 10070 10071 rc = bnx2x_alloc_mem_bp(bp); 10072 if (rc) 10073 return rc; 10074 10075 bnx2x_read_fwinfo(bp); 10076 10077 func = BP_FUNC(bp); 10078 10079 /* need to reset chip if undi was active */ 10080 if (!BP_NOMCP(bp)) 10081 bnx2x_undi_unload(bp); 10082 10083 /* init fw_seq after undi_unload! */ 10084 if (!BP_NOMCP(bp)) { 10085 bp->fw_seq = 10086 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 10087 DRV_MSG_SEQ_NUMBER_MASK); 10088 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 10089 } 10090 10091 if (CHIP_REV_IS_FPGA(bp)) 10092 dev_err(&bp->pdev->dev, "FPGA detected\n"); 10093 10094 if (BP_NOMCP(bp) && (func == 0)) 10095 dev_err(&bp->pdev->dev, "MCP disabled, " 10096 "must load devices in order!\n"); 10097 10098 bp->multi_mode = multi_mode; 10099 10100 bp->disable_tpa = disable_tpa; 10101 10102#ifdef BCM_CNIC 10103 bp->disable_tpa |= IS_MF_ISCSI_SD(bp); 10104#endif 10105 10106 /* Set TPA flags */ 10107 if (bp->disable_tpa) { 10108 bp->flags &= ~TPA_ENABLE_FLAG; 10109 bp->dev->features &= ~NETIF_F_LRO; 10110 } else { 10111 bp->flags |= TPA_ENABLE_FLAG; 10112 bp->dev->features |= NETIF_F_LRO; 10113 } 10114 10115 if (CHIP_IS_E1(bp)) 10116 bp->dropless_fc = 0; 10117 else 10118 bp->dropless_fc = dropless_fc; 10119 10120 bp->mrrs = mrrs; 10121 10122 bp->tx_ring_size = MAX_TX_AVAIL; 10123 10124 /* make sure that the numbers are in the right granularity */ 10125 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; 10126 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; 10127 10128 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; 10129 10130 init_timer(&bp->timer); 10131 bp->timer.expires = jiffies + bp->current_interval; 10132 bp->timer.data = (unsigned long) bp; 10133 bp->timer.function = bnx2x_timer; 10134 10135 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); 10136 bnx2x_dcbx_init_params(bp); 10137 10138#ifdef BCM_CNIC 10139 if (CHIP_IS_E1x(bp)) 10140 bp->cnic_base_cl_id = FP_SB_MAX_E1x; 10141 else 10142 bp->cnic_base_cl_id = FP_SB_MAX_E2; 10143#endif 10144 10145 /* multiple tx priority */ 10146 if (CHIP_IS_E1x(bp)) 10147 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; 10148 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) 10149 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; 10150 if (CHIP_IS_E3B0(bp)) 10151 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; 10152 10153 return rc; 10154} 10155 10156 10157/**************************************************************************** 10158* General service functions 10159****************************************************************************/ 10160 10161/* 10162 * net_device service functions 10163 */ 10164 10165/* called with rtnl_lock */ 10166static int bnx2x_open(struct net_device *dev) 10167{ 10168 struct bnx2x *bp = netdev_priv(dev); 10169 bool global = false; 10170 int other_engine = BP_PATH(bp) ? 0 : 1; 10171 u32 other_load_counter, load_counter; 10172 10173 netif_carrier_off(dev); 10174 10175 bnx2x_set_power_state(bp, PCI_D0); 10176 10177 other_load_counter = bnx2x_get_load_cnt(bp, other_engine); 10178 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp)); 10179 10180 /* 10181 * If parity had happen during the unload, then attentions 10182 * and/or RECOVERY_IN_PROGRES may still be set. In this case we 10183 * want the first function loaded on the current engine to 10184 * complete the recovery. 10185 */ 10186 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 10187 bnx2x_chk_parity_attn(bp, &global, true)) 10188 do { 10189 /* 10190 * If there are attentions and they are in a global 10191 * blocks, set the GLOBAL_RESET bit regardless whether 10192 * it will be this function that will complete the 10193 * recovery or not. 10194 */ 10195 if (global) 10196 bnx2x_set_reset_global(bp); 10197 10198 /* 10199 * Only the first function on the current engine should 10200 * try to recover in open. In case of attentions in 10201 * global blocks only the first in the chip should try 10202 * to recover. 10203 */ 10204 if ((!load_counter && 10205 (!global || !other_load_counter)) && 10206 bnx2x_trylock_leader_lock(bp) && 10207 !bnx2x_leader_reset(bp)) { 10208 netdev_info(bp->dev, "Recovered in open\n"); 10209 break; 10210 } 10211 10212 /* recovery has failed... */ 10213 bnx2x_set_power_state(bp, PCI_D3hot); 10214 bp->recovery_state = BNX2X_RECOVERY_FAILED; 10215 10216 netdev_err(bp->dev, "Recovery flow hasn't been properly" 10217 " completed yet. Try again later. If u still see this" 10218 " message after a few retries then power cycle is" 10219 " required.\n"); 10220 10221 return -EAGAIN; 10222 } while (0); 10223 10224 bp->recovery_state = BNX2X_RECOVERY_DONE; 10225 return bnx2x_nic_load(bp, LOAD_OPEN); 10226} 10227 10228/* called with rtnl_lock */ 10229int bnx2x_close(struct net_device *dev) 10230{ 10231 struct bnx2x *bp = netdev_priv(dev); 10232 10233 /* Unload the driver, release IRQs */ 10234 bnx2x_nic_unload(bp, UNLOAD_CLOSE); 10235 10236 /* Power off */ 10237 bnx2x_set_power_state(bp, PCI_D3hot); 10238 10239 return 0; 10240} 10241 10242static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp, 10243 struct bnx2x_mcast_ramrod_params *p) 10244{ 10245 int mc_count = netdev_mc_count(bp->dev); 10246 struct bnx2x_mcast_list_elem *mc_mac = 10247 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); 10248 struct netdev_hw_addr *ha; 10249 10250 if (!mc_mac) 10251 return -ENOMEM; 10252 10253 INIT_LIST_HEAD(&p->mcast_list); 10254 10255 netdev_for_each_mc_addr(ha, bp->dev) { 10256 mc_mac->mac = bnx2x_mc_addr(ha); 10257 list_add_tail(&mc_mac->link, &p->mcast_list); 10258 mc_mac++; 10259 } 10260 10261 p->mcast_list_len = mc_count; 10262 10263 return 0; 10264} 10265 10266static inline void bnx2x_free_mcast_macs_list( 10267 struct bnx2x_mcast_ramrod_params *p) 10268{ 10269 struct bnx2x_mcast_list_elem *mc_mac = 10270 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, 10271 link); 10272 10273 WARN_ON(!mc_mac); 10274 kfree(mc_mac); 10275} 10276 10277/** 10278 * bnx2x_set_uc_list - configure a new unicast MACs list. 10279 * 10280 * @bp: driver handle 10281 * 10282 * We will use zero (0) as a MAC type for these MACs. 10283 */ 10284static inline int bnx2x_set_uc_list(struct bnx2x *bp) 10285{ 10286 int rc; 10287 struct net_device *dev = bp->dev; 10288 struct netdev_hw_addr *ha; 10289 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj; 10290 unsigned long ramrod_flags = 0; 10291 10292 /* First schedule a cleanup up of old configuration */ 10293 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); 10294 if (rc < 0) { 10295 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); 10296 return rc; 10297 } 10298 10299 netdev_for_each_uc_addr(ha, dev) { 10300 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, 10301 BNX2X_UC_LIST_MAC, &ramrod_flags); 10302 if (rc < 0) { 10303 BNX2X_ERR("Failed to schedule ADD operations: %d\n", 10304 rc); 10305 return rc; 10306 } 10307 } 10308 10309 /* Execute the pending commands */ 10310 __set_bit(RAMROD_CONT, &ramrod_flags); 10311 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, 10312 BNX2X_UC_LIST_MAC, &ramrod_flags); 10313} 10314 10315static inline int bnx2x_set_mc_list(struct bnx2x *bp) 10316{ 10317 struct net_device *dev = bp->dev; 10318 struct bnx2x_mcast_ramrod_params rparam = {0}; 10319 int rc = 0; 10320 10321 rparam.mcast_obj = &bp->mcast_obj; 10322 10323 /* first, clear all configured multicast MACs */ 10324 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 10325 if (rc < 0) { 10326 BNX2X_ERR("Failed to clear multicast " 10327 "configuration: %d\n", rc); 10328 return rc; 10329 } 10330 10331 /* then, configure a new MACs list */ 10332 if (netdev_mc_count(dev)) { 10333 rc = bnx2x_init_mcast_macs_list(bp, &rparam); 10334 if (rc) { 10335 BNX2X_ERR("Failed to create multicast MACs " 10336 "list: %d\n", rc); 10337 return rc; 10338 } 10339 10340 /* Now add the new MACs */ 10341 rc = bnx2x_config_mcast(bp, &rparam, 10342 BNX2X_MCAST_CMD_ADD); 10343 if (rc < 0) 10344 BNX2X_ERR("Failed to set a new multicast " 10345 "configuration: %d\n", rc); 10346 10347 bnx2x_free_mcast_macs_list(&rparam); 10348 } 10349 10350 return rc; 10351} 10352 10353 10354/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ 10355void bnx2x_set_rx_mode(struct net_device *dev) 10356{ 10357 struct bnx2x *bp = netdev_priv(dev); 10358 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 10359 10360 if (bp->state != BNX2X_STATE_OPEN) { 10361 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 10362 return; 10363 } 10364 10365 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); 10366 10367 if (dev->flags & IFF_PROMISC) 10368 rx_mode = BNX2X_RX_MODE_PROMISC; 10369 else if ((dev->flags & IFF_ALLMULTI) || 10370 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && 10371 CHIP_IS_E1(bp))) 10372 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10373 else { 10374 /* some multicasts */ 10375 if (bnx2x_set_mc_list(bp) < 0) 10376 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10377 10378 if (bnx2x_set_uc_list(bp) < 0) 10379 rx_mode = BNX2X_RX_MODE_PROMISC; 10380 } 10381 10382 bp->rx_mode = rx_mode; 10383#ifdef BCM_CNIC 10384 /* handle ISCSI SD mode */ 10385 if (IS_MF_ISCSI_SD(bp)) 10386 bp->rx_mode = BNX2X_RX_MODE_NONE; 10387#endif 10388 10389 /* Schedule the rx_mode command */ 10390 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { 10391 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 10392 return; 10393 } 10394 10395 bnx2x_set_storm_rx_mode(bp); 10396} 10397 10398/* called with rtnl_lock */ 10399static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 10400 int devad, u16 addr) 10401{ 10402 struct bnx2x *bp = netdev_priv(netdev); 10403 u16 value; 10404 int rc; 10405 10406 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 10407 prtad, devad, addr); 10408 10409 /* The HW expects different devad if CL22 is used */ 10410 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10411 10412 bnx2x_acquire_phy_lock(bp); 10413 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); 10414 bnx2x_release_phy_lock(bp); 10415 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 10416 10417 if (!rc) 10418 rc = value; 10419 return rc; 10420} 10421 10422/* called with rtnl_lock */ 10423static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, 10424 u16 addr, u16 value) 10425{ 10426 struct bnx2x *bp = netdev_priv(netdev); 10427 int rc; 10428 10429 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x," 10430 " value 0x%x\n", prtad, devad, addr, value); 10431 10432 /* The HW expects different devad if CL22 is used */ 10433 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10434 10435 bnx2x_acquire_phy_lock(bp); 10436 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); 10437 bnx2x_release_phy_lock(bp); 10438 return rc; 10439} 10440 10441/* called with rtnl_lock */ 10442static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 10443{ 10444 struct bnx2x *bp = netdev_priv(dev); 10445 struct mii_ioctl_data *mdio = if_mii(ifr); 10446 10447 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", 10448 mdio->phy_id, mdio->reg_num, mdio->val_in); 10449 10450 if (!netif_running(dev)) 10451 return -EAGAIN; 10452 10453 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); 10454} 10455 10456#ifdef CONFIG_NET_POLL_CONTROLLER 10457static void poll_bnx2x(struct net_device *dev) 10458{ 10459 struct bnx2x *bp = netdev_priv(dev); 10460 10461 disable_irq(bp->pdev->irq); 10462 bnx2x_interrupt(bp->pdev->irq, dev); 10463 enable_irq(bp->pdev->irq); 10464} 10465#endif 10466 10467static int bnx2x_validate_addr(struct net_device *dev) 10468{ 10469 struct bnx2x *bp = netdev_priv(dev); 10470 10471 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) 10472 return -EADDRNOTAVAIL; 10473 return 0; 10474} 10475 10476static const struct net_device_ops bnx2x_netdev_ops = { 10477 .ndo_open = bnx2x_open, 10478 .ndo_stop = bnx2x_close, 10479 .ndo_start_xmit = bnx2x_start_xmit, 10480 .ndo_select_queue = bnx2x_select_queue, 10481 .ndo_set_rx_mode = bnx2x_set_rx_mode, 10482 .ndo_set_mac_address = bnx2x_change_mac_addr, 10483 .ndo_validate_addr = bnx2x_validate_addr, 10484 .ndo_do_ioctl = bnx2x_ioctl, 10485 .ndo_change_mtu = bnx2x_change_mtu, 10486 .ndo_fix_features = bnx2x_fix_features, 10487 .ndo_set_features = bnx2x_set_features, 10488 .ndo_tx_timeout = bnx2x_tx_timeout, 10489#ifdef CONFIG_NET_POLL_CONTROLLER 10490 .ndo_poll_controller = poll_bnx2x, 10491#endif 10492 .ndo_setup_tc = bnx2x_setup_tc, 10493 10494#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) 10495 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, 10496#endif 10497}; 10498 10499static inline int bnx2x_set_coherency_mask(struct bnx2x *bp) 10500{ 10501 struct device *dev = &bp->pdev->dev; 10502 10503 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 10504 bp->flags |= USING_DAC_FLAG; 10505 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 10506 dev_err(dev, "dma_set_coherent_mask failed, " 10507 "aborting\n"); 10508 return -EIO; 10509 } 10510 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 10511 dev_err(dev, "System does not support DMA, aborting\n"); 10512 return -EIO; 10513 } 10514 10515 return 0; 10516} 10517 10518static int __devinit bnx2x_init_dev(struct pci_dev *pdev, 10519 struct net_device *dev, 10520 unsigned long board_type) 10521{ 10522 struct bnx2x *bp; 10523 int rc; 10524 bool chip_is_e1x = (board_type == BCM57710 || 10525 board_type == BCM57711 || 10526 board_type == BCM57711E); 10527 10528 SET_NETDEV_DEV(dev, &pdev->dev); 10529 bp = netdev_priv(dev); 10530 10531 bp->dev = dev; 10532 bp->pdev = pdev; 10533 bp->flags = 0; 10534 bp->pf_num = PCI_FUNC(pdev->devfn); 10535 10536 rc = pci_enable_device(pdev); 10537 if (rc) { 10538 dev_err(&bp->pdev->dev, 10539 "Cannot enable PCI device, aborting\n"); 10540 goto err_out; 10541 } 10542 10543 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 10544 dev_err(&bp->pdev->dev, 10545 "Cannot find PCI device base address, aborting\n"); 10546 rc = -ENODEV; 10547 goto err_out_disable; 10548 } 10549 10550 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 10551 dev_err(&bp->pdev->dev, "Cannot find second PCI device" 10552 " base address, aborting\n"); 10553 rc = -ENODEV; 10554 goto err_out_disable; 10555 } 10556 10557 if (atomic_read(&pdev->enable_cnt) == 1) { 10558 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 10559 if (rc) { 10560 dev_err(&bp->pdev->dev, 10561 "Cannot obtain PCI resources, aborting\n"); 10562 goto err_out_disable; 10563 } 10564 10565 pci_set_master(pdev); 10566 pci_save_state(pdev); 10567 } 10568 10569 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 10570 if (bp->pm_cap == 0) { 10571 dev_err(&bp->pdev->dev, 10572 "Cannot find power management capability, aborting\n"); 10573 rc = -EIO; 10574 goto err_out_release; 10575 } 10576 10577 if (!pci_is_pcie(pdev)) { 10578 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 10579 rc = -EIO; 10580 goto err_out_release; 10581 } 10582 10583 rc = bnx2x_set_coherency_mask(bp); 10584 if (rc) 10585 goto err_out_release; 10586 10587 dev->mem_start = pci_resource_start(pdev, 0); 10588 dev->base_addr = dev->mem_start; 10589 dev->mem_end = pci_resource_end(pdev, 0); 10590 10591 dev->irq = pdev->irq; 10592 10593 bp->regview = pci_ioremap_bar(pdev, 0); 10594 if (!bp->regview) { 10595 dev_err(&bp->pdev->dev, 10596 "Cannot map register space, aborting\n"); 10597 rc = -ENOMEM; 10598 goto err_out_release; 10599 } 10600 10601 bnx2x_set_power_state(bp, PCI_D0); 10602 10603 /* clean indirect addresses */ 10604 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 10605 PCICFG_VENDOR_ID_OFFSET); 10606 /* 10607 * Clean the following indirect addresses for all functions since it 10608 * is not used by the driver. 10609 */ 10610 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); 10611 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); 10612 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 10613 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 10614 10615 if (chip_is_e1x) { 10616 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 10617 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 10618 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 10619 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); 10620 } 10621 10622 /* 10623 * Enable internal target-read (in case we are probed after PF FLR). 10624 * Must be done prior to any BAR read access. Only for 57712 and up 10625 */ 10626 if (!chip_is_e1x) 10627 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 10628 10629 /* Reset the load counter */ 10630 bnx2x_clear_load_cnt(bp); 10631 10632 dev->watchdog_timeo = TX_TIMEOUT; 10633 10634 dev->netdev_ops = &bnx2x_netdev_ops; 10635 bnx2x_set_ethtool_ops(dev); 10636 10637 dev->priv_flags |= IFF_UNICAST_FLT; 10638 10639 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10640 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_LRO | 10641 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; 10642 10643 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10644 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 10645 10646 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; 10647 if (bp->flags & USING_DAC_FLAG) 10648 dev->features |= NETIF_F_HIGHDMA; 10649 10650 /* Add Loopback capability to the device */ 10651 dev->hw_features |= NETIF_F_LOOPBACK; 10652 10653#ifdef BCM_DCBNL 10654 dev->dcbnl_ops = &bnx2x_dcbnl_ops; 10655#endif 10656 10657 /* get_port_hwinfo() will set prtad and mmds properly */ 10658 bp->mdio.prtad = MDIO_PRTAD_NONE; 10659 bp->mdio.mmds = 0; 10660 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10661 bp->mdio.dev = dev; 10662 bp->mdio.mdio_read = bnx2x_mdio_read; 10663 bp->mdio.mdio_write = bnx2x_mdio_write; 10664 10665 return 0; 10666 10667err_out_release: 10668 if (atomic_read(&pdev->enable_cnt) == 1) 10669 pci_release_regions(pdev); 10670 10671err_out_disable: 10672 pci_disable_device(pdev); 10673 pci_set_drvdata(pdev, NULL); 10674 10675err_out: 10676 return rc; 10677} 10678 10679static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, 10680 int *width, int *speed) 10681{ 10682 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); 10683 10684 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; 10685 10686 /* return value of 1=2.5GHz 2=5GHz */ 10687 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; 10688} 10689 10690static int bnx2x_check_firmware(struct bnx2x *bp) 10691{ 10692 const struct firmware *firmware = bp->firmware; 10693 struct bnx2x_fw_file_hdr *fw_hdr; 10694 struct bnx2x_fw_file_section *sections; 10695 u32 offset, len, num_ops; 10696 u16 *ops_offsets; 10697 int i; 10698 const u8 *fw_ver; 10699 10700 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) 10701 return -EINVAL; 10702 10703 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 10704 sections = (struct bnx2x_fw_file_section *)fw_hdr; 10705 10706 /* Make sure none of the offsets and sizes make us read beyond 10707 * the end of the firmware data */ 10708 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { 10709 offset = be32_to_cpu(sections[i].offset); 10710 len = be32_to_cpu(sections[i].len); 10711 if (offset + len > firmware->size) { 10712 dev_err(&bp->pdev->dev, 10713 "Section %d length is out of bounds\n", i); 10714 return -EINVAL; 10715 } 10716 } 10717 10718 /* Likewise for the init_ops offsets */ 10719 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); 10720 ops_offsets = (u16 *)(firmware->data + offset); 10721 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); 10722 10723 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 10724 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 10725 dev_err(&bp->pdev->dev, 10726 "Section offset %d is out of bounds\n", i); 10727 return -EINVAL; 10728 } 10729 } 10730 10731 /* Check FW version */ 10732 offset = be32_to_cpu(fw_hdr->fw_version.offset); 10733 fw_ver = firmware->data + offset; 10734 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || 10735 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || 10736 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || 10737 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { 10738 dev_err(&bp->pdev->dev, 10739 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 10740 fw_ver[0], fw_ver[1], fw_ver[2], 10741 fw_ver[3], BCM_5710_FW_MAJOR_VERSION, 10742 BCM_5710_FW_MINOR_VERSION, 10743 BCM_5710_FW_REVISION_VERSION, 10744 BCM_5710_FW_ENGINEERING_VERSION); 10745 return -EINVAL; 10746 } 10747 10748 return 0; 10749} 10750 10751static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10752{ 10753 const __be32 *source = (const __be32 *)_source; 10754 u32 *target = (u32 *)_target; 10755 u32 i; 10756 10757 for (i = 0; i < n/4; i++) 10758 target[i] = be32_to_cpu(source[i]); 10759} 10760 10761/* 10762 Ops array is stored in the following format: 10763 {op(8bit), offset(24bit, big endian), data(32bit, big endian)} 10764 */ 10765static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) 10766{ 10767 const __be32 *source = (const __be32 *)_source; 10768 struct raw_op *target = (struct raw_op *)_target; 10769 u32 i, j, tmp; 10770 10771 for (i = 0, j = 0; i < n/8; i++, j += 2) { 10772 tmp = be32_to_cpu(source[j]); 10773 target[i].op = (tmp >> 24) & 0xff; 10774 target[i].offset = tmp & 0xffffff; 10775 target[i].raw_data = be32_to_cpu(source[j + 1]); 10776 } 10777} 10778 10779/** 10780 * IRO array is stored in the following format: 10781 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } 10782 */ 10783static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) 10784{ 10785 const __be32 *source = (const __be32 *)_source; 10786 struct iro *target = (struct iro *)_target; 10787 u32 i, j, tmp; 10788 10789 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { 10790 target[i].base = be32_to_cpu(source[j]); 10791 j++; 10792 tmp = be32_to_cpu(source[j]); 10793 target[i].m1 = (tmp >> 16) & 0xffff; 10794 target[i].m2 = tmp & 0xffff; 10795 j++; 10796 tmp = be32_to_cpu(source[j]); 10797 target[i].m3 = (tmp >> 16) & 0xffff; 10798 target[i].size = tmp & 0xffff; 10799 j++; 10800 } 10801} 10802 10803static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10804{ 10805 const __be16 *source = (const __be16 *)_source; 10806 u16 *target = (u16 *)_target; 10807 u32 i; 10808 10809 for (i = 0; i < n/2; i++) 10810 target[i] = be16_to_cpu(source[i]); 10811} 10812 10813#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ 10814do { \ 10815 u32 len = be32_to_cpu(fw_hdr->arr.len); \ 10816 bp->arr = kmalloc(len, GFP_KERNEL); \ 10817 if (!bp->arr) { \ 10818 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \ 10819 goto lbl; \ 10820 } \ 10821 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ 10822 (u8 *)bp->arr, len); \ 10823} while (0) 10824 10825int bnx2x_init_firmware(struct bnx2x *bp) 10826{ 10827 struct bnx2x_fw_file_hdr *fw_hdr; 10828 int rc; 10829 10830 10831 if (!bp->firmware) { 10832 const char *fw_file_name; 10833 10834 if (CHIP_IS_E1(bp)) 10835 fw_file_name = FW_FILE_NAME_E1; 10836 else if (CHIP_IS_E1H(bp)) 10837 fw_file_name = FW_FILE_NAME_E1H; 10838 else if (!CHIP_IS_E1x(bp)) 10839 fw_file_name = FW_FILE_NAME_E2; 10840 else { 10841 BNX2X_ERR("Unsupported chip revision\n"); 10842 return -EINVAL; 10843 } 10844 BNX2X_DEV_INFO("Loading %s\n", fw_file_name); 10845 10846 rc = request_firmware(&bp->firmware, fw_file_name, 10847 &bp->pdev->dev); 10848 if (rc) { 10849 BNX2X_ERR("Can't load firmware file %s\n", 10850 fw_file_name); 10851 goto request_firmware_exit; 10852 } 10853 10854 rc = bnx2x_check_firmware(bp); 10855 if (rc) { 10856 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); 10857 goto request_firmware_exit; 10858 } 10859 } 10860 10861 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; 10862 10863 /* Initialize the pointers to the init arrays */ 10864 /* Blob */ 10865 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); 10866 10867 /* Opcodes */ 10868 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); 10869 10870 /* Offsets */ 10871 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, 10872 be16_to_cpu_n); 10873 10874 /* STORMs firmware */ 10875 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10876 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); 10877 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + 10878 be32_to_cpu(fw_hdr->tsem_pram_data.offset); 10879 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10880 be32_to_cpu(fw_hdr->usem_int_table_data.offset); 10881 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + 10882 be32_to_cpu(fw_hdr->usem_pram_data.offset); 10883 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10884 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); 10885 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + 10886 be32_to_cpu(fw_hdr->xsem_pram_data.offset); 10887 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10888 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 10889 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 10890 be32_to_cpu(fw_hdr->csem_pram_data.offset); 10891 /* IRO */ 10892 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); 10893 10894 return 0; 10895 10896iro_alloc_err: 10897 kfree(bp->init_ops_offsets); 10898init_offsets_alloc_err: 10899 kfree(bp->init_ops); 10900init_ops_alloc_err: 10901 kfree(bp->init_data); 10902request_firmware_exit: 10903 release_firmware(bp->firmware); 10904 bp->firmware = NULL; 10905 10906 return rc; 10907} 10908 10909static void bnx2x_release_firmware(struct bnx2x *bp) 10910{ 10911 kfree(bp->init_ops_offsets); 10912 kfree(bp->init_ops); 10913 kfree(bp->init_data); 10914 release_firmware(bp->firmware); 10915 bp->firmware = NULL; 10916} 10917 10918 10919static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { 10920 .init_hw_cmn_chip = bnx2x_init_hw_common_chip, 10921 .init_hw_cmn = bnx2x_init_hw_common, 10922 .init_hw_port = bnx2x_init_hw_port, 10923 .init_hw_func = bnx2x_init_hw_func, 10924 10925 .reset_hw_cmn = bnx2x_reset_common, 10926 .reset_hw_port = bnx2x_reset_port, 10927 .reset_hw_func = bnx2x_reset_func, 10928 10929 .gunzip_init = bnx2x_gunzip_init, 10930 .gunzip_end = bnx2x_gunzip_end, 10931 10932 .init_fw = bnx2x_init_firmware, 10933 .release_fw = bnx2x_release_firmware, 10934}; 10935 10936void bnx2x__init_func_obj(struct bnx2x *bp) 10937{ 10938 /* Prepare DMAE related driver resources */ 10939 bnx2x_setup_dmae(bp); 10940 10941 bnx2x_init_func_obj(bp, &bp->func_obj, 10942 bnx2x_sp(bp, func_rdata), 10943 bnx2x_sp_mapping(bp, func_rdata), 10944 &bnx2x_func_sp_drv); 10945} 10946 10947/* must be called after sriov-enable */ 10948static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp) 10949{ 10950 int cid_count = BNX2X_L2_CID_COUNT(bp); 10951 10952#ifdef BCM_CNIC 10953 cid_count += CNIC_CID_MAX; 10954#endif 10955 return roundup(cid_count, QM_CID_ROUND); 10956} 10957 10958/** 10959 * bnx2x_get_num_none_def_sbs - return the number of none default SBs 10960 * 10961 * @dev: pci device 10962 * 10963 */ 10964static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) 10965{ 10966 int pos; 10967 u16 control; 10968 10969 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 10970 10971 /* 10972 * If MSI-X is not supported - return number of SBs needed to support 10973 * one fast path queue: one FP queue + SB for CNIC 10974 */ 10975 if (!pos) 10976 return 1 + CNIC_PRESENT; 10977 10978 /* 10979 * The value in the PCI configuration space is the index of the last 10980 * entry, namely one less than the actual size of the table, which is 10981 * exactly what we want to return from this function: number of all SBs 10982 * without the default SB. 10983 */ 10984 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 10985 return control & PCI_MSIX_FLAGS_QSIZE; 10986} 10987 10988static int __devinit bnx2x_init_one(struct pci_dev *pdev, 10989 const struct pci_device_id *ent) 10990{ 10991 struct net_device *dev = NULL; 10992 struct bnx2x *bp; 10993 int pcie_width, pcie_speed; 10994 int rc, max_non_def_sbs; 10995 int rx_count, tx_count, rss_count; 10996 /* 10997 * An estimated maximum supported CoS number according to the chip 10998 * version. 10999 * We will try to roughly estimate the maximum number of CoSes this chip 11000 * may support in order to minimize the memory allocated for Tx 11001 * netdev_queue's. This number will be accurately calculated during the 11002 * initialization of bp->max_cos based on the chip versions AND chip 11003 * revision in the bnx2x_init_bp(). 11004 */ 11005 u8 max_cos_est = 0; 11006 11007 switch (ent->driver_data) { 11008 case BCM57710: 11009 case BCM57711: 11010 case BCM57711E: 11011 max_cos_est = BNX2X_MULTI_TX_COS_E1X; 11012 break; 11013 11014 case BCM57712: 11015 case BCM57712_MF: 11016 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; 11017 break; 11018 11019 case BCM57800: 11020 case BCM57800_MF: 11021 case BCM57810: 11022 case BCM57810_MF: 11023 case BCM57840: 11024 case BCM57840_MF: 11025 max_cos_est = BNX2X_MULTI_TX_COS_E3B0; 11026 break; 11027 11028 default: 11029 pr_err("Unknown board_type (%ld), aborting\n", 11030 ent->driver_data); 11031 return -ENODEV; 11032 } 11033 11034 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); 11035 11036 /* !!! FIXME !!! 11037 * Do not allow the maximum SB count to grow above 16 11038 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48. 11039 * We will use the FP_SB_MAX_E1x macro for this matter. 11040 */ 11041 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs); 11042 11043 WARN_ON(!max_non_def_sbs); 11044 11045 /* Maximum number of RSS queues: one IGU SB goes to CNIC */ 11046 rss_count = max_non_def_sbs - CNIC_PRESENT; 11047 11048 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ 11049 rx_count = rss_count + FCOE_PRESENT; 11050 11051 /* 11052 * Maximum number of netdev Tx queues: 11053 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 11054 */ 11055 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT; 11056 11057 /* dev zeroed in init_etherdev */ 11058 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); 11059 if (!dev) { 11060 dev_err(&pdev->dev, "Cannot allocate net device\n"); 11061 return -ENOMEM; 11062 } 11063 11064 bp = netdev_priv(dev); 11065 11066 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n", 11067 tx_count, rx_count); 11068 11069 bp->igu_sb_cnt = max_non_def_sbs; 11070 bp->msg_enable = debug; 11071 pci_set_drvdata(pdev, dev); 11072 11073 rc = bnx2x_init_dev(pdev, dev, ent->driver_data); 11074 if (rc < 0) { 11075 free_netdev(dev); 11076 return rc; 11077 } 11078 11079 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs); 11080 11081 rc = bnx2x_init_bp(bp); 11082 if (rc) 11083 goto init_one_exit; 11084 11085 /* 11086 * Map doorbels here as we need the real value of bp->max_cos which 11087 * is initialized in bnx2x_init_bp(). 11088 */ 11089 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), 11090 min_t(u64, BNX2X_DB_SIZE(bp), 11091 pci_resource_len(pdev, 2))); 11092 if (!bp->doorbells) { 11093 dev_err(&bp->pdev->dev, 11094 "Cannot map doorbell space, aborting\n"); 11095 rc = -ENOMEM; 11096 goto init_one_exit; 11097 } 11098 11099 /* calc qm_cid_count */ 11100 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); 11101 11102#ifdef BCM_CNIC 11103 /* disable FCOE L2 queue for E1x */ 11104 if (CHIP_IS_E1x(bp)) 11105 bp->flags |= NO_FCOE_FLAG; 11106 11107#endif 11108 11109 /* Configure interrupt mode: try to enable MSI-X/MSI if 11110 * needed, set bp->num_queues appropriately. 11111 */ 11112 bnx2x_set_int_mode(bp); 11113 11114 /* Add all NAPI objects */ 11115 bnx2x_add_all_napi(bp); 11116 11117 rc = register_netdev(dev); 11118 if (rc) { 11119 dev_err(&pdev->dev, "Cannot register net device\n"); 11120 goto init_one_exit; 11121 } 11122 11123#ifdef BCM_CNIC 11124 if (!NO_FCOE(bp)) { 11125 /* Add storage MAC address */ 11126 rtnl_lock(); 11127 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11128 rtnl_unlock(); 11129 } 11130#endif 11131 11132 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); 11133 11134 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", 11135 board_info[ent->driver_data].name, 11136 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 11137 pcie_width, 11138 ((!CHIP_IS_E2(bp) && pcie_speed == 2) || 11139 (CHIP_IS_E2(bp) && pcie_speed == 1)) ? 11140 "5GHz (Gen2)" : "2.5GHz", 11141 dev->base_addr, bp->pdev->irq, dev->dev_addr); 11142 11143 return 0; 11144 11145init_one_exit: 11146 if (bp->regview) 11147 iounmap(bp->regview); 11148 11149 if (bp->doorbells) 11150 iounmap(bp->doorbells); 11151 11152 free_netdev(dev); 11153 11154 if (atomic_read(&pdev->enable_cnt) == 1) 11155 pci_release_regions(pdev); 11156 11157 pci_disable_device(pdev); 11158 pci_set_drvdata(pdev, NULL); 11159 11160 return rc; 11161} 11162 11163static void __devexit bnx2x_remove_one(struct pci_dev *pdev) 11164{ 11165 struct net_device *dev = pci_get_drvdata(pdev); 11166 struct bnx2x *bp; 11167 11168 if (!dev) { 11169 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); 11170 return; 11171 } 11172 bp = netdev_priv(dev); 11173 11174#ifdef BCM_CNIC 11175 /* Delete storage MAC address */ 11176 if (!NO_FCOE(bp)) { 11177 rtnl_lock(); 11178 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11179 rtnl_unlock(); 11180 } 11181#endif 11182 11183#ifdef BCM_DCBNL 11184 /* Delete app tlvs from dcbnl */ 11185 bnx2x_dcbnl_update_applist(bp, true); 11186#endif 11187 11188 unregister_netdev(dev); 11189 11190 /* Delete all NAPI objects */ 11191 bnx2x_del_all_napi(bp); 11192 11193 /* Power on: we can't let PCI layer write to us while we are in D3 */ 11194 bnx2x_set_power_state(bp, PCI_D0); 11195 11196 /* Disable MSI/MSI-X */ 11197 bnx2x_disable_msi(bp); 11198 11199 /* Power off */ 11200 bnx2x_set_power_state(bp, PCI_D3hot); 11201 11202 /* Make sure RESET task is not scheduled before continuing */ 11203 cancel_delayed_work_sync(&bp->sp_rtnl_task); 11204 11205 if (bp->regview) 11206 iounmap(bp->regview); 11207 11208 if (bp->doorbells) 11209 iounmap(bp->doorbells); 11210 11211 bnx2x_release_firmware(bp); 11212 11213 bnx2x_free_mem_bp(bp); 11214 11215 free_netdev(dev); 11216 11217 if (atomic_read(&pdev->enable_cnt) == 1) 11218 pci_release_regions(pdev); 11219 11220 pci_disable_device(pdev); 11221 pci_set_drvdata(pdev, NULL); 11222} 11223 11224static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 11225{ 11226 int i; 11227 11228 bp->state = BNX2X_STATE_ERROR; 11229 11230 bp->rx_mode = BNX2X_RX_MODE_NONE; 11231 11232#ifdef BCM_CNIC 11233 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); 11234#endif 11235 /* Stop Tx */ 11236 bnx2x_tx_disable(bp); 11237 11238 bnx2x_netif_stop(bp, 0); 11239 11240 del_timer_sync(&bp->timer); 11241 11242 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 11243 11244 /* Release IRQs */ 11245 bnx2x_free_irq(bp); 11246 11247 /* Free SKBs, SGEs, TPA pool and driver internals */ 11248 bnx2x_free_skbs(bp); 11249 11250 for_each_rx_queue(bp, i) 11251 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 11252 11253 bnx2x_free_mem(bp); 11254 11255 bp->state = BNX2X_STATE_CLOSED; 11256 11257 netif_carrier_off(bp->dev); 11258 11259 return 0; 11260} 11261 11262static void bnx2x_eeh_recover(struct bnx2x *bp) 11263{ 11264 u32 val; 11265 11266 mutex_init(&bp->port.phy_mutex); 11267 11268 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 11269 bp->link_params.shmem_base = bp->common.shmem_base; 11270 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base); 11271 11272 if (!bp->common.shmem_base || 11273 (bp->common.shmem_base < 0xA0000) || 11274 (bp->common.shmem_base >= 0xC0000)) { 11275 BNX2X_DEV_INFO("MCP not active\n"); 11276 bp->flags |= NO_MCP_FLAG; 11277 return; 11278 } 11279 11280 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 11281 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11282 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11283 BNX2X_ERR("BAD MCP validity signature\n"); 11284 11285 if (!BP_NOMCP(bp)) { 11286 bp->fw_seq = 11287 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 11288 DRV_MSG_SEQ_NUMBER_MASK); 11289 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 11290 } 11291} 11292 11293/** 11294 * bnx2x_io_error_detected - called when PCI error is detected 11295 * @pdev: Pointer to PCI device 11296 * @state: The current pci connection state 11297 * 11298 * This function is called after a PCI bus error affecting 11299 * this device has been detected. 11300 */ 11301static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, 11302 pci_channel_state_t state) 11303{ 11304 struct net_device *dev = pci_get_drvdata(pdev); 11305 struct bnx2x *bp = netdev_priv(dev); 11306 11307 rtnl_lock(); 11308 11309 netif_device_detach(dev); 11310 11311 if (state == pci_channel_io_perm_failure) { 11312 rtnl_unlock(); 11313 return PCI_ERS_RESULT_DISCONNECT; 11314 } 11315 11316 if (netif_running(dev)) 11317 bnx2x_eeh_nic_unload(bp); 11318 11319 pci_disable_device(pdev); 11320 11321 rtnl_unlock(); 11322 11323 /* Request a slot reset */ 11324 return PCI_ERS_RESULT_NEED_RESET; 11325} 11326 11327/** 11328 * bnx2x_io_slot_reset - called after the PCI bus has been reset 11329 * @pdev: Pointer to PCI device 11330 * 11331 * Restart the card from scratch, as if from a cold-boot. 11332 */ 11333static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) 11334{ 11335 struct net_device *dev = pci_get_drvdata(pdev); 11336 struct bnx2x *bp = netdev_priv(dev); 11337 11338 rtnl_lock(); 11339 11340 if (pci_enable_device(pdev)) { 11341 dev_err(&pdev->dev, 11342 "Cannot re-enable PCI device after reset\n"); 11343 rtnl_unlock(); 11344 return PCI_ERS_RESULT_DISCONNECT; 11345 } 11346 11347 pci_set_master(pdev); 11348 pci_restore_state(pdev); 11349 11350 if (netif_running(dev)) 11351 bnx2x_set_power_state(bp, PCI_D0); 11352 11353 rtnl_unlock(); 11354 11355 return PCI_ERS_RESULT_RECOVERED; 11356} 11357 11358/** 11359 * bnx2x_io_resume - called when traffic can start flowing again 11360 * @pdev: Pointer to PCI device 11361 * 11362 * This callback is called when the error recovery driver tells us that 11363 * its OK to resume normal operation. 11364 */ 11365static void bnx2x_io_resume(struct pci_dev *pdev) 11366{ 11367 struct net_device *dev = pci_get_drvdata(pdev); 11368 struct bnx2x *bp = netdev_priv(dev); 11369 11370 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 11371 netdev_err(bp->dev, "Handling parity error recovery. " 11372 "Try again later\n"); 11373 return; 11374 } 11375 11376 rtnl_lock(); 11377 11378 bnx2x_eeh_recover(bp); 11379 11380 if (netif_running(dev)) 11381 bnx2x_nic_load(bp, LOAD_NORMAL); 11382 11383 netif_device_attach(dev); 11384 11385 rtnl_unlock(); 11386} 11387 11388static struct pci_error_handlers bnx2x_err_handler = { 11389 .error_detected = bnx2x_io_error_detected, 11390 .slot_reset = bnx2x_io_slot_reset, 11391 .resume = bnx2x_io_resume, 11392}; 11393 11394static struct pci_driver bnx2x_pci_driver = { 11395 .name = DRV_MODULE_NAME, 11396 .id_table = bnx2x_pci_tbl, 11397 .probe = bnx2x_init_one, 11398 .remove = __devexit_p(bnx2x_remove_one), 11399 .suspend = bnx2x_suspend, 11400 .resume = bnx2x_resume, 11401 .err_handler = &bnx2x_err_handler, 11402}; 11403 11404static int __init bnx2x_init(void) 11405{ 11406 int ret; 11407 11408 pr_info("%s", version); 11409 11410 bnx2x_wq = create_singlethread_workqueue("bnx2x"); 11411 if (bnx2x_wq == NULL) { 11412 pr_err("Cannot create workqueue\n"); 11413 return -ENOMEM; 11414 } 11415 11416 ret = pci_register_driver(&bnx2x_pci_driver); 11417 if (ret) { 11418 pr_err("Cannot register driver\n"); 11419 destroy_workqueue(bnx2x_wq); 11420 } 11421 return ret; 11422} 11423 11424static void __exit bnx2x_cleanup(void) 11425{ 11426 pci_unregister_driver(&bnx2x_pci_driver); 11427 11428 destroy_workqueue(bnx2x_wq); 11429} 11430 11431void bnx2x_notify_link_changed(struct bnx2x *bp) 11432{ 11433 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); 11434} 11435 11436module_init(bnx2x_init); 11437module_exit(bnx2x_cleanup); 11438 11439#ifdef BCM_CNIC 11440/** 11441 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). 11442 * 11443 * @bp: driver handle 11444 * @set: set or clear the CAM entry 11445 * 11446 * This function will wait until the ramdord completion returns. 11447 * Return 0 if success, -ENODEV if ramrod doesn't return. 11448 */ 11449static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) 11450{ 11451 unsigned long ramrod_flags = 0; 11452 11453 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 11454 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, 11455 &bp->iscsi_l2_mac_obj, true, 11456 BNX2X_ISCSI_ETH_MAC, &ramrod_flags); 11457} 11458 11459/* count denotes the number of new completions we have seen */ 11460static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) 11461{ 11462 struct eth_spe *spe; 11463 11464#ifdef BNX2X_STOP_ON_ERROR 11465 if (unlikely(bp->panic)) 11466 return; 11467#endif 11468 11469 spin_lock_bh(&bp->spq_lock); 11470 BUG_ON(bp->cnic_spq_pending < count); 11471 bp->cnic_spq_pending -= count; 11472 11473 11474 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { 11475 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) 11476 & SPE_HDR_CONN_TYPE) >> 11477 SPE_HDR_CONN_TYPE_SHIFT; 11478 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) 11479 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; 11480 11481 /* Set validation for iSCSI L2 client before sending SETUP 11482 * ramrod 11483 */ 11484 if (type == ETH_CONNECTION_TYPE) { 11485 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) 11486 bnx2x_set_ctx_validation(bp, &bp->context. 11487 vcxt[BNX2X_ISCSI_ETH_CID].eth, 11488 BNX2X_ISCSI_ETH_CID); 11489 } 11490 11491 /* 11492 * There may be not more than 8 L2, not more than 8 L5 SPEs 11493 * and in the air. We also check that number of outstanding 11494 * COMMON ramrods is not more than the EQ and SPQ can 11495 * accommodate. 11496 */ 11497 if (type == ETH_CONNECTION_TYPE) { 11498 if (!atomic_read(&bp->cq_spq_left)) 11499 break; 11500 else 11501 atomic_dec(&bp->cq_spq_left); 11502 } else if (type == NONE_CONNECTION_TYPE) { 11503 if (!atomic_read(&bp->eq_spq_left)) 11504 break; 11505 else 11506 atomic_dec(&bp->eq_spq_left); 11507 } else if ((type == ISCSI_CONNECTION_TYPE) || 11508 (type == FCOE_CONNECTION_TYPE)) { 11509 if (bp->cnic_spq_pending >= 11510 bp->cnic_eth_dev.max_kwqe_pending) 11511 break; 11512 else 11513 bp->cnic_spq_pending++; 11514 } else { 11515 BNX2X_ERR("Unknown SPE type: %d\n", type); 11516 bnx2x_panic(); 11517 break; 11518 } 11519 11520 spe = bnx2x_sp_get_next(bp); 11521 *spe = *bp->cnic_kwq_cons; 11522 11523 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n", 11524 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 11525 11526 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 11527 bp->cnic_kwq_cons = bp->cnic_kwq; 11528 else 11529 bp->cnic_kwq_cons++; 11530 } 11531 bnx2x_sp_prod_update(bp); 11532 spin_unlock_bh(&bp->spq_lock); 11533} 11534 11535static int bnx2x_cnic_sp_queue(struct net_device *dev, 11536 struct kwqe_16 *kwqes[], u32 count) 11537{ 11538 struct bnx2x *bp = netdev_priv(dev); 11539 int i; 11540 11541#ifdef BNX2X_STOP_ON_ERROR 11542 if (unlikely(bp->panic)) 11543 return -EIO; 11544#endif 11545 11546 spin_lock_bh(&bp->spq_lock); 11547 11548 for (i = 0; i < count; i++) { 11549 struct eth_spe *spe = (struct eth_spe *)kwqes[i]; 11550 11551 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) 11552 break; 11553 11554 *bp->cnic_kwq_prod = *spe; 11555 11556 bp->cnic_kwq_pending++; 11557 11558 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n", 11559 spe->hdr.conn_and_cmd_data, spe->hdr.type, 11560 spe->data.update_data_addr.hi, 11561 spe->data.update_data_addr.lo, 11562 bp->cnic_kwq_pending); 11563 11564 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 11565 bp->cnic_kwq_prod = bp->cnic_kwq; 11566 else 11567 bp->cnic_kwq_prod++; 11568 } 11569 11570 spin_unlock_bh(&bp->spq_lock); 11571 11572 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) 11573 bnx2x_cnic_sp_post(bp, 0); 11574 11575 return i; 11576} 11577 11578static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11579{ 11580 struct cnic_ops *c_ops; 11581 int rc = 0; 11582 11583 mutex_lock(&bp->cnic_mutex); 11584 c_ops = rcu_dereference_protected(bp->cnic_ops, 11585 lockdep_is_held(&bp->cnic_mutex)); 11586 if (c_ops) 11587 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11588 mutex_unlock(&bp->cnic_mutex); 11589 11590 return rc; 11591} 11592 11593static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11594{ 11595 struct cnic_ops *c_ops; 11596 int rc = 0; 11597 11598 rcu_read_lock(); 11599 c_ops = rcu_dereference(bp->cnic_ops); 11600 if (c_ops) 11601 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11602 rcu_read_unlock(); 11603 11604 return rc; 11605} 11606 11607/* 11608 * for commands that have no data 11609 */ 11610int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) 11611{ 11612 struct cnic_ctl_info ctl = {0}; 11613 11614 ctl.cmd = cmd; 11615 11616 return bnx2x_cnic_ctl_send(bp, &ctl); 11617} 11618 11619static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) 11620{ 11621 struct cnic_ctl_info ctl = {0}; 11622 11623 /* first we tell CNIC and only then we count this as a completion */ 11624 ctl.cmd = CNIC_CTL_COMPLETION_CMD; 11625 ctl.data.comp.cid = cid; 11626 ctl.data.comp.error = err; 11627 11628 bnx2x_cnic_ctl_send_bh(bp, &ctl); 11629 bnx2x_cnic_sp_post(bp, 0); 11630} 11631 11632 11633/* Called with netif_addr_lock_bh() taken. 11634 * Sets an rx_mode config for an iSCSI ETH client. 11635 * Doesn't block. 11636 * Completion should be checked outside. 11637 */ 11638static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) 11639{ 11640 unsigned long accept_flags = 0, ramrod_flags = 0; 11641 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11642 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; 11643 11644 if (start) { 11645 /* Start accepting on iSCSI L2 ring. Accept all multicasts 11646 * because it's the only way for UIO Queue to accept 11647 * multicasts (in non-promiscuous mode only one Queue per 11648 * function will receive multicast packets (leading in our 11649 * case). 11650 */ 11651 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); 11652 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); 11653 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); 11654 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 11655 11656 /* Clear STOP_PENDING bit if START is requested */ 11657 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); 11658 11659 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; 11660 } else 11661 /* Clear START_PENDING bit if STOP is requested */ 11662 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); 11663 11664 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 11665 set_bit(sched_state, &bp->sp_state); 11666 else { 11667 __set_bit(RAMROD_RX, &ramrod_flags); 11668 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, 11669 ramrod_flags); 11670 } 11671} 11672 11673 11674static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 11675{ 11676 struct bnx2x *bp = netdev_priv(dev); 11677 int rc = 0; 11678 11679 switch (ctl->cmd) { 11680 case DRV_CTL_CTXTBL_WR_CMD: { 11681 u32 index = ctl->data.io.offset; 11682 dma_addr_t addr = ctl->data.io.dma_addr; 11683 11684 bnx2x_ilt_wr(bp, index, addr); 11685 break; 11686 } 11687 11688 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { 11689 int count = ctl->data.credit.credit_count; 11690 11691 bnx2x_cnic_sp_post(bp, count); 11692 break; 11693 } 11694 11695 /* rtnl_lock is held. */ 11696 case DRV_CTL_START_L2_CMD: { 11697 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11698 unsigned long sp_bits = 0; 11699 11700 /* Configure the iSCSI classification object */ 11701 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, 11702 cp->iscsi_l2_client_id, 11703 cp->iscsi_l2_cid, BP_FUNC(bp), 11704 bnx2x_sp(bp, mac_rdata), 11705 bnx2x_sp_mapping(bp, mac_rdata), 11706 BNX2X_FILTER_MAC_PENDING, 11707 &bp->sp_state, BNX2X_OBJ_TYPE_RX, 11708 &bp->macs_pool); 11709 11710 /* Set iSCSI MAC address */ 11711 rc = bnx2x_set_iscsi_eth_mac_addr(bp); 11712 if (rc) 11713 break; 11714 11715 mmiowb(); 11716 barrier(); 11717 11718 /* Start accepting on iSCSI L2 ring */ 11719 11720 netif_addr_lock_bh(dev); 11721 bnx2x_set_iscsi_eth_rx_mode(bp, true); 11722 netif_addr_unlock_bh(dev); 11723 11724 /* bits to wait on */ 11725 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11726 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); 11727 11728 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11729 BNX2X_ERR("rx_mode completion timed out!\n"); 11730 11731 break; 11732 } 11733 11734 /* rtnl_lock is held. */ 11735 case DRV_CTL_STOP_L2_CMD: { 11736 unsigned long sp_bits = 0; 11737 11738 /* Stop accepting on iSCSI L2 ring */ 11739 netif_addr_lock_bh(dev); 11740 bnx2x_set_iscsi_eth_rx_mode(bp, false); 11741 netif_addr_unlock_bh(dev); 11742 11743 /* bits to wait on */ 11744 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11745 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); 11746 11747 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11748 BNX2X_ERR("rx_mode completion timed out!\n"); 11749 11750 mmiowb(); 11751 barrier(); 11752 11753 /* Unset iSCSI L2 MAC */ 11754 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, 11755 BNX2X_ISCSI_ETH_MAC, true); 11756 break; 11757 } 11758 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { 11759 int count = ctl->data.credit.credit_count; 11760 11761 smp_mb__before_atomic_inc(); 11762 atomic_add(count, &bp->cq_spq_left); 11763 smp_mb__after_atomic_inc(); 11764 break; 11765 } 11766 case DRV_CTL_ULP_REGISTER_CMD: { 11767 int ulp_type = ctl->data.ulp_type; 11768 11769 if (CHIP_IS_E3(bp)) { 11770 int idx = BP_FW_MB_IDX(bp); 11771 u32 cap; 11772 11773 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 11774 if (ulp_type == CNIC_ULP_ISCSI) 11775 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 11776 else if (ulp_type == CNIC_ULP_FCOE) 11777 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 11778 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 11779 } 11780 break; 11781 } 11782 case DRV_CTL_ULP_UNREGISTER_CMD: { 11783 int ulp_type = ctl->data.ulp_type; 11784 11785 if (CHIP_IS_E3(bp)) { 11786 int idx = BP_FW_MB_IDX(bp); 11787 u32 cap; 11788 11789 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 11790 if (ulp_type == CNIC_ULP_ISCSI) 11791 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 11792 else if (ulp_type == CNIC_ULP_FCOE) 11793 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 11794 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 11795 } 11796 break; 11797 } 11798 11799 default: 11800 BNX2X_ERR("unknown command %x\n", ctl->cmd); 11801 rc = -EINVAL; 11802 } 11803 11804 return rc; 11805} 11806 11807void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) 11808{ 11809 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11810 11811 if (bp->flags & USING_MSIX_FLAG) { 11812 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 11813 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 11814 cp->irq_arr[0].vector = bp->msix_table[1].vector; 11815 } else { 11816 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 11817 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 11818 } 11819 if (!CHIP_IS_E1x(bp)) 11820 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; 11821 else 11822 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; 11823 11824 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); 11825 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); 11826 cp->irq_arr[1].status_blk = bp->def_status_blk; 11827 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 11828 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; 11829 11830 cp->num_irq = 2; 11831} 11832 11833static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, 11834 void *data) 11835{ 11836 struct bnx2x *bp = netdev_priv(dev); 11837 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11838 11839 if (ops == NULL) 11840 return -EINVAL; 11841 11842 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 11843 if (!bp->cnic_kwq) 11844 return -ENOMEM; 11845 11846 bp->cnic_kwq_cons = bp->cnic_kwq; 11847 bp->cnic_kwq_prod = bp->cnic_kwq; 11848 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; 11849 11850 bp->cnic_spq_pending = 0; 11851 bp->cnic_kwq_pending = 0; 11852 11853 bp->cnic_data = data; 11854 11855 cp->num_irq = 0; 11856 cp->drv_state |= CNIC_DRV_STATE_REGD; 11857 cp->iro_arr = bp->iro_arr; 11858 11859 bnx2x_setup_cnic_irq_info(bp); 11860 11861 rcu_assign_pointer(bp->cnic_ops, ops); 11862 11863 return 0; 11864} 11865 11866static int bnx2x_unregister_cnic(struct net_device *dev) 11867{ 11868 struct bnx2x *bp = netdev_priv(dev); 11869 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11870 11871 mutex_lock(&bp->cnic_mutex); 11872 cp->drv_state = 0; 11873 RCU_INIT_POINTER(bp->cnic_ops, NULL); 11874 mutex_unlock(&bp->cnic_mutex); 11875 synchronize_rcu(); 11876 kfree(bp->cnic_kwq); 11877 bp->cnic_kwq = NULL; 11878 11879 return 0; 11880} 11881 11882struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) 11883{ 11884 struct bnx2x *bp = netdev_priv(dev); 11885 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11886 11887 /* If both iSCSI and FCoE are disabled - return NULL in 11888 * order to indicate CNIC that it should not try to work 11889 * with this device. 11890 */ 11891 if (NO_ISCSI(bp) && NO_FCOE(bp)) 11892 return NULL; 11893 11894 cp->drv_owner = THIS_MODULE; 11895 cp->chip_id = CHIP_ID(bp); 11896 cp->pdev = bp->pdev; 11897 cp->io_base = bp->regview; 11898 cp->io_base2 = bp->doorbells; 11899 cp->max_kwqe_pending = 8; 11900 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; 11901 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 11902 bnx2x_cid_ilt_lines(bp); 11903 cp->ctx_tbl_len = CNIC_ILT_LINES; 11904 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 11905 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 11906 cp->drv_ctl = bnx2x_drv_ctl; 11907 cp->drv_register_cnic = bnx2x_register_cnic; 11908 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 11909 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID; 11910 cp->iscsi_l2_client_id = 11911 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11912 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID; 11913 11914 if (NO_ISCSI_OOO(bp)) 11915 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 11916 11917 if (NO_ISCSI(bp)) 11918 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; 11919 11920 if (NO_FCOE(bp)) 11921 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 11922 11923 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, " 11924 "starting cid %d\n", 11925 cp->ctx_blk_size, 11926 cp->ctx_tbl_offset, 11927 cp->ctx_tbl_len, 11928 cp->starting_cid); 11929 return cp; 11930} 11931EXPORT_SYMBOL(bnx2x_cnic_probe); 11932 11933#endif /* BCM_CNIC */ 11934 11935