bnx2x_main.c revision 2cfa5a0471fef43fda0b7bd87e3a5e4dbadb7809
1/* bnx2x_main.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2011 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20#include <linux/module.h> 21#include <linux/moduleparam.h> 22#include <linux/kernel.h> 23#include <linux/device.h> /* for dev_info() */ 24#include <linux/timer.h> 25#include <linux/errno.h> 26#include <linux/ioport.h> 27#include <linux/slab.h> 28#include <linux/interrupt.h> 29#include <linux/pci.h> 30#include <linux/init.h> 31#include <linux/netdevice.h> 32#include <linux/etherdevice.h> 33#include <linux/skbuff.h> 34#include <linux/dma-mapping.h> 35#include <linux/bitops.h> 36#include <linux/irq.h> 37#include <linux/delay.h> 38#include <asm/byteorder.h> 39#include <linux/time.h> 40#include <linux/ethtool.h> 41#include <linux/mii.h> 42#include <linux/if.h> 43#include <linux/if_vlan.h> 44#include <net/ip.h> 45#include <net/ipv6.h> 46#include <net/tcp.h> 47#include <net/checksum.h> 48#include <net/ip6_checksum.h> 49#include <linux/workqueue.h> 50#include <linux/crc32.h> 51#include <linux/crc32c.h> 52#include <linux/prefetch.h> 53#include <linux/zlib.h> 54#include <linux/io.h> 55#include <linux/stringify.h> 56#include <linux/vmalloc.h> 57 58#include "bnx2x.h" 59#include "bnx2x_init.h" 60#include "bnx2x_init_ops.h" 61#include "bnx2x_cmn.h" 62#include "bnx2x_dcb.h" 63#include "bnx2x_sp.h" 64 65#include <linux/firmware.h> 66#include "bnx2x_fw_file_hdr.h" 67/* FW files */ 68#define FW_FILE_VERSION \ 69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 72 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 73#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 74#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 75#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 76 77/* Time in jiffies before concluding the transmitter is hung */ 78#define TX_TIMEOUT (5*HZ) 79 80static char version[] __devinitdata = 81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " 82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 83 84MODULE_AUTHOR("Eliezer Tamir"); 85MODULE_DESCRIPTION("Broadcom NetXtreme II " 86 "BCM57710/57711/57711E/" 87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 88 "57840/57840_MF Driver"); 89MODULE_LICENSE("GPL"); 90MODULE_VERSION(DRV_MODULE_VERSION); 91MODULE_FIRMWARE(FW_FILE_NAME_E1); 92MODULE_FIRMWARE(FW_FILE_NAME_E1H); 93MODULE_FIRMWARE(FW_FILE_NAME_E2); 94 95static int multi_mode = 1; 96module_param(multi_mode, int, 0); 97MODULE_PARM_DESC(multi_mode, " Multi queue mode " 98 "(0 Disable; 1 Enable (default))"); 99 100int num_queues; 101module_param(num_queues, int, 0); 102MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1" 103 " (default is as a number of CPUs)"); 104 105static int disable_tpa; 106module_param(disable_tpa, int, 0); 107MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 108 109#define INT_MODE_INTx 1 110#define INT_MODE_MSI 2 111static int int_mode; 112module_param(int_mode, int, 0); 113MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 114 "(1 INT#x; 2 MSI)"); 115 116static int dropless_fc; 117module_param(dropless_fc, int, 0); 118MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 119 120static int poll; 121module_param(poll, int, 0); 122MODULE_PARM_DESC(poll, " Use polling (for debug)"); 123 124static int mrrs = -1; 125module_param(mrrs, int, 0); 126MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 127 128static int debug; 129module_param(debug, int, 0); 130MODULE_PARM_DESC(debug, " Default debug msglevel"); 131 132 133 134struct workqueue_struct *bnx2x_wq; 135 136enum bnx2x_board_type { 137 BCM57710 = 0, 138 BCM57711, 139 BCM57711E, 140 BCM57712, 141 BCM57712_MF, 142 BCM57800, 143 BCM57800_MF, 144 BCM57810, 145 BCM57810_MF, 146 BCM57840, 147 BCM57840_MF 148}; 149 150/* indexed by board_type, above */ 151static struct { 152 char *name; 153} board_info[] __devinitdata = { 154 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, 155 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, 156 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, 157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, 158 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, 159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, 160 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, 161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, 162 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, 163 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, 164 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit " 165 "Ethernet Multi Function"} 166}; 167 168#ifndef PCI_DEVICE_ID_NX2_57710 169#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 170#endif 171#ifndef PCI_DEVICE_ID_NX2_57711 172#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 173#endif 174#ifndef PCI_DEVICE_ID_NX2_57711E 175#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 176#endif 177#ifndef PCI_DEVICE_ID_NX2_57712 178#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 179#endif 180#ifndef PCI_DEVICE_ID_NX2_57712_MF 181#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 182#endif 183#ifndef PCI_DEVICE_ID_NX2_57800 184#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 185#endif 186#ifndef PCI_DEVICE_ID_NX2_57800_MF 187#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 188#endif 189#ifndef PCI_DEVICE_ID_NX2_57810 190#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 191#endif 192#ifndef PCI_DEVICE_ID_NX2_57810_MF 193#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 194#endif 195#ifndef PCI_DEVICE_ID_NX2_57840 196#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 197#endif 198#ifndef PCI_DEVICE_ID_NX2_57840_MF 199#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 200#endif 201static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 210 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 211 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, 212 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 213 { 0 } 214}; 215 216MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 217 218/**************************************************************************** 219* General service functions 220****************************************************************************/ 221 222static inline void __storm_memset_dma_mapping(struct bnx2x *bp, 223 u32 addr, dma_addr_t mapping) 224{ 225 REG_WR(bp, addr, U64_LO(mapping)); 226 REG_WR(bp, addr + 4, U64_HI(mapping)); 227} 228 229static inline void storm_memset_spq_addr(struct bnx2x *bp, 230 dma_addr_t mapping, u16 abs_fid) 231{ 232 u32 addr = XSEM_REG_FAST_MEMORY + 233 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 234 235 __storm_memset_dma_mapping(bp, addr, mapping); 236} 237 238static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 239 u16 pf_id) 240{ 241 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 242 pf_id); 243 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 244 pf_id); 245 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 246 pf_id); 247 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 248 pf_id); 249} 250 251static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 252 u8 enable) 253{ 254 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 255 enable); 256 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 257 enable); 258 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 259 enable); 260 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 261 enable); 262} 263 264static inline void storm_memset_eq_data(struct bnx2x *bp, 265 struct event_ring_data *eq_data, 266 u16 pfid) 267{ 268 size_t size = sizeof(struct event_ring_data); 269 270 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 271 272 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 273} 274 275static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 276 u16 pfid) 277{ 278 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 279 REG_WR16(bp, addr, eq_prod); 280} 281 282/* used only at init 283 * locking is done by mcp 284 */ 285static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 286{ 287 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 288 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 289 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 290 PCICFG_VENDOR_ID_OFFSET); 291} 292 293static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 294{ 295 u32 val; 296 297 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 298 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 299 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 300 PCICFG_VENDOR_ID_OFFSET); 301 302 return val; 303} 304 305#define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 306#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 307#define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 308#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 309#define DMAE_DP_DST_NONE "dst_addr [none]" 310 311static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, 312 int msglvl) 313{ 314 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 315 316 switch (dmae->opcode & DMAE_COMMAND_DST) { 317 case DMAE_CMD_DST_PCI: 318 if (src_type == DMAE_CMD_SRC_PCI) 319 DP(msglvl, "DMAE: opcode 0x%08x\n" 320 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 321 "comp_addr [%x:%08x], comp_val 0x%08x\n", 322 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 323 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 324 dmae->comp_addr_hi, dmae->comp_addr_lo, 325 dmae->comp_val); 326 else 327 DP(msglvl, "DMAE: opcode 0x%08x\n" 328 "src [%08x], len [%d*4], dst [%x:%08x]\n" 329 "comp_addr [%x:%08x], comp_val 0x%08x\n", 330 dmae->opcode, dmae->src_addr_lo >> 2, 331 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 332 dmae->comp_addr_hi, dmae->comp_addr_lo, 333 dmae->comp_val); 334 break; 335 case DMAE_CMD_DST_GRC: 336 if (src_type == DMAE_CMD_SRC_PCI) 337 DP(msglvl, "DMAE: opcode 0x%08x\n" 338 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 339 "comp_addr [%x:%08x], comp_val 0x%08x\n", 340 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 341 dmae->len, dmae->dst_addr_lo >> 2, 342 dmae->comp_addr_hi, dmae->comp_addr_lo, 343 dmae->comp_val); 344 else 345 DP(msglvl, "DMAE: opcode 0x%08x\n" 346 "src [%08x], len [%d*4], dst [%08x]\n" 347 "comp_addr [%x:%08x], comp_val 0x%08x\n", 348 dmae->opcode, dmae->src_addr_lo >> 2, 349 dmae->len, dmae->dst_addr_lo >> 2, 350 dmae->comp_addr_hi, dmae->comp_addr_lo, 351 dmae->comp_val); 352 break; 353 default: 354 if (src_type == DMAE_CMD_SRC_PCI) 355 DP(msglvl, "DMAE: opcode 0x%08x\n" 356 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 357 "comp_addr [%x:%08x] comp_val 0x%08x\n", 358 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 359 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 360 dmae->comp_val); 361 else 362 DP(msglvl, "DMAE: opcode 0x%08x\n" 363 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 364 "comp_addr [%x:%08x] comp_val 0x%08x\n", 365 dmae->opcode, dmae->src_addr_lo >> 2, 366 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 367 dmae->comp_val); 368 break; 369 } 370 371} 372 373/* copy command into DMAE command memory and set DMAE command go */ 374void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 375{ 376 u32 cmd_offset; 377 int i; 378 379 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 380 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 381 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 382 383 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n", 384 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); 385 } 386 REG_WR(bp, dmae_reg_go_c[idx], 1); 387} 388 389u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 390{ 391 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 392 DMAE_CMD_C_ENABLE); 393} 394 395u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 396{ 397 return opcode & ~DMAE_CMD_SRC_RESET; 398} 399 400u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 401 bool with_comp, u8 comp_type) 402{ 403 u32 opcode = 0; 404 405 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 406 (dst_type << DMAE_COMMAND_DST_SHIFT)); 407 408 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 409 410 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 411 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | 412 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 413 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 414 415#ifdef __BIG_ENDIAN 416 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 417#else 418 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 419#endif 420 if (with_comp) 421 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 422 return opcode; 423} 424 425static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 426 struct dmae_command *dmae, 427 u8 src_type, u8 dst_type) 428{ 429 memset(dmae, 0, sizeof(struct dmae_command)); 430 431 /* set the opcode */ 432 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 433 true, DMAE_COMP_PCI); 434 435 /* fill in the completion parameters */ 436 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 437 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 438 dmae->comp_val = DMAE_COMP_VAL; 439} 440 441/* issue a dmae command over the init-channel and wailt for completion */ 442static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, 443 struct dmae_command *dmae) 444{ 445 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 446 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 447 int rc = 0; 448 449 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n", 450 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 451 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 452 453 /* 454 * Lock the dmae channel. Disable BHs to prevent a dead-lock 455 * as long as this code is called both from syscall context and 456 * from ndo_set_rx_mode() flow that may be called from BH. 457 */ 458 spin_lock_bh(&bp->dmae_lock); 459 460 /* reset completion */ 461 *wb_comp = 0; 462 463 /* post the command on the channel used for initializations */ 464 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 465 466 /* wait for completion */ 467 udelay(5); 468 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 469 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); 470 471 if (!cnt) { 472 BNX2X_ERR("DMAE timeout!\n"); 473 rc = DMAE_TIMEOUT; 474 goto unlock; 475 } 476 cnt--; 477 udelay(50); 478 } 479 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 480 BNX2X_ERR("DMAE PCI error!\n"); 481 rc = DMAE_PCI_ERROR; 482 } 483 484 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n", 485 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 486 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 487 488unlock: 489 spin_unlock_bh(&bp->dmae_lock); 490 return rc; 491} 492 493void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 494 u32 len32) 495{ 496 struct dmae_command dmae; 497 498 if (!bp->dmae_ready) { 499 u32 *data = bnx2x_sp(bp, wb_data[0]); 500 501 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)" 502 " using indirect\n", dst_addr, len32); 503 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 504 return; 505 } 506 507 /* set opcode and fixed command fields */ 508 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 509 510 /* fill in addresses and len */ 511 dmae.src_addr_lo = U64_LO(dma_addr); 512 dmae.src_addr_hi = U64_HI(dma_addr); 513 dmae.dst_addr_lo = dst_addr >> 2; 514 dmae.dst_addr_hi = 0; 515 dmae.len = len32; 516 517 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 518 519 /* issue the command and wait for completion */ 520 bnx2x_issue_dmae_with_comp(bp, &dmae); 521} 522 523void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 524{ 525 struct dmae_command dmae; 526 527 if (!bp->dmae_ready) { 528 u32 *data = bnx2x_sp(bp, wb_data[0]); 529 int i; 530 531 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)" 532 " using indirect\n", src_addr, len32); 533 for (i = 0; i < len32; i++) 534 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 535 return; 536 } 537 538 /* set opcode and fixed command fields */ 539 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 540 541 /* fill in addresses and len */ 542 dmae.src_addr_lo = src_addr >> 2; 543 dmae.src_addr_hi = 0; 544 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 545 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 546 dmae.len = len32; 547 548 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 549 550 /* issue the command and wait for completion */ 551 bnx2x_issue_dmae_with_comp(bp, &dmae); 552} 553 554static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 555 u32 addr, u32 len) 556{ 557 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 558 int offset = 0; 559 560 while (len > dmae_wr_max) { 561 bnx2x_write_dmae(bp, phys_addr + offset, 562 addr + offset, dmae_wr_max); 563 offset += dmae_wr_max * 4; 564 len -= dmae_wr_max; 565 } 566 567 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 568} 569 570/* used only for slowpath so not inlined */ 571static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo) 572{ 573 u32 wb_write[2]; 574 575 wb_write[0] = val_hi; 576 wb_write[1] = val_lo; 577 REG_WR_DMAE(bp, reg, wb_write, 2); 578} 579 580#ifdef USE_WB_RD 581static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg) 582{ 583 u32 wb_data[2]; 584 585 REG_RD_DMAE(bp, reg, wb_data, 2); 586 587 return HILO_U64(wb_data[0], wb_data[1]); 588} 589#endif 590 591static int bnx2x_mc_assert(struct bnx2x *bp) 592{ 593 char last_idx; 594 int i, rc = 0; 595 u32 row0, row1, row2, row3; 596 597 /* XSTORM */ 598 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + 599 XSTORM_ASSERT_LIST_INDEX_OFFSET); 600 if (last_idx) 601 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 602 603 /* print the asserts */ 604 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 605 606 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + 607 XSTORM_ASSERT_LIST_OFFSET(i)); 608 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + 609 XSTORM_ASSERT_LIST_OFFSET(i) + 4); 610 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + 611 XSTORM_ASSERT_LIST_OFFSET(i) + 8); 612 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + 613 XSTORM_ASSERT_LIST_OFFSET(i) + 12); 614 615 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 616 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x" 617 " 0x%08x 0x%08x 0x%08x\n", 618 i, row3, row2, row1, row0); 619 rc++; 620 } else { 621 break; 622 } 623 } 624 625 /* TSTORM */ 626 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + 627 TSTORM_ASSERT_LIST_INDEX_OFFSET); 628 if (last_idx) 629 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 630 631 /* print the asserts */ 632 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 633 634 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + 635 TSTORM_ASSERT_LIST_OFFSET(i)); 636 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + 637 TSTORM_ASSERT_LIST_OFFSET(i) + 4); 638 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + 639 TSTORM_ASSERT_LIST_OFFSET(i) + 8); 640 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + 641 TSTORM_ASSERT_LIST_OFFSET(i) + 12); 642 643 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 644 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x" 645 " 0x%08x 0x%08x 0x%08x\n", 646 i, row3, row2, row1, row0); 647 rc++; 648 } else { 649 break; 650 } 651 } 652 653 /* CSTORM */ 654 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + 655 CSTORM_ASSERT_LIST_INDEX_OFFSET); 656 if (last_idx) 657 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 658 659 /* print the asserts */ 660 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 661 662 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + 663 CSTORM_ASSERT_LIST_OFFSET(i)); 664 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + 665 CSTORM_ASSERT_LIST_OFFSET(i) + 4); 666 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + 667 CSTORM_ASSERT_LIST_OFFSET(i) + 8); 668 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + 669 CSTORM_ASSERT_LIST_OFFSET(i) + 12); 670 671 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 672 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x" 673 " 0x%08x 0x%08x 0x%08x\n", 674 i, row3, row2, row1, row0); 675 rc++; 676 } else { 677 break; 678 } 679 } 680 681 /* USTORM */ 682 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + 683 USTORM_ASSERT_LIST_INDEX_OFFSET); 684 if (last_idx) 685 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 686 687 /* print the asserts */ 688 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 689 690 row0 = REG_RD(bp, BAR_USTRORM_INTMEM + 691 USTORM_ASSERT_LIST_OFFSET(i)); 692 row1 = REG_RD(bp, BAR_USTRORM_INTMEM + 693 USTORM_ASSERT_LIST_OFFSET(i) + 4); 694 row2 = REG_RD(bp, BAR_USTRORM_INTMEM + 695 USTORM_ASSERT_LIST_OFFSET(i) + 8); 696 row3 = REG_RD(bp, BAR_USTRORM_INTMEM + 697 USTORM_ASSERT_LIST_OFFSET(i) + 12); 698 699 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 700 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x" 701 " 0x%08x 0x%08x 0x%08x\n", 702 i, row3, row2, row1, row0); 703 rc++; 704 } else { 705 break; 706 } 707 } 708 709 return rc; 710} 711 712void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 713{ 714 u32 addr, val; 715 u32 mark, offset; 716 __be32 data[9]; 717 int word; 718 u32 trace_shmem_base; 719 if (BP_NOMCP(bp)) { 720 BNX2X_ERR("NO MCP - can not dump\n"); 721 return; 722 } 723 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 724 (bp->common.bc_ver & 0xff0000) >> 16, 725 (bp->common.bc_ver & 0xff00) >> 8, 726 (bp->common.bc_ver & 0xff)); 727 728 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 729 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 730 printk("%s" "MCP PC at 0x%x\n", lvl, val); 731 732 if (BP_PATH(bp) == 0) 733 trace_shmem_base = bp->common.shmem_base; 734 else 735 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 736 addr = trace_shmem_base - 0x0800 + 4; 737 mark = REG_RD(bp, addr); 738 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 739 + ((mark + 0x3) & ~0x3) - 0x08000000; 740 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 741 742 printk("%s", lvl); 743 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { 744 for (word = 0; word < 8; word++) 745 data[word] = htonl(REG_RD(bp, offset + 4*word)); 746 data[8] = 0x0; 747 pr_cont("%s", (char *)data); 748 } 749 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 750 for (word = 0; word < 8; word++) 751 data[word] = htonl(REG_RD(bp, offset + 4*word)); 752 data[8] = 0x0; 753 pr_cont("%s", (char *)data); 754 } 755 printk("%s" "end of fw dump\n", lvl); 756} 757 758static inline void bnx2x_fw_dump(struct bnx2x *bp) 759{ 760 bnx2x_fw_dump_lvl(bp, KERN_ERR); 761} 762 763void bnx2x_panic_dump(struct bnx2x *bp) 764{ 765 int i; 766 u16 j; 767 struct hc_sp_status_block_data sp_sb_data; 768 int func = BP_FUNC(bp); 769#ifdef BNX2X_STOP_ON_ERROR 770 u16 start = 0, end = 0; 771 u8 cos; 772#endif 773 774 bp->stats_state = STATS_STATE_DISABLED; 775 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 776 777 BNX2X_ERR("begin crash dump -----------------\n"); 778 779 /* Indices */ 780 /* Common */ 781 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)" 782 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 783 bp->def_idx, bp->def_att_idx, bp->attn_state, 784 bp->spq_prod_idx, bp->stats_counter); 785 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 786 bp->def_status_blk->atten_status_block.attn_bits, 787 bp->def_status_blk->atten_status_block.attn_bits_ack, 788 bp->def_status_blk->atten_status_block.status_block_id, 789 bp->def_status_blk->atten_status_block.attn_bits_index); 790 BNX2X_ERR(" def ("); 791 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 792 pr_cont("0x%x%s", 793 bp->def_status_blk->sp_sb.index_values[i], 794 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 795 796 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 797 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + 798 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 799 i*sizeof(u32)); 800 801 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 802 sp_sb_data.igu_sb_id, 803 sp_sb_data.igu_seg_id, 804 sp_sb_data.p_func.pf_id, 805 sp_sb_data.p_func.vnic_id, 806 sp_sb_data.p_func.vf_id, 807 sp_sb_data.p_func.vf_valid, 808 sp_sb_data.state); 809 810 811 for_each_eth_queue(bp, i) { 812 struct bnx2x_fastpath *fp = &bp->fp[i]; 813 int loop; 814 struct hc_status_block_data_e2 sb_data_e2; 815 struct hc_status_block_data_e1x sb_data_e1x; 816 struct hc_status_block_sm *hc_sm_p = 817 CHIP_IS_E1x(bp) ? 818 sb_data_e1x.common.state_machine : 819 sb_data_e2.common.state_machine; 820 struct hc_index_data *hc_index_p = 821 CHIP_IS_E1x(bp) ? 822 sb_data_e1x.index_data : 823 sb_data_e2.index_data; 824 u8 data_size, cos; 825 u32 *sb_data_p; 826 struct bnx2x_fp_txdata txdata; 827 828 /* Rx */ 829 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)" 830 " rx_comp_prod(0x%x)" 831 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 832 i, fp->rx_bd_prod, fp->rx_bd_cons, 833 fp->rx_comp_prod, 834 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 835 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)" 836 " fp_hc_idx(0x%x)\n", 837 fp->rx_sge_prod, fp->last_max_sge, 838 le16_to_cpu(fp->fp_hc_idx)); 839 840 /* Tx */ 841 for_each_cos_in_tx_queue(fp, cos) 842 { 843 txdata = fp->txdata[cos]; 844 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)" 845 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)" 846 " *tx_cons_sb(0x%x)\n", 847 i, txdata.tx_pkt_prod, 848 txdata.tx_pkt_cons, txdata.tx_bd_prod, 849 txdata.tx_bd_cons, 850 le16_to_cpu(*txdata.tx_cons_sb)); 851 } 852 853 loop = CHIP_IS_E1x(bp) ? 854 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 855 856 /* host sb data */ 857 858#ifdef BCM_CNIC 859 if (IS_FCOE_FP(fp)) 860 continue; 861#endif 862 BNX2X_ERR(" run indexes ("); 863 for (j = 0; j < HC_SB_MAX_SM; j++) 864 pr_cont("0x%x%s", 865 fp->sb_running_index[j], 866 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 867 868 BNX2X_ERR(" indexes ("); 869 for (j = 0; j < loop; j++) 870 pr_cont("0x%x%s", 871 fp->sb_index_values[j], 872 (j == loop - 1) ? ")" : " "); 873 /* fw sb data */ 874 data_size = CHIP_IS_E1x(bp) ? 875 sizeof(struct hc_status_block_data_e1x) : 876 sizeof(struct hc_status_block_data_e2); 877 data_size /= sizeof(u32); 878 sb_data_p = CHIP_IS_E1x(bp) ? 879 (u32 *)&sb_data_e1x : 880 (u32 *)&sb_data_e2; 881 /* copy sb data in here */ 882 for (j = 0; j < data_size; j++) 883 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 884 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 885 j * sizeof(u32)); 886 887 if (!CHIP_IS_E1x(bp)) { 888 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 889 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 890 "state(0x%x)\n", 891 sb_data_e2.common.p_func.pf_id, 892 sb_data_e2.common.p_func.vf_id, 893 sb_data_e2.common.p_func.vf_valid, 894 sb_data_e2.common.p_func.vnic_id, 895 sb_data_e2.common.same_igu_sb_1b, 896 sb_data_e2.common.state); 897 } else { 898 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 899 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 900 "state(0x%x)\n", 901 sb_data_e1x.common.p_func.pf_id, 902 sb_data_e1x.common.p_func.vf_id, 903 sb_data_e1x.common.p_func.vf_valid, 904 sb_data_e1x.common.p_func.vnic_id, 905 sb_data_e1x.common.same_igu_sb_1b, 906 sb_data_e1x.common.state); 907 } 908 909 /* SB_SMs data */ 910 for (j = 0; j < HC_SB_MAX_SM; j++) { 911 pr_cont("SM[%d] __flags (0x%x) " 912 "igu_sb_id (0x%x) igu_seg_id(0x%x) " 913 "time_to_expire (0x%x) " 914 "timer_value(0x%x)\n", j, 915 hc_sm_p[j].__flags, 916 hc_sm_p[j].igu_sb_id, 917 hc_sm_p[j].igu_seg_id, 918 hc_sm_p[j].time_to_expire, 919 hc_sm_p[j].timer_value); 920 } 921 922 /* Indecies data */ 923 for (j = 0; j < loop; j++) { 924 pr_cont("INDEX[%d] flags (0x%x) " 925 "timeout (0x%x)\n", j, 926 hc_index_p[j].flags, 927 hc_index_p[j].timeout); 928 } 929 } 930 931#ifdef BNX2X_STOP_ON_ERROR 932 /* Rings */ 933 /* Rx */ 934 for_each_rx_queue(bp, i) { 935 struct bnx2x_fastpath *fp = &bp->fp[i]; 936 937 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 938 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 939 for (j = start; j != end; j = RX_BD(j + 1)) { 940 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 941 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 942 943 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 944 i, j, rx_bd[1], rx_bd[0], sw_bd->skb); 945 } 946 947 start = RX_SGE(fp->rx_sge_prod); 948 end = RX_SGE(fp->last_max_sge); 949 for (j = start; j != end; j = RX_SGE(j + 1)) { 950 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 951 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 952 953 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 954 i, j, rx_sge[1], rx_sge[0], sw_page->page); 955 } 956 957 start = RCQ_BD(fp->rx_comp_cons - 10); 958 end = RCQ_BD(fp->rx_comp_cons + 503); 959 for (j = start; j != end; j = RCQ_BD(j + 1)) { 960 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 961 962 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 963 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 964 } 965 } 966 967 /* Tx */ 968 for_each_tx_queue(bp, i) { 969 struct bnx2x_fastpath *fp = &bp->fp[i]; 970 for_each_cos_in_tx_queue(fp, cos) { 971 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; 972 973 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 974 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 975 for (j = start; j != end; j = TX_BD(j + 1)) { 976 struct sw_tx_bd *sw_bd = 977 &txdata->tx_buf_ring[j]; 978 979 BNX2X_ERR("fp%d: txdata %d, " 980 "packet[%x]=[%p,%x]\n", 981 i, cos, j, sw_bd->skb, 982 sw_bd->first_bd); 983 } 984 985 start = TX_BD(txdata->tx_bd_cons - 10); 986 end = TX_BD(txdata->tx_bd_cons + 254); 987 for (j = start; j != end; j = TX_BD(j + 1)) { 988 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 989 990 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=" 991 "[%x:%x:%x:%x]\n", 992 i, cos, j, tx_bd[0], tx_bd[1], 993 tx_bd[2], tx_bd[3]); 994 } 995 } 996 } 997#endif 998 bnx2x_fw_dump(bp); 999 bnx2x_mc_assert(bp); 1000 BNX2X_ERR("end crash dump -----------------\n"); 1001} 1002 1003/* 1004 * FLR Support for E2 1005 * 1006 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 1007 * initialization. 1008 */ 1009#define FLR_WAIT_USEC 10000 /* 10 miliseconds */ 1010#define FLR_WAIT_INTERAVAL 50 /* usec */ 1011#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */ 1012 1013struct pbf_pN_buf_regs { 1014 int pN; 1015 u32 init_crd; 1016 u32 crd; 1017 u32 crd_freed; 1018}; 1019 1020struct pbf_pN_cmd_regs { 1021 int pN; 1022 u32 lines_occup; 1023 u32 lines_freed; 1024}; 1025 1026static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1027 struct pbf_pN_buf_regs *regs, 1028 u32 poll_count) 1029{ 1030 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1031 u32 cur_cnt = poll_count; 1032 1033 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1034 crd = crd_start = REG_RD(bp, regs->crd); 1035 init_crd = REG_RD(bp, regs->init_crd); 1036 1037 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1038 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1039 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1040 1041 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1042 (init_crd - crd_start))) { 1043 if (cur_cnt--) { 1044 udelay(FLR_WAIT_INTERAVAL); 1045 crd = REG_RD(bp, regs->crd); 1046 crd_freed = REG_RD(bp, regs->crd_freed); 1047 } else { 1048 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1049 regs->pN); 1050 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1051 regs->pN, crd); 1052 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1053 regs->pN, crd_freed); 1054 break; 1055 } 1056 } 1057 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1058 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN); 1059} 1060 1061static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1062 struct pbf_pN_cmd_regs *regs, 1063 u32 poll_count) 1064{ 1065 u32 occup, to_free, freed, freed_start; 1066 u32 cur_cnt = poll_count; 1067 1068 occup = to_free = REG_RD(bp, regs->lines_occup); 1069 freed = freed_start = REG_RD(bp, regs->lines_freed); 1070 1071 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1072 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1073 1074 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1075 if (cur_cnt--) { 1076 udelay(FLR_WAIT_INTERAVAL); 1077 occup = REG_RD(bp, regs->lines_occup); 1078 freed = REG_RD(bp, regs->lines_freed); 1079 } else { 1080 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1081 regs->pN); 1082 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1083 regs->pN, occup); 1084 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1085 regs->pN, freed); 1086 break; 1087 } 1088 } 1089 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1090 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN); 1091} 1092 1093static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1094 u32 expected, u32 poll_count) 1095{ 1096 u32 cur_cnt = poll_count; 1097 u32 val; 1098 1099 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1100 udelay(FLR_WAIT_INTERAVAL); 1101 1102 return val; 1103} 1104 1105static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1106 char *msg, u32 poll_cnt) 1107{ 1108 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1109 if (val != 0) { 1110 BNX2X_ERR("%s usage count=%d\n", msg, val); 1111 return 1; 1112 } 1113 return 0; 1114} 1115 1116static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1117{ 1118 /* adjust polling timeout */ 1119 if (CHIP_REV_IS_EMUL(bp)) 1120 return FLR_POLL_CNT * 2000; 1121 1122 if (CHIP_REV_IS_FPGA(bp)) 1123 return FLR_POLL_CNT * 120; 1124 1125 return FLR_POLL_CNT; 1126} 1127 1128static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1129{ 1130 struct pbf_pN_cmd_regs cmd_regs[] = { 1131 {0, (CHIP_IS_E3B0(bp)) ? 1132 PBF_REG_TQ_OCCUPANCY_Q0 : 1133 PBF_REG_P0_TQ_OCCUPANCY, 1134 (CHIP_IS_E3B0(bp)) ? 1135 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1136 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1137 {1, (CHIP_IS_E3B0(bp)) ? 1138 PBF_REG_TQ_OCCUPANCY_Q1 : 1139 PBF_REG_P1_TQ_OCCUPANCY, 1140 (CHIP_IS_E3B0(bp)) ? 1141 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1142 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1143 {4, (CHIP_IS_E3B0(bp)) ? 1144 PBF_REG_TQ_OCCUPANCY_LB_Q : 1145 PBF_REG_P4_TQ_OCCUPANCY, 1146 (CHIP_IS_E3B0(bp)) ? 1147 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1148 PBF_REG_P4_TQ_LINES_FREED_CNT} 1149 }; 1150 1151 struct pbf_pN_buf_regs buf_regs[] = { 1152 {0, (CHIP_IS_E3B0(bp)) ? 1153 PBF_REG_INIT_CRD_Q0 : 1154 PBF_REG_P0_INIT_CRD , 1155 (CHIP_IS_E3B0(bp)) ? 1156 PBF_REG_CREDIT_Q0 : 1157 PBF_REG_P0_CREDIT, 1158 (CHIP_IS_E3B0(bp)) ? 1159 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1160 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1161 {1, (CHIP_IS_E3B0(bp)) ? 1162 PBF_REG_INIT_CRD_Q1 : 1163 PBF_REG_P1_INIT_CRD, 1164 (CHIP_IS_E3B0(bp)) ? 1165 PBF_REG_CREDIT_Q1 : 1166 PBF_REG_P1_CREDIT, 1167 (CHIP_IS_E3B0(bp)) ? 1168 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1169 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1170 {4, (CHIP_IS_E3B0(bp)) ? 1171 PBF_REG_INIT_CRD_LB_Q : 1172 PBF_REG_P4_INIT_CRD, 1173 (CHIP_IS_E3B0(bp)) ? 1174 PBF_REG_CREDIT_LB_Q : 1175 PBF_REG_P4_CREDIT, 1176 (CHIP_IS_E3B0(bp)) ? 1177 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1178 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1179 }; 1180 1181 int i; 1182 1183 /* Verify the command queues are flushed P0, P1, P4 */ 1184 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1185 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1186 1187 1188 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1189 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1190 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1191} 1192 1193#define OP_GEN_PARAM(param) \ 1194 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1195 1196#define OP_GEN_TYPE(type) \ 1197 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1198 1199#define OP_GEN_AGG_VECT(index) \ 1200 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1201 1202 1203static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, 1204 u32 poll_cnt) 1205{ 1206 struct sdm_op_gen op_gen = {0}; 1207 1208 u32 comp_addr = BAR_CSTRORM_INTMEM + 1209 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1210 int ret = 0; 1211 1212 if (REG_RD(bp, comp_addr)) { 1213 BNX2X_ERR("Cleanup complete is not 0\n"); 1214 return 1; 1215 } 1216 1217 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1218 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1219 op_gen.command |= OP_GEN_AGG_VECT(clnup_func); 1220 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1221 1222 DP(BNX2X_MSG_SP, "FW Final cleanup\n"); 1223 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); 1224 1225 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1226 BNX2X_ERR("FW final cleanup did not succeed\n"); 1227 ret = 1; 1228 } 1229 /* Zero completion for nxt FLR */ 1230 REG_WR(bp, comp_addr, 0); 1231 1232 return ret; 1233} 1234 1235static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1236{ 1237 int pos; 1238 u16 status; 1239 1240 pos = pci_pcie_cap(dev); 1241 if (!pos) 1242 return false; 1243 1244 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 1245 return status & PCI_EXP_DEVSTA_TRPND; 1246} 1247 1248/* PF FLR specific routines 1249*/ 1250static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1251{ 1252 1253 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1254 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1255 CFC_REG_NUM_LCIDS_INSIDE_PF, 1256 "CFC PF usage counter timed out", 1257 poll_cnt)) 1258 return 1; 1259 1260 1261 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1262 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1263 DORQ_REG_PF_USAGE_CNT, 1264 "DQ PF usage counter timed out", 1265 poll_cnt)) 1266 return 1; 1267 1268 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1269 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1270 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1271 "QM PF usage counter timed out", 1272 poll_cnt)) 1273 return 1; 1274 1275 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1276 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1277 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1278 "Timers VNIC usage counter timed out", 1279 poll_cnt)) 1280 return 1; 1281 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1282 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1283 "Timers NUM_SCANS usage counter timed out", 1284 poll_cnt)) 1285 return 1; 1286 1287 /* Wait DMAE PF usage counter to zero */ 1288 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1289 dmae_reg_go_c[INIT_DMAE_C(bp)], 1290 "DMAE dommand register timed out", 1291 poll_cnt)) 1292 return 1; 1293 1294 return 0; 1295} 1296 1297static void bnx2x_hw_enable_status(struct bnx2x *bp) 1298{ 1299 u32 val; 1300 1301 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1302 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1303 1304 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1305 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1306 1307 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1308 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1309 1310 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1311 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1312 1313 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1314 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1315 1316 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1317 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1318 1319 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1320 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1321 1322 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1323 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1324 val); 1325} 1326 1327static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1328{ 1329 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1330 1331 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1332 1333 /* Re-enable PF target read access */ 1334 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1335 1336 /* Poll HW usage counters */ 1337 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1338 return -EBUSY; 1339 1340 /* Zero the igu 'trailing edge' and 'leading edge' */ 1341 1342 /* Send the FW cleanup command */ 1343 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1344 return -EBUSY; 1345 1346 /* ATC cleanup */ 1347 1348 /* Verify TX hw is flushed */ 1349 bnx2x_tx_hw_flushed(bp, poll_cnt); 1350 1351 /* Wait 100ms (not adjusted according to platform) */ 1352 msleep(100); 1353 1354 /* Verify no pending pci transactions */ 1355 if (bnx2x_is_pcie_pending(bp->pdev)) 1356 BNX2X_ERR("PCIE Transactions still pending\n"); 1357 1358 /* Debug */ 1359 bnx2x_hw_enable_status(bp); 1360 1361 /* 1362 * Master enable - Due to WB DMAE writes performed before this 1363 * register is re-initialized as part of the regular function init 1364 */ 1365 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1366 1367 return 0; 1368} 1369 1370static void bnx2x_hc_int_enable(struct bnx2x *bp) 1371{ 1372 int port = BP_PORT(bp); 1373 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1374 u32 val = REG_RD(bp, addr); 1375 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1376 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1377 1378 if (msix) { 1379 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1380 HC_CONFIG_0_REG_INT_LINE_EN_0); 1381 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1382 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1383 } else if (msi) { 1384 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1385 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1386 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1387 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1388 } else { 1389 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1390 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1391 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1392 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1393 1394 if (!CHIP_IS_E1(bp)) { 1395 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1396 val, port, addr); 1397 1398 REG_WR(bp, addr, val); 1399 1400 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1401 } 1402 } 1403 1404 if (CHIP_IS_E1(bp)) 1405 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1406 1407 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", 1408 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1409 1410 REG_WR(bp, addr, val); 1411 /* 1412 * Ensure that HC_CONFIG is written before leading/trailing edge config 1413 */ 1414 mmiowb(); 1415 barrier(); 1416 1417 if (!CHIP_IS_E1(bp)) { 1418 /* init leading/trailing edge */ 1419 if (IS_MF(bp)) { 1420 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1421 if (bp->port.pmf) 1422 /* enable nig and gpio3 attention */ 1423 val |= 0x1100; 1424 } else 1425 val = 0xffff; 1426 1427 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1428 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1429 } 1430 1431 /* Make sure that interrupts are indeed enabled from here on */ 1432 mmiowb(); 1433} 1434 1435static void bnx2x_igu_int_enable(struct bnx2x *bp) 1436{ 1437 u32 val; 1438 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1439 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1440 1441 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1442 1443 if (msix) { 1444 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1445 IGU_PF_CONF_SINGLE_ISR_EN); 1446 val |= (IGU_PF_CONF_FUNC_EN | 1447 IGU_PF_CONF_MSI_MSIX_EN | 1448 IGU_PF_CONF_ATTN_BIT_EN); 1449 } else if (msi) { 1450 val &= ~IGU_PF_CONF_INT_LINE_EN; 1451 val |= (IGU_PF_CONF_FUNC_EN | 1452 IGU_PF_CONF_MSI_MSIX_EN | 1453 IGU_PF_CONF_ATTN_BIT_EN | 1454 IGU_PF_CONF_SINGLE_ISR_EN); 1455 } else { 1456 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1457 val |= (IGU_PF_CONF_FUNC_EN | 1458 IGU_PF_CONF_INT_LINE_EN | 1459 IGU_PF_CONF_ATTN_BIT_EN | 1460 IGU_PF_CONF_SINGLE_ISR_EN); 1461 } 1462 1463 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n", 1464 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1465 1466 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1467 1468 barrier(); 1469 1470 /* init leading/trailing edge */ 1471 if (IS_MF(bp)) { 1472 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1473 if (bp->port.pmf) 1474 /* enable nig and gpio3 attention */ 1475 val |= 0x1100; 1476 } else 1477 val = 0xffff; 1478 1479 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1480 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1481 1482 /* Make sure that interrupts are indeed enabled from here on */ 1483 mmiowb(); 1484} 1485 1486void bnx2x_int_enable(struct bnx2x *bp) 1487{ 1488 if (bp->common.int_block == INT_BLOCK_HC) 1489 bnx2x_hc_int_enable(bp); 1490 else 1491 bnx2x_igu_int_enable(bp); 1492} 1493 1494static void bnx2x_hc_int_disable(struct bnx2x *bp) 1495{ 1496 int port = BP_PORT(bp); 1497 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1498 u32 val = REG_RD(bp, addr); 1499 1500 /* 1501 * in E1 we must use only PCI configuration space to disable 1502 * MSI/MSIX capablility 1503 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 1504 */ 1505 if (CHIP_IS_E1(bp)) { 1506 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 1507 * Use mask register to prevent from HC sending interrupts 1508 * after we exit the function 1509 */ 1510 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 1511 1512 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1513 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1514 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1515 } else 1516 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1517 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1518 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1519 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1520 1521 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1522 val, port, addr); 1523 1524 /* flush all outstanding writes */ 1525 mmiowb(); 1526 1527 REG_WR(bp, addr, val); 1528 if (REG_RD(bp, addr) != val) 1529 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1530} 1531 1532static void bnx2x_igu_int_disable(struct bnx2x *bp) 1533{ 1534 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1535 1536 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 1537 IGU_PF_CONF_INT_LINE_EN | 1538 IGU_PF_CONF_ATTN_BIT_EN); 1539 1540 DP(NETIF_MSG_INTR, "write %x to IGU\n", val); 1541 1542 /* flush all outstanding writes */ 1543 mmiowb(); 1544 1545 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1546 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 1547 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1548} 1549 1550void bnx2x_int_disable(struct bnx2x *bp) 1551{ 1552 if (bp->common.int_block == INT_BLOCK_HC) 1553 bnx2x_hc_int_disable(bp); 1554 else 1555 bnx2x_igu_int_disable(bp); 1556} 1557 1558void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1559{ 1560 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1561 int i, offset; 1562 1563 if (disable_hw) 1564 /* prevent the HW from sending interrupts */ 1565 bnx2x_int_disable(bp); 1566 1567 /* make sure all ISRs are done */ 1568 if (msix) { 1569 synchronize_irq(bp->msix_table[0].vector); 1570 offset = 1; 1571#ifdef BCM_CNIC 1572 offset++; 1573#endif 1574 for_each_eth_queue(bp, i) 1575 synchronize_irq(bp->msix_table[offset++].vector); 1576 } else 1577 synchronize_irq(bp->pdev->irq); 1578 1579 /* make sure sp_task is not running */ 1580 cancel_delayed_work(&bp->sp_task); 1581 cancel_delayed_work(&bp->period_task); 1582 flush_workqueue(bnx2x_wq); 1583} 1584 1585/* fast path */ 1586 1587/* 1588 * General service functions 1589 */ 1590 1591/* Return true if succeeded to acquire the lock */ 1592static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1593{ 1594 u32 lock_status; 1595 u32 resource_bit = (1 << resource); 1596 int func = BP_FUNC(bp); 1597 u32 hw_lock_control_reg; 1598 1599 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource); 1600 1601 /* Validating that the resource is within range */ 1602 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1603 DP(NETIF_MSG_HW, 1604 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1605 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1606 return false; 1607 } 1608 1609 if (func <= 5) 1610 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1611 else 1612 hw_lock_control_reg = 1613 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1614 1615 /* Try to acquire the lock */ 1616 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1617 lock_status = REG_RD(bp, hw_lock_control_reg); 1618 if (lock_status & resource_bit) 1619 return true; 1620 1621 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource); 1622 return false; 1623} 1624 1625/** 1626 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1627 * 1628 * @bp: driver handle 1629 * 1630 * Returns the recovery leader resource id according to the engine this function 1631 * belongs to. Currently only only 2 engines is supported. 1632 */ 1633static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1634{ 1635 if (BP_PATH(bp)) 1636 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1637 else 1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1639} 1640 1641/** 1642 * bnx2x_trylock_leader_lock- try to aquire a leader lock. 1643 * 1644 * @bp: driver handle 1645 * 1646 * Tries to aquire a leader lock for cuurent engine. 1647 */ 1648static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1649{ 1650 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1651} 1652 1653#ifdef BCM_CNIC 1654static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1655#endif 1656 1657void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1658{ 1659 struct bnx2x *bp = fp->bp; 1660 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1661 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1662 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1663 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj; 1664 1665 DP(BNX2X_MSG_SP, 1666 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1667 fp->index, cid, command, bp->state, 1668 rr_cqe->ramrod_cqe.ramrod_type); 1669 1670 switch (command) { 1671 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1672 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1673 drv_cmd = BNX2X_Q_CMD_UPDATE; 1674 break; 1675 1676 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1677 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1678 drv_cmd = BNX2X_Q_CMD_SETUP; 1679 break; 1680 1681 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1682 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1683 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1684 break; 1685 1686 case (RAMROD_CMD_ID_ETH_HALT): 1687 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1688 drv_cmd = BNX2X_Q_CMD_HALT; 1689 break; 1690 1691 case (RAMROD_CMD_ID_ETH_TERMINATE): 1692 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); 1693 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1694 break; 1695 1696 case (RAMROD_CMD_ID_ETH_EMPTY): 1697 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1698 drv_cmd = BNX2X_Q_CMD_EMPTY; 1699 break; 1700 1701 default: 1702 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1703 command, fp->index); 1704 return; 1705 } 1706 1707 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1708 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1709 /* q_obj->complete_cmd() failure means that this was 1710 * an unexpected completion. 1711 * 1712 * In this case we don't want to increase the bp->spq_left 1713 * because apparently we haven't sent this command the first 1714 * place. 1715 */ 1716#ifdef BNX2X_STOP_ON_ERROR 1717 bnx2x_panic(); 1718#else 1719 return; 1720#endif 1721 1722 smp_mb__before_atomic_inc(); 1723 atomic_inc(&bp->cq_spq_left); 1724 /* push the change in bp->spq_left and towards the memory */ 1725 smp_mb__after_atomic_inc(); 1726 1727 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1728 1729 return; 1730} 1731 1732void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 1733 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) 1734{ 1735 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; 1736 1737 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, 1738 start); 1739} 1740 1741irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1742{ 1743 struct bnx2x *bp = netdev_priv(dev_instance); 1744 u16 status = bnx2x_ack_int(bp); 1745 u16 mask; 1746 int i; 1747 u8 cos; 1748 1749 /* Return here if interrupt is shared and it's not for us */ 1750 if (unlikely(status == 0)) { 1751 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1752 return IRQ_NONE; 1753 } 1754 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1755 1756#ifdef BNX2X_STOP_ON_ERROR 1757 if (unlikely(bp->panic)) 1758 return IRQ_HANDLED; 1759#endif 1760 1761 for_each_eth_queue(bp, i) { 1762 struct bnx2x_fastpath *fp = &bp->fp[i]; 1763 1764 mask = 0x2 << (fp->index + CNIC_PRESENT); 1765 if (status & mask) { 1766 /* Handle Rx or Tx according to SB id */ 1767 prefetch(fp->rx_cons_sb); 1768 for_each_cos_in_tx_queue(fp, cos) 1769 prefetch(fp->txdata[cos].tx_cons_sb); 1770 prefetch(&fp->sb_running_index[SM_RX_ID]); 1771 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 1772 status &= ~mask; 1773 } 1774 } 1775 1776#ifdef BCM_CNIC 1777 mask = 0x2; 1778 if (status & (mask | 0x1)) { 1779 struct cnic_ops *c_ops = NULL; 1780 1781 if (likely(bp->state == BNX2X_STATE_OPEN)) { 1782 rcu_read_lock(); 1783 c_ops = rcu_dereference(bp->cnic_ops); 1784 if (c_ops) 1785 c_ops->cnic_handler(bp->cnic_data, NULL); 1786 rcu_read_unlock(); 1787 } 1788 1789 status &= ~mask; 1790 } 1791#endif 1792 1793 if (unlikely(status & 0x1)) { 1794 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1795 1796 status &= ~0x1; 1797 if (!status) 1798 return IRQ_HANDLED; 1799 } 1800 1801 if (unlikely(status)) 1802 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1803 status); 1804 1805 return IRQ_HANDLED; 1806} 1807 1808/* Link */ 1809 1810/* 1811 * General service functions 1812 */ 1813 1814int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 1815{ 1816 u32 lock_status; 1817 u32 resource_bit = (1 << resource); 1818 int func = BP_FUNC(bp); 1819 u32 hw_lock_control_reg; 1820 int cnt; 1821 1822 /* Validating that the resource is within range */ 1823 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1824 DP(NETIF_MSG_HW, 1825 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1826 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1827 return -EINVAL; 1828 } 1829 1830 if (func <= 5) { 1831 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1832 } else { 1833 hw_lock_control_reg = 1834 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1835 } 1836 1837 /* Validating that the resource is not already taken */ 1838 lock_status = REG_RD(bp, hw_lock_control_reg); 1839 if (lock_status & resource_bit) { 1840 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1841 lock_status, resource_bit); 1842 return -EEXIST; 1843 } 1844 1845 /* Try for 5 second every 5ms */ 1846 for (cnt = 0; cnt < 1000; cnt++) { 1847 /* Try to acquire the lock */ 1848 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1849 lock_status = REG_RD(bp, hw_lock_control_reg); 1850 if (lock_status & resource_bit) 1851 return 0; 1852 1853 msleep(5); 1854 } 1855 DP(NETIF_MSG_HW, "Timeout\n"); 1856 return -EAGAIN; 1857} 1858 1859int bnx2x_release_leader_lock(struct bnx2x *bp) 1860{ 1861 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1862} 1863 1864int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 1865{ 1866 u32 lock_status; 1867 u32 resource_bit = (1 << resource); 1868 int func = BP_FUNC(bp); 1869 u32 hw_lock_control_reg; 1870 1871 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource); 1872 1873 /* Validating that the resource is within range */ 1874 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1875 DP(NETIF_MSG_HW, 1876 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1877 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1878 return -EINVAL; 1879 } 1880 1881 if (func <= 5) { 1882 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1883 } else { 1884 hw_lock_control_reg = 1885 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1886 } 1887 1888 /* Validating that the resource is currently taken */ 1889 lock_status = REG_RD(bp, hw_lock_control_reg); 1890 if (!(lock_status & resource_bit)) { 1891 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1892 lock_status, resource_bit); 1893 return -EFAULT; 1894 } 1895 1896 REG_WR(bp, hw_lock_control_reg, resource_bit); 1897 return 0; 1898} 1899 1900 1901int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 1902{ 1903 /* The GPIO should be swapped if swap register is set and active */ 1904 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1905 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1906 int gpio_shift = gpio_num + 1907 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1908 u32 gpio_mask = (1 << gpio_shift); 1909 u32 gpio_reg; 1910 int value; 1911 1912 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1913 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1914 return -EINVAL; 1915 } 1916 1917 /* read GPIO value */ 1918 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1919 1920 /* get the requested pin value */ 1921 if ((gpio_reg & gpio_mask) == gpio_mask) 1922 value = 1; 1923 else 1924 value = 0; 1925 1926 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); 1927 1928 return value; 1929} 1930 1931int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 1932{ 1933 /* The GPIO should be swapped if swap register is set and active */ 1934 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1935 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1936 int gpio_shift = gpio_num + 1937 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1938 u32 gpio_mask = (1 << gpio_shift); 1939 u32 gpio_reg; 1940 1941 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1942 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1943 return -EINVAL; 1944 } 1945 1946 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1947 /* read GPIO and mask except the float bits */ 1948 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 1949 1950 switch (mode) { 1951 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1952 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n", 1953 gpio_num, gpio_shift); 1954 /* clear FLOAT and set CLR */ 1955 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1956 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 1957 break; 1958 1959 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 1960 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n", 1961 gpio_num, gpio_shift); 1962 /* clear FLOAT and set SET */ 1963 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1964 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 1965 break; 1966 1967 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 1968 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", 1969 gpio_num, gpio_shift); 1970 /* set FLOAT */ 1971 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1972 break; 1973 1974 default: 1975 break; 1976 } 1977 1978 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 1979 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1980 1981 return 0; 1982} 1983 1984int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 1985{ 1986 u32 gpio_reg = 0; 1987 int rc = 0; 1988 1989 /* Any port swapping should be handled by caller. */ 1990 1991 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1992 /* read GPIO and mask except the float bits */ 1993 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1994 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 1995 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 1996 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 1997 1998 switch (mode) { 1999 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2000 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 2001 /* set CLR */ 2002 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2003 break; 2004 2005 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2006 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 2007 /* set SET */ 2008 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2009 break; 2010 2011 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2012 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2013 /* set FLOAT */ 2014 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2015 break; 2016 2017 default: 2018 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2019 rc = -EINVAL; 2020 break; 2021 } 2022 2023 if (rc == 0) 2024 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2025 2026 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2027 2028 return rc; 2029} 2030 2031int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2032{ 2033 /* The GPIO should be swapped if swap register is set and active */ 2034 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2035 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2036 int gpio_shift = gpio_num + 2037 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2038 u32 gpio_mask = (1 << gpio_shift); 2039 u32 gpio_reg; 2040 2041 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2042 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2043 return -EINVAL; 2044 } 2045 2046 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2047 /* read GPIO int */ 2048 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2049 2050 switch (mode) { 2051 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2052 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> " 2053 "output low\n", gpio_num, gpio_shift); 2054 /* clear SET and set CLR */ 2055 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2056 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2057 break; 2058 2059 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2060 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> " 2061 "output high\n", gpio_num, gpio_shift); 2062 /* clear CLR and set SET */ 2063 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2064 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2065 break; 2066 2067 default: 2068 break; 2069 } 2070 2071 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2072 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2073 2074 return 0; 2075} 2076 2077static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) 2078{ 2079 u32 spio_mask = (1 << spio_num); 2080 u32 spio_reg; 2081 2082 if ((spio_num < MISC_REGISTERS_SPIO_4) || 2083 (spio_num > MISC_REGISTERS_SPIO_7)) { 2084 BNX2X_ERR("Invalid SPIO %d\n", spio_num); 2085 return -EINVAL; 2086 } 2087 2088 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2089 /* read SPIO and mask except the float bits */ 2090 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); 2091 2092 switch (mode) { 2093 case MISC_REGISTERS_SPIO_OUTPUT_LOW: 2094 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); 2095 /* clear FLOAT and set CLR */ 2096 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2097 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); 2098 break; 2099 2100 case MISC_REGISTERS_SPIO_OUTPUT_HIGH: 2101 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); 2102 /* clear FLOAT and set SET */ 2103 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2104 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); 2105 break; 2106 2107 case MISC_REGISTERS_SPIO_INPUT_HI_Z: 2108 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num); 2109 /* set FLOAT */ 2110 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2111 break; 2112 2113 default: 2114 break; 2115 } 2116 2117 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2118 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2119 2120 return 0; 2121} 2122 2123void bnx2x_calc_fc_adv(struct bnx2x *bp) 2124{ 2125 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2126 switch (bp->link_vars.ieee_fc & 2127 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2128 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 2129 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2130 ADVERTISED_Pause); 2131 break; 2132 2133 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2134 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2135 ADVERTISED_Pause); 2136 break; 2137 2138 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2139 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2140 break; 2141 2142 default: 2143 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2144 ADVERTISED_Pause); 2145 break; 2146 } 2147} 2148 2149u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2150{ 2151 if (!BP_NOMCP(bp)) { 2152 u8 rc; 2153 int cfx_idx = bnx2x_get_link_cfg_idx(bp); 2154 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2155 /* 2156 * Initialize link parameters structure variables 2157 * It is recommended to turn off RX FC for jumbo frames 2158 * for better performance 2159 */ 2160 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2161 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2162 else 2163 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2164 2165 bnx2x_acquire_phy_lock(bp); 2166 2167 if (load_mode == LOAD_DIAG) { 2168 struct link_params *lp = &bp->link_params; 2169 lp->loopback_mode = LOOPBACK_XGXS; 2170 /* do PHY loopback at 10G speed, if possible */ 2171 if (lp->req_line_speed[cfx_idx] < SPEED_10000) { 2172 if (lp->speed_cap_mask[cfx_idx] & 2173 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2174 lp->req_line_speed[cfx_idx] = 2175 SPEED_10000; 2176 else 2177 lp->req_line_speed[cfx_idx] = 2178 SPEED_1000; 2179 } 2180 } 2181 2182 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2183 2184 bnx2x_release_phy_lock(bp); 2185 2186 bnx2x_calc_fc_adv(bp); 2187 2188 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { 2189 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2190 bnx2x_link_report(bp); 2191 } else 2192 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2193 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2194 return rc; 2195 } 2196 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2197 return -EINVAL; 2198} 2199 2200void bnx2x_link_set(struct bnx2x *bp) 2201{ 2202 if (!BP_NOMCP(bp)) { 2203 bnx2x_acquire_phy_lock(bp); 2204 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2205 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2206 bnx2x_release_phy_lock(bp); 2207 2208 bnx2x_calc_fc_adv(bp); 2209 } else 2210 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2211} 2212 2213static void bnx2x__link_reset(struct bnx2x *bp) 2214{ 2215 if (!BP_NOMCP(bp)) { 2216 bnx2x_acquire_phy_lock(bp); 2217 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2218 bnx2x_release_phy_lock(bp); 2219 } else 2220 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2221} 2222 2223u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2224{ 2225 u8 rc = 0; 2226 2227 if (!BP_NOMCP(bp)) { 2228 bnx2x_acquire_phy_lock(bp); 2229 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2230 is_serdes); 2231 bnx2x_release_phy_lock(bp); 2232 } else 2233 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2234 2235 return rc; 2236} 2237 2238static void bnx2x_init_port_minmax(struct bnx2x *bp) 2239{ 2240 u32 r_param = bp->link_vars.line_speed / 8; 2241 u32 fair_periodic_timeout_usec; 2242 u32 t_fair; 2243 2244 memset(&(bp->cmng.rs_vars), 0, 2245 sizeof(struct rate_shaping_vars_per_port)); 2246 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port)); 2247 2248 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ 2249 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4; 2250 2251 /* this is the threshold below which no timer arming will occur 2252 1.25 coefficient is for the threshold to be a little bigger 2253 than the real time, to compensate for timer in-accuracy */ 2254 bp->cmng.rs_vars.rs_threshold = 2255 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; 2256 2257 /* resolution of fairness timer */ 2258 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; 2259 /* for 10G it is 1000usec. for 1G it is 10000usec. */ 2260 t_fair = T_FAIR_COEF / bp->link_vars.line_speed; 2261 2262 /* this is the threshold below which we won't arm the timer anymore */ 2263 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES; 2264 2265 /* we multiply by 1e3/8 to get bytes/msec. 2266 We don't want the credits to pass a credit 2267 of the t_fair*FAIR_MEM (algorithm resolution) */ 2268 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM; 2269 /* since each tick is 4 usec */ 2270 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4; 2271} 2272 2273/* Calculates the sum of vn_min_rates. 2274 It's needed for further normalizing of the min_rates. 2275 Returns: 2276 sum of vn_min_rates. 2277 or 2278 0 - if all the min_rates are 0. 2279 In the later case fainess algorithm should be deactivated. 2280 If not all min_rates are zero then those that are zeroes will be set to 1. 2281 */ 2282static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) 2283{ 2284 int all_zero = 1; 2285 int vn; 2286 2287 bp->vn_weight_sum = 0; 2288 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2289 u32 vn_cfg = bp->mf_config[vn]; 2290 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2291 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2292 2293 /* Skip hidden vns */ 2294 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2295 continue; 2296 2297 /* If min rate is zero - set it to 1 */ 2298 if (!vn_min_rate) 2299 vn_min_rate = DEF_MIN_RATE; 2300 else 2301 all_zero = 0; 2302 2303 bp->vn_weight_sum += vn_min_rate; 2304 } 2305 2306 /* if ETS or all min rates are zeros - disable fairness */ 2307 if (BNX2X_IS_ETS_ENABLED(bp)) { 2308 bp->cmng.flags.cmng_enables &= 2309 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2310 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2311 } else if (all_zero) { 2312 bp->cmng.flags.cmng_enables &= 2313 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2314 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2315 " fairness will be disabled\n"); 2316 } else 2317 bp->cmng.flags.cmng_enables |= 2318 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2319} 2320 2321static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) 2322{ 2323 struct rate_shaping_vars_per_vn m_rs_vn; 2324 struct fairness_vars_per_vn m_fair_vn; 2325 u32 vn_cfg = bp->mf_config[vn]; 2326 int func = func_by_vn(bp, vn); 2327 u16 vn_min_rate, vn_max_rate; 2328 int i; 2329 2330 /* If function is hidden - set min and max to zeroes */ 2331 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 2332 vn_min_rate = 0; 2333 vn_max_rate = 0; 2334 2335 } else { 2336 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2337 2338 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2339 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2340 /* If fairness is enabled (not all min rates are zeroes) and 2341 if current min rate is zero - set it to 1. 2342 This is a requirement of the algorithm. */ 2343 if (bp->vn_weight_sum && (vn_min_rate == 0)) 2344 vn_min_rate = DEF_MIN_RATE; 2345 2346 if (IS_MF_SI(bp)) 2347 /* maxCfg in percents of linkspeed */ 2348 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2349 else 2350 /* maxCfg is absolute in 100Mb units */ 2351 vn_max_rate = maxCfg * 100; 2352 } 2353 2354 DP(NETIF_MSG_IFUP, 2355 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n", 2356 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); 2357 2358 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn)); 2359 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); 2360 2361 /* global vn counter - maximal Mbps for this vn */ 2362 m_rs_vn.vn_counter.rate = vn_max_rate; 2363 2364 /* quota - number of bytes transmitted in this period */ 2365 m_rs_vn.vn_counter.quota = 2366 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8; 2367 2368 if (bp->vn_weight_sum) { 2369 /* credit for each period of the fairness algorithm: 2370 number of bytes in T_FAIR (the vn share the port rate). 2371 vn_weight_sum should not be larger than 10000, thus 2372 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater 2373 than zero */ 2374 m_fair_vn.vn_credit_delta = 2375 max_t(u32, (vn_min_rate * (T_FAIR_COEF / 2376 (8 * bp->vn_weight_sum))), 2377 (bp->cmng.fair_vars.fair_threshold + 2378 MIN_ABOVE_THRESH)); 2379 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n", 2380 m_fair_vn.vn_credit_delta); 2381 } 2382 2383 /* Store it to internal memory */ 2384 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++) 2385 REG_WR(bp, BAR_XSTRORM_INTMEM + 2386 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4, 2387 ((u32 *)(&m_rs_vn))[i]); 2388 2389 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++) 2390 REG_WR(bp, BAR_XSTRORM_INTMEM + 2391 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4, 2392 ((u32 *)(&m_fair_vn))[i]); 2393} 2394 2395static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2396{ 2397 if (CHIP_REV_IS_SLOW(bp)) 2398 return CMNG_FNS_NONE; 2399 if (IS_MF(bp)) 2400 return CMNG_FNS_MINMAX; 2401 2402 return CMNG_FNS_NONE; 2403} 2404 2405void bnx2x_read_mf_cfg(struct bnx2x *bp) 2406{ 2407 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2408 2409 if (BP_NOMCP(bp)) 2410 return; /* what should be the default bvalue in this case */ 2411 2412 /* For 2 port configuration the absolute function number formula 2413 * is: 2414 * abs_func = 2 * vn + BP_PORT + BP_PATH 2415 * 2416 * and there are 4 functions per port 2417 * 2418 * For 4 port configuration it is 2419 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2420 * 2421 * and there are 2 functions per port 2422 */ 2423 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2424 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2425 2426 if (func >= E1H_FUNC_MAX) 2427 break; 2428 2429 bp->mf_config[vn] = 2430 MF_CFG_RD(bp, func_mf_config[func].config); 2431 } 2432} 2433 2434static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2435{ 2436 2437 if (cmng_type == CMNG_FNS_MINMAX) { 2438 int vn; 2439 2440 /* clear cmng_enables */ 2441 bp->cmng.flags.cmng_enables = 0; 2442 2443 /* read mf conf from shmem */ 2444 if (read_cfg) 2445 bnx2x_read_mf_cfg(bp); 2446 2447 /* Init rate shaping and fairness contexts */ 2448 bnx2x_init_port_minmax(bp); 2449 2450 /* vn_weight_sum and enable fairness if not 0 */ 2451 bnx2x_calc_vn_weight_sum(bp); 2452 2453 /* calculate and set min-max rate for each vn */ 2454 if (bp->port.pmf) 2455 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) 2456 bnx2x_init_vn_minmax(bp, vn); 2457 2458 /* always enable rate shaping and fairness */ 2459 bp->cmng.flags.cmng_enables |= 2460 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2461 if (!bp->vn_weight_sum) 2462 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2463 " fairness will be disabled\n"); 2464 return; 2465 } 2466 2467 /* rate shaping and fairness are disabled */ 2468 DP(NETIF_MSG_IFUP, 2469 "rate shaping and fairness are disabled\n"); 2470} 2471 2472/* This function is called upon link interrupt */ 2473static void bnx2x_link_attn(struct bnx2x *bp) 2474{ 2475 /* Make sure that we are synced with the current statistics */ 2476 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2477 2478 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2479 2480 if (bp->link_vars.link_up) { 2481 2482 /* dropless flow control */ 2483 if (!CHIP_IS_E1(bp) && bp->dropless_fc) { 2484 int port = BP_PORT(bp); 2485 u32 pause_enabled = 0; 2486 2487 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2488 pause_enabled = 1; 2489 2490 REG_WR(bp, BAR_USTRORM_INTMEM + 2491 USTORM_ETH_PAUSE_ENABLED_OFFSET(port), 2492 pause_enabled); 2493 } 2494 2495 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2496 struct host_port_stats *pstats; 2497 2498 pstats = bnx2x_sp(bp, port_stats); 2499 /* reset old mac stats */ 2500 memset(&(pstats->mac_stx[0]), 0, 2501 sizeof(struct mac_stx)); 2502 } 2503 if (bp->state == BNX2X_STATE_OPEN) 2504 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2505 } 2506 2507 if (bp->link_vars.link_up && bp->link_vars.line_speed) { 2508 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2509 2510 if (cmng_fns != CMNG_FNS_NONE) { 2511 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2512 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2513 } else 2514 /* rate shaping and fairness are disabled */ 2515 DP(NETIF_MSG_IFUP, 2516 "single function mode without fairness\n"); 2517 } 2518 2519 __bnx2x_link_report(bp); 2520 2521 if (IS_MF(bp)) 2522 bnx2x_link_sync_notify(bp); 2523} 2524 2525void bnx2x__link_status_update(struct bnx2x *bp) 2526{ 2527 if (bp->state != BNX2X_STATE_OPEN) 2528 return; 2529 2530 /* read updated dcb configuration */ 2531 bnx2x_dcbx_pmf_update(bp); 2532 2533 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2534 2535 if (bp->link_vars.link_up) 2536 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2537 else 2538 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2539 2540 /* indicate link status */ 2541 bnx2x_link_report(bp); 2542} 2543 2544static void bnx2x_pmf_update(struct bnx2x *bp) 2545{ 2546 int port = BP_PORT(bp); 2547 u32 val; 2548 2549 bp->port.pmf = 1; 2550 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf); 2551 2552 /* 2553 * We need the mb() to ensure the ordering between the writing to 2554 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2555 */ 2556 smp_mb(); 2557 2558 /* queue a periodic task */ 2559 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2560 2561 bnx2x_dcbx_pmf_update(bp); 2562 2563 /* enable nig attention */ 2564 val = (0xff0f | (1 << (BP_VN(bp) + 4))); 2565 if (bp->common.int_block == INT_BLOCK_HC) { 2566 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 2567 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 2568 } else if (!CHIP_IS_E1x(bp)) { 2569 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 2570 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 2571 } 2572 2573 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 2574} 2575 2576/* end of Link */ 2577 2578/* slow path */ 2579 2580/* 2581 * General service functions 2582 */ 2583 2584/* send the MCP a request, block until there is a reply */ 2585u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 2586{ 2587 int mb_idx = BP_FW_MB_IDX(bp); 2588 u32 seq; 2589 u32 rc = 0; 2590 u32 cnt = 1; 2591 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 2592 2593 mutex_lock(&bp->fw_mb_mutex); 2594 seq = ++bp->fw_seq; 2595 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 2596 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 2597 2598 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 2599 (command | seq), param); 2600 2601 do { 2602 /* let the FW do it's magic ... */ 2603 msleep(delay); 2604 2605 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 2606 2607 /* Give the FW up to 5 second (500*10ms) */ 2608 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2609 2610 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 2611 cnt*delay, rc, seq); 2612 2613 /* is this a reply to our command? */ 2614 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 2615 rc &= FW_MSG_CODE_MASK; 2616 else { 2617 /* FW BUG! */ 2618 BNX2X_ERR("FW failed to respond!\n"); 2619 bnx2x_fw_dump(bp); 2620 rc = 0; 2621 } 2622 mutex_unlock(&bp->fw_mb_mutex); 2623 2624 return rc; 2625} 2626 2627static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp) 2628{ 2629#ifdef BCM_CNIC 2630 /* Statistics are not supported for CNIC Clients at the moment */ 2631 if (IS_FCOE_FP(fp)) 2632 return false; 2633#endif 2634 return true; 2635} 2636 2637void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 2638{ 2639 if (CHIP_IS_E1x(bp)) { 2640 struct tstorm_eth_function_common_config tcfg = {0}; 2641 2642 storm_memset_func_cfg(bp, &tcfg, p->func_id); 2643 } 2644 2645 /* Enable the function in the FW */ 2646 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 2647 storm_memset_func_en(bp, p->func_id, 1); 2648 2649 /* spq */ 2650 if (p->func_flgs & FUNC_FLG_SPQ) { 2651 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 2652 REG_WR(bp, XSEM_REG_FAST_MEMORY + 2653 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 2654 } 2655} 2656 2657/** 2658 * bnx2x_get_tx_only_flags - Return common flags 2659 * 2660 * @bp device handle 2661 * @fp queue handle 2662 * @zero_stats TRUE if statistics zeroing is needed 2663 * 2664 * Return the flags that are common for the Tx-only and not normal connections. 2665 */ 2666static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 2667 struct bnx2x_fastpath *fp, 2668 bool zero_stats) 2669{ 2670 unsigned long flags = 0; 2671 2672 /* PF driver will always initialize the Queue to an ACTIVE state */ 2673 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 2674 2675 /* tx only connections collect statistics (on the same index as the 2676 * parent connection). The statistics are zeroed when the parent 2677 * connection is initialized. 2678 */ 2679 if (stat_counter_valid(bp, fp)) { 2680 __set_bit(BNX2X_Q_FLG_STATS, &flags); 2681 if (zero_stats) 2682 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 2683 } 2684 2685 return flags; 2686} 2687 2688static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 2689 struct bnx2x_fastpath *fp, 2690 bool leading) 2691{ 2692 unsigned long flags = 0; 2693 2694 /* calculate other queue flags */ 2695 if (IS_MF_SD(bp)) 2696 __set_bit(BNX2X_Q_FLG_OV, &flags); 2697 2698 if (IS_FCOE_FP(fp)) 2699 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 2700 2701 if (!fp->disable_tpa) { 2702 __set_bit(BNX2X_Q_FLG_TPA, &flags); 2703 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 2704 } 2705 2706 if (leading) { 2707 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 2708 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 2709 } 2710 2711 /* Always set HW VLAN stripping */ 2712 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 2713 2714 2715 return flags | bnx2x_get_common_flags(bp, fp, true); 2716} 2717 2718static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 2719 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 2720 u8 cos) 2721{ 2722 gen_init->stat_id = bnx2x_stats_id(fp); 2723 gen_init->spcl_id = fp->cl_id; 2724 2725 /* Always use mini-jumbo MTU for FCoE L2 ring */ 2726 if (IS_FCOE_FP(fp)) 2727 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 2728 else 2729 gen_init->mtu = bp->dev->mtu; 2730 2731 gen_init->cos = cos; 2732} 2733 2734static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 2735 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 2736 struct bnx2x_rxq_setup_params *rxq_init) 2737{ 2738 u8 max_sge = 0; 2739 u16 sge_sz = 0; 2740 u16 tpa_agg_size = 0; 2741 2742 if (!fp->disable_tpa) { 2743 pause->sge_th_lo = SGE_TH_LO(bp); 2744 pause->sge_th_hi = SGE_TH_HI(bp); 2745 2746 /* validate SGE ring has enough to cross high threshold */ 2747 WARN_ON(bp->dropless_fc && 2748 pause->sge_th_hi + FW_PREFETCH_CNT > 2749 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); 2750 2751 tpa_agg_size = min_t(u32, 2752 (min_t(u32, 8, MAX_SKB_FRAGS) * 2753 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); 2754 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 2755 SGE_PAGE_SHIFT; 2756 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 2757 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 2758 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, 2759 0xffff); 2760 } 2761 2762 /* pause - not for e1 */ 2763 if (!CHIP_IS_E1(bp)) { 2764 pause->bd_th_lo = BD_TH_LO(bp); 2765 pause->bd_th_hi = BD_TH_HI(bp); 2766 2767 pause->rcq_th_lo = RCQ_TH_LO(bp); 2768 pause->rcq_th_hi = RCQ_TH_HI(bp); 2769 /* 2770 * validate that rings have enough entries to cross 2771 * high thresholds 2772 */ 2773 WARN_ON(bp->dropless_fc && 2774 pause->bd_th_hi + FW_PREFETCH_CNT > 2775 bp->rx_ring_size); 2776 WARN_ON(bp->dropless_fc && 2777 pause->rcq_th_hi + FW_PREFETCH_CNT > 2778 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); 2779 2780 pause->pri_map = 1; 2781 } 2782 2783 /* rxq setup */ 2784 rxq_init->dscr_map = fp->rx_desc_mapping; 2785 rxq_init->sge_map = fp->rx_sge_mapping; 2786 rxq_init->rcq_map = fp->rx_comp_mapping; 2787 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 2788 2789 /* This should be a maximum number of data bytes that may be 2790 * placed on the BD (not including paddings). 2791 */ 2792 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - 2793 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; 2794 2795 rxq_init->cl_qzone_id = fp->cl_qzone_id; 2796 rxq_init->tpa_agg_sz = tpa_agg_size; 2797 rxq_init->sge_buf_sz = sge_sz; 2798 rxq_init->max_sges_pkt = max_sge; 2799 rxq_init->rss_engine_id = BP_FUNC(bp); 2800 2801 /* Maximum number or simultaneous TPA aggregation for this Queue. 2802 * 2803 * For PF Clients it should be the maximum avaliable number. 2804 * VF driver(s) may want to define it to a smaller value. 2805 */ 2806 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); 2807 2808 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 2809 rxq_init->fw_sb_id = fp->fw_sb_id; 2810 2811 if (IS_FCOE_FP(fp)) 2812 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 2813 else 2814 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 2815} 2816 2817static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 2818 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 2819 u8 cos) 2820{ 2821 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping; 2822 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 2823 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 2824 txq_init->fw_sb_id = fp->fw_sb_id; 2825 2826 /* 2827 * set the tss leading client id for TX classfication == 2828 * leading RSS client id 2829 */ 2830 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 2831 2832 if (IS_FCOE_FP(fp)) { 2833 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 2834 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 2835 } 2836} 2837 2838static void bnx2x_pf_init(struct bnx2x *bp) 2839{ 2840 struct bnx2x_func_init_params func_init = {0}; 2841 struct event_ring_data eq_data = { {0} }; 2842 u16 flags; 2843 2844 if (!CHIP_IS_E1x(bp)) { 2845 /* reset IGU PF statistics: MSIX + ATTN */ 2846 /* PF */ 2847 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2848 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2849 (CHIP_MODE_IS_4_PORT(bp) ? 2850 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2851 /* ATTN */ 2852 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2853 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2854 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 2855 (CHIP_MODE_IS_4_PORT(bp) ? 2856 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2857 } 2858 2859 /* function setup flags */ 2860 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 2861 2862 /* This flag is relevant for E1x only. 2863 * E2 doesn't have a TPA configuration in a function level. 2864 */ 2865 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; 2866 2867 func_init.func_flgs = flags; 2868 func_init.pf_id = BP_FUNC(bp); 2869 func_init.func_id = BP_FUNC(bp); 2870 func_init.spq_map = bp->spq_mapping; 2871 func_init.spq_prod = bp->spq_prod_idx; 2872 2873 bnx2x_func_init(bp, &func_init); 2874 2875 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 2876 2877 /* 2878 * Congestion management values depend on the link rate 2879 * There is no active link so initial link rate is set to 10 Gbps. 2880 * When the link comes up The congestion management values are 2881 * re-calculated according to the actual link rate. 2882 */ 2883 bp->link_vars.line_speed = SPEED_10000; 2884 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 2885 2886 /* Only the PMF sets the HW */ 2887 if (bp->port.pmf) 2888 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2889 2890 /* init Event Queue */ 2891 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 2892 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 2893 eq_data.producer = bp->eq_prod; 2894 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 2895 eq_data.sb_id = DEF_SB_ID; 2896 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 2897} 2898 2899 2900static void bnx2x_e1h_disable(struct bnx2x *bp) 2901{ 2902 int port = BP_PORT(bp); 2903 2904 bnx2x_tx_disable(bp); 2905 2906 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 2907} 2908 2909static void bnx2x_e1h_enable(struct bnx2x *bp) 2910{ 2911 int port = BP_PORT(bp); 2912 2913 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 2914 2915 /* Tx queue should be only reenabled */ 2916 netif_tx_wake_all_queues(bp->dev); 2917 2918 /* 2919 * Should not call netif_carrier_on since it will be called if the link 2920 * is up when checking for link state 2921 */ 2922} 2923 2924/* called due to MCP event (on pmf): 2925 * reread new bandwidth configuration 2926 * configure FW 2927 * notify others function about the change 2928 */ 2929static inline void bnx2x_config_mf_bw(struct bnx2x *bp) 2930{ 2931 if (bp->link_vars.link_up) { 2932 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 2933 bnx2x_link_sync_notify(bp); 2934 } 2935 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2936} 2937 2938static inline void bnx2x_set_mf_bw(struct bnx2x *bp) 2939{ 2940 bnx2x_config_mf_bw(bp); 2941 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 2942} 2943 2944static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) 2945{ 2946 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); 2947 2948 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 2949 2950 /* 2951 * This is the only place besides the function initialization 2952 * where the bp->flags can change so it is done without any 2953 * locks 2954 */ 2955 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 2956 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n"); 2957 bp->flags |= MF_FUNC_DIS; 2958 2959 bnx2x_e1h_disable(bp); 2960 } else { 2961 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); 2962 bp->flags &= ~MF_FUNC_DIS; 2963 2964 bnx2x_e1h_enable(bp); 2965 } 2966 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 2967 } 2968 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 2969 bnx2x_config_mf_bw(bp); 2970 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 2971 } 2972 2973 /* Report results to MCP */ 2974 if (dcc_event) 2975 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); 2976 else 2977 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); 2978} 2979 2980/* must be called under the spq lock */ 2981static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 2982{ 2983 struct eth_spe *next_spe = bp->spq_prod_bd; 2984 2985 if (bp->spq_prod_bd == bp->spq_last_bd) { 2986 bp->spq_prod_bd = bp->spq; 2987 bp->spq_prod_idx = 0; 2988 DP(NETIF_MSG_TIMER, "end of spq\n"); 2989 } else { 2990 bp->spq_prod_bd++; 2991 bp->spq_prod_idx++; 2992 } 2993 return next_spe; 2994} 2995 2996/* must be called under the spq lock */ 2997static inline void bnx2x_sp_prod_update(struct bnx2x *bp) 2998{ 2999 int func = BP_FUNC(bp); 3000 3001 /* 3002 * Make sure that BD data is updated before writing the producer: 3003 * BD data is written to the memory, the producer is read from the 3004 * memory, thus we need a full memory barrier to ensure the ordering. 3005 */ 3006 mb(); 3007 3008 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3009 bp->spq_prod_idx); 3010 mmiowb(); 3011} 3012 3013/** 3014 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3015 * 3016 * @cmd: command to check 3017 * @cmd_type: command type 3018 */ 3019static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3020{ 3021 if ((cmd_type == NONE_CONNECTION_TYPE) || 3022 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3023 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3024 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3025 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3026 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3027 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3028 return true; 3029 else 3030 return false; 3031 3032} 3033 3034 3035/** 3036 * bnx2x_sp_post - place a single command on an SP ring 3037 * 3038 * @bp: driver handle 3039 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3040 * @cid: SW CID the command is related to 3041 * @data_hi: command private data address (high 32 bits) 3042 * @data_lo: command private data address (low 32 bits) 3043 * @cmd_type: command type (e.g. NONE, ETH) 3044 * 3045 * SP data is handled as if it's always an address pair, thus data fields are 3046 * not swapped to little endian in upper functions. Instead this function swaps 3047 * data as if it's two u32 fields. 3048 */ 3049int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3050 u32 data_hi, u32 data_lo, int cmd_type) 3051{ 3052 struct eth_spe *spe; 3053 u16 type; 3054 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3055 3056#ifdef BNX2X_STOP_ON_ERROR 3057 if (unlikely(bp->panic)) 3058 return -EIO; 3059#endif 3060 3061 spin_lock_bh(&bp->spq_lock); 3062 3063 if (common) { 3064 if (!atomic_read(&bp->eq_spq_left)) { 3065 BNX2X_ERR("BUG! EQ ring full!\n"); 3066 spin_unlock_bh(&bp->spq_lock); 3067 bnx2x_panic(); 3068 return -EBUSY; 3069 } 3070 } else if (!atomic_read(&bp->cq_spq_left)) { 3071 BNX2X_ERR("BUG! SPQ ring full!\n"); 3072 spin_unlock_bh(&bp->spq_lock); 3073 bnx2x_panic(); 3074 return -EBUSY; 3075 } 3076 3077 spe = bnx2x_sp_get_next(bp); 3078 3079 /* CID needs port number to be encoded int it */ 3080 spe->hdr.conn_and_cmd_data = 3081 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3082 HW_CID(bp, cid)); 3083 3084 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; 3085 3086 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3087 SPE_HDR_FUNCTION_ID); 3088 3089 spe->hdr.type = cpu_to_le16(type); 3090 3091 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3092 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3093 3094 /* 3095 * It's ok if the actual decrement is issued towards the memory 3096 * somewhere between the spin_lock and spin_unlock. Thus no 3097 * more explict memory barrier is needed. 3098 */ 3099 if (common) 3100 atomic_dec(&bp->eq_spq_left); 3101 else 3102 atomic_dec(&bp->cq_spq_left); 3103 3104 3105 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/, 3106 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) " 3107 "type(0x%x) left (CQ, EQ) (%x,%x)\n", 3108 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3109 (u32)(U64_LO(bp->spq_mapping) + 3110 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3111 HW_CID(bp, cid), data_hi, data_lo, type, 3112 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3113 3114 bnx2x_sp_prod_update(bp); 3115 spin_unlock_bh(&bp->spq_lock); 3116 return 0; 3117} 3118 3119/* acquire split MCP access lock register */ 3120static int bnx2x_acquire_alr(struct bnx2x *bp) 3121{ 3122 u32 j, val; 3123 int rc = 0; 3124 3125 might_sleep(); 3126 for (j = 0; j < 1000; j++) { 3127 val = (1UL << 31); 3128 REG_WR(bp, GRCBASE_MCP + 0x9c, val); 3129 val = REG_RD(bp, GRCBASE_MCP + 0x9c); 3130 if (val & (1L << 31)) 3131 break; 3132 3133 msleep(5); 3134 } 3135 if (!(val & (1L << 31))) { 3136 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3137 rc = -EBUSY; 3138 } 3139 3140 return rc; 3141} 3142 3143/* release split MCP access lock register */ 3144static void bnx2x_release_alr(struct bnx2x *bp) 3145{ 3146 REG_WR(bp, GRCBASE_MCP + 0x9c, 0); 3147} 3148 3149#define BNX2X_DEF_SB_ATT_IDX 0x0001 3150#define BNX2X_DEF_SB_IDX 0x0002 3151 3152static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3153{ 3154 struct host_sp_status_block *def_sb = bp->def_status_blk; 3155 u16 rc = 0; 3156 3157 barrier(); /* status block is written to by the chip */ 3158 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3159 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 3160 rc |= BNX2X_DEF_SB_ATT_IDX; 3161 } 3162 3163 if (bp->def_idx != def_sb->sp_sb.running_index) { 3164 bp->def_idx = def_sb->sp_sb.running_index; 3165 rc |= BNX2X_DEF_SB_IDX; 3166 } 3167 3168 /* Do not reorder: indecies reading should complete before handling */ 3169 barrier(); 3170 return rc; 3171} 3172 3173/* 3174 * slow path service functions 3175 */ 3176 3177static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 3178{ 3179 int port = BP_PORT(bp); 3180 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 3181 MISC_REG_AEU_MASK_ATTN_FUNC_0; 3182 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 3183 NIG_REG_MASK_INTERRUPT_PORT0; 3184 u32 aeu_mask; 3185 u32 nig_mask = 0; 3186 u32 reg_addr; 3187 3188 if (bp->attn_state & asserted) 3189 BNX2X_ERR("IGU ERROR\n"); 3190 3191 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3192 aeu_mask = REG_RD(bp, aeu_addr); 3193 3194 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 3195 aeu_mask, asserted); 3196 aeu_mask &= ~(asserted & 0x3ff); 3197 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 3198 3199 REG_WR(bp, aeu_addr, aeu_mask); 3200 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3201 3202 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 3203 bp->attn_state |= asserted; 3204 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 3205 3206 if (asserted & ATTN_HARD_WIRED_MASK) { 3207 if (asserted & ATTN_NIG_FOR_FUNC) { 3208 3209 bnx2x_acquire_phy_lock(bp); 3210 3211 /* save nig interrupt mask */ 3212 nig_mask = REG_RD(bp, nig_int_mask_addr); 3213 3214 /* If nig_mask is not set, no need to call the update 3215 * function. 3216 */ 3217 if (nig_mask) { 3218 REG_WR(bp, nig_int_mask_addr, 0); 3219 3220 bnx2x_link_attn(bp); 3221 } 3222 3223 /* handle unicore attn? */ 3224 } 3225 if (asserted & ATTN_SW_TIMER_4_FUNC) 3226 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 3227 3228 if (asserted & GPIO_2_FUNC) 3229 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 3230 3231 if (asserted & GPIO_3_FUNC) 3232 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 3233 3234 if (asserted & GPIO_4_FUNC) 3235 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 3236 3237 if (port == 0) { 3238 if (asserted & ATTN_GENERAL_ATTN_1) { 3239 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 3240 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 3241 } 3242 if (asserted & ATTN_GENERAL_ATTN_2) { 3243 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 3244 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 3245 } 3246 if (asserted & ATTN_GENERAL_ATTN_3) { 3247 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 3248 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 3249 } 3250 } else { 3251 if (asserted & ATTN_GENERAL_ATTN_4) { 3252 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 3253 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 3254 } 3255 if (asserted & ATTN_GENERAL_ATTN_5) { 3256 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 3257 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 3258 } 3259 if (asserted & ATTN_GENERAL_ATTN_6) { 3260 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 3261 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 3262 } 3263 } 3264 3265 } /* if hardwired */ 3266 3267 if (bp->common.int_block == INT_BLOCK_HC) 3268 reg_addr = (HC_REG_COMMAND_REG + port*32 + 3269 COMMAND_REG_ATTN_BITS_SET); 3270 else 3271 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 3272 3273 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 3274 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 3275 REG_WR(bp, reg_addr, asserted); 3276 3277 /* now set back the mask */ 3278 if (asserted & ATTN_NIG_FOR_FUNC) { 3279 REG_WR(bp, nig_int_mask_addr, nig_mask); 3280 bnx2x_release_phy_lock(bp); 3281 } 3282} 3283 3284static inline void bnx2x_fan_failure(struct bnx2x *bp) 3285{ 3286 int port = BP_PORT(bp); 3287 u32 ext_phy_config; 3288 /* mark the failure */ 3289 ext_phy_config = 3290 SHMEM_RD(bp, 3291 dev_info.port_hw_config[port].external_phy_config); 3292 3293 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 3294 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 3295 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 3296 ext_phy_config); 3297 3298 /* log the failure */ 3299 netdev_err(bp->dev, "Fan Failure on Network Controller has caused" 3300 " the driver to shutdown the card to prevent permanent" 3301 " damage. Please contact OEM Support for assistance\n"); 3302 3303 /* 3304 * Scheudle device reset (unload) 3305 * This is due to some boards consuming sufficient power when driver is 3306 * up to overheat if fan fails. 3307 */ 3308 smp_mb__before_clear_bit(); 3309 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); 3310 smp_mb__after_clear_bit(); 3311 schedule_delayed_work(&bp->sp_rtnl_task, 0); 3312 3313} 3314 3315static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 3316{ 3317 int port = BP_PORT(bp); 3318 int reg_offset; 3319 u32 val; 3320 3321 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 3322 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 3323 3324 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 3325 3326 val = REG_RD(bp, reg_offset); 3327 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 3328 REG_WR(bp, reg_offset, val); 3329 3330 BNX2X_ERR("SPIO5 hw attention\n"); 3331 3332 /* Fan failure attention */ 3333 bnx2x_hw_reset_phy(&bp->link_params); 3334 bnx2x_fan_failure(bp); 3335 } 3336 3337 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 3338 bnx2x_acquire_phy_lock(bp); 3339 bnx2x_handle_module_detect_int(&bp->link_params); 3340 bnx2x_release_phy_lock(bp); 3341 } 3342 3343 if (attn & HW_INTERRUT_ASSERT_SET_0) { 3344 3345 val = REG_RD(bp, reg_offset); 3346 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 3347 REG_WR(bp, reg_offset, val); 3348 3349 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 3350 (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); 3351 bnx2x_panic(); 3352 } 3353} 3354 3355static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 3356{ 3357 u32 val; 3358 3359 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 3360 3361 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 3362 BNX2X_ERR("DB hw attention 0x%x\n", val); 3363 /* DORQ discard attention */ 3364 if (val & 0x2) 3365 BNX2X_ERR("FATAL error from DORQ\n"); 3366 } 3367 3368 if (attn & HW_INTERRUT_ASSERT_SET_1) { 3369 3370 int port = BP_PORT(bp); 3371 int reg_offset; 3372 3373 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 3374 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 3375 3376 val = REG_RD(bp, reg_offset); 3377 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 3378 REG_WR(bp, reg_offset, val); 3379 3380 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 3381 (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); 3382 bnx2x_panic(); 3383 } 3384} 3385 3386static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 3387{ 3388 u32 val; 3389 3390 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 3391 3392 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 3393 BNX2X_ERR("CFC hw attention 0x%x\n", val); 3394 /* CFC error attention */ 3395 if (val & 0x2) 3396 BNX2X_ERR("FATAL error from CFC\n"); 3397 } 3398 3399 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 3400 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 3401 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 3402 /* RQ_USDMDP_FIFO_OVERFLOW */ 3403 if (val & 0x18000) 3404 BNX2X_ERR("FATAL error from PXP\n"); 3405 3406 if (!CHIP_IS_E1x(bp)) { 3407 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 3408 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 3409 } 3410 } 3411 3412 if (attn & HW_INTERRUT_ASSERT_SET_2) { 3413 3414 int port = BP_PORT(bp); 3415 int reg_offset; 3416 3417 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 3418 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 3419 3420 val = REG_RD(bp, reg_offset); 3421 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 3422 REG_WR(bp, reg_offset, val); 3423 3424 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 3425 (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); 3426 bnx2x_panic(); 3427 } 3428} 3429 3430static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 3431{ 3432 u32 val; 3433 3434 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 3435 3436 if (attn & BNX2X_PMF_LINK_ASSERT) { 3437 int func = BP_FUNC(bp); 3438 3439 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 3440 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 3441 func_mf_config[BP_ABS_FUNC(bp)].config); 3442 val = SHMEM_RD(bp, 3443 func_mb[BP_FW_MB_IDX(bp)].drv_status); 3444 if (val & DRV_STATUS_DCC_EVENT_MASK) 3445 bnx2x_dcc_event(bp, 3446 (val & DRV_STATUS_DCC_EVENT_MASK)); 3447 3448 if (val & DRV_STATUS_SET_MF_BW) 3449 bnx2x_set_mf_bw(bp); 3450 3451 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 3452 bnx2x_pmf_update(bp); 3453 3454 if (bp->port.pmf && 3455 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 3456 bp->dcbx_enabled > 0) 3457 /* start dcbx state machine */ 3458 bnx2x_dcbx_set_params(bp, 3459 BNX2X_DCBX_STATE_NEG_RECEIVED); 3460 if (bp->link_vars.periodic_flags & 3461 PERIODIC_FLAGS_LINK_EVENT) { 3462 /* sync with link */ 3463 bnx2x_acquire_phy_lock(bp); 3464 bp->link_vars.periodic_flags &= 3465 ~PERIODIC_FLAGS_LINK_EVENT; 3466 bnx2x_release_phy_lock(bp); 3467 if (IS_MF(bp)) 3468 bnx2x_link_sync_notify(bp); 3469 bnx2x_link_report(bp); 3470 } 3471 /* Always call it here: bnx2x_link_report() will 3472 * prevent the link indication duplication. 3473 */ 3474 bnx2x__link_status_update(bp); 3475 } else if (attn & BNX2X_MC_ASSERT_BITS) { 3476 3477 BNX2X_ERR("MC assert!\n"); 3478 bnx2x_mc_assert(bp); 3479 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 3480 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 3481 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 3482 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 3483 bnx2x_panic(); 3484 3485 } else if (attn & BNX2X_MCP_ASSERT) { 3486 3487 BNX2X_ERR("MCP assert!\n"); 3488 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 3489 bnx2x_fw_dump(bp); 3490 3491 } else 3492 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 3493 } 3494 3495 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 3496 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 3497 if (attn & BNX2X_GRC_TIMEOUT) { 3498 val = CHIP_IS_E1(bp) ? 0 : 3499 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 3500 BNX2X_ERR("GRC time-out 0x%08x\n", val); 3501 } 3502 if (attn & BNX2X_GRC_RSV) { 3503 val = CHIP_IS_E1(bp) ? 0 : 3504 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 3505 BNX2X_ERR("GRC reserved 0x%08x\n", val); 3506 } 3507 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 3508 } 3509} 3510 3511/* 3512 * Bits map: 3513 * 0-7 - Engine0 load counter. 3514 * 8-15 - Engine1 load counter. 3515 * 16 - Engine0 RESET_IN_PROGRESS bit. 3516 * 17 - Engine1 RESET_IN_PROGRESS bit. 3517 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 3518 * on the engine 3519 * 19 - Engine1 ONE_IS_LOADED. 3520 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 3521 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 3522 * just the one belonging to its engine). 3523 * 3524 */ 3525#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 3526 3527#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 3528#define BNX2X_PATH0_LOAD_CNT_SHIFT 0 3529#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 3530#define BNX2X_PATH1_LOAD_CNT_SHIFT 8 3531#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 3532#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 3533#define BNX2X_GLOBAL_RESET_BIT 0x00040000 3534 3535/* 3536 * Set the GLOBAL_RESET bit. 3537 * 3538 * Should be run under rtnl lock 3539 */ 3540void bnx2x_set_reset_global(struct bnx2x *bp) 3541{ 3542 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3543 3544 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 3545 barrier(); 3546 mmiowb(); 3547} 3548 3549/* 3550 * Clear the GLOBAL_RESET bit. 3551 * 3552 * Should be run under rtnl lock 3553 */ 3554static inline void bnx2x_clear_reset_global(struct bnx2x *bp) 3555{ 3556 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3557 3558 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 3559 barrier(); 3560 mmiowb(); 3561} 3562 3563/* 3564 * Checks the GLOBAL_RESET bit. 3565 * 3566 * should be run under rtnl lock 3567 */ 3568static inline bool bnx2x_reset_is_global(struct bnx2x *bp) 3569{ 3570 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3571 3572 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 3573 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 3574} 3575 3576/* 3577 * Clear RESET_IN_PROGRESS bit for the current engine. 3578 * 3579 * Should be run under rtnl lock 3580 */ 3581static inline void bnx2x_set_reset_done(struct bnx2x *bp) 3582{ 3583 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3584 u32 bit = BP_PATH(bp) ? 3585 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3586 3587 /* Clear the bit */ 3588 val &= ~bit; 3589 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3590 barrier(); 3591 mmiowb(); 3592} 3593 3594/* 3595 * Set RESET_IN_PROGRESS for the current engine. 3596 * 3597 * should be run under rtnl lock 3598 */ 3599void bnx2x_set_reset_in_progress(struct bnx2x *bp) 3600{ 3601 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3602 u32 bit = BP_PATH(bp) ? 3603 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3604 3605 /* Set the bit */ 3606 val |= bit; 3607 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3608 barrier(); 3609 mmiowb(); 3610} 3611 3612/* 3613 * Checks the RESET_IN_PROGRESS bit for the given engine. 3614 * should be run under rtnl lock 3615 */ 3616bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 3617{ 3618 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3619 u32 bit = engine ? 3620 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3621 3622 /* return false if bit is set */ 3623 return (val & bit) ? false : true; 3624} 3625 3626/* 3627 * Increment the load counter for the current engine. 3628 * 3629 * should be run under rtnl lock 3630 */ 3631void bnx2x_inc_load_cnt(struct bnx2x *bp) 3632{ 3633 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3634 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3635 BNX2X_PATH0_LOAD_CNT_MASK; 3636 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3637 BNX2X_PATH0_LOAD_CNT_SHIFT; 3638 3639 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3640 3641 /* get the current counter value */ 3642 val1 = (val & mask) >> shift; 3643 3644 /* increment... */ 3645 val1++; 3646 3647 /* clear the old value */ 3648 val &= ~mask; 3649 3650 /* set the new one */ 3651 val |= ((val1 << shift) & mask); 3652 3653 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3654 barrier(); 3655 mmiowb(); 3656} 3657 3658/** 3659 * bnx2x_dec_load_cnt - decrement the load counter 3660 * 3661 * @bp: driver handle 3662 * 3663 * Should be run under rtnl lock. 3664 * Decrements the load counter for the current engine. Returns 3665 * the new counter value. 3666 */ 3667u32 bnx2x_dec_load_cnt(struct bnx2x *bp) 3668{ 3669 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3670 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3671 BNX2X_PATH0_LOAD_CNT_MASK; 3672 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3673 BNX2X_PATH0_LOAD_CNT_SHIFT; 3674 3675 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3676 3677 /* get the current counter value */ 3678 val1 = (val & mask) >> shift; 3679 3680 /* decrement... */ 3681 val1--; 3682 3683 /* clear the old value */ 3684 val &= ~mask; 3685 3686 /* set the new one */ 3687 val |= ((val1 << shift) & mask); 3688 3689 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3690 barrier(); 3691 mmiowb(); 3692 3693 return val1; 3694} 3695 3696/* 3697 * Read the load counter for the current engine. 3698 * 3699 * should be run under rtnl lock 3700 */ 3701static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine) 3702{ 3703 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 3704 BNX2X_PATH0_LOAD_CNT_MASK); 3705 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3706 BNX2X_PATH0_LOAD_CNT_SHIFT); 3707 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3708 3709 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val); 3710 3711 val = (val & mask) >> shift; 3712 3713 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val); 3714 3715 return val; 3716} 3717 3718/* 3719 * Reset the load counter for the current engine. 3720 * 3721 * should be run under rtnl lock 3722 */ 3723static inline void bnx2x_clear_load_cnt(struct bnx2x *bp) 3724{ 3725 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3726 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3727 BNX2X_PATH0_LOAD_CNT_MASK); 3728 3729 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); 3730} 3731 3732static inline void _print_next_block(int idx, const char *blk) 3733{ 3734 pr_cont("%s%s", idx ? ", " : "", blk); 3735} 3736 3737static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, 3738 bool print) 3739{ 3740 int i = 0; 3741 u32 cur_bit = 0; 3742 for (i = 0; sig; i++) { 3743 cur_bit = ((u32)0x1 << i); 3744 if (sig & cur_bit) { 3745 switch (cur_bit) { 3746 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 3747 if (print) 3748 _print_next_block(par_num++, "BRB"); 3749 break; 3750 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 3751 if (print) 3752 _print_next_block(par_num++, "PARSER"); 3753 break; 3754 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 3755 if (print) 3756 _print_next_block(par_num++, "TSDM"); 3757 break; 3758 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 3759 if (print) 3760 _print_next_block(par_num++, 3761 "SEARCHER"); 3762 break; 3763 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 3764 if (print) 3765 _print_next_block(par_num++, "TCM"); 3766 break; 3767 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 3768 if (print) 3769 _print_next_block(par_num++, "TSEMI"); 3770 break; 3771 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 3772 if (print) 3773 _print_next_block(par_num++, "XPB"); 3774 break; 3775 } 3776 3777 /* Clear the bit */ 3778 sig &= ~cur_bit; 3779 } 3780 } 3781 3782 return par_num; 3783} 3784 3785static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, 3786 bool *global, bool print) 3787{ 3788 int i = 0; 3789 u32 cur_bit = 0; 3790 for (i = 0; sig; i++) { 3791 cur_bit = ((u32)0x1 << i); 3792 if (sig & cur_bit) { 3793 switch (cur_bit) { 3794 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 3795 if (print) 3796 _print_next_block(par_num++, "PBF"); 3797 break; 3798 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 3799 if (print) 3800 _print_next_block(par_num++, "QM"); 3801 break; 3802 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 3803 if (print) 3804 _print_next_block(par_num++, "TM"); 3805 break; 3806 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 3807 if (print) 3808 _print_next_block(par_num++, "XSDM"); 3809 break; 3810 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 3811 if (print) 3812 _print_next_block(par_num++, "XCM"); 3813 break; 3814 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 3815 if (print) 3816 _print_next_block(par_num++, "XSEMI"); 3817 break; 3818 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 3819 if (print) 3820 _print_next_block(par_num++, 3821 "DOORBELLQ"); 3822 break; 3823 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 3824 if (print) 3825 _print_next_block(par_num++, "NIG"); 3826 break; 3827 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 3828 if (print) 3829 _print_next_block(par_num++, 3830 "VAUX PCI CORE"); 3831 *global = true; 3832 break; 3833 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 3834 if (print) 3835 _print_next_block(par_num++, "DEBUG"); 3836 break; 3837 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 3838 if (print) 3839 _print_next_block(par_num++, "USDM"); 3840 break; 3841 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 3842 if (print) 3843 _print_next_block(par_num++, "UCM"); 3844 break; 3845 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 3846 if (print) 3847 _print_next_block(par_num++, "USEMI"); 3848 break; 3849 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 3850 if (print) 3851 _print_next_block(par_num++, "UPB"); 3852 break; 3853 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 3854 if (print) 3855 _print_next_block(par_num++, "CSDM"); 3856 break; 3857 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 3858 if (print) 3859 _print_next_block(par_num++, "CCM"); 3860 break; 3861 } 3862 3863 /* Clear the bit */ 3864 sig &= ~cur_bit; 3865 } 3866 } 3867 3868 return par_num; 3869} 3870 3871static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, 3872 bool print) 3873{ 3874 int i = 0; 3875 u32 cur_bit = 0; 3876 for (i = 0; sig; i++) { 3877 cur_bit = ((u32)0x1 << i); 3878 if (sig & cur_bit) { 3879 switch (cur_bit) { 3880 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 3881 if (print) 3882 _print_next_block(par_num++, "CSEMI"); 3883 break; 3884 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 3885 if (print) 3886 _print_next_block(par_num++, "PXP"); 3887 break; 3888 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 3889 if (print) 3890 _print_next_block(par_num++, 3891 "PXPPCICLOCKCLIENT"); 3892 break; 3893 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 3894 if (print) 3895 _print_next_block(par_num++, "CFC"); 3896 break; 3897 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 3898 if (print) 3899 _print_next_block(par_num++, "CDU"); 3900 break; 3901 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 3902 if (print) 3903 _print_next_block(par_num++, "DMAE"); 3904 break; 3905 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 3906 if (print) 3907 _print_next_block(par_num++, "IGU"); 3908 break; 3909 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 3910 if (print) 3911 _print_next_block(par_num++, "MISC"); 3912 break; 3913 } 3914 3915 /* Clear the bit */ 3916 sig &= ~cur_bit; 3917 } 3918 } 3919 3920 return par_num; 3921} 3922 3923static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, 3924 bool *global, bool print) 3925{ 3926 int i = 0; 3927 u32 cur_bit = 0; 3928 for (i = 0; sig; i++) { 3929 cur_bit = ((u32)0x1 << i); 3930 if (sig & cur_bit) { 3931 switch (cur_bit) { 3932 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 3933 if (print) 3934 _print_next_block(par_num++, "MCP ROM"); 3935 *global = true; 3936 break; 3937 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 3938 if (print) 3939 _print_next_block(par_num++, 3940 "MCP UMP RX"); 3941 *global = true; 3942 break; 3943 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 3944 if (print) 3945 _print_next_block(par_num++, 3946 "MCP UMP TX"); 3947 *global = true; 3948 break; 3949 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 3950 if (print) 3951 _print_next_block(par_num++, 3952 "MCP SCPAD"); 3953 *global = true; 3954 break; 3955 } 3956 3957 /* Clear the bit */ 3958 sig &= ~cur_bit; 3959 } 3960 } 3961 3962 return par_num; 3963} 3964 3965static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, 3966 bool print) 3967{ 3968 int i = 0; 3969 u32 cur_bit = 0; 3970 for (i = 0; sig; i++) { 3971 cur_bit = ((u32)0x1 << i); 3972 if (sig & cur_bit) { 3973 switch (cur_bit) { 3974 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 3975 if (print) 3976 _print_next_block(par_num++, "PGLUE_B"); 3977 break; 3978 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 3979 if (print) 3980 _print_next_block(par_num++, "ATC"); 3981 break; 3982 } 3983 3984 /* Clear the bit */ 3985 sig &= ~cur_bit; 3986 } 3987 } 3988 3989 return par_num; 3990} 3991 3992static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 3993 u32 *sig) 3994{ 3995 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 3996 (sig[1] & HW_PRTY_ASSERT_SET_1) || 3997 (sig[2] & HW_PRTY_ASSERT_SET_2) || 3998 (sig[3] & HW_PRTY_ASSERT_SET_3) || 3999 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4000 int par_num = 0; 4001 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: " 4002 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x " 4003 "[4]:0x%08x\n", 4004 sig[0] & HW_PRTY_ASSERT_SET_0, 4005 sig[1] & HW_PRTY_ASSERT_SET_1, 4006 sig[2] & HW_PRTY_ASSERT_SET_2, 4007 sig[3] & HW_PRTY_ASSERT_SET_3, 4008 sig[4] & HW_PRTY_ASSERT_SET_4); 4009 if (print) 4010 netdev_err(bp->dev, 4011 "Parity errors detected in blocks: "); 4012 par_num = bnx2x_check_blocks_with_parity0( 4013 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); 4014 par_num = bnx2x_check_blocks_with_parity1( 4015 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); 4016 par_num = bnx2x_check_blocks_with_parity2( 4017 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); 4018 par_num = bnx2x_check_blocks_with_parity3( 4019 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); 4020 par_num = bnx2x_check_blocks_with_parity4( 4021 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); 4022 4023 if (print) 4024 pr_cont("\n"); 4025 4026 return true; 4027 } else 4028 return false; 4029} 4030 4031/** 4032 * bnx2x_chk_parity_attn - checks for parity attentions. 4033 * 4034 * @bp: driver handle 4035 * @global: true if there was a global attention 4036 * @print: show parity attention in syslog 4037 */ 4038bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 4039{ 4040 struct attn_route attn = { {0} }; 4041 int port = BP_PORT(bp); 4042 4043 attn.sig[0] = REG_RD(bp, 4044 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 4045 port*4); 4046 attn.sig[1] = REG_RD(bp, 4047 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 4048 port*4); 4049 attn.sig[2] = REG_RD(bp, 4050 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 4051 port*4); 4052 attn.sig[3] = REG_RD(bp, 4053 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 4054 port*4); 4055 4056 if (!CHIP_IS_E1x(bp)) 4057 attn.sig[4] = REG_RD(bp, 4058 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 4059 port*4); 4060 4061 return bnx2x_parity_attn(bp, global, print, attn.sig); 4062} 4063 4064 4065static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 4066{ 4067 u32 val; 4068 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 4069 4070 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 4071 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 4072 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 4073 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4074 "ADDRESS_ERROR\n"); 4075 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 4076 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4077 "INCORRECT_RCV_BEHAVIOR\n"); 4078 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 4079 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4080 "WAS_ERROR_ATTN\n"); 4081 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 4082 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4083 "VF_LENGTH_VIOLATION_ATTN\n"); 4084 if (val & 4085 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 4086 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4087 "VF_GRC_SPACE_VIOLATION_ATTN\n"); 4088 if (val & 4089 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 4090 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4091 "VF_MSIX_BAR_VIOLATION_ATTN\n"); 4092 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 4093 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4094 "TCPL_ERROR_ATTN\n"); 4095 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 4096 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4097 "TCPL_IN_TWO_RCBS_ATTN\n"); 4098 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 4099 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4100 "CSSNOOP_FIFO_OVERFLOW\n"); 4101 } 4102 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 4103 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 4104 BNX2X_ERR("ATC hw attention 0x%x\n", val); 4105 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 4106 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 4107 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 4108 BNX2X_ERR("ATC_ATC_INT_STS_REG" 4109 "_ATC_TCPL_TO_NOT_PEND\n"); 4110 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 4111 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4112 "ATC_GPA_MULTIPLE_HITS\n"); 4113 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 4114 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4115 "ATC_RCPL_TO_EMPTY_CNT\n"); 4116 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 4117 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 4118 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 4119 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4120 "ATC_IREQ_LESS_THAN_STU\n"); 4121 } 4122 4123 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4124 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 4125 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 4126 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4127 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 4128 } 4129 4130} 4131 4132static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 4133{ 4134 struct attn_route attn, *group_mask; 4135 int port = BP_PORT(bp); 4136 int index; 4137 u32 reg_addr; 4138 u32 val; 4139 u32 aeu_mask; 4140 bool global = false; 4141 4142 /* need to take HW lock because MCP or other port might also 4143 try to handle this event */ 4144 bnx2x_acquire_alr(bp); 4145 4146 if (bnx2x_chk_parity_attn(bp, &global, true)) { 4147#ifndef BNX2X_STOP_ON_ERROR 4148 bp->recovery_state = BNX2X_RECOVERY_INIT; 4149 schedule_delayed_work(&bp->sp_rtnl_task, 0); 4150 /* Disable HW interrupts */ 4151 bnx2x_int_disable(bp); 4152 /* In case of parity errors don't handle attentions so that 4153 * other function would "see" parity errors. 4154 */ 4155#else 4156 bnx2x_panic(); 4157#endif 4158 bnx2x_release_alr(bp); 4159 return; 4160 } 4161 4162 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 4163 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 4164 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 4165 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 4166 if (!CHIP_IS_E1x(bp)) 4167 attn.sig[4] = 4168 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 4169 else 4170 attn.sig[4] = 0; 4171 4172 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 4173 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 4174 4175 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4176 if (deasserted & (1 << index)) { 4177 group_mask = &bp->attn_group[index]; 4178 4179 DP(NETIF_MSG_HW, "group[%d]: %08x %08x " 4180 "%08x %08x %08x\n", 4181 index, 4182 group_mask->sig[0], group_mask->sig[1], 4183 group_mask->sig[2], group_mask->sig[3], 4184 group_mask->sig[4]); 4185 4186 bnx2x_attn_int_deasserted4(bp, 4187 attn.sig[4] & group_mask->sig[4]); 4188 bnx2x_attn_int_deasserted3(bp, 4189 attn.sig[3] & group_mask->sig[3]); 4190 bnx2x_attn_int_deasserted1(bp, 4191 attn.sig[1] & group_mask->sig[1]); 4192 bnx2x_attn_int_deasserted2(bp, 4193 attn.sig[2] & group_mask->sig[2]); 4194 bnx2x_attn_int_deasserted0(bp, 4195 attn.sig[0] & group_mask->sig[0]); 4196 } 4197 } 4198 4199 bnx2x_release_alr(bp); 4200 4201 if (bp->common.int_block == INT_BLOCK_HC) 4202 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4203 COMMAND_REG_ATTN_BITS_CLR); 4204 else 4205 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 4206 4207 val = ~deasserted; 4208 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 4209 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4210 REG_WR(bp, reg_addr, val); 4211 4212 if (~bp->attn_state & deasserted) 4213 BNX2X_ERR("IGU ERROR\n"); 4214 4215 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4216 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4217 4218 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4219 aeu_mask = REG_RD(bp, reg_addr); 4220 4221 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 4222 aeu_mask, deasserted); 4223 aeu_mask |= (deasserted & 0x3ff); 4224 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4225 4226 REG_WR(bp, reg_addr, aeu_mask); 4227 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4228 4229 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4230 bp->attn_state &= ~deasserted; 4231 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4232} 4233 4234static void bnx2x_attn_int(struct bnx2x *bp) 4235{ 4236 /* read local copy of bits */ 4237 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 4238 attn_bits); 4239 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 4240 attn_bits_ack); 4241 u32 attn_state = bp->attn_state; 4242 4243 /* look for changed bits */ 4244 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 4245 u32 deasserted = ~attn_bits & attn_ack & attn_state; 4246 4247 DP(NETIF_MSG_HW, 4248 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 4249 attn_bits, attn_ack, asserted, deasserted); 4250 4251 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 4252 BNX2X_ERR("BAD attention state\n"); 4253 4254 /* handle bits that were raised */ 4255 if (asserted) 4256 bnx2x_attn_int_asserted(bp, asserted); 4257 4258 if (deasserted) 4259 bnx2x_attn_int_deasserted(bp, deasserted); 4260} 4261 4262void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 4263 u16 index, u8 op, u8 update) 4264{ 4265 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 4266 4267 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 4268 igu_addr); 4269} 4270 4271static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 4272{ 4273 /* No memory barriers */ 4274 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 4275 mmiowb(); /* keep prod updates ordered */ 4276} 4277 4278#ifdef BCM_CNIC 4279static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 4280 union event_ring_elem *elem) 4281{ 4282 u8 err = elem->message.error; 4283 4284 if (!bp->cnic_eth_dev.starting_cid || 4285 (cid < bp->cnic_eth_dev.starting_cid && 4286 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 4287 return 1; 4288 4289 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 4290 4291 if (unlikely(err)) { 4292 4293 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 4294 cid); 4295 bnx2x_panic_dump(bp); 4296 } 4297 bnx2x_cnic_cfc_comp(bp, cid, err); 4298 return 0; 4299} 4300#endif 4301 4302static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 4303{ 4304 struct bnx2x_mcast_ramrod_params rparam; 4305 int rc; 4306 4307 memset(&rparam, 0, sizeof(rparam)); 4308 4309 rparam.mcast_obj = &bp->mcast_obj; 4310 4311 netif_addr_lock_bh(bp->dev); 4312 4313 /* Clear pending state for the last command */ 4314 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 4315 4316 /* If there are pending mcast commands - send them */ 4317 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 4318 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 4319 if (rc < 0) 4320 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 4321 rc); 4322 } 4323 4324 netif_addr_unlock_bh(bp->dev); 4325} 4326 4327static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp, 4328 union event_ring_elem *elem) 4329{ 4330 unsigned long ramrod_flags = 0; 4331 int rc = 0; 4332 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; 4333 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 4334 4335 /* Always push next commands out, don't wait here */ 4336 __set_bit(RAMROD_CONT, &ramrod_flags); 4337 4338 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 4339 case BNX2X_FILTER_MAC_PENDING: 4340#ifdef BCM_CNIC 4341 if (cid == BNX2X_ISCSI_ETH_CID) 4342 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 4343 else 4344#endif 4345 vlan_mac_obj = &bp->fp[cid].mac_obj; 4346 4347 break; 4348 case BNX2X_FILTER_MCAST_PENDING: 4349 /* This is only relevant for 57710 where multicast MACs are 4350 * configured as unicast MACs using the same ramrod. 4351 */ 4352 bnx2x_handle_mcast_eqe(bp); 4353 return; 4354 default: 4355 BNX2X_ERR("Unsupported classification command: %d\n", 4356 elem->message.data.eth_event.echo); 4357 return; 4358 } 4359 4360 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 4361 4362 if (rc < 0) 4363 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 4364 else if (rc > 0) 4365 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 4366 4367} 4368 4369#ifdef BCM_CNIC 4370static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 4371#endif 4372 4373static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 4374{ 4375 netif_addr_lock_bh(bp->dev); 4376 4377 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 4378 4379 /* Send rx_mode command again if was requested */ 4380 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 4381 bnx2x_set_storm_rx_mode(bp); 4382#ifdef BCM_CNIC 4383 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 4384 &bp->sp_state)) 4385 bnx2x_set_iscsi_eth_rx_mode(bp, true); 4386 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 4387 &bp->sp_state)) 4388 bnx2x_set_iscsi_eth_rx_mode(bp, false); 4389#endif 4390 4391 netif_addr_unlock_bh(bp->dev); 4392} 4393 4394static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 4395 struct bnx2x *bp, u32 cid) 4396{ 4397 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 4398#ifdef BCM_CNIC 4399 if (cid == BNX2X_FCOE_ETH_CID) 4400 return &bnx2x_fcoe(bp, q_obj); 4401 else 4402#endif 4403 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj); 4404} 4405 4406static void bnx2x_eq_int(struct bnx2x *bp) 4407{ 4408 u16 hw_cons, sw_cons, sw_prod; 4409 union event_ring_elem *elem; 4410 u32 cid; 4411 u8 opcode; 4412 int spqe_cnt = 0; 4413 struct bnx2x_queue_sp_obj *q_obj; 4414 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 4415 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 4416 4417 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 4418 4419 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 4420 * when we get the the next-page we nned to adjust so the loop 4421 * condition below will be met. The next element is the size of a 4422 * regular element and hence incrementing by 1 4423 */ 4424 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 4425 hw_cons++; 4426 4427 /* This function may never run in parallel with itself for a 4428 * specific bp, thus there is no need in "paired" read memory 4429 * barrier here. 4430 */ 4431 sw_cons = bp->eq_cons; 4432 sw_prod = bp->eq_prod; 4433 4434 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 4435 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 4436 4437 for (; sw_cons != hw_cons; 4438 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 4439 4440 4441 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 4442 4443 cid = SW_CID(elem->message.data.cfc_del_event.cid); 4444 opcode = elem->message.opcode; 4445 4446 4447 /* handle eq element */ 4448 switch (opcode) { 4449 case EVENT_RING_OPCODE_STAT_QUERY: 4450 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n", 4451 bp->stats_comp++); 4452 /* nothing to do with stats comp */ 4453 goto next_spqe; 4454 4455 case EVENT_RING_OPCODE_CFC_DEL: 4456 /* handle according to cid range */ 4457 /* 4458 * we may want to verify here that the bp state is 4459 * HALTING 4460 */ 4461 DP(BNX2X_MSG_SP, 4462 "got delete ramrod for MULTI[%d]\n", cid); 4463#ifdef BCM_CNIC 4464 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 4465 goto next_spqe; 4466#endif 4467 q_obj = bnx2x_cid_to_q_obj(bp, cid); 4468 4469 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 4470 break; 4471 4472 4473 4474 goto next_spqe; 4475 4476 case EVENT_RING_OPCODE_STOP_TRAFFIC: 4477 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n"); 4478 if (f_obj->complete_cmd(bp, f_obj, 4479 BNX2X_F_CMD_TX_STOP)) 4480 break; 4481 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 4482 goto next_spqe; 4483 4484 case EVENT_RING_OPCODE_START_TRAFFIC: 4485 DP(BNX2X_MSG_SP, "got START TRAFFIC\n"); 4486 if (f_obj->complete_cmd(bp, f_obj, 4487 BNX2X_F_CMD_TX_START)) 4488 break; 4489 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 4490 goto next_spqe; 4491 case EVENT_RING_OPCODE_FUNCTION_START: 4492 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n"); 4493 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 4494 break; 4495 4496 goto next_spqe; 4497 4498 case EVENT_RING_OPCODE_FUNCTION_STOP: 4499 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n"); 4500 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 4501 break; 4502 4503 goto next_spqe; 4504 } 4505 4506 switch (opcode | bp->state) { 4507 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4508 BNX2X_STATE_OPEN): 4509 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4510 BNX2X_STATE_OPENING_WAIT4_PORT): 4511 cid = elem->message.data.eth_event.echo & 4512 BNX2X_SWCID_MASK; 4513 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 4514 cid); 4515 rss_raw->clear_pending(rss_raw); 4516 break; 4517 4518 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 4519 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 4520 case (EVENT_RING_OPCODE_SET_MAC | 4521 BNX2X_STATE_CLOSING_WAIT4_HALT): 4522 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4523 BNX2X_STATE_OPEN): 4524 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4525 BNX2X_STATE_DIAG): 4526 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4527 BNX2X_STATE_CLOSING_WAIT4_HALT): 4528 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); 4529 bnx2x_handle_classification_eqe(bp, elem); 4530 break; 4531 4532 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4533 BNX2X_STATE_OPEN): 4534 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4535 BNX2X_STATE_DIAG): 4536 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4537 BNX2X_STATE_CLOSING_WAIT4_HALT): 4538 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 4539 bnx2x_handle_mcast_eqe(bp); 4540 break; 4541 4542 case (EVENT_RING_OPCODE_FILTERS_RULES | 4543 BNX2X_STATE_OPEN): 4544 case (EVENT_RING_OPCODE_FILTERS_RULES | 4545 BNX2X_STATE_DIAG): 4546 case (EVENT_RING_OPCODE_FILTERS_RULES | 4547 BNX2X_STATE_CLOSING_WAIT4_HALT): 4548 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 4549 bnx2x_handle_rx_mode_eqe(bp); 4550 break; 4551 default: 4552 /* unknown event log error and continue */ 4553 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 4554 elem->message.opcode, bp->state); 4555 } 4556next_spqe: 4557 spqe_cnt++; 4558 } /* for */ 4559 4560 smp_mb__before_atomic_inc(); 4561 atomic_add(spqe_cnt, &bp->eq_spq_left); 4562 4563 bp->eq_cons = sw_cons; 4564 bp->eq_prod = sw_prod; 4565 /* Make sure that above mem writes were issued towards the memory */ 4566 smp_wmb(); 4567 4568 /* update producer */ 4569 bnx2x_update_eq_prod(bp, bp->eq_prod); 4570} 4571 4572static void bnx2x_sp_task(struct work_struct *work) 4573{ 4574 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 4575 u16 status; 4576 4577 status = bnx2x_update_dsb_idx(bp); 4578/* if (status == 0) */ 4579/* BNX2X_ERR("spurious slowpath interrupt!\n"); */ 4580 4581 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status); 4582 4583 /* HW attentions */ 4584 if (status & BNX2X_DEF_SB_ATT_IDX) { 4585 bnx2x_attn_int(bp); 4586 status &= ~BNX2X_DEF_SB_ATT_IDX; 4587 } 4588 4589 /* SP events: STAT_QUERY and others */ 4590 if (status & BNX2X_DEF_SB_IDX) { 4591#ifdef BCM_CNIC 4592 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 4593 4594 if ((!NO_FCOE(bp)) && 4595 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 4596 /* 4597 * Prevent local bottom-halves from running as 4598 * we are going to change the local NAPI list. 4599 */ 4600 local_bh_disable(); 4601 napi_schedule(&bnx2x_fcoe(bp, napi)); 4602 local_bh_enable(); 4603 } 4604#endif 4605 /* Handle EQ completions */ 4606 bnx2x_eq_int(bp); 4607 4608 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 4609 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 4610 4611 status &= ~BNX2X_DEF_SB_IDX; 4612 } 4613 4614 if (unlikely(status)) 4615 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 4616 status); 4617 4618 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 4619 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 4620} 4621 4622irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 4623{ 4624 struct net_device *dev = dev_instance; 4625 struct bnx2x *bp = netdev_priv(dev); 4626 4627 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 4628 IGU_INT_DISABLE, 0); 4629 4630#ifdef BNX2X_STOP_ON_ERROR 4631 if (unlikely(bp->panic)) 4632 return IRQ_HANDLED; 4633#endif 4634 4635#ifdef BCM_CNIC 4636 { 4637 struct cnic_ops *c_ops; 4638 4639 rcu_read_lock(); 4640 c_ops = rcu_dereference(bp->cnic_ops); 4641 if (c_ops) 4642 c_ops->cnic_handler(bp->cnic_data, NULL); 4643 rcu_read_unlock(); 4644 } 4645#endif 4646 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 4647 4648 return IRQ_HANDLED; 4649} 4650 4651/* end of slow path */ 4652 4653 4654void bnx2x_drv_pulse(struct bnx2x *bp) 4655{ 4656 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 4657 bp->fw_drv_pulse_wr_seq); 4658} 4659 4660 4661static void bnx2x_timer(unsigned long data) 4662{ 4663 u8 cos; 4664 struct bnx2x *bp = (struct bnx2x *) data; 4665 4666 if (!netif_running(bp->dev)) 4667 return; 4668 4669 if (poll) { 4670 struct bnx2x_fastpath *fp = &bp->fp[0]; 4671 4672 for_each_cos_in_tx_queue(fp, cos) 4673 bnx2x_tx_int(bp, &fp->txdata[cos]); 4674 bnx2x_rx_int(fp, 1000); 4675 } 4676 4677 if (!BP_NOMCP(bp)) { 4678 int mb_idx = BP_FW_MB_IDX(bp); 4679 u32 drv_pulse; 4680 u32 mcp_pulse; 4681 4682 ++bp->fw_drv_pulse_wr_seq; 4683 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 4684 /* TBD - add SYSTEM_TIME */ 4685 drv_pulse = bp->fw_drv_pulse_wr_seq; 4686 bnx2x_drv_pulse(bp); 4687 4688 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 4689 MCP_PULSE_SEQ_MASK); 4690 /* The delta between driver pulse and mcp response 4691 * should be 1 (before mcp response) or 0 (after mcp response) 4692 */ 4693 if ((drv_pulse != mcp_pulse) && 4694 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 4695 /* someone lost a heartbeat... */ 4696 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 4697 drv_pulse, mcp_pulse); 4698 } 4699 } 4700 4701 if (bp->state == BNX2X_STATE_OPEN) 4702 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 4703 4704 mod_timer(&bp->timer, jiffies + bp->current_interval); 4705} 4706 4707/* end of Statistics */ 4708 4709/* nic init */ 4710 4711/* 4712 * nic init service functions 4713 */ 4714 4715static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 4716{ 4717 u32 i; 4718 if (!(len%4) && !(addr%4)) 4719 for (i = 0; i < len; i += 4) 4720 REG_WR(bp, addr + i, fill); 4721 else 4722 for (i = 0; i < len; i++) 4723 REG_WR8(bp, addr + i, fill); 4724 4725} 4726 4727/* helper: writes FP SP data to FW - data_size in dwords */ 4728static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 4729 int fw_sb_id, 4730 u32 *sb_data_p, 4731 u32 data_size) 4732{ 4733 int index; 4734 for (index = 0; index < data_size; index++) 4735 REG_WR(bp, BAR_CSTRORM_INTMEM + 4736 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 4737 sizeof(u32)*index, 4738 *(sb_data_p + index)); 4739} 4740 4741static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 4742{ 4743 u32 *sb_data_p; 4744 u32 data_size = 0; 4745 struct hc_status_block_data_e2 sb_data_e2; 4746 struct hc_status_block_data_e1x sb_data_e1x; 4747 4748 /* disable the function first */ 4749 if (!CHIP_IS_E1x(bp)) { 4750 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 4751 sb_data_e2.common.state = SB_DISABLED; 4752 sb_data_e2.common.p_func.vf_valid = false; 4753 sb_data_p = (u32 *)&sb_data_e2; 4754 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 4755 } else { 4756 memset(&sb_data_e1x, 0, 4757 sizeof(struct hc_status_block_data_e1x)); 4758 sb_data_e1x.common.state = SB_DISABLED; 4759 sb_data_e1x.common.p_func.vf_valid = false; 4760 sb_data_p = (u32 *)&sb_data_e1x; 4761 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 4762 } 4763 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 4764 4765 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4766 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 4767 CSTORM_STATUS_BLOCK_SIZE); 4768 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4769 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 4770 CSTORM_SYNC_BLOCK_SIZE); 4771} 4772 4773/* helper: writes SP SB data to FW */ 4774static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 4775 struct hc_sp_status_block_data *sp_sb_data) 4776{ 4777 int func = BP_FUNC(bp); 4778 int i; 4779 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 4780 REG_WR(bp, BAR_CSTRORM_INTMEM + 4781 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 4782 i*sizeof(u32), 4783 *((u32 *)sp_sb_data + i)); 4784} 4785 4786static inline void bnx2x_zero_sp_sb(struct bnx2x *bp) 4787{ 4788 int func = BP_FUNC(bp); 4789 struct hc_sp_status_block_data sp_sb_data; 4790 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 4791 4792 sp_sb_data.state = SB_DISABLED; 4793 sp_sb_data.p_func.vf_valid = false; 4794 4795 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 4796 4797 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4798 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 4799 CSTORM_SP_STATUS_BLOCK_SIZE); 4800 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4801 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 4802 CSTORM_SP_SYNC_BLOCK_SIZE); 4803 4804} 4805 4806 4807static inline 4808void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 4809 int igu_sb_id, int igu_seg_id) 4810{ 4811 hc_sm->igu_sb_id = igu_sb_id; 4812 hc_sm->igu_seg_id = igu_seg_id; 4813 hc_sm->timer_value = 0xFF; 4814 hc_sm->time_to_expire = 0xFFFFFFFF; 4815} 4816 4817 4818/* allocates state machine ids. */ 4819static inline 4820void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) 4821{ 4822 /* zero out state machine indices */ 4823 /* rx indices */ 4824 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 4825 4826 /* tx indices */ 4827 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 4828 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 4829 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 4830 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 4831 4832 /* map indices */ 4833 /* rx indices */ 4834 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 4835 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4836 4837 /* tx indices */ 4838 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 4839 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4840 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 4841 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4842 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 4843 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4844 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 4845 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4846} 4847 4848static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 4849 u8 vf_valid, int fw_sb_id, int igu_sb_id) 4850{ 4851 int igu_seg_id; 4852 4853 struct hc_status_block_data_e2 sb_data_e2; 4854 struct hc_status_block_data_e1x sb_data_e1x; 4855 struct hc_status_block_sm *hc_sm_p; 4856 int data_size; 4857 u32 *sb_data_p; 4858 4859 if (CHIP_INT_MODE_IS_BC(bp)) 4860 igu_seg_id = HC_SEG_ACCESS_NORM; 4861 else 4862 igu_seg_id = IGU_SEG_ACCESS_NORM; 4863 4864 bnx2x_zero_fp_sb(bp, fw_sb_id); 4865 4866 if (!CHIP_IS_E1x(bp)) { 4867 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 4868 sb_data_e2.common.state = SB_ENABLED; 4869 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 4870 sb_data_e2.common.p_func.vf_id = vfid; 4871 sb_data_e2.common.p_func.vf_valid = vf_valid; 4872 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 4873 sb_data_e2.common.same_igu_sb_1b = true; 4874 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 4875 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 4876 hc_sm_p = sb_data_e2.common.state_machine; 4877 sb_data_p = (u32 *)&sb_data_e2; 4878 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 4879 bnx2x_map_sb_state_machines(sb_data_e2.index_data); 4880 } else { 4881 memset(&sb_data_e1x, 0, 4882 sizeof(struct hc_status_block_data_e1x)); 4883 sb_data_e1x.common.state = SB_ENABLED; 4884 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 4885 sb_data_e1x.common.p_func.vf_id = 0xff; 4886 sb_data_e1x.common.p_func.vf_valid = false; 4887 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 4888 sb_data_e1x.common.same_igu_sb_1b = true; 4889 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 4890 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 4891 hc_sm_p = sb_data_e1x.common.state_machine; 4892 sb_data_p = (u32 *)&sb_data_e1x; 4893 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 4894 bnx2x_map_sb_state_machines(sb_data_e1x.index_data); 4895 } 4896 4897 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 4898 igu_sb_id, igu_seg_id); 4899 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 4900 igu_sb_id, igu_seg_id); 4901 4902 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id); 4903 4904 /* write indecies to HW */ 4905 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 4906} 4907 4908static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 4909 u16 tx_usec, u16 rx_usec) 4910{ 4911 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 4912 false, rx_usec); 4913 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 4914 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 4915 tx_usec); 4916 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 4917 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 4918 tx_usec); 4919 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 4920 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 4921 tx_usec); 4922} 4923 4924static void bnx2x_init_def_sb(struct bnx2x *bp) 4925{ 4926 struct host_sp_status_block *def_sb = bp->def_status_blk; 4927 dma_addr_t mapping = bp->def_status_blk_mapping; 4928 int igu_sp_sb_index; 4929 int igu_seg_id; 4930 int port = BP_PORT(bp); 4931 int func = BP_FUNC(bp); 4932 int reg_offset, reg_offset_en5; 4933 u64 section; 4934 int index; 4935 struct hc_sp_status_block_data sp_sb_data; 4936 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 4937 4938 if (CHIP_INT_MODE_IS_BC(bp)) { 4939 igu_sp_sb_index = DEF_SB_IGU_ID; 4940 igu_seg_id = HC_SEG_ACCESS_DEF; 4941 } else { 4942 igu_sp_sb_index = bp->igu_dsb_id; 4943 igu_seg_id = IGU_SEG_ACCESS_DEF; 4944 } 4945 4946 /* ATTN */ 4947 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 4948 atten_status_block); 4949 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 4950 4951 bp->attn_state = 0; 4952 4953 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 4954 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 4955 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 4956 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); 4957 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4958 int sindex; 4959 /* take care of sig[0]..sig[4] */ 4960 for (sindex = 0; sindex < 4; sindex++) 4961 bp->attn_group[index].sig[sindex] = 4962 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 4963 4964 if (!CHIP_IS_E1x(bp)) 4965 /* 4966 * enable5 is separate from the rest of the registers, 4967 * and therefore the address skip is 4 4968 * and not 16 between the different groups 4969 */ 4970 bp->attn_group[index].sig[4] = REG_RD(bp, 4971 reg_offset_en5 + 0x4*index); 4972 else 4973 bp->attn_group[index].sig[4] = 0; 4974 } 4975 4976 if (bp->common.int_block == INT_BLOCK_HC) { 4977 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 4978 HC_REG_ATTN_MSG0_ADDR_L); 4979 4980 REG_WR(bp, reg_offset, U64_LO(section)); 4981 REG_WR(bp, reg_offset + 4, U64_HI(section)); 4982 } else if (!CHIP_IS_E1x(bp)) { 4983 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 4984 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 4985 } 4986 4987 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 4988 sp_sb); 4989 4990 bnx2x_zero_sp_sb(bp); 4991 4992 sp_sb_data.state = SB_ENABLED; 4993 sp_sb_data.host_sb_addr.lo = U64_LO(section); 4994 sp_sb_data.host_sb_addr.hi = U64_HI(section); 4995 sp_sb_data.igu_sb_id = igu_sp_sb_index; 4996 sp_sb_data.igu_seg_id = igu_seg_id; 4997 sp_sb_data.p_func.pf_id = func; 4998 sp_sb_data.p_func.vnic_id = BP_VN(bp); 4999 sp_sb_data.p_func.vf_id = 0xff; 5000 5001 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5002 5003 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 5004} 5005 5006void bnx2x_update_coalesce(struct bnx2x *bp) 5007{ 5008 int i; 5009 5010 for_each_eth_queue(bp, i) 5011 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 5012 bp->tx_ticks, bp->rx_ticks); 5013} 5014 5015static void bnx2x_init_sp_ring(struct bnx2x *bp) 5016{ 5017 spin_lock_init(&bp->spq_lock); 5018 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 5019 5020 bp->spq_prod_idx = 0; 5021 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 5022 bp->spq_prod_bd = bp->spq; 5023 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 5024} 5025 5026static void bnx2x_init_eq_ring(struct bnx2x *bp) 5027{ 5028 int i; 5029 for (i = 1; i <= NUM_EQ_PAGES; i++) { 5030 union event_ring_elem *elem = 5031 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 5032 5033 elem->next_page.addr.hi = 5034 cpu_to_le32(U64_HI(bp->eq_mapping + 5035 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 5036 elem->next_page.addr.lo = 5037 cpu_to_le32(U64_LO(bp->eq_mapping + 5038 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 5039 } 5040 bp->eq_cons = 0; 5041 bp->eq_prod = NUM_EQ_DESC; 5042 bp->eq_cons_sb = BNX2X_EQ_INDEX; 5043 /* we want a warning message before it gets rought... */ 5044 atomic_set(&bp->eq_spq_left, 5045 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 5046} 5047 5048 5049/* called with netif_addr_lock_bh() */ 5050void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 5051 unsigned long rx_mode_flags, 5052 unsigned long rx_accept_flags, 5053 unsigned long tx_accept_flags, 5054 unsigned long ramrod_flags) 5055{ 5056 struct bnx2x_rx_mode_ramrod_params ramrod_param; 5057 int rc; 5058 5059 memset(&ramrod_param, 0, sizeof(ramrod_param)); 5060 5061 /* Prepare ramrod parameters */ 5062 ramrod_param.cid = 0; 5063 ramrod_param.cl_id = cl_id; 5064 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 5065 ramrod_param.func_id = BP_FUNC(bp); 5066 5067 ramrod_param.pstate = &bp->sp_state; 5068 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 5069 5070 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 5071 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 5072 5073 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5074 5075 ramrod_param.ramrod_flags = ramrod_flags; 5076 ramrod_param.rx_mode_flags = rx_mode_flags; 5077 5078 ramrod_param.rx_accept_flags = rx_accept_flags; 5079 ramrod_param.tx_accept_flags = tx_accept_flags; 5080 5081 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 5082 if (rc < 0) { 5083 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 5084 return; 5085 } 5086} 5087 5088/* called with netif_addr_lock_bh() */ 5089void bnx2x_set_storm_rx_mode(struct bnx2x *bp) 5090{ 5091 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 5092 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 5093 5094#ifdef BCM_CNIC 5095 if (!NO_FCOE(bp)) 5096 5097 /* Configure rx_mode of FCoE Queue */ 5098 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 5099#endif 5100 5101 switch (bp->rx_mode) { 5102 case BNX2X_RX_MODE_NONE: 5103 /* 5104 * 'drop all' supersedes any accept flags that may have been 5105 * passed to the function. 5106 */ 5107 break; 5108 case BNX2X_RX_MODE_NORMAL: 5109 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5110 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); 5111 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5112 5113 /* internal switching mode */ 5114 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5115 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); 5116 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5117 5118 break; 5119 case BNX2X_RX_MODE_ALLMULTI: 5120 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5121 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5122 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5123 5124 /* internal switching mode */ 5125 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5126 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5127 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5128 5129 break; 5130 case BNX2X_RX_MODE_PROMISC: 5131 /* According to deffinition of SI mode, iface in promisc mode 5132 * should receive matched and unmatched (in resolution of port) 5133 * unicast packets. 5134 */ 5135 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); 5136 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5137 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5138 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5139 5140 /* internal switching mode */ 5141 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5142 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5143 5144 if (IS_MF_SI(bp)) 5145 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); 5146 else 5147 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5148 5149 break; 5150 default: 5151 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); 5152 return; 5153 } 5154 5155 if (bp->rx_mode != BNX2X_RX_MODE_NONE) { 5156 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); 5157 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); 5158 } 5159 5160 __set_bit(RAMROD_RX, &ramrod_flags); 5161 __set_bit(RAMROD_TX, &ramrod_flags); 5162 5163 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, 5164 tx_accept_flags, ramrod_flags); 5165} 5166 5167static void bnx2x_init_internal_common(struct bnx2x *bp) 5168{ 5169 int i; 5170 5171 if (IS_MF_SI(bp)) 5172 /* 5173 * In switch independent mode, the TSTORM needs to accept 5174 * packets that failed classification, since approximate match 5175 * mac addresses aren't written to NIG LLH 5176 */ 5177 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5178 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); 5179 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ 5180 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5181 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); 5182 5183 /* Zero this manually as its initialization is 5184 currently missing in the initTool */ 5185 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 5186 REG_WR(bp, BAR_USTRORM_INTMEM + 5187 USTORM_AGG_DATA_OFFSET + i * 4, 0); 5188 if (!CHIP_IS_E1x(bp)) { 5189 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 5190 CHIP_INT_MODE_IS_BC(bp) ? 5191 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 5192 } 5193} 5194 5195static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 5196{ 5197 switch (load_code) { 5198 case FW_MSG_CODE_DRV_LOAD_COMMON: 5199 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5200 bnx2x_init_internal_common(bp); 5201 /* no break */ 5202 5203 case FW_MSG_CODE_DRV_LOAD_PORT: 5204 /* nothing to do */ 5205 /* no break */ 5206 5207 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5208 /* internal memory per function is 5209 initialized inside bnx2x_pf_init */ 5210 break; 5211 5212 default: 5213 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5214 break; 5215 } 5216} 5217 5218static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 5219{ 5220 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; 5221} 5222 5223static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 5224{ 5225 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; 5226} 5227 5228static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 5229{ 5230 if (CHIP_IS_E1x(fp->bp)) 5231 return BP_L_ID(fp->bp) + fp->index; 5232 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 5233 return bnx2x_fp_igu_sb_id(fp); 5234} 5235 5236static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 5237{ 5238 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 5239 u8 cos; 5240 unsigned long q_type = 0; 5241 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 5242 fp->rx_queue = fp_idx; 5243 fp->cid = fp_idx; 5244 fp->cl_id = bnx2x_fp_cl_id(fp); 5245 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 5246 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 5247 /* qZone id equals to FW (per path) client id */ 5248 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 5249 5250 /* init shortcut */ 5251 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 5252 /* Setup SB indicies */ 5253 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 5254 5255 /* Configure Queue State object */ 5256 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 5257 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 5258 5259 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 5260 5261 /* init tx data */ 5262 for_each_cos_in_tx_queue(fp, cos) { 5263 bnx2x_init_txdata(bp, &fp->txdata[cos], 5264 CID_COS_TO_TX_ONLY_CID(fp->cid, cos), 5265 FP_COS_TO_TXQ(fp, cos), 5266 BNX2X_TX_SB_INDEX_BASE + cos); 5267 cids[cos] = fp->txdata[cos].cid; 5268 } 5269 5270 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos, 5271 BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 5272 bnx2x_sp_mapping(bp, q_rdata), q_type); 5273 5274 /** 5275 * Configure classification DBs: Always enable Tx switching 5276 */ 5277 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 5278 5279 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) " 5280 "cl_id %d fw_sb %d igu_sb %d\n", 5281 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 5282 fp->igu_sb_id); 5283 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 5284 fp->fw_sb_id, fp->igu_sb_id); 5285 5286 bnx2x_update_fpsb_idx(fp); 5287} 5288 5289void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) 5290{ 5291 int i; 5292 5293 for_each_eth_queue(bp, i) 5294 bnx2x_init_eth_fp(bp, i); 5295#ifdef BCM_CNIC 5296 if (!NO_FCOE(bp)) 5297 bnx2x_init_fcoe_fp(bp); 5298 5299 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 5300 BNX2X_VF_ID_INVALID, false, 5301 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 5302 5303#endif 5304 5305 /* Initialize MOD_ABS interrupts */ 5306 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 5307 bp->common.shmem_base, bp->common.shmem2_base, 5308 BP_PORT(bp)); 5309 /* ensure status block indices were read */ 5310 rmb(); 5311 5312 bnx2x_init_def_sb(bp); 5313 bnx2x_update_dsb_idx(bp); 5314 bnx2x_init_rx_rings(bp); 5315 bnx2x_init_tx_rings(bp); 5316 bnx2x_init_sp_ring(bp); 5317 bnx2x_init_eq_ring(bp); 5318 bnx2x_init_internal(bp, load_code); 5319 bnx2x_pf_init(bp); 5320 bnx2x_stats_init(bp); 5321 5322 /* flush all before enabling interrupts */ 5323 mb(); 5324 mmiowb(); 5325 5326 bnx2x_int_enable(bp); 5327 5328 /* Check for SPIO5 */ 5329 bnx2x_attn_int_deasserted0(bp, 5330 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 5331 AEU_INPUTS_ATTN_BITS_SPIO5); 5332} 5333 5334/* end of nic init */ 5335 5336/* 5337 * gzip service functions 5338 */ 5339 5340static int bnx2x_gunzip_init(struct bnx2x *bp) 5341{ 5342 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 5343 &bp->gunzip_mapping, GFP_KERNEL); 5344 if (bp->gunzip_buf == NULL) 5345 goto gunzip_nomem1; 5346 5347 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 5348 if (bp->strm == NULL) 5349 goto gunzip_nomem2; 5350 5351 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 5352 if (bp->strm->workspace == NULL) 5353 goto gunzip_nomem3; 5354 5355 return 0; 5356 5357gunzip_nomem3: 5358 kfree(bp->strm); 5359 bp->strm = NULL; 5360 5361gunzip_nomem2: 5362 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5363 bp->gunzip_mapping); 5364 bp->gunzip_buf = NULL; 5365 5366gunzip_nomem1: 5367 netdev_err(bp->dev, "Cannot allocate firmware buffer for" 5368 " un-compression\n"); 5369 return -ENOMEM; 5370} 5371 5372static void bnx2x_gunzip_end(struct bnx2x *bp) 5373{ 5374 if (bp->strm) { 5375 vfree(bp->strm->workspace); 5376 kfree(bp->strm); 5377 bp->strm = NULL; 5378 } 5379 5380 if (bp->gunzip_buf) { 5381 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5382 bp->gunzip_mapping); 5383 bp->gunzip_buf = NULL; 5384 } 5385} 5386 5387static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 5388{ 5389 int n, rc; 5390 5391 /* check gzip header */ 5392 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 5393 BNX2X_ERR("Bad gzip header\n"); 5394 return -EINVAL; 5395 } 5396 5397 n = 10; 5398 5399#define FNAME 0x8 5400 5401 if (zbuf[3] & FNAME) 5402 while ((zbuf[n++] != 0) && (n < len)); 5403 5404 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 5405 bp->strm->avail_in = len - n; 5406 bp->strm->next_out = bp->gunzip_buf; 5407 bp->strm->avail_out = FW_BUF_SIZE; 5408 5409 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 5410 if (rc != Z_OK) 5411 return rc; 5412 5413 rc = zlib_inflate(bp->strm, Z_FINISH); 5414 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 5415 netdev_err(bp->dev, "Firmware decompression error: %s\n", 5416 bp->strm->msg); 5417 5418 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 5419 if (bp->gunzip_outlen & 0x3) 5420 netdev_err(bp->dev, "Firmware decompression error:" 5421 " gunzip_outlen (%d) not aligned\n", 5422 bp->gunzip_outlen); 5423 bp->gunzip_outlen >>= 2; 5424 5425 zlib_inflateEnd(bp->strm); 5426 5427 if (rc == Z_STREAM_END) 5428 return 0; 5429 5430 return rc; 5431} 5432 5433/* nic load/unload */ 5434 5435/* 5436 * General service functions 5437 */ 5438 5439/* send a NIG loopback debug packet */ 5440static void bnx2x_lb_pckt(struct bnx2x *bp) 5441{ 5442 u32 wb_write[3]; 5443 5444 /* Ethernet source and destination addresses */ 5445 wb_write[0] = 0x55555555; 5446 wb_write[1] = 0x55555555; 5447 wb_write[2] = 0x20; /* SOP */ 5448 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5449 5450 /* NON-IP protocol */ 5451 wb_write[0] = 0x09000000; 5452 wb_write[1] = 0x55555555; 5453 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 5454 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5455} 5456 5457/* some of the internal memories 5458 * are not directly readable from the driver 5459 * to test them we send debug packets 5460 */ 5461static int bnx2x_int_mem_test(struct bnx2x *bp) 5462{ 5463 int factor; 5464 int count, i; 5465 u32 val = 0; 5466 5467 if (CHIP_REV_IS_FPGA(bp)) 5468 factor = 120; 5469 else if (CHIP_REV_IS_EMUL(bp)) 5470 factor = 200; 5471 else 5472 factor = 1; 5473 5474 /* Disable inputs of parser neighbor blocks */ 5475 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5476 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5477 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5478 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5479 5480 /* Write 0 to parser credits for CFC search request */ 5481 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5482 5483 /* send Ethernet packet */ 5484 bnx2x_lb_pckt(bp); 5485 5486 /* TODO do i reset NIG statistic? */ 5487 /* Wait until NIG register shows 1 packet of size 0x10 */ 5488 count = 1000 * factor; 5489 while (count) { 5490 5491 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5492 val = *bnx2x_sp(bp, wb_data[0]); 5493 if (val == 0x10) 5494 break; 5495 5496 msleep(10); 5497 count--; 5498 } 5499 if (val != 0x10) { 5500 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5501 return -1; 5502 } 5503 5504 /* Wait until PRS register shows 1 packet */ 5505 count = 1000 * factor; 5506 while (count) { 5507 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5508 if (val == 1) 5509 break; 5510 5511 msleep(10); 5512 count--; 5513 } 5514 if (val != 0x1) { 5515 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5516 return -2; 5517 } 5518 5519 /* Reset and init BRB, PRS */ 5520 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5521 msleep(50); 5522 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5523 msleep(50); 5524 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5525 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5526 5527 DP(NETIF_MSG_HW, "part2\n"); 5528 5529 /* Disable inputs of parser neighbor blocks */ 5530 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5531 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5532 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5533 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5534 5535 /* Write 0 to parser credits for CFC search request */ 5536 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5537 5538 /* send 10 Ethernet packets */ 5539 for (i = 0; i < 10; i++) 5540 bnx2x_lb_pckt(bp); 5541 5542 /* Wait until NIG register shows 10 + 1 5543 packets of size 11*0x10 = 0xb0 */ 5544 count = 1000 * factor; 5545 while (count) { 5546 5547 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5548 val = *bnx2x_sp(bp, wb_data[0]); 5549 if (val == 0xb0) 5550 break; 5551 5552 msleep(10); 5553 count--; 5554 } 5555 if (val != 0xb0) { 5556 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5557 return -3; 5558 } 5559 5560 /* Wait until PRS register shows 2 packets */ 5561 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5562 if (val != 2) 5563 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5564 5565 /* Write 1 to parser credits for CFC search request */ 5566 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 5567 5568 /* Wait until PRS register shows 3 packets */ 5569 msleep(10 * factor); 5570 /* Wait until NIG register shows 1 packet of size 0x10 */ 5571 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5572 if (val != 3) 5573 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5574 5575 /* clear NIG EOP FIFO */ 5576 for (i = 0; i < 11; i++) 5577 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 5578 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 5579 if (val != 1) { 5580 BNX2X_ERR("clear of NIG failed\n"); 5581 return -4; 5582 } 5583 5584 /* Reset and init BRB, PRS, NIG */ 5585 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5586 msleep(50); 5587 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5588 msleep(50); 5589 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5590 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5591#ifndef BCM_CNIC 5592 /* set NIC mode */ 5593 REG_WR(bp, PRS_REG_NIC_MODE, 1); 5594#endif 5595 5596 /* Enable inputs of parser neighbor blocks */ 5597 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 5598 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 5599 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 5600 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 5601 5602 DP(NETIF_MSG_HW, "done\n"); 5603 5604 return 0; /* OK */ 5605} 5606 5607static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 5608{ 5609 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 5610 if (!CHIP_IS_E1x(bp)) 5611 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 5612 else 5613 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 5614 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 5615 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 5616 /* 5617 * mask read length error interrupts in brb for parser 5618 * (parsing unit and 'checksum and crc' unit) 5619 * these errors are legal (PU reads fixed length and CAC can cause 5620 * read length error on truncated packets) 5621 */ 5622 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 5623 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 5624 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 5625 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 5626 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 5627 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 5628/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 5629/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 5630 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 5631 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 5632 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 5633/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 5634/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 5635 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 5636 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 5637 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 5638 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 5639/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 5640/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 5641 5642 if (CHIP_REV_IS_FPGA(bp)) 5643 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); 5644 else if (!CHIP_IS_E1x(bp)) 5645 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 5646 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF 5647 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT 5648 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN 5649 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED 5650 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); 5651 else 5652 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); 5653 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 5654 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 5655 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 5656/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 5657 5658 if (!CHIP_IS_E1x(bp)) 5659 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 5660 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 5661 5662 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 5663 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 5664/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 5665 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 5666} 5667 5668static void bnx2x_reset_common(struct bnx2x *bp) 5669{ 5670 u32 val = 0x1400; 5671 5672 /* reset_common */ 5673 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 5674 0xd3ffff7f); 5675 5676 if (CHIP_IS_E3(bp)) { 5677 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 5678 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 5679 } 5680 5681 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); 5682} 5683 5684static void bnx2x_setup_dmae(struct bnx2x *bp) 5685{ 5686 bp->dmae_ready = 0; 5687 spin_lock_init(&bp->dmae_lock); 5688} 5689 5690static void bnx2x_init_pxp(struct bnx2x *bp) 5691{ 5692 u16 devctl; 5693 int r_order, w_order; 5694 5695 pci_read_config_word(bp->pdev, 5696 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); 5697 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); 5698 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 5699 if (bp->mrrs == -1) 5700 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); 5701 else { 5702 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); 5703 r_order = bp->mrrs; 5704 } 5705 5706 bnx2x_init_pxp_arb(bp, r_order, w_order); 5707} 5708 5709static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 5710{ 5711 int is_required; 5712 u32 val; 5713 int port; 5714 5715 if (BP_NOMCP(bp)) 5716 return; 5717 5718 is_required = 0; 5719 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 5720 SHARED_HW_CFG_FAN_FAILURE_MASK; 5721 5722 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) 5723 is_required = 1; 5724 5725 /* 5726 * The fan failure mechanism is usually related to the PHY type since 5727 * the power consumption of the board is affected by the PHY. Currently, 5728 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 5729 */ 5730 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 5731 for (port = PORT_0; port < PORT_MAX; port++) { 5732 is_required |= 5733 bnx2x_fan_failure_det_req( 5734 bp, 5735 bp->common.shmem_base, 5736 bp->common.shmem2_base, 5737 port); 5738 } 5739 5740 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 5741 5742 if (is_required == 0) 5743 return; 5744 5745 /* Fan failure is indicated by SPIO 5 */ 5746 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, 5747 MISC_REGISTERS_SPIO_INPUT_HI_Z); 5748 5749 /* set to active low mode */ 5750 val = REG_RD(bp, MISC_REG_SPIO_INT); 5751 val |= ((1 << MISC_REGISTERS_SPIO_5) << 5752 MISC_REGISTERS_SPIO_INT_OLD_SET_POS); 5753 REG_WR(bp, MISC_REG_SPIO_INT, val); 5754 5755 /* enable interrupt to signal the IGU */ 5756 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 5757 val |= (1 << MISC_REGISTERS_SPIO_5); 5758 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 5759} 5760 5761static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) 5762{ 5763 u32 offset = 0; 5764 5765 if (CHIP_IS_E1(bp)) 5766 return; 5767 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) 5768 return; 5769 5770 switch (BP_ABS_FUNC(bp)) { 5771 case 0: 5772 offset = PXP2_REG_PGL_PRETEND_FUNC_F0; 5773 break; 5774 case 1: 5775 offset = PXP2_REG_PGL_PRETEND_FUNC_F1; 5776 break; 5777 case 2: 5778 offset = PXP2_REG_PGL_PRETEND_FUNC_F2; 5779 break; 5780 case 3: 5781 offset = PXP2_REG_PGL_PRETEND_FUNC_F3; 5782 break; 5783 case 4: 5784 offset = PXP2_REG_PGL_PRETEND_FUNC_F4; 5785 break; 5786 case 5: 5787 offset = PXP2_REG_PGL_PRETEND_FUNC_F5; 5788 break; 5789 case 6: 5790 offset = PXP2_REG_PGL_PRETEND_FUNC_F6; 5791 break; 5792 case 7: 5793 offset = PXP2_REG_PGL_PRETEND_FUNC_F7; 5794 break; 5795 default: 5796 return; 5797 } 5798 5799 REG_WR(bp, offset, pretend_func_num); 5800 REG_RD(bp, offset); 5801 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); 5802} 5803 5804void bnx2x_pf_disable(struct bnx2x *bp) 5805{ 5806 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 5807 val &= ~IGU_PF_CONF_FUNC_EN; 5808 5809 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 5810 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 5811 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); 5812} 5813 5814static inline void bnx2x__common_init_phy(struct bnx2x *bp) 5815{ 5816 u32 shmem_base[2], shmem2_base[2]; 5817 shmem_base[0] = bp->common.shmem_base; 5818 shmem2_base[0] = bp->common.shmem2_base; 5819 if (!CHIP_IS_E1x(bp)) { 5820 shmem_base[1] = 5821 SHMEM2_RD(bp, other_shmem_base_addr); 5822 shmem2_base[1] = 5823 SHMEM2_RD(bp, other_shmem2_base_addr); 5824 } 5825 bnx2x_acquire_phy_lock(bp); 5826 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, 5827 bp->common.chip_id); 5828 bnx2x_release_phy_lock(bp); 5829} 5830 5831/** 5832 * bnx2x_init_hw_common - initialize the HW at the COMMON phase. 5833 * 5834 * @bp: driver handle 5835 */ 5836static int bnx2x_init_hw_common(struct bnx2x *bp) 5837{ 5838 u32 val; 5839 5840 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp)); 5841 5842 /* 5843 * take the UNDI lock to protect undi_unload flow from accessing 5844 * registers while we're resetting the chip 5845 */ 5846 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 5847 5848 bnx2x_reset_common(bp); 5849 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 5850 5851 val = 0xfffc; 5852 if (CHIP_IS_E3(bp)) { 5853 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 5854 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 5855 } 5856 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 5857 5858 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 5859 5860 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 5861 5862 if (!CHIP_IS_E1x(bp)) { 5863 u8 abs_func_id; 5864 5865 /** 5866 * 4-port mode or 2-port mode we need to turn of master-enable 5867 * for everyone, after that, turn it back on for self. 5868 * so, we disregard multi-function or not, and always disable 5869 * for all functions on the given path, this means 0,2,4,6 for 5870 * path 0 and 1,3,5,7 for path 1 5871 */ 5872 for (abs_func_id = BP_PATH(bp); 5873 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { 5874 if (abs_func_id == BP_ABS_FUNC(bp)) { 5875 REG_WR(bp, 5876 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 5877 1); 5878 continue; 5879 } 5880 5881 bnx2x_pretend_func(bp, abs_func_id); 5882 /* clear pf enable */ 5883 bnx2x_pf_disable(bp); 5884 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 5885 } 5886 } 5887 5888 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); 5889 if (CHIP_IS_E1(bp)) { 5890 /* enable HW interrupt from PXP on USDM overflow 5891 bit 16 on INT_MASK_0 */ 5892 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 5893 } 5894 5895 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); 5896 bnx2x_init_pxp(bp); 5897 5898#ifdef __BIG_ENDIAN 5899 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); 5900 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); 5901 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 5902 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 5903 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 5904 /* make sure this value is 0 */ 5905 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); 5906 5907/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ 5908 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); 5909 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); 5910 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); 5911 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 5912#endif 5913 5914 bnx2x_ilt_init_page_size(bp, INITOP_SET); 5915 5916 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 5917 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 5918 5919 /* let the HW do it's magic ... */ 5920 msleep(100); 5921 /* finish PXP init */ 5922 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); 5923 if (val != 1) { 5924 BNX2X_ERR("PXP2 CFG failed\n"); 5925 return -EBUSY; 5926 } 5927 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); 5928 if (val != 1) { 5929 BNX2X_ERR("PXP2 RD_INIT failed\n"); 5930 return -EBUSY; 5931 } 5932 5933 /* Timers bug workaround E2 only. We need to set the entire ILT to 5934 * have entries with value "0" and valid bit on. 5935 * This needs to be done by the first PF that is loaded in a path 5936 * (i.e. common phase) 5937 */ 5938 if (!CHIP_IS_E1x(bp)) { 5939/* In E2 there is a bug in the timers block that can cause function 6 / 7 5940 * (i.e. vnic3) to start even if it is marked as "scan-off". 5941 * This occurs when a different function (func2,3) is being marked 5942 * as "scan-off". Real-life scenario for example: if a driver is being 5943 * load-unloaded while func6,7 are down. This will cause the timer to access 5944 * the ilt, translate to a logical address and send a request to read/write. 5945 * Since the ilt for the function that is down is not valid, this will cause 5946 * a translation error which is unrecoverable. 5947 * The Workaround is intended to make sure that when this happens nothing fatal 5948 * will occur. The workaround: 5949 * 1. First PF driver which loads on a path will: 5950 * a. After taking the chip out of reset, by using pretend, 5951 * it will write "0" to the following registers of 5952 * the other vnics. 5953 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 5954 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 5955 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 5956 * And for itself it will write '1' to 5957 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 5958 * dmae-operations (writing to pram for example.) 5959 * note: can be done for only function 6,7 but cleaner this 5960 * way. 5961 * b. Write zero+valid to the entire ILT. 5962 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 5963 * VNIC3 (of that port). The range allocated will be the 5964 * entire ILT. This is needed to prevent ILT range error. 5965 * 2. Any PF driver load flow: 5966 * a. ILT update with the physical addresses of the allocated 5967 * logical pages. 5968 * b. Wait 20msec. - note that this timeout is needed to make 5969 * sure there are no requests in one of the PXP internal 5970 * queues with "old" ILT addresses. 5971 * c. PF enable in the PGLC. 5972 * d. Clear the was_error of the PF in the PGLC. (could have 5973 * occured while driver was down) 5974 * e. PF enable in the CFC (WEAK + STRONG) 5975 * f. Timers scan enable 5976 * 3. PF driver unload flow: 5977 * a. Clear the Timers scan_en. 5978 * b. Polling for scan_on=0 for that PF. 5979 * c. Clear the PF enable bit in the PXP. 5980 * d. Clear the PF enable in the CFC (WEAK + STRONG) 5981 * e. Write zero+valid to all ILT entries (The valid bit must 5982 * stay set) 5983 * f. If this is VNIC 3 of a port then also init 5984 * first_timers_ilt_entry to zero and last_timers_ilt_entry 5985 * to the last enrty in the ILT. 5986 * 5987 * Notes: 5988 * Currently the PF error in the PGLC is non recoverable. 5989 * In the future the there will be a recovery routine for this error. 5990 * Currently attention is masked. 5991 * Having an MCP lock on the load/unload process does not guarantee that 5992 * there is no Timer disable during Func6/7 enable. This is because the 5993 * Timers scan is currently being cleared by the MCP on FLR. 5994 * Step 2.d can be done only for PF6/7 and the driver can also check if 5995 * there is error before clearing it. But the flow above is simpler and 5996 * more general. 5997 * All ILT entries are written by zero+valid and not just PF6/7 5998 * ILT entries since in the future the ILT entries allocation for 5999 * PF-s might be dynamic. 6000 */ 6001 struct ilt_client_info ilt_cli; 6002 struct bnx2x_ilt ilt; 6003 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 6004 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); 6005 6006 /* initialize dummy TM client */ 6007 ilt_cli.start = 0; 6008 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 6009 ilt_cli.client_num = ILT_CLIENT_TM; 6010 6011 /* Step 1: set zeroes to all ilt page entries with valid bit on 6012 * Step 2: set the timers first/last ilt entry to point 6013 * to the entire range to prevent ILT range error for 3rd/4th 6014 * vnic (this code assumes existance of the vnic) 6015 * 6016 * both steps performed by call to bnx2x_ilt_client_init_op() 6017 * with dummy TM client 6018 * 6019 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 6020 * and his brother are split registers 6021 */ 6022 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); 6023 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); 6024 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6025 6026 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); 6027 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); 6028 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 6029 } 6030 6031 6032 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 6033 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 6034 6035 if (!CHIP_IS_E1x(bp)) { 6036 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : 6037 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); 6038 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); 6039 6040 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); 6041 6042 /* let the HW do it's magic ... */ 6043 do { 6044 msleep(200); 6045 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); 6046 } while (factor-- && (val != 1)); 6047 6048 if (val != 1) { 6049 BNX2X_ERR("ATC_INIT failed\n"); 6050 return -EBUSY; 6051 } 6052 } 6053 6054 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); 6055 6056 /* clean the DMAE memory */ 6057 bp->dmae_ready = 1; 6058 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); 6059 6060 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); 6061 6062 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); 6063 6064 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); 6065 6066 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); 6067 6068 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); 6069 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); 6070 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); 6071 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); 6072 6073 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); 6074 6075 6076 /* QM queues pointers table */ 6077 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); 6078 6079 /* soft reset pulse */ 6080 REG_WR(bp, QM_REG_SOFT_RESET, 1); 6081 REG_WR(bp, QM_REG_SOFT_RESET, 0); 6082 6083#ifdef BCM_CNIC 6084 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); 6085#endif 6086 6087 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); 6088 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); 6089 if (!CHIP_REV_IS_SLOW(bp)) 6090 /* enable hw interrupt from doorbell Q */ 6091 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6092 6093 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6094 6095 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6096 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 6097 6098 if (!CHIP_IS_E1(bp)) 6099 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); 6100 6101 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) 6102 /* Bit-map indicating which L2 hdrs may appear 6103 * after the basic Ethernet header 6104 */ 6105 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 6106 bp->path_has_ovlan ? 7 : 6); 6107 6108 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); 6109 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); 6110 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); 6111 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); 6112 6113 if (!CHIP_IS_E1x(bp)) { 6114 /* reset VFC memories */ 6115 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6116 VFC_MEMORIES_RST_REG_CAM_RST | 6117 VFC_MEMORIES_RST_REG_RAM_RST); 6118 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6119 VFC_MEMORIES_RST_REG_CAM_RST | 6120 VFC_MEMORIES_RST_REG_RAM_RST); 6121 6122 msleep(20); 6123 } 6124 6125 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); 6126 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); 6127 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); 6128 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); 6129 6130 /* sync semi rtc */ 6131 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6132 0x80000000); 6133 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 6134 0x80000000); 6135 6136 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); 6137 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); 6138 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); 6139 6140 if (!CHIP_IS_E1x(bp)) 6141 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 6142 bp->path_has_ovlan ? 7 : 6); 6143 6144 REG_WR(bp, SRC_REG_SOFT_RST, 1); 6145 6146 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); 6147 6148#ifdef BCM_CNIC 6149 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 6150 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 6151 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); 6152 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); 6153 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); 6154 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 6155 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); 6156 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 6157 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); 6158 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); 6159#endif 6160 REG_WR(bp, SRC_REG_SOFT_RST, 0); 6161 6162 if (sizeof(union cdu_context) != 1024) 6163 /* we currently assume that a context is 1024 bytes */ 6164 dev_alert(&bp->pdev->dev, "please adjust the size " 6165 "of cdu_context(%ld)\n", 6166 (long)sizeof(union cdu_context)); 6167 6168 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 6169 val = (4 << 24) + (0 << 12) + 1024; 6170 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); 6171 6172 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); 6173 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); 6174 /* enable context validation interrupt from CFC */ 6175 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6176 6177 /* set the thresholds to prevent CFC/CDU race */ 6178 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 6179 6180 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); 6181 6182 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) 6183 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); 6184 6185 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); 6186 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); 6187 6188 /* Reset PCIE errors for debug */ 6189 REG_WR(bp, 0x2814, 0xffffffff); 6190 REG_WR(bp, 0x3820, 0xffffffff); 6191 6192 if (!CHIP_IS_E1x(bp)) { 6193 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 6194 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 6195 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 6196 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 6197 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 6198 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 6199 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 6200 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 6201 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 6202 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 6203 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 6204 } 6205 6206 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); 6207 if (!CHIP_IS_E1(bp)) { 6208 /* in E3 this done in per-port section */ 6209 if (!CHIP_IS_E3(bp)) 6210 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6211 } 6212 if (CHIP_IS_E1H(bp)) 6213 /* not applicable for E2 (and above ...) */ 6214 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); 6215 6216 if (CHIP_REV_IS_SLOW(bp)) 6217 msleep(200); 6218 6219 /* finish CFC init */ 6220 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); 6221 if (val != 1) { 6222 BNX2X_ERR("CFC LL_INIT failed\n"); 6223 return -EBUSY; 6224 } 6225 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); 6226 if (val != 1) { 6227 BNX2X_ERR("CFC AC_INIT failed\n"); 6228 return -EBUSY; 6229 } 6230 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 6231 if (val != 1) { 6232 BNX2X_ERR("CFC CAM_INIT failed\n"); 6233 return -EBUSY; 6234 } 6235 REG_WR(bp, CFC_REG_DEBUG0, 0); 6236 6237 if (CHIP_IS_E1(bp)) { 6238 /* read NIG statistic 6239 to see if this is our first up since powerup */ 6240 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6241 val = *bnx2x_sp(bp, wb_data[0]); 6242 6243 /* do internal memory self test */ 6244 if ((val == 0) && bnx2x_int_mem_test(bp)) { 6245 BNX2X_ERR("internal mem self test failed\n"); 6246 return -EBUSY; 6247 } 6248 } 6249 6250 bnx2x_setup_fan_failure_detection(bp); 6251 6252 /* clear PXP2 attentions */ 6253 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 6254 6255 bnx2x_enable_blocks_attention(bp); 6256 bnx2x_enable_blocks_parity(bp); 6257 6258 if (!BP_NOMCP(bp)) { 6259 if (CHIP_IS_E1x(bp)) 6260 bnx2x__common_init_phy(bp); 6261 } else 6262 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 6263 6264 return 0; 6265} 6266 6267/** 6268 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. 6269 * 6270 * @bp: driver handle 6271 */ 6272static int bnx2x_init_hw_common_chip(struct bnx2x *bp) 6273{ 6274 int rc = bnx2x_init_hw_common(bp); 6275 6276 if (rc) 6277 return rc; 6278 6279 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 6280 if (!BP_NOMCP(bp)) 6281 bnx2x__common_init_phy(bp); 6282 6283 return 0; 6284} 6285 6286static int bnx2x_init_hw_port(struct bnx2x *bp) 6287{ 6288 int port = BP_PORT(bp); 6289 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 6290 u32 low, high; 6291 u32 val; 6292 6293 bnx2x__link_reset(bp); 6294 6295 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port); 6296 6297 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 6298 6299 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6300 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6301 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6302 6303 /* Timers bug workaround: disables the pf_master bit in pglue at 6304 * common phase, we need to enable it here before any dmae access are 6305 * attempted. Therefore we manually added the enable-master to the 6306 * port phase (it also happens in the function phase) 6307 */ 6308 if (!CHIP_IS_E1x(bp)) 6309 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6310 6311 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6312 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6313 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6314 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6315 6316 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6317 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6318 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6319 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6320 6321 /* QM cid (connection) count */ 6322 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); 6323 6324#ifdef BCM_CNIC 6325 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6326 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 6327 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 6328#endif 6329 6330 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6331 6332 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { 6333 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6334 6335 if (IS_MF(bp)) 6336 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 6337 else if (bp->dev->mtu > 4096) { 6338 if (bp->flags & ONE_PORT_FLAG) 6339 low = 160; 6340 else { 6341 val = bp->dev->mtu; 6342 /* (24*1024 + val*4)/256 */ 6343 low = 96 + (val/64) + 6344 ((val % 64) ? 1 : 0); 6345 } 6346 } else 6347 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 6348 high = low + 56; /* 14*1024/256 */ 6349 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 6350 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 6351 } 6352 6353 if (CHIP_MODE_IS_4_PORT(bp)) 6354 REG_WR(bp, (BP_PORT(bp) ? 6355 BRB1_REG_MAC_GUARANTIED_1 : 6356 BRB1_REG_MAC_GUARANTIED_0), 40); 6357 6358 6359 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6360 if (CHIP_IS_E3B0(bp)) 6361 /* Ovlan exists only if we are in multi-function + 6362 * switch-dependent mode, in switch-independent there 6363 * is no ovlan headers 6364 */ 6365 REG_WR(bp, BP_PORT(bp) ? 6366 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 6367 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 6368 (bp->path_has_ovlan ? 7 : 6)); 6369 6370 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6371 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6372 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6373 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6374 6375 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6376 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6377 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6378 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6379 6380 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6381 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6382 6383 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6384 6385 if (CHIP_IS_E1x(bp)) { 6386 /* configure PBF to work without PAUSE mtu 9000 */ 6387 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 6388 6389 /* update threshold */ 6390 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 6391 /* update init credit */ 6392 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 6393 6394 /* probe changes */ 6395 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 6396 udelay(50); 6397 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 6398 } 6399 6400#ifdef BCM_CNIC 6401 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6402#endif 6403 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6404 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6405 6406 if (CHIP_IS_E1(bp)) { 6407 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6408 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6409 } 6410 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6411 6412 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6413 6414 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6415 /* init aeu_mask_attn_func_0/1: 6416 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 6417 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 6418 * bits 4-7 are used for "per vn group attention" */ 6419 val = IS_MF(bp) ? 0xF7 : 0x7; 6420 /* Enable DCBX attention for all but E1 */ 6421 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 6422 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 6423 6424 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6425 6426 if (!CHIP_IS_E1x(bp)) { 6427 /* Bit-map indicating which L2 hdrs may appear after the 6428 * basic Ethernet header 6429 */ 6430 REG_WR(bp, BP_PORT(bp) ? 6431 NIG_REG_P1_HDRS_AFTER_BASIC : 6432 NIG_REG_P0_HDRS_AFTER_BASIC, 6433 IS_MF_SD(bp) ? 7 : 6); 6434 6435 if (CHIP_IS_E3(bp)) 6436 REG_WR(bp, BP_PORT(bp) ? 6437 NIG_REG_LLH1_MF_MODE : 6438 NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6439 } 6440 if (!CHIP_IS_E3(bp)) 6441 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 6442 6443 if (!CHIP_IS_E1(bp)) { 6444 /* 0x2 disable mf_ov, 0x1 enable */ 6445 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 6446 (IS_MF_SD(bp) ? 0x1 : 0x2)); 6447 6448 if (!CHIP_IS_E1x(bp)) { 6449 val = 0; 6450 switch (bp->mf_mode) { 6451 case MULTI_FUNCTION_SD: 6452 val = 1; 6453 break; 6454 case MULTI_FUNCTION_SI: 6455 val = 2; 6456 break; 6457 } 6458 6459 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : 6460 NIG_REG_LLH0_CLS_TYPE), val); 6461 } 6462 { 6463 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 6464 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 6465 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 6466 } 6467 } 6468 6469 6470 /* If SPIO5 is set to generate interrupts, enable it for this port */ 6471 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6472 if (val & (1 << MISC_REGISTERS_SPIO_5)) { 6473 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 6474 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 6475 val = REG_RD(bp, reg_addr); 6476 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 6477 REG_WR(bp, reg_addr, val); 6478 } 6479 6480 return 0; 6481} 6482 6483static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 6484{ 6485 int reg; 6486 6487 if (CHIP_IS_E1(bp)) 6488 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 6489 else 6490 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 6491 6492 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr)); 6493} 6494 6495static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) 6496{ 6497 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); 6498} 6499 6500static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) 6501{ 6502 u32 i, base = FUNC_ILT_BASE(func); 6503 for (i = base; i < base + ILT_PER_FUNC; i++) 6504 bnx2x_ilt_wr(bp, i, 0); 6505} 6506 6507static int bnx2x_init_hw_func(struct bnx2x *bp) 6508{ 6509 int port = BP_PORT(bp); 6510 int func = BP_FUNC(bp); 6511 int init_phase = PHASE_PF0 + func; 6512 struct bnx2x_ilt *ilt = BP_ILT(bp); 6513 u16 cdu_ilt_start; 6514 u32 addr, val; 6515 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 6516 int i, main_mem_width; 6517 6518 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func); 6519 6520 /* FLR cleanup - hmmm */ 6521 if (!CHIP_IS_E1x(bp)) 6522 bnx2x_pf_flr_clnup(bp); 6523 6524 /* set MSI reconfigure capability */ 6525 if (bp->common.int_block == INT_BLOCK_HC) { 6526 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 6527 val = REG_RD(bp, addr); 6528 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 6529 REG_WR(bp, addr, val); 6530 } 6531 6532 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6533 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6534 6535 ilt = BP_ILT(bp); 6536 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 6537 6538 for (i = 0; i < L2_ILT_LINES(bp); i++) { 6539 ilt->lines[cdu_ilt_start + i].page = 6540 bp->context.vcxt + (ILT_PAGE_CIDS * i); 6541 ilt->lines[cdu_ilt_start + i].page_mapping = 6542 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i); 6543 /* cdu ilt pages are allocated manually so there's no need to 6544 set the size */ 6545 } 6546 bnx2x_ilt_init_op(bp, INITOP_SET); 6547 6548#ifdef BCM_CNIC 6549 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); 6550 6551 /* T1 hash bits value determines the T1 number of entries */ 6552 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 6553#endif 6554 6555#ifndef BCM_CNIC 6556 /* set NIC mode */ 6557 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6558#endif /* BCM_CNIC */ 6559 6560 if (!CHIP_IS_E1x(bp)) { 6561 u32 pf_conf = IGU_PF_CONF_FUNC_EN; 6562 6563 /* Turn on a single ISR mode in IGU if driver is going to use 6564 * INT#x or MSI 6565 */ 6566 if (!(bp->flags & USING_MSIX_FLAG)) 6567 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 6568 /* 6569 * Timers workaround bug: function init part. 6570 * Need to wait 20msec after initializing ILT, 6571 * needed to make sure there are no requests in 6572 * one of the PXP internal queues with "old" ILT addresses 6573 */ 6574 msleep(20); 6575 /* 6576 * Master enable - Due to WB DMAE writes performed before this 6577 * register is re-initialized as part of the regular function 6578 * init 6579 */ 6580 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6581 /* Enable the function in IGU */ 6582 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); 6583 } 6584 6585 bp->dmae_ready = 1; 6586 6587 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6588 6589 if (!CHIP_IS_E1x(bp)) 6590 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); 6591 6592 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6593 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6594 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6595 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6596 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6597 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6598 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6599 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6600 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6601 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6602 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6603 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6604 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6605 6606 if (!CHIP_IS_E1x(bp)) 6607 REG_WR(bp, QM_REG_PF_EN, 1); 6608 6609 if (!CHIP_IS_E1x(bp)) { 6610 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6611 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6612 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6613 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6614 } 6615 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6616 6617 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6618 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6619 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6620 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6621 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6622 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6623 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6624 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6625 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6626 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6627 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6628 if (!CHIP_IS_E1x(bp)) 6629 REG_WR(bp, PBF_REG_DISABLE_PF, 0); 6630 6631 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6632 6633 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6634 6635 if (!CHIP_IS_E1x(bp)) 6636 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); 6637 6638 if (IS_MF(bp)) { 6639 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 6640 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); 6641 } 6642 6643 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6644 6645 /* HC init per function */ 6646 if (bp->common.int_block == INT_BLOCK_HC) { 6647 if (CHIP_IS_E1H(bp)) { 6648 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6649 6650 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6651 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6652 } 6653 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6654 6655 } else { 6656 int num_segs, sb_idx, prod_offset; 6657 6658 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6659 6660 if (!CHIP_IS_E1x(bp)) { 6661 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 6662 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 6663 } 6664 6665 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6666 6667 if (!CHIP_IS_E1x(bp)) { 6668 int dsb_idx = 0; 6669 /** 6670 * Producer memory: 6671 * E2 mode: address 0-135 match to the mapping memory; 6672 * 136 - PF0 default prod; 137 - PF1 default prod; 6673 * 138 - PF2 default prod; 139 - PF3 default prod; 6674 * 140 - PF0 attn prod; 141 - PF1 attn prod; 6675 * 142 - PF2 attn prod; 143 - PF3 attn prod; 6676 * 144-147 reserved. 6677 * 6678 * E1.5 mode - In backward compatible mode; 6679 * for non default SB; each even line in the memory 6680 * holds the U producer and each odd line hold 6681 * the C producer. The first 128 producers are for 6682 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 6683 * producers are for the DSB for each PF. 6684 * Each PF has five segments: (the order inside each 6685 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 6686 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 6687 * 144-147 attn prods; 6688 */ 6689 /* non-default-status-blocks */ 6690 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6691 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 6692 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { 6693 prod_offset = (bp->igu_base_sb + sb_idx) * 6694 num_segs; 6695 6696 for (i = 0; i < num_segs; i++) { 6697 addr = IGU_REG_PROD_CONS_MEMORY + 6698 (prod_offset + i) * 4; 6699 REG_WR(bp, addr, 0); 6700 } 6701 /* send consumer update with value 0 */ 6702 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, 6703 USTORM_ID, 0, IGU_INT_NOP, 1); 6704 bnx2x_igu_clear_sb(bp, 6705 bp->igu_base_sb + sb_idx); 6706 } 6707 6708 /* default-status-blocks */ 6709 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6710 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 6711 6712 if (CHIP_MODE_IS_4_PORT(bp)) 6713 dsb_idx = BP_FUNC(bp); 6714 else 6715 dsb_idx = BP_VN(bp); 6716 6717 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 6718 IGU_BC_BASE_DSB_PROD + dsb_idx : 6719 IGU_NORM_BASE_DSB_PROD + dsb_idx); 6720 6721 /* 6722 * igu prods come in chunks of E1HVN_MAX (4) - 6723 * does not matters what is the current chip mode 6724 */ 6725 for (i = 0; i < (num_segs * E1HVN_MAX); 6726 i += E1HVN_MAX) { 6727 addr = IGU_REG_PROD_CONS_MEMORY + 6728 (prod_offset + i)*4; 6729 REG_WR(bp, addr, 0); 6730 } 6731 /* send consumer update with 0 */ 6732 if (CHIP_INT_MODE_IS_BC(bp)) { 6733 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6734 USTORM_ID, 0, IGU_INT_NOP, 1); 6735 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6736 CSTORM_ID, 0, IGU_INT_NOP, 1); 6737 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6738 XSTORM_ID, 0, IGU_INT_NOP, 1); 6739 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6740 TSTORM_ID, 0, IGU_INT_NOP, 1); 6741 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6742 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6743 } else { 6744 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6745 USTORM_ID, 0, IGU_INT_NOP, 1); 6746 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6747 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6748 } 6749 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); 6750 6751 /* !!! these should become driver const once 6752 rf-tool supports split-68 const */ 6753 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 6754 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 6755 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 6756 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 6757 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 6758 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 6759 } 6760 } 6761 6762 /* Reset PCIE errors for debug */ 6763 REG_WR(bp, 0x2114, 0xffffffff); 6764 REG_WR(bp, 0x2120, 0xffffffff); 6765 6766 if (CHIP_IS_E1x(bp)) { 6767 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 6768 main_mem_base = HC_REG_MAIN_MEMORY + 6769 BP_PORT(bp) * (main_mem_size * 4); 6770 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 6771 main_mem_width = 8; 6772 6773 val = REG_RD(bp, main_mem_prty_clr); 6774 if (val) 6775 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC " 6776 "block during " 6777 "function init (0x%x)!\n", val); 6778 6779 /* Clear "false" parity errors in MSI-X table */ 6780 for (i = main_mem_base; 6781 i < main_mem_base + main_mem_size * 4; 6782 i += main_mem_width) { 6783 bnx2x_read_dmae(bp, i, main_mem_width / 4); 6784 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), 6785 i, main_mem_width / 4); 6786 } 6787 /* Clear HC parity attention */ 6788 REG_RD(bp, main_mem_prty_clr); 6789 } 6790 6791#ifdef BNX2X_STOP_ON_ERROR 6792 /* Enable STORMs SP logging */ 6793 REG_WR8(bp, BAR_USTRORM_INTMEM + 6794 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6795 REG_WR8(bp, BAR_TSTRORM_INTMEM + 6796 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6797 REG_WR8(bp, BAR_CSTRORM_INTMEM + 6798 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6799 REG_WR8(bp, BAR_XSTRORM_INTMEM + 6800 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6801#endif 6802 6803 bnx2x_phy_probe(&bp->link_params); 6804 6805 return 0; 6806} 6807 6808 6809void bnx2x_free_mem(struct bnx2x *bp) 6810{ 6811 /* fastpath */ 6812 bnx2x_free_fp_mem(bp); 6813 /* end of fastpath */ 6814 6815 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 6816 sizeof(struct host_sp_status_block)); 6817 6818 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 6819 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 6820 6821 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 6822 sizeof(struct bnx2x_slowpath)); 6823 6824 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping, 6825 bp->context.size); 6826 6827 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); 6828 6829 BNX2X_FREE(bp->ilt->lines); 6830 6831#ifdef BCM_CNIC 6832 if (!CHIP_IS_E1x(bp)) 6833 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, 6834 sizeof(struct host_hc_status_block_e2)); 6835 else 6836 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, 6837 sizeof(struct host_hc_status_block_e1x)); 6838 6839 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 6840#endif 6841 6842 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 6843 6844 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, 6845 BCM_PAGE_SIZE * NUM_EQ_PAGES); 6846} 6847 6848static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) 6849{ 6850 int num_groups; 6851 6852 /* number of eth_queues */ 6853 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp); 6854 6855 /* Total number of FW statistics requests = 6856 * 1 for port stats + 1 for PF stats + num_eth_queues */ 6857 bp->fw_stats_num = 2 + num_queue_stats; 6858 6859 6860 /* Request is built from stats_query_header and an array of 6861 * stats_query_cmd_group each of which contains 6862 * STATS_QUERY_CMD_COUNT rules. The real number or requests is 6863 * configured in the stats_query_header. 6864 */ 6865 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT + 6866 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0); 6867 6868 bp->fw_stats_req_sz = sizeof(struct stats_query_header) + 6869 num_groups * sizeof(struct stats_query_cmd_group); 6870 6871 /* Data for statistics requests + stats_conter 6872 * 6873 * stats_counter holds per-STORM counters that are incremented 6874 * when STORM has finished with the current request. 6875 */ 6876 bp->fw_stats_data_sz = sizeof(struct per_port_stats) + 6877 sizeof(struct per_pf_stats) + 6878 sizeof(struct per_queue_stats) * num_queue_stats + 6879 sizeof(struct stats_counter); 6880 6881 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, 6882 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 6883 6884 /* Set shortcuts */ 6885 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; 6886 bp->fw_stats_req_mapping = bp->fw_stats_mapping; 6887 6888 bp->fw_stats_data = (struct bnx2x_fw_stats_data *) 6889 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); 6890 6891 bp->fw_stats_data_mapping = bp->fw_stats_mapping + 6892 bp->fw_stats_req_sz; 6893 return 0; 6894 6895alloc_mem_err: 6896 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 6897 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 6898 return -ENOMEM; 6899} 6900 6901 6902int bnx2x_alloc_mem(struct bnx2x *bp) 6903{ 6904#ifdef BCM_CNIC 6905 if (!CHIP_IS_E1x(bp)) 6906 /* size = the status block + ramrod buffers */ 6907 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, 6908 sizeof(struct host_hc_status_block_e2)); 6909 else 6910 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, 6911 sizeof(struct host_hc_status_block_e1x)); 6912 6913 /* allocate searcher T2 table */ 6914 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); 6915#endif 6916 6917 6918 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, 6919 sizeof(struct host_sp_status_block)); 6920 6921 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, 6922 sizeof(struct bnx2x_slowpath)); 6923 6924 /* Allocated memory for FW statistics */ 6925 if (bnx2x_alloc_fw_stats_mem(bp)) 6926 goto alloc_mem_err; 6927 6928 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); 6929 6930 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping, 6931 bp->context.size); 6932 6933 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); 6934 6935 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) 6936 goto alloc_mem_err; 6937 6938 /* Slow path ring */ 6939 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); 6940 6941 /* EQ */ 6942 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, 6943 BCM_PAGE_SIZE * NUM_EQ_PAGES); 6944 6945 6946 /* fastpath */ 6947 /* need to be done at the end, since it's self adjusting to amount 6948 * of memory available for RSS queues 6949 */ 6950 if (bnx2x_alloc_fp_mem(bp)) 6951 goto alloc_mem_err; 6952 return 0; 6953 6954alloc_mem_err: 6955 bnx2x_free_mem(bp); 6956 return -ENOMEM; 6957} 6958 6959/* 6960 * Init service functions 6961 */ 6962 6963int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 6964 struct bnx2x_vlan_mac_obj *obj, bool set, 6965 int mac_type, unsigned long *ramrod_flags) 6966{ 6967 int rc; 6968 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 6969 6970 memset(&ramrod_param, 0, sizeof(ramrod_param)); 6971 6972 /* Fill general parameters */ 6973 ramrod_param.vlan_mac_obj = obj; 6974 ramrod_param.ramrod_flags = *ramrod_flags; 6975 6976 /* Fill a user request section if needed */ 6977 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 6978 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 6979 6980 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 6981 6982 /* Set the command: ADD or DEL */ 6983 if (set) 6984 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 6985 else 6986 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 6987 } 6988 6989 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 6990 if (rc < 0) 6991 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); 6992 return rc; 6993} 6994 6995int bnx2x_del_all_macs(struct bnx2x *bp, 6996 struct bnx2x_vlan_mac_obj *mac_obj, 6997 int mac_type, bool wait_for_comp) 6998{ 6999 int rc; 7000 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 7001 7002 /* Wait for completion of requested */ 7003 if (wait_for_comp) 7004 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7005 7006 /* Set the mac type of addresses we want to clear */ 7007 __set_bit(mac_type, &vlan_mac_flags); 7008 7009 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); 7010 if (rc < 0) 7011 BNX2X_ERR("Failed to delete MACs: %d\n", rc); 7012 7013 return rc; 7014} 7015 7016int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) 7017{ 7018 unsigned long ramrod_flags = 0; 7019 7020 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); 7021 7022 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7023 /* Eth MAC is set on RSS leading client (fp[0]) */ 7024 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set, 7025 BNX2X_ETH_MAC, &ramrod_flags); 7026} 7027 7028int bnx2x_setup_leading(struct bnx2x *bp) 7029{ 7030 return bnx2x_setup_queue(bp, &bp->fp[0], 1); 7031} 7032 7033/** 7034 * bnx2x_set_int_mode - configure interrupt mode 7035 * 7036 * @bp: driver handle 7037 * 7038 * In case of MSI-X it will also try to enable MSI-X. 7039 */ 7040static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) 7041{ 7042 switch (int_mode) { 7043 case INT_MODE_MSI: 7044 bnx2x_enable_msi(bp); 7045 /* falling through... */ 7046 case INT_MODE_INTx: 7047 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7048 DP(NETIF_MSG_IFUP, "set number of queues to 1\n"); 7049 break; 7050 default: 7051 /* Set number of queues according to bp->multi_mode value */ 7052 bnx2x_set_num_queues(bp); 7053 7054 DP(NETIF_MSG_IFUP, "set number of queues to %d\n", 7055 bp->num_queues); 7056 7057 /* if we can't use MSI-X we only need one fp, 7058 * so try to enable MSI-X with the requested number of fp's 7059 * and fallback to MSI or legacy INTx with one fp 7060 */ 7061 if (bnx2x_enable_msix(bp)) { 7062 /* failed to enable MSI-X */ 7063 if (bp->multi_mode) 7064 DP(NETIF_MSG_IFUP, 7065 "Multi requested but failed to " 7066 "enable MSI-X (%d), " 7067 "set number of queues to %d\n", 7068 bp->num_queues, 7069 1 + NON_ETH_CONTEXT_USE); 7070 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7071 7072 /* Try to enable MSI */ 7073 if (!(bp->flags & DISABLE_MSI_FLAG)) 7074 bnx2x_enable_msi(bp); 7075 } 7076 break; 7077 } 7078} 7079 7080/* must be called prioir to any HW initializations */ 7081static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) 7082{ 7083 return L2_ILT_LINES(bp); 7084} 7085 7086void bnx2x_ilt_set_info(struct bnx2x *bp) 7087{ 7088 struct ilt_client_info *ilt_client; 7089 struct bnx2x_ilt *ilt = BP_ILT(bp); 7090 u16 line = 0; 7091 7092 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); 7093 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); 7094 7095 /* CDU */ 7096 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 7097 ilt_client->client_num = ILT_CLIENT_CDU; 7098 ilt_client->page_size = CDU_ILT_PAGE_SZ; 7099 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 7100 ilt_client->start = line; 7101 line += bnx2x_cid_ilt_lines(bp); 7102#ifdef BCM_CNIC 7103 line += CNIC_ILT_LINES; 7104#endif 7105 ilt_client->end = line - 1; 7106 7107 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, " 7108 "flags 0x%x, hw psz %d\n", 7109 ilt_client->start, 7110 ilt_client->end, 7111 ilt_client->page_size, 7112 ilt_client->flags, 7113 ilog2(ilt_client->page_size >> 12)); 7114 7115 /* QM */ 7116 if (QM_INIT(bp->qm_cid_count)) { 7117 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 7118 ilt_client->client_num = ILT_CLIENT_QM; 7119 ilt_client->page_size = QM_ILT_PAGE_SZ; 7120 ilt_client->flags = 0; 7121 ilt_client->start = line; 7122 7123 /* 4 bytes for each cid */ 7124 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 7125 QM_ILT_PAGE_SZ); 7126 7127 ilt_client->end = line - 1; 7128 7129 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, " 7130 "flags 0x%x, hw psz %d\n", 7131 ilt_client->start, 7132 ilt_client->end, 7133 ilt_client->page_size, 7134 ilt_client->flags, 7135 ilog2(ilt_client->page_size >> 12)); 7136 7137 } 7138 /* SRC */ 7139 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 7140#ifdef BCM_CNIC 7141 ilt_client->client_num = ILT_CLIENT_SRC; 7142 ilt_client->page_size = SRC_ILT_PAGE_SZ; 7143 ilt_client->flags = 0; 7144 ilt_client->start = line; 7145 line += SRC_ILT_LINES; 7146 ilt_client->end = line - 1; 7147 7148 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, " 7149 "flags 0x%x, hw psz %d\n", 7150 ilt_client->start, 7151 ilt_client->end, 7152 ilt_client->page_size, 7153 ilt_client->flags, 7154 ilog2(ilt_client->page_size >> 12)); 7155 7156#else 7157 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7158#endif 7159 7160 /* TM */ 7161 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 7162#ifdef BCM_CNIC 7163 ilt_client->client_num = ILT_CLIENT_TM; 7164 ilt_client->page_size = TM_ILT_PAGE_SZ; 7165 ilt_client->flags = 0; 7166 ilt_client->start = line; 7167 line += TM_ILT_LINES; 7168 ilt_client->end = line - 1; 7169 7170 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, " 7171 "flags 0x%x, hw psz %d\n", 7172 ilt_client->start, 7173 ilt_client->end, 7174 ilt_client->page_size, 7175 ilt_client->flags, 7176 ilog2(ilt_client->page_size >> 12)); 7177 7178#else 7179 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7180#endif 7181 BUG_ON(line > ILT_MAX_LINES); 7182} 7183 7184/** 7185 * bnx2x_pf_q_prep_init - prepare INIT transition parameters 7186 * 7187 * @bp: driver handle 7188 * @fp: pointer to fastpath 7189 * @init_params: pointer to parameters structure 7190 * 7191 * parameters configured: 7192 * - HC configuration 7193 * - Queue's CDU context 7194 */ 7195static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp, 7196 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) 7197{ 7198 7199 u8 cos; 7200 /* FCoE Queue uses Default SB, thus has no HC capabilities */ 7201 if (!IS_FCOE_FP(fp)) { 7202 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); 7203 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); 7204 7205 /* If HC is supporterd, enable host coalescing in the transition 7206 * to INIT state. 7207 */ 7208 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); 7209 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); 7210 7211 /* HC rate */ 7212 init_params->rx.hc_rate = bp->rx_ticks ? 7213 (1000000 / bp->rx_ticks) : 0; 7214 init_params->tx.hc_rate = bp->tx_ticks ? 7215 (1000000 / bp->tx_ticks) : 0; 7216 7217 /* FW SB ID */ 7218 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = 7219 fp->fw_sb_id; 7220 7221 /* 7222 * CQ index among the SB indices: FCoE clients uses the default 7223 * SB, therefore it's different. 7224 */ 7225 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 7226 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 7227 } 7228 7229 /* set maximum number of COSs supported by this queue */ 7230 init_params->max_cos = fp->max_cos; 7231 7232 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n", 7233 fp->index, init_params->max_cos); 7234 7235 /* set the context pointers queue object */ 7236 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) 7237 init_params->cxts[cos] = 7238 &bp->context.vcxt[fp->txdata[cos].cid].eth; 7239} 7240 7241int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7242 struct bnx2x_queue_state_params *q_params, 7243 struct bnx2x_queue_setup_tx_only_params *tx_only_params, 7244 int tx_index, bool leading) 7245{ 7246 memset(tx_only_params, 0, sizeof(*tx_only_params)); 7247 7248 /* Set the command */ 7249 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 7250 7251 /* Set tx-only QUEUE flags: don't zero statistics */ 7252 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); 7253 7254 /* choose the index of the cid to send the slow path on */ 7255 tx_only_params->cid_index = tx_index; 7256 7257 /* Set general TX_ONLY_SETUP parameters */ 7258 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); 7259 7260 /* Set Tx TX_ONLY_SETUP parameters */ 7261 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 7262 7263 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:" 7264 "cos %d, primary cid %d, cid %d, " 7265 "client id %d, sp-client id %d, flags %lx\n", 7266 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 7267 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 7268 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 7269 7270 /* send the ramrod */ 7271 return bnx2x_queue_state_change(bp, q_params); 7272} 7273 7274 7275/** 7276 * bnx2x_setup_queue - setup queue 7277 * 7278 * @bp: driver handle 7279 * @fp: pointer to fastpath 7280 * @leading: is leading 7281 * 7282 * This function performs 2 steps in a Queue state machine 7283 * actually: 1) RESET->INIT 2) INIT->SETUP 7284 */ 7285 7286int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7287 bool leading) 7288{ 7289 struct bnx2x_queue_state_params q_params = {0}; 7290 struct bnx2x_queue_setup_params *setup_params = 7291 &q_params.params.setup; 7292 struct bnx2x_queue_setup_tx_only_params *tx_only_params = 7293 &q_params.params.tx_only; 7294 int rc; 7295 u8 tx_index; 7296 7297 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index); 7298 7299 /* reset IGU state skip FCoE L2 queue */ 7300 if (!IS_FCOE_FP(fp)) 7301 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, 7302 IGU_INT_ENABLE, 0); 7303 7304 q_params.q_obj = &fp->q_obj; 7305 /* We want to wait for completion in this context */ 7306 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7307 7308 /* Prepare the INIT parameters */ 7309 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); 7310 7311 /* Set the command */ 7312 q_params.cmd = BNX2X_Q_CMD_INIT; 7313 7314 /* Change the state to INIT */ 7315 rc = bnx2x_queue_state_change(bp, &q_params); 7316 if (rc) { 7317 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); 7318 return rc; 7319 } 7320 7321 DP(BNX2X_MSG_SP, "init complete\n"); 7322 7323 7324 /* Now move the Queue to the SETUP state... */ 7325 memset(setup_params, 0, sizeof(*setup_params)); 7326 7327 /* Set QUEUE flags */ 7328 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); 7329 7330 /* Set general SETUP parameters */ 7331 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, 7332 FIRST_TX_COS_INDEX); 7333 7334 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, 7335 &setup_params->rxq_params); 7336 7337 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, 7338 FIRST_TX_COS_INDEX); 7339 7340 /* Set the command */ 7341 q_params.cmd = BNX2X_Q_CMD_SETUP; 7342 7343 /* Change the state to SETUP */ 7344 rc = bnx2x_queue_state_change(bp, &q_params); 7345 if (rc) { 7346 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); 7347 return rc; 7348 } 7349 7350 /* loop through the relevant tx-only indices */ 7351 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7352 tx_index < fp->max_cos; 7353 tx_index++) { 7354 7355 /* prepare and send tx-only ramrod*/ 7356 rc = bnx2x_setup_tx_only(bp, fp, &q_params, 7357 tx_only_params, tx_index, leading); 7358 if (rc) { 7359 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", 7360 fp->index, tx_index); 7361 return rc; 7362 } 7363 } 7364 7365 return rc; 7366} 7367 7368static int bnx2x_stop_queue(struct bnx2x *bp, int index) 7369{ 7370 struct bnx2x_fastpath *fp = &bp->fp[index]; 7371 struct bnx2x_fp_txdata *txdata; 7372 struct bnx2x_queue_state_params q_params = {0}; 7373 int rc, tx_index; 7374 7375 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid); 7376 7377 q_params.q_obj = &fp->q_obj; 7378 /* We want to wait for completion in this context */ 7379 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7380 7381 7382 /* close tx-only connections */ 7383 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7384 tx_index < fp->max_cos; 7385 tx_index++){ 7386 7387 /* ascertain this is a normal queue*/ 7388 txdata = &fp->txdata[tx_index]; 7389 7390 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n", 7391 txdata->txq_index); 7392 7393 /* send halt terminate on tx-only connection */ 7394 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7395 memset(&q_params.params.terminate, 0, 7396 sizeof(q_params.params.terminate)); 7397 q_params.params.terminate.cid_index = tx_index; 7398 7399 rc = bnx2x_queue_state_change(bp, &q_params); 7400 if (rc) 7401 return rc; 7402 7403 /* send halt terminate on tx-only connection */ 7404 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7405 memset(&q_params.params.cfc_del, 0, 7406 sizeof(q_params.params.cfc_del)); 7407 q_params.params.cfc_del.cid_index = tx_index; 7408 rc = bnx2x_queue_state_change(bp, &q_params); 7409 if (rc) 7410 return rc; 7411 } 7412 /* Stop the primary connection: */ 7413 /* ...halt the connection */ 7414 q_params.cmd = BNX2X_Q_CMD_HALT; 7415 rc = bnx2x_queue_state_change(bp, &q_params); 7416 if (rc) 7417 return rc; 7418 7419 /* ...terminate the connection */ 7420 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7421 memset(&q_params.params.terminate, 0, 7422 sizeof(q_params.params.terminate)); 7423 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 7424 rc = bnx2x_queue_state_change(bp, &q_params); 7425 if (rc) 7426 return rc; 7427 /* ...delete cfc entry */ 7428 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7429 memset(&q_params.params.cfc_del, 0, 7430 sizeof(q_params.params.cfc_del)); 7431 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 7432 return bnx2x_queue_state_change(bp, &q_params); 7433} 7434 7435 7436static void bnx2x_reset_func(struct bnx2x *bp) 7437{ 7438 int port = BP_PORT(bp); 7439 int func = BP_FUNC(bp); 7440 int i; 7441 7442 /* Disable the function in the FW */ 7443 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 7444 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 7445 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 7446 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 7447 7448 /* FP SBs */ 7449 for_each_eth_queue(bp, i) { 7450 struct bnx2x_fastpath *fp = &bp->fp[i]; 7451 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7452 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 7453 SB_DISABLED); 7454 } 7455 7456#ifdef BCM_CNIC 7457 /* CNIC SB */ 7458 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7459 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), 7460 SB_DISABLED); 7461#endif 7462 /* SP SB */ 7463 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7464 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 7465 SB_DISABLED); 7466 7467 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) 7468 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 7469 0); 7470 7471 /* Configure IGU */ 7472 if (bp->common.int_block == INT_BLOCK_HC) { 7473 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7474 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7475 } else { 7476 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 7477 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 7478 } 7479 7480#ifdef BCM_CNIC 7481 /* Disable Timer scan */ 7482 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 7483 /* 7484 * Wait for at least 10ms and up to 2 second for the timers scan to 7485 * complete 7486 */ 7487 for (i = 0; i < 200; i++) { 7488 msleep(10); 7489 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) 7490 break; 7491 } 7492#endif 7493 /* Clear ILT */ 7494 bnx2x_clear_func_ilt(bp, func); 7495 7496 /* Timers workaround bug for E2: if this is vnic-3, 7497 * we need to set the entire ilt range for this timers. 7498 */ 7499 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { 7500 struct ilt_client_info ilt_cli; 7501 /* use dummy TM client */ 7502 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 7503 ilt_cli.start = 0; 7504 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 7505 ilt_cli.client_num = ILT_CLIENT_TM; 7506 7507 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); 7508 } 7509 7510 /* this assumes that reset_port() called before reset_func()*/ 7511 if (!CHIP_IS_E1x(bp)) 7512 bnx2x_pf_disable(bp); 7513 7514 bp->dmae_ready = 0; 7515} 7516 7517static void bnx2x_reset_port(struct bnx2x *bp) 7518{ 7519 int port = BP_PORT(bp); 7520 u32 val; 7521 7522 /* Reset physical Link */ 7523 bnx2x__link_reset(bp); 7524 7525 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 7526 7527 /* Do not rcv packets to BRB */ 7528 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 7529 /* Do not direct rcv packets that are not for MCP to the BRB */ 7530 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 7531 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 7532 7533 /* Configure AEU */ 7534 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 7535 7536 msleep(100); 7537 /* Check for BRB port occupancy */ 7538 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 7539 if (val) 7540 DP(NETIF_MSG_IFDOWN, 7541 "BRB1 is not empty %d blocks are occupied\n", val); 7542 7543 /* TODO: Close Doorbell port? */ 7544} 7545 7546static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) 7547{ 7548 struct bnx2x_func_state_params func_params = {0}; 7549 7550 /* Prepare parameters for function state transitions */ 7551 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7552 7553 func_params.f_obj = &bp->func_obj; 7554 func_params.cmd = BNX2X_F_CMD_HW_RESET; 7555 7556 func_params.params.hw_init.load_phase = load_code; 7557 7558 return bnx2x_func_state_change(bp, &func_params); 7559} 7560 7561static inline int bnx2x_func_stop(struct bnx2x *bp) 7562{ 7563 struct bnx2x_func_state_params func_params = {0}; 7564 int rc; 7565 7566 /* Prepare parameters for function state transitions */ 7567 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7568 func_params.f_obj = &bp->func_obj; 7569 func_params.cmd = BNX2X_F_CMD_STOP; 7570 7571 /* 7572 * Try to stop the function the 'good way'. If fails (in case 7573 * of a parity error during bnx2x_chip_cleanup()) and we are 7574 * not in a debug mode, perform a state transaction in order to 7575 * enable further HW_RESET transaction. 7576 */ 7577 rc = bnx2x_func_state_change(bp, &func_params); 7578 if (rc) { 7579#ifdef BNX2X_STOP_ON_ERROR 7580 return rc; 7581#else 7582 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry " 7583 "transaction\n"); 7584 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 7585 return bnx2x_func_state_change(bp, &func_params); 7586#endif 7587 } 7588 7589 return 0; 7590} 7591 7592/** 7593 * bnx2x_send_unload_req - request unload mode from the MCP. 7594 * 7595 * @bp: driver handle 7596 * @unload_mode: requested function's unload mode 7597 * 7598 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 7599 */ 7600u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 7601{ 7602 u32 reset_code = 0; 7603 int port = BP_PORT(bp); 7604 7605 /* Select the UNLOAD request mode */ 7606 if (unload_mode == UNLOAD_NORMAL) 7607 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7608 7609 else if (bp->flags & NO_WOL_FLAG) 7610 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 7611 7612 else if (bp->wol) { 7613 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 7614 u8 *mac_addr = bp->dev->dev_addr; 7615 u32 val; 7616 u16 pmc; 7617 7618 /* The mac address is written to entries 1-4 to 7619 * preserve entry 0 which is used by the PMF 7620 */ 7621 u8 entry = (BP_VN(bp) + 1)*8; 7622 7623 val = (mac_addr[0] << 8) | mac_addr[1]; 7624 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 7625 7626 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 7627 (mac_addr[4] << 8) | mac_addr[5]; 7628 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 7629 7630 /* Enable the PME and clear the status */ 7631 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); 7632 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; 7633 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); 7634 7635 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 7636 7637 } else 7638 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7639 7640 /* Send the request to the MCP */ 7641 if (!BP_NOMCP(bp)) 7642 reset_code = bnx2x_fw_command(bp, reset_code, 0); 7643 else { 7644 int path = BP_PATH(bp); 7645 7646 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] " 7647 "%d, %d, %d\n", 7648 path, load_count[path][0], load_count[path][1], 7649 load_count[path][2]); 7650 load_count[path][0]--; 7651 load_count[path][1 + port]--; 7652 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] " 7653 "%d, %d, %d\n", 7654 path, load_count[path][0], load_count[path][1], 7655 load_count[path][2]); 7656 if (load_count[path][0] == 0) 7657 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 7658 else if (load_count[path][1 + port] == 0) 7659 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 7660 else 7661 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 7662 } 7663 7664 return reset_code; 7665} 7666 7667/** 7668 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 7669 * 7670 * @bp: driver handle 7671 */ 7672void bnx2x_send_unload_done(struct bnx2x *bp) 7673{ 7674 /* Report UNLOAD_DONE to MCP */ 7675 if (!BP_NOMCP(bp)) 7676 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 7677} 7678 7679static inline int bnx2x_func_wait_started(struct bnx2x *bp) 7680{ 7681 int tout = 50; 7682 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 7683 7684 if (!bp->port.pmf) 7685 return 0; 7686 7687 /* 7688 * (assumption: No Attention from MCP at this stage) 7689 * PMF probably in the middle of TXdisable/enable transaction 7690 * 1. Sync IRS for default SB 7691 * 2. Sync SP queue - this guarantes us that attention handling started 7692 * 3. Wait, that TXdisable/enable transaction completes 7693 * 7694 * 1+2 guranty that if DCBx attention was scheduled it already changed 7695 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy 7696 * received complettion for the transaction the state is TX_STOPPED. 7697 * State will return to STARTED after completion of TX_STOPPED-->STARTED 7698 * transaction. 7699 */ 7700 7701 /* make sure default SB ISR is done */ 7702 if (msix) 7703 synchronize_irq(bp->msix_table[0].vector); 7704 else 7705 synchronize_irq(bp->pdev->irq); 7706 7707 flush_workqueue(bnx2x_wq); 7708 7709 while (bnx2x_func_get_state(bp, &bp->func_obj) != 7710 BNX2X_F_STATE_STARTED && tout--) 7711 msleep(20); 7712 7713 if (bnx2x_func_get_state(bp, &bp->func_obj) != 7714 BNX2X_F_STATE_STARTED) { 7715#ifdef BNX2X_STOP_ON_ERROR 7716 return -EBUSY; 7717#else 7718 /* 7719 * Failed to complete the transaction in a "good way" 7720 * Force both transactions with CLR bit 7721 */ 7722 struct bnx2x_func_state_params func_params = {0}; 7723 7724 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! " 7725 "Forcing STARTED-->TX_ST0PPED-->STARTED\n"); 7726 7727 func_params.f_obj = &bp->func_obj; 7728 __set_bit(RAMROD_DRV_CLR_ONLY, 7729 &func_params.ramrod_flags); 7730 7731 /* STARTED-->TX_ST0PPED */ 7732 func_params.cmd = BNX2X_F_CMD_TX_STOP; 7733 bnx2x_func_state_change(bp, &func_params); 7734 7735 /* TX_ST0PPED-->STARTED */ 7736 func_params.cmd = BNX2X_F_CMD_TX_START; 7737 return bnx2x_func_state_change(bp, &func_params); 7738#endif 7739 } 7740 7741 return 0; 7742} 7743 7744void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) 7745{ 7746 int port = BP_PORT(bp); 7747 int i, rc = 0; 7748 u8 cos; 7749 struct bnx2x_mcast_ramrod_params rparam = {0}; 7750 u32 reset_code; 7751 7752 /* Wait until tx fastpath tasks complete */ 7753 for_each_tx_queue(bp, i) { 7754 struct bnx2x_fastpath *fp = &bp->fp[i]; 7755 7756 for_each_cos_in_tx_queue(fp, cos) 7757 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]); 7758#ifdef BNX2X_STOP_ON_ERROR 7759 if (rc) 7760 return; 7761#endif 7762 } 7763 7764 /* Give HW time to discard old tx messages */ 7765 usleep_range(1000, 1000); 7766 7767 /* Clean all ETH MACs */ 7768 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false); 7769 if (rc < 0) 7770 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); 7771 7772 /* Clean up UC list */ 7773 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, 7774 true); 7775 if (rc < 0) 7776 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: " 7777 "%d\n", rc); 7778 7779 /* Disable LLH */ 7780 if (!CHIP_IS_E1(bp)) 7781 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 7782 7783 /* Set "drop all" (stop Rx). 7784 * We need to take a netif_addr_lock() here in order to prevent 7785 * a race between the completion code and this code. 7786 */ 7787 netif_addr_lock_bh(bp->dev); 7788 /* Schedule the rx_mode command */ 7789 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 7790 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 7791 else 7792 bnx2x_set_storm_rx_mode(bp); 7793 7794 /* Cleanup multicast configuration */ 7795 rparam.mcast_obj = &bp->mcast_obj; 7796 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 7797 if (rc < 0) 7798 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); 7799 7800 netif_addr_unlock_bh(bp->dev); 7801 7802 7803 7804 /* 7805 * Send the UNLOAD_REQUEST to the MCP. This will return if 7806 * this function should perform FUNC, PORT or COMMON HW 7807 * reset. 7808 */ 7809 reset_code = bnx2x_send_unload_req(bp, unload_mode); 7810 7811 /* 7812 * (assumption: No Attention from MCP at this stage) 7813 * PMF probably in the middle of TXdisable/enable transaction 7814 */ 7815 rc = bnx2x_func_wait_started(bp); 7816 if (rc) { 7817 BNX2X_ERR("bnx2x_func_wait_started failed\n"); 7818#ifdef BNX2X_STOP_ON_ERROR 7819 return; 7820#endif 7821 } 7822 7823 /* Close multi and leading connections 7824 * Completions for ramrods are collected in a synchronous way 7825 */ 7826 for_each_queue(bp, i) 7827 if (bnx2x_stop_queue(bp, i)) 7828#ifdef BNX2X_STOP_ON_ERROR 7829 return; 7830#else 7831 goto unload_error; 7832#endif 7833 /* If SP settings didn't get completed so far - something 7834 * very wrong has happen. 7835 */ 7836 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) 7837 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); 7838 7839#ifndef BNX2X_STOP_ON_ERROR 7840unload_error: 7841#endif 7842 rc = bnx2x_func_stop(bp); 7843 if (rc) { 7844 BNX2X_ERR("Function stop failed!\n"); 7845#ifdef BNX2X_STOP_ON_ERROR 7846 return; 7847#endif 7848 } 7849 7850 /* Disable HW interrupts, NAPI */ 7851 bnx2x_netif_stop(bp, 1); 7852 7853 /* Release IRQs */ 7854 bnx2x_free_irq(bp); 7855 7856 /* Reset the chip */ 7857 rc = bnx2x_reset_hw(bp, reset_code); 7858 if (rc) 7859 BNX2X_ERR("HW_RESET failed\n"); 7860 7861 7862 /* Report UNLOAD_DONE to MCP */ 7863 bnx2x_send_unload_done(bp); 7864} 7865 7866void bnx2x_disable_close_the_gate(struct bnx2x *bp) 7867{ 7868 u32 val; 7869 7870 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n"); 7871 7872 if (CHIP_IS_E1(bp)) { 7873 int port = BP_PORT(bp); 7874 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 7875 MISC_REG_AEU_MASK_ATTN_FUNC_0; 7876 7877 val = REG_RD(bp, addr); 7878 val &= ~(0x300); 7879 REG_WR(bp, addr, val); 7880 } else { 7881 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); 7882 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 7883 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 7884 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); 7885 } 7886} 7887 7888/* Close gates #2, #3 and #4: */ 7889static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 7890{ 7891 u32 val; 7892 7893 /* Gates #2 and #4a are closed/opened for "not E1" only */ 7894 if (!CHIP_IS_E1(bp)) { 7895 /* #4 */ 7896 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 7897 /* #2 */ 7898 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 7899 } 7900 7901 /* #3 */ 7902 if (CHIP_IS_E1x(bp)) { 7903 /* Prevent interrupts from HC on both ports */ 7904 val = REG_RD(bp, HC_REG_CONFIG_1); 7905 REG_WR(bp, HC_REG_CONFIG_1, 7906 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 7907 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 7908 7909 val = REG_RD(bp, HC_REG_CONFIG_0); 7910 REG_WR(bp, HC_REG_CONFIG_0, 7911 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 7912 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 7913 } else { 7914 /* Prevent incomming interrupts in IGU */ 7915 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 7916 7917 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, 7918 (!close) ? 7919 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 7920 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 7921 } 7922 7923 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n", 7924 close ? "closing" : "opening"); 7925 mmiowb(); 7926} 7927 7928#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ 7929 7930static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) 7931{ 7932 /* Do some magic... */ 7933 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 7934 *magic_val = val & SHARED_MF_CLP_MAGIC; 7935 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 7936} 7937 7938/** 7939 * bnx2x_clp_reset_done - restore the value of the `magic' bit. 7940 * 7941 * @bp: driver handle 7942 * @magic_val: old value of the `magic' bit. 7943 */ 7944static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 7945{ 7946 /* Restore the `magic' bit value... */ 7947 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 7948 MF_CFG_WR(bp, shared_mf_config.clp_mb, 7949 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 7950} 7951 7952/** 7953 * bnx2x_reset_mcp_prep - prepare for MCP reset. 7954 * 7955 * @bp: driver handle 7956 * @magic_val: old value of 'magic' bit. 7957 * 7958 * Takes care of CLP configurations. 7959 */ 7960static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 7961{ 7962 u32 shmem; 7963 u32 validity_offset; 7964 7965 DP(NETIF_MSG_HW, "Starting\n"); 7966 7967 /* Set `magic' bit in order to save MF config */ 7968 if (!CHIP_IS_E1(bp)) 7969 bnx2x_clp_reset_prep(bp, magic_val); 7970 7971 /* Get shmem offset */ 7972 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 7973 validity_offset = offsetof(struct shmem_region, validity_map[0]); 7974 7975 /* Clear validity map flags */ 7976 if (shmem > 0) 7977 REG_WR(bp, shmem + validity_offset, 0); 7978} 7979 7980#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 7981#define MCP_ONE_TIMEOUT 100 /* 100 ms */ 7982 7983/** 7984 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT 7985 * 7986 * @bp: driver handle 7987 */ 7988static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) 7989{ 7990 /* special handling for emulation and FPGA, 7991 wait 10 times longer */ 7992 if (CHIP_REV_IS_SLOW(bp)) 7993 msleep(MCP_ONE_TIMEOUT*10); 7994 else 7995 msleep(MCP_ONE_TIMEOUT); 7996} 7997 7998/* 7999 * initializes bp->common.shmem_base and waits for validity signature to appear 8000 */ 8001static int bnx2x_init_shmem(struct bnx2x *bp) 8002{ 8003 int cnt = 0; 8004 u32 val = 0; 8005 8006 do { 8007 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8008 if (bp->common.shmem_base) { 8009 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 8010 if (val & SHR_MEM_VALIDITY_MB) 8011 return 0; 8012 } 8013 8014 bnx2x_mcp_wait_one(bp); 8015 8016 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 8017 8018 BNX2X_ERR("BAD MCP validity signature\n"); 8019 8020 return -ENODEV; 8021} 8022 8023static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 8024{ 8025 int rc = bnx2x_init_shmem(bp); 8026 8027 /* Restore the `magic' bit value */ 8028 if (!CHIP_IS_E1(bp)) 8029 bnx2x_clp_reset_done(bp, magic_val); 8030 8031 return rc; 8032} 8033 8034static void bnx2x_pxp_prep(struct bnx2x *bp) 8035{ 8036 if (!CHIP_IS_E1(bp)) { 8037 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 8038 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 8039 mmiowb(); 8040 } 8041} 8042 8043/* 8044 * Reset the whole chip except for: 8045 * - PCIE core 8046 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by 8047 * one reset bit) 8048 * - IGU 8049 * - MISC (including AEU) 8050 * - GRC 8051 * - RBCN, RBCP 8052 */ 8053static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) 8054{ 8055 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 8056 u32 global_bits2, stay_reset2; 8057 8058 /* 8059 * Bits that have to be set in reset_mask2 if we want to reset 'global' 8060 * (per chip) blocks. 8061 */ 8062 global_bits2 = 8063 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 8064 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 8065 8066 /* Don't reset the following blocks */ 8067 not_reset_mask1 = 8068 MISC_REGISTERS_RESET_REG_1_RST_HC | 8069 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 8070 MISC_REGISTERS_RESET_REG_1_RST_PXP; 8071 8072 not_reset_mask2 = 8073 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 8074 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 8075 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 8076 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 8077 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 8078 MISC_REGISTERS_RESET_REG_2_RST_GRC | 8079 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 8080 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 8081 MISC_REGISTERS_RESET_REG_2_RST_ATC | 8082 MISC_REGISTERS_RESET_REG_2_PGLC; 8083 8084 /* 8085 * Keep the following blocks in reset: 8086 * - all xxMACs are handled by the bnx2x_link code. 8087 */ 8088 stay_reset2 = 8089 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 8090 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 8091 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 8092 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 8093 MISC_REGISTERS_RESET_REG_2_UMAC0 | 8094 MISC_REGISTERS_RESET_REG_2_UMAC1 | 8095 MISC_REGISTERS_RESET_REG_2_XMAC | 8096 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 8097 8098 /* Full reset masks according to the chip */ 8099 reset_mask1 = 0xffffffff; 8100 8101 if (CHIP_IS_E1(bp)) 8102 reset_mask2 = 0xffff; 8103 else if (CHIP_IS_E1H(bp)) 8104 reset_mask2 = 0x1ffff; 8105 else if (CHIP_IS_E2(bp)) 8106 reset_mask2 = 0xfffff; 8107 else /* CHIP_IS_E3 */ 8108 reset_mask2 = 0x3ffffff; 8109 8110 /* Don't reset global blocks unless we need to */ 8111 if (!global) 8112 reset_mask2 &= ~global_bits2; 8113 8114 /* 8115 * In case of attention in the QM, we need to reset PXP 8116 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 8117 * because otherwise QM reset would release 'close the gates' shortly 8118 * before resetting the PXP, then the PSWRQ would send a write 8119 * request to PGLUE. Then when PXP is reset, PGLUE would try to 8120 * read the payload data from PSWWR, but PSWWR would not 8121 * respond. The write queue in PGLUE would stuck, dmae commands 8122 * would not return. Therefore it's important to reset the second 8123 * reset register (containing the 8124 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 8125 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 8126 * bit). 8127 */ 8128 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8129 reset_mask2 & (~not_reset_mask2)); 8130 8131 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8132 reset_mask1 & (~not_reset_mask1)); 8133 8134 barrier(); 8135 mmiowb(); 8136 8137 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 8138 reset_mask2 & (~stay_reset2)); 8139 8140 barrier(); 8141 mmiowb(); 8142 8143 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 8144 mmiowb(); 8145} 8146 8147/** 8148 * bnx2x_er_poll_igu_vq - poll for pending writes bit. 8149 * It should get cleared in no more than 1s. 8150 * 8151 * @bp: driver handle 8152 * 8153 * It should get cleared in no more than 1s. Returns 0 if 8154 * pending writes bit gets cleared. 8155 */ 8156static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) 8157{ 8158 u32 cnt = 1000; 8159 u32 pend_bits = 0; 8160 8161 do { 8162 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); 8163 8164 if (pend_bits == 0) 8165 break; 8166 8167 usleep_range(1000, 1000); 8168 } while (cnt-- > 0); 8169 8170 if (cnt <= 0) { 8171 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", 8172 pend_bits); 8173 return -EBUSY; 8174 } 8175 8176 return 0; 8177} 8178 8179static int bnx2x_process_kill(struct bnx2x *bp, bool global) 8180{ 8181 int cnt = 1000; 8182 u32 val = 0; 8183 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 8184 8185 8186 /* Empty the Tetris buffer, wait for 1s */ 8187 do { 8188 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); 8189 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); 8190 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); 8191 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); 8192 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); 8193 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 8194 ((port_is_idle_0 & 0x1) == 0x1) && 8195 ((port_is_idle_1 & 0x1) == 0x1) && 8196 (pgl_exp_rom2 == 0xffffffff)) 8197 break; 8198 usleep_range(1000, 1000); 8199 } while (cnt-- > 0); 8200 8201 if (cnt <= 0) { 8202 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there" 8203 " are still" 8204 " outstanding read requests after 1s!\n"); 8205 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x," 8206 " port_is_idle_0=0x%08x," 8207 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 8208 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 8209 pgl_exp_rom2); 8210 return -EAGAIN; 8211 } 8212 8213 barrier(); 8214 8215 /* Close gates #2, #3 and #4 */ 8216 bnx2x_set_234_gates(bp, true); 8217 8218 /* Poll for IGU VQs for 57712 and newer chips */ 8219 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) 8220 return -EAGAIN; 8221 8222 8223 /* TBD: Indicate that "process kill" is in progress to MCP */ 8224 8225 /* Clear "unprepared" bit */ 8226 REG_WR(bp, MISC_REG_UNPREPARED, 0); 8227 barrier(); 8228 8229 /* Make sure all is written to the chip before the reset */ 8230 mmiowb(); 8231 8232 /* Wait for 1ms to empty GLUE and PCI-E core queues, 8233 * PSWHST, GRC and PSWRD Tetris buffer. 8234 */ 8235 usleep_range(1000, 1000); 8236 8237 /* Prepare to chip reset: */ 8238 /* MCP */ 8239 if (global) 8240 bnx2x_reset_mcp_prep(bp, &val); 8241 8242 /* PXP */ 8243 bnx2x_pxp_prep(bp); 8244 barrier(); 8245 8246 /* reset the chip */ 8247 bnx2x_process_kill_chip_reset(bp, global); 8248 barrier(); 8249 8250 /* Recover after reset: */ 8251 /* MCP */ 8252 if (global && bnx2x_reset_mcp_comp(bp, val)) 8253 return -EAGAIN; 8254 8255 /* TBD: Add resetting the NO_MCP mode DB here */ 8256 8257 /* PXP */ 8258 bnx2x_pxp_prep(bp); 8259 8260 /* Open the gates #2, #3 and #4 */ 8261 bnx2x_set_234_gates(bp, false); 8262 8263 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a 8264 * reset state, re-enable attentions. */ 8265 8266 return 0; 8267} 8268 8269int bnx2x_leader_reset(struct bnx2x *bp) 8270{ 8271 int rc = 0; 8272 bool global = bnx2x_reset_is_global(bp); 8273 8274 /* Try to recover after the failure */ 8275 if (bnx2x_process_kill(bp, global)) { 8276 netdev_err(bp->dev, "Something bad had happen on engine %d! " 8277 "Aii!\n", BP_PATH(bp)); 8278 rc = -EAGAIN; 8279 goto exit_leader_reset; 8280 } 8281 8282 /* 8283 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver 8284 * state. 8285 */ 8286 bnx2x_set_reset_done(bp); 8287 if (global) 8288 bnx2x_clear_reset_global(bp); 8289 8290exit_leader_reset: 8291 bp->is_leader = 0; 8292 bnx2x_release_leader_lock(bp); 8293 smp_mb(); 8294 return rc; 8295} 8296 8297static inline void bnx2x_recovery_failed(struct bnx2x *bp) 8298{ 8299 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); 8300 8301 /* Disconnect this device */ 8302 netif_device_detach(bp->dev); 8303 8304 /* 8305 * Block ifup for all function on this engine until "process kill" 8306 * or power cycle. 8307 */ 8308 bnx2x_set_reset_in_progress(bp); 8309 8310 /* Shut down the power */ 8311 bnx2x_set_power_state(bp, PCI_D3hot); 8312 8313 bp->recovery_state = BNX2X_RECOVERY_FAILED; 8314 8315 smp_mb(); 8316} 8317 8318/* 8319 * Assumption: runs under rtnl lock. This together with the fact 8320 * that it's called only from bnx2x_sp_rtnl() ensure that it 8321 * will never be called when netif_running(bp->dev) is false. 8322 */ 8323static void bnx2x_parity_recover(struct bnx2x *bp) 8324{ 8325 bool global = false; 8326 8327 DP(NETIF_MSG_HW, "Handling parity\n"); 8328 while (1) { 8329 switch (bp->recovery_state) { 8330 case BNX2X_RECOVERY_INIT: 8331 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 8332 bnx2x_chk_parity_attn(bp, &global, false); 8333 8334 /* Try to get a LEADER_LOCK HW lock */ 8335 if (bnx2x_trylock_leader_lock(bp)) { 8336 bnx2x_set_reset_in_progress(bp); 8337 /* 8338 * Check if there is a global attention and if 8339 * there was a global attention, set the global 8340 * reset bit. 8341 */ 8342 8343 if (global) 8344 bnx2x_set_reset_global(bp); 8345 8346 bp->is_leader = 1; 8347 } 8348 8349 /* Stop the driver */ 8350 /* If interface has been removed - break */ 8351 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) 8352 return; 8353 8354 bp->recovery_state = BNX2X_RECOVERY_WAIT; 8355 8356 /* 8357 * Reset MCP command sequence number and MCP mail box 8358 * sequence as we are going to reset the MCP. 8359 */ 8360 if (global) { 8361 bp->fw_seq = 0; 8362 bp->fw_drv_pulse_wr_seq = 0; 8363 } 8364 8365 /* Ensure "is_leader", MCP command sequence and 8366 * "recovery_state" update values are seen on other 8367 * CPUs. 8368 */ 8369 smp_mb(); 8370 break; 8371 8372 case BNX2X_RECOVERY_WAIT: 8373 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 8374 if (bp->is_leader) { 8375 int other_engine = BP_PATH(bp) ? 0 : 1; 8376 u32 other_load_counter = 8377 bnx2x_get_load_cnt(bp, other_engine); 8378 u32 load_counter = 8379 bnx2x_get_load_cnt(bp, BP_PATH(bp)); 8380 global = bnx2x_reset_is_global(bp); 8381 8382 /* 8383 * In case of a parity in a global block, let 8384 * the first leader that performs a 8385 * leader_reset() reset the global blocks in 8386 * order to clear global attentions. Otherwise 8387 * the the gates will remain closed for that 8388 * engine. 8389 */ 8390 if (load_counter || 8391 (global && other_load_counter)) { 8392 /* Wait until all other functions get 8393 * down. 8394 */ 8395 schedule_delayed_work(&bp->sp_rtnl_task, 8396 HZ/10); 8397 return; 8398 } else { 8399 /* If all other functions got down - 8400 * try to bring the chip back to 8401 * normal. In any case it's an exit 8402 * point for a leader. 8403 */ 8404 if (bnx2x_leader_reset(bp)) { 8405 bnx2x_recovery_failed(bp); 8406 return; 8407 } 8408 8409 /* If we are here, means that the 8410 * leader has succeeded and doesn't 8411 * want to be a leader any more. Try 8412 * to continue as a none-leader. 8413 */ 8414 break; 8415 } 8416 } else { /* non-leader */ 8417 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { 8418 /* Try to get a LEADER_LOCK HW lock as 8419 * long as a former leader may have 8420 * been unloaded by the user or 8421 * released a leadership by another 8422 * reason. 8423 */ 8424 if (bnx2x_trylock_leader_lock(bp)) { 8425 /* I'm a leader now! Restart a 8426 * switch case. 8427 */ 8428 bp->is_leader = 1; 8429 break; 8430 } 8431 8432 schedule_delayed_work(&bp->sp_rtnl_task, 8433 HZ/10); 8434 return; 8435 8436 } else { 8437 /* 8438 * If there was a global attention, wait 8439 * for it to be cleared. 8440 */ 8441 if (bnx2x_reset_is_global(bp)) { 8442 schedule_delayed_work( 8443 &bp->sp_rtnl_task, 8444 HZ/10); 8445 return; 8446 } 8447 8448 if (bnx2x_nic_load(bp, LOAD_NORMAL)) 8449 bnx2x_recovery_failed(bp); 8450 else { 8451 bp->recovery_state = 8452 BNX2X_RECOVERY_DONE; 8453 smp_mb(); 8454 } 8455 8456 return; 8457 } 8458 } 8459 default: 8460 return; 8461 } 8462 } 8463} 8464 8465/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is 8466 * scheduled on a general queue in order to prevent a dead lock. 8467 */ 8468static void bnx2x_sp_rtnl_task(struct work_struct *work) 8469{ 8470 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); 8471 8472 rtnl_lock(); 8473 8474 if (!netif_running(bp->dev)) 8475 goto sp_rtnl_exit; 8476 8477 /* if stop on error is defined no recovery flows should be executed */ 8478#ifdef BNX2X_STOP_ON_ERROR 8479 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined " 8480 "so reset not done to allow debug dump,\n" 8481 "you will need to reboot when done\n"); 8482 goto sp_rtnl_not_reset; 8483#endif 8484 8485 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { 8486 /* 8487 * Clear all pending SP commands as we are going to reset the 8488 * function anyway. 8489 */ 8490 bp->sp_rtnl_state = 0; 8491 smp_mb(); 8492 8493 bnx2x_parity_recover(bp); 8494 8495 goto sp_rtnl_exit; 8496 } 8497 8498 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { 8499 /* 8500 * Clear all pending SP commands as we are going to reset the 8501 * function anyway. 8502 */ 8503 bp->sp_rtnl_state = 0; 8504 smp_mb(); 8505 8506 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 8507 bnx2x_nic_load(bp, LOAD_NORMAL); 8508 8509 goto sp_rtnl_exit; 8510 } 8511#ifdef BNX2X_STOP_ON_ERROR 8512sp_rtnl_not_reset: 8513#endif 8514 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) 8515 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); 8516 8517 /* 8518 * in case of fan failure we need to reset id if the "stop on error" 8519 * debug flag is set, since we trying to prevent permanent overheating 8520 * damage 8521 */ 8522 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { 8523 DP(BNX2X_MSG_SP, "fan failure detected. Unloading driver\n"); 8524 netif_device_detach(bp->dev); 8525 bnx2x_close(bp->dev); 8526 } 8527 8528sp_rtnl_exit: 8529 rtnl_unlock(); 8530} 8531 8532/* end of nic load/unload */ 8533 8534static void bnx2x_period_task(struct work_struct *work) 8535{ 8536 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); 8537 8538 if (!netif_running(bp->dev)) 8539 goto period_task_exit; 8540 8541 if (CHIP_REV_IS_SLOW(bp)) { 8542 BNX2X_ERR("period task called on emulation, ignoring\n"); 8543 goto period_task_exit; 8544 } 8545 8546 bnx2x_acquire_phy_lock(bp); 8547 /* 8548 * The barrier is needed to ensure the ordering between the writing to 8549 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and 8550 * the reading here. 8551 */ 8552 smp_mb(); 8553 if (bp->port.pmf) { 8554 bnx2x_period_func(&bp->link_params, &bp->link_vars); 8555 8556 /* Re-queue task in 1 sec */ 8557 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); 8558 } 8559 8560 bnx2x_release_phy_lock(bp); 8561period_task_exit: 8562 return; 8563} 8564 8565/* 8566 * Init service functions 8567 */ 8568 8569static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) 8570{ 8571 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; 8572 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; 8573 return base + (BP_ABS_FUNC(bp)) * stride; 8574} 8575 8576static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) 8577{ 8578 u32 reg = bnx2x_get_pretend_reg(bp); 8579 8580 /* Flush all outstanding writes */ 8581 mmiowb(); 8582 8583 /* Pretend to be function 0 */ 8584 REG_WR(bp, reg, 0); 8585 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ 8586 8587 /* From now we are in the "like-E1" mode */ 8588 bnx2x_int_disable(bp); 8589 8590 /* Flush all outstanding writes */ 8591 mmiowb(); 8592 8593 /* Restore the original function */ 8594 REG_WR(bp, reg, BP_ABS_FUNC(bp)); 8595 REG_RD(bp, reg); 8596} 8597 8598static inline void bnx2x_undi_int_disable(struct bnx2x *bp) 8599{ 8600 if (CHIP_IS_E1(bp)) 8601 bnx2x_int_disable(bp); 8602 else 8603 bnx2x_undi_int_disable_e1h(bp); 8604} 8605 8606static void __devinit bnx2x_undi_unload(struct bnx2x *bp) 8607{ 8608 u32 val; 8609 8610 /* Check if there is any driver already loaded */ 8611 val = REG_RD(bp, MISC_REG_UNPREPARED); 8612 if (val == 0x1) { 8613 8614 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8615 /* 8616 * Check if it is the UNDI driver 8617 * UNDI driver initializes CID offset for normal bell to 0x7 8618 */ 8619 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 8620 if (val == 0x7) { 8621 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8622 /* save our pf_num */ 8623 int orig_pf_num = bp->pf_num; 8624 int port; 8625 u32 swap_en, swap_val, value; 8626 8627 /* clear the UNDI indication */ 8628 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 8629 8630 BNX2X_DEV_INFO("UNDI is active! reset device\n"); 8631 8632 /* try unload UNDI on port 0 */ 8633 bp->pf_num = 0; 8634 bp->fw_seq = 8635 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8636 DRV_MSG_SEQ_NUMBER_MASK); 8637 reset_code = bnx2x_fw_command(bp, reset_code, 0); 8638 8639 /* if UNDI is loaded on the other port */ 8640 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { 8641 8642 /* send "DONE" for previous unload */ 8643 bnx2x_fw_command(bp, 8644 DRV_MSG_CODE_UNLOAD_DONE, 0); 8645 8646 /* unload UNDI on port 1 */ 8647 bp->pf_num = 1; 8648 bp->fw_seq = 8649 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8650 DRV_MSG_SEQ_NUMBER_MASK); 8651 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8652 8653 bnx2x_fw_command(bp, reset_code, 0); 8654 } 8655 8656 bnx2x_undi_int_disable(bp); 8657 port = BP_PORT(bp); 8658 8659 /* close input traffic and wait for it */ 8660 /* Do not rcv packets to BRB */ 8661 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK : 8662 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0); 8663 /* Do not direct rcv packets that are not for MCP to 8664 * the BRB */ 8665 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 8666 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 8667 /* clear AEU */ 8668 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8669 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0); 8670 msleep(10); 8671 8672 /* save NIG port swap info */ 8673 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 8674 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 8675 /* reset device */ 8676 REG_WR(bp, 8677 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8678 0xd3ffffff); 8679 8680 value = 0x1400; 8681 if (CHIP_IS_E3(bp)) { 8682 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 8683 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 8684 } 8685 8686 REG_WR(bp, 8687 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8688 value); 8689 8690 /* take the NIG out of reset and restore swap values */ 8691 REG_WR(bp, 8692 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 8693 MISC_REGISTERS_RESET_REG_1_RST_NIG); 8694 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val); 8695 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en); 8696 8697 /* send unload done to the MCP */ 8698 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 8699 8700 /* restore our func and fw_seq */ 8701 bp->pf_num = orig_pf_num; 8702 bp->fw_seq = 8703 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8704 DRV_MSG_SEQ_NUMBER_MASK); 8705 } 8706 8707 /* now it's safe to release the lock */ 8708 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8709 } 8710} 8711 8712static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) 8713{ 8714 u32 val, val2, val3, val4, id; 8715 u16 pmc; 8716 8717 /* Get the chip revision id and number. */ 8718 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 8719 val = REG_RD(bp, MISC_REG_CHIP_NUM); 8720 id = ((val & 0xffff) << 16); 8721 val = REG_RD(bp, MISC_REG_CHIP_REV); 8722 id |= ((val & 0xf) << 12); 8723 val = REG_RD(bp, MISC_REG_CHIP_METAL); 8724 id |= ((val & 0xff) << 4); 8725 val = REG_RD(bp, MISC_REG_BOND_ID); 8726 id |= (val & 0xf); 8727 bp->common.chip_id = id; 8728 8729 /* Set doorbell size */ 8730 bp->db_size = (1 << BNX2X_DB_SHIFT); 8731 8732 if (!CHIP_IS_E1x(bp)) { 8733 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 8734 if ((val & 1) == 0) 8735 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); 8736 else 8737 val = (val >> 1) & 1; 8738 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : 8739 "2_PORT_MODE"); 8740 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : 8741 CHIP_2_PORT_MODE; 8742 8743 if (CHIP_MODE_IS_4_PORT(bp)) 8744 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ 8745 else 8746 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ 8747 } else { 8748 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ 8749 bp->pfid = bp->pf_num; /* 0..7 */ 8750 } 8751 8752 bp->link_params.chip_id = bp->common.chip_id; 8753 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 8754 8755 val = (REG_RD(bp, 0x2874) & 0x55); 8756 if ((bp->common.chip_id & 0x1) || 8757 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { 8758 bp->flags |= ONE_PORT_FLAG; 8759 BNX2X_DEV_INFO("single port device\n"); 8760 } 8761 8762 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); 8763 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << 8764 (val & MCPR_NVM_CFG4_FLASH_SIZE)); 8765 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 8766 bp->common.flash_size, bp->common.flash_size); 8767 8768 bnx2x_init_shmem(bp); 8769 8770 8771 8772 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? 8773 MISC_REG_GENERIC_CR_1 : 8774 MISC_REG_GENERIC_CR_0)); 8775 8776 bp->link_params.shmem_base = bp->common.shmem_base; 8777 bp->link_params.shmem2_base = bp->common.shmem2_base; 8778 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 8779 bp->common.shmem_base, bp->common.shmem2_base); 8780 8781 if (!bp->common.shmem_base) { 8782 BNX2X_DEV_INFO("MCP not active\n"); 8783 bp->flags |= NO_MCP_FLAG; 8784 return; 8785 } 8786 8787 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 8788 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 8789 8790 bp->link_params.hw_led_mode = ((bp->common.hw_config & 8791 SHARED_HW_CFG_LED_MODE_MASK) >> 8792 SHARED_HW_CFG_LED_MODE_SHIFT); 8793 8794 bp->link_params.feature_config_flags = 0; 8795 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); 8796 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) 8797 bp->link_params.feature_config_flags |= 8798 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 8799 else 8800 bp->link_params.feature_config_flags &= 8801 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 8802 8803 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 8804 bp->common.bc_ver = val; 8805 BNX2X_DEV_INFO("bc_ver %X\n", val); 8806 if (val < BNX2X_BC_VER) { 8807 /* for now only warn 8808 * later we might need to enforce this */ 8809 BNX2X_ERR("This driver needs bc_ver %X but found %X, " 8810 "please upgrade BC\n", BNX2X_BC_VER, val); 8811 } 8812 bp->link_params.feature_config_flags |= 8813 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 8814 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 8815 8816 bp->link_params.feature_config_flags |= 8817 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? 8818 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; 8819 8820 bp->link_params.feature_config_flags |= 8821 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? 8822 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; 8823 8824 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); 8825 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; 8826 8827 BNX2X_DEV_INFO("%sWoL capable\n", 8828 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 8829 8830 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 8831 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 8832 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); 8833 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); 8834 8835 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", 8836 val, val2, val3, val4); 8837} 8838 8839#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 8840#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 8841 8842static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) 8843{ 8844 int pfid = BP_FUNC(bp); 8845 int igu_sb_id; 8846 u32 val; 8847 u8 fid, igu_sb_cnt = 0; 8848 8849 bp->igu_base_sb = 0xff; 8850 if (CHIP_INT_MODE_IS_BC(bp)) { 8851 int vn = BP_VN(bp); 8852 igu_sb_cnt = bp->igu_sb_cnt; 8853 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 8854 FP_SB_MAX_E1x; 8855 8856 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + 8857 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); 8858 8859 return; 8860 } 8861 8862 /* IGU in normal mode - read CAM */ 8863 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 8864 igu_sb_id++) { 8865 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 8866 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 8867 continue; 8868 fid = IGU_FID(val); 8869 if ((fid & IGU_FID_ENCODE_IS_PF)) { 8870 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) 8871 continue; 8872 if (IGU_VEC(val) == 0) 8873 /* default status block */ 8874 bp->igu_dsb_id = igu_sb_id; 8875 else { 8876 if (bp->igu_base_sb == 0xff) 8877 bp->igu_base_sb = igu_sb_id; 8878 igu_sb_cnt++; 8879 } 8880 } 8881 } 8882 8883#ifdef CONFIG_PCI_MSI 8884 /* 8885 * It's expected that number of CAM entries for this functions is equal 8886 * to the number evaluated based on the MSI-X table size. We want a 8887 * harsh warning if these values are different! 8888 */ 8889 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); 8890#endif 8891 8892 if (igu_sb_cnt == 0) 8893 BNX2X_ERR("CAM configuration error\n"); 8894} 8895 8896static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, 8897 u32 switch_cfg) 8898{ 8899 int cfg_size = 0, idx, port = BP_PORT(bp); 8900 8901 /* Aggregation of supported attributes of all external phys */ 8902 bp->port.supported[0] = 0; 8903 bp->port.supported[1] = 0; 8904 switch (bp->link_params.num_phys) { 8905 case 1: 8906 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; 8907 cfg_size = 1; 8908 break; 8909 case 2: 8910 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; 8911 cfg_size = 1; 8912 break; 8913 case 3: 8914 if (bp->link_params.multi_phy_config & 8915 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 8916 bp->port.supported[1] = 8917 bp->link_params.phy[EXT_PHY1].supported; 8918 bp->port.supported[0] = 8919 bp->link_params.phy[EXT_PHY2].supported; 8920 } else { 8921 bp->port.supported[0] = 8922 bp->link_params.phy[EXT_PHY1].supported; 8923 bp->port.supported[1] = 8924 bp->link_params.phy[EXT_PHY2].supported; 8925 } 8926 cfg_size = 2; 8927 break; 8928 } 8929 8930 if (!(bp->port.supported[0] || bp->port.supported[1])) { 8931 BNX2X_ERR("NVRAM config error. BAD phy config." 8932 "PHY1 config 0x%x, PHY2 config 0x%x\n", 8933 SHMEM_RD(bp, 8934 dev_info.port_hw_config[port].external_phy_config), 8935 SHMEM_RD(bp, 8936 dev_info.port_hw_config[port].external_phy_config2)); 8937 return; 8938 } 8939 8940 if (CHIP_IS_E3(bp)) 8941 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); 8942 else { 8943 switch (switch_cfg) { 8944 case SWITCH_CFG_1G: 8945 bp->port.phy_addr = REG_RD( 8946 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 8947 break; 8948 case SWITCH_CFG_10G: 8949 bp->port.phy_addr = REG_RD( 8950 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 8951 break; 8952 default: 8953 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 8954 bp->port.link_config[0]); 8955 return; 8956 } 8957 } 8958 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 8959 /* mask what we support according to speed_cap_mask per configuration */ 8960 for (idx = 0; idx < cfg_size; idx++) { 8961 if (!(bp->link_params.speed_cap_mask[idx] & 8962 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 8963 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; 8964 8965 if (!(bp->link_params.speed_cap_mask[idx] & 8966 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 8967 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; 8968 8969 if (!(bp->link_params.speed_cap_mask[idx] & 8970 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 8971 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; 8972 8973 if (!(bp->link_params.speed_cap_mask[idx] & 8974 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 8975 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; 8976 8977 if (!(bp->link_params.speed_cap_mask[idx] & 8978 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 8979 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | 8980 SUPPORTED_1000baseT_Full); 8981 8982 if (!(bp->link_params.speed_cap_mask[idx] & 8983 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 8984 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; 8985 8986 if (!(bp->link_params.speed_cap_mask[idx] & 8987 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 8988 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; 8989 8990 } 8991 8992 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], 8993 bp->port.supported[1]); 8994} 8995 8996static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) 8997{ 8998 u32 link_config, idx, cfg_size = 0; 8999 bp->port.advertising[0] = 0; 9000 bp->port.advertising[1] = 0; 9001 switch (bp->link_params.num_phys) { 9002 case 1: 9003 case 2: 9004 cfg_size = 1; 9005 break; 9006 case 3: 9007 cfg_size = 2; 9008 break; 9009 } 9010 for (idx = 0; idx < cfg_size; idx++) { 9011 bp->link_params.req_duplex[idx] = DUPLEX_FULL; 9012 link_config = bp->port.link_config[idx]; 9013 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 9014 case PORT_FEATURE_LINK_SPEED_AUTO: 9015 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { 9016 bp->link_params.req_line_speed[idx] = 9017 SPEED_AUTO_NEG; 9018 bp->port.advertising[idx] |= 9019 bp->port.supported[idx]; 9020 } else { 9021 /* force 10G, no AN */ 9022 bp->link_params.req_line_speed[idx] = 9023 SPEED_10000; 9024 bp->port.advertising[idx] |= 9025 (ADVERTISED_10000baseT_Full | 9026 ADVERTISED_FIBRE); 9027 continue; 9028 } 9029 break; 9030 9031 case PORT_FEATURE_LINK_SPEED_10M_FULL: 9032 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { 9033 bp->link_params.req_line_speed[idx] = 9034 SPEED_10; 9035 bp->port.advertising[idx] |= 9036 (ADVERTISED_10baseT_Full | 9037 ADVERTISED_TP); 9038 } else { 9039 BNX2X_ERR("NVRAM config error. " 9040 "Invalid link_config 0x%x" 9041 " speed_cap_mask 0x%x\n", 9042 link_config, 9043 bp->link_params.speed_cap_mask[idx]); 9044 return; 9045 } 9046 break; 9047 9048 case PORT_FEATURE_LINK_SPEED_10M_HALF: 9049 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { 9050 bp->link_params.req_line_speed[idx] = 9051 SPEED_10; 9052 bp->link_params.req_duplex[idx] = 9053 DUPLEX_HALF; 9054 bp->port.advertising[idx] |= 9055 (ADVERTISED_10baseT_Half | 9056 ADVERTISED_TP); 9057 } else { 9058 BNX2X_ERR("NVRAM config error. " 9059 "Invalid link_config 0x%x" 9060 " speed_cap_mask 0x%x\n", 9061 link_config, 9062 bp->link_params.speed_cap_mask[idx]); 9063 return; 9064 } 9065 break; 9066 9067 case PORT_FEATURE_LINK_SPEED_100M_FULL: 9068 if (bp->port.supported[idx] & 9069 SUPPORTED_100baseT_Full) { 9070 bp->link_params.req_line_speed[idx] = 9071 SPEED_100; 9072 bp->port.advertising[idx] |= 9073 (ADVERTISED_100baseT_Full | 9074 ADVERTISED_TP); 9075 } else { 9076 BNX2X_ERR("NVRAM config error. " 9077 "Invalid link_config 0x%x" 9078 " speed_cap_mask 0x%x\n", 9079 link_config, 9080 bp->link_params.speed_cap_mask[idx]); 9081 return; 9082 } 9083 break; 9084 9085 case PORT_FEATURE_LINK_SPEED_100M_HALF: 9086 if (bp->port.supported[idx] & 9087 SUPPORTED_100baseT_Half) { 9088 bp->link_params.req_line_speed[idx] = 9089 SPEED_100; 9090 bp->link_params.req_duplex[idx] = 9091 DUPLEX_HALF; 9092 bp->port.advertising[idx] |= 9093 (ADVERTISED_100baseT_Half | 9094 ADVERTISED_TP); 9095 } else { 9096 BNX2X_ERR("NVRAM config error. " 9097 "Invalid link_config 0x%x" 9098 " speed_cap_mask 0x%x\n", 9099 link_config, 9100 bp->link_params.speed_cap_mask[idx]); 9101 return; 9102 } 9103 break; 9104 9105 case PORT_FEATURE_LINK_SPEED_1G: 9106 if (bp->port.supported[idx] & 9107 SUPPORTED_1000baseT_Full) { 9108 bp->link_params.req_line_speed[idx] = 9109 SPEED_1000; 9110 bp->port.advertising[idx] |= 9111 (ADVERTISED_1000baseT_Full | 9112 ADVERTISED_TP); 9113 } else { 9114 BNX2X_ERR("NVRAM config error. " 9115 "Invalid link_config 0x%x" 9116 " speed_cap_mask 0x%x\n", 9117 link_config, 9118 bp->link_params.speed_cap_mask[idx]); 9119 return; 9120 } 9121 break; 9122 9123 case PORT_FEATURE_LINK_SPEED_2_5G: 9124 if (bp->port.supported[idx] & 9125 SUPPORTED_2500baseX_Full) { 9126 bp->link_params.req_line_speed[idx] = 9127 SPEED_2500; 9128 bp->port.advertising[idx] |= 9129 (ADVERTISED_2500baseX_Full | 9130 ADVERTISED_TP); 9131 } else { 9132 BNX2X_ERR("NVRAM config error. " 9133 "Invalid link_config 0x%x" 9134 " speed_cap_mask 0x%x\n", 9135 link_config, 9136 bp->link_params.speed_cap_mask[idx]); 9137 return; 9138 } 9139 break; 9140 9141 case PORT_FEATURE_LINK_SPEED_10G_CX4: 9142 if (bp->port.supported[idx] & 9143 SUPPORTED_10000baseT_Full) { 9144 bp->link_params.req_line_speed[idx] = 9145 SPEED_10000; 9146 bp->port.advertising[idx] |= 9147 (ADVERTISED_10000baseT_Full | 9148 ADVERTISED_FIBRE); 9149 } else { 9150 BNX2X_ERR("NVRAM config error. " 9151 "Invalid link_config 0x%x" 9152 " speed_cap_mask 0x%x\n", 9153 link_config, 9154 bp->link_params.speed_cap_mask[idx]); 9155 return; 9156 } 9157 break; 9158 case PORT_FEATURE_LINK_SPEED_20G: 9159 bp->link_params.req_line_speed[idx] = SPEED_20000; 9160 9161 break; 9162 default: 9163 BNX2X_ERR("NVRAM config error. " 9164 "BAD link speed link_config 0x%x\n", 9165 link_config); 9166 bp->link_params.req_line_speed[idx] = 9167 SPEED_AUTO_NEG; 9168 bp->port.advertising[idx] = 9169 bp->port.supported[idx]; 9170 break; 9171 } 9172 9173 bp->link_params.req_flow_ctrl[idx] = (link_config & 9174 PORT_FEATURE_FLOW_CONTROL_MASK); 9175 if ((bp->link_params.req_flow_ctrl[idx] == 9176 BNX2X_FLOW_CTRL_AUTO) && 9177 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { 9178 bp->link_params.req_flow_ctrl[idx] = 9179 BNX2X_FLOW_CTRL_NONE; 9180 } 9181 9182 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl" 9183 " 0x%x advertising 0x%x\n", 9184 bp->link_params.req_line_speed[idx], 9185 bp->link_params.req_duplex[idx], 9186 bp->link_params.req_flow_ctrl[idx], 9187 bp->port.advertising[idx]); 9188 } 9189} 9190 9191static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 9192{ 9193 mac_hi = cpu_to_be16(mac_hi); 9194 mac_lo = cpu_to_be32(mac_lo); 9195 memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); 9196 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); 9197} 9198 9199static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) 9200{ 9201 int port = BP_PORT(bp); 9202 u32 config; 9203 u32 ext_phy_type, ext_phy_config; 9204 9205 bp->link_params.bp = bp; 9206 bp->link_params.port = port; 9207 9208 bp->link_params.lane_config = 9209 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 9210 9211 bp->link_params.speed_cap_mask[0] = 9212 SHMEM_RD(bp, 9213 dev_info.port_hw_config[port].speed_capability_mask); 9214 bp->link_params.speed_cap_mask[1] = 9215 SHMEM_RD(bp, 9216 dev_info.port_hw_config[port].speed_capability_mask2); 9217 bp->port.link_config[0] = 9218 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 9219 9220 bp->port.link_config[1] = 9221 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); 9222 9223 bp->link_params.multi_phy_config = 9224 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); 9225 /* If the device is capable of WoL, set the default state according 9226 * to the HW 9227 */ 9228 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 9229 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 9230 (config & PORT_FEATURE_WOL_ENABLED)); 9231 9232 BNX2X_DEV_INFO("lane_config 0x%08x " 9233 "speed_cap_mask0 0x%08x link_config0 0x%08x\n", 9234 bp->link_params.lane_config, 9235 bp->link_params.speed_cap_mask[0], 9236 bp->port.link_config[0]); 9237 9238 bp->link_params.switch_cfg = (bp->port.link_config[0] & 9239 PORT_FEATURE_CONNECTED_SWITCH_MASK); 9240 bnx2x_phy_probe(&bp->link_params); 9241 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 9242 9243 bnx2x_link_settings_requested(bp); 9244 9245 /* 9246 * If connected directly, work with the internal PHY, otherwise, work 9247 * with the external PHY 9248 */ 9249 ext_phy_config = 9250 SHMEM_RD(bp, 9251 dev_info.port_hw_config[port].external_phy_config); 9252 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 9253 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 9254 bp->mdio.prtad = bp->port.phy_addr; 9255 9256 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 9257 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 9258 bp->mdio.prtad = 9259 XGXS_EXT_PHY_ADDR(ext_phy_config); 9260 9261 /* 9262 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) 9263 * In MF mode, it is set to cover self test cases 9264 */ 9265 if (IS_MF(bp)) 9266 bp->port.need_hw_lock = 1; 9267 else 9268 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, 9269 bp->common.shmem_base, 9270 bp->common.shmem2_base); 9271} 9272 9273#ifdef BCM_CNIC 9274void bnx2x_get_iscsi_info(struct bnx2x *bp) 9275{ 9276 int port = BP_PORT(bp); 9277 9278 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9279 drv_lic_key[port].max_iscsi_conn); 9280 9281 /* Get the number of maximum allowed iSCSI connections */ 9282 bp->cnic_eth_dev.max_iscsi_conn = 9283 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> 9284 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; 9285 9286 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", 9287 bp->cnic_eth_dev.max_iscsi_conn); 9288 9289 /* 9290 * If maximum allowed number of connections is zero - 9291 * disable the feature. 9292 */ 9293 if (!bp->cnic_eth_dev.max_iscsi_conn) 9294 bp->flags |= NO_ISCSI_FLAG; 9295} 9296 9297static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp) 9298{ 9299 int port = BP_PORT(bp); 9300 int func = BP_ABS_FUNC(bp); 9301 9302 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9303 drv_lic_key[port].max_fcoe_conn); 9304 9305 /* Get the number of maximum allowed FCoE connections */ 9306 bp->cnic_eth_dev.max_fcoe_conn = 9307 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> 9308 BNX2X_MAX_FCOE_INIT_CONN_SHIFT; 9309 9310 /* Read the WWN: */ 9311 if (!IS_MF(bp)) { 9312 /* Port info */ 9313 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9314 SHMEM_RD(bp, 9315 dev_info.port_hw_config[port]. 9316 fcoe_wwn_port_name_upper); 9317 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9318 SHMEM_RD(bp, 9319 dev_info.port_hw_config[port]. 9320 fcoe_wwn_port_name_lower); 9321 9322 /* Node info */ 9323 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9324 SHMEM_RD(bp, 9325 dev_info.port_hw_config[port]. 9326 fcoe_wwn_node_name_upper); 9327 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9328 SHMEM_RD(bp, 9329 dev_info.port_hw_config[port]. 9330 fcoe_wwn_node_name_lower); 9331 } else if (!IS_MF_SD(bp)) { 9332 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9333 9334 /* 9335 * Read the WWN info only if the FCoE feature is enabled for 9336 * this function. 9337 */ 9338 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9339 /* Port info */ 9340 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9341 MF_CFG_RD(bp, func_ext_config[func]. 9342 fcoe_wwn_port_name_upper); 9343 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9344 MF_CFG_RD(bp, func_ext_config[func]. 9345 fcoe_wwn_port_name_lower); 9346 9347 /* Node info */ 9348 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9349 MF_CFG_RD(bp, func_ext_config[func]. 9350 fcoe_wwn_node_name_upper); 9351 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9352 MF_CFG_RD(bp, func_ext_config[func]. 9353 fcoe_wwn_node_name_lower); 9354 } 9355 } 9356 9357 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); 9358 9359 /* 9360 * If maximum allowed number of connections is zero - 9361 * disable the feature. 9362 */ 9363 if (!bp->cnic_eth_dev.max_fcoe_conn) 9364 bp->flags |= NO_FCOE_FLAG; 9365} 9366 9367static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) 9368{ 9369 /* 9370 * iSCSI may be dynamically disabled but reading 9371 * info here we will decrease memory usage by driver 9372 * if the feature is disabled for good 9373 */ 9374 bnx2x_get_iscsi_info(bp); 9375 bnx2x_get_fcoe_info(bp); 9376} 9377#endif 9378 9379static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) 9380{ 9381 u32 val, val2; 9382 int func = BP_ABS_FUNC(bp); 9383 int port = BP_PORT(bp); 9384#ifdef BCM_CNIC 9385 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; 9386 u8 *fip_mac = bp->fip_mac; 9387#endif 9388 9389 /* Zero primary MAC configuration */ 9390 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9391 9392 if (BP_NOMCP(bp)) { 9393 BNX2X_ERROR("warning: random MAC workaround active\n"); 9394 random_ether_addr(bp->dev->dev_addr); 9395 } else if (IS_MF(bp)) { 9396 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 9397 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); 9398 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && 9399 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) 9400 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9401 9402#ifdef BCM_CNIC 9403 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or 9404 * FCoE MAC then the appropriate feature should be disabled. 9405 */ 9406 if (IS_MF_SI(bp)) { 9407 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9408 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 9409 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9410 iscsi_mac_addr_upper); 9411 val = MF_CFG_RD(bp, func_ext_config[func]. 9412 iscsi_mac_addr_lower); 9413 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9414 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9415 iscsi_mac); 9416 } else 9417 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 9418 9419 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9420 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9421 fcoe_mac_addr_upper); 9422 val = MF_CFG_RD(bp, func_ext_config[func]. 9423 fcoe_mac_addr_lower); 9424 bnx2x_set_mac_buf(fip_mac, val, val2); 9425 BNX2X_DEV_INFO("Read FCoE L2 MAC to %pM\n", 9426 fip_mac); 9427 9428 } else 9429 bp->flags |= NO_FCOE_FLAG; 9430 } 9431#endif 9432 } else { 9433 /* in SF read MACs from port configuration */ 9434 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 9435 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 9436 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9437 9438#ifdef BCM_CNIC 9439 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9440 iscsi_mac_upper); 9441 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9442 iscsi_mac_lower); 9443 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9444 9445 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9446 fcoe_fip_mac_upper); 9447 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9448 fcoe_fip_mac_lower); 9449 bnx2x_set_mac_buf(fip_mac, val, val2); 9450#endif 9451 } 9452 9453 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 9454 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); 9455 9456#ifdef BCM_CNIC 9457 /* Set the FCoE MAC in MF_SD mode */ 9458 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp)) 9459 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); 9460 9461 /* Disable iSCSI if MAC configuration is 9462 * invalid. 9463 */ 9464 if (!is_valid_ether_addr(iscsi_mac)) { 9465 bp->flags |= NO_ISCSI_FLAG; 9466 memset(iscsi_mac, 0, ETH_ALEN); 9467 } 9468 9469 /* Disable FCoE if MAC configuration is 9470 * invalid. 9471 */ 9472 if (!is_valid_ether_addr(fip_mac)) { 9473 bp->flags |= NO_FCOE_FLAG; 9474 memset(bp->fip_mac, 0, ETH_ALEN); 9475 } 9476#endif 9477 9478 if (!is_valid_ether_addr(bp->dev->dev_addr)) 9479 dev_err(&bp->pdev->dev, 9480 "bad Ethernet MAC address configuration: " 9481 "%pM, change it manually before bringing up " 9482 "the appropriate network interface\n", 9483 bp->dev->dev_addr); 9484} 9485 9486static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) 9487{ 9488 int /*abs*/func = BP_ABS_FUNC(bp); 9489 int vn; 9490 u32 val = 0; 9491 int rc = 0; 9492 9493 bnx2x_get_common_hwinfo(bp); 9494 9495 /* 9496 * initialize IGU parameters 9497 */ 9498 if (CHIP_IS_E1x(bp)) { 9499 bp->common.int_block = INT_BLOCK_HC; 9500 9501 bp->igu_dsb_id = DEF_SB_IGU_ID; 9502 bp->igu_base_sb = 0; 9503 } else { 9504 bp->common.int_block = INT_BLOCK_IGU; 9505 9506 /* do not allow device reset during IGU info preocessing */ 9507 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9508 9509 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 9510 9511 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9512 int tout = 5000; 9513 9514 BNX2X_DEV_INFO("FORCING Normal Mode\n"); 9515 9516 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 9517 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); 9518 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); 9519 9520 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9521 tout--; 9522 usleep_range(1000, 1000); 9523 } 9524 9525 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9526 dev_err(&bp->pdev->dev, 9527 "FORCING Normal Mode failed!!!\n"); 9528 return -EPERM; 9529 } 9530 } 9531 9532 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9533 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); 9534 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; 9535 } else 9536 BNX2X_DEV_INFO("IGU Normal Mode\n"); 9537 9538 bnx2x_get_igu_cam_info(bp); 9539 9540 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9541 } 9542 9543 /* 9544 * set base FW non-default (fast path) status block id, this value is 9545 * used to initialize the fw_sb_id saved on the fp/queue structure to 9546 * determine the id used by the FW. 9547 */ 9548 if (CHIP_IS_E1x(bp)) 9549 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); 9550 else /* 9551 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of 9552 * the same queue are indicated on the same IGU SB). So we prefer 9553 * FW and IGU SBs to be the same value. 9554 */ 9555 bp->base_fw_ndsb = bp->igu_base_sb; 9556 9557 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" 9558 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, 9559 bp->igu_sb_cnt, bp->base_fw_ndsb); 9560 9561 /* 9562 * Initialize MF configuration 9563 */ 9564 9565 bp->mf_ov = 0; 9566 bp->mf_mode = 0; 9567 vn = BP_VN(bp); 9568 9569 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 9570 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 9571 bp->common.shmem2_base, SHMEM2_RD(bp, size), 9572 (u32)offsetof(struct shmem2_region, mf_cfg_addr)); 9573 9574 if (SHMEM2_HAS(bp, mf_cfg_addr)) 9575 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); 9576 else 9577 bp->common.mf_cfg_base = bp->common.shmem_base + 9578 offsetof(struct shmem_region, func_mb) + 9579 E1H_FUNC_MAX * sizeof(struct drv_func_mb); 9580 /* 9581 * get mf configuration: 9582 * 1. existence of MF configuration 9583 * 2. MAC address must be legal (check only upper bytes) 9584 * for Switch-Independent mode; 9585 * OVLAN must be legal for Switch-Dependent mode 9586 * 3. SF_MODE configures specific MF mode 9587 */ 9588 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9589 /* get mf configuration */ 9590 val = SHMEM_RD(bp, 9591 dev_info.shared_feature_config.config); 9592 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; 9593 9594 switch (val) { 9595 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 9596 val = MF_CFG_RD(bp, func_mf_config[func]. 9597 mac_upper); 9598 /* check for legal mac (upper bytes)*/ 9599 if (val != 0xffff) { 9600 bp->mf_mode = MULTI_FUNCTION_SI; 9601 bp->mf_config[vn] = MF_CFG_RD(bp, 9602 func_mf_config[func].config); 9603 } else 9604 BNX2X_DEV_INFO("illegal MAC address " 9605 "for SI\n"); 9606 break; 9607 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 9608 /* get OV configuration */ 9609 val = MF_CFG_RD(bp, 9610 func_mf_config[FUNC_0].e1hov_tag); 9611 val &= FUNC_MF_CFG_E1HOV_TAG_MASK; 9612 9613 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9614 bp->mf_mode = MULTI_FUNCTION_SD; 9615 bp->mf_config[vn] = MF_CFG_RD(bp, 9616 func_mf_config[func].config); 9617 } else 9618 BNX2X_DEV_INFO("illegal OV for SD\n"); 9619 break; 9620 default: 9621 /* Unknown configuration: reset mf_config */ 9622 bp->mf_config[vn] = 0; 9623 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val); 9624 } 9625 } 9626 9627 BNX2X_DEV_INFO("%s function mode\n", 9628 IS_MF(bp) ? "multi" : "single"); 9629 9630 switch (bp->mf_mode) { 9631 case MULTI_FUNCTION_SD: 9632 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 9633 FUNC_MF_CFG_E1HOV_TAG_MASK; 9634 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9635 bp->mf_ov = val; 9636 bp->path_has_ovlan = true; 9637 9638 BNX2X_DEV_INFO("MF OV for func %d is %d " 9639 "(0x%04x)\n", func, bp->mf_ov, 9640 bp->mf_ov); 9641 } else { 9642 dev_err(&bp->pdev->dev, 9643 "No valid MF OV for func %d, " 9644 "aborting\n", func); 9645 return -EPERM; 9646 } 9647 break; 9648 case MULTI_FUNCTION_SI: 9649 BNX2X_DEV_INFO("func %d is in MF " 9650 "switch-independent mode\n", func); 9651 break; 9652 default: 9653 if (vn) { 9654 dev_err(&bp->pdev->dev, 9655 "VN %d is in a single function mode, " 9656 "aborting\n", vn); 9657 return -EPERM; 9658 } 9659 break; 9660 } 9661 9662 /* check if other port on the path needs ovlan: 9663 * Since MF configuration is shared between ports 9664 * Possible mixed modes are only 9665 * {SF, SI} {SF, SD} {SD, SF} {SI, SF} 9666 */ 9667 if (CHIP_MODE_IS_4_PORT(bp) && 9668 !bp->path_has_ovlan && 9669 !IS_MF(bp) && 9670 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9671 u8 other_port = !BP_PORT(bp); 9672 u8 other_func = BP_PATH(bp) + 2*other_port; 9673 val = MF_CFG_RD(bp, 9674 func_mf_config[other_func].e1hov_tag); 9675 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) 9676 bp->path_has_ovlan = true; 9677 } 9678 } 9679 9680 /* adjust igu_sb_cnt to MF for E1x */ 9681 if (CHIP_IS_E1x(bp) && IS_MF(bp)) 9682 bp->igu_sb_cnt /= E1HVN_MAX; 9683 9684 /* port info */ 9685 bnx2x_get_port_hwinfo(bp); 9686 9687 /* Get MAC addresses */ 9688 bnx2x_get_mac_hwinfo(bp); 9689 9690#ifdef BCM_CNIC 9691 bnx2x_get_cnic_info(bp); 9692#endif 9693 9694 /* Get current FW pulse sequence */ 9695 if (!BP_NOMCP(bp)) { 9696 int mb_idx = BP_FW_MB_IDX(bp); 9697 9698 bp->fw_drv_pulse_wr_seq = 9699 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) & 9700 DRV_PULSE_SEQ_MASK); 9701 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq); 9702 } 9703 9704 return rc; 9705} 9706 9707static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) 9708{ 9709 int cnt, i, block_end, rodi; 9710 char vpd_data[BNX2X_VPD_LEN+1]; 9711 char str_id_reg[VENDOR_ID_LEN+1]; 9712 char str_id_cap[VENDOR_ID_LEN+1]; 9713 u8 len; 9714 9715 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data); 9716 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); 9717 9718 if (cnt < BNX2X_VPD_LEN) 9719 goto out_not_found; 9720 9721 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN, 9722 PCI_VPD_LRDT_RO_DATA); 9723 if (i < 0) 9724 goto out_not_found; 9725 9726 9727 block_end = i + PCI_VPD_LRDT_TAG_SIZE + 9728 pci_vpd_lrdt_size(&vpd_data[i]); 9729 9730 i += PCI_VPD_LRDT_TAG_SIZE; 9731 9732 if (block_end > BNX2X_VPD_LEN) 9733 goto out_not_found; 9734 9735 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 9736 PCI_VPD_RO_KEYWORD_MFR_ID); 9737 if (rodi < 0) 9738 goto out_not_found; 9739 9740 len = pci_vpd_info_field_size(&vpd_data[rodi]); 9741 9742 if (len != VENDOR_ID_LEN) 9743 goto out_not_found; 9744 9745 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 9746 9747 /* vendor specific info */ 9748 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); 9749 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); 9750 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || 9751 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { 9752 9753 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 9754 PCI_VPD_RO_KEYWORD_VENDOR0); 9755 if (rodi >= 0) { 9756 len = pci_vpd_info_field_size(&vpd_data[rodi]); 9757 9758 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 9759 9760 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { 9761 memcpy(bp->fw_ver, &vpd_data[rodi], len); 9762 bp->fw_ver[len] = ' '; 9763 } 9764 } 9765 return; 9766 } 9767out_not_found: 9768 return; 9769} 9770 9771static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) 9772{ 9773 u32 flags = 0; 9774 9775 if (CHIP_REV_IS_FPGA(bp)) 9776 SET_FLAGS(flags, MODE_FPGA); 9777 else if (CHIP_REV_IS_EMUL(bp)) 9778 SET_FLAGS(flags, MODE_EMUL); 9779 else 9780 SET_FLAGS(flags, MODE_ASIC); 9781 9782 if (CHIP_MODE_IS_4_PORT(bp)) 9783 SET_FLAGS(flags, MODE_PORT4); 9784 else 9785 SET_FLAGS(flags, MODE_PORT2); 9786 9787 if (CHIP_IS_E2(bp)) 9788 SET_FLAGS(flags, MODE_E2); 9789 else if (CHIP_IS_E3(bp)) { 9790 SET_FLAGS(flags, MODE_E3); 9791 if (CHIP_REV(bp) == CHIP_REV_Ax) 9792 SET_FLAGS(flags, MODE_E3_A0); 9793 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ 9794 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 9795 } 9796 9797 if (IS_MF(bp)) { 9798 SET_FLAGS(flags, MODE_MF); 9799 switch (bp->mf_mode) { 9800 case MULTI_FUNCTION_SD: 9801 SET_FLAGS(flags, MODE_MF_SD); 9802 break; 9803 case MULTI_FUNCTION_SI: 9804 SET_FLAGS(flags, MODE_MF_SI); 9805 break; 9806 } 9807 } else 9808 SET_FLAGS(flags, MODE_SF); 9809 9810#if defined(__LITTLE_ENDIAN) 9811 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 9812#else /*(__BIG_ENDIAN)*/ 9813 SET_FLAGS(flags, MODE_BIG_ENDIAN); 9814#endif 9815 INIT_MODE_FLAGS(bp) = flags; 9816} 9817 9818static int __devinit bnx2x_init_bp(struct bnx2x *bp) 9819{ 9820 int func; 9821 int timer_interval; 9822 int rc; 9823 9824 mutex_init(&bp->port.phy_mutex); 9825 mutex_init(&bp->fw_mb_mutex); 9826 spin_lock_init(&bp->stats_lock); 9827#ifdef BCM_CNIC 9828 mutex_init(&bp->cnic_mutex); 9829#endif 9830 9831 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); 9832 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); 9833 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); 9834 rc = bnx2x_get_hwinfo(bp); 9835 if (rc) 9836 return rc; 9837 9838 bnx2x_set_modes_bitmap(bp); 9839 9840 rc = bnx2x_alloc_mem_bp(bp); 9841 if (rc) 9842 return rc; 9843 9844 bnx2x_read_fwinfo(bp); 9845 9846 func = BP_FUNC(bp); 9847 9848 /* need to reset chip if undi was active */ 9849 if (!BP_NOMCP(bp)) 9850 bnx2x_undi_unload(bp); 9851 9852 /* init fw_seq after undi_unload! */ 9853 if (!BP_NOMCP(bp)) { 9854 bp->fw_seq = 9855 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 9856 DRV_MSG_SEQ_NUMBER_MASK); 9857 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 9858 } 9859 9860 if (CHIP_REV_IS_FPGA(bp)) 9861 dev_err(&bp->pdev->dev, "FPGA detected\n"); 9862 9863 if (BP_NOMCP(bp) && (func == 0)) 9864 dev_err(&bp->pdev->dev, "MCP disabled, " 9865 "must load devices in order!\n"); 9866 9867 bp->multi_mode = multi_mode; 9868 9869 /* Set TPA flags */ 9870 if (disable_tpa) { 9871 bp->flags &= ~TPA_ENABLE_FLAG; 9872 bp->dev->features &= ~NETIF_F_LRO; 9873 } else { 9874 bp->flags |= TPA_ENABLE_FLAG; 9875 bp->dev->features |= NETIF_F_LRO; 9876 } 9877 bp->disable_tpa = disable_tpa; 9878 9879 if (CHIP_IS_E1(bp)) 9880 bp->dropless_fc = 0; 9881 else 9882 bp->dropless_fc = dropless_fc; 9883 9884 bp->mrrs = mrrs; 9885 9886 bp->tx_ring_size = MAX_TX_AVAIL; 9887 9888 /* make sure that the numbers are in the right granularity */ 9889 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; 9890 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; 9891 9892 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ); 9893 bp->current_interval = (poll ? poll : timer_interval); 9894 9895 init_timer(&bp->timer); 9896 bp->timer.expires = jiffies + bp->current_interval; 9897 bp->timer.data = (unsigned long) bp; 9898 bp->timer.function = bnx2x_timer; 9899 9900 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); 9901 bnx2x_dcbx_init_params(bp); 9902 9903#ifdef BCM_CNIC 9904 if (CHIP_IS_E1x(bp)) 9905 bp->cnic_base_cl_id = FP_SB_MAX_E1x; 9906 else 9907 bp->cnic_base_cl_id = FP_SB_MAX_E2; 9908#endif 9909 9910 /* multiple tx priority */ 9911 if (CHIP_IS_E1x(bp)) 9912 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; 9913 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) 9914 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; 9915 if (CHIP_IS_E3B0(bp)) 9916 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; 9917 9918 return rc; 9919} 9920 9921 9922/**************************************************************************** 9923* General service functions 9924****************************************************************************/ 9925 9926/* 9927 * net_device service functions 9928 */ 9929 9930/* called with rtnl_lock */ 9931static int bnx2x_open(struct net_device *dev) 9932{ 9933 struct bnx2x *bp = netdev_priv(dev); 9934 bool global = false; 9935 int other_engine = BP_PATH(bp) ? 0 : 1; 9936 u32 other_load_counter, load_counter; 9937 9938 netif_carrier_off(dev); 9939 9940 bnx2x_set_power_state(bp, PCI_D0); 9941 9942 other_load_counter = bnx2x_get_load_cnt(bp, other_engine); 9943 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp)); 9944 9945 /* 9946 * If parity had happen during the unload, then attentions 9947 * and/or RECOVERY_IN_PROGRES may still be set. In this case we 9948 * want the first function loaded on the current engine to 9949 * complete the recovery. 9950 */ 9951 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 9952 bnx2x_chk_parity_attn(bp, &global, true)) 9953 do { 9954 /* 9955 * If there are attentions and they are in a global 9956 * blocks, set the GLOBAL_RESET bit regardless whether 9957 * it will be this function that will complete the 9958 * recovery or not. 9959 */ 9960 if (global) 9961 bnx2x_set_reset_global(bp); 9962 9963 /* 9964 * Only the first function on the current engine should 9965 * try to recover in open. In case of attentions in 9966 * global blocks only the first in the chip should try 9967 * to recover. 9968 */ 9969 if ((!load_counter && 9970 (!global || !other_load_counter)) && 9971 bnx2x_trylock_leader_lock(bp) && 9972 !bnx2x_leader_reset(bp)) { 9973 netdev_info(bp->dev, "Recovered in open\n"); 9974 break; 9975 } 9976 9977 /* recovery has failed... */ 9978 bnx2x_set_power_state(bp, PCI_D3hot); 9979 bp->recovery_state = BNX2X_RECOVERY_FAILED; 9980 9981 netdev_err(bp->dev, "Recovery flow hasn't been properly" 9982 " completed yet. Try again later. If u still see this" 9983 " message after a few retries then power cycle is" 9984 " required.\n"); 9985 9986 return -EAGAIN; 9987 } while (0); 9988 9989 bp->recovery_state = BNX2X_RECOVERY_DONE; 9990 return bnx2x_nic_load(bp, LOAD_OPEN); 9991} 9992 9993/* called with rtnl_lock */ 9994int bnx2x_close(struct net_device *dev) 9995{ 9996 struct bnx2x *bp = netdev_priv(dev); 9997 9998 /* Unload the driver, release IRQs */ 9999 bnx2x_nic_unload(bp, UNLOAD_CLOSE); 10000 10001 /* Power off */ 10002 bnx2x_set_power_state(bp, PCI_D3hot); 10003 10004 return 0; 10005} 10006 10007static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp, 10008 struct bnx2x_mcast_ramrod_params *p) 10009{ 10010 int mc_count = netdev_mc_count(bp->dev); 10011 struct bnx2x_mcast_list_elem *mc_mac = 10012 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); 10013 struct netdev_hw_addr *ha; 10014 10015 if (!mc_mac) 10016 return -ENOMEM; 10017 10018 INIT_LIST_HEAD(&p->mcast_list); 10019 10020 netdev_for_each_mc_addr(ha, bp->dev) { 10021 mc_mac->mac = bnx2x_mc_addr(ha); 10022 list_add_tail(&mc_mac->link, &p->mcast_list); 10023 mc_mac++; 10024 } 10025 10026 p->mcast_list_len = mc_count; 10027 10028 return 0; 10029} 10030 10031static inline void bnx2x_free_mcast_macs_list( 10032 struct bnx2x_mcast_ramrod_params *p) 10033{ 10034 struct bnx2x_mcast_list_elem *mc_mac = 10035 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, 10036 link); 10037 10038 WARN_ON(!mc_mac); 10039 kfree(mc_mac); 10040} 10041 10042/** 10043 * bnx2x_set_uc_list - configure a new unicast MACs list. 10044 * 10045 * @bp: driver handle 10046 * 10047 * We will use zero (0) as a MAC type for these MACs. 10048 */ 10049static inline int bnx2x_set_uc_list(struct bnx2x *bp) 10050{ 10051 int rc; 10052 struct net_device *dev = bp->dev; 10053 struct netdev_hw_addr *ha; 10054 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj; 10055 unsigned long ramrod_flags = 0; 10056 10057 /* First schedule a cleanup up of old configuration */ 10058 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); 10059 if (rc < 0) { 10060 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); 10061 return rc; 10062 } 10063 10064 netdev_for_each_uc_addr(ha, dev) { 10065 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, 10066 BNX2X_UC_LIST_MAC, &ramrod_flags); 10067 if (rc < 0) { 10068 BNX2X_ERR("Failed to schedule ADD operations: %d\n", 10069 rc); 10070 return rc; 10071 } 10072 } 10073 10074 /* Execute the pending commands */ 10075 __set_bit(RAMROD_CONT, &ramrod_flags); 10076 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, 10077 BNX2X_UC_LIST_MAC, &ramrod_flags); 10078} 10079 10080static inline int bnx2x_set_mc_list(struct bnx2x *bp) 10081{ 10082 struct net_device *dev = bp->dev; 10083 struct bnx2x_mcast_ramrod_params rparam = {0}; 10084 int rc = 0; 10085 10086 rparam.mcast_obj = &bp->mcast_obj; 10087 10088 /* first, clear all configured multicast MACs */ 10089 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 10090 if (rc < 0) { 10091 BNX2X_ERR("Failed to clear multicast " 10092 "configuration: %d\n", rc); 10093 return rc; 10094 } 10095 10096 /* then, configure a new MACs list */ 10097 if (netdev_mc_count(dev)) { 10098 rc = bnx2x_init_mcast_macs_list(bp, &rparam); 10099 if (rc) { 10100 BNX2X_ERR("Failed to create multicast MACs " 10101 "list: %d\n", rc); 10102 return rc; 10103 } 10104 10105 /* Now add the new MACs */ 10106 rc = bnx2x_config_mcast(bp, &rparam, 10107 BNX2X_MCAST_CMD_ADD); 10108 if (rc < 0) 10109 BNX2X_ERR("Failed to set a new multicast " 10110 "configuration: %d\n", rc); 10111 10112 bnx2x_free_mcast_macs_list(&rparam); 10113 } 10114 10115 return rc; 10116} 10117 10118 10119/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ 10120void bnx2x_set_rx_mode(struct net_device *dev) 10121{ 10122 struct bnx2x *bp = netdev_priv(dev); 10123 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 10124 10125 if (bp->state != BNX2X_STATE_OPEN) { 10126 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 10127 return; 10128 } 10129 10130 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); 10131 10132 if (dev->flags & IFF_PROMISC) 10133 rx_mode = BNX2X_RX_MODE_PROMISC; 10134 else if ((dev->flags & IFF_ALLMULTI) || 10135 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && 10136 CHIP_IS_E1(bp))) 10137 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10138 else { 10139 /* some multicasts */ 10140 if (bnx2x_set_mc_list(bp) < 0) 10141 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10142 10143 if (bnx2x_set_uc_list(bp) < 0) 10144 rx_mode = BNX2X_RX_MODE_PROMISC; 10145 } 10146 10147 bp->rx_mode = rx_mode; 10148 10149 /* Schedule the rx_mode command */ 10150 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { 10151 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 10152 return; 10153 } 10154 10155 bnx2x_set_storm_rx_mode(bp); 10156} 10157 10158/* called with rtnl_lock */ 10159static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 10160 int devad, u16 addr) 10161{ 10162 struct bnx2x *bp = netdev_priv(netdev); 10163 u16 value; 10164 int rc; 10165 10166 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 10167 prtad, devad, addr); 10168 10169 /* The HW expects different devad if CL22 is used */ 10170 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10171 10172 bnx2x_acquire_phy_lock(bp); 10173 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); 10174 bnx2x_release_phy_lock(bp); 10175 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 10176 10177 if (!rc) 10178 rc = value; 10179 return rc; 10180} 10181 10182/* called with rtnl_lock */ 10183static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, 10184 u16 addr, u16 value) 10185{ 10186 struct bnx2x *bp = netdev_priv(netdev); 10187 int rc; 10188 10189 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x," 10190 " value 0x%x\n", prtad, devad, addr, value); 10191 10192 /* The HW expects different devad if CL22 is used */ 10193 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10194 10195 bnx2x_acquire_phy_lock(bp); 10196 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); 10197 bnx2x_release_phy_lock(bp); 10198 return rc; 10199} 10200 10201/* called with rtnl_lock */ 10202static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 10203{ 10204 struct bnx2x *bp = netdev_priv(dev); 10205 struct mii_ioctl_data *mdio = if_mii(ifr); 10206 10207 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", 10208 mdio->phy_id, mdio->reg_num, mdio->val_in); 10209 10210 if (!netif_running(dev)) 10211 return -EAGAIN; 10212 10213 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); 10214} 10215 10216#ifdef CONFIG_NET_POLL_CONTROLLER 10217static void poll_bnx2x(struct net_device *dev) 10218{ 10219 struct bnx2x *bp = netdev_priv(dev); 10220 10221 disable_irq(bp->pdev->irq); 10222 bnx2x_interrupt(bp->pdev->irq, dev); 10223 enable_irq(bp->pdev->irq); 10224} 10225#endif 10226 10227static const struct net_device_ops bnx2x_netdev_ops = { 10228 .ndo_open = bnx2x_open, 10229 .ndo_stop = bnx2x_close, 10230 .ndo_start_xmit = bnx2x_start_xmit, 10231 .ndo_select_queue = bnx2x_select_queue, 10232 .ndo_set_rx_mode = bnx2x_set_rx_mode, 10233 .ndo_set_mac_address = bnx2x_change_mac_addr, 10234 .ndo_validate_addr = eth_validate_addr, 10235 .ndo_do_ioctl = bnx2x_ioctl, 10236 .ndo_change_mtu = bnx2x_change_mtu, 10237 .ndo_fix_features = bnx2x_fix_features, 10238 .ndo_set_features = bnx2x_set_features, 10239 .ndo_tx_timeout = bnx2x_tx_timeout, 10240#ifdef CONFIG_NET_POLL_CONTROLLER 10241 .ndo_poll_controller = poll_bnx2x, 10242#endif 10243 .ndo_setup_tc = bnx2x_setup_tc, 10244 10245#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) 10246 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, 10247#endif 10248}; 10249 10250static inline int bnx2x_set_coherency_mask(struct bnx2x *bp) 10251{ 10252 struct device *dev = &bp->pdev->dev; 10253 10254 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 10255 bp->flags |= USING_DAC_FLAG; 10256 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 10257 dev_err(dev, "dma_set_coherent_mask failed, " 10258 "aborting\n"); 10259 return -EIO; 10260 } 10261 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 10262 dev_err(dev, "System does not support DMA, aborting\n"); 10263 return -EIO; 10264 } 10265 10266 return 0; 10267} 10268 10269static int __devinit bnx2x_init_dev(struct pci_dev *pdev, 10270 struct net_device *dev, 10271 unsigned long board_type) 10272{ 10273 struct bnx2x *bp; 10274 int rc; 10275 10276 SET_NETDEV_DEV(dev, &pdev->dev); 10277 bp = netdev_priv(dev); 10278 10279 bp->dev = dev; 10280 bp->pdev = pdev; 10281 bp->flags = 0; 10282 bp->pf_num = PCI_FUNC(pdev->devfn); 10283 10284 rc = pci_enable_device(pdev); 10285 if (rc) { 10286 dev_err(&bp->pdev->dev, 10287 "Cannot enable PCI device, aborting\n"); 10288 goto err_out; 10289 } 10290 10291 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 10292 dev_err(&bp->pdev->dev, 10293 "Cannot find PCI device base address, aborting\n"); 10294 rc = -ENODEV; 10295 goto err_out_disable; 10296 } 10297 10298 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 10299 dev_err(&bp->pdev->dev, "Cannot find second PCI device" 10300 " base address, aborting\n"); 10301 rc = -ENODEV; 10302 goto err_out_disable; 10303 } 10304 10305 if (atomic_read(&pdev->enable_cnt) == 1) { 10306 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 10307 if (rc) { 10308 dev_err(&bp->pdev->dev, 10309 "Cannot obtain PCI resources, aborting\n"); 10310 goto err_out_disable; 10311 } 10312 10313 pci_set_master(pdev); 10314 pci_save_state(pdev); 10315 } 10316 10317 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 10318 if (bp->pm_cap == 0) { 10319 dev_err(&bp->pdev->dev, 10320 "Cannot find power management capability, aborting\n"); 10321 rc = -EIO; 10322 goto err_out_release; 10323 } 10324 10325 if (!pci_is_pcie(pdev)) { 10326 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 10327 rc = -EIO; 10328 goto err_out_release; 10329 } 10330 10331 rc = bnx2x_set_coherency_mask(bp); 10332 if (rc) 10333 goto err_out_release; 10334 10335 dev->mem_start = pci_resource_start(pdev, 0); 10336 dev->base_addr = dev->mem_start; 10337 dev->mem_end = pci_resource_end(pdev, 0); 10338 10339 dev->irq = pdev->irq; 10340 10341 bp->regview = pci_ioremap_bar(pdev, 0); 10342 if (!bp->regview) { 10343 dev_err(&bp->pdev->dev, 10344 "Cannot map register space, aborting\n"); 10345 rc = -ENOMEM; 10346 goto err_out_release; 10347 } 10348 10349 bnx2x_set_power_state(bp, PCI_D0); 10350 10351 /* clean indirect addresses */ 10352 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 10353 PCICFG_VENDOR_ID_OFFSET); 10354 /* 10355 * Clean the following indirect addresses for all functions since it 10356 * is not used by the driver. 10357 */ 10358 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); 10359 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); 10360 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 10361 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 10362 10363 if (CHIP_IS_E1x(bp)) { 10364 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 10365 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 10366 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 10367 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); 10368 } 10369 10370 /* 10371 * Enable internal target-read (in case we are probed after PF FLR). 10372 * Must be done prior to any BAR read access. Only for 57712 and up 10373 */ 10374 if (board_type != BCM57710 && 10375 board_type != BCM57711 && 10376 board_type != BCM57711E) 10377 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 10378 10379 /* Reset the load counter */ 10380 bnx2x_clear_load_cnt(bp); 10381 10382 dev->watchdog_timeo = TX_TIMEOUT; 10383 10384 dev->netdev_ops = &bnx2x_netdev_ops; 10385 bnx2x_set_ethtool_ops(dev); 10386 10387 dev->priv_flags |= IFF_UNICAST_FLT; 10388 10389 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10390 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_LRO | 10391 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; 10392 10393 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10394 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 10395 10396 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; 10397 if (bp->flags & USING_DAC_FLAG) 10398 dev->features |= NETIF_F_HIGHDMA; 10399 10400 /* Add Loopback capability to the device */ 10401 dev->hw_features |= NETIF_F_LOOPBACK; 10402 10403#ifdef BCM_DCBNL 10404 dev->dcbnl_ops = &bnx2x_dcbnl_ops; 10405#endif 10406 10407 /* get_port_hwinfo() will set prtad and mmds properly */ 10408 bp->mdio.prtad = MDIO_PRTAD_NONE; 10409 bp->mdio.mmds = 0; 10410 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10411 bp->mdio.dev = dev; 10412 bp->mdio.mdio_read = bnx2x_mdio_read; 10413 bp->mdio.mdio_write = bnx2x_mdio_write; 10414 10415 return 0; 10416 10417err_out_release: 10418 if (atomic_read(&pdev->enable_cnt) == 1) 10419 pci_release_regions(pdev); 10420 10421err_out_disable: 10422 pci_disable_device(pdev); 10423 pci_set_drvdata(pdev, NULL); 10424 10425err_out: 10426 return rc; 10427} 10428 10429static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, 10430 int *width, int *speed) 10431{ 10432 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); 10433 10434 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; 10435 10436 /* return value of 1=2.5GHz 2=5GHz */ 10437 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; 10438} 10439 10440static int bnx2x_check_firmware(struct bnx2x *bp) 10441{ 10442 const struct firmware *firmware = bp->firmware; 10443 struct bnx2x_fw_file_hdr *fw_hdr; 10444 struct bnx2x_fw_file_section *sections; 10445 u32 offset, len, num_ops; 10446 u16 *ops_offsets; 10447 int i; 10448 const u8 *fw_ver; 10449 10450 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) 10451 return -EINVAL; 10452 10453 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 10454 sections = (struct bnx2x_fw_file_section *)fw_hdr; 10455 10456 /* Make sure none of the offsets and sizes make us read beyond 10457 * the end of the firmware data */ 10458 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { 10459 offset = be32_to_cpu(sections[i].offset); 10460 len = be32_to_cpu(sections[i].len); 10461 if (offset + len > firmware->size) { 10462 dev_err(&bp->pdev->dev, 10463 "Section %d length is out of bounds\n", i); 10464 return -EINVAL; 10465 } 10466 } 10467 10468 /* Likewise for the init_ops offsets */ 10469 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); 10470 ops_offsets = (u16 *)(firmware->data + offset); 10471 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); 10472 10473 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 10474 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 10475 dev_err(&bp->pdev->dev, 10476 "Section offset %d is out of bounds\n", i); 10477 return -EINVAL; 10478 } 10479 } 10480 10481 /* Check FW version */ 10482 offset = be32_to_cpu(fw_hdr->fw_version.offset); 10483 fw_ver = firmware->data + offset; 10484 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || 10485 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || 10486 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || 10487 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { 10488 dev_err(&bp->pdev->dev, 10489 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 10490 fw_ver[0], fw_ver[1], fw_ver[2], 10491 fw_ver[3], BCM_5710_FW_MAJOR_VERSION, 10492 BCM_5710_FW_MINOR_VERSION, 10493 BCM_5710_FW_REVISION_VERSION, 10494 BCM_5710_FW_ENGINEERING_VERSION); 10495 return -EINVAL; 10496 } 10497 10498 return 0; 10499} 10500 10501static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10502{ 10503 const __be32 *source = (const __be32 *)_source; 10504 u32 *target = (u32 *)_target; 10505 u32 i; 10506 10507 for (i = 0; i < n/4; i++) 10508 target[i] = be32_to_cpu(source[i]); 10509} 10510 10511/* 10512 Ops array is stored in the following format: 10513 {op(8bit), offset(24bit, big endian), data(32bit, big endian)} 10514 */ 10515static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) 10516{ 10517 const __be32 *source = (const __be32 *)_source; 10518 struct raw_op *target = (struct raw_op *)_target; 10519 u32 i, j, tmp; 10520 10521 for (i = 0, j = 0; i < n/8; i++, j += 2) { 10522 tmp = be32_to_cpu(source[j]); 10523 target[i].op = (tmp >> 24) & 0xff; 10524 target[i].offset = tmp & 0xffffff; 10525 target[i].raw_data = be32_to_cpu(source[j + 1]); 10526 } 10527} 10528 10529/** 10530 * IRO array is stored in the following format: 10531 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } 10532 */ 10533static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) 10534{ 10535 const __be32 *source = (const __be32 *)_source; 10536 struct iro *target = (struct iro *)_target; 10537 u32 i, j, tmp; 10538 10539 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { 10540 target[i].base = be32_to_cpu(source[j]); 10541 j++; 10542 tmp = be32_to_cpu(source[j]); 10543 target[i].m1 = (tmp >> 16) & 0xffff; 10544 target[i].m2 = tmp & 0xffff; 10545 j++; 10546 tmp = be32_to_cpu(source[j]); 10547 target[i].m3 = (tmp >> 16) & 0xffff; 10548 target[i].size = tmp & 0xffff; 10549 j++; 10550 } 10551} 10552 10553static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10554{ 10555 const __be16 *source = (const __be16 *)_source; 10556 u16 *target = (u16 *)_target; 10557 u32 i; 10558 10559 for (i = 0; i < n/2; i++) 10560 target[i] = be16_to_cpu(source[i]); 10561} 10562 10563#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ 10564do { \ 10565 u32 len = be32_to_cpu(fw_hdr->arr.len); \ 10566 bp->arr = kmalloc(len, GFP_KERNEL); \ 10567 if (!bp->arr) { \ 10568 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \ 10569 goto lbl; \ 10570 } \ 10571 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ 10572 (u8 *)bp->arr, len); \ 10573} while (0) 10574 10575int bnx2x_init_firmware(struct bnx2x *bp) 10576{ 10577 struct bnx2x_fw_file_hdr *fw_hdr; 10578 int rc; 10579 10580 10581 if (!bp->firmware) { 10582 const char *fw_file_name; 10583 10584 if (CHIP_IS_E1(bp)) 10585 fw_file_name = FW_FILE_NAME_E1; 10586 else if (CHIP_IS_E1H(bp)) 10587 fw_file_name = FW_FILE_NAME_E1H; 10588 else if (!CHIP_IS_E1x(bp)) 10589 fw_file_name = FW_FILE_NAME_E2; 10590 else { 10591 BNX2X_ERR("Unsupported chip revision\n"); 10592 return -EINVAL; 10593 } 10594 BNX2X_DEV_INFO("Loading %s\n", fw_file_name); 10595 10596 rc = request_firmware(&bp->firmware, fw_file_name, 10597 &bp->pdev->dev); 10598 if (rc) { 10599 BNX2X_ERR("Can't load firmware file %s\n", 10600 fw_file_name); 10601 goto request_firmware_exit; 10602 } 10603 10604 rc = bnx2x_check_firmware(bp); 10605 if (rc) { 10606 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); 10607 goto request_firmware_exit; 10608 } 10609 } 10610 10611 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; 10612 10613 /* Initialize the pointers to the init arrays */ 10614 /* Blob */ 10615 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); 10616 10617 /* Opcodes */ 10618 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); 10619 10620 /* Offsets */ 10621 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, 10622 be16_to_cpu_n); 10623 10624 /* STORMs firmware */ 10625 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10626 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); 10627 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + 10628 be32_to_cpu(fw_hdr->tsem_pram_data.offset); 10629 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10630 be32_to_cpu(fw_hdr->usem_int_table_data.offset); 10631 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + 10632 be32_to_cpu(fw_hdr->usem_pram_data.offset); 10633 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10634 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); 10635 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + 10636 be32_to_cpu(fw_hdr->xsem_pram_data.offset); 10637 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10638 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 10639 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 10640 be32_to_cpu(fw_hdr->csem_pram_data.offset); 10641 /* IRO */ 10642 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); 10643 10644 return 0; 10645 10646iro_alloc_err: 10647 kfree(bp->init_ops_offsets); 10648init_offsets_alloc_err: 10649 kfree(bp->init_ops); 10650init_ops_alloc_err: 10651 kfree(bp->init_data); 10652request_firmware_exit: 10653 release_firmware(bp->firmware); 10654 10655 return rc; 10656} 10657 10658static void bnx2x_release_firmware(struct bnx2x *bp) 10659{ 10660 kfree(bp->init_ops_offsets); 10661 kfree(bp->init_ops); 10662 kfree(bp->init_data); 10663 release_firmware(bp->firmware); 10664 bp->firmware = NULL; 10665} 10666 10667 10668static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { 10669 .init_hw_cmn_chip = bnx2x_init_hw_common_chip, 10670 .init_hw_cmn = bnx2x_init_hw_common, 10671 .init_hw_port = bnx2x_init_hw_port, 10672 .init_hw_func = bnx2x_init_hw_func, 10673 10674 .reset_hw_cmn = bnx2x_reset_common, 10675 .reset_hw_port = bnx2x_reset_port, 10676 .reset_hw_func = bnx2x_reset_func, 10677 10678 .gunzip_init = bnx2x_gunzip_init, 10679 .gunzip_end = bnx2x_gunzip_end, 10680 10681 .init_fw = bnx2x_init_firmware, 10682 .release_fw = bnx2x_release_firmware, 10683}; 10684 10685void bnx2x__init_func_obj(struct bnx2x *bp) 10686{ 10687 /* Prepare DMAE related driver resources */ 10688 bnx2x_setup_dmae(bp); 10689 10690 bnx2x_init_func_obj(bp, &bp->func_obj, 10691 bnx2x_sp(bp, func_rdata), 10692 bnx2x_sp_mapping(bp, func_rdata), 10693 &bnx2x_func_sp_drv); 10694} 10695 10696/* must be called after sriov-enable */ 10697static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp) 10698{ 10699 int cid_count = BNX2X_L2_CID_COUNT(bp); 10700 10701#ifdef BCM_CNIC 10702 cid_count += CNIC_CID_MAX; 10703#endif 10704 return roundup(cid_count, QM_CID_ROUND); 10705} 10706 10707/** 10708 * bnx2x_get_num_none_def_sbs - return the number of none default SBs 10709 * 10710 * @dev: pci device 10711 * 10712 */ 10713static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) 10714{ 10715 int pos; 10716 u16 control; 10717 10718 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 10719 10720 /* 10721 * If MSI-X is not supported - return number of SBs needed to support 10722 * one fast path queue: one FP queue + SB for CNIC 10723 */ 10724 if (!pos) 10725 return 1 + CNIC_PRESENT; 10726 10727 /* 10728 * The value in the PCI configuration space is the index of the last 10729 * entry, namely one less than the actual size of the table, which is 10730 * exactly what we want to return from this function: number of all SBs 10731 * without the default SB. 10732 */ 10733 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 10734 return control & PCI_MSIX_FLAGS_QSIZE; 10735} 10736 10737static int __devinit bnx2x_init_one(struct pci_dev *pdev, 10738 const struct pci_device_id *ent) 10739{ 10740 struct net_device *dev = NULL; 10741 struct bnx2x *bp; 10742 int pcie_width, pcie_speed; 10743 int rc, max_non_def_sbs; 10744 int rx_count, tx_count, rss_count; 10745 /* 10746 * An estimated maximum supported CoS number according to the chip 10747 * version. 10748 * We will try to roughly estimate the maximum number of CoSes this chip 10749 * may support in order to minimize the memory allocated for Tx 10750 * netdev_queue's. This number will be accurately calculated during the 10751 * initialization of bp->max_cos based on the chip versions AND chip 10752 * revision in the bnx2x_init_bp(). 10753 */ 10754 u8 max_cos_est = 0; 10755 10756 switch (ent->driver_data) { 10757 case BCM57710: 10758 case BCM57711: 10759 case BCM57711E: 10760 max_cos_est = BNX2X_MULTI_TX_COS_E1X; 10761 break; 10762 10763 case BCM57712: 10764 case BCM57712_MF: 10765 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; 10766 break; 10767 10768 case BCM57800: 10769 case BCM57800_MF: 10770 case BCM57810: 10771 case BCM57810_MF: 10772 case BCM57840: 10773 case BCM57840_MF: 10774 max_cos_est = BNX2X_MULTI_TX_COS_E3B0; 10775 break; 10776 10777 default: 10778 pr_err("Unknown board_type (%ld), aborting\n", 10779 ent->driver_data); 10780 return -ENODEV; 10781 } 10782 10783 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); 10784 10785 /* !!! FIXME !!! 10786 * Do not allow the maximum SB count to grow above 16 10787 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48. 10788 * We will use the FP_SB_MAX_E1x macro for this matter. 10789 */ 10790 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs); 10791 10792 WARN_ON(!max_non_def_sbs); 10793 10794 /* Maximum number of RSS queues: one IGU SB goes to CNIC */ 10795 rss_count = max_non_def_sbs - CNIC_PRESENT; 10796 10797 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ 10798 rx_count = rss_count + FCOE_PRESENT; 10799 10800 /* 10801 * Maximum number of netdev Tx queues: 10802 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 10803 */ 10804 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT; 10805 10806 /* dev zeroed in init_etherdev */ 10807 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); 10808 if (!dev) { 10809 dev_err(&pdev->dev, "Cannot allocate net device\n"); 10810 return -ENOMEM; 10811 } 10812 10813 bp = netdev_priv(dev); 10814 10815 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n", 10816 tx_count, rx_count); 10817 10818 bp->igu_sb_cnt = max_non_def_sbs; 10819 bp->msg_enable = debug; 10820 pci_set_drvdata(pdev, dev); 10821 10822 rc = bnx2x_init_dev(pdev, dev, ent->driver_data); 10823 if (rc < 0) { 10824 free_netdev(dev); 10825 return rc; 10826 } 10827 10828 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs); 10829 10830 rc = bnx2x_init_bp(bp); 10831 if (rc) 10832 goto init_one_exit; 10833 10834 /* 10835 * Map doorbels here as we need the real value of bp->max_cos which 10836 * is initialized in bnx2x_init_bp(). 10837 */ 10838 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), 10839 min_t(u64, BNX2X_DB_SIZE(bp), 10840 pci_resource_len(pdev, 2))); 10841 if (!bp->doorbells) { 10842 dev_err(&bp->pdev->dev, 10843 "Cannot map doorbell space, aborting\n"); 10844 rc = -ENOMEM; 10845 goto init_one_exit; 10846 } 10847 10848 /* calc qm_cid_count */ 10849 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); 10850 10851#ifdef BCM_CNIC 10852 /* disable FCOE L2 queue for E1x */ 10853 if (CHIP_IS_E1x(bp)) 10854 bp->flags |= NO_FCOE_FLAG; 10855 10856#endif 10857 10858 /* Configure interrupt mode: try to enable MSI-X/MSI if 10859 * needed, set bp->num_queues appropriately. 10860 */ 10861 bnx2x_set_int_mode(bp); 10862 10863 /* Add all NAPI objects */ 10864 bnx2x_add_all_napi(bp); 10865 10866 rc = register_netdev(dev); 10867 if (rc) { 10868 dev_err(&pdev->dev, "Cannot register net device\n"); 10869 goto init_one_exit; 10870 } 10871 10872#ifdef BCM_CNIC 10873 if (!NO_FCOE(bp)) { 10874 /* Add storage MAC address */ 10875 rtnl_lock(); 10876 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 10877 rtnl_unlock(); 10878 } 10879#endif 10880 10881 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); 10882 10883 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", 10884 board_info[ent->driver_data].name, 10885 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 10886 pcie_width, 10887 ((!CHIP_IS_E2(bp) && pcie_speed == 2) || 10888 (CHIP_IS_E2(bp) && pcie_speed == 1)) ? 10889 "5GHz (Gen2)" : "2.5GHz", 10890 dev->base_addr, bp->pdev->irq, dev->dev_addr); 10891 10892 return 0; 10893 10894init_one_exit: 10895 if (bp->regview) 10896 iounmap(bp->regview); 10897 10898 if (bp->doorbells) 10899 iounmap(bp->doorbells); 10900 10901 free_netdev(dev); 10902 10903 if (atomic_read(&pdev->enable_cnt) == 1) 10904 pci_release_regions(pdev); 10905 10906 pci_disable_device(pdev); 10907 pci_set_drvdata(pdev, NULL); 10908 10909 return rc; 10910} 10911 10912static void __devexit bnx2x_remove_one(struct pci_dev *pdev) 10913{ 10914 struct net_device *dev = pci_get_drvdata(pdev); 10915 struct bnx2x *bp; 10916 10917 if (!dev) { 10918 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); 10919 return; 10920 } 10921 bp = netdev_priv(dev); 10922 10923#ifdef BCM_CNIC 10924 /* Delete storage MAC address */ 10925 if (!NO_FCOE(bp)) { 10926 rtnl_lock(); 10927 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 10928 rtnl_unlock(); 10929 } 10930#endif 10931 10932#ifdef BCM_DCBNL 10933 /* Delete app tlvs from dcbnl */ 10934 bnx2x_dcbnl_update_applist(bp, true); 10935#endif 10936 10937 unregister_netdev(dev); 10938 10939 /* Delete all NAPI objects */ 10940 bnx2x_del_all_napi(bp); 10941 10942 /* Power on: we can't let PCI layer write to us while we are in D3 */ 10943 bnx2x_set_power_state(bp, PCI_D0); 10944 10945 /* Disable MSI/MSI-X */ 10946 bnx2x_disable_msi(bp); 10947 10948 /* Power off */ 10949 bnx2x_set_power_state(bp, PCI_D3hot); 10950 10951 /* Make sure RESET task is not scheduled before continuing */ 10952 cancel_delayed_work_sync(&bp->sp_rtnl_task); 10953 10954 if (bp->regview) 10955 iounmap(bp->regview); 10956 10957 if (bp->doorbells) 10958 iounmap(bp->doorbells); 10959 10960 bnx2x_release_firmware(bp); 10961 10962 bnx2x_free_mem_bp(bp); 10963 10964 free_netdev(dev); 10965 10966 if (atomic_read(&pdev->enable_cnt) == 1) 10967 pci_release_regions(pdev); 10968 10969 pci_disable_device(pdev); 10970 pci_set_drvdata(pdev, NULL); 10971} 10972 10973static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 10974{ 10975 int i; 10976 10977 bp->state = BNX2X_STATE_ERROR; 10978 10979 bp->rx_mode = BNX2X_RX_MODE_NONE; 10980 10981#ifdef BCM_CNIC 10982 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); 10983#endif 10984 /* Stop Tx */ 10985 bnx2x_tx_disable(bp); 10986 10987 bnx2x_netif_stop(bp, 0); 10988 10989 del_timer_sync(&bp->timer); 10990 10991 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 10992 10993 /* Release IRQs */ 10994 bnx2x_free_irq(bp); 10995 10996 /* Free SKBs, SGEs, TPA pool and driver internals */ 10997 bnx2x_free_skbs(bp); 10998 10999 for_each_rx_queue(bp, i) 11000 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 11001 11002 bnx2x_free_mem(bp); 11003 11004 bp->state = BNX2X_STATE_CLOSED; 11005 11006 netif_carrier_off(bp->dev); 11007 11008 return 0; 11009} 11010 11011static void bnx2x_eeh_recover(struct bnx2x *bp) 11012{ 11013 u32 val; 11014 11015 mutex_init(&bp->port.phy_mutex); 11016 11017 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 11018 bp->link_params.shmem_base = bp->common.shmem_base; 11019 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base); 11020 11021 if (!bp->common.shmem_base || 11022 (bp->common.shmem_base < 0xA0000) || 11023 (bp->common.shmem_base >= 0xC0000)) { 11024 BNX2X_DEV_INFO("MCP not active\n"); 11025 bp->flags |= NO_MCP_FLAG; 11026 return; 11027 } 11028 11029 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 11030 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11031 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11032 BNX2X_ERR("BAD MCP validity signature\n"); 11033 11034 if (!BP_NOMCP(bp)) { 11035 bp->fw_seq = 11036 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 11037 DRV_MSG_SEQ_NUMBER_MASK); 11038 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 11039 } 11040} 11041 11042/** 11043 * bnx2x_io_error_detected - called when PCI error is detected 11044 * @pdev: Pointer to PCI device 11045 * @state: The current pci connection state 11046 * 11047 * This function is called after a PCI bus error affecting 11048 * this device has been detected. 11049 */ 11050static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, 11051 pci_channel_state_t state) 11052{ 11053 struct net_device *dev = pci_get_drvdata(pdev); 11054 struct bnx2x *bp = netdev_priv(dev); 11055 11056 rtnl_lock(); 11057 11058 netif_device_detach(dev); 11059 11060 if (state == pci_channel_io_perm_failure) { 11061 rtnl_unlock(); 11062 return PCI_ERS_RESULT_DISCONNECT; 11063 } 11064 11065 if (netif_running(dev)) 11066 bnx2x_eeh_nic_unload(bp); 11067 11068 pci_disable_device(pdev); 11069 11070 rtnl_unlock(); 11071 11072 /* Request a slot reset */ 11073 return PCI_ERS_RESULT_NEED_RESET; 11074} 11075 11076/** 11077 * bnx2x_io_slot_reset - called after the PCI bus has been reset 11078 * @pdev: Pointer to PCI device 11079 * 11080 * Restart the card from scratch, as if from a cold-boot. 11081 */ 11082static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) 11083{ 11084 struct net_device *dev = pci_get_drvdata(pdev); 11085 struct bnx2x *bp = netdev_priv(dev); 11086 11087 rtnl_lock(); 11088 11089 if (pci_enable_device(pdev)) { 11090 dev_err(&pdev->dev, 11091 "Cannot re-enable PCI device after reset\n"); 11092 rtnl_unlock(); 11093 return PCI_ERS_RESULT_DISCONNECT; 11094 } 11095 11096 pci_set_master(pdev); 11097 pci_restore_state(pdev); 11098 11099 if (netif_running(dev)) 11100 bnx2x_set_power_state(bp, PCI_D0); 11101 11102 rtnl_unlock(); 11103 11104 return PCI_ERS_RESULT_RECOVERED; 11105} 11106 11107/** 11108 * bnx2x_io_resume - called when traffic can start flowing again 11109 * @pdev: Pointer to PCI device 11110 * 11111 * This callback is called when the error recovery driver tells us that 11112 * its OK to resume normal operation. 11113 */ 11114static void bnx2x_io_resume(struct pci_dev *pdev) 11115{ 11116 struct net_device *dev = pci_get_drvdata(pdev); 11117 struct bnx2x *bp = netdev_priv(dev); 11118 11119 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 11120 netdev_err(bp->dev, "Handling parity error recovery. " 11121 "Try again later\n"); 11122 return; 11123 } 11124 11125 rtnl_lock(); 11126 11127 bnx2x_eeh_recover(bp); 11128 11129 if (netif_running(dev)) 11130 bnx2x_nic_load(bp, LOAD_NORMAL); 11131 11132 netif_device_attach(dev); 11133 11134 rtnl_unlock(); 11135} 11136 11137static struct pci_error_handlers bnx2x_err_handler = { 11138 .error_detected = bnx2x_io_error_detected, 11139 .slot_reset = bnx2x_io_slot_reset, 11140 .resume = bnx2x_io_resume, 11141}; 11142 11143static struct pci_driver bnx2x_pci_driver = { 11144 .name = DRV_MODULE_NAME, 11145 .id_table = bnx2x_pci_tbl, 11146 .probe = bnx2x_init_one, 11147 .remove = __devexit_p(bnx2x_remove_one), 11148 .suspend = bnx2x_suspend, 11149 .resume = bnx2x_resume, 11150 .err_handler = &bnx2x_err_handler, 11151}; 11152 11153static int __init bnx2x_init(void) 11154{ 11155 int ret; 11156 11157 pr_info("%s", version); 11158 11159 bnx2x_wq = create_singlethread_workqueue("bnx2x"); 11160 if (bnx2x_wq == NULL) { 11161 pr_err("Cannot create workqueue\n"); 11162 return -ENOMEM; 11163 } 11164 11165 ret = pci_register_driver(&bnx2x_pci_driver); 11166 if (ret) { 11167 pr_err("Cannot register driver\n"); 11168 destroy_workqueue(bnx2x_wq); 11169 } 11170 return ret; 11171} 11172 11173static void __exit bnx2x_cleanup(void) 11174{ 11175 pci_unregister_driver(&bnx2x_pci_driver); 11176 11177 destroy_workqueue(bnx2x_wq); 11178} 11179 11180void bnx2x_notify_link_changed(struct bnx2x *bp) 11181{ 11182 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); 11183} 11184 11185module_init(bnx2x_init); 11186module_exit(bnx2x_cleanup); 11187 11188#ifdef BCM_CNIC 11189/** 11190 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). 11191 * 11192 * @bp: driver handle 11193 * @set: set or clear the CAM entry 11194 * 11195 * This function will wait until the ramdord completion returns. 11196 * Return 0 if success, -ENODEV if ramrod doesn't return. 11197 */ 11198static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) 11199{ 11200 unsigned long ramrod_flags = 0; 11201 11202 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 11203 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, 11204 &bp->iscsi_l2_mac_obj, true, 11205 BNX2X_ISCSI_ETH_MAC, &ramrod_flags); 11206} 11207 11208/* count denotes the number of new completions we have seen */ 11209static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) 11210{ 11211 struct eth_spe *spe; 11212 11213#ifdef BNX2X_STOP_ON_ERROR 11214 if (unlikely(bp->panic)) 11215 return; 11216#endif 11217 11218 spin_lock_bh(&bp->spq_lock); 11219 BUG_ON(bp->cnic_spq_pending < count); 11220 bp->cnic_spq_pending -= count; 11221 11222 11223 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { 11224 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) 11225 & SPE_HDR_CONN_TYPE) >> 11226 SPE_HDR_CONN_TYPE_SHIFT; 11227 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) 11228 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; 11229 11230 /* Set validation for iSCSI L2 client before sending SETUP 11231 * ramrod 11232 */ 11233 if (type == ETH_CONNECTION_TYPE) { 11234 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) 11235 bnx2x_set_ctx_validation(bp, &bp->context. 11236 vcxt[BNX2X_ISCSI_ETH_CID].eth, 11237 BNX2X_ISCSI_ETH_CID); 11238 } 11239 11240 /* 11241 * There may be not more than 8 L2, not more than 8 L5 SPEs 11242 * and in the air. We also check that number of outstanding 11243 * COMMON ramrods is not more than the EQ and SPQ can 11244 * accommodate. 11245 */ 11246 if (type == ETH_CONNECTION_TYPE) { 11247 if (!atomic_read(&bp->cq_spq_left)) 11248 break; 11249 else 11250 atomic_dec(&bp->cq_spq_left); 11251 } else if (type == NONE_CONNECTION_TYPE) { 11252 if (!atomic_read(&bp->eq_spq_left)) 11253 break; 11254 else 11255 atomic_dec(&bp->eq_spq_left); 11256 } else if ((type == ISCSI_CONNECTION_TYPE) || 11257 (type == FCOE_CONNECTION_TYPE)) { 11258 if (bp->cnic_spq_pending >= 11259 bp->cnic_eth_dev.max_kwqe_pending) 11260 break; 11261 else 11262 bp->cnic_spq_pending++; 11263 } else { 11264 BNX2X_ERR("Unknown SPE type: %d\n", type); 11265 bnx2x_panic(); 11266 break; 11267 } 11268 11269 spe = bnx2x_sp_get_next(bp); 11270 *spe = *bp->cnic_kwq_cons; 11271 11272 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n", 11273 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 11274 11275 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 11276 bp->cnic_kwq_cons = bp->cnic_kwq; 11277 else 11278 bp->cnic_kwq_cons++; 11279 } 11280 bnx2x_sp_prod_update(bp); 11281 spin_unlock_bh(&bp->spq_lock); 11282} 11283 11284static int bnx2x_cnic_sp_queue(struct net_device *dev, 11285 struct kwqe_16 *kwqes[], u32 count) 11286{ 11287 struct bnx2x *bp = netdev_priv(dev); 11288 int i; 11289 11290#ifdef BNX2X_STOP_ON_ERROR 11291 if (unlikely(bp->panic)) 11292 return -EIO; 11293#endif 11294 11295 spin_lock_bh(&bp->spq_lock); 11296 11297 for (i = 0; i < count; i++) { 11298 struct eth_spe *spe = (struct eth_spe *)kwqes[i]; 11299 11300 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) 11301 break; 11302 11303 *bp->cnic_kwq_prod = *spe; 11304 11305 bp->cnic_kwq_pending++; 11306 11307 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n", 11308 spe->hdr.conn_and_cmd_data, spe->hdr.type, 11309 spe->data.update_data_addr.hi, 11310 spe->data.update_data_addr.lo, 11311 bp->cnic_kwq_pending); 11312 11313 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 11314 bp->cnic_kwq_prod = bp->cnic_kwq; 11315 else 11316 bp->cnic_kwq_prod++; 11317 } 11318 11319 spin_unlock_bh(&bp->spq_lock); 11320 11321 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) 11322 bnx2x_cnic_sp_post(bp, 0); 11323 11324 return i; 11325} 11326 11327static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11328{ 11329 struct cnic_ops *c_ops; 11330 int rc = 0; 11331 11332 mutex_lock(&bp->cnic_mutex); 11333 c_ops = rcu_dereference_protected(bp->cnic_ops, 11334 lockdep_is_held(&bp->cnic_mutex)); 11335 if (c_ops) 11336 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11337 mutex_unlock(&bp->cnic_mutex); 11338 11339 return rc; 11340} 11341 11342static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11343{ 11344 struct cnic_ops *c_ops; 11345 int rc = 0; 11346 11347 rcu_read_lock(); 11348 c_ops = rcu_dereference(bp->cnic_ops); 11349 if (c_ops) 11350 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11351 rcu_read_unlock(); 11352 11353 return rc; 11354} 11355 11356/* 11357 * for commands that have no data 11358 */ 11359int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) 11360{ 11361 struct cnic_ctl_info ctl = {0}; 11362 11363 ctl.cmd = cmd; 11364 11365 return bnx2x_cnic_ctl_send(bp, &ctl); 11366} 11367 11368static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) 11369{ 11370 struct cnic_ctl_info ctl = {0}; 11371 11372 /* first we tell CNIC and only then we count this as a completion */ 11373 ctl.cmd = CNIC_CTL_COMPLETION_CMD; 11374 ctl.data.comp.cid = cid; 11375 ctl.data.comp.error = err; 11376 11377 bnx2x_cnic_ctl_send_bh(bp, &ctl); 11378 bnx2x_cnic_sp_post(bp, 0); 11379} 11380 11381 11382/* Called with netif_addr_lock_bh() taken. 11383 * Sets an rx_mode config for an iSCSI ETH client. 11384 * Doesn't block. 11385 * Completion should be checked outside. 11386 */ 11387static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) 11388{ 11389 unsigned long accept_flags = 0, ramrod_flags = 0; 11390 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11391 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; 11392 11393 if (start) { 11394 /* Start accepting on iSCSI L2 ring. Accept all multicasts 11395 * because it's the only way for UIO Queue to accept 11396 * multicasts (in non-promiscuous mode only one Queue per 11397 * function will receive multicast packets (leading in our 11398 * case). 11399 */ 11400 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); 11401 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); 11402 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); 11403 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 11404 11405 /* Clear STOP_PENDING bit if START is requested */ 11406 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); 11407 11408 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; 11409 } else 11410 /* Clear START_PENDING bit if STOP is requested */ 11411 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); 11412 11413 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 11414 set_bit(sched_state, &bp->sp_state); 11415 else { 11416 __set_bit(RAMROD_RX, &ramrod_flags); 11417 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, 11418 ramrod_flags); 11419 } 11420} 11421 11422 11423static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 11424{ 11425 struct bnx2x *bp = netdev_priv(dev); 11426 int rc = 0; 11427 11428 switch (ctl->cmd) { 11429 case DRV_CTL_CTXTBL_WR_CMD: { 11430 u32 index = ctl->data.io.offset; 11431 dma_addr_t addr = ctl->data.io.dma_addr; 11432 11433 bnx2x_ilt_wr(bp, index, addr); 11434 break; 11435 } 11436 11437 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { 11438 int count = ctl->data.credit.credit_count; 11439 11440 bnx2x_cnic_sp_post(bp, count); 11441 break; 11442 } 11443 11444 /* rtnl_lock is held. */ 11445 case DRV_CTL_START_L2_CMD: { 11446 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11447 unsigned long sp_bits = 0; 11448 11449 /* Configure the iSCSI classification object */ 11450 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, 11451 cp->iscsi_l2_client_id, 11452 cp->iscsi_l2_cid, BP_FUNC(bp), 11453 bnx2x_sp(bp, mac_rdata), 11454 bnx2x_sp_mapping(bp, mac_rdata), 11455 BNX2X_FILTER_MAC_PENDING, 11456 &bp->sp_state, BNX2X_OBJ_TYPE_RX, 11457 &bp->macs_pool); 11458 11459 /* Set iSCSI MAC address */ 11460 rc = bnx2x_set_iscsi_eth_mac_addr(bp); 11461 if (rc) 11462 break; 11463 11464 mmiowb(); 11465 barrier(); 11466 11467 /* Start accepting on iSCSI L2 ring */ 11468 11469 netif_addr_lock_bh(dev); 11470 bnx2x_set_iscsi_eth_rx_mode(bp, true); 11471 netif_addr_unlock_bh(dev); 11472 11473 /* bits to wait on */ 11474 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11475 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); 11476 11477 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11478 BNX2X_ERR("rx_mode completion timed out!\n"); 11479 11480 break; 11481 } 11482 11483 /* rtnl_lock is held. */ 11484 case DRV_CTL_STOP_L2_CMD: { 11485 unsigned long sp_bits = 0; 11486 11487 /* Stop accepting on iSCSI L2 ring */ 11488 netif_addr_lock_bh(dev); 11489 bnx2x_set_iscsi_eth_rx_mode(bp, false); 11490 netif_addr_unlock_bh(dev); 11491 11492 /* bits to wait on */ 11493 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11494 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); 11495 11496 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11497 BNX2X_ERR("rx_mode completion timed out!\n"); 11498 11499 mmiowb(); 11500 barrier(); 11501 11502 /* Unset iSCSI L2 MAC */ 11503 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, 11504 BNX2X_ISCSI_ETH_MAC, true); 11505 break; 11506 } 11507 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { 11508 int count = ctl->data.credit.credit_count; 11509 11510 smp_mb__before_atomic_inc(); 11511 atomic_add(count, &bp->cq_spq_left); 11512 smp_mb__after_atomic_inc(); 11513 break; 11514 } 11515 11516 default: 11517 BNX2X_ERR("unknown command %x\n", ctl->cmd); 11518 rc = -EINVAL; 11519 } 11520 11521 return rc; 11522} 11523 11524void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) 11525{ 11526 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11527 11528 if (bp->flags & USING_MSIX_FLAG) { 11529 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 11530 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 11531 cp->irq_arr[0].vector = bp->msix_table[1].vector; 11532 } else { 11533 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 11534 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 11535 } 11536 if (!CHIP_IS_E1x(bp)) 11537 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; 11538 else 11539 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; 11540 11541 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); 11542 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); 11543 cp->irq_arr[1].status_blk = bp->def_status_blk; 11544 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 11545 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; 11546 11547 cp->num_irq = 2; 11548} 11549 11550static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, 11551 void *data) 11552{ 11553 struct bnx2x *bp = netdev_priv(dev); 11554 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11555 11556 if (ops == NULL) 11557 return -EINVAL; 11558 11559 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 11560 if (!bp->cnic_kwq) 11561 return -ENOMEM; 11562 11563 bp->cnic_kwq_cons = bp->cnic_kwq; 11564 bp->cnic_kwq_prod = bp->cnic_kwq; 11565 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; 11566 11567 bp->cnic_spq_pending = 0; 11568 bp->cnic_kwq_pending = 0; 11569 11570 bp->cnic_data = data; 11571 11572 cp->num_irq = 0; 11573 cp->drv_state |= CNIC_DRV_STATE_REGD; 11574 cp->iro_arr = bp->iro_arr; 11575 11576 bnx2x_setup_cnic_irq_info(bp); 11577 11578 rcu_assign_pointer(bp->cnic_ops, ops); 11579 11580 return 0; 11581} 11582 11583static int bnx2x_unregister_cnic(struct net_device *dev) 11584{ 11585 struct bnx2x *bp = netdev_priv(dev); 11586 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11587 11588 mutex_lock(&bp->cnic_mutex); 11589 cp->drv_state = 0; 11590 RCU_INIT_POINTER(bp->cnic_ops, NULL); 11591 mutex_unlock(&bp->cnic_mutex); 11592 synchronize_rcu(); 11593 kfree(bp->cnic_kwq); 11594 bp->cnic_kwq = NULL; 11595 11596 return 0; 11597} 11598 11599struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) 11600{ 11601 struct bnx2x *bp = netdev_priv(dev); 11602 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11603 11604 /* If both iSCSI and FCoE are disabled - return NULL in 11605 * order to indicate CNIC that it should not try to work 11606 * with this device. 11607 */ 11608 if (NO_ISCSI(bp) && NO_FCOE(bp)) 11609 return NULL; 11610 11611 cp->drv_owner = THIS_MODULE; 11612 cp->chip_id = CHIP_ID(bp); 11613 cp->pdev = bp->pdev; 11614 cp->io_base = bp->regview; 11615 cp->io_base2 = bp->doorbells; 11616 cp->max_kwqe_pending = 8; 11617 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; 11618 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 11619 bnx2x_cid_ilt_lines(bp); 11620 cp->ctx_tbl_len = CNIC_ILT_LINES; 11621 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 11622 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 11623 cp->drv_ctl = bnx2x_drv_ctl; 11624 cp->drv_register_cnic = bnx2x_register_cnic; 11625 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 11626 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID; 11627 cp->iscsi_l2_client_id = 11628 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11629 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID; 11630 11631 if (NO_ISCSI_OOO(bp)) 11632 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 11633 11634 if (NO_ISCSI(bp)) 11635 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; 11636 11637 if (NO_FCOE(bp)) 11638 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 11639 11640 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, " 11641 "starting cid %d\n", 11642 cp->ctx_blk_size, 11643 cp->ctx_tbl_offset, 11644 cp->ctx_tbl_len, 11645 cp->starting_cid); 11646 return cp; 11647} 11648EXPORT_SYMBOL(bnx2x_cnic_probe); 11649 11650#endif /* BCM_CNIC */ 11651 11652