bnx2x_main.c revision 452427b015b1b0cbbef7b6207908726837d39d57
1/* bnx2x_main.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20#include <linux/module.h> 21#include <linux/moduleparam.h> 22#include <linux/kernel.h> 23#include <linux/device.h> /* for dev_info() */ 24#include <linux/timer.h> 25#include <linux/errno.h> 26#include <linux/ioport.h> 27#include <linux/slab.h> 28#include <linux/interrupt.h> 29#include <linux/pci.h> 30#include <linux/init.h> 31#include <linux/netdevice.h> 32#include <linux/etherdevice.h> 33#include <linux/skbuff.h> 34#include <linux/dma-mapping.h> 35#include <linux/bitops.h> 36#include <linux/irq.h> 37#include <linux/delay.h> 38#include <asm/byteorder.h> 39#include <linux/time.h> 40#include <linux/ethtool.h> 41#include <linux/mii.h> 42#include <linux/if.h> 43#include <linux/if_vlan.h> 44#include <net/ip.h> 45#include <net/ipv6.h> 46#include <net/tcp.h> 47#include <net/checksum.h> 48#include <net/ip6_checksum.h> 49#include <linux/workqueue.h> 50#include <linux/crc32.h> 51#include <linux/crc32c.h> 52#include <linux/prefetch.h> 53#include <linux/zlib.h> 54#include <linux/io.h> 55#include <linux/semaphore.h> 56#include <linux/stringify.h> 57#include <linux/vmalloc.h> 58 59#include "bnx2x.h" 60#include "bnx2x_init.h" 61#include "bnx2x_init_ops.h" 62#include "bnx2x_cmn.h" 63#include "bnx2x_dcb.h" 64#include "bnx2x_sp.h" 65 66#include <linux/firmware.h> 67#include "bnx2x_fw_file_hdr.h" 68/* FW files */ 69#define FW_FILE_VERSION \ 70 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 71 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 72 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 73 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 74#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 75#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 76#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 77 78/* Time in jiffies before concluding the transmitter is hung */ 79#define TX_TIMEOUT (5*HZ) 80 81static char version[] __devinitdata = 82 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " 83 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 84 85MODULE_AUTHOR("Eliezer Tamir"); 86MODULE_DESCRIPTION("Broadcom NetXtreme II " 87 "BCM57710/57711/57711E/" 88 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 89 "57840/57840_MF Driver"); 90MODULE_LICENSE("GPL"); 91MODULE_VERSION(DRV_MODULE_VERSION); 92MODULE_FIRMWARE(FW_FILE_NAME_E1); 93MODULE_FIRMWARE(FW_FILE_NAME_E1H); 94MODULE_FIRMWARE(FW_FILE_NAME_E2); 95 96static int multi_mode = 1; 97module_param(multi_mode, int, 0); 98MODULE_PARM_DESC(multi_mode, " Multi queue mode " 99 "(0 Disable; 1 Enable (default))"); 100 101int num_queues; 102module_param(num_queues, int, 0); 103MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1" 104 " (default is as a number of CPUs)"); 105 106static int disable_tpa; 107module_param(disable_tpa, int, 0); 108MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 109 110#define INT_MODE_INTx 1 111#define INT_MODE_MSI 2 112static int int_mode; 113module_param(int_mode, int, 0); 114MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 115 "(1 INT#x; 2 MSI)"); 116 117static int dropless_fc; 118module_param(dropless_fc, int, 0); 119MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 120 121static int mrrs = -1; 122module_param(mrrs, int, 0); 123MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 124 125static int debug; 126module_param(debug, int, 0); 127MODULE_PARM_DESC(debug, " Default debug msglevel"); 128 129 130 131struct workqueue_struct *bnx2x_wq; 132 133enum bnx2x_board_type { 134 BCM57710 = 0, 135 BCM57711, 136 BCM57711E, 137 BCM57712, 138 BCM57712_MF, 139 BCM57800, 140 BCM57800_MF, 141 BCM57810, 142 BCM57810_MF, 143 BCM57840, 144 BCM57840_MF 145}; 146 147/* indexed by board_type, above */ 148static struct { 149 char *name; 150} board_info[] __devinitdata = { 151 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, 152 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, 153 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, 154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, 155 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, 156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, 157 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, 158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, 159 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, 160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, 161 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit " 162 "Ethernet Multi Function"} 163}; 164 165#ifndef PCI_DEVICE_ID_NX2_57710 166#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 167#endif 168#ifndef PCI_DEVICE_ID_NX2_57711 169#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 170#endif 171#ifndef PCI_DEVICE_ID_NX2_57711E 172#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 173#endif 174#ifndef PCI_DEVICE_ID_NX2_57712 175#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 176#endif 177#ifndef PCI_DEVICE_ID_NX2_57712_MF 178#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 179#endif 180#ifndef PCI_DEVICE_ID_NX2_57800 181#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 182#endif 183#ifndef PCI_DEVICE_ID_NX2_57800_MF 184#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 185#endif 186#ifndef PCI_DEVICE_ID_NX2_57810 187#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 188#endif 189#ifndef PCI_DEVICE_ID_NX2_57810_MF 190#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 191#endif 192#ifndef PCI_DEVICE_ID_NX2_57840 193#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 194#endif 195#ifndef PCI_DEVICE_ID_NX2_57840_MF 196#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 197#endif 198static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { 199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, 209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 210 { 0 } 211}; 212 213MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 214 215/* Global resources for unloading a previously loaded device */ 216#define BNX2X_PREV_WAIT_NEEDED 1 217static DEFINE_SEMAPHORE(bnx2x_prev_sem); 218static LIST_HEAD(bnx2x_prev_list); 219/**************************************************************************** 220* General service functions 221****************************************************************************/ 222 223static inline void __storm_memset_dma_mapping(struct bnx2x *bp, 224 u32 addr, dma_addr_t mapping) 225{ 226 REG_WR(bp, addr, U64_LO(mapping)); 227 REG_WR(bp, addr + 4, U64_HI(mapping)); 228} 229 230static inline void storm_memset_spq_addr(struct bnx2x *bp, 231 dma_addr_t mapping, u16 abs_fid) 232{ 233 u32 addr = XSEM_REG_FAST_MEMORY + 234 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 235 236 __storm_memset_dma_mapping(bp, addr, mapping); 237} 238 239static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 240 u16 pf_id) 241{ 242 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 243 pf_id); 244 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 245 pf_id); 246 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 247 pf_id); 248 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 249 pf_id); 250} 251 252static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 253 u8 enable) 254{ 255 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 256 enable); 257 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 258 enable); 259 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 260 enable); 261 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 262 enable); 263} 264 265static inline void storm_memset_eq_data(struct bnx2x *bp, 266 struct event_ring_data *eq_data, 267 u16 pfid) 268{ 269 size_t size = sizeof(struct event_ring_data); 270 271 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 272 273 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 274} 275 276static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 277 u16 pfid) 278{ 279 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 280 REG_WR16(bp, addr, eq_prod); 281} 282 283/* used only at init 284 * locking is done by mcp 285 */ 286static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 287{ 288 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 289 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 290 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 291 PCICFG_VENDOR_ID_OFFSET); 292} 293 294static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 295{ 296 u32 val; 297 298 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 299 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 300 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 301 PCICFG_VENDOR_ID_OFFSET); 302 303 return val; 304} 305 306#define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 307#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 308#define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 309#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 310#define DMAE_DP_DST_NONE "dst_addr [none]" 311 312static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, 313 int msglvl) 314{ 315 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 316 317 switch (dmae->opcode & DMAE_COMMAND_DST) { 318 case DMAE_CMD_DST_PCI: 319 if (src_type == DMAE_CMD_SRC_PCI) 320 DP(msglvl, "DMAE: opcode 0x%08x\n" 321 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 322 "comp_addr [%x:%08x], comp_val 0x%08x\n", 323 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 324 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 325 dmae->comp_addr_hi, dmae->comp_addr_lo, 326 dmae->comp_val); 327 else 328 DP(msglvl, "DMAE: opcode 0x%08x\n" 329 "src [%08x], len [%d*4], dst [%x:%08x]\n" 330 "comp_addr [%x:%08x], comp_val 0x%08x\n", 331 dmae->opcode, dmae->src_addr_lo >> 2, 332 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 333 dmae->comp_addr_hi, dmae->comp_addr_lo, 334 dmae->comp_val); 335 break; 336 case DMAE_CMD_DST_GRC: 337 if (src_type == DMAE_CMD_SRC_PCI) 338 DP(msglvl, "DMAE: opcode 0x%08x\n" 339 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 340 "comp_addr [%x:%08x], comp_val 0x%08x\n", 341 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 342 dmae->len, dmae->dst_addr_lo >> 2, 343 dmae->comp_addr_hi, dmae->comp_addr_lo, 344 dmae->comp_val); 345 else 346 DP(msglvl, "DMAE: opcode 0x%08x\n" 347 "src [%08x], len [%d*4], dst [%08x]\n" 348 "comp_addr [%x:%08x], comp_val 0x%08x\n", 349 dmae->opcode, dmae->src_addr_lo >> 2, 350 dmae->len, dmae->dst_addr_lo >> 2, 351 dmae->comp_addr_hi, dmae->comp_addr_lo, 352 dmae->comp_val); 353 break; 354 default: 355 if (src_type == DMAE_CMD_SRC_PCI) 356 DP(msglvl, "DMAE: opcode 0x%08x\n" 357 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 358 "comp_addr [%x:%08x] comp_val 0x%08x\n", 359 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 360 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 361 dmae->comp_val); 362 else 363 DP(msglvl, "DMAE: opcode 0x%08x\n" 364 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 365 "comp_addr [%x:%08x] comp_val 0x%08x\n", 366 dmae->opcode, dmae->src_addr_lo >> 2, 367 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 368 dmae->comp_val); 369 break; 370 } 371 372} 373 374/* copy command into DMAE command memory and set DMAE command go */ 375void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 376{ 377 u32 cmd_offset; 378 int i; 379 380 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 381 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 382 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 383 } 384 REG_WR(bp, dmae_reg_go_c[idx], 1); 385} 386 387u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 388{ 389 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 390 DMAE_CMD_C_ENABLE); 391} 392 393u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 394{ 395 return opcode & ~DMAE_CMD_SRC_RESET; 396} 397 398u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 399 bool with_comp, u8 comp_type) 400{ 401 u32 opcode = 0; 402 403 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 404 (dst_type << DMAE_COMMAND_DST_SHIFT)); 405 406 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 407 408 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 409 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | 410 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 411 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 412 413#ifdef __BIG_ENDIAN 414 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 415#else 416 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 417#endif 418 if (with_comp) 419 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 420 return opcode; 421} 422 423static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 424 struct dmae_command *dmae, 425 u8 src_type, u8 dst_type) 426{ 427 memset(dmae, 0, sizeof(struct dmae_command)); 428 429 /* set the opcode */ 430 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 431 true, DMAE_COMP_PCI); 432 433 /* fill in the completion parameters */ 434 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 435 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 436 dmae->comp_val = DMAE_COMP_VAL; 437} 438 439/* issue a dmae command over the init-channel and wailt for completion */ 440static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, 441 struct dmae_command *dmae) 442{ 443 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 444 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 445 int rc = 0; 446 447 /* 448 * Lock the dmae channel. Disable BHs to prevent a dead-lock 449 * as long as this code is called both from syscall context and 450 * from ndo_set_rx_mode() flow that may be called from BH. 451 */ 452 spin_lock_bh(&bp->dmae_lock); 453 454 /* reset completion */ 455 *wb_comp = 0; 456 457 /* post the command on the channel used for initializations */ 458 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 459 460 /* wait for completion */ 461 udelay(5); 462 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 463 464 if (!cnt || 465 (bp->recovery_state != BNX2X_RECOVERY_DONE && 466 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 467 BNX2X_ERR("DMAE timeout!\n"); 468 rc = DMAE_TIMEOUT; 469 goto unlock; 470 } 471 cnt--; 472 udelay(50); 473 } 474 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 475 BNX2X_ERR("DMAE PCI error!\n"); 476 rc = DMAE_PCI_ERROR; 477 } 478 479unlock: 480 spin_unlock_bh(&bp->dmae_lock); 481 return rc; 482} 483 484void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 485 u32 len32) 486{ 487 struct dmae_command dmae; 488 489 if (!bp->dmae_ready) { 490 u32 *data = bnx2x_sp(bp, wb_data[0]); 491 492 if (CHIP_IS_E1(bp)) 493 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 494 else 495 bnx2x_init_str_wr(bp, dst_addr, data, len32); 496 return; 497 } 498 499 /* set opcode and fixed command fields */ 500 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 501 502 /* fill in addresses and len */ 503 dmae.src_addr_lo = U64_LO(dma_addr); 504 dmae.src_addr_hi = U64_HI(dma_addr); 505 dmae.dst_addr_lo = dst_addr >> 2; 506 dmae.dst_addr_hi = 0; 507 dmae.len = len32; 508 509 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 510 511 /* issue the command and wait for completion */ 512 bnx2x_issue_dmae_with_comp(bp, &dmae); 513} 514 515void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 516{ 517 struct dmae_command dmae; 518 519 if (!bp->dmae_ready) { 520 u32 *data = bnx2x_sp(bp, wb_data[0]); 521 int i; 522 523 if (CHIP_IS_E1(bp)) 524 for (i = 0; i < len32; i++) 525 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 526 else 527 for (i = 0; i < len32; i++) 528 data[i] = REG_RD(bp, src_addr + i*4); 529 530 return; 531 } 532 533 /* set opcode and fixed command fields */ 534 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 535 536 /* fill in addresses and len */ 537 dmae.src_addr_lo = src_addr >> 2; 538 dmae.src_addr_hi = 0; 539 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 540 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 541 dmae.len = len32; 542 543 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 544 545 /* issue the command and wait for completion */ 546 bnx2x_issue_dmae_with_comp(bp, &dmae); 547} 548 549static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 550 u32 addr, u32 len) 551{ 552 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 553 int offset = 0; 554 555 while (len > dmae_wr_max) { 556 bnx2x_write_dmae(bp, phys_addr + offset, 557 addr + offset, dmae_wr_max); 558 offset += dmae_wr_max * 4; 559 len -= dmae_wr_max; 560 } 561 562 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 563} 564 565/* used only for slowpath so not inlined */ 566static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo) 567{ 568 u32 wb_write[2]; 569 570 wb_write[0] = val_hi; 571 wb_write[1] = val_lo; 572 REG_WR_DMAE(bp, reg, wb_write, 2); 573} 574 575#ifdef USE_WB_RD 576static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg) 577{ 578 u32 wb_data[2]; 579 580 REG_RD_DMAE(bp, reg, wb_data, 2); 581 582 return HILO_U64(wb_data[0], wb_data[1]); 583} 584#endif 585 586static int bnx2x_mc_assert(struct bnx2x *bp) 587{ 588 char last_idx; 589 int i, rc = 0; 590 u32 row0, row1, row2, row3; 591 592 /* XSTORM */ 593 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + 594 XSTORM_ASSERT_LIST_INDEX_OFFSET); 595 if (last_idx) 596 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 597 598 /* print the asserts */ 599 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 600 601 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + 602 XSTORM_ASSERT_LIST_OFFSET(i)); 603 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + 604 XSTORM_ASSERT_LIST_OFFSET(i) + 4); 605 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + 606 XSTORM_ASSERT_LIST_OFFSET(i) + 8); 607 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + 608 XSTORM_ASSERT_LIST_OFFSET(i) + 12); 609 610 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 611 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 612 i, row3, row2, row1, row0); 613 rc++; 614 } else { 615 break; 616 } 617 } 618 619 /* TSTORM */ 620 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + 621 TSTORM_ASSERT_LIST_INDEX_OFFSET); 622 if (last_idx) 623 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 624 625 /* print the asserts */ 626 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 627 628 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + 629 TSTORM_ASSERT_LIST_OFFSET(i)); 630 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + 631 TSTORM_ASSERT_LIST_OFFSET(i) + 4); 632 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + 633 TSTORM_ASSERT_LIST_OFFSET(i) + 8); 634 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + 635 TSTORM_ASSERT_LIST_OFFSET(i) + 12); 636 637 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 638 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 639 i, row3, row2, row1, row0); 640 rc++; 641 } else { 642 break; 643 } 644 } 645 646 /* CSTORM */ 647 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + 648 CSTORM_ASSERT_LIST_INDEX_OFFSET); 649 if (last_idx) 650 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 651 652 /* print the asserts */ 653 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 654 655 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + 656 CSTORM_ASSERT_LIST_OFFSET(i)); 657 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + 658 CSTORM_ASSERT_LIST_OFFSET(i) + 4); 659 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + 660 CSTORM_ASSERT_LIST_OFFSET(i) + 8); 661 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + 662 CSTORM_ASSERT_LIST_OFFSET(i) + 12); 663 664 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 665 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 666 i, row3, row2, row1, row0); 667 rc++; 668 } else { 669 break; 670 } 671 } 672 673 /* USTORM */ 674 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + 675 USTORM_ASSERT_LIST_INDEX_OFFSET); 676 if (last_idx) 677 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 678 679 /* print the asserts */ 680 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 681 682 row0 = REG_RD(bp, BAR_USTRORM_INTMEM + 683 USTORM_ASSERT_LIST_OFFSET(i)); 684 row1 = REG_RD(bp, BAR_USTRORM_INTMEM + 685 USTORM_ASSERT_LIST_OFFSET(i) + 4); 686 row2 = REG_RD(bp, BAR_USTRORM_INTMEM + 687 USTORM_ASSERT_LIST_OFFSET(i) + 8); 688 row3 = REG_RD(bp, BAR_USTRORM_INTMEM + 689 USTORM_ASSERT_LIST_OFFSET(i) + 12); 690 691 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 692 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 693 i, row3, row2, row1, row0); 694 rc++; 695 } else { 696 break; 697 } 698 } 699 700 return rc; 701} 702 703void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 704{ 705 u32 addr, val; 706 u32 mark, offset; 707 __be32 data[9]; 708 int word; 709 u32 trace_shmem_base; 710 if (BP_NOMCP(bp)) { 711 BNX2X_ERR("NO MCP - can not dump\n"); 712 return; 713 } 714 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 715 (bp->common.bc_ver & 0xff0000) >> 16, 716 (bp->common.bc_ver & 0xff00) >> 8, 717 (bp->common.bc_ver & 0xff)); 718 719 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 720 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 721 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); 722 723 if (BP_PATH(bp) == 0) 724 trace_shmem_base = bp->common.shmem_base; 725 else 726 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 727 addr = trace_shmem_base - 0x800; 728 729 /* validate TRCB signature */ 730 mark = REG_RD(bp, addr); 731 if (mark != MFW_TRACE_SIGNATURE) { 732 BNX2X_ERR("Trace buffer signature is missing."); 733 return ; 734 } 735 736 /* read cyclic buffer pointer */ 737 addr += 4; 738 mark = REG_RD(bp, addr); 739 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 740 + ((mark + 0x3) & ~0x3) - 0x08000000; 741 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 742 743 printk("%s", lvl); 744 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { 745 for (word = 0; word < 8; word++) 746 data[word] = htonl(REG_RD(bp, offset + 4*word)); 747 data[8] = 0x0; 748 pr_cont("%s", (char *)data); 749 } 750 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 751 for (word = 0; word < 8; word++) 752 data[word] = htonl(REG_RD(bp, offset + 4*word)); 753 data[8] = 0x0; 754 pr_cont("%s", (char *)data); 755 } 756 printk("%s" "end of fw dump\n", lvl); 757} 758 759static inline void bnx2x_fw_dump(struct bnx2x *bp) 760{ 761 bnx2x_fw_dump_lvl(bp, KERN_ERR); 762} 763 764void bnx2x_panic_dump(struct bnx2x *bp) 765{ 766 int i; 767 u16 j; 768 struct hc_sp_status_block_data sp_sb_data; 769 int func = BP_FUNC(bp); 770#ifdef BNX2X_STOP_ON_ERROR 771 u16 start = 0, end = 0; 772 u8 cos; 773#endif 774 775 bp->stats_state = STATS_STATE_DISABLED; 776 bp->eth_stats.unrecoverable_error++; 777 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 778 779 BNX2X_ERR("begin crash dump -----------------\n"); 780 781 /* Indices */ 782 /* Common */ 783 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 784 bp->def_idx, bp->def_att_idx, bp->attn_state, 785 bp->spq_prod_idx, bp->stats_counter); 786 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 787 bp->def_status_blk->atten_status_block.attn_bits, 788 bp->def_status_blk->atten_status_block.attn_bits_ack, 789 bp->def_status_blk->atten_status_block.status_block_id, 790 bp->def_status_blk->atten_status_block.attn_bits_index); 791 BNX2X_ERR(" def ("); 792 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 793 pr_cont("0x%x%s", 794 bp->def_status_blk->sp_sb.index_values[i], 795 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 796 797 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 798 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + 799 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 800 i*sizeof(u32)); 801 802 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 803 sp_sb_data.igu_sb_id, 804 sp_sb_data.igu_seg_id, 805 sp_sb_data.p_func.pf_id, 806 sp_sb_data.p_func.vnic_id, 807 sp_sb_data.p_func.vf_id, 808 sp_sb_data.p_func.vf_valid, 809 sp_sb_data.state); 810 811 812 for_each_eth_queue(bp, i) { 813 struct bnx2x_fastpath *fp = &bp->fp[i]; 814 int loop; 815 struct hc_status_block_data_e2 sb_data_e2; 816 struct hc_status_block_data_e1x sb_data_e1x; 817 struct hc_status_block_sm *hc_sm_p = 818 CHIP_IS_E1x(bp) ? 819 sb_data_e1x.common.state_machine : 820 sb_data_e2.common.state_machine; 821 struct hc_index_data *hc_index_p = 822 CHIP_IS_E1x(bp) ? 823 sb_data_e1x.index_data : 824 sb_data_e2.index_data; 825 u8 data_size, cos; 826 u32 *sb_data_p; 827 struct bnx2x_fp_txdata txdata; 828 829 /* Rx */ 830 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 831 i, fp->rx_bd_prod, fp->rx_bd_cons, 832 fp->rx_comp_prod, 833 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 834 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", 835 fp->rx_sge_prod, fp->last_max_sge, 836 le16_to_cpu(fp->fp_hc_idx)); 837 838 /* Tx */ 839 for_each_cos_in_tx_queue(fp, cos) 840 { 841 txdata = fp->txdata[cos]; 842 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", 843 i, txdata.tx_pkt_prod, 844 txdata.tx_pkt_cons, txdata.tx_bd_prod, 845 txdata.tx_bd_cons, 846 le16_to_cpu(*txdata.tx_cons_sb)); 847 } 848 849 loop = CHIP_IS_E1x(bp) ? 850 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 851 852 /* host sb data */ 853 854#ifdef BCM_CNIC 855 if (IS_FCOE_FP(fp)) 856 continue; 857#endif 858 BNX2X_ERR(" run indexes ("); 859 for (j = 0; j < HC_SB_MAX_SM; j++) 860 pr_cont("0x%x%s", 861 fp->sb_running_index[j], 862 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 863 864 BNX2X_ERR(" indexes ("); 865 for (j = 0; j < loop; j++) 866 pr_cont("0x%x%s", 867 fp->sb_index_values[j], 868 (j == loop - 1) ? ")" : " "); 869 /* fw sb data */ 870 data_size = CHIP_IS_E1x(bp) ? 871 sizeof(struct hc_status_block_data_e1x) : 872 sizeof(struct hc_status_block_data_e2); 873 data_size /= sizeof(u32); 874 sb_data_p = CHIP_IS_E1x(bp) ? 875 (u32 *)&sb_data_e1x : 876 (u32 *)&sb_data_e2; 877 /* copy sb data in here */ 878 for (j = 0; j < data_size; j++) 879 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 880 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 881 j * sizeof(u32)); 882 883 if (!CHIP_IS_E1x(bp)) { 884 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", 885 sb_data_e2.common.p_func.pf_id, 886 sb_data_e2.common.p_func.vf_id, 887 sb_data_e2.common.p_func.vf_valid, 888 sb_data_e2.common.p_func.vnic_id, 889 sb_data_e2.common.same_igu_sb_1b, 890 sb_data_e2.common.state); 891 } else { 892 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", 893 sb_data_e1x.common.p_func.pf_id, 894 sb_data_e1x.common.p_func.vf_id, 895 sb_data_e1x.common.p_func.vf_valid, 896 sb_data_e1x.common.p_func.vnic_id, 897 sb_data_e1x.common.same_igu_sb_1b, 898 sb_data_e1x.common.state); 899 } 900 901 /* SB_SMs data */ 902 for (j = 0; j < HC_SB_MAX_SM; j++) { 903 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", 904 j, hc_sm_p[j].__flags, 905 hc_sm_p[j].igu_sb_id, 906 hc_sm_p[j].igu_seg_id, 907 hc_sm_p[j].time_to_expire, 908 hc_sm_p[j].timer_value); 909 } 910 911 /* Indecies data */ 912 for (j = 0; j < loop; j++) { 913 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, 914 hc_index_p[j].flags, 915 hc_index_p[j].timeout); 916 } 917 } 918 919#ifdef BNX2X_STOP_ON_ERROR 920 /* Rings */ 921 /* Rx */ 922 for_each_rx_queue(bp, i) { 923 struct bnx2x_fastpath *fp = &bp->fp[i]; 924 925 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 926 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 927 for (j = start; j != end; j = RX_BD(j + 1)) { 928 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 929 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 930 931 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 932 i, j, rx_bd[1], rx_bd[0], sw_bd->data); 933 } 934 935 start = RX_SGE(fp->rx_sge_prod); 936 end = RX_SGE(fp->last_max_sge); 937 for (j = start; j != end; j = RX_SGE(j + 1)) { 938 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 939 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 940 941 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 942 i, j, rx_sge[1], rx_sge[0], sw_page->page); 943 } 944 945 start = RCQ_BD(fp->rx_comp_cons - 10); 946 end = RCQ_BD(fp->rx_comp_cons + 503); 947 for (j = start; j != end; j = RCQ_BD(j + 1)) { 948 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 949 950 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 951 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 952 } 953 } 954 955 /* Tx */ 956 for_each_tx_queue(bp, i) { 957 struct bnx2x_fastpath *fp = &bp->fp[i]; 958 for_each_cos_in_tx_queue(fp, cos) { 959 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; 960 961 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 962 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 963 for (j = start; j != end; j = TX_BD(j + 1)) { 964 struct sw_tx_bd *sw_bd = 965 &txdata->tx_buf_ring[j]; 966 967 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", 968 i, cos, j, sw_bd->skb, 969 sw_bd->first_bd); 970 } 971 972 start = TX_BD(txdata->tx_bd_cons - 10); 973 end = TX_BD(txdata->tx_bd_cons + 254); 974 for (j = start; j != end; j = TX_BD(j + 1)) { 975 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 976 977 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", 978 i, cos, j, tx_bd[0], tx_bd[1], 979 tx_bd[2], tx_bd[3]); 980 } 981 } 982 } 983#endif 984 bnx2x_fw_dump(bp); 985 bnx2x_mc_assert(bp); 986 BNX2X_ERR("end crash dump -----------------\n"); 987} 988 989/* 990 * FLR Support for E2 991 * 992 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 993 * initialization. 994 */ 995#define FLR_WAIT_USEC 10000 /* 10 miliseconds */ 996#define FLR_WAIT_INTERVAL 50 /* usec */ 997#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ 998 999struct pbf_pN_buf_regs { 1000 int pN; 1001 u32 init_crd; 1002 u32 crd; 1003 u32 crd_freed; 1004}; 1005 1006struct pbf_pN_cmd_regs { 1007 int pN; 1008 u32 lines_occup; 1009 u32 lines_freed; 1010}; 1011 1012static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1013 struct pbf_pN_buf_regs *regs, 1014 u32 poll_count) 1015{ 1016 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1017 u32 cur_cnt = poll_count; 1018 1019 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1020 crd = crd_start = REG_RD(bp, regs->crd); 1021 init_crd = REG_RD(bp, regs->init_crd); 1022 1023 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1024 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1025 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1026 1027 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1028 (init_crd - crd_start))) { 1029 if (cur_cnt--) { 1030 udelay(FLR_WAIT_INTERVAL); 1031 crd = REG_RD(bp, regs->crd); 1032 crd_freed = REG_RD(bp, regs->crd_freed); 1033 } else { 1034 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1035 regs->pN); 1036 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1037 regs->pN, crd); 1038 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1039 regs->pN, crd_freed); 1040 break; 1041 } 1042 } 1043 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1044 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1045} 1046 1047static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1048 struct pbf_pN_cmd_regs *regs, 1049 u32 poll_count) 1050{ 1051 u32 occup, to_free, freed, freed_start; 1052 u32 cur_cnt = poll_count; 1053 1054 occup = to_free = REG_RD(bp, regs->lines_occup); 1055 freed = freed_start = REG_RD(bp, regs->lines_freed); 1056 1057 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1058 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1059 1060 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1061 if (cur_cnt--) { 1062 udelay(FLR_WAIT_INTERVAL); 1063 occup = REG_RD(bp, regs->lines_occup); 1064 freed = REG_RD(bp, regs->lines_freed); 1065 } else { 1066 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1067 regs->pN); 1068 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1069 regs->pN, occup); 1070 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1071 regs->pN, freed); 1072 break; 1073 } 1074 } 1075 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1076 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1077} 1078 1079static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1080 u32 expected, u32 poll_count) 1081{ 1082 u32 cur_cnt = poll_count; 1083 u32 val; 1084 1085 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1086 udelay(FLR_WAIT_INTERVAL); 1087 1088 return val; 1089} 1090 1091static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1092 char *msg, u32 poll_cnt) 1093{ 1094 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1095 if (val != 0) { 1096 BNX2X_ERR("%s usage count=%d\n", msg, val); 1097 return 1; 1098 } 1099 return 0; 1100} 1101 1102static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1103{ 1104 /* adjust polling timeout */ 1105 if (CHIP_REV_IS_EMUL(bp)) 1106 return FLR_POLL_CNT * 2000; 1107 1108 if (CHIP_REV_IS_FPGA(bp)) 1109 return FLR_POLL_CNT * 120; 1110 1111 return FLR_POLL_CNT; 1112} 1113 1114static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1115{ 1116 struct pbf_pN_cmd_regs cmd_regs[] = { 1117 {0, (CHIP_IS_E3B0(bp)) ? 1118 PBF_REG_TQ_OCCUPANCY_Q0 : 1119 PBF_REG_P0_TQ_OCCUPANCY, 1120 (CHIP_IS_E3B0(bp)) ? 1121 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1122 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1123 {1, (CHIP_IS_E3B0(bp)) ? 1124 PBF_REG_TQ_OCCUPANCY_Q1 : 1125 PBF_REG_P1_TQ_OCCUPANCY, 1126 (CHIP_IS_E3B0(bp)) ? 1127 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1128 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1129 {4, (CHIP_IS_E3B0(bp)) ? 1130 PBF_REG_TQ_OCCUPANCY_LB_Q : 1131 PBF_REG_P4_TQ_OCCUPANCY, 1132 (CHIP_IS_E3B0(bp)) ? 1133 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1134 PBF_REG_P4_TQ_LINES_FREED_CNT} 1135 }; 1136 1137 struct pbf_pN_buf_regs buf_regs[] = { 1138 {0, (CHIP_IS_E3B0(bp)) ? 1139 PBF_REG_INIT_CRD_Q0 : 1140 PBF_REG_P0_INIT_CRD , 1141 (CHIP_IS_E3B0(bp)) ? 1142 PBF_REG_CREDIT_Q0 : 1143 PBF_REG_P0_CREDIT, 1144 (CHIP_IS_E3B0(bp)) ? 1145 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1146 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1147 {1, (CHIP_IS_E3B0(bp)) ? 1148 PBF_REG_INIT_CRD_Q1 : 1149 PBF_REG_P1_INIT_CRD, 1150 (CHIP_IS_E3B0(bp)) ? 1151 PBF_REG_CREDIT_Q1 : 1152 PBF_REG_P1_CREDIT, 1153 (CHIP_IS_E3B0(bp)) ? 1154 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1155 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1156 {4, (CHIP_IS_E3B0(bp)) ? 1157 PBF_REG_INIT_CRD_LB_Q : 1158 PBF_REG_P4_INIT_CRD, 1159 (CHIP_IS_E3B0(bp)) ? 1160 PBF_REG_CREDIT_LB_Q : 1161 PBF_REG_P4_CREDIT, 1162 (CHIP_IS_E3B0(bp)) ? 1163 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1164 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1165 }; 1166 1167 int i; 1168 1169 /* Verify the command queues are flushed P0, P1, P4 */ 1170 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1171 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1172 1173 1174 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1175 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1176 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1177} 1178 1179#define OP_GEN_PARAM(param) \ 1180 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1181 1182#define OP_GEN_TYPE(type) \ 1183 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1184 1185#define OP_GEN_AGG_VECT(index) \ 1186 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1187 1188 1189static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, 1190 u32 poll_cnt) 1191{ 1192 struct sdm_op_gen op_gen = {0}; 1193 1194 u32 comp_addr = BAR_CSTRORM_INTMEM + 1195 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1196 int ret = 0; 1197 1198 if (REG_RD(bp, comp_addr)) { 1199 BNX2X_ERR("Cleanup complete was not 0 before sending\n"); 1200 return 1; 1201 } 1202 1203 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1204 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1205 op_gen.command |= OP_GEN_AGG_VECT(clnup_func); 1206 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1207 1208 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); 1209 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); 1210 1211 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1212 BNX2X_ERR("FW final cleanup did not succeed\n"); 1213 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", 1214 (REG_RD(bp, comp_addr))); 1215 ret = 1; 1216 } 1217 /* Zero completion for nxt FLR */ 1218 REG_WR(bp, comp_addr, 0); 1219 1220 return ret; 1221} 1222 1223static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1224{ 1225 int pos; 1226 u16 status; 1227 1228 pos = pci_pcie_cap(dev); 1229 if (!pos) 1230 return false; 1231 1232 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 1233 return status & PCI_EXP_DEVSTA_TRPND; 1234} 1235 1236/* PF FLR specific routines 1237*/ 1238static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1239{ 1240 1241 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1242 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1243 CFC_REG_NUM_LCIDS_INSIDE_PF, 1244 "CFC PF usage counter timed out", 1245 poll_cnt)) 1246 return 1; 1247 1248 1249 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1250 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1251 DORQ_REG_PF_USAGE_CNT, 1252 "DQ PF usage counter timed out", 1253 poll_cnt)) 1254 return 1; 1255 1256 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1257 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1258 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1259 "QM PF usage counter timed out", 1260 poll_cnt)) 1261 return 1; 1262 1263 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1264 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1265 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1266 "Timers VNIC usage counter timed out", 1267 poll_cnt)) 1268 return 1; 1269 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1270 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1271 "Timers NUM_SCANS usage counter timed out", 1272 poll_cnt)) 1273 return 1; 1274 1275 /* Wait DMAE PF usage counter to zero */ 1276 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1277 dmae_reg_go_c[INIT_DMAE_C(bp)], 1278 "DMAE dommand register timed out", 1279 poll_cnt)) 1280 return 1; 1281 1282 return 0; 1283} 1284 1285static void bnx2x_hw_enable_status(struct bnx2x *bp) 1286{ 1287 u32 val; 1288 1289 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1290 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1291 1292 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1293 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1294 1295 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1296 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1297 1298 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1299 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1300 1301 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1302 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1303 1304 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1305 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1306 1307 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1308 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1309 1310 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1311 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1312 val); 1313} 1314 1315static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1316{ 1317 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1318 1319 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1320 1321 /* Re-enable PF target read access */ 1322 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1323 1324 /* Poll HW usage counters */ 1325 DP(BNX2X_MSG_SP, "Polling usage counters\n"); 1326 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1327 return -EBUSY; 1328 1329 /* Zero the igu 'trailing edge' and 'leading edge' */ 1330 1331 /* Send the FW cleanup command */ 1332 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1333 return -EBUSY; 1334 1335 /* ATC cleanup */ 1336 1337 /* Verify TX hw is flushed */ 1338 bnx2x_tx_hw_flushed(bp, poll_cnt); 1339 1340 /* Wait 100ms (not adjusted according to platform) */ 1341 msleep(100); 1342 1343 /* Verify no pending pci transactions */ 1344 if (bnx2x_is_pcie_pending(bp->pdev)) 1345 BNX2X_ERR("PCIE Transactions still pending\n"); 1346 1347 /* Debug */ 1348 bnx2x_hw_enable_status(bp); 1349 1350 /* 1351 * Master enable - Due to WB DMAE writes performed before this 1352 * register is re-initialized as part of the regular function init 1353 */ 1354 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1355 1356 return 0; 1357} 1358 1359static void bnx2x_hc_int_enable(struct bnx2x *bp) 1360{ 1361 int port = BP_PORT(bp); 1362 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1363 u32 val = REG_RD(bp, addr); 1364 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1365 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1366 1367 if (msix) { 1368 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1369 HC_CONFIG_0_REG_INT_LINE_EN_0); 1370 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1371 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1372 } else if (msi) { 1373 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1374 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1375 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1376 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1377 } else { 1378 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1379 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1380 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1381 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1382 1383 if (!CHIP_IS_E1(bp)) { 1384 DP(NETIF_MSG_IFUP, 1385 "write %x to HC %d (addr 0x%x)\n", val, port, addr); 1386 1387 REG_WR(bp, addr, val); 1388 1389 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1390 } 1391 } 1392 1393 if (CHIP_IS_E1(bp)) 1394 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1395 1396 DP(NETIF_MSG_IFUP, 1397 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, 1398 (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1399 1400 REG_WR(bp, addr, val); 1401 /* 1402 * Ensure that HC_CONFIG is written before leading/trailing edge config 1403 */ 1404 mmiowb(); 1405 barrier(); 1406 1407 if (!CHIP_IS_E1(bp)) { 1408 /* init leading/trailing edge */ 1409 if (IS_MF(bp)) { 1410 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1411 if (bp->port.pmf) 1412 /* enable nig and gpio3 attention */ 1413 val |= 0x1100; 1414 } else 1415 val = 0xffff; 1416 1417 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1418 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1419 } 1420 1421 /* Make sure that interrupts are indeed enabled from here on */ 1422 mmiowb(); 1423} 1424 1425static void bnx2x_igu_int_enable(struct bnx2x *bp) 1426{ 1427 u32 val; 1428 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1429 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1430 1431 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1432 1433 if (msix) { 1434 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1435 IGU_PF_CONF_SINGLE_ISR_EN); 1436 val |= (IGU_PF_CONF_FUNC_EN | 1437 IGU_PF_CONF_MSI_MSIX_EN | 1438 IGU_PF_CONF_ATTN_BIT_EN); 1439 } else if (msi) { 1440 val &= ~IGU_PF_CONF_INT_LINE_EN; 1441 val |= (IGU_PF_CONF_FUNC_EN | 1442 IGU_PF_CONF_MSI_MSIX_EN | 1443 IGU_PF_CONF_ATTN_BIT_EN | 1444 IGU_PF_CONF_SINGLE_ISR_EN); 1445 } else { 1446 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1447 val |= (IGU_PF_CONF_FUNC_EN | 1448 IGU_PF_CONF_INT_LINE_EN | 1449 IGU_PF_CONF_ATTN_BIT_EN | 1450 IGU_PF_CONF_SINGLE_ISR_EN); 1451 } 1452 1453 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", 1454 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1455 1456 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1457 1458 barrier(); 1459 1460 /* init leading/trailing edge */ 1461 if (IS_MF(bp)) { 1462 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1463 if (bp->port.pmf) 1464 /* enable nig and gpio3 attention */ 1465 val |= 0x1100; 1466 } else 1467 val = 0xffff; 1468 1469 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1470 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1471 1472 /* Make sure that interrupts are indeed enabled from here on */ 1473 mmiowb(); 1474} 1475 1476void bnx2x_int_enable(struct bnx2x *bp) 1477{ 1478 if (bp->common.int_block == INT_BLOCK_HC) 1479 bnx2x_hc_int_enable(bp); 1480 else 1481 bnx2x_igu_int_enable(bp); 1482} 1483 1484static void bnx2x_hc_int_disable(struct bnx2x *bp) 1485{ 1486 int port = BP_PORT(bp); 1487 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1488 u32 val = REG_RD(bp, addr); 1489 1490 /* 1491 * in E1 we must use only PCI configuration space to disable 1492 * MSI/MSIX capablility 1493 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 1494 */ 1495 if (CHIP_IS_E1(bp)) { 1496 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 1497 * Use mask register to prevent from HC sending interrupts 1498 * after we exit the function 1499 */ 1500 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 1501 1502 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1503 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1504 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1505 } else 1506 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1507 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1508 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1509 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1510 1511 DP(NETIF_MSG_IFDOWN, 1512 "write %x to HC %d (addr 0x%x)\n", 1513 val, port, addr); 1514 1515 /* flush all outstanding writes */ 1516 mmiowb(); 1517 1518 REG_WR(bp, addr, val); 1519 if (REG_RD(bp, addr) != val) 1520 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1521} 1522 1523static void bnx2x_igu_int_disable(struct bnx2x *bp) 1524{ 1525 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1526 1527 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 1528 IGU_PF_CONF_INT_LINE_EN | 1529 IGU_PF_CONF_ATTN_BIT_EN); 1530 1531 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); 1532 1533 /* flush all outstanding writes */ 1534 mmiowb(); 1535 1536 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1537 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 1538 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1539} 1540 1541void bnx2x_int_disable(struct bnx2x *bp) 1542{ 1543 if (bp->common.int_block == INT_BLOCK_HC) 1544 bnx2x_hc_int_disable(bp); 1545 else 1546 bnx2x_igu_int_disable(bp); 1547} 1548 1549void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1550{ 1551 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1552 int i, offset; 1553 1554 if (disable_hw) 1555 /* prevent the HW from sending interrupts */ 1556 bnx2x_int_disable(bp); 1557 1558 /* make sure all ISRs are done */ 1559 if (msix) { 1560 synchronize_irq(bp->msix_table[0].vector); 1561 offset = 1; 1562#ifdef BCM_CNIC 1563 offset++; 1564#endif 1565 for_each_eth_queue(bp, i) 1566 synchronize_irq(bp->msix_table[offset++].vector); 1567 } else 1568 synchronize_irq(bp->pdev->irq); 1569 1570 /* make sure sp_task is not running */ 1571 cancel_delayed_work(&bp->sp_task); 1572 cancel_delayed_work(&bp->period_task); 1573 flush_workqueue(bnx2x_wq); 1574} 1575 1576/* fast path */ 1577 1578/* 1579 * General service functions 1580 */ 1581 1582/* Return true if succeeded to acquire the lock */ 1583static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1584{ 1585 u32 lock_status; 1586 u32 resource_bit = (1 << resource); 1587 int func = BP_FUNC(bp); 1588 u32 hw_lock_control_reg; 1589 1590 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1591 "Trying to take a lock on resource %d\n", resource); 1592 1593 /* Validating that the resource is within range */ 1594 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1595 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1596 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1597 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1598 return false; 1599 } 1600 1601 if (func <= 5) 1602 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1603 else 1604 hw_lock_control_reg = 1605 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1606 1607 /* Try to acquire the lock */ 1608 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1609 lock_status = REG_RD(bp, hw_lock_control_reg); 1610 if (lock_status & resource_bit) 1611 return true; 1612 1613 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1614 "Failed to get a lock on resource %d\n", resource); 1615 return false; 1616} 1617 1618/** 1619 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1620 * 1621 * @bp: driver handle 1622 * 1623 * Returns the recovery leader resource id according to the engine this function 1624 * belongs to. Currently only only 2 engines is supported. 1625 */ 1626static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1627{ 1628 if (BP_PATH(bp)) 1629 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1630 else 1631 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1632} 1633 1634/** 1635 * bnx2x_trylock_leader_lock- try to aquire a leader lock. 1636 * 1637 * @bp: driver handle 1638 * 1639 * Tries to aquire a leader lock for cuurent engine. 1640 */ 1641static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1642{ 1643 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1644} 1645 1646#ifdef BCM_CNIC 1647static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1648#endif 1649 1650void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1651{ 1652 struct bnx2x *bp = fp->bp; 1653 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1654 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1655 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1656 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj; 1657 1658 DP(BNX2X_MSG_SP, 1659 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1660 fp->index, cid, command, bp->state, 1661 rr_cqe->ramrod_cqe.ramrod_type); 1662 1663 switch (command) { 1664 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1665 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1666 drv_cmd = BNX2X_Q_CMD_UPDATE; 1667 break; 1668 1669 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1670 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1671 drv_cmd = BNX2X_Q_CMD_SETUP; 1672 break; 1673 1674 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1675 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1676 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1677 break; 1678 1679 case (RAMROD_CMD_ID_ETH_HALT): 1680 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1681 drv_cmd = BNX2X_Q_CMD_HALT; 1682 break; 1683 1684 case (RAMROD_CMD_ID_ETH_TERMINATE): 1685 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); 1686 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1687 break; 1688 1689 case (RAMROD_CMD_ID_ETH_EMPTY): 1690 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1691 drv_cmd = BNX2X_Q_CMD_EMPTY; 1692 break; 1693 1694 default: 1695 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1696 command, fp->index); 1697 return; 1698 } 1699 1700 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1701 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1702 /* q_obj->complete_cmd() failure means that this was 1703 * an unexpected completion. 1704 * 1705 * In this case we don't want to increase the bp->spq_left 1706 * because apparently we haven't sent this command the first 1707 * place. 1708 */ 1709#ifdef BNX2X_STOP_ON_ERROR 1710 bnx2x_panic(); 1711#else 1712 return; 1713#endif 1714 1715 smp_mb__before_atomic_inc(); 1716 atomic_inc(&bp->cq_spq_left); 1717 /* push the change in bp->spq_left and towards the memory */ 1718 smp_mb__after_atomic_inc(); 1719 1720 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1721 1722 return; 1723} 1724 1725void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 1726 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) 1727{ 1728 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; 1729 1730 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, 1731 start); 1732} 1733 1734irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1735{ 1736 struct bnx2x *bp = netdev_priv(dev_instance); 1737 u16 status = bnx2x_ack_int(bp); 1738 u16 mask; 1739 int i; 1740 u8 cos; 1741 1742 /* Return here if interrupt is shared and it's not for us */ 1743 if (unlikely(status == 0)) { 1744 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1745 return IRQ_NONE; 1746 } 1747 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1748 1749#ifdef BNX2X_STOP_ON_ERROR 1750 if (unlikely(bp->panic)) 1751 return IRQ_HANDLED; 1752#endif 1753 1754 for_each_eth_queue(bp, i) { 1755 struct bnx2x_fastpath *fp = &bp->fp[i]; 1756 1757 mask = 0x2 << (fp->index + CNIC_PRESENT); 1758 if (status & mask) { 1759 /* Handle Rx or Tx according to SB id */ 1760 prefetch(fp->rx_cons_sb); 1761 for_each_cos_in_tx_queue(fp, cos) 1762 prefetch(fp->txdata[cos].tx_cons_sb); 1763 prefetch(&fp->sb_running_index[SM_RX_ID]); 1764 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 1765 status &= ~mask; 1766 } 1767 } 1768 1769#ifdef BCM_CNIC 1770 mask = 0x2; 1771 if (status & (mask | 0x1)) { 1772 struct cnic_ops *c_ops = NULL; 1773 1774 if (likely(bp->state == BNX2X_STATE_OPEN)) { 1775 rcu_read_lock(); 1776 c_ops = rcu_dereference(bp->cnic_ops); 1777 if (c_ops) 1778 c_ops->cnic_handler(bp->cnic_data, NULL); 1779 rcu_read_unlock(); 1780 } 1781 1782 status &= ~mask; 1783 } 1784#endif 1785 1786 if (unlikely(status & 0x1)) { 1787 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1788 1789 status &= ~0x1; 1790 if (!status) 1791 return IRQ_HANDLED; 1792 } 1793 1794 if (unlikely(status)) 1795 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1796 status); 1797 1798 return IRQ_HANDLED; 1799} 1800 1801/* Link */ 1802 1803/* 1804 * General service functions 1805 */ 1806 1807int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 1808{ 1809 u32 lock_status; 1810 u32 resource_bit = (1 << resource); 1811 int func = BP_FUNC(bp); 1812 u32 hw_lock_control_reg; 1813 int cnt; 1814 1815 /* Validating that the resource is within range */ 1816 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1817 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1818 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1819 return -EINVAL; 1820 } 1821 1822 if (func <= 5) { 1823 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1824 } else { 1825 hw_lock_control_reg = 1826 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1827 } 1828 1829 /* Validating that the resource is not already taken */ 1830 lock_status = REG_RD(bp, hw_lock_control_reg); 1831 if (lock_status & resource_bit) { 1832 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", 1833 lock_status, resource_bit); 1834 return -EEXIST; 1835 } 1836 1837 /* Try for 5 second every 5ms */ 1838 for (cnt = 0; cnt < 1000; cnt++) { 1839 /* Try to acquire the lock */ 1840 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1841 lock_status = REG_RD(bp, hw_lock_control_reg); 1842 if (lock_status & resource_bit) 1843 return 0; 1844 1845 msleep(5); 1846 } 1847 BNX2X_ERR("Timeout\n"); 1848 return -EAGAIN; 1849} 1850 1851int bnx2x_release_leader_lock(struct bnx2x *bp) 1852{ 1853 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1854} 1855 1856int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 1857{ 1858 u32 lock_status; 1859 u32 resource_bit = (1 << resource); 1860 int func = BP_FUNC(bp); 1861 u32 hw_lock_control_reg; 1862 1863 /* Validating that the resource is within range */ 1864 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1865 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1866 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1867 return -EINVAL; 1868 } 1869 1870 if (func <= 5) { 1871 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1872 } else { 1873 hw_lock_control_reg = 1874 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1875 } 1876 1877 /* Validating that the resource is currently taken */ 1878 lock_status = REG_RD(bp, hw_lock_control_reg); 1879 if (!(lock_status & resource_bit)) { 1880 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n", 1881 lock_status, resource_bit); 1882 return -EFAULT; 1883 } 1884 1885 REG_WR(bp, hw_lock_control_reg, resource_bit); 1886 return 0; 1887} 1888 1889 1890int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 1891{ 1892 /* The GPIO should be swapped if swap register is set and active */ 1893 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1894 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1895 int gpio_shift = gpio_num + 1896 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1897 u32 gpio_mask = (1 << gpio_shift); 1898 u32 gpio_reg; 1899 int value; 1900 1901 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1902 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1903 return -EINVAL; 1904 } 1905 1906 /* read GPIO value */ 1907 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1908 1909 /* get the requested pin value */ 1910 if ((gpio_reg & gpio_mask) == gpio_mask) 1911 value = 1; 1912 else 1913 value = 0; 1914 1915 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); 1916 1917 return value; 1918} 1919 1920int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 1921{ 1922 /* The GPIO should be swapped if swap register is set and active */ 1923 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1924 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1925 int gpio_shift = gpio_num + 1926 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1927 u32 gpio_mask = (1 << gpio_shift); 1928 u32 gpio_reg; 1929 1930 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1931 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1932 return -EINVAL; 1933 } 1934 1935 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1936 /* read GPIO and mask except the float bits */ 1937 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 1938 1939 switch (mode) { 1940 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1941 DP(NETIF_MSG_LINK, 1942 "Set GPIO %d (shift %d) -> output low\n", 1943 gpio_num, gpio_shift); 1944 /* clear FLOAT and set CLR */ 1945 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1946 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 1947 break; 1948 1949 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 1950 DP(NETIF_MSG_LINK, 1951 "Set GPIO %d (shift %d) -> output high\n", 1952 gpio_num, gpio_shift); 1953 /* clear FLOAT and set SET */ 1954 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1955 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 1956 break; 1957 1958 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 1959 DP(NETIF_MSG_LINK, 1960 "Set GPIO %d (shift %d) -> input\n", 1961 gpio_num, gpio_shift); 1962 /* set FLOAT */ 1963 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1964 break; 1965 1966 default: 1967 break; 1968 } 1969 1970 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 1971 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1972 1973 return 0; 1974} 1975 1976int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 1977{ 1978 u32 gpio_reg = 0; 1979 int rc = 0; 1980 1981 /* Any port swapping should be handled by caller. */ 1982 1983 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1984 /* read GPIO and mask except the float bits */ 1985 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1986 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 1987 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 1988 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 1989 1990 switch (mode) { 1991 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1992 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 1993 /* set CLR */ 1994 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 1995 break; 1996 1997 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 1998 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 1999 /* set SET */ 2000 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2001 break; 2002 2003 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2004 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2005 /* set FLOAT */ 2006 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2007 break; 2008 2009 default: 2010 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2011 rc = -EINVAL; 2012 break; 2013 } 2014 2015 if (rc == 0) 2016 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2017 2018 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2019 2020 return rc; 2021} 2022 2023int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2024{ 2025 /* The GPIO should be swapped if swap register is set and active */ 2026 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2027 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2028 int gpio_shift = gpio_num + 2029 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2030 u32 gpio_mask = (1 << gpio_shift); 2031 u32 gpio_reg; 2032 2033 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2034 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2035 return -EINVAL; 2036 } 2037 2038 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2039 /* read GPIO int */ 2040 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2041 2042 switch (mode) { 2043 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2044 DP(NETIF_MSG_LINK, 2045 "Clear GPIO INT %d (shift %d) -> output low\n", 2046 gpio_num, gpio_shift); 2047 /* clear SET and set CLR */ 2048 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2049 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2050 break; 2051 2052 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2053 DP(NETIF_MSG_LINK, 2054 "Set GPIO INT %d (shift %d) -> output high\n", 2055 gpio_num, gpio_shift); 2056 /* clear CLR and set SET */ 2057 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2058 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2059 break; 2060 2061 default: 2062 break; 2063 } 2064 2065 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2066 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2067 2068 return 0; 2069} 2070 2071static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) 2072{ 2073 u32 spio_mask = (1 << spio_num); 2074 u32 spio_reg; 2075 2076 if ((spio_num < MISC_REGISTERS_SPIO_4) || 2077 (spio_num > MISC_REGISTERS_SPIO_7)) { 2078 BNX2X_ERR("Invalid SPIO %d\n", spio_num); 2079 return -EINVAL; 2080 } 2081 2082 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2083 /* read SPIO and mask except the float bits */ 2084 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); 2085 2086 switch (mode) { 2087 case MISC_REGISTERS_SPIO_OUTPUT_LOW: 2088 DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num); 2089 /* clear FLOAT and set CLR */ 2090 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2091 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); 2092 break; 2093 2094 case MISC_REGISTERS_SPIO_OUTPUT_HIGH: 2095 DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num); 2096 /* clear FLOAT and set SET */ 2097 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2098 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); 2099 break; 2100 2101 case MISC_REGISTERS_SPIO_INPUT_HI_Z: 2102 DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num); 2103 /* set FLOAT */ 2104 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2105 break; 2106 2107 default: 2108 break; 2109 } 2110 2111 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2112 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2113 2114 return 0; 2115} 2116 2117void bnx2x_calc_fc_adv(struct bnx2x *bp) 2118{ 2119 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2120 switch (bp->link_vars.ieee_fc & 2121 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2122 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 2123 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2124 ADVERTISED_Pause); 2125 break; 2126 2127 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2128 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2129 ADVERTISED_Pause); 2130 break; 2131 2132 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2133 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2134 break; 2135 2136 default: 2137 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2138 ADVERTISED_Pause); 2139 break; 2140 } 2141} 2142 2143u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2144{ 2145 if (!BP_NOMCP(bp)) { 2146 u8 rc; 2147 int cfx_idx = bnx2x_get_link_cfg_idx(bp); 2148 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2149 /* 2150 * Initialize link parameters structure variables 2151 * It is recommended to turn off RX FC for jumbo frames 2152 * for better performance 2153 */ 2154 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2155 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2156 else 2157 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2158 2159 bnx2x_acquire_phy_lock(bp); 2160 2161 if (load_mode == LOAD_DIAG) { 2162 struct link_params *lp = &bp->link_params; 2163 lp->loopback_mode = LOOPBACK_XGXS; 2164 /* do PHY loopback at 10G speed, if possible */ 2165 if (lp->req_line_speed[cfx_idx] < SPEED_10000) { 2166 if (lp->speed_cap_mask[cfx_idx] & 2167 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2168 lp->req_line_speed[cfx_idx] = 2169 SPEED_10000; 2170 else 2171 lp->req_line_speed[cfx_idx] = 2172 SPEED_1000; 2173 } 2174 } 2175 2176 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2177 2178 bnx2x_release_phy_lock(bp); 2179 2180 bnx2x_calc_fc_adv(bp); 2181 2182 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { 2183 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2184 bnx2x_link_report(bp); 2185 } else 2186 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2187 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2188 return rc; 2189 } 2190 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2191 return -EINVAL; 2192} 2193 2194void bnx2x_link_set(struct bnx2x *bp) 2195{ 2196 if (!BP_NOMCP(bp)) { 2197 bnx2x_acquire_phy_lock(bp); 2198 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2199 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2200 bnx2x_release_phy_lock(bp); 2201 2202 bnx2x_calc_fc_adv(bp); 2203 } else 2204 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2205} 2206 2207static void bnx2x__link_reset(struct bnx2x *bp) 2208{ 2209 if (!BP_NOMCP(bp)) { 2210 bnx2x_acquire_phy_lock(bp); 2211 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2212 bnx2x_release_phy_lock(bp); 2213 } else 2214 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2215} 2216 2217u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2218{ 2219 u8 rc = 0; 2220 2221 if (!BP_NOMCP(bp)) { 2222 bnx2x_acquire_phy_lock(bp); 2223 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2224 is_serdes); 2225 bnx2x_release_phy_lock(bp); 2226 } else 2227 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2228 2229 return rc; 2230} 2231 2232static void bnx2x_init_port_minmax(struct bnx2x *bp) 2233{ 2234 u32 r_param = bp->link_vars.line_speed / 8; 2235 u32 fair_periodic_timeout_usec; 2236 u32 t_fair; 2237 2238 memset(&(bp->cmng.rs_vars), 0, 2239 sizeof(struct rate_shaping_vars_per_port)); 2240 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port)); 2241 2242 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ 2243 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4; 2244 2245 /* this is the threshold below which no timer arming will occur 2246 1.25 coefficient is for the threshold to be a little bigger 2247 than the real time, to compensate for timer in-accuracy */ 2248 bp->cmng.rs_vars.rs_threshold = 2249 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; 2250 2251 /* resolution of fairness timer */ 2252 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; 2253 /* for 10G it is 1000usec. for 1G it is 10000usec. */ 2254 t_fair = T_FAIR_COEF / bp->link_vars.line_speed; 2255 2256 /* this is the threshold below which we won't arm the timer anymore */ 2257 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES; 2258 2259 /* we multiply by 1e3/8 to get bytes/msec. 2260 We don't want the credits to pass a credit 2261 of the t_fair*FAIR_MEM (algorithm resolution) */ 2262 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM; 2263 /* since each tick is 4 usec */ 2264 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4; 2265} 2266 2267/* Calculates the sum of vn_min_rates. 2268 It's needed for further normalizing of the min_rates. 2269 Returns: 2270 sum of vn_min_rates. 2271 or 2272 0 - if all the min_rates are 0. 2273 In the later case fainess algorithm should be deactivated. 2274 If not all min_rates are zero then those that are zeroes will be set to 1. 2275 */ 2276static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) 2277{ 2278 int all_zero = 1; 2279 int vn; 2280 2281 bp->vn_weight_sum = 0; 2282 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2283 u32 vn_cfg = bp->mf_config[vn]; 2284 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2285 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2286 2287 /* Skip hidden vns */ 2288 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2289 continue; 2290 2291 /* If min rate is zero - set it to 1 */ 2292 if (!vn_min_rate) 2293 vn_min_rate = DEF_MIN_RATE; 2294 else 2295 all_zero = 0; 2296 2297 bp->vn_weight_sum += vn_min_rate; 2298 } 2299 2300 /* if ETS or all min rates are zeros - disable fairness */ 2301 if (BNX2X_IS_ETS_ENABLED(bp)) { 2302 bp->cmng.flags.cmng_enables &= 2303 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2304 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2305 } else if (all_zero) { 2306 bp->cmng.flags.cmng_enables &= 2307 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2308 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2309 " fairness will be disabled\n"); 2310 } else 2311 bp->cmng.flags.cmng_enables |= 2312 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2313} 2314 2315static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) 2316{ 2317 struct rate_shaping_vars_per_vn m_rs_vn; 2318 struct fairness_vars_per_vn m_fair_vn; 2319 u32 vn_cfg = bp->mf_config[vn]; 2320 int func = func_by_vn(bp, vn); 2321 u16 vn_min_rate, vn_max_rate; 2322 int i; 2323 2324 /* If function is hidden - set min and max to zeroes */ 2325 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 2326 vn_min_rate = 0; 2327 vn_max_rate = 0; 2328 2329 } else { 2330 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2331 2332 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2333 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2334 /* If fairness is enabled (not all min rates are zeroes) and 2335 if current min rate is zero - set it to 1. 2336 This is a requirement of the algorithm. */ 2337 if (bp->vn_weight_sum && (vn_min_rate == 0)) 2338 vn_min_rate = DEF_MIN_RATE; 2339 2340 if (IS_MF_SI(bp)) 2341 /* maxCfg in percents of linkspeed */ 2342 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2343 else 2344 /* maxCfg is absolute in 100Mb units */ 2345 vn_max_rate = maxCfg * 100; 2346 } 2347 2348 DP(NETIF_MSG_IFUP, 2349 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n", 2350 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); 2351 2352 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn)); 2353 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); 2354 2355 /* global vn counter - maximal Mbps for this vn */ 2356 m_rs_vn.vn_counter.rate = vn_max_rate; 2357 2358 /* quota - number of bytes transmitted in this period */ 2359 m_rs_vn.vn_counter.quota = 2360 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8; 2361 2362 if (bp->vn_weight_sum) { 2363 /* credit for each period of the fairness algorithm: 2364 number of bytes in T_FAIR (the vn share the port rate). 2365 vn_weight_sum should not be larger than 10000, thus 2366 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater 2367 than zero */ 2368 m_fair_vn.vn_credit_delta = 2369 max_t(u32, (vn_min_rate * (T_FAIR_COEF / 2370 (8 * bp->vn_weight_sum))), 2371 (bp->cmng.fair_vars.fair_threshold + 2372 MIN_ABOVE_THRESH)); 2373 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n", 2374 m_fair_vn.vn_credit_delta); 2375 } 2376 2377 /* Store it to internal memory */ 2378 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++) 2379 REG_WR(bp, BAR_XSTRORM_INTMEM + 2380 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4, 2381 ((u32 *)(&m_rs_vn))[i]); 2382 2383 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++) 2384 REG_WR(bp, BAR_XSTRORM_INTMEM + 2385 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4, 2386 ((u32 *)(&m_fair_vn))[i]); 2387} 2388 2389static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2390{ 2391 if (CHIP_REV_IS_SLOW(bp)) 2392 return CMNG_FNS_NONE; 2393 if (IS_MF(bp)) 2394 return CMNG_FNS_MINMAX; 2395 2396 return CMNG_FNS_NONE; 2397} 2398 2399void bnx2x_read_mf_cfg(struct bnx2x *bp) 2400{ 2401 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2402 2403 if (BP_NOMCP(bp)) 2404 return; /* what should be the default bvalue in this case */ 2405 2406 /* For 2 port configuration the absolute function number formula 2407 * is: 2408 * abs_func = 2 * vn + BP_PORT + BP_PATH 2409 * 2410 * and there are 4 functions per port 2411 * 2412 * For 4 port configuration it is 2413 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2414 * 2415 * and there are 2 functions per port 2416 */ 2417 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2418 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2419 2420 if (func >= E1H_FUNC_MAX) 2421 break; 2422 2423 bp->mf_config[vn] = 2424 MF_CFG_RD(bp, func_mf_config[func].config); 2425 } 2426} 2427 2428static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2429{ 2430 2431 if (cmng_type == CMNG_FNS_MINMAX) { 2432 int vn; 2433 2434 /* clear cmng_enables */ 2435 bp->cmng.flags.cmng_enables = 0; 2436 2437 /* read mf conf from shmem */ 2438 if (read_cfg) 2439 bnx2x_read_mf_cfg(bp); 2440 2441 /* Init rate shaping and fairness contexts */ 2442 bnx2x_init_port_minmax(bp); 2443 2444 /* vn_weight_sum and enable fairness if not 0 */ 2445 bnx2x_calc_vn_weight_sum(bp); 2446 2447 /* calculate and set min-max rate for each vn */ 2448 if (bp->port.pmf) 2449 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) 2450 bnx2x_init_vn_minmax(bp, vn); 2451 2452 /* always enable rate shaping and fairness */ 2453 bp->cmng.flags.cmng_enables |= 2454 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2455 if (!bp->vn_weight_sum) 2456 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2457 " fairness will be disabled\n"); 2458 return; 2459 } 2460 2461 /* rate shaping and fairness are disabled */ 2462 DP(NETIF_MSG_IFUP, 2463 "rate shaping and fairness are disabled\n"); 2464} 2465 2466/* This function is called upon link interrupt */ 2467static void bnx2x_link_attn(struct bnx2x *bp) 2468{ 2469 /* Make sure that we are synced with the current statistics */ 2470 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2471 2472 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2473 2474 if (bp->link_vars.link_up) { 2475 2476 /* dropless flow control */ 2477 if (!CHIP_IS_E1(bp) && bp->dropless_fc) { 2478 int port = BP_PORT(bp); 2479 u32 pause_enabled = 0; 2480 2481 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2482 pause_enabled = 1; 2483 2484 REG_WR(bp, BAR_USTRORM_INTMEM + 2485 USTORM_ETH_PAUSE_ENABLED_OFFSET(port), 2486 pause_enabled); 2487 } 2488 2489 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2490 struct host_port_stats *pstats; 2491 2492 pstats = bnx2x_sp(bp, port_stats); 2493 /* reset old mac stats */ 2494 memset(&(pstats->mac_stx[0]), 0, 2495 sizeof(struct mac_stx)); 2496 } 2497 if (bp->state == BNX2X_STATE_OPEN) 2498 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2499 } 2500 2501 if (bp->link_vars.link_up && bp->link_vars.line_speed) { 2502 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2503 2504 if (cmng_fns != CMNG_FNS_NONE) { 2505 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2506 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2507 } else 2508 /* rate shaping and fairness are disabled */ 2509 DP(NETIF_MSG_IFUP, 2510 "single function mode without fairness\n"); 2511 } 2512 2513 __bnx2x_link_report(bp); 2514 2515 if (IS_MF(bp)) 2516 bnx2x_link_sync_notify(bp); 2517} 2518 2519void bnx2x__link_status_update(struct bnx2x *bp) 2520{ 2521 if (bp->state != BNX2X_STATE_OPEN) 2522 return; 2523 2524 /* read updated dcb configuration */ 2525 bnx2x_dcbx_pmf_update(bp); 2526 2527 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2528 2529 if (bp->link_vars.link_up) 2530 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2531 else 2532 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2533 2534 /* indicate link status */ 2535 bnx2x_link_report(bp); 2536} 2537 2538static void bnx2x_pmf_update(struct bnx2x *bp) 2539{ 2540 int port = BP_PORT(bp); 2541 u32 val; 2542 2543 bp->port.pmf = 1; 2544 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); 2545 2546 /* 2547 * We need the mb() to ensure the ordering between the writing to 2548 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2549 */ 2550 smp_mb(); 2551 2552 /* queue a periodic task */ 2553 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2554 2555 bnx2x_dcbx_pmf_update(bp); 2556 2557 /* enable nig attention */ 2558 val = (0xff0f | (1 << (BP_VN(bp) + 4))); 2559 if (bp->common.int_block == INT_BLOCK_HC) { 2560 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 2561 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 2562 } else if (!CHIP_IS_E1x(bp)) { 2563 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 2564 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 2565 } 2566 2567 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 2568} 2569 2570/* end of Link */ 2571 2572/* slow path */ 2573 2574/* 2575 * General service functions 2576 */ 2577 2578/* send the MCP a request, block until there is a reply */ 2579u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 2580{ 2581 int mb_idx = BP_FW_MB_IDX(bp); 2582 u32 seq; 2583 u32 rc = 0; 2584 u32 cnt = 1; 2585 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 2586 2587 mutex_lock(&bp->fw_mb_mutex); 2588 seq = ++bp->fw_seq; 2589 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 2590 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 2591 2592 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 2593 (command | seq), param); 2594 2595 do { 2596 /* let the FW do it's magic ... */ 2597 msleep(delay); 2598 2599 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 2600 2601 /* Give the FW up to 5 second (500*10ms) */ 2602 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2603 2604 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 2605 cnt*delay, rc, seq); 2606 2607 /* is this a reply to our command? */ 2608 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 2609 rc &= FW_MSG_CODE_MASK; 2610 else { 2611 /* FW BUG! */ 2612 BNX2X_ERR("FW failed to respond!\n"); 2613 bnx2x_fw_dump(bp); 2614 rc = 0; 2615 } 2616 mutex_unlock(&bp->fw_mb_mutex); 2617 2618 return rc; 2619} 2620 2621 2622void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 2623{ 2624 if (CHIP_IS_E1x(bp)) { 2625 struct tstorm_eth_function_common_config tcfg = {0}; 2626 2627 storm_memset_func_cfg(bp, &tcfg, p->func_id); 2628 } 2629 2630 /* Enable the function in the FW */ 2631 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 2632 storm_memset_func_en(bp, p->func_id, 1); 2633 2634 /* spq */ 2635 if (p->func_flgs & FUNC_FLG_SPQ) { 2636 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 2637 REG_WR(bp, XSEM_REG_FAST_MEMORY + 2638 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 2639 } 2640} 2641 2642/** 2643 * bnx2x_get_tx_only_flags - Return common flags 2644 * 2645 * @bp device handle 2646 * @fp queue handle 2647 * @zero_stats TRUE if statistics zeroing is needed 2648 * 2649 * Return the flags that are common for the Tx-only and not normal connections. 2650 */ 2651static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 2652 struct bnx2x_fastpath *fp, 2653 bool zero_stats) 2654{ 2655 unsigned long flags = 0; 2656 2657 /* PF driver will always initialize the Queue to an ACTIVE state */ 2658 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 2659 2660 /* tx only connections collect statistics (on the same index as the 2661 * parent connection). The statistics are zeroed when the parent 2662 * connection is initialized. 2663 */ 2664 2665 __set_bit(BNX2X_Q_FLG_STATS, &flags); 2666 if (zero_stats) 2667 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 2668 2669 2670 return flags; 2671} 2672 2673static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 2674 struct bnx2x_fastpath *fp, 2675 bool leading) 2676{ 2677 unsigned long flags = 0; 2678 2679 /* calculate other queue flags */ 2680 if (IS_MF_SD(bp)) 2681 __set_bit(BNX2X_Q_FLG_OV, &flags); 2682 2683 if (IS_FCOE_FP(fp)) 2684 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 2685 2686 if (!fp->disable_tpa) { 2687 __set_bit(BNX2X_Q_FLG_TPA, &flags); 2688 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 2689 if (fp->mode == TPA_MODE_GRO) 2690 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); 2691 } 2692 2693 if (leading) { 2694 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 2695 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 2696 } 2697 2698 /* Always set HW VLAN stripping */ 2699 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 2700 2701 2702 return flags | bnx2x_get_common_flags(bp, fp, true); 2703} 2704 2705static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 2706 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 2707 u8 cos) 2708{ 2709 gen_init->stat_id = bnx2x_stats_id(fp); 2710 gen_init->spcl_id = fp->cl_id; 2711 2712 /* Always use mini-jumbo MTU for FCoE L2 ring */ 2713 if (IS_FCOE_FP(fp)) 2714 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 2715 else 2716 gen_init->mtu = bp->dev->mtu; 2717 2718 gen_init->cos = cos; 2719} 2720 2721static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 2722 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 2723 struct bnx2x_rxq_setup_params *rxq_init) 2724{ 2725 u8 max_sge = 0; 2726 u16 sge_sz = 0; 2727 u16 tpa_agg_size = 0; 2728 2729 if (!fp->disable_tpa) { 2730 pause->sge_th_lo = SGE_TH_LO(bp); 2731 pause->sge_th_hi = SGE_TH_HI(bp); 2732 2733 /* validate SGE ring has enough to cross high threshold */ 2734 WARN_ON(bp->dropless_fc && 2735 pause->sge_th_hi + FW_PREFETCH_CNT > 2736 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); 2737 2738 tpa_agg_size = min_t(u32, 2739 (min_t(u32, 8, MAX_SKB_FRAGS) * 2740 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); 2741 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 2742 SGE_PAGE_SHIFT; 2743 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 2744 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 2745 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, 2746 0xffff); 2747 } 2748 2749 /* pause - not for e1 */ 2750 if (!CHIP_IS_E1(bp)) { 2751 pause->bd_th_lo = BD_TH_LO(bp); 2752 pause->bd_th_hi = BD_TH_HI(bp); 2753 2754 pause->rcq_th_lo = RCQ_TH_LO(bp); 2755 pause->rcq_th_hi = RCQ_TH_HI(bp); 2756 /* 2757 * validate that rings have enough entries to cross 2758 * high thresholds 2759 */ 2760 WARN_ON(bp->dropless_fc && 2761 pause->bd_th_hi + FW_PREFETCH_CNT > 2762 bp->rx_ring_size); 2763 WARN_ON(bp->dropless_fc && 2764 pause->rcq_th_hi + FW_PREFETCH_CNT > 2765 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); 2766 2767 pause->pri_map = 1; 2768 } 2769 2770 /* rxq setup */ 2771 rxq_init->dscr_map = fp->rx_desc_mapping; 2772 rxq_init->sge_map = fp->rx_sge_mapping; 2773 rxq_init->rcq_map = fp->rx_comp_mapping; 2774 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 2775 2776 /* This should be a maximum number of data bytes that may be 2777 * placed on the BD (not including paddings). 2778 */ 2779 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - 2780 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; 2781 2782 rxq_init->cl_qzone_id = fp->cl_qzone_id; 2783 rxq_init->tpa_agg_sz = tpa_agg_size; 2784 rxq_init->sge_buf_sz = sge_sz; 2785 rxq_init->max_sges_pkt = max_sge; 2786 rxq_init->rss_engine_id = BP_FUNC(bp); 2787 rxq_init->mcast_engine_id = BP_FUNC(bp); 2788 2789 /* Maximum number or simultaneous TPA aggregation for this Queue. 2790 * 2791 * For PF Clients it should be the maximum avaliable number. 2792 * VF driver(s) may want to define it to a smaller value. 2793 */ 2794 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); 2795 2796 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 2797 rxq_init->fw_sb_id = fp->fw_sb_id; 2798 2799 if (IS_FCOE_FP(fp)) 2800 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 2801 else 2802 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 2803} 2804 2805static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 2806 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 2807 u8 cos) 2808{ 2809 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping; 2810 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 2811 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 2812 txq_init->fw_sb_id = fp->fw_sb_id; 2813 2814 /* 2815 * set the tss leading client id for TX classfication == 2816 * leading RSS client id 2817 */ 2818 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 2819 2820 if (IS_FCOE_FP(fp)) { 2821 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 2822 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 2823 } 2824} 2825 2826static void bnx2x_pf_init(struct bnx2x *bp) 2827{ 2828 struct bnx2x_func_init_params func_init = {0}; 2829 struct event_ring_data eq_data = { {0} }; 2830 u16 flags; 2831 2832 if (!CHIP_IS_E1x(bp)) { 2833 /* reset IGU PF statistics: MSIX + ATTN */ 2834 /* PF */ 2835 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2836 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2837 (CHIP_MODE_IS_4_PORT(bp) ? 2838 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2839 /* ATTN */ 2840 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2841 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2842 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 2843 (CHIP_MODE_IS_4_PORT(bp) ? 2844 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2845 } 2846 2847 /* function setup flags */ 2848 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 2849 2850 /* This flag is relevant for E1x only. 2851 * E2 doesn't have a TPA configuration in a function level. 2852 */ 2853 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; 2854 2855 func_init.func_flgs = flags; 2856 func_init.pf_id = BP_FUNC(bp); 2857 func_init.func_id = BP_FUNC(bp); 2858 func_init.spq_map = bp->spq_mapping; 2859 func_init.spq_prod = bp->spq_prod_idx; 2860 2861 bnx2x_func_init(bp, &func_init); 2862 2863 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 2864 2865 /* 2866 * Congestion management values depend on the link rate 2867 * There is no active link so initial link rate is set to 10 Gbps. 2868 * When the link comes up The congestion management values are 2869 * re-calculated according to the actual link rate. 2870 */ 2871 bp->link_vars.line_speed = SPEED_10000; 2872 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 2873 2874 /* Only the PMF sets the HW */ 2875 if (bp->port.pmf) 2876 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2877 2878 /* init Event Queue */ 2879 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 2880 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 2881 eq_data.producer = bp->eq_prod; 2882 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 2883 eq_data.sb_id = DEF_SB_ID; 2884 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 2885} 2886 2887 2888static void bnx2x_e1h_disable(struct bnx2x *bp) 2889{ 2890 int port = BP_PORT(bp); 2891 2892 bnx2x_tx_disable(bp); 2893 2894 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 2895} 2896 2897static void bnx2x_e1h_enable(struct bnx2x *bp) 2898{ 2899 int port = BP_PORT(bp); 2900 2901 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 2902 2903 /* Tx queue should be only reenabled */ 2904 netif_tx_wake_all_queues(bp->dev); 2905 2906 /* 2907 * Should not call netif_carrier_on since it will be called if the link 2908 * is up when checking for link state 2909 */ 2910} 2911 2912#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 2913 2914static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) 2915{ 2916 struct eth_stats_info *ether_stat = 2917 &bp->slowpath->drv_info_to_mcp.ether_stat; 2918 2919 /* leave last char as NULL */ 2920 memcpy(ether_stat->version, DRV_MODULE_VERSION, 2921 ETH_STAT_INFO_VERSION_LEN - 1); 2922 2923 bp->fp[0].mac_obj.get_n_elements(bp, &bp->fp[0].mac_obj, 2924 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 2925 ether_stat->mac_local); 2926 2927 ether_stat->mtu_size = bp->dev->mtu; 2928 2929 if (bp->dev->features & NETIF_F_RXCSUM) 2930 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 2931 if (bp->dev->features & NETIF_F_TSO) 2932 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 2933 ether_stat->feature_flags |= bp->common.boot_mode; 2934 2935 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; 2936 2937 ether_stat->txq_size = bp->tx_ring_size; 2938 ether_stat->rxq_size = bp->rx_ring_size; 2939} 2940 2941static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) 2942{ 2943#ifdef BCM_CNIC 2944 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 2945 struct fcoe_stats_info *fcoe_stat = 2946 &bp->slowpath->drv_info_to_mcp.fcoe_stat; 2947 2948 memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN); 2949 2950 fcoe_stat->qos_priority = 2951 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; 2952 2953 /* insert FCoE stats from ramrod response */ 2954 if (!NO_FCOE(bp)) { 2955 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = 2956 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2957 tstorm_queue_statistics; 2958 2959 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = 2960 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2961 xstorm_queue_statistics; 2962 2963 struct fcoe_statistics_params *fw_fcoe_stat = 2964 &bp->fw_stats_data->fcoe; 2965 2966 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo, 2967 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); 2968 2969 ADD_64(fcoe_stat->rx_bytes_hi, 2970 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, 2971 fcoe_stat->rx_bytes_lo, 2972 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); 2973 2974 ADD_64(fcoe_stat->rx_bytes_hi, 2975 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, 2976 fcoe_stat->rx_bytes_lo, 2977 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); 2978 2979 ADD_64(fcoe_stat->rx_bytes_hi, 2980 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, 2981 fcoe_stat->rx_bytes_lo, 2982 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); 2983 2984 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2985 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); 2986 2987 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2988 fcoe_q_tstorm_stats->rcv_ucast_pkts); 2989 2990 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2991 fcoe_q_tstorm_stats->rcv_bcast_pkts); 2992 2993 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2994 fcoe_q_tstorm_stats->rcv_mcast_pkts); 2995 2996 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo, 2997 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); 2998 2999 ADD_64(fcoe_stat->tx_bytes_hi, 3000 fcoe_q_xstorm_stats->ucast_bytes_sent.hi, 3001 fcoe_stat->tx_bytes_lo, 3002 fcoe_q_xstorm_stats->ucast_bytes_sent.lo); 3003 3004 ADD_64(fcoe_stat->tx_bytes_hi, 3005 fcoe_q_xstorm_stats->bcast_bytes_sent.hi, 3006 fcoe_stat->tx_bytes_lo, 3007 fcoe_q_xstorm_stats->bcast_bytes_sent.lo); 3008 3009 ADD_64(fcoe_stat->tx_bytes_hi, 3010 fcoe_q_xstorm_stats->mcast_bytes_sent.hi, 3011 fcoe_stat->tx_bytes_lo, 3012 fcoe_q_xstorm_stats->mcast_bytes_sent.lo); 3013 3014 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3015 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); 3016 3017 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3018 fcoe_q_xstorm_stats->ucast_pkts_sent); 3019 3020 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3021 fcoe_q_xstorm_stats->bcast_pkts_sent); 3022 3023 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3024 fcoe_q_xstorm_stats->mcast_pkts_sent); 3025 } 3026 3027 /* ask L5 driver to add data to the struct */ 3028 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); 3029#endif 3030} 3031 3032static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) 3033{ 3034#ifdef BCM_CNIC 3035 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3036 struct iscsi_stats_info *iscsi_stat = 3037 &bp->slowpath->drv_info_to_mcp.iscsi_stat; 3038 3039 memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); 3040 3041 iscsi_stat->qos_priority = 3042 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; 3043 3044 /* ask L5 driver to add data to the struct */ 3045 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); 3046#endif 3047} 3048 3049/* called due to MCP event (on pmf): 3050 * reread new bandwidth configuration 3051 * configure FW 3052 * notify others function about the change 3053 */ 3054static inline void bnx2x_config_mf_bw(struct bnx2x *bp) 3055{ 3056 if (bp->link_vars.link_up) { 3057 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 3058 bnx2x_link_sync_notify(bp); 3059 } 3060 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3061} 3062 3063static inline void bnx2x_set_mf_bw(struct bnx2x *bp) 3064{ 3065 bnx2x_config_mf_bw(bp); 3066 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 3067} 3068 3069static void bnx2x_handle_drv_info_req(struct bnx2x *bp) 3070{ 3071 enum drv_info_opcode op_code; 3072 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); 3073 3074 /* if drv_info version supported by MFW doesn't match - send NACK */ 3075 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 3076 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3077 return; 3078 } 3079 3080 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 3081 DRV_INFO_CONTROL_OP_CODE_SHIFT; 3082 3083 memset(&bp->slowpath->drv_info_to_mcp, 0, 3084 sizeof(union drv_info_to_mcp)); 3085 3086 switch (op_code) { 3087 case ETH_STATS_OPCODE: 3088 bnx2x_drv_info_ether_stat(bp); 3089 break; 3090 case FCOE_STATS_OPCODE: 3091 bnx2x_drv_info_fcoe_stat(bp); 3092 break; 3093 case ISCSI_STATS_OPCODE: 3094 bnx2x_drv_info_iscsi_stat(bp); 3095 break; 3096 default: 3097 /* if op code isn't supported - send NACK */ 3098 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3099 return; 3100 } 3101 3102 /* if we got drv_info attn from MFW then these fields are defined in 3103 * shmem2 for sure 3104 */ 3105 SHMEM2_WR(bp, drv_info_host_addr_lo, 3106 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3107 SHMEM2_WR(bp, drv_info_host_addr_hi, 3108 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3109 3110 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); 3111} 3112 3113static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) 3114{ 3115 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); 3116 3117 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 3118 3119 /* 3120 * This is the only place besides the function initialization 3121 * where the bp->flags can change so it is done without any 3122 * locks 3123 */ 3124 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 3125 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); 3126 bp->flags |= MF_FUNC_DIS; 3127 3128 bnx2x_e1h_disable(bp); 3129 } else { 3130 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); 3131 bp->flags &= ~MF_FUNC_DIS; 3132 3133 bnx2x_e1h_enable(bp); 3134 } 3135 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 3136 } 3137 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 3138 bnx2x_config_mf_bw(bp); 3139 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 3140 } 3141 3142 /* Report results to MCP */ 3143 if (dcc_event) 3144 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); 3145 else 3146 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); 3147} 3148 3149/* must be called under the spq lock */ 3150static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 3151{ 3152 struct eth_spe *next_spe = bp->spq_prod_bd; 3153 3154 if (bp->spq_prod_bd == bp->spq_last_bd) { 3155 bp->spq_prod_bd = bp->spq; 3156 bp->spq_prod_idx = 0; 3157 DP(BNX2X_MSG_SP, "end of spq\n"); 3158 } else { 3159 bp->spq_prod_bd++; 3160 bp->spq_prod_idx++; 3161 } 3162 return next_spe; 3163} 3164 3165/* must be called under the spq lock */ 3166static inline void bnx2x_sp_prod_update(struct bnx2x *bp) 3167{ 3168 int func = BP_FUNC(bp); 3169 3170 /* 3171 * Make sure that BD data is updated before writing the producer: 3172 * BD data is written to the memory, the producer is read from the 3173 * memory, thus we need a full memory barrier to ensure the ordering. 3174 */ 3175 mb(); 3176 3177 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3178 bp->spq_prod_idx); 3179 mmiowb(); 3180} 3181 3182/** 3183 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3184 * 3185 * @cmd: command to check 3186 * @cmd_type: command type 3187 */ 3188static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3189{ 3190 if ((cmd_type == NONE_CONNECTION_TYPE) || 3191 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3192 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3193 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3194 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3195 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3196 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3197 return true; 3198 else 3199 return false; 3200 3201} 3202 3203 3204/** 3205 * bnx2x_sp_post - place a single command on an SP ring 3206 * 3207 * @bp: driver handle 3208 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3209 * @cid: SW CID the command is related to 3210 * @data_hi: command private data address (high 32 bits) 3211 * @data_lo: command private data address (low 32 bits) 3212 * @cmd_type: command type (e.g. NONE, ETH) 3213 * 3214 * SP data is handled as if it's always an address pair, thus data fields are 3215 * not swapped to little endian in upper functions. Instead this function swaps 3216 * data as if it's two u32 fields. 3217 */ 3218int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3219 u32 data_hi, u32 data_lo, int cmd_type) 3220{ 3221 struct eth_spe *spe; 3222 u16 type; 3223 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3224 3225#ifdef BNX2X_STOP_ON_ERROR 3226 if (unlikely(bp->panic)) { 3227 BNX2X_ERR("Can't post SP when there is panic\n"); 3228 return -EIO; 3229 } 3230#endif 3231 3232 spin_lock_bh(&bp->spq_lock); 3233 3234 if (common) { 3235 if (!atomic_read(&bp->eq_spq_left)) { 3236 BNX2X_ERR("BUG! EQ ring full!\n"); 3237 spin_unlock_bh(&bp->spq_lock); 3238 bnx2x_panic(); 3239 return -EBUSY; 3240 } 3241 } else if (!atomic_read(&bp->cq_spq_left)) { 3242 BNX2X_ERR("BUG! SPQ ring full!\n"); 3243 spin_unlock_bh(&bp->spq_lock); 3244 bnx2x_panic(); 3245 return -EBUSY; 3246 } 3247 3248 spe = bnx2x_sp_get_next(bp); 3249 3250 /* CID needs port number to be encoded int it */ 3251 spe->hdr.conn_and_cmd_data = 3252 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3253 HW_CID(bp, cid)); 3254 3255 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; 3256 3257 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3258 SPE_HDR_FUNCTION_ID); 3259 3260 spe->hdr.type = cpu_to_le16(type); 3261 3262 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3263 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3264 3265 /* 3266 * It's ok if the actual decrement is issued towards the memory 3267 * somewhere between the spin_lock and spin_unlock. Thus no 3268 * more explict memory barrier is needed. 3269 */ 3270 if (common) 3271 atomic_dec(&bp->eq_spq_left); 3272 else 3273 atomic_dec(&bp->cq_spq_left); 3274 3275 3276 DP(BNX2X_MSG_SP, 3277 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", 3278 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3279 (u32)(U64_LO(bp->spq_mapping) + 3280 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3281 HW_CID(bp, cid), data_hi, data_lo, type, 3282 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3283 3284 bnx2x_sp_prod_update(bp); 3285 spin_unlock_bh(&bp->spq_lock); 3286 return 0; 3287} 3288 3289/* acquire split MCP access lock register */ 3290static int bnx2x_acquire_alr(struct bnx2x *bp) 3291{ 3292 u32 j, val; 3293 int rc = 0; 3294 3295 might_sleep(); 3296 for (j = 0; j < 1000; j++) { 3297 val = (1UL << 31); 3298 REG_WR(bp, GRCBASE_MCP + 0x9c, val); 3299 val = REG_RD(bp, GRCBASE_MCP + 0x9c); 3300 if (val & (1L << 31)) 3301 break; 3302 3303 msleep(5); 3304 } 3305 if (!(val & (1L << 31))) { 3306 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3307 rc = -EBUSY; 3308 } 3309 3310 return rc; 3311} 3312 3313/* release split MCP access lock register */ 3314static void bnx2x_release_alr(struct bnx2x *bp) 3315{ 3316 REG_WR(bp, GRCBASE_MCP + 0x9c, 0); 3317} 3318 3319#define BNX2X_DEF_SB_ATT_IDX 0x0001 3320#define BNX2X_DEF_SB_IDX 0x0002 3321 3322static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3323{ 3324 struct host_sp_status_block *def_sb = bp->def_status_blk; 3325 u16 rc = 0; 3326 3327 barrier(); /* status block is written to by the chip */ 3328 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3329 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 3330 rc |= BNX2X_DEF_SB_ATT_IDX; 3331 } 3332 3333 if (bp->def_idx != def_sb->sp_sb.running_index) { 3334 bp->def_idx = def_sb->sp_sb.running_index; 3335 rc |= BNX2X_DEF_SB_IDX; 3336 } 3337 3338 /* Do not reorder: indecies reading should complete before handling */ 3339 barrier(); 3340 return rc; 3341} 3342 3343/* 3344 * slow path service functions 3345 */ 3346 3347static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 3348{ 3349 int port = BP_PORT(bp); 3350 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 3351 MISC_REG_AEU_MASK_ATTN_FUNC_0; 3352 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 3353 NIG_REG_MASK_INTERRUPT_PORT0; 3354 u32 aeu_mask; 3355 u32 nig_mask = 0; 3356 u32 reg_addr; 3357 3358 if (bp->attn_state & asserted) 3359 BNX2X_ERR("IGU ERROR\n"); 3360 3361 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3362 aeu_mask = REG_RD(bp, aeu_addr); 3363 3364 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 3365 aeu_mask, asserted); 3366 aeu_mask &= ~(asserted & 0x3ff); 3367 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 3368 3369 REG_WR(bp, aeu_addr, aeu_mask); 3370 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3371 3372 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 3373 bp->attn_state |= asserted; 3374 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 3375 3376 if (asserted & ATTN_HARD_WIRED_MASK) { 3377 if (asserted & ATTN_NIG_FOR_FUNC) { 3378 3379 bnx2x_acquire_phy_lock(bp); 3380 3381 /* save nig interrupt mask */ 3382 nig_mask = REG_RD(bp, nig_int_mask_addr); 3383 3384 /* If nig_mask is not set, no need to call the update 3385 * function. 3386 */ 3387 if (nig_mask) { 3388 REG_WR(bp, nig_int_mask_addr, 0); 3389 3390 bnx2x_link_attn(bp); 3391 } 3392 3393 /* handle unicore attn? */ 3394 } 3395 if (asserted & ATTN_SW_TIMER_4_FUNC) 3396 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 3397 3398 if (asserted & GPIO_2_FUNC) 3399 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 3400 3401 if (asserted & GPIO_3_FUNC) 3402 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 3403 3404 if (asserted & GPIO_4_FUNC) 3405 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 3406 3407 if (port == 0) { 3408 if (asserted & ATTN_GENERAL_ATTN_1) { 3409 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 3410 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 3411 } 3412 if (asserted & ATTN_GENERAL_ATTN_2) { 3413 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 3414 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 3415 } 3416 if (asserted & ATTN_GENERAL_ATTN_3) { 3417 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 3418 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 3419 } 3420 } else { 3421 if (asserted & ATTN_GENERAL_ATTN_4) { 3422 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 3423 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 3424 } 3425 if (asserted & ATTN_GENERAL_ATTN_5) { 3426 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 3427 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 3428 } 3429 if (asserted & ATTN_GENERAL_ATTN_6) { 3430 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 3431 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 3432 } 3433 } 3434 3435 } /* if hardwired */ 3436 3437 if (bp->common.int_block == INT_BLOCK_HC) 3438 reg_addr = (HC_REG_COMMAND_REG + port*32 + 3439 COMMAND_REG_ATTN_BITS_SET); 3440 else 3441 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 3442 3443 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 3444 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 3445 REG_WR(bp, reg_addr, asserted); 3446 3447 /* now set back the mask */ 3448 if (asserted & ATTN_NIG_FOR_FUNC) { 3449 REG_WR(bp, nig_int_mask_addr, nig_mask); 3450 bnx2x_release_phy_lock(bp); 3451 } 3452} 3453 3454static inline void bnx2x_fan_failure(struct bnx2x *bp) 3455{ 3456 int port = BP_PORT(bp); 3457 u32 ext_phy_config; 3458 /* mark the failure */ 3459 ext_phy_config = 3460 SHMEM_RD(bp, 3461 dev_info.port_hw_config[port].external_phy_config); 3462 3463 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 3464 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 3465 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 3466 ext_phy_config); 3467 3468 /* log the failure */ 3469 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" 3470 "Please contact OEM Support for assistance\n"); 3471 3472 /* 3473 * Scheudle device reset (unload) 3474 * This is due to some boards consuming sufficient power when driver is 3475 * up to overheat if fan fails. 3476 */ 3477 smp_mb__before_clear_bit(); 3478 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); 3479 smp_mb__after_clear_bit(); 3480 schedule_delayed_work(&bp->sp_rtnl_task, 0); 3481 3482} 3483 3484static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 3485{ 3486 int port = BP_PORT(bp); 3487 int reg_offset; 3488 u32 val; 3489 3490 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 3491 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 3492 3493 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 3494 3495 val = REG_RD(bp, reg_offset); 3496 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 3497 REG_WR(bp, reg_offset, val); 3498 3499 BNX2X_ERR("SPIO5 hw attention\n"); 3500 3501 /* Fan failure attention */ 3502 bnx2x_hw_reset_phy(&bp->link_params); 3503 bnx2x_fan_failure(bp); 3504 } 3505 3506 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 3507 bnx2x_acquire_phy_lock(bp); 3508 bnx2x_handle_module_detect_int(&bp->link_params); 3509 bnx2x_release_phy_lock(bp); 3510 } 3511 3512 if (attn & HW_INTERRUT_ASSERT_SET_0) { 3513 3514 val = REG_RD(bp, reg_offset); 3515 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 3516 REG_WR(bp, reg_offset, val); 3517 3518 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 3519 (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); 3520 bnx2x_panic(); 3521 } 3522} 3523 3524static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 3525{ 3526 u32 val; 3527 3528 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 3529 3530 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 3531 BNX2X_ERR("DB hw attention 0x%x\n", val); 3532 /* DORQ discard attention */ 3533 if (val & 0x2) 3534 BNX2X_ERR("FATAL error from DORQ\n"); 3535 } 3536 3537 if (attn & HW_INTERRUT_ASSERT_SET_1) { 3538 3539 int port = BP_PORT(bp); 3540 int reg_offset; 3541 3542 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 3543 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 3544 3545 val = REG_RD(bp, reg_offset); 3546 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 3547 REG_WR(bp, reg_offset, val); 3548 3549 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 3550 (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); 3551 bnx2x_panic(); 3552 } 3553} 3554 3555static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 3556{ 3557 u32 val; 3558 3559 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 3560 3561 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 3562 BNX2X_ERR("CFC hw attention 0x%x\n", val); 3563 /* CFC error attention */ 3564 if (val & 0x2) 3565 BNX2X_ERR("FATAL error from CFC\n"); 3566 } 3567 3568 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 3569 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 3570 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 3571 /* RQ_USDMDP_FIFO_OVERFLOW */ 3572 if (val & 0x18000) 3573 BNX2X_ERR("FATAL error from PXP\n"); 3574 3575 if (!CHIP_IS_E1x(bp)) { 3576 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 3577 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 3578 } 3579 } 3580 3581 if (attn & HW_INTERRUT_ASSERT_SET_2) { 3582 3583 int port = BP_PORT(bp); 3584 int reg_offset; 3585 3586 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 3587 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 3588 3589 val = REG_RD(bp, reg_offset); 3590 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 3591 REG_WR(bp, reg_offset, val); 3592 3593 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 3594 (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); 3595 bnx2x_panic(); 3596 } 3597} 3598 3599static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 3600{ 3601 u32 val; 3602 3603 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 3604 3605 if (attn & BNX2X_PMF_LINK_ASSERT) { 3606 int func = BP_FUNC(bp); 3607 3608 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 3609 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 3610 func_mf_config[BP_ABS_FUNC(bp)].config); 3611 val = SHMEM_RD(bp, 3612 func_mb[BP_FW_MB_IDX(bp)].drv_status); 3613 if (val & DRV_STATUS_DCC_EVENT_MASK) 3614 bnx2x_dcc_event(bp, 3615 (val & DRV_STATUS_DCC_EVENT_MASK)); 3616 3617 if (val & DRV_STATUS_SET_MF_BW) 3618 bnx2x_set_mf_bw(bp); 3619 3620 if (val & DRV_STATUS_DRV_INFO_REQ) 3621 bnx2x_handle_drv_info_req(bp); 3622 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 3623 bnx2x_pmf_update(bp); 3624 3625 if (bp->port.pmf && 3626 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 3627 bp->dcbx_enabled > 0) 3628 /* start dcbx state machine */ 3629 bnx2x_dcbx_set_params(bp, 3630 BNX2X_DCBX_STATE_NEG_RECEIVED); 3631 if (bp->link_vars.periodic_flags & 3632 PERIODIC_FLAGS_LINK_EVENT) { 3633 /* sync with link */ 3634 bnx2x_acquire_phy_lock(bp); 3635 bp->link_vars.periodic_flags &= 3636 ~PERIODIC_FLAGS_LINK_EVENT; 3637 bnx2x_release_phy_lock(bp); 3638 if (IS_MF(bp)) 3639 bnx2x_link_sync_notify(bp); 3640 bnx2x_link_report(bp); 3641 } 3642 /* Always call it here: bnx2x_link_report() will 3643 * prevent the link indication duplication. 3644 */ 3645 bnx2x__link_status_update(bp); 3646 } else if (attn & BNX2X_MC_ASSERT_BITS) { 3647 3648 BNX2X_ERR("MC assert!\n"); 3649 bnx2x_mc_assert(bp); 3650 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 3651 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 3652 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 3653 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 3654 bnx2x_panic(); 3655 3656 } else if (attn & BNX2X_MCP_ASSERT) { 3657 3658 BNX2X_ERR("MCP assert!\n"); 3659 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 3660 bnx2x_fw_dump(bp); 3661 3662 } else 3663 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 3664 } 3665 3666 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 3667 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 3668 if (attn & BNX2X_GRC_TIMEOUT) { 3669 val = CHIP_IS_E1(bp) ? 0 : 3670 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 3671 BNX2X_ERR("GRC time-out 0x%08x\n", val); 3672 } 3673 if (attn & BNX2X_GRC_RSV) { 3674 val = CHIP_IS_E1(bp) ? 0 : 3675 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 3676 BNX2X_ERR("GRC reserved 0x%08x\n", val); 3677 } 3678 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 3679 } 3680} 3681 3682/* 3683 * Bits map: 3684 * 0-7 - Engine0 load counter. 3685 * 8-15 - Engine1 load counter. 3686 * 16 - Engine0 RESET_IN_PROGRESS bit. 3687 * 17 - Engine1 RESET_IN_PROGRESS bit. 3688 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 3689 * on the engine 3690 * 19 - Engine1 ONE_IS_LOADED. 3691 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 3692 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 3693 * just the one belonging to its engine). 3694 * 3695 */ 3696#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 3697 3698#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 3699#define BNX2X_PATH0_LOAD_CNT_SHIFT 0 3700#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 3701#define BNX2X_PATH1_LOAD_CNT_SHIFT 8 3702#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 3703#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 3704#define BNX2X_GLOBAL_RESET_BIT 0x00040000 3705 3706/* 3707 * Set the GLOBAL_RESET bit. 3708 * 3709 * Should be run under rtnl lock 3710 */ 3711void bnx2x_set_reset_global(struct bnx2x *bp) 3712{ 3713 u32 val; 3714 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3715 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3716 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 3717 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3718} 3719 3720/* 3721 * Clear the GLOBAL_RESET bit. 3722 * 3723 * Should be run under rtnl lock 3724 */ 3725static inline void bnx2x_clear_reset_global(struct bnx2x *bp) 3726{ 3727 u32 val; 3728 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3729 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3730 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 3731 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3732} 3733 3734/* 3735 * Checks the GLOBAL_RESET bit. 3736 * 3737 * should be run under rtnl lock 3738 */ 3739static inline bool bnx2x_reset_is_global(struct bnx2x *bp) 3740{ 3741 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3742 3743 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 3744 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 3745} 3746 3747/* 3748 * Clear RESET_IN_PROGRESS bit for the current engine. 3749 * 3750 * Should be run under rtnl lock 3751 */ 3752static inline void bnx2x_set_reset_done(struct bnx2x *bp) 3753{ 3754 u32 val; 3755 u32 bit = BP_PATH(bp) ? 3756 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3757 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3758 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3759 3760 /* Clear the bit */ 3761 val &= ~bit; 3762 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3763 3764 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3765} 3766 3767/* 3768 * Set RESET_IN_PROGRESS for the current engine. 3769 * 3770 * should be run under rtnl lock 3771 */ 3772void bnx2x_set_reset_in_progress(struct bnx2x *bp) 3773{ 3774 u32 val; 3775 u32 bit = BP_PATH(bp) ? 3776 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3777 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3778 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3779 3780 /* Set the bit */ 3781 val |= bit; 3782 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3783 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3784} 3785 3786/* 3787 * Checks the RESET_IN_PROGRESS bit for the given engine. 3788 * should be run under rtnl lock 3789 */ 3790bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 3791{ 3792 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3793 u32 bit = engine ? 3794 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3795 3796 /* return false if bit is set */ 3797 return (val & bit) ? false : true; 3798} 3799 3800/* 3801 * set pf load for the current pf. 3802 * 3803 * should be run under rtnl lock 3804 */ 3805void bnx2x_set_pf_load(struct bnx2x *bp) 3806{ 3807 u32 val1, val; 3808 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3809 BNX2X_PATH0_LOAD_CNT_MASK; 3810 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3811 BNX2X_PATH0_LOAD_CNT_SHIFT; 3812 3813 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3814 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3815 3816 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); 3817 3818 /* get the current counter value */ 3819 val1 = (val & mask) >> shift; 3820 3821 /* set bit of that PF */ 3822 val1 |= (1 << bp->pf_num); 3823 3824 /* clear the old value */ 3825 val &= ~mask; 3826 3827 /* set the new one */ 3828 val |= ((val1 << shift) & mask); 3829 3830 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3831 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3832} 3833 3834/** 3835 * bnx2x_clear_pf_load - clear pf load mark 3836 * 3837 * @bp: driver handle 3838 * 3839 * Should be run under rtnl lock. 3840 * Decrements the load counter for the current engine. Returns 3841 * whether other functions are still loaded 3842 */ 3843bool bnx2x_clear_pf_load(struct bnx2x *bp) 3844{ 3845 u32 val1, val; 3846 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3847 BNX2X_PATH0_LOAD_CNT_MASK; 3848 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3849 BNX2X_PATH0_LOAD_CNT_SHIFT; 3850 3851 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3852 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3853 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); 3854 3855 /* get the current counter value */ 3856 val1 = (val & mask) >> shift; 3857 3858 /* clear bit of that PF */ 3859 val1 &= ~(1 << bp->pf_num); 3860 3861 /* clear the old value */ 3862 val &= ~mask; 3863 3864 /* set the new one */ 3865 val |= ((val1 << shift) & mask); 3866 3867 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3868 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3869 return val1 != 0; 3870} 3871 3872/* 3873 * Read the load status for the current engine. 3874 * 3875 * should be run under rtnl lock 3876 */ 3877static inline bool bnx2x_get_load_status(struct bnx2x *bp, int engine) 3878{ 3879 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 3880 BNX2X_PATH0_LOAD_CNT_MASK); 3881 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3882 BNX2X_PATH0_LOAD_CNT_SHIFT); 3883 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3884 3885 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); 3886 3887 val = (val & mask) >> shift; 3888 3889 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", 3890 engine, val); 3891 3892 return val != 0; 3893} 3894 3895/* 3896 * Reset the load status for the current engine. 3897 */ 3898static inline void bnx2x_clear_load_status(struct bnx2x *bp) 3899{ 3900 u32 val; 3901 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3902 BNX2X_PATH0_LOAD_CNT_MASK); 3903 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3904 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3905 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); 3906 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3907} 3908 3909static inline void _print_next_block(int idx, const char *blk) 3910{ 3911 pr_cont("%s%s", idx ? ", " : "", blk); 3912} 3913 3914static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, 3915 bool print) 3916{ 3917 int i = 0; 3918 u32 cur_bit = 0; 3919 for (i = 0; sig; i++) { 3920 cur_bit = ((u32)0x1 << i); 3921 if (sig & cur_bit) { 3922 switch (cur_bit) { 3923 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 3924 if (print) 3925 _print_next_block(par_num++, "BRB"); 3926 break; 3927 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 3928 if (print) 3929 _print_next_block(par_num++, "PARSER"); 3930 break; 3931 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 3932 if (print) 3933 _print_next_block(par_num++, "TSDM"); 3934 break; 3935 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 3936 if (print) 3937 _print_next_block(par_num++, 3938 "SEARCHER"); 3939 break; 3940 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 3941 if (print) 3942 _print_next_block(par_num++, "TCM"); 3943 break; 3944 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 3945 if (print) 3946 _print_next_block(par_num++, "TSEMI"); 3947 break; 3948 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 3949 if (print) 3950 _print_next_block(par_num++, "XPB"); 3951 break; 3952 } 3953 3954 /* Clear the bit */ 3955 sig &= ~cur_bit; 3956 } 3957 } 3958 3959 return par_num; 3960} 3961 3962static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, 3963 bool *global, bool print) 3964{ 3965 int i = 0; 3966 u32 cur_bit = 0; 3967 for (i = 0; sig; i++) { 3968 cur_bit = ((u32)0x1 << i); 3969 if (sig & cur_bit) { 3970 switch (cur_bit) { 3971 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 3972 if (print) 3973 _print_next_block(par_num++, "PBF"); 3974 break; 3975 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 3976 if (print) 3977 _print_next_block(par_num++, "QM"); 3978 break; 3979 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 3980 if (print) 3981 _print_next_block(par_num++, "TM"); 3982 break; 3983 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 3984 if (print) 3985 _print_next_block(par_num++, "XSDM"); 3986 break; 3987 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 3988 if (print) 3989 _print_next_block(par_num++, "XCM"); 3990 break; 3991 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 3992 if (print) 3993 _print_next_block(par_num++, "XSEMI"); 3994 break; 3995 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 3996 if (print) 3997 _print_next_block(par_num++, 3998 "DOORBELLQ"); 3999 break; 4000 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 4001 if (print) 4002 _print_next_block(par_num++, "NIG"); 4003 break; 4004 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 4005 if (print) 4006 _print_next_block(par_num++, 4007 "VAUX PCI CORE"); 4008 *global = true; 4009 break; 4010 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 4011 if (print) 4012 _print_next_block(par_num++, "DEBUG"); 4013 break; 4014 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 4015 if (print) 4016 _print_next_block(par_num++, "USDM"); 4017 break; 4018 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 4019 if (print) 4020 _print_next_block(par_num++, "UCM"); 4021 break; 4022 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 4023 if (print) 4024 _print_next_block(par_num++, "USEMI"); 4025 break; 4026 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 4027 if (print) 4028 _print_next_block(par_num++, "UPB"); 4029 break; 4030 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 4031 if (print) 4032 _print_next_block(par_num++, "CSDM"); 4033 break; 4034 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 4035 if (print) 4036 _print_next_block(par_num++, "CCM"); 4037 break; 4038 } 4039 4040 /* Clear the bit */ 4041 sig &= ~cur_bit; 4042 } 4043 } 4044 4045 return par_num; 4046} 4047 4048static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, 4049 bool print) 4050{ 4051 int i = 0; 4052 u32 cur_bit = 0; 4053 for (i = 0; sig; i++) { 4054 cur_bit = ((u32)0x1 << i); 4055 if (sig & cur_bit) { 4056 switch (cur_bit) { 4057 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 4058 if (print) 4059 _print_next_block(par_num++, "CSEMI"); 4060 break; 4061 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 4062 if (print) 4063 _print_next_block(par_num++, "PXP"); 4064 break; 4065 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 4066 if (print) 4067 _print_next_block(par_num++, 4068 "PXPPCICLOCKCLIENT"); 4069 break; 4070 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 4071 if (print) 4072 _print_next_block(par_num++, "CFC"); 4073 break; 4074 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 4075 if (print) 4076 _print_next_block(par_num++, "CDU"); 4077 break; 4078 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 4079 if (print) 4080 _print_next_block(par_num++, "DMAE"); 4081 break; 4082 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 4083 if (print) 4084 _print_next_block(par_num++, "IGU"); 4085 break; 4086 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 4087 if (print) 4088 _print_next_block(par_num++, "MISC"); 4089 break; 4090 } 4091 4092 /* Clear the bit */ 4093 sig &= ~cur_bit; 4094 } 4095 } 4096 4097 return par_num; 4098} 4099 4100static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, 4101 bool *global, bool print) 4102{ 4103 int i = 0; 4104 u32 cur_bit = 0; 4105 for (i = 0; sig; i++) { 4106 cur_bit = ((u32)0x1 << i); 4107 if (sig & cur_bit) { 4108 switch (cur_bit) { 4109 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 4110 if (print) 4111 _print_next_block(par_num++, "MCP ROM"); 4112 *global = true; 4113 break; 4114 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 4115 if (print) 4116 _print_next_block(par_num++, 4117 "MCP UMP RX"); 4118 *global = true; 4119 break; 4120 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 4121 if (print) 4122 _print_next_block(par_num++, 4123 "MCP UMP TX"); 4124 *global = true; 4125 break; 4126 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 4127 if (print) 4128 _print_next_block(par_num++, 4129 "MCP SCPAD"); 4130 *global = true; 4131 break; 4132 } 4133 4134 /* Clear the bit */ 4135 sig &= ~cur_bit; 4136 } 4137 } 4138 4139 return par_num; 4140} 4141 4142static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, 4143 bool print) 4144{ 4145 int i = 0; 4146 u32 cur_bit = 0; 4147 for (i = 0; sig; i++) { 4148 cur_bit = ((u32)0x1 << i); 4149 if (sig & cur_bit) { 4150 switch (cur_bit) { 4151 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 4152 if (print) 4153 _print_next_block(par_num++, "PGLUE_B"); 4154 break; 4155 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 4156 if (print) 4157 _print_next_block(par_num++, "ATC"); 4158 break; 4159 } 4160 4161 /* Clear the bit */ 4162 sig &= ~cur_bit; 4163 } 4164 } 4165 4166 return par_num; 4167} 4168 4169static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4170 u32 *sig) 4171{ 4172 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4173 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4174 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4175 (sig[3] & HW_PRTY_ASSERT_SET_3) || 4176 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4177 int par_num = 0; 4178 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" 4179 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", 4180 sig[0] & HW_PRTY_ASSERT_SET_0, 4181 sig[1] & HW_PRTY_ASSERT_SET_1, 4182 sig[2] & HW_PRTY_ASSERT_SET_2, 4183 sig[3] & HW_PRTY_ASSERT_SET_3, 4184 sig[4] & HW_PRTY_ASSERT_SET_4); 4185 if (print) 4186 netdev_err(bp->dev, 4187 "Parity errors detected in blocks: "); 4188 par_num = bnx2x_check_blocks_with_parity0( 4189 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); 4190 par_num = bnx2x_check_blocks_with_parity1( 4191 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); 4192 par_num = bnx2x_check_blocks_with_parity2( 4193 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); 4194 par_num = bnx2x_check_blocks_with_parity3( 4195 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); 4196 par_num = bnx2x_check_blocks_with_parity4( 4197 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); 4198 4199 if (print) 4200 pr_cont("\n"); 4201 4202 return true; 4203 } else 4204 return false; 4205} 4206 4207/** 4208 * bnx2x_chk_parity_attn - checks for parity attentions. 4209 * 4210 * @bp: driver handle 4211 * @global: true if there was a global attention 4212 * @print: show parity attention in syslog 4213 */ 4214bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 4215{ 4216 struct attn_route attn = { {0} }; 4217 int port = BP_PORT(bp); 4218 4219 attn.sig[0] = REG_RD(bp, 4220 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 4221 port*4); 4222 attn.sig[1] = REG_RD(bp, 4223 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 4224 port*4); 4225 attn.sig[2] = REG_RD(bp, 4226 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 4227 port*4); 4228 attn.sig[3] = REG_RD(bp, 4229 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 4230 port*4); 4231 4232 if (!CHIP_IS_E1x(bp)) 4233 attn.sig[4] = REG_RD(bp, 4234 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 4235 port*4); 4236 4237 return bnx2x_parity_attn(bp, global, print, attn.sig); 4238} 4239 4240 4241static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 4242{ 4243 u32 val; 4244 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 4245 4246 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 4247 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 4248 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 4249 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); 4250 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 4251 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); 4252 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 4253 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); 4254 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 4255 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); 4256 if (val & 4257 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 4258 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); 4259 if (val & 4260 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 4261 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); 4262 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 4263 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); 4264 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 4265 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); 4266 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 4267 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); 4268 } 4269 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 4270 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 4271 BNX2X_ERR("ATC hw attention 0x%x\n", val); 4272 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 4273 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 4274 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 4275 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); 4276 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 4277 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); 4278 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 4279 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); 4280 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 4281 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 4282 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 4283 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); 4284 } 4285 4286 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4287 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 4288 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 4289 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4290 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 4291 } 4292 4293} 4294 4295static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 4296{ 4297 struct attn_route attn, *group_mask; 4298 int port = BP_PORT(bp); 4299 int index; 4300 u32 reg_addr; 4301 u32 val; 4302 u32 aeu_mask; 4303 bool global = false; 4304 4305 /* need to take HW lock because MCP or other port might also 4306 try to handle this event */ 4307 bnx2x_acquire_alr(bp); 4308 4309 if (bnx2x_chk_parity_attn(bp, &global, true)) { 4310#ifndef BNX2X_STOP_ON_ERROR 4311 bp->recovery_state = BNX2X_RECOVERY_INIT; 4312 schedule_delayed_work(&bp->sp_rtnl_task, 0); 4313 /* Disable HW interrupts */ 4314 bnx2x_int_disable(bp); 4315 /* In case of parity errors don't handle attentions so that 4316 * other function would "see" parity errors. 4317 */ 4318#else 4319 bnx2x_panic(); 4320#endif 4321 bnx2x_release_alr(bp); 4322 return; 4323 } 4324 4325 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 4326 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 4327 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 4328 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 4329 if (!CHIP_IS_E1x(bp)) 4330 attn.sig[4] = 4331 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 4332 else 4333 attn.sig[4] = 0; 4334 4335 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 4336 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 4337 4338 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4339 if (deasserted & (1 << index)) { 4340 group_mask = &bp->attn_group[index]; 4341 4342 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", 4343 index, 4344 group_mask->sig[0], group_mask->sig[1], 4345 group_mask->sig[2], group_mask->sig[3], 4346 group_mask->sig[4]); 4347 4348 bnx2x_attn_int_deasserted4(bp, 4349 attn.sig[4] & group_mask->sig[4]); 4350 bnx2x_attn_int_deasserted3(bp, 4351 attn.sig[3] & group_mask->sig[3]); 4352 bnx2x_attn_int_deasserted1(bp, 4353 attn.sig[1] & group_mask->sig[1]); 4354 bnx2x_attn_int_deasserted2(bp, 4355 attn.sig[2] & group_mask->sig[2]); 4356 bnx2x_attn_int_deasserted0(bp, 4357 attn.sig[0] & group_mask->sig[0]); 4358 } 4359 } 4360 4361 bnx2x_release_alr(bp); 4362 4363 if (bp->common.int_block == INT_BLOCK_HC) 4364 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4365 COMMAND_REG_ATTN_BITS_CLR); 4366 else 4367 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 4368 4369 val = ~deasserted; 4370 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 4371 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4372 REG_WR(bp, reg_addr, val); 4373 4374 if (~bp->attn_state & deasserted) 4375 BNX2X_ERR("IGU ERROR\n"); 4376 4377 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4378 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4379 4380 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4381 aeu_mask = REG_RD(bp, reg_addr); 4382 4383 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 4384 aeu_mask, deasserted); 4385 aeu_mask |= (deasserted & 0x3ff); 4386 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4387 4388 REG_WR(bp, reg_addr, aeu_mask); 4389 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4390 4391 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4392 bp->attn_state &= ~deasserted; 4393 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4394} 4395 4396static void bnx2x_attn_int(struct bnx2x *bp) 4397{ 4398 /* read local copy of bits */ 4399 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 4400 attn_bits); 4401 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 4402 attn_bits_ack); 4403 u32 attn_state = bp->attn_state; 4404 4405 /* look for changed bits */ 4406 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 4407 u32 deasserted = ~attn_bits & attn_ack & attn_state; 4408 4409 DP(NETIF_MSG_HW, 4410 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 4411 attn_bits, attn_ack, asserted, deasserted); 4412 4413 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 4414 BNX2X_ERR("BAD attention state\n"); 4415 4416 /* handle bits that were raised */ 4417 if (asserted) 4418 bnx2x_attn_int_asserted(bp, asserted); 4419 4420 if (deasserted) 4421 bnx2x_attn_int_deasserted(bp, deasserted); 4422} 4423 4424void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 4425 u16 index, u8 op, u8 update) 4426{ 4427 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 4428 4429 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 4430 igu_addr); 4431} 4432 4433static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 4434{ 4435 /* No memory barriers */ 4436 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 4437 mmiowb(); /* keep prod updates ordered */ 4438} 4439 4440#ifdef BCM_CNIC 4441static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 4442 union event_ring_elem *elem) 4443{ 4444 u8 err = elem->message.error; 4445 4446 if (!bp->cnic_eth_dev.starting_cid || 4447 (cid < bp->cnic_eth_dev.starting_cid && 4448 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 4449 return 1; 4450 4451 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 4452 4453 if (unlikely(err)) { 4454 4455 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 4456 cid); 4457 bnx2x_panic_dump(bp); 4458 } 4459 bnx2x_cnic_cfc_comp(bp, cid, err); 4460 return 0; 4461} 4462#endif 4463 4464static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 4465{ 4466 struct bnx2x_mcast_ramrod_params rparam; 4467 int rc; 4468 4469 memset(&rparam, 0, sizeof(rparam)); 4470 4471 rparam.mcast_obj = &bp->mcast_obj; 4472 4473 netif_addr_lock_bh(bp->dev); 4474 4475 /* Clear pending state for the last command */ 4476 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 4477 4478 /* If there are pending mcast commands - send them */ 4479 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 4480 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 4481 if (rc < 0) 4482 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 4483 rc); 4484 } 4485 4486 netif_addr_unlock_bh(bp->dev); 4487} 4488 4489static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp, 4490 union event_ring_elem *elem) 4491{ 4492 unsigned long ramrod_flags = 0; 4493 int rc = 0; 4494 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; 4495 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 4496 4497 /* Always push next commands out, don't wait here */ 4498 __set_bit(RAMROD_CONT, &ramrod_flags); 4499 4500 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 4501 case BNX2X_FILTER_MAC_PENDING: 4502 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); 4503#ifdef BCM_CNIC 4504 if (cid == BNX2X_ISCSI_ETH_CID) 4505 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 4506 else 4507#endif 4508 vlan_mac_obj = &bp->fp[cid].mac_obj; 4509 4510 break; 4511 case BNX2X_FILTER_MCAST_PENDING: 4512 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); 4513 /* This is only relevant for 57710 where multicast MACs are 4514 * configured as unicast MACs using the same ramrod. 4515 */ 4516 bnx2x_handle_mcast_eqe(bp); 4517 return; 4518 default: 4519 BNX2X_ERR("Unsupported classification command: %d\n", 4520 elem->message.data.eth_event.echo); 4521 return; 4522 } 4523 4524 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 4525 4526 if (rc < 0) 4527 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 4528 else if (rc > 0) 4529 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 4530 4531} 4532 4533#ifdef BCM_CNIC 4534static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 4535#endif 4536 4537static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 4538{ 4539 netif_addr_lock_bh(bp->dev); 4540 4541 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 4542 4543 /* Send rx_mode command again if was requested */ 4544 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 4545 bnx2x_set_storm_rx_mode(bp); 4546#ifdef BCM_CNIC 4547 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 4548 &bp->sp_state)) 4549 bnx2x_set_iscsi_eth_rx_mode(bp, true); 4550 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 4551 &bp->sp_state)) 4552 bnx2x_set_iscsi_eth_rx_mode(bp, false); 4553#endif 4554 4555 netif_addr_unlock_bh(bp->dev); 4556} 4557 4558static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 4559 struct bnx2x *bp, u32 cid) 4560{ 4561 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 4562#ifdef BCM_CNIC 4563 if (cid == BNX2X_FCOE_ETH_CID) 4564 return &bnx2x_fcoe(bp, q_obj); 4565 else 4566#endif 4567 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj); 4568} 4569 4570static void bnx2x_eq_int(struct bnx2x *bp) 4571{ 4572 u16 hw_cons, sw_cons, sw_prod; 4573 union event_ring_elem *elem; 4574 u32 cid; 4575 u8 opcode; 4576 int spqe_cnt = 0; 4577 struct bnx2x_queue_sp_obj *q_obj; 4578 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 4579 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 4580 4581 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 4582 4583 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 4584 * when we get the the next-page we nned to adjust so the loop 4585 * condition below will be met. The next element is the size of a 4586 * regular element and hence incrementing by 1 4587 */ 4588 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 4589 hw_cons++; 4590 4591 /* This function may never run in parallel with itself for a 4592 * specific bp, thus there is no need in "paired" read memory 4593 * barrier here. 4594 */ 4595 sw_cons = bp->eq_cons; 4596 sw_prod = bp->eq_prod; 4597 4598 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 4599 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 4600 4601 for (; sw_cons != hw_cons; 4602 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 4603 4604 4605 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 4606 4607 cid = SW_CID(elem->message.data.cfc_del_event.cid); 4608 opcode = elem->message.opcode; 4609 4610 4611 /* handle eq element */ 4612 switch (opcode) { 4613 case EVENT_RING_OPCODE_STAT_QUERY: 4614 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS, 4615 "got statistics comp event %d\n", 4616 bp->stats_comp++); 4617 /* nothing to do with stats comp */ 4618 goto next_spqe; 4619 4620 case EVENT_RING_OPCODE_CFC_DEL: 4621 /* handle according to cid range */ 4622 /* 4623 * we may want to verify here that the bp state is 4624 * HALTING 4625 */ 4626 DP(BNX2X_MSG_SP, 4627 "got delete ramrod for MULTI[%d]\n", cid); 4628#ifdef BCM_CNIC 4629 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 4630 goto next_spqe; 4631#endif 4632 q_obj = bnx2x_cid_to_q_obj(bp, cid); 4633 4634 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 4635 break; 4636 4637 4638 4639 goto next_spqe; 4640 4641 case EVENT_RING_OPCODE_STOP_TRAFFIC: 4642 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); 4643 if (f_obj->complete_cmd(bp, f_obj, 4644 BNX2X_F_CMD_TX_STOP)) 4645 break; 4646 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 4647 goto next_spqe; 4648 4649 case EVENT_RING_OPCODE_START_TRAFFIC: 4650 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); 4651 if (f_obj->complete_cmd(bp, f_obj, 4652 BNX2X_F_CMD_TX_START)) 4653 break; 4654 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 4655 goto next_spqe; 4656 case EVENT_RING_OPCODE_FUNCTION_START: 4657 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 4658 "got FUNC_START ramrod\n"); 4659 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 4660 break; 4661 4662 goto next_spqe; 4663 4664 case EVENT_RING_OPCODE_FUNCTION_STOP: 4665 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 4666 "got FUNC_STOP ramrod\n"); 4667 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 4668 break; 4669 4670 goto next_spqe; 4671 } 4672 4673 switch (opcode | bp->state) { 4674 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4675 BNX2X_STATE_OPEN): 4676 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4677 BNX2X_STATE_OPENING_WAIT4_PORT): 4678 cid = elem->message.data.eth_event.echo & 4679 BNX2X_SWCID_MASK; 4680 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 4681 cid); 4682 rss_raw->clear_pending(rss_raw); 4683 break; 4684 4685 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 4686 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 4687 case (EVENT_RING_OPCODE_SET_MAC | 4688 BNX2X_STATE_CLOSING_WAIT4_HALT): 4689 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4690 BNX2X_STATE_OPEN): 4691 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4692 BNX2X_STATE_DIAG): 4693 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4694 BNX2X_STATE_CLOSING_WAIT4_HALT): 4695 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); 4696 bnx2x_handle_classification_eqe(bp, elem); 4697 break; 4698 4699 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4700 BNX2X_STATE_OPEN): 4701 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4702 BNX2X_STATE_DIAG): 4703 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4704 BNX2X_STATE_CLOSING_WAIT4_HALT): 4705 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 4706 bnx2x_handle_mcast_eqe(bp); 4707 break; 4708 4709 case (EVENT_RING_OPCODE_FILTERS_RULES | 4710 BNX2X_STATE_OPEN): 4711 case (EVENT_RING_OPCODE_FILTERS_RULES | 4712 BNX2X_STATE_DIAG): 4713 case (EVENT_RING_OPCODE_FILTERS_RULES | 4714 BNX2X_STATE_CLOSING_WAIT4_HALT): 4715 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 4716 bnx2x_handle_rx_mode_eqe(bp); 4717 break; 4718 default: 4719 /* unknown event log error and continue */ 4720 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 4721 elem->message.opcode, bp->state); 4722 } 4723next_spqe: 4724 spqe_cnt++; 4725 } /* for */ 4726 4727 smp_mb__before_atomic_inc(); 4728 atomic_add(spqe_cnt, &bp->eq_spq_left); 4729 4730 bp->eq_cons = sw_cons; 4731 bp->eq_prod = sw_prod; 4732 /* Make sure that above mem writes were issued towards the memory */ 4733 smp_wmb(); 4734 4735 /* update producer */ 4736 bnx2x_update_eq_prod(bp, bp->eq_prod); 4737} 4738 4739static void bnx2x_sp_task(struct work_struct *work) 4740{ 4741 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 4742 u16 status; 4743 4744 status = bnx2x_update_dsb_idx(bp); 4745/* if (status == 0) */ 4746/* BNX2X_ERR("spurious slowpath interrupt!\n"); */ 4747 4748 DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status); 4749 4750 /* HW attentions */ 4751 if (status & BNX2X_DEF_SB_ATT_IDX) { 4752 bnx2x_attn_int(bp); 4753 status &= ~BNX2X_DEF_SB_ATT_IDX; 4754 } 4755 4756 /* SP events: STAT_QUERY and others */ 4757 if (status & BNX2X_DEF_SB_IDX) { 4758#ifdef BCM_CNIC 4759 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 4760 4761 if ((!NO_FCOE(bp)) && 4762 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 4763 /* 4764 * Prevent local bottom-halves from running as 4765 * we are going to change the local NAPI list. 4766 */ 4767 local_bh_disable(); 4768 napi_schedule(&bnx2x_fcoe(bp, napi)); 4769 local_bh_enable(); 4770 } 4771#endif 4772 /* Handle EQ completions */ 4773 bnx2x_eq_int(bp); 4774 4775 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 4776 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 4777 4778 status &= ~BNX2X_DEF_SB_IDX; 4779 } 4780 4781 if (unlikely(status)) 4782 DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n", 4783 status); 4784 4785 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 4786 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 4787} 4788 4789irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 4790{ 4791 struct net_device *dev = dev_instance; 4792 struct bnx2x *bp = netdev_priv(dev); 4793 4794 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 4795 IGU_INT_DISABLE, 0); 4796 4797#ifdef BNX2X_STOP_ON_ERROR 4798 if (unlikely(bp->panic)) 4799 return IRQ_HANDLED; 4800#endif 4801 4802#ifdef BCM_CNIC 4803 { 4804 struct cnic_ops *c_ops; 4805 4806 rcu_read_lock(); 4807 c_ops = rcu_dereference(bp->cnic_ops); 4808 if (c_ops) 4809 c_ops->cnic_handler(bp->cnic_data, NULL); 4810 rcu_read_unlock(); 4811 } 4812#endif 4813 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 4814 4815 return IRQ_HANDLED; 4816} 4817 4818/* end of slow path */ 4819 4820 4821void bnx2x_drv_pulse(struct bnx2x *bp) 4822{ 4823 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 4824 bp->fw_drv_pulse_wr_seq); 4825} 4826 4827 4828static void bnx2x_timer(unsigned long data) 4829{ 4830 struct bnx2x *bp = (struct bnx2x *) data; 4831 4832 if (!netif_running(bp->dev)) 4833 return; 4834 4835 if (!BP_NOMCP(bp)) { 4836 int mb_idx = BP_FW_MB_IDX(bp); 4837 u32 drv_pulse; 4838 u32 mcp_pulse; 4839 4840 ++bp->fw_drv_pulse_wr_seq; 4841 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 4842 /* TBD - add SYSTEM_TIME */ 4843 drv_pulse = bp->fw_drv_pulse_wr_seq; 4844 bnx2x_drv_pulse(bp); 4845 4846 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 4847 MCP_PULSE_SEQ_MASK); 4848 /* The delta between driver pulse and mcp response 4849 * should be 1 (before mcp response) or 0 (after mcp response) 4850 */ 4851 if ((drv_pulse != mcp_pulse) && 4852 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 4853 /* someone lost a heartbeat... */ 4854 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 4855 drv_pulse, mcp_pulse); 4856 } 4857 } 4858 4859 if (bp->state == BNX2X_STATE_OPEN) 4860 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 4861 4862 mod_timer(&bp->timer, jiffies + bp->current_interval); 4863} 4864 4865/* end of Statistics */ 4866 4867/* nic init */ 4868 4869/* 4870 * nic init service functions 4871 */ 4872 4873static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 4874{ 4875 u32 i; 4876 if (!(len%4) && !(addr%4)) 4877 for (i = 0; i < len; i += 4) 4878 REG_WR(bp, addr + i, fill); 4879 else 4880 for (i = 0; i < len; i++) 4881 REG_WR8(bp, addr + i, fill); 4882 4883} 4884 4885/* helper: writes FP SP data to FW - data_size in dwords */ 4886static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 4887 int fw_sb_id, 4888 u32 *sb_data_p, 4889 u32 data_size) 4890{ 4891 int index; 4892 for (index = 0; index < data_size; index++) 4893 REG_WR(bp, BAR_CSTRORM_INTMEM + 4894 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 4895 sizeof(u32)*index, 4896 *(sb_data_p + index)); 4897} 4898 4899static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 4900{ 4901 u32 *sb_data_p; 4902 u32 data_size = 0; 4903 struct hc_status_block_data_e2 sb_data_e2; 4904 struct hc_status_block_data_e1x sb_data_e1x; 4905 4906 /* disable the function first */ 4907 if (!CHIP_IS_E1x(bp)) { 4908 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 4909 sb_data_e2.common.state = SB_DISABLED; 4910 sb_data_e2.common.p_func.vf_valid = false; 4911 sb_data_p = (u32 *)&sb_data_e2; 4912 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 4913 } else { 4914 memset(&sb_data_e1x, 0, 4915 sizeof(struct hc_status_block_data_e1x)); 4916 sb_data_e1x.common.state = SB_DISABLED; 4917 sb_data_e1x.common.p_func.vf_valid = false; 4918 sb_data_p = (u32 *)&sb_data_e1x; 4919 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 4920 } 4921 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 4922 4923 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4924 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 4925 CSTORM_STATUS_BLOCK_SIZE); 4926 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4927 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 4928 CSTORM_SYNC_BLOCK_SIZE); 4929} 4930 4931/* helper: writes SP SB data to FW */ 4932static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 4933 struct hc_sp_status_block_data *sp_sb_data) 4934{ 4935 int func = BP_FUNC(bp); 4936 int i; 4937 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 4938 REG_WR(bp, BAR_CSTRORM_INTMEM + 4939 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 4940 i*sizeof(u32), 4941 *((u32 *)sp_sb_data + i)); 4942} 4943 4944static inline void bnx2x_zero_sp_sb(struct bnx2x *bp) 4945{ 4946 int func = BP_FUNC(bp); 4947 struct hc_sp_status_block_data sp_sb_data; 4948 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 4949 4950 sp_sb_data.state = SB_DISABLED; 4951 sp_sb_data.p_func.vf_valid = false; 4952 4953 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 4954 4955 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4956 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 4957 CSTORM_SP_STATUS_BLOCK_SIZE); 4958 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4959 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 4960 CSTORM_SP_SYNC_BLOCK_SIZE); 4961 4962} 4963 4964 4965static inline 4966void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 4967 int igu_sb_id, int igu_seg_id) 4968{ 4969 hc_sm->igu_sb_id = igu_sb_id; 4970 hc_sm->igu_seg_id = igu_seg_id; 4971 hc_sm->timer_value = 0xFF; 4972 hc_sm->time_to_expire = 0xFFFFFFFF; 4973} 4974 4975 4976/* allocates state machine ids. */ 4977static inline 4978void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) 4979{ 4980 /* zero out state machine indices */ 4981 /* rx indices */ 4982 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 4983 4984 /* tx indices */ 4985 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 4986 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 4987 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 4988 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 4989 4990 /* map indices */ 4991 /* rx indices */ 4992 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 4993 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4994 4995 /* tx indices */ 4996 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 4997 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4998 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 4999 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5000 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 5001 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5002 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 5003 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5004} 5005 5006static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 5007 u8 vf_valid, int fw_sb_id, int igu_sb_id) 5008{ 5009 int igu_seg_id; 5010 5011 struct hc_status_block_data_e2 sb_data_e2; 5012 struct hc_status_block_data_e1x sb_data_e1x; 5013 struct hc_status_block_sm *hc_sm_p; 5014 int data_size; 5015 u32 *sb_data_p; 5016 5017 if (CHIP_INT_MODE_IS_BC(bp)) 5018 igu_seg_id = HC_SEG_ACCESS_NORM; 5019 else 5020 igu_seg_id = IGU_SEG_ACCESS_NORM; 5021 5022 bnx2x_zero_fp_sb(bp, fw_sb_id); 5023 5024 if (!CHIP_IS_E1x(bp)) { 5025 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5026 sb_data_e2.common.state = SB_ENABLED; 5027 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 5028 sb_data_e2.common.p_func.vf_id = vfid; 5029 sb_data_e2.common.p_func.vf_valid = vf_valid; 5030 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 5031 sb_data_e2.common.same_igu_sb_1b = true; 5032 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 5033 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 5034 hc_sm_p = sb_data_e2.common.state_machine; 5035 sb_data_p = (u32 *)&sb_data_e2; 5036 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5037 bnx2x_map_sb_state_machines(sb_data_e2.index_data); 5038 } else { 5039 memset(&sb_data_e1x, 0, 5040 sizeof(struct hc_status_block_data_e1x)); 5041 sb_data_e1x.common.state = SB_ENABLED; 5042 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 5043 sb_data_e1x.common.p_func.vf_id = 0xff; 5044 sb_data_e1x.common.p_func.vf_valid = false; 5045 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 5046 sb_data_e1x.common.same_igu_sb_1b = true; 5047 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 5048 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 5049 hc_sm_p = sb_data_e1x.common.state_machine; 5050 sb_data_p = (u32 *)&sb_data_e1x; 5051 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5052 bnx2x_map_sb_state_machines(sb_data_e1x.index_data); 5053 } 5054 5055 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 5056 igu_sb_id, igu_seg_id); 5057 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 5058 igu_sb_id, igu_seg_id); 5059 5060 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); 5061 5062 /* write indecies to HW */ 5063 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5064} 5065 5066static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 5067 u16 tx_usec, u16 rx_usec) 5068{ 5069 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 5070 false, rx_usec); 5071 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5072 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 5073 tx_usec); 5074 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5075 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 5076 tx_usec); 5077 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5078 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 5079 tx_usec); 5080} 5081 5082static void bnx2x_init_def_sb(struct bnx2x *bp) 5083{ 5084 struct host_sp_status_block *def_sb = bp->def_status_blk; 5085 dma_addr_t mapping = bp->def_status_blk_mapping; 5086 int igu_sp_sb_index; 5087 int igu_seg_id; 5088 int port = BP_PORT(bp); 5089 int func = BP_FUNC(bp); 5090 int reg_offset, reg_offset_en5; 5091 u64 section; 5092 int index; 5093 struct hc_sp_status_block_data sp_sb_data; 5094 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5095 5096 if (CHIP_INT_MODE_IS_BC(bp)) { 5097 igu_sp_sb_index = DEF_SB_IGU_ID; 5098 igu_seg_id = HC_SEG_ACCESS_DEF; 5099 } else { 5100 igu_sp_sb_index = bp->igu_dsb_id; 5101 igu_seg_id = IGU_SEG_ACCESS_DEF; 5102 } 5103 5104 /* ATTN */ 5105 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5106 atten_status_block); 5107 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 5108 5109 bp->attn_state = 0; 5110 5111 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 5112 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 5113 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 5114 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); 5115 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 5116 int sindex; 5117 /* take care of sig[0]..sig[4] */ 5118 for (sindex = 0; sindex < 4; sindex++) 5119 bp->attn_group[index].sig[sindex] = 5120 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 5121 5122 if (!CHIP_IS_E1x(bp)) 5123 /* 5124 * enable5 is separate from the rest of the registers, 5125 * and therefore the address skip is 4 5126 * and not 16 between the different groups 5127 */ 5128 bp->attn_group[index].sig[4] = REG_RD(bp, 5129 reg_offset_en5 + 0x4*index); 5130 else 5131 bp->attn_group[index].sig[4] = 0; 5132 } 5133 5134 if (bp->common.int_block == INT_BLOCK_HC) { 5135 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 5136 HC_REG_ATTN_MSG0_ADDR_L); 5137 5138 REG_WR(bp, reg_offset, U64_LO(section)); 5139 REG_WR(bp, reg_offset + 4, U64_HI(section)); 5140 } else if (!CHIP_IS_E1x(bp)) { 5141 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 5142 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 5143 } 5144 5145 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5146 sp_sb); 5147 5148 bnx2x_zero_sp_sb(bp); 5149 5150 sp_sb_data.state = SB_ENABLED; 5151 sp_sb_data.host_sb_addr.lo = U64_LO(section); 5152 sp_sb_data.host_sb_addr.hi = U64_HI(section); 5153 sp_sb_data.igu_sb_id = igu_sp_sb_index; 5154 sp_sb_data.igu_seg_id = igu_seg_id; 5155 sp_sb_data.p_func.pf_id = func; 5156 sp_sb_data.p_func.vnic_id = BP_VN(bp); 5157 sp_sb_data.p_func.vf_id = 0xff; 5158 5159 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5160 5161 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 5162} 5163 5164void bnx2x_update_coalesce(struct bnx2x *bp) 5165{ 5166 int i; 5167 5168 for_each_eth_queue(bp, i) 5169 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 5170 bp->tx_ticks, bp->rx_ticks); 5171} 5172 5173static void bnx2x_init_sp_ring(struct bnx2x *bp) 5174{ 5175 spin_lock_init(&bp->spq_lock); 5176 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 5177 5178 bp->spq_prod_idx = 0; 5179 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 5180 bp->spq_prod_bd = bp->spq; 5181 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 5182} 5183 5184static void bnx2x_init_eq_ring(struct bnx2x *bp) 5185{ 5186 int i; 5187 for (i = 1; i <= NUM_EQ_PAGES; i++) { 5188 union event_ring_elem *elem = 5189 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 5190 5191 elem->next_page.addr.hi = 5192 cpu_to_le32(U64_HI(bp->eq_mapping + 5193 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 5194 elem->next_page.addr.lo = 5195 cpu_to_le32(U64_LO(bp->eq_mapping + 5196 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 5197 } 5198 bp->eq_cons = 0; 5199 bp->eq_prod = NUM_EQ_DESC; 5200 bp->eq_cons_sb = BNX2X_EQ_INDEX; 5201 /* we want a warning message before it gets rought... */ 5202 atomic_set(&bp->eq_spq_left, 5203 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 5204} 5205 5206 5207/* called with netif_addr_lock_bh() */ 5208void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 5209 unsigned long rx_mode_flags, 5210 unsigned long rx_accept_flags, 5211 unsigned long tx_accept_flags, 5212 unsigned long ramrod_flags) 5213{ 5214 struct bnx2x_rx_mode_ramrod_params ramrod_param; 5215 int rc; 5216 5217 memset(&ramrod_param, 0, sizeof(ramrod_param)); 5218 5219 /* Prepare ramrod parameters */ 5220 ramrod_param.cid = 0; 5221 ramrod_param.cl_id = cl_id; 5222 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 5223 ramrod_param.func_id = BP_FUNC(bp); 5224 5225 ramrod_param.pstate = &bp->sp_state; 5226 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 5227 5228 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 5229 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 5230 5231 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5232 5233 ramrod_param.ramrod_flags = ramrod_flags; 5234 ramrod_param.rx_mode_flags = rx_mode_flags; 5235 5236 ramrod_param.rx_accept_flags = rx_accept_flags; 5237 ramrod_param.tx_accept_flags = tx_accept_flags; 5238 5239 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 5240 if (rc < 0) { 5241 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 5242 return; 5243 } 5244} 5245 5246/* called with netif_addr_lock_bh() */ 5247void bnx2x_set_storm_rx_mode(struct bnx2x *bp) 5248{ 5249 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 5250 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 5251 5252#ifdef BCM_CNIC 5253 if (!NO_FCOE(bp)) 5254 5255 /* Configure rx_mode of FCoE Queue */ 5256 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 5257#endif 5258 5259 switch (bp->rx_mode) { 5260 case BNX2X_RX_MODE_NONE: 5261 /* 5262 * 'drop all' supersedes any accept flags that may have been 5263 * passed to the function. 5264 */ 5265 break; 5266 case BNX2X_RX_MODE_NORMAL: 5267 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5268 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); 5269 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5270 5271 /* internal switching mode */ 5272 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5273 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); 5274 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5275 5276 break; 5277 case BNX2X_RX_MODE_ALLMULTI: 5278 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5279 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5280 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5281 5282 /* internal switching mode */ 5283 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5284 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5285 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5286 5287 break; 5288 case BNX2X_RX_MODE_PROMISC: 5289 /* According to deffinition of SI mode, iface in promisc mode 5290 * should receive matched and unmatched (in resolution of port) 5291 * unicast packets. 5292 */ 5293 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); 5294 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5295 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5296 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5297 5298 /* internal switching mode */ 5299 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5300 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5301 5302 if (IS_MF_SI(bp)) 5303 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); 5304 else 5305 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5306 5307 break; 5308 default: 5309 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); 5310 return; 5311 } 5312 5313 if (bp->rx_mode != BNX2X_RX_MODE_NONE) { 5314 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); 5315 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); 5316 } 5317 5318 __set_bit(RAMROD_RX, &ramrod_flags); 5319 __set_bit(RAMROD_TX, &ramrod_flags); 5320 5321 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, 5322 tx_accept_flags, ramrod_flags); 5323} 5324 5325static void bnx2x_init_internal_common(struct bnx2x *bp) 5326{ 5327 int i; 5328 5329 if (IS_MF_SI(bp)) 5330 /* 5331 * In switch independent mode, the TSTORM needs to accept 5332 * packets that failed classification, since approximate match 5333 * mac addresses aren't written to NIG LLH 5334 */ 5335 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5336 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); 5337 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ 5338 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5339 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); 5340 5341 /* Zero this manually as its initialization is 5342 currently missing in the initTool */ 5343 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 5344 REG_WR(bp, BAR_USTRORM_INTMEM + 5345 USTORM_AGG_DATA_OFFSET + i * 4, 0); 5346 if (!CHIP_IS_E1x(bp)) { 5347 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 5348 CHIP_INT_MODE_IS_BC(bp) ? 5349 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 5350 } 5351} 5352 5353static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 5354{ 5355 switch (load_code) { 5356 case FW_MSG_CODE_DRV_LOAD_COMMON: 5357 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5358 bnx2x_init_internal_common(bp); 5359 /* no break */ 5360 5361 case FW_MSG_CODE_DRV_LOAD_PORT: 5362 /* nothing to do */ 5363 /* no break */ 5364 5365 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5366 /* internal memory per function is 5367 initialized inside bnx2x_pf_init */ 5368 break; 5369 5370 default: 5371 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5372 break; 5373 } 5374} 5375 5376static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 5377{ 5378 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; 5379} 5380 5381static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 5382{ 5383 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; 5384} 5385 5386static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 5387{ 5388 if (CHIP_IS_E1x(fp->bp)) 5389 return BP_L_ID(fp->bp) + fp->index; 5390 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 5391 return bnx2x_fp_igu_sb_id(fp); 5392} 5393 5394static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 5395{ 5396 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 5397 u8 cos; 5398 unsigned long q_type = 0; 5399 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 5400 fp->rx_queue = fp_idx; 5401 fp->cid = fp_idx; 5402 fp->cl_id = bnx2x_fp_cl_id(fp); 5403 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 5404 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 5405 /* qZone id equals to FW (per path) client id */ 5406 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 5407 5408 /* init shortcut */ 5409 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 5410 5411 /* Setup SB indicies */ 5412 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 5413 5414 /* Configure Queue State object */ 5415 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 5416 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 5417 5418 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 5419 5420 /* init tx data */ 5421 for_each_cos_in_tx_queue(fp, cos) { 5422 bnx2x_init_txdata(bp, &fp->txdata[cos], 5423 CID_COS_TO_TX_ONLY_CID(fp->cid, cos), 5424 FP_COS_TO_TXQ(fp, cos), 5425 BNX2X_TX_SB_INDEX_BASE + cos); 5426 cids[cos] = fp->txdata[cos].cid; 5427 } 5428 5429 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos, 5430 BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 5431 bnx2x_sp_mapping(bp, q_rdata), q_type); 5432 5433 /** 5434 * Configure classification DBs: Always enable Tx switching 5435 */ 5436 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 5437 5438 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 5439 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 5440 fp->igu_sb_id); 5441 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 5442 fp->fw_sb_id, fp->igu_sb_id); 5443 5444 bnx2x_update_fpsb_idx(fp); 5445} 5446 5447void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) 5448{ 5449 int i; 5450 5451 for_each_eth_queue(bp, i) 5452 bnx2x_init_eth_fp(bp, i); 5453#ifdef BCM_CNIC 5454 if (!NO_FCOE(bp)) 5455 bnx2x_init_fcoe_fp(bp); 5456 5457 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 5458 BNX2X_VF_ID_INVALID, false, 5459 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 5460 5461#endif 5462 5463 /* Initialize MOD_ABS interrupts */ 5464 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 5465 bp->common.shmem_base, bp->common.shmem2_base, 5466 BP_PORT(bp)); 5467 /* ensure status block indices were read */ 5468 rmb(); 5469 5470 bnx2x_init_def_sb(bp); 5471 bnx2x_update_dsb_idx(bp); 5472 bnx2x_init_rx_rings(bp); 5473 bnx2x_init_tx_rings(bp); 5474 bnx2x_init_sp_ring(bp); 5475 bnx2x_init_eq_ring(bp); 5476 bnx2x_init_internal(bp, load_code); 5477 bnx2x_pf_init(bp); 5478 bnx2x_stats_init(bp); 5479 5480 /* flush all before enabling interrupts */ 5481 mb(); 5482 mmiowb(); 5483 5484 bnx2x_int_enable(bp); 5485 5486 /* Check for SPIO5 */ 5487 bnx2x_attn_int_deasserted0(bp, 5488 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 5489 AEU_INPUTS_ATTN_BITS_SPIO5); 5490} 5491 5492/* end of nic init */ 5493 5494/* 5495 * gzip service functions 5496 */ 5497 5498static int bnx2x_gunzip_init(struct bnx2x *bp) 5499{ 5500 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 5501 &bp->gunzip_mapping, GFP_KERNEL); 5502 if (bp->gunzip_buf == NULL) 5503 goto gunzip_nomem1; 5504 5505 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 5506 if (bp->strm == NULL) 5507 goto gunzip_nomem2; 5508 5509 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 5510 if (bp->strm->workspace == NULL) 5511 goto gunzip_nomem3; 5512 5513 return 0; 5514 5515gunzip_nomem3: 5516 kfree(bp->strm); 5517 bp->strm = NULL; 5518 5519gunzip_nomem2: 5520 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5521 bp->gunzip_mapping); 5522 bp->gunzip_buf = NULL; 5523 5524gunzip_nomem1: 5525 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); 5526 return -ENOMEM; 5527} 5528 5529static void bnx2x_gunzip_end(struct bnx2x *bp) 5530{ 5531 if (bp->strm) { 5532 vfree(bp->strm->workspace); 5533 kfree(bp->strm); 5534 bp->strm = NULL; 5535 } 5536 5537 if (bp->gunzip_buf) { 5538 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5539 bp->gunzip_mapping); 5540 bp->gunzip_buf = NULL; 5541 } 5542} 5543 5544static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 5545{ 5546 int n, rc; 5547 5548 /* check gzip header */ 5549 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 5550 BNX2X_ERR("Bad gzip header\n"); 5551 return -EINVAL; 5552 } 5553 5554 n = 10; 5555 5556#define FNAME 0x8 5557 5558 if (zbuf[3] & FNAME) 5559 while ((zbuf[n++] != 0) && (n < len)); 5560 5561 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 5562 bp->strm->avail_in = len - n; 5563 bp->strm->next_out = bp->gunzip_buf; 5564 bp->strm->avail_out = FW_BUF_SIZE; 5565 5566 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 5567 if (rc != Z_OK) 5568 return rc; 5569 5570 rc = zlib_inflate(bp->strm, Z_FINISH); 5571 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 5572 netdev_err(bp->dev, "Firmware decompression error: %s\n", 5573 bp->strm->msg); 5574 5575 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 5576 if (bp->gunzip_outlen & 0x3) 5577 netdev_err(bp->dev, 5578 "Firmware decompression error: gunzip_outlen (%d) not aligned\n", 5579 bp->gunzip_outlen); 5580 bp->gunzip_outlen >>= 2; 5581 5582 zlib_inflateEnd(bp->strm); 5583 5584 if (rc == Z_STREAM_END) 5585 return 0; 5586 5587 return rc; 5588} 5589 5590/* nic load/unload */ 5591 5592/* 5593 * General service functions 5594 */ 5595 5596/* send a NIG loopback debug packet */ 5597static void bnx2x_lb_pckt(struct bnx2x *bp) 5598{ 5599 u32 wb_write[3]; 5600 5601 /* Ethernet source and destination addresses */ 5602 wb_write[0] = 0x55555555; 5603 wb_write[1] = 0x55555555; 5604 wb_write[2] = 0x20; /* SOP */ 5605 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5606 5607 /* NON-IP protocol */ 5608 wb_write[0] = 0x09000000; 5609 wb_write[1] = 0x55555555; 5610 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 5611 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5612} 5613 5614/* some of the internal memories 5615 * are not directly readable from the driver 5616 * to test them we send debug packets 5617 */ 5618static int bnx2x_int_mem_test(struct bnx2x *bp) 5619{ 5620 int factor; 5621 int count, i; 5622 u32 val = 0; 5623 5624 if (CHIP_REV_IS_FPGA(bp)) 5625 factor = 120; 5626 else if (CHIP_REV_IS_EMUL(bp)) 5627 factor = 200; 5628 else 5629 factor = 1; 5630 5631 /* Disable inputs of parser neighbor blocks */ 5632 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5633 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5634 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5635 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5636 5637 /* Write 0 to parser credits for CFC search request */ 5638 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5639 5640 /* send Ethernet packet */ 5641 bnx2x_lb_pckt(bp); 5642 5643 /* TODO do i reset NIG statistic? */ 5644 /* Wait until NIG register shows 1 packet of size 0x10 */ 5645 count = 1000 * factor; 5646 while (count) { 5647 5648 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5649 val = *bnx2x_sp(bp, wb_data[0]); 5650 if (val == 0x10) 5651 break; 5652 5653 msleep(10); 5654 count--; 5655 } 5656 if (val != 0x10) { 5657 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5658 return -1; 5659 } 5660 5661 /* Wait until PRS register shows 1 packet */ 5662 count = 1000 * factor; 5663 while (count) { 5664 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5665 if (val == 1) 5666 break; 5667 5668 msleep(10); 5669 count--; 5670 } 5671 if (val != 0x1) { 5672 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5673 return -2; 5674 } 5675 5676 /* Reset and init BRB, PRS */ 5677 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5678 msleep(50); 5679 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5680 msleep(50); 5681 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5682 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5683 5684 DP(NETIF_MSG_HW, "part2\n"); 5685 5686 /* Disable inputs of parser neighbor blocks */ 5687 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5688 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5689 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5690 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5691 5692 /* Write 0 to parser credits for CFC search request */ 5693 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5694 5695 /* send 10 Ethernet packets */ 5696 for (i = 0; i < 10; i++) 5697 bnx2x_lb_pckt(bp); 5698 5699 /* Wait until NIG register shows 10 + 1 5700 packets of size 11*0x10 = 0xb0 */ 5701 count = 1000 * factor; 5702 while (count) { 5703 5704 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5705 val = *bnx2x_sp(bp, wb_data[0]); 5706 if (val == 0xb0) 5707 break; 5708 5709 msleep(10); 5710 count--; 5711 } 5712 if (val != 0xb0) { 5713 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5714 return -3; 5715 } 5716 5717 /* Wait until PRS register shows 2 packets */ 5718 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5719 if (val != 2) 5720 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5721 5722 /* Write 1 to parser credits for CFC search request */ 5723 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 5724 5725 /* Wait until PRS register shows 3 packets */ 5726 msleep(10 * factor); 5727 /* Wait until NIG register shows 1 packet of size 0x10 */ 5728 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5729 if (val != 3) 5730 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5731 5732 /* clear NIG EOP FIFO */ 5733 for (i = 0; i < 11; i++) 5734 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 5735 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 5736 if (val != 1) { 5737 BNX2X_ERR("clear of NIG failed\n"); 5738 return -4; 5739 } 5740 5741 /* Reset and init BRB, PRS, NIG */ 5742 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5743 msleep(50); 5744 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5745 msleep(50); 5746 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5747 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5748#ifndef BCM_CNIC 5749 /* set NIC mode */ 5750 REG_WR(bp, PRS_REG_NIC_MODE, 1); 5751#endif 5752 5753 /* Enable inputs of parser neighbor blocks */ 5754 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 5755 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 5756 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 5757 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 5758 5759 DP(NETIF_MSG_HW, "done\n"); 5760 5761 return 0; /* OK */ 5762} 5763 5764static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 5765{ 5766 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 5767 if (!CHIP_IS_E1x(bp)) 5768 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 5769 else 5770 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 5771 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 5772 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 5773 /* 5774 * mask read length error interrupts in brb for parser 5775 * (parsing unit and 'checksum and crc' unit) 5776 * these errors are legal (PU reads fixed length and CAC can cause 5777 * read length error on truncated packets) 5778 */ 5779 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 5780 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 5781 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 5782 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 5783 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 5784 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 5785/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 5786/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 5787 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 5788 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 5789 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 5790/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 5791/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 5792 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 5793 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 5794 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 5795 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 5796/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 5797/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 5798 5799 if (CHIP_REV_IS_FPGA(bp)) 5800 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); 5801 else if (!CHIP_IS_E1x(bp)) 5802 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 5803 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF 5804 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT 5805 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN 5806 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED 5807 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); 5808 else 5809 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); 5810 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 5811 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 5812 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 5813/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 5814 5815 if (!CHIP_IS_E1x(bp)) 5816 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 5817 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 5818 5819 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 5820 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 5821/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 5822 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 5823} 5824 5825static void bnx2x_reset_common(struct bnx2x *bp) 5826{ 5827 u32 val = 0x1400; 5828 5829 /* reset_common */ 5830 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 5831 0xd3ffff7f); 5832 5833 if (CHIP_IS_E3(bp)) { 5834 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 5835 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 5836 } 5837 5838 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); 5839} 5840 5841static void bnx2x_setup_dmae(struct bnx2x *bp) 5842{ 5843 bp->dmae_ready = 0; 5844 spin_lock_init(&bp->dmae_lock); 5845} 5846 5847static void bnx2x_init_pxp(struct bnx2x *bp) 5848{ 5849 u16 devctl; 5850 int r_order, w_order; 5851 5852 pci_read_config_word(bp->pdev, 5853 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); 5854 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); 5855 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 5856 if (bp->mrrs == -1) 5857 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); 5858 else { 5859 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); 5860 r_order = bp->mrrs; 5861 } 5862 5863 bnx2x_init_pxp_arb(bp, r_order, w_order); 5864} 5865 5866static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 5867{ 5868 int is_required; 5869 u32 val; 5870 int port; 5871 5872 if (BP_NOMCP(bp)) 5873 return; 5874 5875 is_required = 0; 5876 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 5877 SHARED_HW_CFG_FAN_FAILURE_MASK; 5878 5879 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) 5880 is_required = 1; 5881 5882 /* 5883 * The fan failure mechanism is usually related to the PHY type since 5884 * the power consumption of the board is affected by the PHY. Currently, 5885 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 5886 */ 5887 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 5888 for (port = PORT_0; port < PORT_MAX; port++) { 5889 is_required |= 5890 bnx2x_fan_failure_det_req( 5891 bp, 5892 bp->common.shmem_base, 5893 bp->common.shmem2_base, 5894 port); 5895 } 5896 5897 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 5898 5899 if (is_required == 0) 5900 return; 5901 5902 /* Fan failure is indicated by SPIO 5 */ 5903 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, 5904 MISC_REGISTERS_SPIO_INPUT_HI_Z); 5905 5906 /* set to active low mode */ 5907 val = REG_RD(bp, MISC_REG_SPIO_INT); 5908 val |= ((1 << MISC_REGISTERS_SPIO_5) << 5909 MISC_REGISTERS_SPIO_INT_OLD_SET_POS); 5910 REG_WR(bp, MISC_REG_SPIO_INT, val); 5911 5912 /* enable interrupt to signal the IGU */ 5913 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 5914 val |= (1 << MISC_REGISTERS_SPIO_5); 5915 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 5916} 5917 5918static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) 5919{ 5920 u32 offset = 0; 5921 5922 if (CHIP_IS_E1(bp)) 5923 return; 5924 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) 5925 return; 5926 5927 switch (BP_ABS_FUNC(bp)) { 5928 case 0: 5929 offset = PXP2_REG_PGL_PRETEND_FUNC_F0; 5930 break; 5931 case 1: 5932 offset = PXP2_REG_PGL_PRETEND_FUNC_F1; 5933 break; 5934 case 2: 5935 offset = PXP2_REG_PGL_PRETEND_FUNC_F2; 5936 break; 5937 case 3: 5938 offset = PXP2_REG_PGL_PRETEND_FUNC_F3; 5939 break; 5940 case 4: 5941 offset = PXP2_REG_PGL_PRETEND_FUNC_F4; 5942 break; 5943 case 5: 5944 offset = PXP2_REG_PGL_PRETEND_FUNC_F5; 5945 break; 5946 case 6: 5947 offset = PXP2_REG_PGL_PRETEND_FUNC_F6; 5948 break; 5949 case 7: 5950 offset = PXP2_REG_PGL_PRETEND_FUNC_F7; 5951 break; 5952 default: 5953 return; 5954 } 5955 5956 REG_WR(bp, offset, pretend_func_num); 5957 REG_RD(bp, offset); 5958 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); 5959} 5960 5961void bnx2x_pf_disable(struct bnx2x *bp) 5962{ 5963 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 5964 val &= ~IGU_PF_CONF_FUNC_EN; 5965 5966 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 5967 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 5968 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); 5969} 5970 5971static inline void bnx2x__common_init_phy(struct bnx2x *bp) 5972{ 5973 u32 shmem_base[2], shmem2_base[2]; 5974 shmem_base[0] = bp->common.shmem_base; 5975 shmem2_base[0] = bp->common.shmem2_base; 5976 if (!CHIP_IS_E1x(bp)) { 5977 shmem_base[1] = 5978 SHMEM2_RD(bp, other_shmem_base_addr); 5979 shmem2_base[1] = 5980 SHMEM2_RD(bp, other_shmem2_base_addr); 5981 } 5982 bnx2x_acquire_phy_lock(bp); 5983 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, 5984 bp->common.chip_id); 5985 bnx2x_release_phy_lock(bp); 5986} 5987 5988/** 5989 * bnx2x_init_hw_common - initialize the HW at the COMMON phase. 5990 * 5991 * @bp: driver handle 5992 */ 5993static int bnx2x_init_hw_common(struct bnx2x *bp) 5994{ 5995 u32 val; 5996 5997 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); 5998 5999 /* 6000 * take the UNDI lock to protect undi_unload flow from accessing 6001 * registers while we're resetting the chip 6002 */ 6003 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6004 6005 bnx2x_reset_common(bp); 6006 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 6007 6008 val = 0xfffc; 6009 if (CHIP_IS_E3(bp)) { 6010 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 6011 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 6012 } 6013 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 6014 6015 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6016 6017 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 6018 6019 if (!CHIP_IS_E1x(bp)) { 6020 u8 abs_func_id; 6021 6022 /** 6023 * 4-port mode or 2-port mode we need to turn of master-enable 6024 * for everyone, after that, turn it back on for self. 6025 * so, we disregard multi-function or not, and always disable 6026 * for all functions on the given path, this means 0,2,4,6 for 6027 * path 0 and 1,3,5,7 for path 1 6028 */ 6029 for (abs_func_id = BP_PATH(bp); 6030 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { 6031 if (abs_func_id == BP_ABS_FUNC(bp)) { 6032 REG_WR(bp, 6033 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 6034 1); 6035 continue; 6036 } 6037 6038 bnx2x_pretend_func(bp, abs_func_id); 6039 /* clear pf enable */ 6040 bnx2x_pf_disable(bp); 6041 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6042 } 6043 } 6044 6045 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); 6046 if (CHIP_IS_E1(bp)) { 6047 /* enable HW interrupt from PXP on USDM overflow 6048 bit 16 on INT_MASK_0 */ 6049 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 6050 } 6051 6052 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); 6053 bnx2x_init_pxp(bp); 6054 6055#ifdef __BIG_ENDIAN 6056 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); 6057 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); 6058 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 6059 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 6060 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 6061 /* make sure this value is 0 */ 6062 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); 6063 6064/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ 6065 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); 6066 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); 6067 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); 6068 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 6069#endif 6070 6071 bnx2x_ilt_init_page_size(bp, INITOP_SET); 6072 6073 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 6074 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 6075 6076 /* let the HW do it's magic ... */ 6077 msleep(100); 6078 /* finish PXP init */ 6079 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); 6080 if (val != 1) { 6081 BNX2X_ERR("PXP2 CFG failed\n"); 6082 return -EBUSY; 6083 } 6084 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); 6085 if (val != 1) { 6086 BNX2X_ERR("PXP2 RD_INIT failed\n"); 6087 return -EBUSY; 6088 } 6089 6090 /* Timers bug workaround E2 only. We need to set the entire ILT to 6091 * have entries with value "0" and valid bit on. 6092 * This needs to be done by the first PF that is loaded in a path 6093 * (i.e. common phase) 6094 */ 6095 if (!CHIP_IS_E1x(bp)) { 6096/* In E2 there is a bug in the timers block that can cause function 6 / 7 6097 * (i.e. vnic3) to start even if it is marked as "scan-off". 6098 * This occurs when a different function (func2,3) is being marked 6099 * as "scan-off". Real-life scenario for example: if a driver is being 6100 * load-unloaded while func6,7 are down. This will cause the timer to access 6101 * the ilt, translate to a logical address and send a request to read/write. 6102 * Since the ilt for the function that is down is not valid, this will cause 6103 * a translation error which is unrecoverable. 6104 * The Workaround is intended to make sure that when this happens nothing fatal 6105 * will occur. The workaround: 6106 * 1. First PF driver which loads on a path will: 6107 * a. After taking the chip out of reset, by using pretend, 6108 * it will write "0" to the following registers of 6109 * the other vnics. 6110 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6111 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 6112 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 6113 * And for itself it will write '1' to 6114 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 6115 * dmae-operations (writing to pram for example.) 6116 * note: can be done for only function 6,7 but cleaner this 6117 * way. 6118 * b. Write zero+valid to the entire ILT. 6119 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 6120 * VNIC3 (of that port). The range allocated will be the 6121 * entire ILT. This is needed to prevent ILT range error. 6122 * 2. Any PF driver load flow: 6123 * a. ILT update with the physical addresses of the allocated 6124 * logical pages. 6125 * b. Wait 20msec. - note that this timeout is needed to make 6126 * sure there are no requests in one of the PXP internal 6127 * queues with "old" ILT addresses. 6128 * c. PF enable in the PGLC. 6129 * d. Clear the was_error of the PF in the PGLC. (could have 6130 * occured while driver was down) 6131 * e. PF enable in the CFC (WEAK + STRONG) 6132 * f. Timers scan enable 6133 * 3. PF driver unload flow: 6134 * a. Clear the Timers scan_en. 6135 * b. Polling for scan_on=0 for that PF. 6136 * c. Clear the PF enable bit in the PXP. 6137 * d. Clear the PF enable in the CFC (WEAK + STRONG) 6138 * e. Write zero+valid to all ILT entries (The valid bit must 6139 * stay set) 6140 * f. If this is VNIC 3 of a port then also init 6141 * first_timers_ilt_entry to zero and last_timers_ilt_entry 6142 * to the last enrty in the ILT. 6143 * 6144 * Notes: 6145 * Currently the PF error in the PGLC is non recoverable. 6146 * In the future the there will be a recovery routine for this error. 6147 * Currently attention is masked. 6148 * Having an MCP lock on the load/unload process does not guarantee that 6149 * there is no Timer disable during Func6/7 enable. This is because the 6150 * Timers scan is currently being cleared by the MCP on FLR. 6151 * Step 2.d can be done only for PF6/7 and the driver can also check if 6152 * there is error before clearing it. But the flow above is simpler and 6153 * more general. 6154 * All ILT entries are written by zero+valid and not just PF6/7 6155 * ILT entries since in the future the ILT entries allocation for 6156 * PF-s might be dynamic. 6157 */ 6158 struct ilt_client_info ilt_cli; 6159 struct bnx2x_ilt ilt; 6160 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 6161 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); 6162 6163 /* initialize dummy TM client */ 6164 ilt_cli.start = 0; 6165 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 6166 ilt_cli.client_num = ILT_CLIENT_TM; 6167 6168 /* Step 1: set zeroes to all ilt page entries with valid bit on 6169 * Step 2: set the timers first/last ilt entry to point 6170 * to the entire range to prevent ILT range error for 3rd/4th 6171 * vnic (this code assumes existance of the vnic) 6172 * 6173 * both steps performed by call to bnx2x_ilt_client_init_op() 6174 * with dummy TM client 6175 * 6176 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 6177 * and his brother are split registers 6178 */ 6179 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); 6180 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); 6181 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6182 6183 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); 6184 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); 6185 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 6186 } 6187 6188 6189 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 6190 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 6191 6192 if (!CHIP_IS_E1x(bp)) { 6193 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : 6194 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); 6195 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); 6196 6197 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); 6198 6199 /* let the HW do it's magic ... */ 6200 do { 6201 msleep(200); 6202 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); 6203 } while (factor-- && (val != 1)); 6204 6205 if (val != 1) { 6206 BNX2X_ERR("ATC_INIT failed\n"); 6207 return -EBUSY; 6208 } 6209 } 6210 6211 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); 6212 6213 /* clean the DMAE memory */ 6214 bp->dmae_ready = 1; 6215 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); 6216 6217 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); 6218 6219 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); 6220 6221 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); 6222 6223 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); 6224 6225 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); 6226 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); 6227 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); 6228 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); 6229 6230 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); 6231 6232 6233 /* QM queues pointers table */ 6234 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); 6235 6236 /* soft reset pulse */ 6237 REG_WR(bp, QM_REG_SOFT_RESET, 1); 6238 REG_WR(bp, QM_REG_SOFT_RESET, 0); 6239 6240#ifdef BCM_CNIC 6241 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); 6242#endif 6243 6244 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); 6245 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); 6246 if (!CHIP_REV_IS_SLOW(bp)) 6247 /* enable hw interrupt from doorbell Q */ 6248 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6249 6250 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6251 6252 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6253 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 6254 6255 if (!CHIP_IS_E1(bp)) 6256 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); 6257 6258 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) 6259 /* Bit-map indicating which L2 hdrs may appear 6260 * after the basic Ethernet header 6261 */ 6262 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 6263 bp->path_has_ovlan ? 7 : 6); 6264 6265 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); 6266 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); 6267 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); 6268 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); 6269 6270 if (!CHIP_IS_E1x(bp)) { 6271 /* reset VFC memories */ 6272 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6273 VFC_MEMORIES_RST_REG_CAM_RST | 6274 VFC_MEMORIES_RST_REG_RAM_RST); 6275 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6276 VFC_MEMORIES_RST_REG_CAM_RST | 6277 VFC_MEMORIES_RST_REG_RAM_RST); 6278 6279 msleep(20); 6280 } 6281 6282 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); 6283 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); 6284 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); 6285 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); 6286 6287 /* sync semi rtc */ 6288 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6289 0x80000000); 6290 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 6291 0x80000000); 6292 6293 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); 6294 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); 6295 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); 6296 6297 if (!CHIP_IS_E1x(bp)) 6298 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 6299 bp->path_has_ovlan ? 7 : 6); 6300 6301 REG_WR(bp, SRC_REG_SOFT_RST, 1); 6302 6303 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); 6304 6305#ifdef BCM_CNIC 6306 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 6307 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 6308 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); 6309 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); 6310 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); 6311 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 6312 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); 6313 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 6314 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); 6315 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); 6316#endif 6317 REG_WR(bp, SRC_REG_SOFT_RST, 0); 6318 6319 if (sizeof(union cdu_context) != 1024) 6320 /* we currently assume that a context is 1024 bytes */ 6321 dev_alert(&bp->pdev->dev, 6322 "please adjust the size of cdu_context(%ld)\n", 6323 (long)sizeof(union cdu_context)); 6324 6325 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 6326 val = (4 << 24) + (0 << 12) + 1024; 6327 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); 6328 6329 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); 6330 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); 6331 /* enable context validation interrupt from CFC */ 6332 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6333 6334 /* set the thresholds to prevent CFC/CDU race */ 6335 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 6336 6337 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); 6338 6339 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) 6340 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); 6341 6342 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); 6343 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); 6344 6345 /* Reset PCIE errors for debug */ 6346 REG_WR(bp, 0x2814, 0xffffffff); 6347 REG_WR(bp, 0x3820, 0xffffffff); 6348 6349 if (!CHIP_IS_E1x(bp)) { 6350 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 6351 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 6352 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 6353 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 6354 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 6355 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 6356 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 6357 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 6358 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 6359 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 6360 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 6361 } 6362 6363 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); 6364 if (!CHIP_IS_E1(bp)) { 6365 /* in E3 this done in per-port section */ 6366 if (!CHIP_IS_E3(bp)) 6367 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6368 } 6369 if (CHIP_IS_E1H(bp)) 6370 /* not applicable for E2 (and above ...) */ 6371 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); 6372 6373 if (CHIP_REV_IS_SLOW(bp)) 6374 msleep(200); 6375 6376 /* finish CFC init */ 6377 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); 6378 if (val != 1) { 6379 BNX2X_ERR("CFC LL_INIT failed\n"); 6380 return -EBUSY; 6381 } 6382 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); 6383 if (val != 1) { 6384 BNX2X_ERR("CFC AC_INIT failed\n"); 6385 return -EBUSY; 6386 } 6387 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 6388 if (val != 1) { 6389 BNX2X_ERR("CFC CAM_INIT failed\n"); 6390 return -EBUSY; 6391 } 6392 REG_WR(bp, CFC_REG_DEBUG0, 0); 6393 6394 if (CHIP_IS_E1(bp)) { 6395 /* read NIG statistic 6396 to see if this is our first up since powerup */ 6397 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6398 val = *bnx2x_sp(bp, wb_data[0]); 6399 6400 /* do internal memory self test */ 6401 if ((val == 0) && bnx2x_int_mem_test(bp)) { 6402 BNX2X_ERR("internal mem self test failed\n"); 6403 return -EBUSY; 6404 } 6405 } 6406 6407 bnx2x_setup_fan_failure_detection(bp); 6408 6409 /* clear PXP2 attentions */ 6410 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 6411 6412 bnx2x_enable_blocks_attention(bp); 6413 bnx2x_enable_blocks_parity(bp); 6414 6415 if (!BP_NOMCP(bp)) { 6416 if (CHIP_IS_E1x(bp)) 6417 bnx2x__common_init_phy(bp); 6418 } else 6419 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 6420 6421 return 0; 6422} 6423 6424/** 6425 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. 6426 * 6427 * @bp: driver handle 6428 */ 6429static int bnx2x_init_hw_common_chip(struct bnx2x *bp) 6430{ 6431 int rc = bnx2x_init_hw_common(bp); 6432 6433 if (rc) 6434 return rc; 6435 6436 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 6437 if (!BP_NOMCP(bp)) 6438 bnx2x__common_init_phy(bp); 6439 6440 return 0; 6441} 6442 6443static int bnx2x_init_hw_port(struct bnx2x *bp) 6444{ 6445 int port = BP_PORT(bp); 6446 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 6447 u32 low, high; 6448 u32 val; 6449 6450 bnx2x__link_reset(bp); 6451 6452 DP(NETIF_MSG_HW, "starting port init port %d\n", port); 6453 6454 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 6455 6456 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6457 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6458 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6459 6460 /* Timers bug workaround: disables the pf_master bit in pglue at 6461 * common phase, we need to enable it here before any dmae access are 6462 * attempted. Therefore we manually added the enable-master to the 6463 * port phase (it also happens in the function phase) 6464 */ 6465 if (!CHIP_IS_E1x(bp)) 6466 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6467 6468 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6469 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6470 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6471 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6472 6473 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6474 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6475 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6476 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6477 6478 /* QM cid (connection) count */ 6479 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); 6480 6481#ifdef BCM_CNIC 6482 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6483 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 6484 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 6485#endif 6486 6487 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6488 6489 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { 6490 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6491 6492 if (IS_MF(bp)) 6493 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 6494 else if (bp->dev->mtu > 4096) { 6495 if (bp->flags & ONE_PORT_FLAG) 6496 low = 160; 6497 else { 6498 val = bp->dev->mtu; 6499 /* (24*1024 + val*4)/256 */ 6500 low = 96 + (val/64) + 6501 ((val % 64) ? 1 : 0); 6502 } 6503 } else 6504 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 6505 high = low + 56; /* 14*1024/256 */ 6506 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 6507 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 6508 } 6509 6510 if (CHIP_MODE_IS_4_PORT(bp)) 6511 REG_WR(bp, (BP_PORT(bp) ? 6512 BRB1_REG_MAC_GUARANTIED_1 : 6513 BRB1_REG_MAC_GUARANTIED_0), 40); 6514 6515 6516 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6517 if (CHIP_IS_E3B0(bp)) 6518 /* Ovlan exists only if we are in multi-function + 6519 * switch-dependent mode, in switch-independent there 6520 * is no ovlan headers 6521 */ 6522 REG_WR(bp, BP_PORT(bp) ? 6523 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 6524 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 6525 (bp->path_has_ovlan ? 7 : 6)); 6526 6527 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6528 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6529 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6530 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6531 6532 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6533 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6534 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6535 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6536 6537 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6538 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6539 6540 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6541 6542 if (CHIP_IS_E1x(bp)) { 6543 /* configure PBF to work without PAUSE mtu 9000 */ 6544 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 6545 6546 /* update threshold */ 6547 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 6548 /* update init credit */ 6549 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 6550 6551 /* probe changes */ 6552 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 6553 udelay(50); 6554 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 6555 } 6556 6557#ifdef BCM_CNIC 6558 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6559#endif 6560 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6561 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6562 6563 if (CHIP_IS_E1(bp)) { 6564 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6565 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6566 } 6567 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6568 6569 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6570 6571 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6572 /* init aeu_mask_attn_func_0/1: 6573 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 6574 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 6575 * bits 4-7 are used for "per vn group attention" */ 6576 val = IS_MF(bp) ? 0xF7 : 0x7; 6577 /* Enable DCBX attention for all but E1 */ 6578 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 6579 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 6580 6581 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6582 6583 if (!CHIP_IS_E1x(bp)) { 6584 /* Bit-map indicating which L2 hdrs may appear after the 6585 * basic Ethernet header 6586 */ 6587 REG_WR(bp, BP_PORT(bp) ? 6588 NIG_REG_P1_HDRS_AFTER_BASIC : 6589 NIG_REG_P0_HDRS_AFTER_BASIC, 6590 IS_MF_SD(bp) ? 7 : 6); 6591 6592 if (CHIP_IS_E3(bp)) 6593 REG_WR(bp, BP_PORT(bp) ? 6594 NIG_REG_LLH1_MF_MODE : 6595 NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6596 } 6597 if (!CHIP_IS_E3(bp)) 6598 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 6599 6600 if (!CHIP_IS_E1(bp)) { 6601 /* 0x2 disable mf_ov, 0x1 enable */ 6602 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 6603 (IS_MF_SD(bp) ? 0x1 : 0x2)); 6604 6605 if (!CHIP_IS_E1x(bp)) { 6606 val = 0; 6607 switch (bp->mf_mode) { 6608 case MULTI_FUNCTION_SD: 6609 val = 1; 6610 break; 6611 case MULTI_FUNCTION_SI: 6612 val = 2; 6613 break; 6614 } 6615 6616 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : 6617 NIG_REG_LLH0_CLS_TYPE), val); 6618 } 6619 { 6620 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 6621 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 6622 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 6623 } 6624 } 6625 6626 6627 /* If SPIO5 is set to generate interrupts, enable it for this port */ 6628 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6629 if (val & (1 << MISC_REGISTERS_SPIO_5)) { 6630 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 6631 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 6632 val = REG_RD(bp, reg_addr); 6633 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 6634 REG_WR(bp, reg_addr, val); 6635 } 6636 6637 return 0; 6638} 6639 6640static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 6641{ 6642 int reg; 6643 6644 if (CHIP_IS_E1(bp)) 6645 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 6646 else 6647 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 6648 6649 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr)); 6650} 6651 6652static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) 6653{ 6654 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); 6655} 6656 6657static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) 6658{ 6659 u32 i, base = FUNC_ILT_BASE(func); 6660 for (i = base; i < base + ILT_PER_FUNC; i++) 6661 bnx2x_ilt_wr(bp, i, 0); 6662} 6663 6664static int bnx2x_init_hw_func(struct bnx2x *bp) 6665{ 6666 int port = BP_PORT(bp); 6667 int func = BP_FUNC(bp); 6668 int init_phase = PHASE_PF0 + func; 6669 struct bnx2x_ilt *ilt = BP_ILT(bp); 6670 u16 cdu_ilt_start; 6671 u32 addr, val; 6672 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 6673 int i, main_mem_width, rc; 6674 6675 DP(NETIF_MSG_HW, "starting func init func %d\n", func); 6676 6677 /* FLR cleanup - hmmm */ 6678 if (!CHIP_IS_E1x(bp)) { 6679 rc = bnx2x_pf_flr_clnup(bp); 6680 if (rc) 6681 return rc; 6682 } 6683 6684 /* set MSI reconfigure capability */ 6685 if (bp->common.int_block == INT_BLOCK_HC) { 6686 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 6687 val = REG_RD(bp, addr); 6688 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 6689 REG_WR(bp, addr, val); 6690 } 6691 6692 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6693 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6694 6695 ilt = BP_ILT(bp); 6696 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 6697 6698 for (i = 0; i < L2_ILT_LINES(bp); i++) { 6699 ilt->lines[cdu_ilt_start + i].page = 6700 bp->context.vcxt + (ILT_PAGE_CIDS * i); 6701 ilt->lines[cdu_ilt_start + i].page_mapping = 6702 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i); 6703 /* cdu ilt pages are allocated manually so there's no need to 6704 set the size */ 6705 } 6706 bnx2x_ilt_init_op(bp, INITOP_SET); 6707 6708#ifdef BCM_CNIC 6709 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); 6710 6711 /* T1 hash bits value determines the T1 number of entries */ 6712 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 6713#endif 6714 6715#ifndef BCM_CNIC 6716 /* set NIC mode */ 6717 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6718#endif /* BCM_CNIC */ 6719 6720 if (!CHIP_IS_E1x(bp)) { 6721 u32 pf_conf = IGU_PF_CONF_FUNC_EN; 6722 6723 /* Turn on a single ISR mode in IGU if driver is going to use 6724 * INT#x or MSI 6725 */ 6726 if (!(bp->flags & USING_MSIX_FLAG)) 6727 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 6728 /* 6729 * Timers workaround bug: function init part. 6730 * Need to wait 20msec after initializing ILT, 6731 * needed to make sure there are no requests in 6732 * one of the PXP internal queues with "old" ILT addresses 6733 */ 6734 msleep(20); 6735 /* 6736 * Master enable - Due to WB DMAE writes performed before this 6737 * register is re-initialized as part of the regular function 6738 * init 6739 */ 6740 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6741 /* Enable the function in IGU */ 6742 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); 6743 } 6744 6745 bp->dmae_ready = 1; 6746 6747 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6748 6749 if (!CHIP_IS_E1x(bp)) 6750 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); 6751 6752 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6753 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6754 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6755 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6756 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6757 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6758 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6759 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6760 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6761 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6762 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6763 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6764 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6765 6766 if (!CHIP_IS_E1x(bp)) 6767 REG_WR(bp, QM_REG_PF_EN, 1); 6768 6769 if (!CHIP_IS_E1x(bp)) { 6770 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6771 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6772 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6773 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6774 } 6775 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6776 6777 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6778 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6779 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6780 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6781 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6782 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6783 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6784 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6785 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6786 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6787 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6788 if (!CHIP_IS_E1x(bp)) 6789 REG_WR(bp, PBF_REG_DISABLE_PF, 0); 6790 6791 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6792 6793 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6794 6795 if (!CHIP_IS_E1x(bp)) 6796 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); 6797 6798 if (IS_MF(bp)) { 6799 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 6800 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); 6801 } 6802 6803 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6804 6805 /* HC init per function */ 6806 if (bp->common.int_block == INT_BLOCK_HC) { 6807 if (CHIP_IS_E1H(bp)) { 6808 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6809 6810 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6811 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6812 } 6813 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6814 6815 } else { 6816 int num_segs, sb_idx, prod_offset; 6817 6818 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6819 6820 if (!CHIP_IS_E1x(bp)) { 6821 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 6822 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 6823 } 6824 6825 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6826 6827 if (!CHIP_IS_E1x(bp)) { 6828 int dsb_idx = 0; 6829 /** 6830 * Producer memory: 6831 * E2 mode: address 0-135 match to the mapping memory; 6832 * 136 - PF0 default prod; 137 - PF1 default prod; 6833 * 138 - PF2 default prod; 139 - PF3 default prod; 6834 * 140 - PF0 attn prod; 141 - PF1 attn prod; 6835 * 142 - PF2 attn prod; 143 - PF3 attn prod; 6836 * 144-147 reserved. 6837 * 6838 * E1.5 mode - In backward compatible mode; 6839 * for non default SB; each even line in the memory 6840 * holds the U producer and each odd line hold 6841 * the C producer. The first 128 producers are for 6842 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 6843 * producers are for the DSB for each PF. 6844 * Each PF has five segments: (the order inside each 6845 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 6846 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 6847 * 144-147 attn prods; 6848 */ 6849 /* non-default-status-blocks */ 6850 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6851 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 6852 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { 6853 prod_offset = (bp->igu_base_sb + sb_idx) * 6854 num_segs; 6855 6856 for (i = 0; i < num_segs; i++) { 6857 addr = IGU_REG_PROD_CONS_MEMORY + 6858 (prod_offset + i) * 4; 6859 REG_WR(bp, addr, 0); 6860 } 6861 /* send consumer update with value 0 */ 6862 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, 6863 USTORM_ID, 0, IGU_INT_NOP, 1); 6864 bnx2x_igu_clear_sb(bp, 6865 bp->igu_base_sb + sb_idx); 6866 } 6867 6868 /* default-status-blocks */ 6869 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6870 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 6871 6872 if (CHIP_MODE_IS_4_PORT(bp)) 6873 dsb_idx = BP_FUNC(bp); 6874 else 6875 dsb_idx = BP_VN(bp); 6876 6877 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 6878 IGU_BC_BASE_DSB_PROD + dsb_idx : 6879 IGU_NORM_BASE_DSB_PROD + dsb_idx); 6880 6881 /* 6882 * igu prods come in chunks of E1HVN_MAX (4) - 6883 * does not matters what is the current chip mode 6884 */ 6885 for (i = 0; i < (num_segs * E1HVN_MAX); 6886 i += E1HVN_MAX) { 6887 addr = IGU_REG_PROD_CONS_MEMORY + 6888 (prod_offset + i)*4; 6889 REG_WR(bp, addr, 0); 6890 } 6891 /* send consumer update with 0 */ 6892 if (CHIP_INT_MODE_IS_BC(bp)) { 6893 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6894 USTORM_ID, 0, IGU_INT_NOP, 1); 6895 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6896 CSTORM_ID, 0, IGU_INT_NOP, 1); 6897 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6898 XSTORM_ID, 0, IGU_INT_NOP, 1); 6899 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6900 TSTORM_ID, 0, IGU_INT_NOP, 1); 6901 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6902 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6903 } else { 6904 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6905 USTORM_ID, 0, IGU_INT_NOP, 1); 6906 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6907 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6908 } 6909 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); 6910 6911 /* !!! these should become driver const once 6912 rf-tool supports split-68 const */ 6913 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 6914 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 6915 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 6916 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 6917 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 6918 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 6919 } 6920 } 6921 6922 /* Reset PCIE errors for debug */ 6923 REG_WR(bp, 0x2114, 0xffffffff); 6924 REG_WR(bp, 0x2120, 0xffffffff); 6925 6926 if (CHIP_IS_E1x(bp)) { 6927 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 6928 main_mem_base = HC_REG_MAIN_MEMORY + 6929 BP_PORT(bp) * (main_mem_size * 4); 6930 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 6931 main_mem_width = 8; 6932 6933 val = REG_RD(bp, main_mem_prty_clr); 6934 if (val) 6935 DP(NETIF_MSG_HW, 6936 "Hmmm... Parity errors in HC block during function init (0x%x)!\n", 6937 val); 6938 6939 /* Clear "false" parity errors in MSI-X table */ 6940 for (i = main_mem_base; 6941 i < main_mem_base + main_mem_size * 4; 6942 i += main_mem_width) { 6943 bnx2x_read_dmae(bp, i, main_mem_width / 4); 6944 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), 6945 i, main_mem_width / 4); 6946 } 6947 /* Clear HC parity attention */ 6948 REG_RD(bp, main_mem_prty_clr); 6949 } 6950 6951#ifdef BNX2X_STOP_ON_ERROR 6952 /* Enable STORMs SP logging */ 6953 REG_WR8(bp, BAR_USTRORM_INTMEM + 6954 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6955 REG_WR8(bp, BAR_TSTRORM_INTMEM + 6956 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6957 REG_WR8(bp, BAR_CSTRORM_INTMEM + 6958 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6959 REG_WR8(bp, BAR_XSTRORM_INTMEM + 6960 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6961#endif 6962 6963 bnx2x_phy_probe(&bp->link_params); 6964 6965 return 0; 6966} 6967 6968 6969void bnx2x_free_mem(struct bnx2x *bp) 6970{ 6971 /* fastpath */ 6972 bnx2x_free_fp_mem(bp); 6973 /* end of fastpath */ 6974 6975 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 6976 sizeof(struct host_sp_status_block)); 6977 6978 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 6979 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 6980 6981 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 6982 sizeof(struct bnx2x_slowpath)); 6983 6984 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping, 6985 bp->context.size); 6986 6987 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); 6988 6989 BNX2X_FREE(bp->ilt->lines); 6990 6991#ifdef BCM_CNIC 6992 if (!CHIP_IS_E1x(bp)) 6993 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, 6994 sizeof(struct host_hc_status_block_e2)); 6995 else 6996 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, 6997 sizeof(struct host_hc_status_block_e1x)); 6998 6999 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 7000#endif 7001 7002 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 7003 7004 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, 7005 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7006} 7007 7008static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) 7009{ 7010 int num_groups; 7011 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1; 7012 7013 /* number of queues for statistics is number of eth queues + FCoE */ 7014 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats; 7015 7016 /* Total number of FW statistics requests = 7017 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats + 7018 * num of queues 7019 */ 7020 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats; 7021 7022 7023 /* Request is built from stats_query_header and an array of 7024 * stats_query_cmd_group each of which contains 7025 * STATS_QUERY_CMD_COUNT rules. The real number or requests is 7026 * configured in the stats_query_header. 7027 */ 7028 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) + 7029 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0); 7030 7031 bp->fw_stats_req_sz = sizeof(struct stats_query_header) + 7032 num_groups * sizeof(struct stats_query_cmd_group); 7033 7034 /* Data for statistics requests + stats_conter 7035 * 7036 * stats_counter holds per-STORM counters that are incremented 7037 * when STORM has finished with the current request. 7038 * 7039 * memory for FCoE offloaded statistics are counted anyway, 7040 * even if they will not be sent. 7041 */ 7042 bp->fw_stats_data_sz = sizeof(struct per_port_stats) + 7043 sizeof(struct per_pf_stats) + 7044 sizeof(struct fcoe_statistics_params) + 7045 sizeof(struct per_queue_stats) * num_queue_stats + 7046 sizeof(struct stats_counter); 7047 7048 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, 7049 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7050 7051 /* Set shortcuts */ 7052 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; 7053 bp->fw_stats_req_mapping = bp->fw_stats_mapping; 7054 7055 bp->fw_stats_data = (struct bnx2x_fw_stats_data *) 7056 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); 7057 7058 bp->fw_stats_data_mapping = bp->fw_stats_mapping + 7059 bp->fw_stats_req_sz; 7060 return 0; 7061 7062alloc_mem_err: 7063 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 7064 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7065 BNX2X_ERR("Can't allocate memory\n"); 7066 return -ENOMEM; 7067} 7068 7069 7070int bnx2x_alloc_mem(struct bnx2x *bp) 7071{ 7072#ifdef BCM_CNIC 7073 if (!CHIP_IS_E1x(bp)) 7074 /* size = the status block + ramrod buffers */ 7075 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, 7076 sizeof(struct host_hc_status_block_e2)); 7077 else 7078 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, 7079 sizeof(struct host_hc_status_block_e1x)); 7080 7081 /* allocate searcher T2 table */ 7082 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); 7083#endif 7084 7085 7086 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, 7087 sizeof(struct host_sp_status_block)); 7088 7089 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, 7090 sizeof(struct bnx2x_slowpath)); 7091 7092#ifdef BCM_CNIC 7093 /* write address to which L5 should insert its values */ 7094 bp->cnic_eth_dev.addr_drv_info_to_mcp = &bp->slowpath->drv_info_to_mcp; 7095#endif 7096 7097 /* Allocated memory for FW statistics */ 7098 if (bnx2x_alloc_fw_stats_mem(bp)) 7099 goto alloc_mem_err; 7100 7101 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); 7102 7103 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping, 7104 bp->context.size); 7105 7106 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); 7107 7108 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) 7109 goto alloc_mem_err; 7110 7111 /* Slow path ring */ 7112 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); 7113 7114 /* EQ */ 7115 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, 7116 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7117 7118 7119 /* fastpath */ 7120 /* need to be done at the end, since it's self adjusting to amount 7121 * of memory available for RSS queues 7122 */ 7123 if (bnx2x_alloc_fp_mem(bp)) 7124 goto alloc_mem_err; 7125 return 0; 7126 7127alloc_mem_err: 7128 bnx2x_free_mem(bp); 7129 BNX2X_ERR("Can't allocate memory\n"); 7130 return -ENOMEM; 7131} 7132 7133/* 7134 * Init service functions 7135 */ 7136 7137int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 7138 struct bnx2x_vlan_mac_obj *obj, bool set, 7139 int mac_type, unsigned long *ramrod_flags) 7140{ 7141 int rc; 7142 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 7143 7144 memset(&ramrod_param, 0, sizeof(ramrod_param)); 7145 7146 /* Fill general parameters */ 7147 ramrod_param.vlan_mac_obj = obj; 7148 ramrod_param.ramrod_flags = *ramrod_flags; 7149 7150 /* Fill a user request section if needed */ 7151 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 7152 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 7153 7154 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 7155 7156 /* Set the command: ADD or DEL */ 7157 if (set) 7158 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 7159 else 7160 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 7161 } 7162 7163 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 7164 if (rc < 0) 7165 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); 7166 return rc; 7167} 7168 7169int bnx2x_del_all_macs(struct bnx2x *bp, 7170 struct bnx2x_vlan_mac_obj *mac_obj, 7171 int mac_type, bool wait_for_comp) 7172{ 7173 int rc; 7174 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 7175 7176 /* Wait for completion of requested */ 7177 if (wait_for_comp) 7178 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7179 7180 /* Set the mac type of addresses we want to clear */ 7181 __set_bit(mac_type, &vlan_mac_flags); 7182 7183 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); 7184 if (rc < 0) 7185 BNX2X_ERR("Failed to delete MACs: %d\n", rc); 7186 7187 return rc; 7188} 7189 7190int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) 7191{ 7192 unsigned long ramrod_flags = 0; 7193 7194#ifdef BCM_CNIC 7195 if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_STORAGE_SD(bp)) { 7196 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN, 7197 "Ignoring Zero MAC for STORAGE SD mode\n"); 7198 return 0; 7199 } 7200#endif 7201 7202 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); 7203 7204 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7205 /* Eth MAC is set on RSS leading client (fp[0]) */ 7206 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set, 7207 BNX2X_ETH_MAC, &ramrod_flags); 7208} 7209 7210int bnx2x_setup_leading(struct bnx2x *bp) 7211{ 7212 return bnx2x_setup_queue(bp, &bp->fp[0], 1); 7213} 7214 7215/** 7216 * bnx2x_set_int_mode - configure interrupt mode 7217 * 7218 * @bp: driver handle 7219 * 7220 * In case of MSI-X it will also try to enable MSI-X. 7221 */ 7222static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) 7223{ 7224 switch (int_mode) { 7225 case INT_MODE_MSI: 7226 bnx2x_enable_msi(bp); 7227 /* falling through... */ 7228 case INT_MODE_INTx: 7229 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7230 BNX2X_DEV_INFO("set number of queues to 1\n"); 7231 break; 7232 default: 7233 /* Set number of queues according to bp->multi_mode value */ 7234 bnx2x_set_num_queues(bp); 7235 7236 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 7237 7238 /* if we can't use MSI-X we only need one fp, 7239 * so try to enable MSI-X with the requested number of fp's 7240 * and fallback to MSI or legacy INTx with one fp 7241 */ 7242 if (bnx2x_enable_msix(bp)) { 7243 /* failed to enable MSI-X */ 7244 BNX2X_DEV_INFO("Failed to enable MSI-X (%d), set number of queues to %d\n", 7245 bp->num_queues, 1 + NON_ETH_CONTEXT_USE); 7246 7247 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7248 7249 /* Try to enable MSI */ 7250 if (!(bp->flags & DISABLE_MSI_FLAG)) 7251 bnx2x_enable_msi(bp); 7252 } 7253 break; 7254 } 7255} 7256 7257/* must be called prioir to any HW initializations */ 7258static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) 7259{ 7260 return L2_ILT_LINES(bp); 7261} 7262 7263void bnx2x_ilt_set_info(struct bnx2x *bp) 7264{ 7265 struct ilt_client_info *ilt_client; 7266 struct bnx2x_ilt *ilt = BP_ILT(bp); 7267 u16 line = 0; 7268 7269 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); 7270 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); 7271 7272 /* CDU */ 7273 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 7274 ilt_client->client_num = ILT_CLIENT_CDU; 7275 ilt_client->page_size = CDU_ILT_PAGE_SZ; 7276 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 7277 ilt_client->start = line; 7278 line += bnx2x_cid_ilt_lines(bp); 7279#ifdef BCM_CNIC 7280 line += CNIC_ILT_LINES; 7281#endif 7282 ilt_client->end = line - 1; 7283 7284 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 7285 ilt_client->start, 7286 ilt_client->end, 7287 ilt_client->page_size, 7288 ilt_client->flags, 7289 ilog2(ilt_client->page_size >> 12)); 7290 7291 /* QM */ 7292 if (QM_INIT(bp->qm_cid_count)) { 7293 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 7294 ilt_client->client_num = ILT_CLIENT_QM; 7295 ilt_client->page_size = QM_ILT_PAGE_SZ; 7296 ilt_client->flags = 0; 7297 ilt_client->start = line; 7298 7299 /* 4 bytes for each cid */ 7300 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 7301 QM_ILT_PAGE_SZ); 7302 7303 ilt_client->end = line - 1; 7304 7305 DP(NETIF_MSG_IFUP, 7306 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 7307 ilt_client->start, 7308 ilt_client->end, 7309 ilt_client->page_size, 7310 ilt_client->flags, 7311 ilog2(ilt_client->page_size >> 12)); 7312 7313 } 7314 /* SRC */ 7315 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 7316#ifdef BCM_CNIC 7317 ilt_client->client_num = ILT_CLIENT_SRC; 7318 ilt_client->page_size = SRC_ILT_PAGE_SZ; 7319 ilt_client->flags = 0; 7320 ilt_client->start = line; 7321 line += SRC_ILT_LINES; 7322 ilt_client->end = line - 1; 7323 7324 DP(NETIF_MSG_IFUP, 7325 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 7326 ilt_client->start, 7327 ilt_client->end, 7328 ilt_client->page_size, 7329 ilt_client->flags, 7330 ilog2(ilt_client->page_size >> 12)); 7331 7332#else 7333 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7334#endif 7335 7336 /* TM */ 7337 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 7338#ifdef BCM_CNIC 7339 ilt_client->client_num = ILT_CLIENT_TM; 7340 ilt_client->page_size = TM_ILT_PAGE_SZ; 7341 ilt_client->flags = 0; 7342 ilt_client->start = line; 7343 line += TM_ILT_LINES; 7344 ilt_client->end = line - 1; 7345 7346 DP(NETIF_MSG_IFUP, 7347 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 7348 ilt_client->start, 7349 ilt_client->end, 7350 ilt_client->page_size, 7351 ilt_client->flags, 7352 ilog2(ilt_client->page_size >> 12)); 7353 7354#else 7355 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7356#endif 7357 BUG_ON(line > ILT_MAX_LINES); 7358} 7359 7360/** 7361 * bnx2x_pf_q_prep_init - prepare INIT transition parameters 7362 * 7363 * @bp: driver handle 7364 * @fp: pointer to fastpath 7365 * @init_params: pointer to parameters structure 7366 * 7367 * parameters configured: 7368 * - HC configuration 7369 * - Queue's CDU context 7370 */ 7371static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp, 7372 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) 7373{ 7374 7375 u8 cos; 7376 /* FCoE Queue uses Default SB, thus has no HC capabilities */ 7377 if (!IS_FCOE_FP(fp)) { 7378 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); 7379 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); 7380 7381 /* If HC is supporterd, enable host coalescing in the transition 7382 * to INIT state. 7383 */ 7384 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); 7385 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); 7386 7387 /* HC rate */ 7388 init_params->rx.hc_rate = bp->rx_ticks ? 7389 (1000000 / bp->rx_ticks) : 0; 7390 init_params->tx.hc_rate = bp->tx_ticks ? 7391 (1000000 / bp->tx_ticks) : 0; 7392 7393 /* FW SB ID */ 7394 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = 7395 fp->fw_sb_id; 7396 7397 /* 7398 * CQ index among the SB indices: FCoE clients uses the default 7399 * SB, therefore it's different. 7400 */ 7401 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 7402 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 7403 } 7404 7405 /* set maximum number of COSs supported by this queue */ 7406 init_params->max_cos = fp->max_cos; 7407 7408 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", 7409 fp->index, init_params->max_cos); 7410 7411 /* set the context pointers queue object */ 7412 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) 7413 init_params->cxts[cos] = 7414 &bp->context.vcxt[fp->txdata[cos].cid].eth; 7415} 7416 7417int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7418 struct bnx2x_queue_state_params *q_params, 7419 struct bnx2x_queue_setup_tx_only_params *tx_only_params, 7420 int tx_index, bool leading) 7421{ 7422 memset(tx_only_params, 0, sizeof(*tx_only_params)); 7423 7424 /* Set the command */ 7425 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 7426 7427 /* Set tx-only QUEUE flags: don't zero statistics */ 7428 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); 7429 7430 /* choose the index of the cid to send the slow path on */ 7431 tx_only_params->cid_index = tx_index; 7432 7433 /* Set general TX_ONLY_SETUP parameters */ 7434 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); 7435 7436 /* Set Tx TX_ONLY_SETUP parameters */ 7437 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 7438 7439 DP(NETIF_MSG_IFUP, 7440 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", 7441 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 7442 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 7443 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 7444 7445 /* send the ramrod */ 7446 return bnx2x_queue_state_change(bp, q_params); 7447} 7448 7449 7450/** 7451 * bnx2x_setup_queue - setup queue 7452 * 7453 * @bp: driver handle 7454 * @fp: pointer to fastpath 7455 * @leading: is leading 7456 * 7457 * This function performs 2 steps in a Queue state machine 7458 * actually: 1) RESET->INIT 2) INIT->SETUP 7459 */ 7460 7461int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7462 bool leading) 7463{ 7464 struct bnx2x_queue_state_params q_params = {NULL}; 7465 struct bnx2x_queue_setup_params *setup_params = 7466 &q_params.params.setup; 7467 struct bnx2x_queue_setup_tx_only_params *tx_only_params = 7468 &q_params.params.tx_only; 7469 int rc; 7470 u8 tx_index; 7471 7472 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); 7473 7474 /* reset IGU state skip FCoE L2 queue */ 7475 if (!IS_FCOE_FP(fp)) 7476 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, 7477 IGU_INT_ENABLE, 0); 7478 7479 q_params.q_obj = &fp->q_obj; 7480 /* We want to wait for completion in this context */ 7481 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7482 7483 /* Prepare the INIT parameters */ 7484 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); 7485 7486 /* Set the command */ 7487 q_params.cmd = BNX2X_Q_CMD_INIT; 7488 7489 /* Change the state to INIT */ 7490 rc = bnx2x_queue_state_change(bp, &q_params); 7491 if (rc) { 7492 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); 7493 return rc; 7494 } 7495 7496 DP(NETIF_MSG_IFUP, "init complete\n"); 7497 7498 7499 /* Now move the Queue to the SETUP state... */ 7500 memset(setup_params, 0, sizeof(*setup_params)); 7501 7502 /* Set QUEUE flags */ 7503 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); 7504 7505 /* Set general SETUP parameters */ 7506 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, 7507 FIRST_TX_COS_INDEX); 7508 7509 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, 7510 &setup_params->rxq_params); 7511 7512 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, 7513 FIRST_TX_COS_INDEX); 7514 7515 /* Set the command */ 7516 q_params.cmd = BNX2X_Q_CMD_SETUP; 7517 7518 /* Change the state to SETUP */ 7519 rc = bnx2x_queue_state_change(bp, &q_params); 7520 if (rc) { 7521 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); 7522 return rc; 7523 } 7524 7525 /* loop through the relevant tx-only indices */ 7526 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7527 tx_index < fp->max_cos; 7528 tx_index++) { 7529 7530 /* prepare and send tx-only ramrod*/ 7531 rc = bnx2x_setup_tx_only(bp, fp, &q_params, 7532 tx_only_params, tx_index, leading); 7533 if (rc) { 7534 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", 7535 fp->index, tx_index); 7536 return rc; 7537 } 7538 } 7539 7540 return rc; 7541} 7542 7543static int bnx2x_stop_queue(struct bnx2x *bp, int index) 7544{ 7545 struct bnx2x_fastpath *fp = &bp->fp[index]; 7546 struct bnx2x_fp_txdata *txdata; 7547 struct bnx2x_queue_state_params q_params = {NULL}; 7548 int rc, tx_index; 7549 7550 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); 7551 7552 q_params.q_obj = &fp->q_obj; 7553 /* We want to wait for completion in this context */ 7554 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7555 7556 7557 /* close tx-only connections */ 7558 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7559 tx_index < fp->max_cos; 7560 tx_index++){ 7561 7562 /* ascertain this is a normal queue*/ 7563 txdata = &fp->txdata[tx_index]; 7564 7565 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", 7566 txdata->txq_index); 7567 7568 /* send halt terminate on tx-only connection */ 7569 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7570 memset(&q_params.params.terminate, 0, 7571 sizeof(q_params.params.terminate)); 7572 q_params.params.terminate.cid_index = tx_index; 7573 7574 rc = bnx2x_queue_state_change(bp, &q_params); 7575 if (rc) 7576 return rc; 7577 7578 /* send halt terminate on tx-only connection */ 7579 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7580 memset(&q_params.params.cfc_del, 0, 7581 sizeof(q_params.params.cfc_del)); 7582 q_params.params.cfc_del.cid_index = tx_index; 7583 rc = bnx2x_queue_state_change(bp, &q_params); 7584 if (rc) 7585 return rc; 7586 } 7587 /* Stop the primary connection: */ 7588 /* ...halt the connection */ 7589 q_params.cmd = BNX2X_Q_CMD_HALT; 7590 rc = bnx2x_queue_state_change(bp, &q_params); 7591 if (rc) 7592 return rc; 7593 7594 /* ...terminate the connection */ 7595 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7596 memset(&q_params.params.terminate, 0, 7597 sizeof(q_params.params.terminate)); 7598 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 7599 rc = bnx2x_queue_state_change(bp, &q_params); 7600 if (rc) 7601 return rc; 7602 /* ...delete cfc entry */ 7603 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7604 memset(&q_params.params.cfc_del, 0, 7605 sizeof(q_params.params.cfc_del)); 7606 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 7607 return bnx2x_queue_state_change(bp, &q_params); 7608} 7609 7610 7611static void bnx2x_reset_func(struct bnx2x *bp) 7612{ 7613 int port = BP_PORT(bp); 7614 int func = BP_FUNC(bp); 7615 int i; 7616 7617 /* Disable the function in the FW */ 7618 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 7619 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 7620 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 7621 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 7622 7623 /* FP SBs */ 7624 for_each_eth_queue(bp, i) { 7625 struct bnx2x_fastpath *fp = &bp->fp[i]; 7626 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7627 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 7628 SB_DISABLED); 7629 } 7630 7631#ifdef BCM_CNIC 7632 /* CNIC SB */ 7633 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7634 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), 7635 SB_DISABLED); 7636#endif 7637 /* SP SB */ 7638 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7639 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 7640 SB_DISABLED); 7641 7642 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) 7643 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 7644 0); 7645 7646 /* Configure IGU */ 7647 if (bp->common.int_block == INT_BLOCK_HC) { 7648 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7649 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7650 } else { 7651 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 7652 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 7653 } 7654 7655#ifdef BCM_CNIC 7656 /* Disable Timer scan */ 7657 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 7658 /* 7659 * Wait for at least 10ms and up to 2 second for the timers scan to 7660 * complete 7661 */ 7662 for (i = 0; i < 200; i++) { 7663 msleep(10); 7664 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) 7665 break; 7666 } 7667#endif 7668 /* Clear ILT */ 7669 bnx2x_clear_func_ilt(bp, func); 7670 7671 /* Timers workaround bug for E2: if this is vnic-3, 7672 * we need to set the entire ilt range for this timers. 7673 */ 7674 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { 7675 struct ilt_client_info ilt_cli; 7676 /* use dummy TM client */ 7677 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 7678 ilt_cli.start = 0; 7679 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 7680 ilt_cli.client_num = ILT_CLIENT_TM; 7681 7682 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); 7683 } 7684 7685 /* this assumes that reset_port() called before reset_func()*/ 7686 if (!CHIP_IS_E1x(bp)) 7687 bnx2x_pf_disable(bp); 7688 7689 bp->dmae_ready = 0; 7690} 7691 7692static void bnx2x_reset_port(struct bnx2x *bp) 7693{ 7694 int port = BP_PORT(bp); 7695 u32 val; 7696 7697 /* Reset physical Link */ 7698 bnx2x__link_reset(bp); 7699 7700 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 7701 7702 /* Do not rcv packets to BRB */ 7703 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 7704 /* Do not direct rcv packets that are not for MCP to the BRB */ 7705 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 7706 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 7707 7708 /* Configure AEU */ 7709 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 7710 7711 msleep(100); 7712 /* Check for BRB port occupancy */ 7713 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 7714 if (val) 7715 DP(NETIF_MSG_IFDOWN, 7716 "BRB1 is not empty %d blocks are occupied\n", val); 7717 7718 /* TODO: Close Doorbell port? */ 7719} 7720 7721static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) 7722{ 7723 struct bnx2x_func_state_params func_params = {NULL}; 7724 7725 /* Prepare parameters for function state transitions */ 7726 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7727 7728 func_params.f_obj = &bp->func_obj; 7729 func_params.cmd = BNX2X_F_CMD_HW_RESET; 7730 7731 func_params.params.hw_init.load_phase = load_code; 7732 7733 return bnx2x_func_state_change(bp, &func_params); 7734} 7735 7736static inline int bnx2x_func_stop(struct bnx2x *bp) 7737{ 7738 struct bnx2x_func_state_params func_params = {NULL}; 7739 int rc; 7740 7741 /* Prepare parameters for function state transitions */ 7742 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7743 func_params.f_obj = &bp->func_obj; 7744 func_params.cmd = BNX2X_F_CMD_STOP; 7745 7746 /* 7747 * Try to stop the function the 'good way'. If fails (in case 7748 * of a parity error during bnx2x_chip_cleanup()) and we are 7749 * not in a debug mode, perform a state transaction in order to 7750 * enable further HW_RESET transaction. 7751 */ 7752 rc = bnx2x_func_state_change(bp, &func_params); 7753 if (rc) { 7754#ifdef BNX2X_STOP_ON_ERROR 7755 return rc; 7756#else 7757 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); 7758 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 7759 return bnx2x_func_state_change(bp, &func_params); 7760#endif 7761 } 7762 7763 return 0; 7764} 7765 7766/** 7767 * bnx2x_send_unload_req - request unload mode from the MCP. 7768 * 7769 * @bp: driver handle 7770 * @unload_mode: requested function's unload mode 7771 * 7772 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 7773 */ 7774u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 7775{ 7776 u32 reset_code = 0; 7777 int port = BP_PORT(bp); 7778 7779 /* Select the UNLOAD request mode */ 7780 if (unload_mode == UNLOAD_NORMAL) 7781 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7782 7783 else if (bp->flags & NO_WOL_FLAG) 7784 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 7785 7786 else if (bp->wol) { 7787 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 7788 u8 *mac_addr = bp->dev->dev_addr; 7789 u32 val; 7790 u16 pmc; 7791 7792 /* The mac address is written to entries 1-4 to 7793 * preserve entry 0 which is used by the PMF 7794 */ 7795 u8 entry = (BP_VN(bp) + 1)*8; 7796 7797 val = (mac_addr[0] << 8) | mac_addr[1]; 7798 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 7799 7800 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 7801 (mac_addr[4] << 8) | mac_addr[5]; 7802 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 7803 7804 /* Enable the PME and clear the status */ 7805 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); 7806 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; 7807 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); 7808 7809 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 7810 7811 } else 7812 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7813 7814 /* Send the request to the MCP */ 7815 if (!BP_NOMCP(bp)) 7816 reset_code = bnx2x_fw_command(bp, reset_code, 0); 7817 else { 7818 int path = BP_PATH(bp); 7819 7820 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", 7821 path, load_count[path][0], load_count[path][1], 7822 load_count[path][2]); 7823 load_count[path][0]--; 7824 load_count[path][1 + port]--; 7825 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", 7826 path, load_count[path][0], load_count[path][1], 7827 load_count[path][2]); 7828 if (load_count[path][0] == 0) 7829 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 7830 else if (load_count[path][1 + port] == 0) 7831 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 7832 else 7833 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 7834 } 7835 7836 return reset_code; 7837} 7838 7839/** 7840 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 7841 * 7842 * @bp: driver handle 7843 */ 7844void bnx2x_send_unload_done(struct bnx2x *bp) 7845{ 7846 /* Report UNLOAD_DONE to MCP */ 7847 if (!BP_NOMCP(bp)) 7848 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 7849} 7850 7851static inline int bnx2x_func_wait_started(struct bnx2x *bp) 7852{ 7853 int tout = 50; 7854 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 7855 7856 if (!bp->port.pmf) 7857 return 0; 7858 7859 /* 7860 * (assumption: No Attention from MCP at this stage) 7861 * PMF probably in the middle of TXdisable/enable transaction 7862 * 1. Sync IRS for default SB 7863 * 2. Sync SP queue - this guarantes us that attention handling started 7864 * 3. Wait, that TXdisable/enable transaction completes 7865 * 7866 * 1+2 guranty that if DCBx attention was scheduled it already changed 7867 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy 7868 * received complettion for the transaction the state is TX_STOPPED. 7869 * State will return to STARTED after completion of TX_STOPPED-->STARTED 7870 * transaction. 7871 */ 7872 7873 /* make sure default SB ISR is done */ 7874 if (msix) 7875 synchronize_irq(bp->msix_table[0].vector); 7876 else 7877 synchronize_irq(bp->pdev->irq); 7878 7879 flush_workqueue(bnx2x_wq); 7880 7881 while (bnx2x_func_get_state(bp, &bp->func_obj) != 7882 BNX2X_F_STATE_STARTED && tout--) 7883 msleep(20); 7884 7885 if (bnx2x_func_get_state(bp, &bp->func_obj) != 7886 BNX2X_F_STATE_STARTED) { 7887#ifdef BNX2X_STOP_ON_ERROR 7888 BNX2X_ERR("Wrong function state\n"); 7889 return -EBUSY; 7890#else 7891 /* 7892 * Failed to complete the transaction in a "good way" 7893 * Force both transactions with CLR bit 7894 */ 7895 struct bnx2x_func_state_params func_params = {NULL}; 7896 7897 DP(NETIF_MSG_IFDOWN, 7898 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n"); 7899 7900 func_params.f_obj = &bp->func_obj; 7901 __set_bit(RAMROD_DRV_CLR_ONLY, 7902 &func_params.ramrod_flags); 7903 7904 /* STARTED-->TX_ST0PPED */ 7905 func_params.cmd = BNX2X_F_CMD_TX_STOP; 7906 bnx2x_func_state_change(bp, &func_params); 7907 7908 /* TX_ST0PPED-->STARTED */ 7909 func_params.cmd = BNX2X_F_CMD_TX_START; 7910 return bnx2x_func_state_change(bp, &func_params); 7911#endif 7912 } 7913 7914 return 0; 7915} 7916 7917void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) 7918{ 7919 int port = BP_PORT(bp); 7920 int i, rc = 0; 7921 u8 cos; 7922 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 7923 u32 reset_code; 7924 7925 /* Wait until tx fastpath tasks complete */ 7926 for_each_tx_queue(bp, i) { 7927 struct bnx2x_fastpath *fp = &bp->fp[i]; 7928 7929 for_each_cos_in_tx_queue(fp, cos) 7930 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]); 7931#ifdef BNX2X_STOP_ON_ERROR 7932 if (rc) 7933 return; 7934#endif 7935 } 7936 7937 /* Give HW time to discard old tx messages */ 7938 usleep_range(1000, 1000); 7939 7940 /* Clean all ETH MACs */ 7941 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false); 7942 if (rc < 0) 7943 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); 7944 7945 /* Clean up UC list */ 7946 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, 7947 true); 7948 if (rc < 0) 7949 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", 7950 rc); 7951 7952 /* Disable LLH */ 7953 if (!CHIP_IS_E1(bp)) 7954 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 7955 7956 /* Set "drop all" (stop Rx). 7957 * We need to take a netif_addr_lock() here in order to prevent 7958 * a race between the completion code and this code. 7959 */ 7960 netif_addr_lock_bh(bp->dev); 7961 /* Schedule the rx_mode command */ 7962 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 7963 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 7964 else 7965 bnx2x_set_storm_rx_mode(bp); 7966 7967 /* Cleanup multicast configuration */ 7968 rparam.mcast_obj = &bp->mcast_obj; 7969 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 7970 if (rc < 0) 7971 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); 7972 7973 netif_addr_unlock_bh(bp->dev); 7974 7975 7976 7977 /* 7978 * Send the UNLOAD_REQUEST to the MCP. This will return if 7979 * this function should perform FUNC, PORT or COMMON HW 7980 * reset. 7981 */ 7982 reset_code = bnx2x_send_unload_req(bp, unload_mode); 7983 7984 /* 7985 * (assumption: No Attention from MCP at this stage) 7986 * PMF probably in the middle of TXdisable/enable transaction 7987 */ 7988 rc = bnx2x_func_wait_started(bp); 7989 if (rc) { 7990 BNX2X_ERR("bnx2x_func_wait_started failed\n"); 7991#ifdef BNX2X_STOP_ON_ERROR 7992 return; 7993#endif 7994 } 7995 7996 /* Close multi and leading connections 7997 * Completions for ramrods are collected in a synchronous way 7998 */ 7999 for_each_queue(bp, i) 8000 if (bnx2x_stop_queue(bp, i)) 8001#ifdef BNX2X_STOP_ON_ERROR 8002 return; 8003#else 8004 goto unload_error; 8005#endif 8006 /* If SP settings didn't get completed so far - something 8007 * very wrong has happen. 8008 */ 8009 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) 8010 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); 8011 8012#ifndef BNX2X_STOP_ON_ERROR 8013unload_error: 8014#endif 8015 rc = bnx2x_func_stop(bp); 8016 if (rc) { 8017 BNX2X_ERR("Function stop failed!\n"); 8018#ifdef BNX2X_STOP_ON_ERROR 8019 return; 8020#endif 8021 } 8022 8023 /* Disable HW interrupts, NAPI */ 8024 bnx2x_netif_stop(bp, 1); 8025 8026 /* Release IRQs */ 8027 bnx2x_free_irq(bp); 8028 8029 /* Reset the chip */ 8030 rc = bnx2x_reset_hw(bp, reset_code); 8031 if (rc) 8032 BNX2X_ERR("HW_RESET failed\n"); 8033 8034 8035 /* Report UNLOAD_DONE to MCP */ 8036 bnx2x_send_unload_done(bp); 8037} 8038 8039void bnx2x_disable_close_the_gate(struct bnx2x *bp) 8040{ 8041 u32 val; 8042 8043 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); 8044 8045 if (CHIP_IS_E1(bp)) { 8046 int port = BP_PORT(bp); 8047 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8048 MISC_REG_AEU_MASK_ATTN_FUNC_0; 8049 8050 val = REG_RD(bp, addr); 8051 val &= ~(0x300); 8052 REG_WR(bp, addr, val); 8053 } else { 8054 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); 8055 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 8056 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 8057 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); 8058 } 8059} 8060 8061/* Close gates #2, #3 and #4: */ 8062static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 8063{ 8064 u32 val; 8065 8066 /* Gates #2 and #4a are closed/opened for "not E1" only */ 8067 if (!CHIP_IS_E1(bp)) { 8068 /* #4 */ 8069 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 8070 /* #2 */ 8071 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 8072 } 8073 8074 /* #3 */ 8075 if (CHIP_IS_E1x(bp)) { 8076 /* Prevent interrupts from HC on both ports */ 8077 val = REG_RD(bp, HC_REG_CONFIG_1); 8078 REG_WR(bp, HC_REG_CONFIG_1, 8079 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 8080 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 8081 8082 val = REG_RD(bp, HC_REG_CONFIG_0); 8083 REG_WR(bp, HC_REG_CONFIG_0, 8084 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 8085 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 8086 } else { 8087 /* Prevent incomming interrupts in IGU */ 8088 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 8089 8090 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, 8091 (!close) ? 8092 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 8093 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 8094 } 8095 8096 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", 8097 close ? "closing" : "opening"); 8098 mmiowb(); 8099} 8100 8101#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ 8102 8103static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) 8104{ 8105 /* Do some magic... */ 8106 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8107 *magic_val = val & SHARED_MF_CLP_MAGIC; 8108 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 8109} 8110 8111/** 8112 * bnx2x_clp_reset_done - restore the value of the `magic' bit. 8113 * 8114 * @bp: driver handle 8115 * @magic_val: old value of the `magic' bit. 8116 */ 8117static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 8118{ 8119 /* Restore the `magic' bit value... */ 8120 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8121 MF_CFG_WR(bp, shared_mf_config.clp_mb, 8122 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 8123} 8124 8125/** 8126 * bnx2x_reset_mcp_prep - prepare for MCP reset. 8127 * 8128 * @bp: driver handle 8129 * @magic_val: old value of 'magic' bit. 8130 * 8131 * Takes care of CLP configurations. 8132 */ 8133static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 8134{ 8135 u32 shmem; 8136 u32 validity_offset; 8137 8138 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); 8139 8140 /* Set `magic' bit in order to save MF config */ 8141 if (!CHIP_IS_E1(bp)) 8142 bnx2x_clp_reset_prep(bp, magic_val); 8143 8144 /* Get shmem offset */ 8145 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8146 validity_offset = offsetof(struct shmem_region, validity_map[0]); 8147 8148 /* Clear validity map flags */ 8149 if (shmem > 0) 8150 REG_WR(bp, shmem + validity_offset, 0); 8151} 8152 8153#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 8154#define MCP_ONE_TIMEOUT 100 /* 100 ms */ 8155 8156/** 8157 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT 8158 * 8159 * @bp: driver handle 8160 */ 8161static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) 8162{ 8163 /* special handling for emulation and FPGA, 8164 wait 10 times longer */ 8165 if (CHIP_REV_IS_SLOW(bp)) 8166 msleep(MCP_ONE_TIMEOUT*10); 8167 else 8168 msleep(MCP_ONE_TIMEOUT); 8169} 8170 8171/* 8172 * initializes bp->common.shmem_base and waits for validity signature to appear 8173 */ 8174static int bnx2x_init_shmem(struct bnx2x *bp) 8175{ 8176 int cnt = 0; 8177 u32 val = 0; 8178 8179 do { 8180 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8181 if (bp->common.shmem_base) { 8182 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 8183 if (val & SHR_MEM_VALIDITY_MB) 8184 return 0; 8185 } 8186 8187 bnx2x_mcp_wait_one(bp); 8188 8189 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 8190 8191 BNX2X_ERR("BAD MCP validity signature\n"); 8192 8193 return -ENODEV; 8194} 8195 8196static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 8197{ 8198 int rc = bnx2x_init_shmem(bp); 8199 8200 /* Restore the `magic' bit value */ 8201 if (!CHIP_IS_E1(bp)) 8202 bnx2x_clp_reset_done(bp, magic_val); 8203 8204 return rc; 8205} 8206 8207static void bnx2x_pxp_prep(struct bnx2x *bp) 8208{ 8209 if (!CHIP_IS_E1(bp)) { 8210 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 8211 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 8212 mmiowb(); 8213 } 8214} 8215 8216/* 8217 * Reset the whole chip except for: 8218 * - PCIE core 8219 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by 8220 * one reset bit) 8221 * - IGU 8222 * - MISC (including AEU) 8223 * - GRC 8224 * - RBCN, RBCP 8225 */ 8226static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) 8227{ 8228 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 8229 u32 global_bits2, stay_reset2; 8230 8231 /* 8232 * Bits that have to be set in reset_mask2 if we want to reset 'global' 8233 * (per chip) blocks. 8234 */ 8235 global_bits2 = 8236 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 8237 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 8238 8239 /* Don't reset the following blocks */ 8240 not_reset_mask1 = 8241 MISC_REGISTERS_RESET_REG_1_RST_HC | 8242 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 8243 MISC_REGISTERS_RESET_REG_1_RST_PXP; 8244 8245 not_reset_mask2 = 8246 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 8247 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 8248 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 8249 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 8250 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 8251 MISC_REGISTERS_RESET_REG_2_RST_GRC | 8252 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 8253 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 8254 MISC_REGISTERS_RESET_REG_2_RST_ATC | 8255 MISC_REGISTERS_RESET_REG_2_PGLC; 8256 8257 /* 8258 * Keep the following blocks in reset: 8259 * - all xxMACs are handled by the bnx2x_link code. 8260 */ 8261 stay_reset2 = 8262 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 8263 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 8264 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 8265 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 8266 MISC_REGISTERS_RESET_REG_2_UMAC0 | 8267 MISC_REGISTERS_RESET_REG_2_UMAC1 | 8268 MISC_REGISTERS_RESET_REG_2_XMAC | 8269 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 8270 8271 /* Full reset masks according to the chip */ 8272 reset_mask1 = 0xffffffff; 8273 8274 if (CHIP_IS_E1(bp)) 8275 reset_mask2 = 0xffff; 8276 else if (CHIP_IS_E1H(bp)) 8277 reset_mask2 = 0x1ffff; 8278 else if (CHIP_IS_E2(bp)) 8279 reset_mask2 = 0xfffff; 8280 else /* CHIP_IS_E3 */ 8281 reset_mask2 = 0x3ffffff; 8282 8283 /* Don't reset global blocks unless we need to */ 8284 if (!global) 8285 reset_mask2 &= ~global_bits2; 8286 8287 /* 8288 * In case of attention in the QM, we need to reset PXP 8289 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 8290 * because otherwise QM reset would release 'close the gates' shortly 8291 * before resetting the PXP, then the PSWRQ would send a write 8292 * request to PGLUE. Then when PXP is reset, PGLUE would try to 8293 * read the payload data from PSWWR, but PSWWR would not 8294 * respond. The write queue in PGLUE would stuck, dmae commands 8295 * would not return. Therefore it's important to reset the second 8296 * reset register (containing the 8297 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 8298 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 8299 * bit). 8300 */ 8301 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8302 reset_mask2 & (~not_reset_mask2)); 8303 8304 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8305 reset_mask1 & (~not_reset_mask1)); 8306 8307 barrier(); 8308 mmiowb(); 8309 8310 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 8311 reset_mask2 & (~stay_reset2)); 8312 8313 barrier(); 8314 mmiowb(); 8315 8316 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 8317 mmiowb(); 8318} 8319 8320/** 8321 * bnx2x_er_poll_igu_vq - poll for pending writes bit. 8322 * It should get cleared in no more than 1s. 8323 * 8324 * @bp: driver handle 8325 * 8326 * It should get cleared in no more than 1s. Returns 0 if 8327 * pending writes bit gets cleared. 8328 */ 8329static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) 8330{ 8331 u32 cnt = 1000; 8332 u32 pend_bits = 0; 8333 8334 do { 8335 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); 8336 8337 if (pend_bits == 0) 8338 break; 8339 8340 usleep_range(1000, 1000); 8341 } while (cnt-- > 0); 8342 8343 if (cnt <= 0) { 8344 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", 8345 pend_bits); 8346 return -EBUSY; 8347 } 8348 8349 return 0; 8350} 8351 8352static int bnx2x_process_kill(struct bnx2x *bp, bool global) 8353{ 8354 int cnt = 1000; 8355 u32 val = 0; 8356 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 8357 8358 8359 /* Empty the Tetris buffer, wait for 1s */ 8360 do { 8361 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); 8362 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); 8363 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); 8364 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); 8365 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); 8366 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 8367 ((port_is_idle_0 & 0x1) == 0x1) && 8368 ((port_is_idle_1 & 0x1) == 0x1) && 8369 (pgl_exp_rom2 == 0xffffffff)) 8370 break; 8371 usleep_range(1000, 1000); 8372 } while (cnt-- > 0); 8373 8374 if (cnt <= 0) { 8375 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); 8376 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 8377 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 8378 pgl_exp_rom2); 8379 return -EAGAIN; 8380 } 8381 8382 barrier(); 8383 8384 /* Close gates #2, #3 and #4 */ 8385 bnx2x_set_234_gates(bp, true); 8386 8387 /* Poll for IGU VQs for 57712 and newer chips */ 8388 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) 8389 return -EAGAIN; 8390 8391 8392 /* TBD: Indicate that "process kill" is in progress to MCP */ 8393 8394 /* Clear "unprepared" bit */ 8395 REG_WR(bp, MISC_REG_UNPREPARED, 0); 8396 barrier(); 8397 8398 /* Make sure all is written to the chip before the reset */ 8399 mmiowb(); 8400 8401 /* Wait for 1ms to empty GLUE and PCI-E core queues, 8402 * PSWHST, GRC and PSWRD Tetris buffer. 8403 */ 8404 usleep_range(1000, 1000); 8405 8406 /* Prepare to chip reset: */ 8407 /* MCP */ 8408 if (global) 8409 bnx2x_reset_mcp_prep(bp, &val); 8410 8411 /* PXP */ 8412 bnx2x_pxp_prep(bp); 8413 barrier(); 8414 8415 /* reset the chip */ 8416 bnx2x_process_kill_chip_reset(bp, global); 8417 barrier(); 8418 8419 /* Recover after reset: */ 8420 /* MCP */ 8421 if (global && bnx2x_reset_mcp_comp(bp, val)) 8422 return -EAGAIN; 8423 8424 /* TBD: Add resetting the NO_MCP mode DB here */ 8425 8426 /* PXP */ 8427 bnx2x_pxp_prep(bp); 8428 8429 /* Open the gates #2, #3 and #4 */ 8430 bnx2x_set_234_gates(bp, false); 8431 8432 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a 8433 * reset state, re-enable attentions. */ 8434 8435 return 0; 8436} 8437 8438int bnx2x_leader_reset(struct bnx2x *bp) 8439{ 8440 int rc = 0; 8441 bool global = bnx2x_reset_is_global(bp); 8442 u32 load_code; 8443 8444 /* if not going to reset MCP - load "fake" driver to reset HW while 8445 * driver is owner of the HW 8446 */ 8447 if (!global && !BP_NOMCP(bp)) { 8448 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 0); 8449 if (!load_code) { 8450 BNX2X_ERR("MCP response failure, aborting\n"); 8451 rc = -EAGAIN; 8452 goto exit_leader_reset; 8453 } 8454 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && 8455 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { 8456 BNX2X_ERR("MCP unexpected resp, aborting\n"); 8457 rc = -EAGAIN; 8458 goto exit_leader_reset2; 8459 } 8460 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); 8461 if (!load_code) { 8462 BNX2X_ERR("MCP response failure, aborting\n"); 8463 rc = -EAGAIN; 8464 goto exit_leader_reset2; 8465 } 8466 } 8467 8468 /* Try to recover after the failure */ 8469 if (bnx2x_process_kill(bp, global)) { 8470 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", 8471 BP_PATH(bp)); 8472 rc = -EAGAIN; 8473 goto exit_leader_reset2; 8474 } 8475 8476 /* 8477 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver 8478 * state. 8479 */ 8480 bnx2x_set_reset_done(bp); 8481 if (global) 8482 bnx2x_clear_reset_global(bp); 8483 8484exit_leader_reset2: 8485 /* unload "fake driver" if it was loaded */ 8486 if (!global && !BP_NOMCP(bp)) { 8487 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); 8488 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 8489 } 8490exit_leader_reset: 8491 bp->is_leader = 0; 8492 bnx2x_release_leader_lock(bp); 8493 smp_mb(); 8494 return rc; 8495} 8496 8497static inline void bnx2x_recovery_failed(struct bnx2x *bp) 8498{ 8499 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); 8500 8501 /* Disconnect this device */ 8502 netif_device_detach(bp->dev); 8503 8504 /* 8505 * Block ifup for all function on this engine until "process kill" 8506 * or power cycle. 8507 */ 8508 bnx2x_set_reset_in_progress(bp); 8509 8510 /* Shut down the power */ 8511 bnx2x_set_power_state(bp, PCI_D3hot); 8512 8513 bp->recovery_state = BNX2X_RECOVERY_FAILED; 8514 8515 smp_mb(); 8516} 8517 8518/* 8519 * Assumption: runs under rtnl lock. This together with the fact 8520 * that it's called only from bnx2x_sp_rtnl() ensure that it 8521 * will never be called when netif_running(bp->dev) is false. 8522 */ 8523static void bnx2x_parity_recover(struct bnx2x *bp) 8524{ 8525 bool global = false; 8526 u32 error_recovered, error_unrecovered; 8527 bool is_parity; 8528 8529 DP(NETIF_MSG_HW, "Handling parity\n"); 8530 while (1) { 8531 switch (bp->recovery_state) { 8532 case BNX2X_RECOVERY_INIT: 8533 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 8534 is_parity = bnx2x_chk_parity_attn(bp, &global, false); 8535 WARN_ON(!is_parity); 8536 8537 /* Try to get a LEADER_LOCK HW lock */ 8538 if (bnx2x_trylock_leader_lock(bp)) { 8539 bnx2x_set_reset_in_progress(bp); 8540 /* 8541 * Check if there is a global attention and if 8542 * there was a global attention, set the global 8543 * reset bit. 8544 */ 8545 8546 if (global) 8547 bnx2x_set_reset_global(bp); 8548 8549 bp->is_leader = 1; 8550 } 8551 8552 /* Stop the driver */ 8553 /* If interface has been removed - break */ 8554 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) 8555 return; 8556 8557 bp->recovery_state = BNX2X_RECOVERY_WAIT; 8558 8559 /* Ensure "is_leader", MCP command sequence and 8560 * "recovery_state" update values are seen on other 8561 * CPUs. 8562 */ 8563 smp_mb(); 8564 break; 8565 8566 case BNX2X_RECOVERY_WAIT: 8567 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 8568 if (bp->is_leader) { 8569 int other_engine = BP_PATH(bp) ? 0 : 1; 8570 bool other_load_status = 8571 bnx2x_get_load_status(bp, other_engine); 8572 bool load_status = 8573 bnx2x_get_load_status(bp, BP_PATH(bp)); 8574 global = bnx2x_reset_is_global(bp); 8575 8576 /* 8577 * In case of a parity in a global block, let 8578 * the first leader that performs a 8579 * leader_reset() reset the global blocks in 8580 * order to clear global attentions. Otherwise 8581 * the the gates will remain closed for that 8582 * engine. 8583 */ 8584 if (load_status || 8585 (global && other_load_status)) { 8586 /* Wait until all other functions get 8587 * down. 8588 */ 8589 schedule_delayed_work(&bp->sp_rtnl_task, 8590 HZ/10); 8591 return; 8592 } else { 8593 /* If all other functions got down - 8594 * try to bring the chip back to 8595 * normal. In any case it's an exit 8596 * point for a leader. 8597 */ 8598 if (bnx2x_leader_reset(bp)) { 8599 bnx2x_recovery_failed(bp); 8600 return; 8601 } 8602 8603 /* If we are here, means that the 8604 * leader has succeeded and doesn't 8605 * want to be a leader any more. Try 8606 * to continue as a none-leader. 8607 */ 8608 break; 8609 } 8610 } else { /* non-leader */ 8611 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { 8612 /* Try to get a LEADER_LOCK HW lock as 8613 * long as a former leader may have 8614 * been unloaded by the user or 8615 * released a leadership by another 8616 * reason. 8617 */ 8618 if (bnx2x_trylock_leader_lock(bp)) { 8619 /* I'm a leader now! Restart a 8620 * switch case. 8621 */ 8622 bp->is_leader = 1; 8623 break; 8624 } 8625 8626 schedule_delayed_work(&bp->sp_rtnl_task, 8627 HZ/10); 8628 return; 8629 8630 } else { 8631 /* 8632 * If there was a global attention, wait 8633 * for it to be cleared. 8634 */ 8635 if (bnx2x_reset_is_global(bp)) { 8636 schedule_delayed_work( 8637 &bp->sp_rtnl_task, 8638 HZ/10); 8639 return; 8640 } 8641 8642 error_recovered = 8643 bp->eth_stats.recoverable_error; 8644 error_unrecovered = 8645 bp->eth_stats.unrecoverable_error; 8646 bp->recovery_state = 8647 BNX2X_RECOVERY_NIC_LOADING; 8648 if (bnx2x_nic_load(bp, LOAD_NORMAL)) { 8649 error_unrecovered++; 8650 netdev_err(bp->dev, 8651 "Recovery failed. Power cycle needed\n"); 8652 /* Disconnect this device */ 8653 netif_device_detach(bp->dev); 8654 /* Shut down the power */ 8655 bnx2x_set_power_state( 8656 bp, PCI_D3hot); 8657 smp_mb(); 8658 } else { 8659 bp->recovery_state = 8660 BNX2X_RECOVERY_DONE; 8661 error_recovered++; 8662 smp_mb(); 8663 } 8664 bp->eth_stats.recoverable_error = 8665 error_recovered; 8666 bp->eth_stats.unrecoverable_error = 8667 error_unrecovered; 8668 8669 return; 8670 } 8671 } 8672 default: 8673 return; 8674 } 8675 } 8676} 8677 8678static int bnx2x_close(struct net_device *dev); 8679 8680/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is 8681 * scheduled on a general queue in order to prevent a dead lock. 8682 */ 8683static void bnx2x_sp_rtnl_task(struct work_struct *work) 8684{ 8685 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); 8686 8687 rtnl_lock(); 8688 8689 if (!netif_running(bp->dev)) 8690 goto sp_rtnl_exit; 8691 8692 /* if stop on error is defined no recovery flows should be executed */ 8693#ifdef BNX2X_STOP_ON_ERROR 8694 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" 8695 "you will need to reboot when done\n"); 8696 goto sp_rtnl_not_reset; 8697#endif 8698 8699 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { 8700 /* 8701 * Clear all pending SP commands as we are going to reset the 8702 * function anyway. 8703 */ 8704 bp->sp_rtnl_state = 0; 8705 smp_mb(); 8706 8707 bnx2x_parity_recover(bp); 8708 8709 goto sp_rtnl_exit; 8710 } 8711 8712 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { 8713 /* 8714 * Clear all pending SP commands as we are going to reset the 8715 * function anyway. 8716 */ 8717 bp->sp_rtnl_state = 0; 8718 smp_mb(); 8719 8720 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 8721 bnx2x_nic_load(bp, LOAD_NORMAL); 8722 8723 goto sp_rtnl_exit; 8724 } 8725#ifdef BNX2X_STOP_ON_ERROR 8726sp_rtnl_not_reset: 8727#endif 8728 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) 8729 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); 8730 8731 /* 8732 * in case of fan failure we need to reset id if the "stop on error" 8733 * debug flag is set, since we trying to prevent permanent overheating 8734 * damage 8735 */ 8736 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { 8737 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); 8738 netif_device_detach(bp->dev); 8739 bnx2x_close(bp->dev); 8740 } 8741 8742sp_rtnl_exit: 8743 rtnl_unlock(); 8744} 8745 8746/* end of nic load/unload */ 8747 8748static void bnx2x_period_task(struct work_struct *work) 8749{ 8750 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); 8751 8752 if (!netif_running(bp->dev)) 8753 goto period_task_exit; 8754 8755 if (CHIP_REV_IS_SLOW(bp)) { 8756 BNX2X_ERR("period task called on emulation, ignoring\n"); 8757 goto period_task_exit; 8758 } 8759 8760 bnx2x_acquire_phy_lock(bp); 8761 /* 8762 * The barrier is needed to ensure the ordering between the writing to 8763 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and 8764 * the reading here. 8765 */ 8766 smp_mb(); 8767 if (bp->port.pmf) { 8768 bnx2x_period_func(&bp->link_params, &bp->link_vars); 8769 8770 /* Re-queue task in 1 sec */ 8771 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); 8772 } 8773 8774 bnx2x_release_phy_lock(bp); 8775period_task_exit: 8776 return; 8777} 8778 8779/* 8780 * Init service functions 8781 */ 8782 8783static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) 8784{ 8785 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; 8786 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; 8787 return base + (BP_ABS_FUNC(bp)) * stride; 8788} 8789 8790static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) 8791{ 8792 u32 reg = bnx2x_get_pretend_reg(bp); 8793 8794 /* Flush all outstanding writes */ 8795 mmiowb(); 8796 8797 /* Pretend to be function 0 */ 8798 REG_WR(bp, reg, 0); 8799 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ 8800 8801 /* From now we are in the "like-E1" mode */ 8802 bnx2x_int_disable(bp); 8803 8804 /* Flush all outstanding writes */ 8805 mmiowb(); 8806 8807 /* Restore the original function */ 8808 REG_WR(bp, reg, BP_ABS_FUNC(bp)); 8809 REG_RD(bp, reg); 8810} 8811 8812static inline void bnx2x_undi_int_disable(struct bnx2x *bp) 8813{ 8814 if (CHIP_IS_E1(bp)) 8815 bnx2x_int_disable(bp); 8816 else 8817 bnx2x_undi_int_disable_e1h(bp); 8818} 8819 8820static void __devinit bnx2x_prev_unload_close_mac(struct bnx2x *bp) 8821{ 8822 u32 val, base_addr, offset, mask, reset_reg; 8823 bool mac_stopped = false; 8824 u8 port = BP_PORT(bp); 8825 8826 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); 8827 8828 if (!CHIP_IS_E3(bp)) { 8829 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); 8830 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; 8831 if ((mask & reset_reg) && val) { 8832 u32 wb_data[2]; 8833 BNX2X_DEV_INFO("Disable bmac Rx\n"); 8834 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM 8835 : NIG_REG_INGRESS_BMAC0_MEM; 8836 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL 8837 : BIGMAC_REGISTER_BMAC_CONTROL; 8838 8839 /* 8840 * use rd/wr since we cannot use dmae. This is safe 8841 * since MCP won't access the bus due to the request 8842 * to unload, and no function on the path can be 8843 * loaded at this time. 8844 */ 8845 wb_data[0] = REG_RD(bp, base_addr + offset); 8846 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); 8847 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; 8848 REG_WR(bp, base_addr + offset, wb_data[0]); 8849 REG_WR(bp, base_addr + offset + 0x4, wb_data[1]); 8850 8851 } 8852 BNX2X_DEV_INFO("Disable emac Rx\n"); 8853 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0); 8854 8855 mac_stopped = true; 8856 } else { 8857 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { 8858 BNX2X_DEV_INFO("Disable xmac Rx\n"); 8859 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 8860 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); 8861 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, 8862 val & ~(1 << 1)); 8863 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, 8864 val | (1 << 1)); 8865 REG_WR(bp, base_addr + XMAC_REG_CTRL, 0); 8866 mac_stopped = true; 8867 } 8868 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; 8869 if (mask & reset_reg) { 8870 BNX2X_DEV_INFO("Disable umac Rx\n"); 8871 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 8872 REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0); 8873 mac_stopped = true; 8874 } 8875 } 8876 8877 if (mac_stopped) 8878 msleep(20); 8879 8880} 8881 8882#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) 8883#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) 8884#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) 8885#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) 8886 8887static void __devinit bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, 8888 u8 inc) 8889{ 8890 u16 rcq, bd; 8891 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port)); 8892 8893 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; 8894 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; 8895 8896 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); 8897 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg); 8898 8899 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n", 8900 port, bd, rcq); 8901} 8902 8903static int __devinit bnx2x_prev_mcp_done(struct bnx2x *bp) 8904{ 8905 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 8906 if (!rc) { 8907 BNX2X_ERR("MCP response failure, aborting\n"); 8908 return -EBUSY; 8909 } 8910 8911 return 0; 8912} 8913 8914static bool __devinit bnx2x_prev_is_path_marked(struct bnx2x *bp) 8915{ 8916 struct bnx2x_prev_path_list *tmp_list; 8917 int rc = false; 8918 8919 if (down_trylock(&bnx2x_prev_sem)) 8920 return false; 8921 8922 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) { 8923 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && 8924 bp->pdev->bus->number == tmp_list->bus && 8925 BP_PATH(bp) == tmp_list->path) { 8926 rc = true; 8927 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", 8928 BP_PATH(bp)); 8929 break; 8930 } 8931 } 8932 8933 up(&bnx2x_prev_sem); 8934 8935 return rc; 8936} 8937 8938static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp) 8939{ 8940 struct bnx2x_prev_path_list *tmp_list; 8941 int rc; 8942 8943 tmp_list = (struct bnx2x_prev_path_list *) 8944 kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); 8945 if (!tmp_list) { 8946 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); 8947 return -ENOMEM; 8948 } 8949 8950 tmp_list->bus = bp->pdev->bus->number; 8951 tmp_list->slot = PCI_SLOT(bp->pdev->devfn); 8952 tmp_list->path = BP_PATH(bp); 8953 8954 rc = down_interruptible(&bnx2x_prev_sem); 8955 if (rc) { 8956 BNX2X_ERR("Received %d when tried to take lock\n", rc); 8957 kfree(tmp_list); 8958 } else { 8959 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n", 8960 BP_PATH(bp)); 8961 list_add(&tmp_list->list, &bnx2x_prev_list); 8962 up(&bnx2x_prev_sem); 8963 } 8964 8965 return rc; 8966} 8967 8968static bool __devinit bnx2x_can_flr(struct bnx2x *bp) 8969{ 8970 int pos; 8971 u32 cap; 8972 struct pci_dev *dev = bp->pdev; 8973 8974 pos = pci_pcie_cap(dev); 8975 if (!pos) 8976 return false; 8977 8978 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap); 8979 if (!(cap & PCI_EXP_DEVCAP_FLR)) 8980 return false; 8981 8982 return true; 8983} 8984 8985static int __devinit bnx2x_do_flr(struct bnx2x *bp) 8986{ 8987 int i, pos; 8988 u16 status; 8989 struct pci_dev *dev = bp->pdev; 8990 8991 /* probe the capability first */ 8992 if (bnx2x_can_flr(bp)) 8993 return -ENOTTY; 8994 8995 pos = pci_pcie_cap(dev); 8996 if (!pos) 8997 return -ENOTTY; 8998 8999 /* Wait for Transaction Pending bit clean */ 9000 for (i = 0; i < 4; i++) { 9001 if (i) 9002 msleep((1 << (i - 1)) * 100); 9003 9004 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 9005 if (!(status & PCI_EXP_DEVSTA_TRPND)) 9006 goto clear; 9007 } 9008 9009 dev_err(&dev->dev, 9010 "transaction is not cleared; proceeding with reset anyway\n"); 9011 9012clear: 9013 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { 9014 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", 9015 bp->common.bc_ver); 9016 return -EINVAL; 9017 } 9018 9019 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); 9020 9021 return 0; 9022} 9023 9024static int __devinit bnx2x_prev_unload_uncommon(struct bnx2x *bp) 9025{ 9026 int rc; 9027 9028 BNX2X_DEV_INFO("Uncommon unload Flow\n"); 9029 9030 /* Test if previous unload process was already finished for this path */ 9031 if (bnx2x_prev_is_path_marked(bp)) 9032 return bnx2x_prev_mcp_done(bp); 9033 9034 /* If function has FLR capabilities, and existing FW version matches 9035 * the one required, then FLR will be sufficient to clean any residue 9036 * left by previous driver 9037 */ 9038 if (bnx2x_test_firmware_version(bp, false) && bnx2x_can_flr(bp)) 9039 return bnx2x_do_flr(bp); 9040 9041 /* Close the MCP request, return failure*/ 9042 rc = bnx2x_prev_mcp_done(bp); 9043 if (!rc) 9044 rc = BNX2X_PREV_WAIT_NEEDED; 9045 9046 return rc; 9047} 9048 9049static int __devinit bnx2x_prev_unload_common(struct bnx2x *bp) 9050{ 9051 u32 reset_reg, tmp_reg = 0, rc; 9052 /* It is possible a previous function received 'common' answer, 9053 * but hasn't loaded yet, therefore creating a scenario of 9054 * multiple functions receiving 'common' on the same path. 9055 */ 9056 BNX2X_DEV_INFO("Common unload Flow\n"); 9057 9058 if (bnx2x_prev_is_path_marked(bp)) 9059 return bnx2x_prev_mcp_done(bp); 9060 9061 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); 9062 9063 /* Reset should be performed after BRB is emptied */ 9064 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { 9065 u32 timer_count = 1000; 9066 bool prev_undi = false; 9067 9068 /* Close the MAC Rx to prevent BRB from filling up */ 9069 bnx2x_prev_unload_close_mac(bp); 9070 9071 /* Check if the UNDI driver was previously loaded 9072 * UNDI driver initializes CID offset for normal bell to 0x7 9073 */ 9074 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); 9075 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { 9076 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 9077 if (tmp_reg == 0x7) { 9078 BNX2X_DEV_INFO("UNDI previously loaded\n"); 9079 prev_undi = true; 9080 /* clear the UNDI indication */ 9081 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 9082 } 9083 } 9084 /* wait until BRB is empty */ 9085 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); 9086 while (timer_count) { 9087 u32 prev_brb = tmp_reg; 9088 9089 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); 9090 if (!tmp_reg) 9091 break; 9092 9093 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); 9094 9095 /* reset timer as long as BRB actually gets emptied */ 9096 if (prev_brb > tmp_reg) 9097 timer_count = 1000; 9098 else 9099 timer_count--; 9100 9101 /* If UNDI resides in memory, manually increment it */ 9102 if (prev_undi) 9103 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1); 9104 9105 udelay(10); 9106 } 9107 9108 if (!timer_count) 9109 BNX2X_ERR("Failed to empty BRB, hope for the best\n"); 9110 9111 } 9112 9113 /* No packets are in the pipeline, path is ready for reset */ 9114 bnx2x_reset_common(bp); 9115 9116 rc = bnx2x_prev_mark_path(bp); 9117 if (rc) { 9118 bnx2x_prev_mcp_done(bp); 9119 return rc; 9120 } 9121 9122 return bnx2x_prev_mcp_done(bp); 9123} 9124 9125static int __devinit bnx2x_prev_unload(struct bnx2x *bp) 9126{ 9127 int time_counter = 10; 9128 u32 rc, fw, hw_lock_reg, hw_lock_val; 9129 BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); 9130 9131 /* Release previously held locks */ 9132 hw_lock_reg = (BP_FUNC(bp) <= 5) ? 9133 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : 9134 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); 9135 9136 hw_lock_val = (REG_RD(bp, hw_lock_reg)); 9137 if (hw_lock_val) { 9138 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { 9139 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); 9140 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 9141 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); 9142 } 9143 9144 BNX2X_DEV_INFO("Release Previously held hw lock\n"); 9145 REG_WR(bp, hw_lock_reg, 0xffffffff); 9146 } else 9147 BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); 9148 9149 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { 9150 BNX2X_DEV_INFO("Release previously held alr\n"); 9151 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); 9152 } 9153 9154 9155 do { 9156 /* Lock MCP using an unload request */ 9157 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); 9158 if (!fw) { 9159 BNX2X_ERR("MCP response failure, aborting\n"); 9160 rc = -EBUSY; 9161 break; 9162 } 9163 9164 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) { 9165 rc = bnx2x_prev_unload_common(bp); 9166 break; 9167 } 9168 9169 /* non-common reply from MCP night require looping */ 9170 rc = bnx2x_prev_unload_uncommon(bp); 9171 if (rc != BNX2X_PREV_WAIT_NEEDED) 9172 break; 9173 9174 msleep(20); 9175 } while (--time_counter); 9176 9177 if (!time_counter || rc) { 9178 BNX2X_ERR("Failed unloading previous driver, aborting\n"); 9179 rc = -EBUSY; 9180 } 9181 9182 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); 9183 9184 return rc; 9185} 9186 9187static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) 9188{ 9189 u32 val, val2, val3, val4, id, boot_mode; 9190 u16 pmc; 9191 9192 /* Get the chip revision id and number. */ 9193 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 9194 val = REG_RD(bp, MISC_REG_CHIP_NUM); 9195 id = ((val & 0xffff) << 16); 9196 val = REG_RD(bp, MISC_REG_CHIP_REV); 9197 id |= ((val & 0xf) << 12); 9198 val = REG_RD(bp, MISC_REG_CHIP_METAL); 9199 id |= ((val & 0xff) << 4); 9200 val = REG_RD(bp, MISC_REG_BOND_ID); 9201 id |= (val & 0xf); 9202 bp->common.chip_id = id; 9203 9204 /* Set doorbell size */ 9205 bp->db_size = (1 << BNX2X_DB_SHIFT); 9206 9207 if (!CHIP_IS_E1x(bp)) { 9208 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 9209 if ((val & 1) == 0) 9210 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); 9211 else 9212 val = (val >> 1) & 1; 9213 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : 9214 "2_PORT_MODE"); 9215 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : 9216 CHIP_2_PORT_MODE; 9217 9218 if (CHIP_MODE_IS_4_PORT(bp)) 9219 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ 9220 else 9221 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ 9222 } else { 9223 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ 9224 bp->pfid = bp->pf_num; /* 0..7 */ 9225 } 9226 9227 BNX2X_DEV_INFO("pf_id: %x", bp->pfid); 9228 9229 bp->link_params.chip_id = bp->common.chip_id; 9230 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 9231 9232 val = (REG_RD(bp, 0x2874) & 0x55); 9233 if ((bp->common.chip_id & 0x1) || 9234 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { 9235 bp->flags |= ONE_PORT_FLAG; 9236 BNX2X_DEV_INFO("single port device\n"); 9237 } 9238 9239 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); 9240 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << 9241 (val & MCPR_NVM_CFG4_FLASH_SIZE)); 9242 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 9243 bp->common.flash_size, bp->common.flash_size); 9244 9245 bnx2x_init_shmem(bp); 9246 9247 9248 9249 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? 9250 MISC_REG_GENERIC_CR_1 : 9251 MISC_REG_GENERIC_CR_0)); 9252 9253 bp->link_params.shmem_base = bp->common.shmem_base; 9254 bp->link_params.shmem2_base = bp->common.shmem2_base; 9255 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 9256 bp->common.shmem_base, bp->common.shmem2_base); 9257 9258 if (!bp->common.shmem_base) { 9259 BNX2X_DEV_INFO("MCP not active\n"); 9260 bp->flags |= NO_MCP_FLAG; 9261 return; 9262 } 9263 9264 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 9265 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 9266 9267 bp->link_params.hw_led_mode = ((bp->common.hw_config & 9268 SHARED_HW_CFG_LED_MODE_MASK) >> 9269 SHARED_HW_CFG_LED_MODE_SHIFT); 9270 9271 bp->link_params.feature_config_flags = 0; 9272 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); 9273 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) 9274 bp->link_params.feature_config_flags |= 9275 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 9276 else 9277 bp->link_params.feature_config_flags &= 9278 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 9279 9280 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 9281 bp->common.bc_ver = val; 9282 BNX2X_DEV_INFO("bc_ver %X\n", val); 9283 if (val < BNX2X_BC_VER) { 9284 /* for now only warn 9285 * later we might need to enforce this */ 9286 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", 9287 BNX2X_BC_VER, val); 9288 } 9289 bp->link_params.feature_config_flags |= 9290 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 9291 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 9292 9293 bp->link_params.feature_config_flags |= 9294 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? 9295 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; 9296 9297 bp->link_params.feature_config_flags |= 9298 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? 9299 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; 9300 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? 9301 BC_SUPPORTS_PFC_STATS : 0; 9302 9303 boot_mode = SHMEM_RD(bp, 9304 dev_info.port_feature_config[BP_PORT(bp)].mba_config) & 9305 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; 9306 switch (boot_mode) { 9307 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: 9308 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; 9309 break; 9310 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: 9311 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; 9312 break; 9313 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: 9314 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; 9315 break; 9316 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: 9317 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; 9318 break; 9319 } 9320 9321 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); 9322 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; 9323 9324 BNX2X_DEV_INFO("%sWoL capable\n", 9325 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 9326 9327 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 9328 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 9329 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); 9330 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); 9331 9332 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", 9333 val, val2, val3, val4); 9334} 9335 9336#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 9337#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 9338 9339static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) 9340{ 9341 int pfid = BP_FUNC(bp); 9342 int igu_sb_id; 9343 u32 val; 9344 u8 fid, igu_sb_cnt = 0; 9345 9346 bp->igu_base_sb = 0xff; 9347 if (CHIP_INT_MODE_IS_BC(bp)) { 9348 int vn = BP_VN(bp); 9349 igu_sb_cnt = bp->igu_sb_cnt; 9350 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 9351 FP_SB_MAX_E1x; 9352 9353 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + 9354 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); 9355 9356 return; 9357 } 9358 9359 /* IGU in normal mode - read CAM */ 9360 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 9361 igu_sb_id++) { 9362 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 9363 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 9364 continue; 9365 fid = IGU_FID(val); 9366 if ((fid & IGU_FID_ENCODE_IS_PF)) { 9367 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) 9368 continue; 9369 if (IGU_VEC(val) == 0) 9370 /* default status block */ 9371 bp->igu_dsb_id = igu_sb_id; 9372 else { 9373 if (bp->igu_base_sb == 0xff) 9374 bp->igu_base_sb = igu_sb_id; 9375 igu_sb_cnt++; 9376 } 9377 } 9378 } 9379 9380#ifdef CONFIG_PCI_MSI 9381 /* 9382 * It's expected that number of CAM entries for this functions is equal 9383 * to the number evaluated based on the MSI-X table size. We want a 9384 * harsh warning if these values are different! 9385 */ 9386 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); 9387#endif 9388 9389 if (igu_sb_cnt == 0) 9390 BNX2X_ERR("CAM configuration error\n"); 9391} 9392 9393static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, 9394 u32 switch_cfg) 9395{ 9396 int cfg_size = 0, idx, port = BP_PORT(bp); 9397 9398 /* Aggregation of supported attributes of all external phys */ 9399 bp->port.supported[0] = 0; 9400 bp->port.supported[1] = 0; 9401 switch (bp->link_params.num_phys) { 9402 case 1: 9403 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; 9404 cfg_size = 1; 9405 break; 9406 case 2: 9407 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; 9408 cfg_size = 1; 9409 break; 9410 case 3: 9411 if (bp->link_params.multi_phy_config & 9412 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 9413 bp->port.supported[1] = 9414 bp->link_params.phy[EXT_PHY1].supported; 9415 bp->port.supported[0] = 9416 bp->link_params.phy[EXT_PHY2].supported; 9417 } else { 9418 bp->port.supported[0] = 9419 bp->link_params.phy[EXT_PHY1].supported; 9420 bp->port.supported[1] = 9421 bp->link_params.phy[EXT_PHY2].supported; 9422 } 9423 cfg_size = 2; 9424 break; 9425 } 9426 9427 if (!(bp->port.supported[0] || bp->port.supported[1])) { 9428 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", 9429 SHMEM_RD(bp, 9430 dev_info.port_hw_config[port].external_phy_config), 9431 SHMEM_RD(bp, 9432 dev_info.port_hw_config[port].external_phy_config2)); 9433 return; 9434 } 9435 9436 if (CHIP_IS_E3(bp)) 9437 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); 9438 else { 9439 switch (switch_cfg) { 9440 case SWITCH_CFG_1G: 9441 bp->port.phy_addr = REG_RD( 9442 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 9443 break; 9444 case SWITCH_CFG_10G: 9445 bp->port.phy_addr = REG_RD( 9446 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 9447 break; 9448 default: 9449 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 9450 bp->port.link_config[0]); 9451 return; 9452 } 9453 } 9454 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 9455 /* mask what we support according to speed_cap_mask per configuration */ 9456 for (idx = 0; idx < cfg_size; idx++) { 9457 if (!(bp->link_params.speed_cap_mask[idx] & 9458 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 9459 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; 9460 9461 if (!(bp->link_params.speed_cap_mask[idx] & 9462 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 9463 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; 9464 9465 if (!(bp->link_params.speed_cap_mask[idx] & 9466 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 9467 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; 9468 9469 if (!(bp->link_params.speed_cap_mask[idx] & 9470 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 9471 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; 9472 9473 if (!(bp->link_params.speed_cap_mask[idx] & 9474 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 9475 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | 9476 SUPPORTED_1000baseT_Full); 9477 9478 if (!(bp->link_params.speed_cap_mask[idx] & 9479 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 9480 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; 9481 9482 if (!(bp->link_params.speed_cap_mask[idx] & 9483 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 9484 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; 9485 9486 } 9487 9488 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], 9489 bp->port.supported[1]); 9490} 9491 9492static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) 9493{ 9494 u32 link_config, idx, cfg_size = 0; 9495 bp->port.advertising[0] = 0; 9496 bp->port.advertising[1] = 0; 9497 switch (bp->link_params.num_phys) { 9498 case 1: 9499 case 2: 9500 cfg_size = 1; 9501 break; 9502 case 3: 9503 cfg_size = 2; 9504 break; 9505 } 9506 for (idx = 0; idx < cfg_size; idx++) { 9507 bp->link_params.req_duplex[idx] = DUPLEX_FULL; 9508 link_config = bp->port.link_config[idx]; 9509 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 9510 case PORT_FEATURE_LINK_SPEED_AUTO: 9511 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { 9512 bp->link_params.req_line_speed[idx] = 9513 SPEED_AUTO_NEG; 9514 bp->port.advertising[idx] |= 9515 bp->port.supported[idx]; 9516 if (bp->link_params.phy[EXT_PHY1].type == 9517 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 9518 bp->port.advertising[idx] |= 9519 (SUPPORTED_100baseT_Half | 9520 SUPPORTED_100baseT_Full); 9521 } else { 9522 /* force 10G, no AN */ 9523 bp->link_params.req_line_speed[idx] = 9524 SPEED_10000; 9525 bp->port.advertising[idx] |= 9526 (ADVERTISED_10000baseT_Full | 9527 ADVERTISED_FIBRE); 9528 continue; 9529 } 9530 break; 9531 9532 case PORT_FEATURE_LINK_SPEED_10M_FULL: 9533 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { 9534 bp->link_params.req_line_speed[idx] = 9535 SPEED_10; 9536 bp->port.advertising[idx] |= 9537 (ADVERTISED_10baseT_Full | 9538 ADVERTISED_TP); 9539 } else { 9540 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 9541 link_config, 9542 bp->link_params.speed_cap_mask[idx]); 9543 return; 9544 } 9545 break; 9546 9547 case PORT_FEATURE_LINK_SPEED_10M_HALF: 9548 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { 9549 bp->link_params.req_line_speed[idx] = 9550 SPEED_10; 9551 bp->link_params.req_duplex[idx] = 9552 DUPLEX_HALF; 9553 bp->port.advertising[idx] |= 9554 (ADVERTISED_10baseT_Half | 9555 ADVERTISED_TP); 9556 } else { 9557 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 9558 link_config, 9559 bp->link_params.speed_cap_mask[idx]); 9560 return; 9561 } 9562 break; 9563 9564 case PORT_FEATURE_LINK_SPEED_100M_FULL: 9565 if (bp->port.supported[idx] & 9566 SUPPORTED_100baseT_Full) { 9567 bp->link_params.req_line_speed[idx] = 9568 SPEED_100; 9569 bp->port.advertising[idx] |= 9570 (ADVERTISED_100baseT_Full | 9571 ADVERTISED_TP); 9572 } else { 9573 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 9574 link_config, 9575 bp->link_params.speed_cap_mask[idx]); 9576 return; 9577 } 9578 break; 9579 9580 case PORT_FEATURE_LINK_SPEED_100M_HALF: 9581 if (bp->port.supported[idx] & 9582 SUPPORTED_100baseT_Half) { 9583 bp->link_params.req_line_speed[idx] = 9584 SPEED_100; 9585 bp->link_params.req_duplex[idx] = 9586 DUPLEX_HALF; 9587 bp->port.advertising[idx] |= 9588 (ADVERTISED_100baseT_Half | 9589 ADVERTISED_TP); 9590 } else { 9591 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 9592 link_config, 9593 bp->link_params.speed_cap_mask[idx]); 9594 return; 9595 } 9596 break; 9597 9598 case PORT_FEATURE_LINK_SPEED_1G: 9599 if (bp->port.supported[idx] & 9600 SUPPORTED_1000baseT_Full) { 9601 bp->link_params.req_line_speed[idx] = 9602 SPEED_1000; 9603 bp->port.advertising[idx] |= 9604 (ADVERTISED_1000baseT_Full | 9605 ADVERTISED_TP); 9606 } else { 9607 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 9608 link_config, 9609 bp->link_params.speed_cap_mask[idx]); 9610 return; 9611 } 9612 break; 9613 9614 case PORT_FEATURE_LINK_SPEED_2_5G: 9615 if (bp->port.supported[idx] & 9616 SUPPORTED_2500baseX_Full) { 9617 bp->link_params.req_line_speed[idx] = 9618 SPEED_2500; 9619 bp->port.advertising[idx] |= 9620 (ADVERTISED_2500baseX_Full | 9621 ADVERTISED_TP); 9622 } else { 9623 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 9624 link_config, 9625 bp->link_params.speed_cap_mask[idx]); 9626 return; 9627 } 9628 break; 9629 9630 case PORT_FEATURE_LINK_SPEED_10G_CX4: 9631 if (bp->port.supported[idx] & 9632 SUPPORTED_10000baseT_Full) { 9633 bp->link_params.req_line_speed[idx] = 9634 SPEED_10000; 9635 bp->port.advertising[idx] |= 9636 (ADVERTISED_10000baseT_Full | 9637 ADVERTISED_FIBRE); 9638 } else { 9639 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 9640 link_config, 9641 bp->link_params.speed_cap_mask[idx]); 9642 return; 9643 } 9644 break; 9645 case PORT_FEATURE_LINK_SPEED_20G: 9646 bp->link_params.req_line_speed[idx] = SPEED_20000; 9647 9648 break; 9649 default: 9650 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", 9651 link_config); 9652 bp->link_params.req_line_speed[idx] = 9653 SPEED_AUTO_NEG; 9654 bp->port.advertising[idx] = 9655 bp->port.supported[idx]; 9656 break; 9657 } 9658 9659 bp->link_params.req_flow_ctrl[idx] = (link_config & 9660 PORT_FEATURE_FLOW_CONTROL_MASK); 9661 if ((bp->link_params.req_flow_ctrl[idx] == 9662 BNX2X_FLOW_CTRL_AUTO) && 9663 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { 9664 bp->link_params.req_flow_ctrl[idx] = 9665 BNX2X_FLOW_CTRL_NONE; 9666 } 9667 9668 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", 9669 bp->link_params.req_line_speed[idx], 9670 bp->link_params.req_duplex[idx], 9671 bp->link_params.req_flow_ctrl[idx], 9672 bp->port.advertising[idx]); 9673 } 9674} 9675 9676static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 9677{ 9678 mac_hi = cpu_to_be16(mac_hi); 9679 mac_lo = cpu_to_be32(mac_lo); 9680 memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); 9681 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); 9682} 9683 9684static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) 9685{ 9686 int port = BP_PORT(bp); 9687 u32 config; 9688 u32 ext_phy_type, ext_phy_config; 9689 9690 bp->link_params.bp = bp; 9691 bp->link_params.port = port; 9692 9693 bp->link_params.lane_config = 9694 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 9695 9696 bp->link_params.speed_cap_mask[0] = 9697 SHMEM_RD(bp, 9698 dev_info.port_hw_config[port].speed_capability_mask); 9699 bp->link_params.speed_cap_mask[1] = 9700 SHMEM_RD(bp, 9701 dev_info.port_hw_config[port].speed_capability_mask2); 9702 bp->port.link_config[0] = 9703 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 9704 9705 bp->port.link_config[1] = 9706 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); 9707 9708 bp->link_params.multi_phy_config = 9709 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); 9710 /* If the device is capable of WoL, set the default state according 9711 * to the HW 9712 */ 9713 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 9714 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 9715 (config & PORT_FEATURE_WOL_ENABLED)); 9716 9717 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", 9718 bp->link_params.lane_config, 9719 bp->link_params.speed_cap_mask[0], 9720 bp->port.link_config[0]); 9721 9722 bp->link_params.switch_cfg = (bp->port.link_config[0] & 9723 PORT_FEATURE_CONNECTED_SWITCH_MASK); 9724 bnx2x_phy_probe(&bp->link_params); 9725 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 9726 9727 bnx2x_link_settings_requested(bp); 9728 9729 /* 9730 * If connected directly, work with the internal PHY, otherwise, work 9731 * with the external PHY 9732 */ 9733 ext_phy_config = 9734 SHMEM_RD(bp, 9735 dev_info.port_hw_config[port].external_phy_config); 9736 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 9737 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 9738 bp->mdio.prtad = bp->port.phy_addr; 9739 9740 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 9741 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 9742 bp->mdio.prtad = 9743 XGXS_EXT_PHY_ADDR(ext_phy_config); 9744 9745 /* 9746 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) 9747 * In MF mode, it is set to cover self test cases 9748 */ 9749 if (IS_MF(bp)) 9750 bp->port.need_hw_lock = 1; 9751 else 9752 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, 9753 bp->common.shmem_base, 9754 bp->common.shmem2_base); 9755} 9756 9757void bnx2x_get_iscsi_info(struct bnx2x *bp) 9758{ 9759 u32 no_flags = NO_ISCSI_FLAG; 9760#ifdef BCM_CNIC 9761 int port = BP_PORT(bp); 9762 9763 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9764 drv_lic_key[port].max_iscsi_conn); 9765 9766 /* Get the number of maximum allowed iSCSI connections */ 9767 bp->cnic_eth_dev.max_iscsi_conn = 9768 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> 9769 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; 9770 9771 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", 9772 bp->cnic_eth_dev.max_iscsi_conn); 9773 9774 /* 9775 * If maximum allowed number of connections is zero - 9776 * disable the feature. 9777 */ 9778 if (!bp->cnic_eth_dev.max_iscsi_conn) 9779 bp->flags |= no_flags; 9780#else 9781 bp->flags |= no_flags; 9782#endif 9783} 9784 9785#ifdef BCM_CNIC 9786static void __devinit bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) 9787{ 9788 /* Port info */ 9789 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9790 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); 9791 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9792 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); 9793 9794 /* Node info */ 9795 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9796 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); 9797 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9798 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); 9799} 9800#endif 9801static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp) 9802{ 9803#ifdef BCM_CNIC 9804 int port = BP_PORT(bp); 9805 int func = BP_ABS_FUNC(bp); 9806 9807 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9808 drv_lic_key[port].max_fcoe_conn); 9809 9810 /* Get the number of maximum allowed FCoE connections */ 9811 bp->cnic_eth_dev.max_fcoe_conn = 9812 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> 9813 BNX2X_MAX_FCOE_INIT_CONN_SHIFT; 9814 9815 /* Read the WWN: */ 9816 if (!IS_MF(bp)) { 9817 /* Port info */ 9818 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9819 SHMEM_RD(bp, 9820 dev_info.port_hw_config[port]. 9821 fcoe_wwn_port_name_upper); 9822 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9823 SHMEM_RD(bp, 9824 dev_info.port_hw_config[port]. 9825 fcoe_wwn_port_name_lower); 9826 9827 /* Node info */ 9828 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9829 SHMEM_RD(bp, 9830 dev_info.port_hw_config[port]. 9831 fcoe_wwn_node_name_upper); 9832 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9833 SHMEM_RD(bp, 9834 dev_info.port_hw_config[port]. 9835 fcoe_wwn_node_name_lower); 9836 } else if (!IS_MF_SD(bp)) { 9837 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9838 9839 /* 9840 * Read the WWN info only if the FCoE feature is enabled for 9841 * this function. 9842 */ 9843 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 9844 bnx2x_get_ext_wwn_info(bp, func); 9845 9846 } else if (IS_MF_FCOE_SD(bp)) 9847 bnx2x_get_ext_wwn_info(bp, func); 9848 9849 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); 9850 9851 /* 9852 * If maximum allowed number of connections is zero - 9853 * disable the feature. 9854 */ 9855 if (!bp->cnic_eth_dev.max_fcoe_conn) 9856 bp->flags |= NO_FCOE_FLAG; 9857#else 9858 bp->flags |= NO_FCOE_FLAG; 9859#endif 9860} 9861 9862static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) 9863{ 9864 /* 9865 * iSCSI may be dynamically disabled but reading 9866 * info here we will decrease memory usage by driver 9867 * if the feature is disabled for good 9868 */ 9869 bnx2x_get_iscsi_info(bp); 9870 bnx2x_get_fcoe_info(bp); 9871} 9872 9873static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) 9874{ 9875 u32 val, val2; 9876 int func = BP_ABS_FUNC(bp); 9877 int port = BP_PORT(bp); 9878#ifdef BCM_CNIC 9879 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; 9880 u8 *fip_mac = bp->fip_mac; 9881#endif 9882 9883 /* Zero primary MAC configuration */ 9884 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9885 9886 if (BP_NOMCP(bp)) { 9887 BNX2X_ERROR("warning: random MAC workaround active\n"); 9888 eth_hw_addr_random(bp->dev); 9889 } else if (IS_MF(bp)) { 9890 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 9891 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); 9892 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && 9893 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) 9894 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9895 9896#ifdef BCM_CNIC 9897 /* 9898 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or 9899 * FCoE MAC then the appropriate feature should be disabled. 9900 * 9901 * In non SD mode features configuration comes from 9902 * struct func_ext_config. 9903 */ 9904 if (!IS_MF_SD(bp)) { 9905 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9906 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 9907 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9908 iscsi_mac_addr_upper); 9909 val = MF_CFG_RD(bp, func_ext_config[func]. 9910 iscsi_mac_addr_lower); 9911 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9912 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9913 iscsi_mac); 9914 } else 9915 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 9916 9917 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9918 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9919 fcoe_mac_addr_upper); 9920 val = MF_CFG_RD(bp, func_ext_config[func]. 9921 fcoe_mac_addr_lower); 9922 bnx2x_set_mac_buf(fip_mac, val, val2); 9923 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n", 9924 fip_mac); 9925 9926 } else 9927 bp->flags |= NO_FCOE_FLAG; 9928 } else { /* SD MODE */ 9929 if (IS_MF_STORAGE_SD(bp)) { 9930 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { 9931 /* use primary mac as iscsi mac */ 9932 memcpy(iscsi_mac, bp->dev->dev_addr, 9933 ETH_ALEN); 9934 9935 BNX2X_DEV_INFO("SD ISCSI MODE\n"); 9936 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9937 iscsi_mac); 9938 } else { /* FCoE */ 9939 memcpy(fip_mac, bp->dev->dev_addr, 9940 ETH_ALEN); 9941 BNX2X_DEV_INFO("SD FCoE MODE\n"); 9942 BNX2X_DEV_INFO("Read FIP MAC: %pM\n", 9943 fip_mac); 9944 } 9945 /* Zero primary MAC configuration */ 9946 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9947 } 9948 } 9949#endif 9950 } else { 9951 /* in SF read MACs from port configuration */ 9952 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 9953 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 9954 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9955 9956#ifdef BCM_CNIC 9957 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9958 iscsi_mac_upper); 9959 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9960 iscsi_mac_lower); 9961 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9962 9963 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9964 fcoe_fip_mac_upper); 9965 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9966 fcoe_fip_mac_lower); 9967 bnx2x_set_mac_buf(fip_mac, val, val2); 9968#endif 9969 } 9970 9971 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 9972 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); 9973 9974#ifdef BCM_CNIC 9975 /* Disable iSCSI if MAC configuration is 9976 * invalid. 9977 */ 9978 if (!is_valid_ether_addr(iscsi_mac)) { 9979 bp->flags |= NO_ISCSI_FLAG; 9980 memset(iscsi_mac, 0, ETH_ALEN); 9981 } 9982 9983 /* Disable FCoE if MAC configuration is 9984 * invalid. 9985 */ 9986 if (!is_valid_ether_addr(fip_mac)) { 9987 bp->flags |= NO_FCOE_FLAG; 9988 memset(bp->fip_mac, 0, ETH_ALEN); 9989 } 9990#endif 9991 9992 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) 9993 dev_err(&bp->pdev->dev, 9994 "bad Ethernet MAC address configuration: %pM\n" 9995 "change it manually before bringing up the appropriate network interface\n", 9996 bp->dev->dev_addr); 9997 9998 9999} 10000 10001static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) 10002{ 10003 int /*abs*/func = BP_ABS_FUNC(bp); 10004 int vn; 10005 u32 val = 0; 10006 int rc = 0; 10007 10008 bnx2x_get_common_hwinfo(bp); 10009 10010 /* 10011 * initialize IGU parameters 10012 */ 10013 if (CHIP_IS_E1x(bp)) { 10014 bp->common.int_block = INT_BLOCK_HC; 10015 10016 bp->igu_dsb_id = DEF_SB_IGU_ID; 10017 bp->igu_base_sb = 0; 10018 } else { 10019 bp->common.int_block = INT_BLOCK_IGU; 10020 10021 /* do not allow device reset during IGU info preocessing */ 10022 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 10023 10024 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 10025 10026 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 10027 int tout = 5000; 10028 10029 BNX2X_DEV_INFO("FORCING Normal Mode\n"); 10030 10031 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 10032 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); 10033 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); 10034 10035 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 10036 tout--; 10037 usleep_range(1000, 1000); 10038 } 10039 10040 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 10041 dev_err(&bp->pdev->dev, 10042 "FORCING Normal Mode failed!!!\n"); 10043 return -EPERM; 10044 } 10045 } 10046 10047 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 10048 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); 10049 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; 10050 } else 10051 BNX2X_DEV_INFO("IGU Normal Mode\n"); 10052 10053 bnx2x_get_igu_cam_info(bp); 10054 10055 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 10056 } 10057 10058 /* 10059 * set base FW non-default (fast path) status block id, this value is 10060 * used to initialize the fw_sb_id saved on the fp/queue structure to 10061 * determine the id used by the FW. 10062 */ 10063 if (CHIP_IS_E1x(bp)) 10064 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); 10065 else /* 10066 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of 10067 * the same queue are indicated on the same IGU SB). So we prefer 10068 * FW and IGU SBs to be the same value. 10069 */ 10070 bp->base_fw_ndsb = bp->igu_base_sb; 10071 10072 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" 10073 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, 10074 bp->igu_sb_cnt, bp->base_fw_ndsb); 10075 10076 /* 10077 * Initialize MF configuration 10078 */ 10079 10080 bp->mf_ov = 0; 10081 bp->mf_mode = 0; 10082 vn = BP_VN(bp); 10083 10084 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 10085 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 10086 bp->common.shmem2_base, SHMEM2_RD(bp, size), 10087 (u32)offsetof(struct shmem2_region, mf_cfg_addr)); 10088 10089 if (SHMEM2_HAS(bp, mf_cfg_addr)) 10090 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); 10091 else 10092 bp->common.mf_cfg_base = bp->common.shmem_base + 10093 offsetof(struct shmem_region, func_mb) + 10094 E1H_FUNC_MAX * sizeof(struct drv_func_mb); 10095 /* 10096 * get mf configuration: 10097 * 1. existence of MF configuration 10098 * 2. MAC address must be legal (check only upper bytes) 10099 * for Switch-Independent mode; 10100 * OVLAN must be legal for Switch-Dependent mode 10101 * 3. SF_MODE configures specific MF mode 10102 */ 10103 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 10104 /* get mf configuration */ 10105 val = SHMEM_RD(bp, 10106 dev_info.shared_feature_config.config); 10107 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; 10108 10109 switch (val) { 10110 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 10111 val = MF_CFG_RD(bp, func_mf_config[func]. 10112 mac_upper); 10113 /* check for legal mac (upper bytes)*/ 10114 if (val != 0xffff) { 10115 bp->mf_mode = MULTI_FUNCTION_SI; 10116 bp->mf_config[vn] = MF_CFG_RD(bp, 10117 func_mf_config[func].config); 10118 } else 10119 BNX2X_DEV_INFO("illegal MAC address for SI\n"); 10120 break; 10121 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 10122 /* get OV configuration */ 10123 val = MF_CFG_RD(bp, 10124 func_mf_config[FUNC_0].e1hov_tag); 10125 val &= FUNC_MF_CFG_E1HOV_TAG_MASK; 10126 10127 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 10128 bp->mf_mode = MULTI_FUNCTION_SD; 10129 bp->mf_config[vn] = MF_CFG_RD(bp, 10130 func_mf_config[func].config); 10131 } else 10132 BNX2X_DEV_INFO("illegal OV for SD\n"); 10133 break; 10134 default: 10135 /* Unknown configuration: reset mf_config */ 10136 bp->mf_config[vn] = 0; 10137 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); 10138 } 10139 } 10140 10141 BNX2X_DEV_INFO("%s function mode\n", 10142 IS_MF(bp) ? "multi" : "single"); 10143 10144 switch (bp->mf_mode) { 10145 case MULTI_FUNCTION_SD: 10146 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 10147 FUNC_MF_CFG_E1HOV_TAG_MASK; 10148 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 10149 bp->mf_ov = val; 10150 bp->path_has_ovlan = true; 10151 10152 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", 10153 func, bp->mf_ov, bp->mf_ov); 10154 } else { 10155 dev_err(&bp->pdev->dev, 10156 "No valid MF OV for func %d, aborting\n", 10157 func); 10158 return -EPERM; 10159 } 10160 break; 10161 case MULTI_FUNCTION_SI: 10162 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", 10163 func); 10164 break; 10165 default: 10166 if (vn) { 10167 dev_err(&bp->pdev->dev, 10168 "VN %d is in a single function mode, aborting\n", 10169 vn); 10170 return -EPERM; 10171 } 10172 break; 10173 } 10174 10175 /* check if other port on the path needs ovlan: 10176 * Since MF configuration is shared between ports 10177 * Possible mixed modes are only 10178 * {SF, SI} {SF, SD} {SD, SF} {SI, SF} 10179 */ 10180 if (CHIP_MODE_IS_4_PORT(bp) && 10181 !bp->path_has_ovlan && 10182 !IS_MF(bp) && 10183 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 10184 u8 other_port = !BP_PORT(bp); 10185 u8 other_func = BP_PATH(bp) + 2*other_port; 10186 val = MF_CFG_RD(bp, 10187 func_mf_config[other_func].e1hov_tag); 10188 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) 10189 bp->path_has_ovlan = true; 10190 } 10191 } 10192 10193 /* adjust igu_sb_cnt to MF for E1x */ 10194 if (CHIP_IS_E1x(bp) && IS_MF(bp)) 10195 bp->igu_sb_cnt /= E1HVN_MAX; 10196 10197 /* port info */ 10198 bnx2x_get_port_hwinfo(bp); 10199 10200 /* Get MAC addresses */ 10201 bnx2x_get_mac_hwinfo(bp); 10202 10203 bnx2x_get_cnic_info(bp); 10204 10205 return rc; 10206} 10207 10208static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) 10209{ 10210 int cnt, i, block_end, rodi; 10211 char vpd_start[BNX2X_VPD_LEN+1]; 10212 char str_id_reg[VENDOR_ID_LEN+1]; 10213 char str_id_cap[VENDOR_ID_LEN+1]; 10214 char *vpd_data; 10215 char *vpd_extended_data = NULL; 10216 u8 len; 10217 10218 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); 10219 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); 10220 10221 if (cnt < BNX2X_VPD_LEN) 10222 goto out_not_found; 10223 10224 /* VPD RO tag should be first tag after identifier string, hence 10225 * we should be able to find it in first BNX2X_VPD_LEN chars 10226 */ 10227 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, 10228 PCI_VPD_LRDT_RO_DATA); 10229 if (i < 0) 10230 goto out_not_found; 10231 10232 block_end = i + PCI_VPD_LRDT_TAG_SIZE + 10233 pci_vpd_lrdt_size(&vpd_start[i]); 10234 10235 i += PCI_VPD_LRDT_TAG_SIZE; 10236 10237 if (block_end > BNX2X_VPD_LEN) { 10238 vpd_extended_data = kmalloc(block_end, GFP_KERNEL); 10239 if (vpd_extended_data == NULL) 10240 goto out_not_found; 10241 10242 /* read rest of vpd image into vpd_extended_data */ 10243 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); 10244 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, 10245 block_end - BNX2X_VPD_LEN, 10246 vpd_extended_data + BNX2X_VPD_LEN); 10247 if (cnt < (block_end - BNX2X_VPD_LEN)) 10248 goto out_not_found; 10249 vpd_data = vpd_extended_data; 10250 } else 10251 vpd_data = vpd_start; 10252 10253 /* now vpd_data holds full vpd content in both cases */ 10254 10255 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 10256 PCI_VPD_RO_KEYWORD_MFR_ID); 10257 if (rodi < 0) 10258 goto out_not_found; 10259 10260 len = pci_vpd_info_field_size(&vpd_data[rodi]); 10261 10262 if (len != VENDOR_ID_LEN) 10263 goto out_not_found; 10264 10265 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 10266 10267 /* vendor specific info */ 10268 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); 10269 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); 10270 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || 10271 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { 10272 10273 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 10274 PCI_VPD_RO_KEYWORD_VENDOR0); 10275 if (rodi >= 0) { 10276 len = pci_vpd_info_field_size(&vpd_data[rodi]); 10277 10278 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 10279 10280 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { 10281 memcpy(bp->fw_ver, &vpd_data[rodi], len); 10282 bp->fw_ver[len] = ' '; 10283 } 10284 } 10285 kfree(vpd_extended_data); 10286 return; 10287 } 10288out_not_found: 10289 kfree(vpd_extended_data); 10290 return; 10291} 10292 10293static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) 10294{ 10295 u32 flags = 0; 10296 10297 if (CHIP_REV_IS_FPGA(bp)) 10298 SET_FLAGS(flags, MODE_FPGA); 10299 else if (CHIP_REV_IS_EMUL(bp)) 10300 SET_FLAGS(flags, MODE_EMUL); 10301 else 10302 SET_FLAGS(flags, MODE_ASIC); 10303 10304 if (CHIP_MODE_IS_4_PORT(bp)) 10305 SET_FLAGS(flags, MODE_PORT4); 10306 else 10307 SET_FLAGS(flags, MODE_PORT2); 10308 10309 if (CHIP_IS_E2(bp)) 10310 SET_FLAGS(flags, MODE_E2); 10311 else if (CHIP_IS_E3(bp)) { 10312 SET_FLAGS(flags, MODE_E3); 10313 if (CHIP_REV(bp) == CHIP_REV_Ax) 10314 SET_FLAGS(flags, MODE_E3_A0); 10315 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ 10316 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 10317 } 10318 10319 if (IS_MF(bp)) { 10320 SET_FLAGS(flags, MODE_MF); 10321 switch (bp->mf_mode) { 10322 case MULTI_FUNCTION_SD: 10323 SET_FLAGS(flags, MODE_MF_SD); 10324 break; 10325 case MULTI_FUNCTION_SI: 10326 SET_FLAGS(flags, MODE_MF_SI); 10327 break; 10328 } 10329 } else 10330 SET_FLAGS(flags, MODE_SF); 10331 10332#if defined(__LITTLE_ENDIAN) 10333 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 10334#else /*(__BIG_ENDIAN)*/ 10335 SET_FLAGS(flags, MODE_BIG_ENDIAN); 10336#endif 10337 INIT_MODE_FLAGS(bp) = flags; 10338} 10339 10340static int __devinit bnx2x_init_bp(struct bnx2x *bp) 10341{ 10342 int func; 10343 int rc; 10344 10345 mutex_init(&bp->port.phy_mutex); 10346 mutex_init(&bp->fw_mb_mutex); 10347 spin_lock_init(&bp->stats_lock); 10348#ifdef BCM_CNIC 10349 mutex_init(&bp->cnic_mutex); 10350#endif 10351 10352 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); 10353 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); 10354 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); 10355 rc = bnx2x_get_hwinfo(bp); 10356 if (rc) 10357 return rc; 10358 10359 bnx2x_set_modes_bitmap(bp); 10360 10361 rc = bnx2x_alloc_mem_bp(bp); 10362 if (rc) 10363 return rc; 10364 10365 bnx2x_read_fwinfo(bp); 10366 10367 func = BP_FUNC(bp); 10368 10369 /* need to reset chip if undi was active */ 10370 if (!BP_NOMCP(bp)) { 10371 /* init fw_seq */ 10372 bp->fw_seq = 10373 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 10374 DRV_MSG_SEQ_NUMBER_MASK; 10375 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 10376 10377 bnx2x_prev_unload(bp); 10378 } 10379 10380 10381 if (CHIP_REV_IS_FPGA(bp)) 10382 dev_err(&bp->pdev->dev, "FPGA detected\n"); 10383 10384 if (BP_NOMCP(bp) && (func == 0)) 10385 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); 10386 10387 bp->multi_mode = multi_mode; 10388 10389 bp->disable_tpa = disable_tpa; 10390 10391#ifdef BCM_CNIC 10392 bp->disable_tpa |= IS_MF_STORAGE_SD(bp); 10393#endif 10394 10395 /* Set TPA flags */ 10396 if (bp->disable_tpa) { 10397 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); 10398 bp->dev->features &= ~NETIF_F_LRO; 10399 } else { 10400 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); 10401 bp->dev->features |= NETIF_F_LRO; 10402 } 10403 10404 if (CHIP_IS_E1(bp)) 10405 bp->dropless_fc = 0; 10406 else 10407 bp->dropless_fc = dropless_fc; 10408 10409 bp->mrrs = mrrs; 10410 10411 bp->tx_ring_size = MAX_TX_AVAIL; 10412 10413 /* make sure that the numbers are in the right granularity */ 10414 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; 10415 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; 10416 10417 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; 10418 10419 init_timer(&bp->timer); 10420 bp->timer.expires = jiffies + bp->current_interval; 10421 bp->timer.data = (unsigned long) bp; 10422 bp->timer.function = bnx2x_timer; 10423 10424 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); 10425 bnx2x_dcbx_init_params(bp); 10426 10427#ifdef BCM_CNIC 10428 if (CHIP_IS_E1x(bp)) 10429 bp->cnic_base_cl_id = FP_SB_MAX_E1x; 10430 else 10431 bp->cnic_base_cl_id = FP_SB_MAX_E2; 10432#endif 10433 10434 /* multiple tx priority */ 10435 if (CHIP_IS_E1x(bp)) 10436 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; 10437 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) 10438 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; 10439 if (CHIP_IS_E3B0(bp)) 10440 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; 10441 10442 bp->gro_check = bnx2x_need_gro_check(bp->dev->mtu); 10443 10444 return rc; 10445} 10446 10447 10448/**************************************************************************** 10449* General service functions 10450****************************************************************************/ 10451 10452/* 10453 * net_device service functions 10454 */ 10455 10456/* called with rtnl_lock */ 10457static int bnx2x_open(struct net_device *dev) 10458{ 10459 struct bnx2x *bp = netdev_priv(dev); 10460 bool global = false; 10461 int other_engine = BP_PATH(bp) ? 0 : 1; 10462 bool other_load_status, load_status; 10463 10464 bp->stats_init = true; 10465 10466 netif_carrier_off(dev); 10467 10468 bnx2x_set_power_state(bp, PCI_D0); 10469 10470 other_load_status = bnx2x_get_load_status(bp, other_engine); 10471 load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); 10472 10473 /* 10474 * If parity had happen during the unload, then attentions 10475 * and/or RECOVERY_IN_PROGRES may still be set. In this case we 10476 * want the first function loaded on the current engine to 10477 * complete the recovery. 10478 */ 10479 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 10480 bnx2x_chk_parity_attn(bp, &global, true)) 10481 do { 10482 /* 10483 * If there are attentions and they are in a global 10484 * blocks, set the GLOBAL_RESET bit regardless whether 10485 * it will be this function that will complete the 10486 * recovery or not. 10487 */ 10488 if (global) 10489 bnx2x_set_reset_global(bp); 10490 10491 /* 10492 * Only the first function on the current engine should 10493 * try to recover in open. In case of attentions in 10494 * global blocks only the first in the chip should try 10495 * to recover. 10496 */ 10497 if ((!load_status && 10498 (!global || !other_load_status)) && 10499 bnx2x_trylock_leader_lock(bp) && 10500 !bnx2x_leader_reset(bp)) { 10501 netdev_info(bp->dev, "Recovered in open\n"); 10502 break; 10503 } 10504 10505 /* recovery has failed... */ 10506 bnx2x_set_power_state(bp, PCI_D3hot); 10507 bp->recovery_state = BNX2X_RECOVERY_FAILED; 10508 10509 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" 10510 "If you still see this message after a few retries then power cycle is required.\n"); 10511 10512 return -EAGAIN; 10513 } while (0); 10514 10515 bp->recovery_state = BNX2X_RECOVERY_DONE; 10516 return bnx2x_nic_load(bp, LOAD_OPEN); 10517} 10518 10519/* called with rtnl_lock */ 10520static int bnx2x_close(struct net_device *dev) 10521{ 10522 struct bnx2x *bp = netdev_priv(dev); 10523 10524 /* Unload the driver, release IRQs */ 10525 bnx2x_nic_unload(bp, UNLOAD_CLOSE); 10526 10527 /* Power off */ 10528 bnx2x_set_power_state(bp, PCI_D3hot); 10529 10530 return 0; 10531} 10532 10533static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp, 10534 struct bnx2x_mcast_ramrod_params *p) 10535{ 10536 int mc_count = netdev_mc_count(bp->dev); 10537 struct bnx2x_mcast_list_elem *mc_mac = 10538 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); 10539 struct netdev_hw_addr *ha; 10540 10541 if (!mc_mac) 10542 return -ENOMEM; 10543 10544 INIT_LIST_HEAD(&p->mcast_list); 10545 10546 netdev_for_each_mc_addr(ha, bp->dev) { 10547 mc_mac->mac = bnx2x_mc_addr(ha); 10548 list_add_tail(&mc_mac->link, &p->mcast_list); 10549 mc_mac++; 10550 } 10551 10552 p->mcast_list_len = mc_count; 10553 10554 return 0; 10555} 10556 10557static inline void bnx2x_free_mcast_macs_list( 10558 struct bnx2x_mcast_ramrod_params *p) 10559{ 10560 struct bnx2x_mcast_list_elem *mc_mac = 10561 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, 10562 link); 10563 10564 WARN_ON(!mc_mac); 10565 kfree(mc_mac); 10566} 10567 10568/** 10569 * bnx2x_set_uc_list - configure a new unicast MACs list. 10570 * 10571 * @bp: driver handle 10572 * 10573 * We will use zero (0) as a MAC type for these MACs. 10574 */ 10575static inline int bnx2x_set_uc_list(struct bnx2x *bp) 10576{ 10577 int rc; 10578 struct net_device *dev = bp->dev; 10579 struct netdev_hw_addr *ha; 10580 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj; 10581 unsigned long ramrod_flags = 0; 10582 10583 /* First schedule a cleanup up of old configuration */ 10584 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); 10585 if (rc < 0) { 10586 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); 10587 return rc; 10588 } 10589 10590 netdev_for_each_uc_addr(ha, dev) { 10591 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, 10592 BNX2X_UC_LIST_MAC, &ramrod_flags); 10593 if (rc < 0) { 10594 BNX2X_ERR("Failed to schedule ADD operations: %d\n", 10595 rc); 10596 return rc; 10597 } 10598 } 10599 10600 /* Execute the pending commands */ 10601 __set_bit(RAMROD_CONT, &ramrod_flags); 10602 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, 10603 BNX2X_UC_LIST_MAC, &ramrod_flags); 10604} 10605 10606static inline int bnx2x_set_mc_list(struct bnx2x *bp) 10607{ 10608 struct net_device *dev = bp->dev; 10609 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 10610 int rc = 0; 10611 10612 rparam.mcast_obj = &bp->mcast_obj; 10613 10614 /* first, clear all configured multicast MACs */ 10615 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 10616 if (rc < 0) { 10617 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); 10618 return rc; 10619 } 10620 10621 /* then, configure a new MACs list */ 10622 if (netdev_mc_count(dev)) { 10623 rc = bnx2x_init_mcast_macs_list(bp, &rparam); 10624 if (rc) { 10625 BNX2X_ERR("Failed to create multicast MACs list: %d\n", 10626 rc); 10627 return rc; 10628 } 10629 10630 /* Now add the new MACs */ 10631 rc = bnx2x_config_mcast(bp, &rparam, 10632 BNX2X_MCAST_CMD_ADD); 10633 if (rc < 0) 10634 BNX2X_ERR("Failed to set a new multicast configuration: %d\n", 10635 rc); 10636 10637 bnx2x_free_mcast_macs_list(&rparam); 10638 } 10639 10640 return rc; 10641} 10642 10643 10644/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ 10645void bnx2x_set_rx_mode(struct net_device *dev) 10646{ 10647 struct bnx2x *bp = netdev_priv(dev); 10648 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 10649 10650 if (bp->state != BNX2X_STATE_OPEN) { 10651 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 10652 return; 10653 } 10654 10655 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); 10656 10657 if (dev->flags & IFF_PROMISC) 10658 rx_mode = BNX2X_RX_MODE_PROMISC; 10659 else if ((dev->flags & IFF_ALLMULTI) || 10660 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && 10661 CHIP_IS_E1(bp))) 10662 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10663 else { 10664 /* some multicasts */ 10665 if (bnx2x_set_mc_list(bp) < 0) 10666 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10667 10668 if (bnx2x_set_uc_list(bp) < 0) 10669 rx_mode = BNX2X_RX_MODE_PROMISC; 10670 } 10671 10672 bp->rx_mode = rx_mode; 10673#ifdef BCM_CNIC 10674 /* handle ISCSI SD mode */ 10675 if (IS_MF_ISCSI_SD(bp)) 10676 bp->rx_mode = BNX2X_RX_MODE_NONE; 10677#endif 10678 10679 /* Schedule the rx_mode command */ 10680 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { 10681 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 10682 return; 10683 } 10684 10685 bnx2x_set_storm_rx_mode(bp); 10686} 10687 10688/* called with rtnl_lock */ 10689static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 10690 int devad, u16 addr) 10691{ 10692 struct bnx2x *bp = netdev_priv(netdev); 10693 u16 value; 10694 int rc; 10695 10696 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 10697 prtad, devad, addr); 10698 10699 /* The HW expects different devad if CL22 is used */ 10700 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10701 10702 bnx2x_acquire_phy_lock(bp); 10703 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); 10704 bnx2x_release_phy_lock(bp); 10705 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 10706 10707 if (!rc) 10708 rc = value; 10709 return rc; 10710} 10711 10712/* called with rtnl_lock */ 10713static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, 10714 u16 addr, u16 value) 10715{ 10716 struct bnx2x *bp = netdev_priv(netdev); 10717 int rc; 10718 10719 DP(NETIF_MSG_LINK, 10720 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", 10721 prtad, devad, addr, value); 10722 10723 /* The HW expects different devad if CL22 is used */ 10724 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10725 10726 bnx2x_acquire_phy_lock(bp); 10727 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); 10728 bnx2x_release_phy_lock(bp); 10729 return rc; 10730} 10731 10732/* called with rtnl_lock */ 10733static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 10734{ 10735 struct bnx2x *bp = netdev_priv(dev); 10736 struct mii_ioctl_data *mdio = if_mii(ifr); 10737 10738 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", 10739 mdio->phy_id, mdio->reg_num, mdio->val_in); 10740 10741 if (!netif_running(dev)) 10742 return -EAGAIN; 10743 10744 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); 10745} 10746 10747#ifdef CONFIG_NET_POLL_CONTROLLER 10748static void poll_bnx2x(struct net_device *dev) 10749{ 10750 struct bnx2x *bp = netdev_priv(dev); 10751 10752 disable_irq(bp->pdev->irq); 10753 bnx2x_interrupt(bp->pdev->irq, dev); 10754 enable_irq(bp->pdev->irq); 10755} 10756#endif 10757 10758static int bnx2x_validate_addr(struct net_device *dev) 10759{ 10760 struct bnx2x *bp = netdev_priv(dev); 10761 10762 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) { 10763 BNX2X_ERR("Non-valid Ethernet address\n"); 10764 return -EADDRNOTAVAIL; 10765 } 10766 return 0; 10767} 10768 10769static const struct net_device_ops bnx2x_netdev_ops = { 10770 .ndo_open = bnx2x_open, 10771 .ndo_stop = bnx2x_close, 10772 .ndo_start_xmit = bnx2x_start_xmit, 10773 .ndo_select_queue = bnx2x_select_queue, 10774 .ndo_set_rx_mode = bnx2x_set_rx_mode, 10775 .ndo_set_mac_address = bnx2x_change_mac_addr, 10776 .ndo_validate_addr = bnx2x_validate_addr, 10777 .ndo_do_ioctl = bnx2x_ioctl, 10778 .ndo_change_mtu = bnx2x_change_mtu, 10779 .ndo_fix_features = bnx2x_fix_features, 10780 .ndo_set_features = bnx2x_set_features, 10781 .ndo_tx_timeout = bnx2x_tx_timeout, 10782#ifdef CONFIG_NET_POLL_CONTROLLER 10783 .ndo_poll_controller = poll_bnx2x, 10784#endif 10785 .ndo_setup_tc = bnx2x_setup_tc, 10786 10787#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) 10788 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, 10789#endif 10790}; 10791 10792static inline int bnx2x_set_coherency_mask(struct bnx2x *bp) 10793{ 10794 struct device *dev = &bp->pdev->dev; 10795 10796 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 10797 bp->flags |= USING_DAC_FLAG; 10798 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 10799 dev_err(dev, "dma_set_coherent_mask failed, aborting\n"); 10800 return -EIO; 10801 } 10802 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 10803 dev_err(dev, "System does not support DMA, aborting\n"); 10804 return -EIO; 10805 } 10806 10807 return 0; 10808} 10809 10810static int __devinit bnx2x_init_dev(struct pci_dev *pdev, 10811 struct net_device *dev, 10812 unsigned long board_type) 10813{ 10814 struct bnx2x *bp; 10815 int rc; 10816 u32 pci_cfg_dword; 10817 bool chip_is_e1x = (board_type == BCM57710 || 10818 board_type == BCM57711 || 10819 board_type == BCM57711E); 10820 10821 SET_NETDEV_DEV(dev, &pdev->dev); 10822 bp = netdev_priv(dev); 10823 10824 bp->dev = dev; 10825 bp->pdev = pdev; 10826 bp->flags = 0; 10827 10828 rc = pci_enable_device(pdev); 10829 if (rc) { 10830 dev_err(&bp->pdev->dev, 10831 "Cannot enable PCI device, aborting\n"); 10832 goto err_out; 10833 } 10834 10835 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 10836 dev_err(&bp->pdev->dev, 10837 "Cannot find PCI device base address, aborting\n"); 10838 rc = -ENODEV; 10839 goto err_out_disable; 10840 } 10841 10842 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 10843 dev_err(&bp->pdev->dev, "Cannot find second PCI device" 10844 " base address, aborting\n"); 10845 rc = -ENODEV; 10846 goto err_out_disable; 10847 } 10848 10849 if (atomic_read(&pdev->enable_cnt) == 1) { 10850 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 10851 if (rc) { 10852 dev_err(&bp->pdev->dev, 10853 "Cannot obtain PCI resources, aborting\n"); 10854 goto err_out_disable; 10855 } 10856 10857 pci_set_master(pdev); 10858 pci_save_state(pdev); 10859 } 10860 10861 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 10862 if (bp->pm_cap == 0) { 10863 dev_err(&bp->pdev->dev, 10864 "Cannot find power management capability, aborting\n"); 10865 rc = -EIO; 10866 goto err_out_release; 10867 } 10868 10869 if (!pci_is_pcie(pdev)) { 10870 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 10871 rc = -EIO; 10872 goto err_out_release; 10873 } 10874 10875 rc = bnx2x_set_coherency_mask(bp); 10876 if (rc) 10877 goto err_out_release; 10878 10879 dev->mem_start = pci_resource_start(pdev, 0); 10880 dev->base_addr = dev->mem_start; 10881 dev->mem_end = pci_resource_end(pdev, 0); 10882 10883 dev->irq = pdev->irq; 10884 10885 bp->regview = pci_ioremap_bar(pdev, 0); 10886 if (!bp->regview) { 10887 dev_err(&bp->pdev->dev, 10888 "Cannot map register space, aborting\n"); 10889 rc = -ENOMEM; 10890 goto err_out_release; 10891 } 10892 10893 /* In E1/E1H use pci device function given by kernel. 10894 * In E2/E3 read physical function from ME register since these chips 10895 * support Physical Device Assignment where kernel BDF maybe arbitrary 10896 * (depending on hypervisor). 10897 */ 10898 if (chip_is_e1x) 10899 bp->pf_num = PCI_FUNC(pdev->devfn); 10900 else {/* chip is E2/3*/ 10901 pci_read_config_dword(bp->pdev, 10902 PCICFG_ME_REGISTER, &pci_cfg_dword); 10903 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> 10904 ME_REG_ABS_PF_NUM_SHIFT); 10905 } 10906 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); 10907 10908 bnx2x_set_power_state(bp, PCI_D0); 10909 10910 /* clean indirect addresses */ 10911 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 10912 PCICFG_VENDOR_ID_OFFSET); 10913 /* 10914 * Clean the following indirect addresses for all functions since it 10915 * is not used by the driver. 10916 */ 10917 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); 10918 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); 10919 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 10920 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 10921 10922 if (chip_is_e1x) { 10923 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 10924 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 10925 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 10926 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); 10927 } 10928 10929 /* 10930 * Enable internal target-read (in case we are probed after PF FLR). 10931 * Must be done prior to any BAR read access. Only for 57712 and up 10932 */ 10933 if (!chip_is_e1x) 10934 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 10935 10936 /* Reset the load counter */ 10937 bnx2x_clear_load_status(bp); 10938 10939 dev->watchdog_timeo = TX_TIMEOUT; 10940 10941 dev->netdev_ops = &bnx2x_netdev_ops; 10942 bnx2x_set_ethtool_ops(dev); 10943 10944 dev->priv_flags |= IFF_UNICAST_FLT; 10945 10946 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10947 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | 10948 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | 10949 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; 10950 10951 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10952 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 10953 10954 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; 10955 if (bp->flags & USING_DAC_FLAG) 10956 dev->features |= NETIF_F_HIGHDMA; 10957 10958 /* Add Loopback capability to the device */ 10959 dev->hw_features |= NETIF_F_LOOPBACK; 10960 10961#ifdef BCM_DCBNL 10962 dev->dcbnl_ops = &bnx2x_dcbnl_ops; 10963#endif 10964 10965 /* get_port_hwinfo() will set prtad and mmds properly */ 10966 bp->mdio.prtad = MDIO_PRTAD_NONE; 10967 bp->mdio.mmds = 0; 10968 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10969 bp->mdio.dev = dev; 10970 bp->mdio.mdio_read = bnx2x_mdio_read; 10971 bp->mdio.mdio_write = bnx2x_mdio_write; 10972 10973 return 0; 10974 10975err_out_release: 10976 if (atomic_read(&pdev->enable_cnt) == 1) 10977 pci_release_regions(pdev); 10978 10979err_out_disable: 10980 pci_disable_device(pdev); 10981 pci_set_drvdata(pdev, NULL); 10982 10983err_out: 10984 return rc; 10985} 10986 10987static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, 10988 int *width, int *speed) 10989{ 10990 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); 10991 10992 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; 10993 10994 /* return value of 1=2.5GHz 2=5GHz */ 10995 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; 10996} 10997 10998static int bnx2x_check_firmware(struct bnx2x *bp) 10999{ 11000 const struct firmware *firmware = bp->firmware; 11001 struct bnx2x_fw_file_hdr *fw_hdr; 11002 struct bnx2x_fw_file_section *sections; 11003 u32 offset, len, num_ops; 11004 u16 *ops_offsets; 11005 int i; 11006 const u8 *fw_ver; 11007 11008 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { 11009 BNX2X_ERR("Wrong FW size\n"); 11010 return -EINVAL; 11011 } 11012 11013 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 11014 sections = (struct bnx2x_fw_file_section *)fw_hdr; 11015 11016 /* Make sure none of the offsets and sizes make us read beyond 11017 * the end of the firmware data */ 11018 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { 11019 offset = be32_to_cpu(sections[i].offset); 11020 len = be32_to_cpu(sections[i].len); 11021 if (offset + len > firmware->size) { 11022 BNX2X_ERR("Section %d length is out of bounds\n", i); 11023 return -EINVAL; 11024 } 11025 } 11026 11027 /* Likewise for the init_ops offsets */ 11028 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); 11029 ops_offsets = (u16 *)(firmware->data + offset); 11030 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); 11031 11032 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 11033 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 11034 BNX2X_ERR("Section offset %d is out of bounds\n", i); 11035 return -EINVAL; 11036 } 11037 } 11038 11039 /* Check FW version */ 11040 offset = be32_to_cpu(fw_hdr->fw_version.offset); 11041 fw_ver = firmware->data + offset; 11042 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || 11043 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || 11044 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || 11045 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { 11046 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 11047 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], 11048 BCM_5710_FW_MAJOR_VERSION, 11049 BCM_5710_FW_MINOR_VERSION, 11050 BCM_5710_FW_REVISION_VERSION, 11051 BCM_5710_FW_ENGINEERING_VERSION); 11052 return -EINVAL; 11053 } 11054 11055 return 0; 11056} 11057 11058static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 11059{ 11060 const __be32 *source = (const __be32 *)_source; 11061 u32 *target = (u32 *)_target; 11062 u32 i; 11063 11064 for (i = 0; i < n/4; i++) 11065 target[i] = be32_to_cpu(source[i]); 11066} 11067 11068/* 11069 Ops array is stored in the following format: 11070 {op(8bit), offset(24bit, big endian), data(32bit, big endian)} 11071 */ 11072static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) 11073{ 11074 const __be32 *source = (const __be32 *)_source; 11075 struct raw_op *target = (struct raw_op *)_target; 11076 u32 i, j, tmp; 11077 11078 for (i = 0, j = 0; i < n/8; i++, j += 2) { 11079 tmp = be32_to_cpu(source[j]); 11080 target[i].op = (tmp >> 24) & 0xff; 11081 target[i].offset = tmp & 0xffffff; 11082 target[i].raw_data = be32_to_cpu(source[j + 1]); 11083 } 11084} 11085 11086/** 11087 * IRO array is stored in the following format: 11088 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } 11089 */ 11090static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) 11091{ 11092 const __be32 *source = (const __be32 *)_source; 11093 struct iro *target = (struct iro *)_target; 11094 u32 i, j, tmp; 11095 11096 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { 11097 target[i].base = be32_to_cpu(source[j]); 11098 j++; 11099 tmp = be32_to_cpu(source[j]); 11100 target[i].m1 = (tmp >> 16) & 0xffff; 11101 target[i].m2 = tmp & 0xffff; 11102 j++; 11103 tmp = be32_to_cpu(source[j]); 11104 target[i].m3 = (tmp >> 16) & 0xffff; 11105 target[i].size = tmp & 0xffff; 11106 j++; 11107 } 11108} 11109 11110static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 11111{ 11112 const __be16 *source = (const __be16 *)_source; 11113 u16 *target = (u16 *)_target; 11114 u32 i; 11115 11116 for (i = 0; i < n/2; i++) 11117 target[i] = be16_to_cpu(source[i]); 11118} 11119 11120#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ 11121do { \ 11122 u32 len = be32_to_cpu(fw_hdr->arr.len); \ 11123 bp->arr = kmalloc(len, GFP_KERNEL); \ 11124 if (!bp->arr) \ 11125 goto lbl; \ 11126 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ 11127 (u8 *)bp->arr, len); \ 11128} while (0) 11129 11130static int bnx2x_init_firmware(struct bnx2x *bp) 11131{ 11132 const char *fw_file_name; 11133 struct bnx2x_fw_file_hdr *fw_hdr; 11134 int rc; 11135 11136 if (bp->firmware) 11137 return 0; 11138 11139 if (CHIP_IS_E1(bp)) 11140 fw_file_name = FW_FILE_NAME_E1; 11141 else if (CHIP_IS_E1H(bp)) 11142 fw_file_name = FW_FILE_NAME_E1H; 11143 else if (!CHIP_IS_E1x(bp)) 11144 fw_file_name = FW_FILE_NAME_E2; 11145 else { 11146 BNX2X_ERR("Unsupported chip revision\n"); 11147 return -EINVAL; 11148 } 11149 BNX2X_DEV_INFO("Loading %s\n", fw_file_name); 11150 11151 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); 11152 if (rc) { 11153 BNX2X_ERR("Can't load firmware file %s\n", 11154 fw_file_name); 11155 goto request_firmware_exit; 11156 } 11157 11158 rc = bnx2x_check_firmware(bp); 11159 if (rc) { 11160 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); 11161 goto request_firmware_exit; 11162 } 11163 11164 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; 11165 11166 /* Initialize the pointers to the init arrays */ 11167 /* Blob */ 11168 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); 11169 11170 /* Opcodes */ 11171 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); 11172 11173 /* Offsets */ 11174 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, 11175 be16_to_cpu_n); 11176 11177 /* STORMs firmware */ 11178 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 11179 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); 11180 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + 11181 be32_to_cpu(fw_hdr->tsem_pram_data.offset); 11182 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + 11183 be32_to_cpu(fw_hdr->usem_int_table_data.offset); 11184 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + 11185 be32_to_cpu(fw_hdr->usem_pram_data.offset); 11186 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 11187 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); 11188 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + 11189 be32_to_cpu(fw_hdr->xsem_pram_data.offset); 11190 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 11191 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 11192 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 11193 be32_to_cpu(fw_hdr->csem_pram_data.offset); 11194 /* IRO */ 11195 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); 11196 11197 return 0; 11198 11199iro_alloc_err: 11200 kfree(bp->init_ops_offsets); 11201init_offsets_alloc_err: 11202 kfree(bp->init_ops); 11203init_ops_alloc_err: 11204 kfree(bp->init_data); 11205request_firmware_exit: 11206 release_firmware(bp->firmware); 11207 bp->firmware = NULL; 11208 11209 return rc; 11210} 11211 11212static void bnx2x_release_firmware(struct bnx2x *bp) 11213{ 11214 kfree(bp->init_ops_offsets); 11215 kfree(bp->init_ops); 11216 kfree(bp->init_data); 11217 release_firmware(bp->firmware); 11218 bp->firmware = NULL; 11219} 11220 11221 11222static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { 11223 .init_hw_cmn_chip = bnx2x_init_hw_common_chip, 11224 .init_hw_cmn = bnx2x_init_hw_common, 11225 .init_hw_port = bnx2x_init_hw_port, 11226 .init_hw_func = bnx2x_init_hw_func, 11227 11228 .reset_hw_cmn = bnx2x_reset_common, 11229 .reset_hw_port = bnx2x_reset_port, 11230 .reset_hw_func = bnx2x_reset_func, 11231 11232 .gunzip_init = bnx2x_gunzip_init, 11233 .gunzip_end = bnx2x_gunzip_end, 11234 11235 .init_fw = bnx2x_init_firmware, 11236 .release_fw = bnx2x_release_firmware, 11237}; 11238 11239void bnx2x__init_func_obj(struct bnx2x *bp) 11240{ 11241 /* Prepare DMAE related driver resources */ 11242 bnx2x_setup_dmae(bp); 11243 11244 bnx2x_init_func_obj(bp, &bp->func_obj, 11245 bnx2x_sp(bp, func_rdata), 11246 bnx2x_sp_mapping(bp, func_rdata), 11247 &bnx2x_func_sp_drv); 11248} 11249 11250/* must be called after sriov-enable */ 11251static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp) 11252{ 11253 int cid_count = BNX2X_L2_CID_COUNT(bp); 11254 11255#ifdef BCM_CNIC 11256 cid_count += CNIC_CID_MAX; 11257#endif 11258 return roundup(cid_count, QM_CID_ROUND); 11259} 11260 11261/** 11262 * bnx2x_get_num_none_def_sbs - return the number of none default SBs 11263 * 11264 * @dev: pci device 11265 * 11266 */ 11267static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) 11268{ 11269 int pos; 11270 u16 control; 11271 11272 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 11273 11274 /* 11275 * If MSI-X is not supported - return number of SBs needed to support 11276 * one fast path queue: one FP queue + SB for CNIC 11277 */ 11278 if (!pos) 11279 return 1 + CNIC_PRESENT; 11280 11281 /* 11282 * The value in the PCI configuration space is the index of the last 11283 * entry, namely one less than the actual size of the table, which is 11284 * exactly what we want to return from this function: number of all SBs 11285 * without the default SB. 11286 */ 11287 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 11288 return control & PCI_MSIX_FLAGS_QSIZE; 11289} 11290 11291static int __devinit bnx2x_init_one(struct pci_dev *pdev, 11292 const struct pci_device_id *ent) 11293{ 11294 struct net_device *dev = NULL; 11295 struct bnx2x *bp; 11296 int pcie_width, pcie_speed; 11297 int rc, max_non_def_sbs; 11298 int rx_count, tx_count, rss_count; 11299 /* 11300 * An estimated maximum supported CoS number according to the chip 11301 * version. 11302 * We will try to roughly estimate the maximum number of CoSes this chip 11303 * may support in order to minimize the memory allocated for Tx 11304 * netdev_queue's. This number will be accurately calculated during the 11305 * initialization of bp->max_cos based on the chip versions AND chip 11306 * revision in the bnx2x_init_bp(). 11307 */ 11308 u8 max_cos_est = 0; 11309 11310 switch (ent->driver_data) { 11311 case BCM57710: 11312 case BCM57711: 11313 case BCM57711E: 11314 max_cos_est = BNX2X_MULTI_TX_COS_E1X; 11315 break; 11316 11317 case BCM57712: 11318 case BCM57712_MF: 11319 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; 11320 break; 11321 11322 case BCM57800: 11323 case BCM57800_MF: 11324 case BCM57810: 11325 case BCM57810_MF: 11326 case BCM57840: 11327 case BCM57840_MF: 11328 max_cos_est = BNX2X_MULTI_TX_COS_E3B0; 11329 break; 11330 11331 default: 11332 pr_err("Unknown board_type (%ld), aborting\n", 11333 ent->driver_data); 11334 return -ENODEV; 11335 } 11336 11337 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); 11338 11339 /* !!! FIXME !!! 11340 * Do not allow the maximum SB count to grow above 16 11341 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48. 11342 * We will use the FP_SB_MAX_E1x macro for this matter. 11343 */ 11344 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs); 11345 11346 WARN_ON(!max_non_def_sbs); 11347 11348 /* Maximum number of RSS queues: one IGU SB goes to CNIC */ 11349 rss_count = max_non_def_sbs - CNIC_PRESENT; 11350 11351 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ 11352 rx_count = rss_count + FCOE_PRESENT; 11353 11354 /* 11355 * Maximum number of netdev Tx queues: 11356 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 11357 */ 11358 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT; 11359 11360 /* dev zeroed in init_etherdev */ 11361 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); 11362 if (!dev) 11363 return -ENOMEM; 11364 11365 bp = netdev_priv(dev); 11366 11367 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", 11368 tx_count, rx_count); 11369 11370 bp->igu_sb_cnt = max_non_def_sbs; 11371 bp->msg_enable = debug; 11372 pci_set_drvdata(pdev, dev); 11373 11374 rc = bnx2x_init_dev(pdev, dev, ent->driver_data); 11375 if (rc < 0) { 11376 free_netdev(dev); 11377 return rc; 11378 } 11379 11380 BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs); 11381 11382 rc = bnx2x_init_bp(bp); 11383 if (rc) 11384 goto init_one_exit; 11385 11386 /* 11387 * Map doorbels here as we need the real value of bp->max_cos which 11388 * is initialized in bnx2x_init_bp(). 11389 */ 11390 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), 11391 min_t(u64, BNX2X_DB_SIZE(bp), 11392 pci_resource_len(pdev, 2))); 11393 if (!bp->doorbells) { 11394 dev_err(&bp->pdev->dev, 11395 "Cannot map doorbell space, aborting\n"); 11396 rc = -ENOMEM; 11397 goto init_one_exit; 11398 } 11399 11400 /* calc qm_cid_count */ 11401 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); 11402 11403#ifdef BCM_CNIC 11404 /* disable FCOE L2 queue for E1x */ 11405 if (CHIP_IS_E1x(bp)) 11406 bp->flags |= NO_FCOE_FLAG; 11407 11408#endif 11409 11410 /* Configure interrupt mode: try to enable MSI-X/MSI if 11411 * needed, set bp->num_queues appropriately. 11412 */ 11413 bnx2x_set_int_mode(bp); 11414 11415 /* Add all NAPI objects */ 11416 bnx2x_add_all_napi(bp); 11417 11418 rc = register_netdev(dev); 11419 if (rc) { 11420 dev_err(&pdev->dev, "Cannot register net device\n"); 11421 goto init_one_exit; 11422 } 11423 11424#ifdef BCM_CNIC 11425 if (!NO_FCOE(bp)) { 11426 /* Add storage MAC address */ 11427 rtnl_lock(); 11428 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11429 rtnl_unlock(); 11430 } 11431#endif 11432 11433 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); 11434 11435 BNX2X_DEV_INFO( 11436 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", 11437 board_info[ent->driver_data].name, 11438 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 11439 pcie_width, 11440 ((!CHIP_IS_E2(bp) && pcie_speed == 2) || 11441 (CHIP_IS_E2(bp) && pcie_speed == 1)) ? 11442 "5GHz (Gen2)" : "2.5GHz", 11443 dev->base_addr, bp->pdev->irq, dev->dev_addr); 11444 11445 return 0; 11446 11447init_one_exit: 11448 if (bp->regview) 11449 iounmap(bp->regview); 11450 11451 if (bp->doorbells) 11452 iounmap(bp->doorbells); 11453 11454 free_netdev(dev); 11455 11456 if (atomic_read(&pdev->enable_cnt) == 1) 11457 pci_release_regions(pdev); 11458 11459 pci_disable_device(pdev); 11460 pci_set_drvdata(pdev, NULL); 11461 11462 return rc; 11463} 11464 11465static void __devexit bnx2x_remove_one(struct pci_dev *pdev) 11466{ 11467 struct net_device *dev = pci_get_drvdata(pdev); 11468 struct bnx2x *bp; 11469 11470 if (!dev) { 11471 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); 11472 return; 11473 } 11474 bp = netdev_priv(dev); 11475 11476#ifdef BCM_CNIC 11477 /* Delete storage MAC address */ 11478 if (!NO_FCOE(bp)) { 11479 rtnl_lock(); 11480 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11481 rtnl_unlock(); 11482 } 11483#endif 11484 11485#ifdef BCM_DCBNL 11486 /* Delete app tlvs from dcbnl */ 11487 bnx2x_dcbnl_update_applist(bp, true); 11488#endif 11489 11490 unregister_netdev(dev); 11491 11492 /* Delete all NAPI objects */ 11493 bnx2x_del_all_napi(bp); 11494 11495 /* Power on: we can't let PCI layer write to us while we are in D3 */ 11496 bnx2x_set_power_state(bp, PCI_D0); 11497 11498 /* Disable MSI/MSI-X */ 11499 bnx2x_disable_msi(bp); 11500 11501 /* Power off */ 11502 bnx2x_set_power_state(bp, PCI_D3hot); 11503 11504 /* Make sure RESET task is not scheduled before continuing */ 11505 cancel_delayed_work_sync(&bp->sp_rtnl_task); 11506 11507 if (bp->regview) 11508 iounmap(bp->regview); 11509 11510 if (bp->doorbells) 11511 iounmap(bp->doorbells); 11512 11513 bnx2x_release_firmware(bp); 11514 11515 bnx2x_free_mem_bp(bp); 11516 11517 free_netdev(dev); 11518 11519 if (atomic_read(&pdev->enable_cnt) == 1) 11520 pci_release_regions(pdev); 11521 11522 pci_disable_device(pdev); 11523 pci_set_drvdata(pdev, NULL); 11524} 11525 11526static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 11527{ 11528 int i; 11529 11530 bp->state = BNX2X_STATE_ERROR; 11531 11532 bp->rx_mode = BNX2X_RX_MODE_NONE; 11533 11534#ifdef BCM_CNIC 11535 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); 11536#endif 11537 /* Stop Tx */ 11538 bnx2x_tx_disable(bp); 11539 11540 bnx2x_netif_stop(bp, 0); 11541 11542 del_timer_sync(&bp->timer); 11543 11544 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 11545 11546 /* Release IRQs */ 11547 bnx2x_free_irq(bp); 11548 11549 /* Free SKBs, SGEs, TPA pool and driver internals */ 11550 bnx2x_free_skbs(bp); 11551 11552 for_each_rx_queue(bp, i) 11553 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 11554 11555 bnx2x_free_mem(bp); 11556 11557 bp->state = BNX2X_STATE_CLOSED; 11558 11559 netif_carrier_off(bp->dev); 11560 11561 return 0; 11562} 11563 11564static void bnx2x_eeh_recover(struct bnx2x *bp) 11565{ 11566 u32 val; 11567 11568 mutex_init(&bp->port.phy_mutex); 11569 11570 11571 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 11572 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11573 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11574 BNX2X_ERR("BAD MCP validity signature\n"); 11575} 11576 11577/** 11578 * bnx2x_io_error_detected - called when PCI error is detected 11579 * @pdev: Pointer to PCI device 11580 * @state: The current pci connection state 11581 * 11582 * This function is called after a PCI bus error affecting 11583 * this device has been detected. 11584 */ 11585static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, 11586 pci_channel_state_t state) 11587{ 11588 struct net_device *dev = pci_get_drvdata(pdev); 11589 struct bnx2x *bp = netdev_priv(dev); 11590 11591 rtnl_lock(); 11592 11593 netif_device_detach(dev); 11594 11595 if (state == pci_channel_io_perm_failure) { 11596 rtnl_unlock(); 11597 return PCI_ERS_RESULT_DISCONNECT; 11598 } 11599 11600 if (netif_running(dev)) 11601 bnx2x_eeh_nic_unload(bp); 11602 11603 pci_disable_device(pdev); 11604 11605 rtnl_unlock(); 11606 11607 /* Request a slot reset */ 11608 return PCI_ERS_RESULT_NEED_RESET; 11609} 11610 11611/** 11612 * bnx2x_io_slot_reset - called after the PCI bus has been reset 11613 * @pdev: Pointer to PCI device 11614 * 11615 * Restart the card from scratch, as if from a cold-boot. 11616 */ 11617static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) 11618{ 11619 struct net_device *dev = pci_get_drvdata(pdev); 11620 struct bnx2x *bp = netdev_priv(dev); 11621 11622 rtnl_lock(); 11623 11624 if (pci_enable_device(pdev)) { 11625 dev_err(&pdev->dev, 11626 "Cannot re-enable PCI device after reset\n"); 11627 rtnl_unlock(); 11628 return PCI_ERS_RESULT_DISCONNECT; 11629 } 11630 11631 pci_set_master(pdev); 11632 pci_restore_state(pdev); 11633 11634 if (netif_running(dev)) 11635 bnx2x_set_power_state(bp, PCI_D0); 11636 11637 rtnl_unlock(); 11638 11639 return PCI_ERS_RESULT_RECOVERED; 11640} 11641 11642/** 11643 * bnx2x_io_resume - called when traffic can start flowing again 11644 * @pdev: Pointer to PCI device 11645 * 11646 * This callback is called when the error recovery driver tells us that 11647 * its OK to resume normal operation. 11648 */ 11649static void bnx2x_io_resume(struct pci_dev *pdev) 11650{ 11651 struct net_device *dev = pci_get_drvdata(pdev); 11652 struct bnx2x *bp = netdev_priv(dev); 11653 11654 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 11655 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); 11656 return; 11657 } 11658 11659 rtnl_lock(); 11660 11661 bnx2x_eeh_recover(bp); 11662 11663 if (netif_running(dev)) 11664 bnx2x_nic_load(bp, LOAD_NORMAL); 11665 11666 netif_device_attach(dev); 11667 11668 rtnl_unlock(); 11669} 11670 11671static struct pci_error_handlers bnx2x_err_handler = { 11672 .error_detected = bnx2x_io_error_detected, 11673 .slot_reset = bnx2x_io_slot_reset, 11674 .resume = bnx2x_io_resume, 11675}; 11676 11677static struct pci_driver bnx2x_pci_driver = { 11678 .name = DRV_MODULE_NAME, 11679 .id_table = bnx2x_pci_tbl, 11680 .probe = bnx2x_init_one, 11681 .remove = __devexit_p(bnx2x_remove_one), 11682 .suspend = bnx2x_suspend, 11683 .resume = bnx2x_resume, 11684 .err_handler = &bnx2x_err_handler, 11685}; 11686 11687static int __init bnx2x_init(void) 11688{ 11689 int ret; 11690 11691 pr_info("%s", version); 11692 11693 bnx2x_wq = create_singlethread_workqueue("bnx2x"); 11694 if (bnx2x_wq == NULL) { 11695 pr_err("Cannot create workqueue\n"); 11696 return -ENOMEM; 11697 } 11698 11699 ret = pci_register_driver(&bnx2x_pci_driver); 11700 if (ret) { 11701 pr_err("Cannot register driver\n"); 11702 destroy_workqueue(bnx2x_wq); 11703 } 11704 return ret; 11705} 11706 11707static void __exit bnx2x_cleanup(void) 11708{ 11709 struct list_head *pos, *q; 11710 pci_unregister_driver(&bnx2x_pci_driver); 11711 11712 destroy_workqueue(bnx2x_wq); 11713 11714 /* Free globablly allocated resources */ 11715 list_for_each_safe(pos, q, &bnx2x_prev_list) { 11716 struct bnx2x_prev_path_list *tmp = 11717 list_entry(pos, struct bnx2x_prev_path_list, list); 11718 list_del(pos); 11719 kfree(tmp); 11720 } 11721} 11722 11723void bnx2x_notify_link_changed(struct bnx2x *bp) 11724{ 11725 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); 11726} 11727 11728module_init(bnx2x_init); 11729module_exit(bnx2x_cleanup); 11730 11731#ifdef BCM_CNIC 11732/** 11733 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). 11734 * 11735 * @bp: driver handle 11736 * @set: set or clear the CAM entry 11737 * 11738 * This function will wait until the ramdord completion returns. 11739 * Return 0 if success, -ENODEV if ramrod doesn't return. 11740 */ 11741static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) 11742{ 11743 unsigned long ramrod_flags = 0; 11744 11745 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 11746 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, 11747 &bp->iscsi_l2_mac_obj, true, 11748 BNX2X_ISCSI_ETH_MAC, &ramrod_flags); 11749} 11750 11751/* count denotes the number of new completions we have seen */ 11752static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) 11753{ 11754 struct eth_spe *spe; 11755 11756#ifdef BNX2X_STOP_ON_ERROR 11757 if (unlikely(bp->panic)) 11758 return; 11759#endif 11760 11761 spin_lock_bh(&bp->spq_lock); 11762 BUG_ON(bp->cnic_spq_pending < count); 11763 bp->cnic_spq_pending -= count; 11764 11765 11766 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { 11767 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) 11768 & SPE_HDR_CONN_TYPE) >> 11769 SPE_HDR_CONN_TYPE_SHIFT; 11770 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) 11771 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; 11772 11773 /* Set validation for iSCSI L2 client before sending SETUP 11774 * ramrod 11775 */ 11776 if (type == ETH_CONNECTION_TYPE) { 11777 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) 11778 bnx2x_set_ctx_validation(bp, &bp->context. 11779 vcxt[BNX2X_ISCSI_ETH_CID].eth, 11780 BNX2X_ISCSI_ETH_CID); 11781 } 11782 11783 /* 11784 * There may be not more than 8 L2, not more than 8 L5 SPEs 11785 * and in the air. We also check that number of outstanding 11786 * COMMON ramrods is not more than the EQ and SPQ can 11787 * accommodate. 11788 */ 11789 if (type == ETH_CONNECTION_TYPE) { 11790 if (!atomic_read(&bp->cq_spq_left)) 11791 break; 11792 else 11793 atomic_dec(&bp->cq_spq_left); 11794 } else if (type == NONE_CONNECTION_TYPE) { 11795 if (!atomic_read(&bp->eq_spq_left)) 11796 break; 11797 else 11798 atomic_dec(&bp->eq_spq_left); 11799 } else if ((type == ISCSI_CONNECTION_TYPE) || 11800 (type == FCOE_CONNECTION_TYPE)) { 11801 if (bp->cnic_spq_pending >= 11802 bp->cnic_eth_dev.max_kwqe_pending) 11803 break; 11804 else 11805 bp->cnic_spq_pending++; 11806 } else { 11807 BNX2X_ERR("Unknown SPE type: %d\n", type); 11808 bnx2x_panic(); 11809 break; 11810 } 11811 11812 spe = bnx2x_sp_get_next(bp); 11813 *spe = *bp->cnic_kwq_cons; 11814 11815 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", 11816 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 11817 11818 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 11819 bp->cnic_kwq_cons = bp->cnic_kwq; 11820 else 11821 bp->cnic_kwq_cons++; 11822 } 11823 bnx2x_sp_prod_update(bp); 11824 spin_unlock_bh(&bp->spq_lock); 11825} 11826 11827static int bnx2x_cnic_sp_queue(struct net_device *dev, 11828 struct kwqe_16 *kwqes[], u32 count) 11829{ 11830 struct bnx2x *bp = netdev_priv(dev); 11831 int i; 11832 11833#ifdef BNX2X_STOP_ON_ERROR 11834 if (unlikely(bp->panic)) { 11835 BNX2X_ERR("Can't post to SP queue while panic\n"); 11836 return -EIO; 11837 } 11838#endif 11839 11840 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && 11841 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 11842 BNX2X_ERR("Handling parity error recovery. Try again later\n"); 11843 return -EAGAIN; 11844 } 11845 11846 spin_lock_bh(&bp->spq_lock); 11847 11848 for (i = 0; i < count; i++) { 11849 struct eth_spe *spe = (struct eth_spe *)kwqes[i]; 11850 11851 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) 11852 break; 11853 11854 *bp->cnic_kwq_prod = *spe; 11855 11856 bp->cnic_kwq_pending++; 11857 11858 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", 11859 spe->hdr.conn_and_cmd_data, spe->hdr.type, 11860 spe->data.update_data_addr.hi, 11861 spe->data.update_data_addr.lo, 11862 bp->cnic_kwq_pending); 11863 11864 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 11865 bp->cnic_kwq_prod = bp->cnic_kwq; 11866 else 11867 bp->cnic_kwq_prod++; 11868 } 11869 11870 spin_unlock_bh(&bp->spq_lock); 11871 11872 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) 11873 bnx2x_cnic_sp_post(bp, 0); 11874 11875 return i; 11876} 11877 11878static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11879{ 11880 struct cnic_ops *c_ops; 11881 int rc = 0; 11882 11883 mutex_lock(&bp->cnic_mutex); 11884 c_ops = rcu_dereference_protected(bp->cnic_ops, 11885 lockdep_is_held(&bp->cnic_mutex)); 11886 if (c_ops) 11887 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11888 mutex_unlock(&bp->cnic_mutex); 11889 11890 return rc; 11891} 11892 11893static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11894{ 11895 struct cnic_ops *c_ops; 11896 int rc = 0; 11897 11898 rcu_read_lock(); 11899 c_ops = rcu_dereference(bp->cnic_ops); 11900 if (c_ops) 11901 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11902 rcu_read_unlock(); 11903 11904 return rc; 11905} 11906 11907/* 11908 * for commands that have no data 11909 */ 11910int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) 11911{ 11912 struct cnic_ctl_info ctl = {0}; 11913 11914 ctl.cmd = cmd; 11915 11916 return bnx2x_cnic_ctl_send(bp, &ctl); 11917} 11918 11919static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) 11920{ 11921 struct cnic_ctl_info ctl = {0}; 11922 11923 /* first we tell CNIC and only then we count this as a completion */ 11924 ctl.cmd = CNIC_CTL_COMPLETION_CMD; 11925 ctl.data.comp.cid = cid; 11926 ctl.data.comp.error = err; 11927 11928 bnx2x_cnic_ctl_send_bh(bp, &ctl); 11929 bnx2x_cnic_sp_post(bp, 0); 11930} 11931 11932 11933/* Called with netif_addr_lock_bh() taken. 11934 * Sets an rx_mode config for an iSCSI ETH client. 11935 * Doesn't block. 11936 * Completion should be checked outside. 11937 */ 11938static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) 11939{ 11940 unsigned long accept_flags = 0, ramrod_flags = 0; 11941 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11942 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; 11943 11944 if (start) { 11945 /* Start accepting on iSCSI L2 ring. Accept all multicasts 11946 * because it's the only way for UIO Queue to accept 11947 * multicasts (in non-promiscuous mode only one Queue per 11948 * function will receive multicast packets (leading in our 11949 * case). 11950 */ 11951 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); 11952 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); 11953 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); 11954 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 11955 11956 /* Clear STOP_PENDING bit if START is requested */ 11957 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); 11958 11959 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; 11960 } else 11961 /* Clear START_PENDING bit if STOP is requested */ 11962 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); 11963 11964 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 11965 set_bit(sched_state, &bp->sp_state); 11966 else { 11967 __set_bit(RAMROD_RX, &ramrod_flags); 11968 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, 11969 ramrod_flags); 11970 } 11971} 11972 11973 11974static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 11975{ 11976 struct bnx2x *bp = netdev_priv(dev); 11977 int rc = 0; 11978 11979 switch (ctl->cmd) { 11980 case DRV_CTL_CTXTBL_WR_CMD: { 11981 u32 index = ctl->data.io.offset; 11982 dma_addr_t addr = ctl->data.io.dma_addr; 11983 11984 bnx2x_ilt_wr(bp, index, addr); 11985 break; 11986 } 11987 11988 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { 11989 int count = ctl->data.credit.credit_count; 11990 11991 bnx2x_cnic_sp_post(bp, count); 11992 break; 11993 } 11994 11995 /* rtnl_lock is held. */ 11996 case DRV_CTL_START_L2_CMD: { 11997 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11998 unsigned long sp_bits = 0; 11999 12000 /* Configure the iSCSI classification object */ 12001 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, 12002 cp->iscsi_l2_client_id, 12003 cp->iscsi_l2_cid, BP_FUNC(bp), 12004 bnx2x_sp(bp, mac_rdata), 12005 bnx2x_sp_mapping(bp, mac_rdata), 12006 BNX2X_FILTER_MAC_PENDING, 12007 &bp->sp_state, BNX2X_OBJ_TYPE_RX, 12008 &bp->macs_pool); 12009 12010 /* Set iSCSI MAC address */ 12011 rc = bnx2x_set_iscsi_eth_mac_addr(bp); 12012 if (rc) 12013 break; 12014 12015 mmiowb(); 12016 barrier(); 12017 12018 /* Start accepting on iSCSI L2 ring */ 12019 12020 netif_addr_lock_bh(dev); 12021 bnx2x_set_iscsi_eth_rx_mode(bp, true); 12022 netif_addr_unlock_bh(dev); 12023 12024 /* bits to wait on */ 12025 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 12026 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); 12027 12028 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 12029 BNX2X_ERR("rx_mode completion timed out!\n"); 12030 12031 break; 12032 } 12033 12034 /* rtnl_lock is held. */ 12035 case DRV_CTL_STOP_L2_CMD: { 12036 unsigned long sp_bits = 0; 12037 12038 /* Stop accepting on iSCSI L2 ring */ 12039 netif_addr_lock_bh(dev); 12040 bnx2x_set_iscsi_eth_rx_mode(bp, false); 12041 netif_addr_unlock_bh(dev); 12042 12043 /* bits to wait on */ 12044 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 12045 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); 12046 12047 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 12048 BNX2X_ERR("rx_mode completion timed out!\n"); 12049 12050 mmiowb(); 12051 barrier(); 12052 12053 /* Unset iSCSI L2 MAC */ 12054 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, 12055 BNX2X_ISCSI_ETH_MAC, true); 12056 break; 12057 } 12058 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { 12059 int count = ctl->data.credit.credit_count; 12060 12061 smp_mb__before_atomic_inc(); 12062 atomic_add(count, &bp->cq_spq_left); 12063 smp_mb__after_atomic_inc(); 12064 break; 12065 } 12066 case DRV_CTL_ULP_REGISTER_CMD: { 12067 int ulp_type = ctl->data.ulp_type; 12068 12069 if (CHIP_IS_E3(bp)) { 12070 int idx = BP_FW_MB_IDX(bp); 12071 u32 cap; 12072 12073 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 12074 if (ulp_type == CNIC_ULP_ISCSI) 12075 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 12076 else if (ulp_type == CNIC_ULP_FCOE) 12077 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 12078 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 12079 } 12080 break; 12081 } 12082 case DRV_CTL_ULP_UNREGISTER_CMD: { 12083 int ulp_type = ctl->data.ulp_type; 12084 12085 if (CHIP_IS_E3(bp)) { 12086 int idx = BP_FW_MB_IDX(bp); 12087 u32 cap; 12088 12089 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 12090 if (ulp_type == CNIC_ULP_ISCSI) 12091 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 12092 else if (ulp_type == CNIC_ULP_FCOE) 12093 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 12094 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 12095 } 12096 break; 12097 } 12098 12099 default: 12100 BNX2X_ERR("unknown command %x\n", ctl->cmd); 12101 rc = -EINVAL; 12102 } 12103 12104 return rc; 12105} 12106 12107void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) 12108{ 12109 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 12110 12111 if (bp->flags & USING_MSIX_FLAG) { 12112 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 12113 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 12114 cp->irq_arr[0].vector = bp->msix_table[1].vector; 12115 } else { 12116 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 12117 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 12118 } 12119 if (!CHIP_IS_E1x(bp)) 12120 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; 12121 else 12122 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; 12123 12124 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); 12125 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); 12126 cp->irq_arr[1].status_blk = bp->def_status_blk; 12127 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 12128 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; 12129 12130 cp->num_irq = 2; 12131} 12132 12133static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, 12134 void *data) 12135{ 12136 struct bnx2x *bp = netdev_priv(dev); 12137 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 12138 12139 if (ops == NULL) { 12140 BNX2X_ERR("NULL ops received\n"); 12141 return -EINVAL; 12142 } 12143 12144 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 12145 if (!bp->cnic_kwq) 12146 return -ENOMEM; 12147 12148 bp->cnic_kwq_cons = bp->cnic_kwq; 12149 bp->cnic_kwq_prod = bp->cnic_kwq; 12150 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; 12151 12152 bp->cnic_spq_pending = 0; 12153 bp->cnic_kwq_pending = 0; 12154 12155 bp->cnic_data = data; 12156 12157 cp->num_irq = 0; 12158 cp->drv_state |= CNIC_DRV_STATE_REGD; 12159 cp->iro_arr = bp->iro_arr; 12160 12161 bnx2x_setup_cnic_irq_info(bp); 12162 12163 rcu_assign_pointer(bp->cnic_ops, ops); 12164 12165 return 0; 12166} 12167 12168static int bnx2x_unregister_cnic(struct net_device *dev) 12169{ 12170 struct bnx2x *bp = netdev_priv(dev); 12171 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 12172 12173 mutex_lock(&bp->cnic_mutex); 12174 cp->drv_state = 0; 12175 RCU_INIT_POINTER(bp->cnic_ops, NULL); 12176 mutex_unlock(&bp->cnic_mutex); 12177 synchronize_rcu(); 12178 kfree(bp->cnic_kwq); 12179 bp->cnic_kwq = NULL; 12180 12181 return 0; 12182} 12183 12184struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) 12185{ 12186 struct bnx2x *bp = netdev_priv(dev); 12187 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 12188 12189 /* If both iSCSI and FCoE are disabled - return NULL in 12190 * order to indicate CNIC that it should not try to work 12191 * with this device. 12192 */ 12193 if (NO_ISCSI(bp) && NO_FCOE(bp)) 12194 return NULL; 12195 12196 cp->drv_owner = THIS_MODULE; 12197 cp->chip_id = CHIP_ID(bp); 12198 cp->pdev = bp->pdev; 12199 cp->io_base = bp->regview; 12200 cp->io_base2 = bp->doorbells; 12201 cp->max_kwqe_pending = 8; 12202 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; 12203 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 12204 bnx2x_cid_ilt_lines(bp); 12205 cp->ctx_tbl_len = CNIC_ILT_LINES; 12206 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 12207 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 12208 cp->drv_ctl = bnx2x_drv_ctl; 12209 cp->drv_register_cnic = bnx2x_register_cnic; 12210 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 12211 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID; 12212 cp->iscsi_l2_client_id = 12213 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 12214 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID; 12215 12216 if (NO_ISCSI_OOO(bp)) 12217 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 12218 12219 if (NO_ISCSI(bp)) 12220 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; 12221 12222 if (NO_FCOE(bp)) 12223 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 12224 12225 BNX2X_DEV_INFO( 12226 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", 12227 cp->ctx_blk_size, 12228 cp->ctx_tbl_offset, 12229 cp->ctx_tbl_len, 12230 cp->starting_cid); 12231 return cp; 12232} 12233EXPORT_SYMBOL(bnx2x_cnic_probe); 12234 12235#endif /* BCM_CNIC */ 12236 12237