bnx2x_main.c revision 6e68c912eee8f5ebc975cfb81d66d4a214b07d46
1/* bnx2x_main.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2011 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20#include <linux/module.h> 21#include <linux/moduleparam.h> 22#include <linux/kernel.h> 23#include <linux/device.h> /* for dev_info() */ 24#include <linux/timer.h> 25#include <linux/errno.h> 26#include <linux/ioport.h> 27#include <linux/slab.h> 28#include <linux/interrupt.h> 29#include <linux/pci.h> 30#include <linux/init.h> 31#include <linux/netdevice.h> 32#include <linux/etherdevice.h> 33#include <linux/skbuff.h> 34#include <linux/dma-mapping.h> 35#include <linux/bitops.h> 36#include <linux/irq.h> 37#include <linux/delay.h> 38#include <asm/byteorder.h> 39#include <linux/time.h> 40#include <linux/ethtool.h> 41#include <linux/mii.h> 42#include <linux/if.h> 43#include <linux/if_vlan.h> 44#include <net/ip.h> 45#include <net/ipv6.h> 46#include <net/tcp.h> 47#include <net/checksum.h> 48#include <net/ip6_checksum.h> 49#include <linux/workqueue.h> 50#include <linux/crc32.h> 51#include <linux/crc32c.h> 52#include <linux/prefetch.h> 53#include <linux/zlib.h> 54#include <linux/io.h> 55#include <linux/stringify.h> 56#include <linux/vmalloc.h> 57 58#include "bnx2x.h" 59#include "bnx2x_init.h" 60#include "bnx2x_init_ops.h" 61#include "bnx2x_cmn.h" 62#include "bnx2x_dcb.h" 63#include "bnx2x_sp.h" 64 65#include <linux/firmware.h> 66#include "bnx2x_fw_file_hdr.h" 67/* FW files */ 68#define FW_FILE_VERSION \ 69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 72 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 73#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 74#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 75#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 76 77/* Time in jiffies before concluding the transmitter is hung */ 78#define TX_TIMEOUT (5*HZ) 79 80static char version[] __devinitdata = 81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " 82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 83 84MODULE_AUTHOR("Eliezer Tamir"); 85MODULE_DESCRIPTION("Broadcom NetXtreme II " 86 "BCM57710/57711/57711E/" 87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 88 "57840/57840_MF Driver"); 89MODULE_LICENSE("GPL"); 90MODULE_VERSION(DRV_MODULE_VERSION); 91MODULE_FIRMWARE(FW_FILE_NAME_E1); 92MODULE_FIRMWARE(FW_FILE_NAME_E1H); 93MODULE_FIRMWARE(FW_FILE_NAME_E2); 94 95static int multi_mode = 1; 96module_param(multi_mode, int, 0); 97MODULE_PARM_DESC(multi_mode, " Multi queue mode " 98 "(0 Disable; 1 Enable (default))"); 99 100int num_queues; 101module_param(num_queues, int, 0); 102MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1" 103 " (default is as a number of CPUs)"); 104 105static int disable_tpa; 106module_param(disable_tpa, int, 0); 107MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 108 109#define INT_MODE_INTx 1 110#define INT_MODE_MSI 2 111static int int_mode; 112module_param(int_mode, int, 0); 113MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 114 "(1 INT#x; 2 MSI)"); 115 116static int dropless_fc; 117module_param(dropless_fc, int, 0); 118MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 119 120static int poll; 121module_param(poll, int, 0); 122MODULE_PARM_DESC(poll, " Use polling (for debug)"); 123 124static int mrrs = -1; 125module_param(mrrs, int, 0); 126MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 127 128static int debug; 129module_param(debug, int, 0); 130MODULE_PARM_DESC(debug, " Default debug msglevel"); 131 132 133 134struct workqueue_struct *bnx2x_wq; 135 136enum bnx2x_board_type { 137 BCM57710 = 0, 138 BCM57711, 139 BCM57711E, 140 BCM57712, 141 BCM57712_MF, 142 BCM57800, 143 BCM57800_MF, 144 BCM57810, 145 BCM57810_MF, 146 BCM57840, 147 BCM57840_MF 148}; 149 150/* indexed by board_type, above */ 151static struct { 152 char *name; 153} board_info[] __devinitdata = { 154 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, 155 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, 156 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, 157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, 158 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, 159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, 160 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, 161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, 162 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, 163 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, 164 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit " 165 "Ethernet Multi Function"} 166}; 167 168#ifndef PCI_DEVICE_ID_NX2_57710 169#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 170#endif 171#ifndef PCI_DEVICE_ID_NX2_57711 172#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 173#endif 174#ifndef PCI_DEVICE_ID_NX2_57711E 175#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 176#endif 177#ifndef PCI_DEVICE_ID_NX2_57712 178#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 179#endif 180#ifndef PCI_DEVICE_ID_NX2_57712_MF 181#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 182#endif 183#ifndef PCI_DEVICE_ID_NX2_57800 184#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 185#endif 186#ifndef PCI_DEVICE_ID_NX2_57800_MF 187#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 188#endif 189#ifndef PCI_DEVICE_ID_NX2_57810 190#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 191#endif 192#ifndef PCI_DEVICE_ID_NX2_57810_MF 193#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 194#endif 195#ifndef PCI_DEVICE_ID_NX2_57840 196#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 197#endif 198#ifndef PCI_DEVICE_ID_NX2_57840_MF 199#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 200#endif 201static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 210 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 211 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, 212 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 213 { 0 } 214}; 215 216MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 217 218/**************************************************************************** 219* General service functions 220****************************************************************************/ 221 222static inline void __storm_memset_dma_mapping(struct bnx2x *bp, 223 u32 addr, dma_addr_t mapping) 224{ 225 REG_WR(bp, addr, U64_LO(mapping)); 226 REG_WR(bp, addr + 4, U64_HI(mapping)); 227} 228 229static inline void storm_memset_spq_addr(struct bnx2x *bp, 230 dma_addr_t mapping, u16 abs_fid) 231{ 232 u32 addr = XSEM_REG_FAST_MEMORY + 233 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 234 235 __storm_memset_dma_mapping(bp, addr, mapping); 236} 237 238static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 239 u16 pf_id) 240{ 241 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 242 pf_id); 243 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 244 pf_id); 245 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 246 pf_id); 247 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 248 pf_id); 249} 250 251static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 252 u8 enable) 253{ 254 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 255 enable); 256 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 257 enable); 258 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 259 enable); 260 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 261 enable); 262} 263 264static inline void storm_memset_eq_data(struct bnx2x *bp, 265 struct event_ring_data *eq_data, 266 u16 pfid) 267{ 268 size_t size = sizeof(struct event_ring_data); 269 270 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 271 272 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 273} 274 275static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 276 u16 pfid) 277{ 278 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 279 REG_WR16(bp, addr, eq_prod); 280} 281 282/* used only at init 283 * locking is done by mcp 284 */ 285static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 286{ 287 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 288 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 289 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 290 PCICFG_VENDOR_ID_OFFSET); 291} 292 293static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 294{ 295 u32 val; 296 297 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 298 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 299 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 300 PCICFG_VENDOR_ID_OFFSET); 301 302 return val; 303} 304 305#define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 306#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 307#define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 308#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 309#define DMAE_DP_DST_NONE "dst_addr [none]" 310 311static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, 312 int msglvl) 313{ 314 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 315 316 switch (dmae->opcode & DMAE_COMMAND_DST) { 317 case DMAE_CMD_DST_PCI: 318 if (src_type == DMAE_CMD_SRC_PCI) 319 DP(msglvl, "DMAE: opcode 0x%08x\n" 320 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 321 "comp_addr [%x:%08x], comp_val 0x%08x\n", 322 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 323 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 324 dmae->comp_addr_hi, dmae->comp_addr_lo, 325 dmae->comp_val); 326 else 327 DP(msglvl, "DMAE: opcode 0x%08x\n" 328 "src [%08x], len [%d*4], dst [%x:%08x]\n" 329 "comp_addr [%x:%08x], comp_val 0x%08x\n", 330 dmae->opcode, dmae->src_addr_lo >> 2, 331 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 332 dmae->comp_addr_hi, dmae->comp_addr_lo, 333 dmae->comp_val); 334 break; 335 case DMAE_CMD_DST_GRC: 336 if (src_type == DMAE_CMD_SRC_PCI) 337 DP(msglvl, "DMAE: opcode 0x%08x\n" 338 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 339 "comp_addr [%x:%08x], comp_val 0x%08x\n", 340 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 341 dmae->len, dmae->dst_addr_lo >> 2, 342 dmae->comp_addr_hi, dmae->comp_addr_lo, 343 dmae->comp_val); 344 else 345 DP(msglvl, "DMAE: opcode 0x%08x\n" 346 "src [%08x], len [%d*4], dst [%08x]\n" 347 "comp_addr [%x:%08x], comp_val 0x%08x\n", 348 dmae->opcode, dmae->src_addr_lo >> 2, 349 dmae->len, dmae->dst_addr_lo >> 2, 350 dmae->comp_addr_hi, dmae->comp_addr_lo, 351 dmae->comp_val); 352 break; 353 default: 354 if (src_type == DMAE_CMD_SRC_PCI) 355 DP(msglvl, "DMAE: opcode 0x%08x\n" 356 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 357 "comp_addr [%x:%08x] comp_val 0x%08x\n", 358 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 359 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 360 dmae->comp_val); 361 else 362 DP(msglvl, "DMAE: opcode 0x%08x\n" 363 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 364 "comp_addr [%x:%08x] comp_val 0x%08x\n", 365 dmae->opcode, dmae->src_addr_lo >> 2, 366 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 367 dmae->comp_val); 368 break; 369 } 370 371} 372 373/* copy command into DMAE command memory and set DMAE command go */ 374void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 375{ 376 u32 cmd_offset; 377 int i; 378 379 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 380 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 381 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 382 383 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n", 384 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); 385 } 386 REG_WR(bp, dmae_reg_go_c[idx], 1); 387} 388 389u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 390{ 391 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 392 DMAE_CMD_C_ENABLE); 393} 394 395u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 396{ 397 return opcode & ~DMAE_CMD_SRC_RESET; 398} 399 400u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 401 bool with_comp, u8 comp_type) 402{ 403 u32 opcode = 0; 404 405 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 406 (dst_type << DMAE_COMMAND_DST_SHIFT)); 407 408 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 409 410 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 411 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) | 412 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 413 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 414 415#ifdef __BIG_ENDIAN 416 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 417#else 418 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 419#endif 420 if (with_comp) 421 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 422 return opcode; 423} 424 425static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 426 struct dmae_command *dmae, 427 u8 src_type, u8 dst_type) 428{ 429 memset(dmae, 0, sizeof(struct dmae_command)); 430 431 /* set the opcode */ 432 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 433 true, DMAE_COMP_PCI); 434 435 /* fill in the completion parameters */ 436 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 437 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 438 dmae->comp_val = DMAE_COMP_VAL; 439} 440 441/* issue a dmae command over the init-channel and wailt for completion */ 442static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, 443 struct dmae_command *dmae) 444{ 445 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 446 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 447 int rc = 0; 448 449 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n", 450 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 451 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 452 453 /* 454 * Lock the dmae channel. Disable BHs to prevent a dead-lock 455 * as long as this code is called both from syscall context and 456 * from ndo_set_rx_mode() flow that may be called from BH. 457 */ 458 spin_lock_bh(&bp->dmae_lock); 459 460 /* reset completion */ 461 *wb_comp = 0; 462 463 /* post the command on the channel used for initializations */ 464 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 465 466 /* wait for completion */ 467 udelay(5); 468 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 469 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); 470 471 if (!cnt) { 472 BNX2X_ERR("DMAE timeout!\n"); 473 rc = DMAE_TIMEOUT; 474 goto unlock; 475 } 476 cnt--; 477 udelay(50); 478 } 479 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 480 BNX2X_ERR("DMAE PCI error!\n"); 481 rc = DMAE_PCI_ERROR; 482 } 483 484 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n", 485 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 486 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 487 488unlock: 489 spin_unlock_bh(&bp->dmae_lock); 490 return rc; 491} 492 493void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 494 u32 len32) 495{ 496 struct dmae_command dmae; 497 498 if (!bp->dmae_ready) { 499 u32 *data = bnx2x_sp(bp, wb_data[0]); 500 501 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)" 502 " using indirect\n", dst_addr, len32); 503 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 504 return; 505 } 506 507 /* set opcode and fixed command fields */ 508 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 509 510 /* fill in addresses and len */ 511 dmae.src_addr_lo = U64_LO(dma_addr); 512 dmae.src_addr_hi = U64_HI(dma_addr); 513 dmae.dst_addr_lo = dst_addr >> 2; 514 dmae.dst_addr_hi = 0; 515 dmae.len = len32; 516 517 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 518 519 /* issue the command and wait for completion */ 520 bnx2x_issue_dmae_with_comp(bp, &dmae); 521} 522 523void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 524{ 525 struct dmae_command dmae; 526 527 if (!bp->dmae_ready) { 528 u32 *data = bnx2x_sp(bp, wb_data[0]); 529 int i; 530 531 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)" 532 " using indirect\n", src_addr, len32); 533 for (i = 0; i < len32; i++) 534 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 535 return; 536 } 537 538 /* set opcode and fixed command fields */ 539 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 540 541 /* fill in addresses and len */ 542 dmae.src_addr_lo = src_addr >> 2; 543 dmae.src_addr_hi = 0; 544 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 545 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 546 dmae.len = len32; 547 548 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 549 550 /* issue the command and wait for completion */ 551 bnx2x_issue_dmae_with_comp(bp, &dmae); 552} 553 554static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 555 u32 addr, u32 len) 556{ 557 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 558 int offset = 0; 559 560 while (len > dmae_wr_max) { 561 bnx2x_write_dmae(bp, phys_addr + offset, 562 addr + offset, dmae_wr_max); 563 offset += dmae_wr_max * 4; 564 len -= dmae_wr_max; 565 } 566 567 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 568} 569 570/* used only for slowpath so not inlined */ 571static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo) 572{ 573 u32 wb_write[2]; 574 575 wb_write[0] = val_hi; 576 wb_write[1] = val_lo; 577 REG_WR_DMAE(bp, reg, wb_write, 2); 578} 579 580#ifdef USE_WB_RD 581static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg) 582{ 583 u32 wb_data[2]; 584 585 REG_RD_DMAE(bp, reg, wb_data, 2); 586 587 return HILO_U64(wb_data[0], wb_data[1]); 588} 589#endif 590 591static int bnx2x_mc_assert(struct bnx2x *bp) 592{ 593 char last_idx; 594 int i, rc = 0; 595 u32 row0, row1, row2, row3; 596 597 /* XSTORM */ 598 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + 599 XSTORM_ASSERT_LIST_INDEX_OFFSET); 600 if (last_idx) 601 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 602 603 /* print the asserts */ 604 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 605 606 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + 607 XSTORM_ASSERT_LIST_OFFSET(i)); 608 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + 609 XSTORM_ASSERT_LIST_OFFSET(i) + 4); 610 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + 611 XSTORM_ASSERT_LIST_OFFSET(i) + 8); 612 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + 613 XSTORM_ASSERT_LIST_OFFSET(i) + 12); 614 615 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 616 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x" 617 " 0x%08x 0x%08x 0x%08x\n", 618 i, row3, row2, row1, row0); 619 rc++; 620 } else { 621 break; 622 } 623 } 624 625 /* TSTORM */ 626 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + 627 TSTORM_ASSERT_LIST_INDEX_OFFSET); 628 if (last_idx) 629 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 630 631 /* print the asserts */ 632 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 633 634 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + 635 TSTORM_ASSERT_LIST_OFFSET(i)); 636 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + 637 TSTORM_ASSERT_LIST_OFFSET(i) + 4); 638 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + 639 TSTORM_ASSERT_LIST_OFFSET(i) + 8); 640 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + 641 TSTORM_ASSERT_LIST_OFFSET(i) + 12); 642 643 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 644 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x" 645 " 0x%08x 0x%08x 0x%08x\n", 646 i, row3, row2, row1, row0); 647 rc++; 648 } else { 649 break; 650 } 651 } 652 653 /* CSTORM */ 654 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + 655 CSTORM_ASSERT_LIST_INDEX_OFFSET); 656 if (last_idx) 657 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 658 659 /* print the asserts */ 660 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 661 662 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + 663 CSTORM_ASSERT_LIST_OFFSET(i)); 664 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + 665 CSTORM_ASSERT_LIST_OFFSET(i) + 4); 666 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + 667 CSTORM_ASSERT_LIST_OFFSET(i) + 8); 668 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + 669 CSTORM_ASSERT_LIST_OFFSET(i) + 12); 670 671 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 672 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x" 673 " 0x%08x 0x%08x 0x%08x\n", 674 i, row3, row2, row1, row0); 675 rc++; 676 } else { 677 break; 678 } 679 } 680 681 /* USTORM */ 682 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + 683 USTORM_ASSERT_LIST_INDEX_OFFSET); 684 if (last_idx) 685 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 686 687 /* print the asserts */ 688 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 689 690 row0 = REG_RD(bp, BAR_USTRORM_INTMEM + 691 USTORM_ASSERT_LIST_OFFSET(i)); 692 row1 = REG_RD(bp, BAR_USTRORM_INTMEM + 693 USTORM_ASSERT_LIST_OFFSET(i) + 4); 694 row2 = REG_RD(bp, BAR_USTRORM_INTMEM + 695 USTORM_ASSERT_LIST_OFFSET(i) + 8); 696 row3 = REG_RD(bp, BAR_USTRORM_INTMEM + 697 USTORM_ASSERT_LIST_OFFSET(i) + 12); 698 699 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 700 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x" 701 " 0x%08x 0x%08x 0x%08x\n", 702 i, row3, row2, row1, row0); 703 rc++; 704 } else { 705 break; 706 } 707 } 708 709 return rc; 710} 711 712void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 713{ 714 u32 addr, val; 715 u32 mark, offset; 716 __be32 data[9]; 717 int word; 718 u32 trace_shmem_base; 719 if (BP_NOMCP(bp)) { 720 BNX2X_ERR("NO MCP - can not dump\n"); 721 return; 722 } 723 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 724 (bp->common.bc_ver & 0xff0000) >> 16, 725 (bp->common.bc_ver & 0xff00) >> 8, 726 (bp->common.bc_ver & 0xff)); 727 728 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 729 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 730 printk("%s" "MCP PC at 0x%x\n", lvl, val); 731 732 if (BP_PATH(bp) == 0) 733 trace_shmem_base = bp->common.shmem_base; 734 else 735 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 736 addr = trace_shmem_base - 0x0800 + 4; 737 mark = REG_RD(bp, addr); 738 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 739 + ((mark + 0x3) & ~0x3) - 0x08000000; 740 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 741 742 printk("%s", lvl); 743 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { 744 for (word = 0; word < 8; word++) 745 data[word] = htonl(REG_RD(bp, offset + 4*word)); 746 data[8] = 0x0; 747 pr_cont("%s", (char *)data); 748 } 749 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 750 for (word = 0; word < 8; word++) 751 data[word] = htonl(REG_RD(bp, offset + 4*word)); 752 data[8] = 0x0; 753 pr_cont("%s", (char *)data); 754 } 755 printk("%s" "end of fw dump\n", lvl); 756} 757 758static inline void bnx2x_fw_dump(struct bnx2x *bp) 759{ 760 bnx2x_fw_dump_lvl(bp, KERN_ERR); 761} 762 763void bnx2x_panic_dump(struct bnx2x *bp) 764{ 765 int i; 766 u16 j; 767 struct hc_sp_status_block_data sp_sb_data; 768 int func = BP_FUNC(bp); 769#ifdef BNX2X_STOP_ON_ERROR 770 u16 start = 0, end = 0; 771 u8 cos; 772#endif 773 774 bp->stats_state = STATS_STATE_DISABLED; 775 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 776 777 BNX2X_ERR("begin crash dump -----------------\n"); 778 779 /* Indices */ 780 /* Common */ 781 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)" 782 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 783 bp->def_idx, bp->def_att_idx, bp->attn_state, 784 bp->spq_prod_idx, bp->stats_counter); 785 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 786 bp->def_status_blk->atten_status_block.attn_bits, 787 bp->def_status_blk->atten_status_block.attn_bits_ack, 788 bp->def_status_blk->atten_status_block.status_block_id, 789 bp->def_status_blk->atten_status_block.attn_bits_index); 790 BNX2X_ERR(" def ("); 791 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 792 pr_cont("0x%x%s", 793 bp->def_status_blk->sp_sb.index_values[i], 794 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 795 796 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 797 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + 798 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 799 i*sizeof(u32)); 800 801 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 802 sp_sb_data.igu_sb_id, 803 sp_sb_data.igu_seg_id, 804 sp_sb_data.p_func.pf_id, 805 sp_sb_data.p_func.vnic_id, 806 sp_sb_data.p_func.vf_id, 807 sp_sb_data.p_func.vf_valid, 808 sp_sb_data.state); 809 810 811 for_each_eth_queue(bp, i) { 812 struct bnx2x_fastpath *fp = &bp->fp[i]; 813 int loop; 814 struct hc_status_block_data_e2 sb_data_e2; 815 struct hc_status_block_data_e1x sb_data_e1x; 816 struct hc_status_block_sm *hc_sm_p = 817 CHIP_IS_E1x(bp) ? 818 sb_data_e1x.common.state_machine : 819 sb_data_e2.common.state_machine; 820 struct hc_index_data *hc_index_p = 821 CHIP_IS_E1x(bp) ? 822 sb_data_e1x.index_data : 823 sb_data_e2.index_data; 824 u8 data_size, cos; 825 u32 *sb_data_p; 826 struct bnx2x_fp_txdata txdata; 827 828 /* Rx */ 829 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)" 830 " rx_comp_prod(0x%x)" 831 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 832 i, fp->rx_bd_prod, fp->rx_bd_cons, 833 fp->rx_comp_prod, 834 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 835 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)" 836 " fp_hc_idx(0x%x)\n", 837 fp->rx_sge_prod, fp->last_max_sge, 838 le16_to_cpu(fp->fp_hc_idx)); 839 840 /* Tx */ 841 for_each_cos_in_tx_queue(fp, cos) 842 { 843 txdata = fp->txdata[cos]; 844 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)" 845 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)" 846 " *tx_cons_sb(0x%x)\n", 847 i, txdata.tx_pkt_prod, 848 txdata.tx_pkt_cons, txdata.tx_bd_prod, 849 txdata.tx_bd_cons, 850 le16_to_cpu(*txdata.tx_cons_sb)); 851 } 852 853 loop = CHIP_IS_E1x(bp) ? 854 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 855 856 /* host sb data */ 857 858#ifdef BCM_CNIC 859 if (IS_FCOE_FP(fp)) 860 continue; 861#endif 862 BNX2X_ERR(" run indexes ("); 863 for (j = 0; j < HC_SB_MAX_SM; j++) 864 pr_cont("0x%x%s", 865 fp->sb_running_index[j], 866 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 867 868 BNX2X_ERR(" indexes ("); 869 for (j = 0; j < loop; j++) 870 pr_cont("0x%x%s", 871 fp->sb_index_values[j], 872 (j == loop - 1) ? ")" : " "); 873 /* fw sb data */ 874 data_size = CHIP_IS_E1x(bp) ? 875 sizeof(struct hc_status_block_data_e1x) : 876 sizeof(struct hc_status_block_data_e2); 877 data_size /= sizeof(u32); 878 sb_data_p = CHIP_IS_E1x(bp) ? 879 (u32 *)&sb_data_e1x : 880 (u32 *)&sb_data_e2; 881 /* copy sb data in here */ 882 for (j = 0; j < data_size; j++) 883 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 884 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 885 j * sizeof(u32)); 886 887 if (!CHIP_IS_E1x(bp)) { 888 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 889 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 890 "state(0x%x)\n", 891 sb_data_e2.common.p_func.pf_id, 892 sb_data_e2.common.p_func.vf_id, 893 sb_data_e2.common.p_func.vf_valid, 894 sb_data_e2.common.p_func.vnic_id, 895 sb_data_e2.common.same_igu_sb_1b, 896 sb_data_e2.common.state); 897 } else { 898 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 899 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 900 "state(0x%x)\n", 901 sb_data_e1x.common.p_func.pf_id, 902 sb_data_e1x.common.p_func.vf_id, 903 sb_data_e1x.common.p_func.vf_valid, 904 sb_data_e1x.common.p_func.vnic_id, 905 sb_data_e1x.common.same_igu_sb_1b, 906 sb_data_e1x.common.state); 907 } 908 909 /* SB_SMs data */ 910 for (j = 0; j < HC_SB_MAX_SM; j++) { 911 pr_cont("SM[%d] __flags (0x%x) " 912 "igu_sb_id (0x%x) igu_seg_id(0x%x) " 913 "time_to_expire (0x%x) " 914 "timer_value(0x%x)\n", j, 915 hc_sm_p[j].__flags, 916 hc_sm_p[j].igu_sb_id, 917 hc_sm_p[j].igu_seg_id, 918 hc_sm_p[j].time_to_expire, 919 hc_sm_p[j].timer_value); 920 } 921 922 /* Indecies data */ 923 for (j = 0; j < loop; j++) { 924 pr_cont("INDEX[%d] flags (0x%x) " 925 "timeout (0x%x)\n", j, 926 hc_index_p[j].flags, 927 hc_index_p[j].timeout); 928 } 929 } 930 931#ifdef BNX2X_STOP_ON_ERROR 932 /* Rings */ 933 /* Rx */ 934 for_each_rx_queue(bp, i) { 935 struct bnx2x_fastpath *fp = &bp->fp[i]; 936 937 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 938 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 939 for (j = start; j != end; j = RX_BD(j + 1)) { 940 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 941 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 942 943 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 944 i, j, rx_bd[1], rx_bd[0], sw_bd->skb); 945 } 946 947 start = RX_SGE(fp->rx_sge_prod); 948 end = RX_SGE(fp->last_max_sge); 949 for (j = start; j != end; j = RX_SGE(j + 1)) { 950 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 951 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 952 953 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 954 i, j, rx_sge[1], rx_sge[0], sw_page->page); 955 } 956 957 start = RCQ_BD(fp->rx_comp_cons - 10); 958 end = RCQ_BD(fp->rx_comp_cons + 503); 959 for (j = start; j != end; j = RCQ_BD(j + 1)) { 960 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 961 962 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 963 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 964 } 965 } 966 967 /* Tx */ 968 for_each_tx_queue(bp, i) { 969 struct bnx2x_fastpath *fp = &bp->fp[i]; 970 for_each_cos_in_tx_queue(fp, cos) { 971 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; 972 973 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 974 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 975 for (j = start; j != end; j = TX_BD(j + 1)) { 976 struct sw_tx_bd *sw_bd = 977 &txdata->tx_buf_ring[j]; 978 979 BNX2X_ERR("fp%d: txdata %d, " 980 "packet[%x]=[%p,%x]\n", 981 i, cos, j, sw_bd->skb, 982 sw_bd->first_bd); 983 } 984 985 start = TX_BD(txdata->tx_bd_cons - 10); 986 end = TX_BD(txdata->tx_bd_cons + 254); 987 for (j = start; j != end; j = TX_BD(j + 1)) { 988 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 989 990 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=" 991 "[%x:%x:%x:%x]\n", 992 i, cos, j, tx_bd[0], tx_bd[1], 993 tx_bd[2], tx_bd[3]); 994 } 995 } 996 } 997#endif 998 bnx2x_fw_dump(bp); 999 bnx2x_mc_assert(bp); 1000 BNX2X_ERR("end crash dump -----------------\n"); 1001} 1002 1003/* 1004 * FLR Support for E2 1005 * 1006 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 1007 * initialization. 1008 */ 1009#define FLR_WAIT_USEC 10000 /* 10 miliseconds */ 1010#define FLR_WAIT_INTERAVAL 50 /* usec */ 1011#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */ 1012 1013struct pbf_pN_buf_regs { 1014 int pN; 1015 u32 init_crd; 1016 u32 crd; 1017 u32 crd_freed; 1018}; 1019 1020struct pbf_pN_cmd_regs { 1021 int pN; 1022 u32 lines_occup; 1023 u32 lines_freed; 1024}; 1025 1026static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1027 struct pbf_pN_buf_regs *regs, 1028 u32 poll_count) 1029{ 1030 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1031 u32 cur_cnt = poll_count; 1032 1033 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1034 crd = crd_start = REG_RD(bp, regs->crd); 1035 init_crd = REG_RD(bp, regs->init_crd); 1036 1037 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1038 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1039 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1040 1041 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1042 (init_crd - crd_start))) { 1043 if (cur_cnt--) { 1044 udelay(FLR_WAIT_INTERAVAL); 1045 crd = REG_RD(bp, regs->crd); 1046 crd_freed = REG_RD(bp, regs->crd_freed); 1047 } else { 1048 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1049 regs->pN); 1050 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1051 regs->pN, crd); 1052 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1053 regs->pN, crd_freed); 1054 break; 1055 } 1056 } 1057 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1058 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN); 1059} 1060 1061static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1062 struct pbf_pN_cmd_regs *regs, 1063 u32 poll_count) 1064{ 1065 u32 occup, to_free, freed, freed_start; 1066 u32 cur_cnt = poll_count; 1067 1068 occup = to_free = REG_RD(bp, regs->lines_occup); 1069 freed = freed_start = REG_RD(bp, regs->lines_freed); 1070 1071 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1072 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1073 1074 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1075 if (cur_cnt--) { 1076 udelay(FLR_WAIT_INTERAVAL); 1077 occup = REG_RD(bp, regs->lines_occup); 1078 freed = REG_RD(bp, regs->lines_freed); 1079 } else { 1080 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1081 regs->pN); 1082 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1083 regs->pN, occup); 1084 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1085 regs->pN, freed); 1086 break; 1087 } 1088 } 1089 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1090 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN); 1091} 1092 1093static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1094 u32 expected, u32 poll_count) 1095{ 1096 u32 cur_cnt = poll_count; 1097 u32 val; 1098 1099 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1100 udelay(FLR_WAIT_INTERAVAL); 1101 1102 return val; 1103} 1104 1105static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1106 char *msg, u32 poll_cnt) 1107{ 1108 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1109 if (val != 0) { 1110 BNX2X_ERR("%s usage count=%d\n", msg, val); 1111 return 1; 1112 } 1113 return 0; 1114} 1115 1116static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1117{ 1118 /* adjust polling timeout */ 1119 if (CHIP_REV_IS_EMUL(bp)) 1120 return FLR_POLL_CNT * 2000; 1121 1122 if (CHIP_REV_IS_FPGA(bp)) 1123 return FLR_POLL_CNT * 120; 1124 1125 return FLR_POLL_CNT; 1126} 1127 1128static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1129{ 1130 struct pbf_pN_cmd_regs cmd_regs[] = { 1131 {0, (CHIP_IS_E3B0(bp)) ? 1132 PBF_REG_TQ_OCCUPANCY_Q0 : 1133 PBF_REG_P0_TQ_OCCUPANCY, 1134 (CHIP_IS_E3B0(bp)) ? 1135 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1136 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1137 {1, (CHIP_IS_E3B0(bp)) ? 1138 PBF_REG_TQ_OCCUPANCY_Q1 : 1139 PBF_REG_P1_TQ_OCCUPANCY, 1140 (CHIP_IS_E3B0(bp)) ? 1141 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1142 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1143 {4, (CHIP_IS_E3B0(bp)) ? 1144 PBF_REG_TQ_OCCUPANCY_LB_Q : 1145 PBF_REG_P4_TQ_OCCUPANCY, 1146 (CHIP_IS_E3B0(bp)) ? 1147 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1148 PBF_REG_P4_TQ_LINES_FREED_CNT} 1149 }; 1150 1151 struct pbf_pN_buf_regs buf_regs[] = { 1152 {0, (CHIP_IS_E3B0(bp)) ? 1153 PBF_REG_INIT_CRD_Q0 : 1154 PBF_REG_P0_INIT_CRD , 1155 (CHIP_IS_E3B0(bp)) ? 1156 PBF_REG_CREDIT_Q0 : 1157 PBF_REG_P0_CREDIT, 1158 (CHIP_IS_E3B0(bp)) ? 1159 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1160 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1161 {1, (CHIP_IS_E3B0(bp)) ? 1162 PBF_REG_INIT_CRD_Q1 : 1163 PBF_REG_P1_INIT_CRD, 1164 (CHIP_IS_E3B0(bp)) ? 1165 PBF_REG_CREDIT_Q1 : 1166 PBF_REG_P1_CREDIT, 1167 (CHIP_IS_E3B0(bp)) ? 1168 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1169 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1170 {4, (CHIP_IS_E3B0(bp)) ? 1171 PBF_REG_INIT_CRD_LB_Q : 1172 PBF_REG_P4_INIT_CRD, 1173 (CHIP_IS_E3B0(bp)) ? 1174 PBF_REG_CREDIT_LB_Q : 1175 PBF_REG_P4_CREDIT, 1176 (CHIP_IS_E3B0(bp)) ? 1177 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1178 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1179 }; 1180 1181 int i; 1182 1183 /* Verify the command queues are flushed P0, P1, P4 */ 1184 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1185 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1186 1187 1188 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1189 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1190 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1191} 1192 1193#define OP_GEN_PARAM(param) \ 1194 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1195 1196#define OP_GEN_TYPE(type) \ 1197 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1198 1199#define OP_GEN_AGG_VECT(index) \ 1200 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1201 1202 1203static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, 1204 u32 poll_cnt) 1205{ 1206 struct sdm_op_gen op_gen = {0}; 1207 1208 u32 comp_addr = BAR_CSTRORM_INTMEM + 1209 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1210 int ret = 0; 1211 1212 if (REG_RD(bp, comp_addr)) { 1213 BNX2X_ERR("Cleanup complete is not 0\n"); 1214 return 1; 1215 } 1216 1217 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1218 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1219 op_gen.command |= OP_GEN_AGG_VECT(clnup_func); 1220 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1221 1222 DP(BNX2X_MSG_SP, "FW Final cleanup\n"); 1223 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); 1224 1225 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1226 BNX2X_ERR("FW final cleanup did not succeed\n"); 1227 ret = 1; 1228 } 1229 /* Zero completion for nxt FLR */ 1230 REG_WR(bp, comp_addr, 0); 1231 1232 return ret; 1233} 1234 1235static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1236{ 1237 int pos; 1238 u16 status; 1239 1240 pos = pci_pcie_cap(dev); 1241 if (!pos) 1242 return false; 1243 1244 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 1245 return status & PCI_EXP_DEVSTA_TRPND; 1246} 1247 1248/* PF FLR specific routines 1249*/ 1250static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1251{ 1252 1253 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1254 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1255 CFC_REG_NUM_LCIDS_INSIDE_PF, 1256 "CFC PF usage counter timed out", 1257 poll_cnt)) 1258 return 1; 1259 1260 1261 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1262 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1263 DORQ_REG_PF_USAGE_CNT, 1264 "DQ PF usage counter timed out", 1265 poll_cnt)) 1266 return 1; 1267 1268 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1269 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1270 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1271 "QM PF usage counter timed out", 1272 poll_cnt)) 1273 return 1; 1274 1275 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1276 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1277 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1278 "Timers VNIC usage counter timed out", 1279 poll_cnt)) 1280 return 1; 1281 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1282 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1283 "Timers NUM_SCANS usage counter timed out", 1284 poll_cnt)) 1285 return 1; 1286 1287 /* Wait DMAE PF usage counter to zero */ 1288 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1289 dmae_reg_go_c[INIT_DMAE_C(bp)], 1290 "DMAE dommand register timed out", 1291 poll_cnt)) 1292 return 1; 1293 1294 return 0; 1295} 1296 1297static void bnx2x_hw_enable_status(struct bnx2x *bp) 1298{ 1299 u32 val; 1300 1301 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1302 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1303 1304 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1305 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1306 1307 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1308 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1309 1310 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1311 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1312 1313 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1314 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1315 1316 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1317 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1318 1319 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1320 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1321 1322 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1323 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1324 val); 1325} 1326 1327static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1328{ 1329 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1330 1331 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1332 1333 /* Re-enable PF target read access */ 1334 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1335 1336 /* Poll HW usage counters */ 1337 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1338 return -EBUSY; 1339 1340 /* Zero the igu 'trailing edge' and 'leading edge' */ 1341 1342 /* Send the FW cleanup command */ 1343 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1344 return -EBUSY; 1345 1346 /* ATC cleanup */ 1347 1348 /* Verify TX hw is flushed */ 1349 bnx2x_tx_hw_flushed(bp, poll_cnt); 1350 1351 /* Wait 100ms (not adjusted according to platform) */ 1352 msleep(100); 1353 1354 /* Verify no pending pci transactions */ 1355 if (bnx2x_is_pcie_pending(bp->pdev)) 1356 BNX2X_ERR("PCIE Transactions still pending\n"); 1357 1358 /* Debug */ 1359 bnx2x_hw_enable_status(bp); 1360 1361 /* 1362 * Master enable - Due to WB DMAE writes performed before this 1363 * register is re-initialized as part of the regular function init 1364 */ 1365 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1366 1367 return 0; 1368} 1369 1370static void bnx2x_hc_int_enable(struct bnx2x *bp) 1371{ 1372 int port = BP_PORT(bp); 1373 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1374 u32 val = REG_RD(bp, addr); 1375 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1376 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1377 1378 if (msix) { 1379 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1380 HC_CONFIG_0_REG_INT_LINE_EN_0); 1381 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1382 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1383 } else if (msi) { 1384 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1385 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1386 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1387 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1388 } else { 1389 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1390 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1391 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1392 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1393 1394 if (!CHIP_IS_E1(bp)) { 1395 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1396 val, port, addr); 1397 1398 REG_WR(bp, addr, val); 1399 1400 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1401 } 1402 } 1403 1404 if (CHIP_IS_E1(bp)) 1405 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1406 1407 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", 1408 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1409 1410 REG_WR(bp, addr, val); 1411 /* 1412 * Ensure that HC_CONFIG is written before leading/trailing edge config 1413 */ 1414 mmiowb(); 1415 barrier(); 1416 1417 if (!CHIP_IS_E1(bp)) { 1418 /* init leading/trailing edge */ 1419 if (IS_MF(bp)) { 1420 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4))); 1421 if (bp->port.pmf) 1422 /* enable nig and gpio3 attention */ 1423 val |= 0x1100; 1424 } else 1425 val = 0xffff; 1426 1427 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1428 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1429 } 1430 1431 /* Make sure that interrupts are indeed enabled from here on */ 1432 mmiowb(); 1433} 1434 1435static void bnx2x_igu_int_enable(struct bnx2x *bp) 1436{ 1437 u32 val; 1438 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1439 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1440 1441 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1442 1443 if (msix) { 1444 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1445 IGU_PF_CONF_SINGLE_ISR_EN); 1446 val |= (IGU_PF_CONF_FUNC_EN | 1447 IGU_PF_CONF_MSI_MSIX_EN | 1448 IGU_PF_CONF_ATTN_BIT_EN); 1449 } else if (msi) { 1450 val &= ~IGU_PF_CONF_INT_LINE_EN; 1451 val |= (IGU_PF_CONF_FUNC_EN | 1452 IGU_PF_CONF_MSI_MSIX_EN | 1453 IGU_PF_CONF_ATTN_BIT_EN | 1454 IGU_PF_CONF_SINGLE_ISR_EN); 1455 } else { 1456 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1457 val |= (IGU_PF_CONF_FUNC_EN | 1458 IGU_PF_CONF_INT_LINE_EN | 1459 IGU_PF_CONF_ATTN_BIT_EN | 1460 IGU_PF_CONF_SINGLE_ISR_EN); 1461 } 1462 1463 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n", 1464 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1465 1466 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1467 1468 barrier(); 1469 1470 /* init leading/trailing edge */ 1471 if (IS_MF(bp)) { 1472 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4))); 1473 if (bp->port.pmf) 1474 /* enable nig and gpio3 attention */ 1475 val |= 0x1100; 1476 } else 1477 val = 0xffff; 1478 1479 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1480 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1481 1482 /* Make sure that interrupts are indeed enabled from here on */ 1483 mmiowb(); 1484} 1485 1486void bnx2x_int_enable(struct bnx2x *bp) 1487{ 1488 if (bp->common.int_block == INT_BLOCK_HC) 1489 bnx2x_hc_int_enable(bp); 1490 else 1491 bnx2x_igu_int_enable(bp); 1492} 1493 1494static void bnx2x_hc_int_disable(struct bnx2x *bp) 1495{ 1496 int port = BP_PORT(bp); 1497 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1498 u32 val = REG_RD(bp, addr); 1499 1500 /* 1501 * in E1 we must use only PCI configuration space to disable 1502 * MSI/MSIX capablility 1503 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 1504 */ 1505 if (CHIP_IS_E1(bp)) { 1506 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 1507 * Use mask register to prevent from HC sending interrupts 1508 * after we exit the function 1509 */ 1510 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 1511 1512 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1513 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1514 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1515 } else 1516 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1517 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1518 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1519 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1520 1521 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1522 val, port, addr); 1523 1524 /* flush all outstanding writes */ 1525 mmiowb(); 1526 1527 REG_WR(bp, addr, val); 1528 if (REG_RD(bp, addr) != val) 1529 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1530} 1531 1532static void bnx2x_igu_int_disable(struct bnx2x *bp) 1533{ 1534 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1535 1536 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 1537 IGU_PF_CONF_INT_LINE_EN | 1538 IGU_PF_CONF_ATTN_BIT_EN); 1539 1540 DP(NETIF_MSG_INTR, "write %x to IGU\n", val); 1541 1542 /* flush all outstanding writes */ 1543 mmiowb(); 1544 1545 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1546 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 1547 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1548} 1549 1550void bnx2x_int_disable(struct bnx2x *bp) 1551{ 1552 if (bp->common.int_block == INT_BLOCK_HC) 1553 bnx2x_hc_int_disable(bp); 1554 else 1555 bnx2x_igu_int_disable(bp); 1556} 1557 1558void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1559{ 1560 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1561 int i, offset; 1562 1563 if (disable_hw) 1564 /* prevent the HW from sending interrupts */ 1565 bnx2x_int_disable(bp); 1566 1567 /* make sure all ISRs are done */ 1568 if (msix) { 1569 synchronize_irq(bp->msix_table[0].vector); 1570 offset = 1; 1571#ifdef BCM_CNIC 1572 offset++; 1573#endif 1574 for_each_eth_queue(bp, i) 1575 synchronize_irq(bp->msix_table[offset++].vector); 1576 } else 1577 synchronize_irq(bp->pdev->irq); 1578 1579 /* make sure sp_task is not running */ 1580 cancel_delayed_work(&bp->sp_task); 1581 cancel_delayed_work(&bp->period_task); 1582 flush_workqueue(bnx2x_wq); 1583} 1584 1585/* fast path */ 1586 1587/* 1588 * General service functions 1589 */ 1590 1591/* Return true if succeeded to acquire the lock */ 1592static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1593{ 1594 u32 lock_status; 1595 u32 resource_bit = (1 << resource); 1596 int func = BP_FUNC(bp); 1597 u32 hw_lock_control_reg; 1598 1599 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource); 1600 1601 /* Validating that the resource is within range */ 1602 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1603 DP(NETIF_MSG_HW, 1604 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1605 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1606 return false; 1607 } 1608 1609 if (func <= 5) 1610 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1611 else 1612 hw_lock_control_reg = 1613 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1614 1615 /* Try to acquire the lock */ 1616 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1617 lock_status = REG_RD(bp, hw_lock_control_reg); 1618 if (lock_status & resource_bit) 1619 return true; 1620 1621 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource); 1622 return false; 1623} 1624 1625/** 1626 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1627 * 1628 * @bp: driver handle 1629 * 1630 * Returns the recovery leader resource id according to the engine this function 1631 * belongs to. Currently only only 2 engines is supported. 1632 */ 1633static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1634{ 1635 if (BP_PATH(bp)) 1636 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1637 else 1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1639} 1640 1641/** 1642 * bnx2x_trylock_leader_lock- try to aquire a leader lock. 1643 * 1644 * @bp: driver handle 1645 * 1646 * Tries to aquire a leader lock for cuurent engine. 1647 */ 1648static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1649{ 1650 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1651} 1652 1653#ifdef BCM_CNIC 1654static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1655#endif 1656 1657void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1658{ 1659 struct bnx2x *bp = fp->bp; 1660 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1661 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1662 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1663 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj; 1664 1665 DP(BNX2X_MSG_SP, 1666 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1667 fp->index, cid, command, bp->state, 1668 rr_cqe->ramrod_cqe.ramrod_type); 1669 1670 switch (command) { 1671 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1672 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1673 drv_cmd = BNX2X_Q_CMD_UPDATE; 1674 break; 1675 1676 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1677 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1678 drv_cmd = BNX2X_Q_CMD_SETUP; 1679 break; 1680 1681 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1682 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1683 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1684 break; 1685 1686 case (RAMROD_CMD_ID_ETH_HALT): 1687 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1688 drv_cmd = BNX2X_Q_CMD_HALT; 1689 break; 1690 1691 case (RAMROD_CMD_ID_ETH_TERMINATE): 1692 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); 1693 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1694 break; 1695 1696 case (RAMROD_CMD_ID_ETH_EMPTY): 1697 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1698 drv_cmd = BNX2X_Q_CMD_EMPTY; 1699 break; 1700 1701 default: 1702 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1703 command, fp->index); 1704 return; 1705 } 1706 1707 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1708 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1709 /* q_obj->complete_cmd() failure means that this was 1710 * an unexpected completion. 1711 * 1712 * In this case we don't want to increase the bp->spq_left 1713 * because apparently we haven't sent this command the first 1714 * place. 1715 */ 1716#ifdef BNX2X_STOP_ON_ERROR 1717 bnx2x_panic(); 1718#else 1719 return; 1720#endif 1721 1722 smp_mb__before_atomic_inc(); 1723 atomic_inc(&bp->cq_spq_left); 1724 /* push the change in bp->spq_left and towards the memory */ 1725 smp_mb__after_atomic_inc(); 1726 1727 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1728 1729 return; 1730} 1731 1732void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 1733 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) 1734{ 1735 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; 1736 1737 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, 1738 start); 1739} 1740 1741irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1742{ 1743 struct bnx2x *bp = netdev_priv(dev_instance); 1744 u16 status = bnx2x_ack_int(bp); 1745 u16 mask; 1746 int i; 1747 u8 cos; 1748 1749 /* Return here if interrupt is shared and it's not for us */ 1750 if (unlikely(status == 0)) { 1751 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1752 return IRQ_NONE; 1753 } 1754 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1755 1756#ifdef BNX2X_STOP_ON_ERROR 1757 if (unlikely(bp->panic)) 1758 return IRQ_HANDLED; 1759#endif 1760 1761 for_each_eth_queue(bp, i) { 1762 struct bnx2x_fastpath *fp = &bp->fp[i]; 1763 1764 mask = 0x2 << (fp->index + CNIC_PRESENT); 1765 if (status & mask) { 1766 /* Handle Rx or Tx according to SB id */ 1767 prefetch(fp->rx_cons_sb); 1768 for_each_cos_in_tx_queue(fp, cos) 1769 prefetch(fp->txdata[cos].tx_cons_sb); 1770 prefetch(&fp->sb_running_index[SM_RX_ID]); 1771 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 1772 status &= ~mask; 1773 } 1774 } 1775 1776#ifdef BCM_CNIC 1777 mask = 0x2; 1778 if (status & (mask | 0x1)) { 1779 struct cnic_ops *c_ops = NULL; 1780 1781 if (likely(bp->state == BNX2X_STATE_OPEN)) { 1782 rcu_read_lock(); 1783 c_ops = rcu_dereference(bp->cnic_ops); 1784 if (c_ops) 1785 c_ops->cnic_handler(bp->cnic_data, NULL); 1786 rcu_read_unlock(); 1787 } 1788 1789 status &= ~mask; 1790 } 1791#endif 1792 1793 if (unlikely(status & 0x1)) { 1794 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1795 1796 status &= ~0x1; 1797 if (!status) 1798 return IRQ_HANDLED; 1799 } 1800 1801 if (unlikely(status)) 1802 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1803 status); 1804 1805 return IRQ_HANDLED; 1806} 1807 1808/* Link */ 1809 1810/* 1811 * General service functions 1812 */ 1813 1814int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 1815{ 1816 u32 lock_status; 1817 u32 resource_bit = (1 << resource); 1818 int func = BP_FUNC(bp); 1819 u32 hw_lock_control_reg; 1820 int cnt; 1821 1822 /* Validating that the resource is within range */ 1823 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1824 DP(NETIF_MSG_HW, 1825 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1826 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1827 return -EINVAL; 1828 } 1829 1830 if (func <= 5) { 1831 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1832 } else { 1833 hw_lock_control_reg = 1834 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1835 } 1836 1837 /* Validating that the resource is not already taken */ 1838 lock_status = REG_RD(bp, hw_lock_control_reg); 1839 if (lock_status & resource_bit) { 1840 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1841 lock_status, resource_bit); 1842 return -EEXIST; 1843 } 1844 1845 /* Try for 5 second every 5ms */ 1846 for (cnt = 0; cnt < 1000; cnt++) { 1847 /* Try to acquire the lock */ 1848 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1849 lock_status = REG_RD(bp, hw_lock_control_reg); 1850 if (lock_status & resource_bit) 1851 return 0; 1852 1853 msleep(5); 1854 } 1855 DP(NETIF_MSG_HW, "Timeout\n"); 1856 return -EAGAIN; 1857} 1858 1859int bnx2x_release_leader_lock(struct bnx2x *bp) 1860{ 1861 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1862} 1863 1864int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 1865{ 1866 u32 lock_status; 1867 u32 resource_bit = (1 << resource); 1868 int func = BP_FUNC(bp); 1869 u32 hw_lock_control_reg; 1870 1871 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource); 1872 1873 /* Validating that the resource is within range */ 1874 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1875 DP(NETIF_MSG_HW, 1876 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1877 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1878 return -EINVAL; 1879 } 1880 1881 if (func <= 5) { 1882 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1883 } else { 1884 hw_lock_control_reg = 1885 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1886 } 1887 1888 /* Validating that the resource is currently taken */ 1889 lock_status = REG_RD(bp, hw_lock_control_reg); 1890 if (!(lock_status & resource_bit)) { 1891 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1892 lock_status, resource_bit); 1893 return -EFAULT; 1894 } 1895 1896 REG_WR(bp, hw_lock_control_reg, resource_bit); 1897 return 0; 1898} 1899 1900 1901int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 1902{ 1903 /* The GPIO should be swapped if swap register is set and active */ 1904 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1905 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1906 int gpio_shift = gpio_num + 1907 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1908 u32 gpio_mask = (1 << gpio_shift); 1909 u32 gpio_reg; 1910 int value; 1911 1912 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1913 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1914 return -EINVAL; 1915 } 1916 1917 /* read GPIO value */ 1918 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1919 1920 /* get the requested pin value */ 1921 if ((gpio_reg & gpio_mask) == gpio_mask) 1922 value = 1; 1923 else 1924 value = 0; 1925 1926 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); 1927 1928 return value; 1929} 1930 1931int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 1932{ 1933 /* The GPIO should be swapped if swap register is set and active */ 1934 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1935 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1936 int gpio_shift = gpio_num + 1937 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1938 u32 gpio_mask = (1 << gpio_shift); 1939 u32 gpio_reg; 1940 1941 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1942 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1943 return -EINVAL; 1944 } 1945 1946 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1947 /* read GPIO and mask except the float bits */ 1948 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 1949 1950 switch (mode) { 1951 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1952 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n", 1953 gpio_num, gpio_shift); 1954 /* clear FLOAT and set CLR */ 1955 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1956 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 1957 break; 1958 1959 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 1960 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n", 1961 gpio_num, gpio_shift); 1962 /* clear FLOAT and set SET */ 1963 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1964 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 1965 break; 1966 1967 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 1968 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", 1969 gpio_num, gpio_shift); 1970 /* set FLOAT */ 1971 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1972 break; 1973 1974 default: 1975 break; 1976 } 1977 1978 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 1979 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1980 1981 return 0; 1982} 1983 1984int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 1985{ 1986 u32 gpio_reg = 0; 1987 int rc = 0; 1988 1989 /* Any port swapping should be handled by caller. */ 1990 1991 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1992 /* read GPIO and mask except the float bits */ 1993 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1994 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 1995 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 1996 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 1997 1998 switch (mode) { 1999 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2000 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 2001 /* set CLR */ 2002 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2003 break; 2004 2005 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2006 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 2007 /* set SET */ 2008 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2009 break; 2010 2011 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2012 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2013 /* set FLOAT */ 2014 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2015 break; 2016 2017 default: 2018 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2019 rc = -EINVAL; 2020 break; 2021 } 2022 2023 if (rc == 0) 2024 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2025 2026 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2027 2028 return rc; 2029} 2030 2031int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2032{ 2033 /* The GPIO should be swapped if swap register is set and active */ 2034 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2035 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2036 int gpio_shift = gpio_num + 2037 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2038 u32 gpio_mask = (1 << gpio_shift); 2039 u32 gpio_reg; 2040 2041 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2042 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2043 return -EINVAL; 2044 } 2045 2046 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2047 /* read GPIO int */ 2048 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2049 2050 switch (mode) { 2051 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2052 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> " 2053 "output low\n", gpio_num, gpio_shift); 2054 /* clear SET and set CLR */ 2055 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2056 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2057 break; 2058 2059 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2060 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> " 2061 "output high\n", gpio_num, gpio_shift); 2062 /* clear CLR and set SET */ 2063 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2064 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2065 break; 2066 2067 default: 2068 break; 2069 } 2070 2071 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2072 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2073 2074 return 0; 2075} 2076 2077static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) 2078{ 2079 u32 spio_mask = (1 << spio_num); 2080 u32 spio_reg; 2081 2082 if ((spio_num < MISC_REGISTERS_SPIO_4) || 2083 (spio_num > MISC_REGISTERS_SPIO_7)) { 2084 BNX2X_ERR("Invalid SPIO %d\n", spio_num); 2085 return -EINVAL; 2086 } 2087 2088 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2089 /* read SPIO and mask except the float bits */ 2090 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); 2091 2092 switch (mode) { 2093 case MISC_REGISTERS_SPIO_OUTPUT_LOW: 2094 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); 2095 /* clear FLOAT and set CLR */ 2096 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2097 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); 2098 break; 2099 2100 case MISC_REGISTERS_SPIO_OUTPUT_HIGH: 2101 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); 2102 /* clear FLOAT and set SET */ 2103 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2104 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); 2105 break; 2106 2107 case MISC_REGISTERS_SPIO_INPUT_HI_Z: 2108 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num); 2109 /* set FLOAT */ 2110 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2111 break; 2112 2113 default: 2114 break; 2115 } 2116 2117 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2118 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2119 2120 return 0; 2121} 2122 2123void bnx2x_calc_fc_adv(struct bnx2x *bp) 2124{ 2125 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2126 switch (bp->link_vars.ieee_fc & 2127 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2128 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 2129 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2130 ADVERTISED_Pause); 2131 break; 2132 2133 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2134 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2135 ADVERTISED_Pause); 2136 break; 2137 2138 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2139 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2140 break; 2141 2142 default: 2143 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2144 ADVERTISED_Pause); 2145 break; 2146 } 2147} 2148 2149u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2150{ 2151 if (!BP_NOMCP(bp)) { 2152 u8 rc; 2153 int cfx_idx = bnx2x_get_link_cfg_idx(bp); 2154 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2155 /* 2156 * Initialize link parameters structure variables 2157 * It is recommended to turn off RX FC for jumbo frames 2158 * for better performance 2159 */ 2160 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2161 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2162 else 2163 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2164 2165 bnx2x_acquire_phy_lock(bp); 2166 2167 if (load_mode == LOAD_DIAG) { 2168 struct link_params *lp = &bp->link_params; 2169 lp->loopback_mode = LOOPBACK_XGXS; 2170 /* do PHY loopback at 10G speed, if possible */ 2171 if (lp->req_line_speed[cfx_idx] < SPEED_10000) { 2172 if (lp->speed_cap_mask[cfx_idx] & 2173 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2174 lp->req_line_speed[cfx_idx] = 2175 SPEED_10000; 2176 else 2177 lp->req_line_speed[cfx_idx] = 2178 SPEED_1000; 2179 } 2180 } 2181 2182 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2183 2184 bnx2x_release_phy_lock(bp); 2185 2186 bnx2x_calc_fc_adv(bp); 2187 2188 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { 2189 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2190 bnx2x_link_report(bp); 2191 } else 2192 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2193 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2194 return rc; 2195 } 2196 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2197 return -EINVAL; 2198} 2199 2200void bnx2x_link_set(struct bnx2x *bp) 2201{ 2202 if (!BP_NOMCP(bp)) { 2203 bnx2x_acquire_phy_lock(bp); 2204 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2205 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2206 bnx2x_release_phy_lock(bp); 2207 2208 bnx2x_calc_fc_adv(bp); 2209 } else 2210 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2211} 2212 2213static void bnx2x__link_reset(struct bnx2x *bp) 2214{ 2215 if (!BP_NOMCP(bp)) { 2216 bnx2x_acquire_phy_lock(bp); 2217 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2218 bnx2x_release_phy_lock(bp); 2219 } else 2220 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2221} 2222 2223u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2224{ 2225 u8 rc = 0; 2226 2227 if (!BP_NOMCP(bp)) { 2228 bnx2x_acquire_phy_lock(bp); 2229 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2230 is_serdes); 2231 bnx2x_release_phy_lock(bp); 2232 } else 2233 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2234 2235 return rc; 2236} 2237 2238static void bnx2x_init_port_minmax(struct bnx2x *bp) 2239{ 2240 u32 r_param = bp->link_vars.line_speed / 8; 2241 u32 fair_periodic_timeout_usec; 2242 u32 t_fair; 2243 2244 memset(&(bp->cmng.rs_vars), 0, 2245 sizeof(struct rate_shaping_vars_per_port)); 2246 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port)); 2247 2248 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ 2249 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4; 2250 2251 /* this is the threshold below which no timer arming will occur 2252 1.25 coefficient is for the threshold to be a little bigger 2253 than the real time, to compensate for timer in-accuracy */ 2254 bp->cmng.rs_vars.rs_threshold = 2255 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; 2256 2257 /* resolution of fairness timer */ 2258 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; 2259 /* for 10G it is 1000usec. for 1G it is 10000usec. */ 2260 t_fair = T_FAIR_COEF / bp->link_vars.line_speed; 2261 2262 /* this is the threshold below which we won't arm the timer anymore */ 2263 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES; 2264 2265 /* we multiply by 1e3/8 to get bytes/msec. 2266 We don't want the credits to pass a credit 2267 of the t_fair*FAIR_MEM (algorithm resolution) */ 2268 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM; 2269 /* since each tick is 4 usec */ 2270 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4; 2271} 2272 2273/* Calculates the sum of vn_min_rates. 2274 It's needed for further normalizing of the min_rates. 2275 Returns: 2276 sum of vn_min_rates. 2277 or 2278 0 - if all the min_rates are 0. 2279 In the later case fainess algorithm should be deactivated. 2280 If not all min_rates are zero then those that are zeroes will be set to 1. 2281 */ 2282static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) 2283{ 2284 int all_zero = 1; 2285 int vn; 2286 2287 bp->vn_weight_sum = 0; 2288 for (vn = VN_0; vn < E1HVN_MAX; vn++) { 2289 u32 vn_cfg = bp->mf_config[vn]; 2290 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2291 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2292 2293 /* Skip hidden vns */ 2294 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2295 continue; 2296 2297 /* If min rate is zero - set it to 1 */ 2298 if (!vn_min_rate) 2299 vn_min_rate = DEF_MIN_RATE; 2300 else 2301 all_zero = 0; 2302 2303 bp->vn_weight_sum += vn_min_rate; 2304 } 2305 2306 /* if ETS or all min rates are zeros - disable fairness */ 2307 if (BNX2X_IS_ETS_ENABLED(bp)) { 2308 bp->cmng.flags.cmng_enables &= 2309 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2310 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2311 } else if (all_zero) { 2312 bp->cmng.flags.cmng_enables &= 2313 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2314 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2315 " fairness will be disabled\n"); 2316 } else 2317 bp->cmng.flags.cmng_enables |= 2318 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2319} 2320 2321static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) 2322{ 2323 struct rate_shaping_vars_per_vn m_rs_vn; 2324 struct fairness_vars_per_vn m_fair_vn; 2325 u32 vn_cfg = bp->mf_config[vn]; 2326 int func = 2*vn + BP_PORT(bp); 2327 u16 vn_min_rate, vn_max_rate; 2328 int i; 2329 2330 /* If function is hidden - set min and max to zeroes */ 2331 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 2332 vn_min_rate = 0; 2333 vn_max_rate = 0; 2334 2335 } else { 2336 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2337 2338 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2339 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2340 /* If fairness is enabled (not all min rates are zeroes) and 2341 if current min rate is zero - set it to 1. 2342 This is a requirement of the algorithm. */ 2343 if (bp->vn_weight_sum && (vn_min_rate == 0)) 2344 vn_min_rate = DEF_MIN_RATE; 2345 2346 if (IS_MF_SI(bp)) 2347 /* maxCfg in percents of linkspeed */ 2348 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2349 else 2350 /* maxCfg is absolute in 100Mb units */ 2351 vn_max_rate = maxCfg * 100; 2352 } 2353 2354 DP(NETIF_MSG_IFUP, 2355 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n", 2356 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); 2357 2358 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn)); 2359 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); 2360 2361 /* global vn counter - maximal Mbps for this vn */ 2362 m_rs_vn.vn_counter.rate = vn_max_rate; 2363 2364 /* quota - number of bytes transmitted in this period */ 2365 m_rs_vn.vn_counter.quota = 2366 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8; 2367 2368 if (bp->vn_weight_sum) { 2369 /* credit for each period of the fairness algorithm: 2370 number of bytes in T_FAIR (the vn share the port rate). 2371 vn_weight_sum should not be larger than 10000, thus 2372 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater 2373 than zero */ 2374 m_fair_vn.vn_credit_delta = 2375 max_t(u32, (vn_min_rate * (T_FAIR_COEF / 2376 (8 * bp->vn_weight_sum))), 2377 (bp->cmng.fair_vars.fair_threshold + 2378 MIN_ABOVE_THRESH)); 2379 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n", 2380 m_fair_vn.vn_credit_delta); 2381 } 2382 2383 /* Store it to internal memory */ 2384 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++) 2385 REG_WR(bp, BAR_XSTRORM_INTMEM + 2386 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4, 2387 ((u32 *)(&m_rs_vn))[i]); 2388 2389 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++) 2390 REG_WR(bp, BAR_XSTRORM_INTMEM + 2391 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4, 2392 ((u32 *)(&m_fair_vn))[i]); 2393} 2394 2395static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2396{ 2397 if (CHIP_REV_IS_SLOW(bp)) 2398 return CMNG_FNS_NONE; 2399 if (IS_MF(bp)) 2400 return CMNG_FNS_MINMAX; 2401 2402 return CMNG_FNS_NONE; 2403} 2404 2405void bnx2x_read_mf_cfg(struct bnx2x *bp) 2406{ 2407 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2408 2409 if (BP_NOMCP(bp)) 2410 return; /* what should be the default bvalue in this case */ 2411 2412 /* For 2 port configuration the absolute function number formula 2413 * is: 2414 * abs_func = 2 * vn + BP_PORT + BP_PATH 2415 * 2416 * and there are 4 functions per port 2417 * 2418 * For 4 port configuration it is 2419 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2420 * 2421 * and there are 2 functions per port 2422 */ 2423 for (vn = VN_0; vn < E1HVN_MAX; vn++) { 2424 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2425 2426 if (func >= E1H_FUNC_MAX) 2427 break; 2428 2429 bp->mf_config[vn] = 2430 MF_CFG_RD(bp, func_mf_config[func].config); 2431 } 2432} 2433 2434static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2435{ 2436 2437 if (cmng_type == CMNG_FNS_MINMAX) { 2438 int vn; 2439 2440 /* clear cmng_enables */ 2441 bp->cmng.flags.cmng_enables = 0; 2442 2443 /* read mf conf from shmem */ 2444 if (read_cfg) 2445 bnx2x_read_mf_cfg(bp); 2446 2447 /* Init rate shaping and fairness contexts */ 2448 bnx2x_init_port_minmax(bp); 2449 2450 /* vn_weight_sum and enable fairness if not 0 */ 2451 bnx2x_calc_vn_weight_sum(bp); 2452 2453 /* calculate and set min-max rate for each vn */ 2454 if (bp->port.pmf) 2455 for (vn = VN_0; vn < E1HVN_MAX; vn++) 2456 bnx2x_init_vn_minmax(bp, vn); 2457 2458 /* always enable rate shaping and fairness */ 2459 bp->cmng.flags.cmng_enables |= 2460 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2461 if (!bp->vn_weight_sum) 2462 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2463 " fairness will be disabled\n"); 2464 return; 2465 } 2466 2467 /* rate shaping and fairness are disabled */ 2468 DP(NETIF_MSG_IFUP, 2469 "rate shaping and fairness are disabled\n"); 2470} 2471 2472static inline void bnx2x_link_sync_notify(struct bnx2x *bp) 2473{ 2474 int port = BP_PORT(bp); 2475 int func; 2476 int vn; 2477 2478 /* Set the attention towards other drivers on the same port */ 2479 for (vn = VN_0; vn < E1HVN_MAX; vn++) { 2480 if (vn == BP_E1HVN(bp)) 2481 continue; 2482 2483 func = ((vn << 1) | port); 2484 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + 2485 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); 2486 } 2487} 2488 2489/* This function is called upon link interrupt */ 2490static void bnx2x_link_attn(struct bnx2x *bp) 2491{ 2492 /* Make sure that we are synced with the current statistics */ 2493 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2494 2495 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2496 2497 if (bp->link_vars.link_up) { 2498 2499 /* dropless flow control */ 2500 if (!CHIP_IS_E1(bp) && bp->dropless_fc) { 2501 int port = BP_PORT(bp); 2502 u32 pause_enabled = 0; 2503 2504 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2505 pause_enabled = 1; 2506 2507 REG_WR(bp, BAR_USTRORM_INTMEM + 2508 USTORM_ETH_PAUSE_ENABLED_OFFSET(port), 2509 pause_enabled); 2510 } 2511 2512 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2513 struct host_port_stats *pstats; 2514 2515 pstats = bnx2x_sp(bp, port_stats); 2516 /* reset old mac stats */ 2517 memset(&(pstats->mac_stx[0]), 0, 2518 sizeof(struct mac_stx)); 2519 } 2520 if (bp->state == BNX2X_STATE_OPEN) 2521 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2522 } 2523 2524 if (bp->link_vars.link_up && bp->link_vars.line_speed) { 2525 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2526 2527 if (cmng_fns != CMNG_FNS_NONE) { 2528 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2529 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2530 } else 2531 /* rate shaping and fairness are disabled */ 2532 DP(NETIF_MSG_IFUP, 2533 "single function mode without fairness\n"); 2534 } 2535 2536 __bnx2x_link_report(bp); 2537 2538 if (IS_MF(bp)) 2539 bnx2x_link_sync_notify(bp); 2540} 2541 2542void bnx2x__link_status_update(struct bnx2x *bp) 2543{ 2544 if (bp->state != BNX2X_STATE_OPEN) 2545 return; 2546 2547 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2548 2549 if (bp->link_vars.link_up) 2550 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2551 else 2552 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2553 2554 /* indicate link status */ 2555 bnx2x_link_report(bp); 2556} 2557 2558static void bnx2x_pmf_update(struct bnx2x *bp) 2559{ 2560 int port = BP_PORT(bp); 2561 u32 val; 2562 2563 bp->port.pmf = 1; 2564 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf); 2565 2566 /* 2567 * We need the mb() to ensure the ordering between the writing to 2568 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2569 */ 2570 smp_mb(); 2571 2572 /* queue a periodic task */ 2573 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2574 2575 bnx2x_dcbx_pmf_update(bp); 2576 2577 /* enable nig attention */ 2578 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4))); 2579 if (bp->common.int_block == INT_BLOCK_HC) { 2580 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 2581 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 2582 } else if (!CHIP_IS_E1x(bp)) { 2583 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 2584 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 2585 } 2586 2587 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 2588} 2589 2590/* end of Link */ 2591 2592/* slow path */ 2593 2594/* 2595 * General service functions 2596 */ 2597 2598/* send the MCP a request, block until there is a reply */ 2599u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 2600{ 2601 int mb_idx = BP_FW_MB_IDX(bp); 2602 u32 seq; 2603 u32 rc = 0; 2604 u32 cnt = 1; 2605 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 2606 2607 mutex_lock(&bp->fw_mb_mutex); 2608 seq = ++bp->fw_seq; 2609 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 2610 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 2611 2612 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 2613 (command | seq), param); 2614 2615 do { 2616 /* let the FW do it's magic ... */ 2617 msleep(delay); 2618 2619 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 2620 2621 /* Give the FW up to 5 second (500*10ms) */ 2622 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2623 2624 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 2625 cnt*delay, rc, seq); 2626 2627 /* is this a reply to our command? */ 2628 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 2629 rc &= FW_MSG_CODE_MASK; 2630 else { 2631 /* FW BUG! */ 2632 BNX2X_ERR("FW failed to respond!\n"); 2633 bnx2x_fw_dump(bp); 2634 rc = 0; 2635 } 2636 mutex_unlock(&bp->fw_mb_mutex); 2637 2638 return rc; 2639} 2640 2641static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp) 2642{ 2643#ifdef BCM_CNIC 2644 /* Statistics are not supported for CNIC Clients at the moment */ 2645 if (IS_FCOE_FP(fp)) 2646 return false; 2647#endif 2648 return true; 2649} 2650 2651void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 2652{ 2653 if (CHIP_IS_E1x(bp)) { 2654 struct tstorm_eth_function_common_config tcfg = {0}; 2655 2656 storm_memset_func_cfg(bp, &tcfg, p->func_id); 2657 } 2658 2659 /* Enable the function in the FW */ 2660 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 2661 storm_memset_func_en(bp, p->func_id, 1); 2662 2663 /* spq */ 2664 if (p->func_flgs & FUNC_FLG_SPQ) { 2665 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 2666 REG_WR(bp, XSEM_REG_FAST_MEMORY + 2667 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 2668 } 2669} 2670 2671/** 2672 * bnx2x_get_tx_only_flags - Return common flags 2673 * 2674 * @bp device handle 2675 * @fp queue handle 2676 * @zero_stats TRUE if statistics zeroing is needed 2677 * 2678 * Return the flags that are common for the Tx-only and not normal connections. 2679 */ 2680static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 2681 struct bnx2x_fastpath *fp, 2682 bool zero_stats) 2683{ 2684 unsigned long flags = 0; 2685 2686 /* PF driver will always initialize the Queue to an ACTIVE state */ 2687 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 2688 2689 /* tx only connections collect statistics (on the same index as the 2690 * parent connection). The statistics are zeroed when the parent 2691 * connection is initialized. 2692 */ 2693 if (stat_counter_valid(bp, fp)) { 2694 __set_bit(BNX2X_Q_FLG_STATS, &flags); 2695 if (zero_stats) 2696 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 2697 } 2698 2699 return flags; 2700} 2701 2702static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 2703 struct bnx2x_fastpath *fp, 2704 bool leading) 2705{ 2706 unsigned long flags = 0; 2707 2708 /* calculate other queue flags */ 2709 if (IS_MF_SD(bp)) 2710 __set_bit(BNX2X_Q_FLG_OV, &flags); 2711 2712 if (IS_FCOE_FP(fp)) 2713 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 2714 2715 if (!fp->disable_tpa) { 2716 __set_bit(BNX2X_Q_FLG_TPA, &flags); 2717 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 2718 } 2719 2720 if (leading) { 2721 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 2722 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 2723 } 2724 2725 /* Always set HW VLAN stripping */ 2726 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 2727 2728 2729 return flags | bnx2x_get_common_flags(bp, fp, true); 2730} 2731 2732static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 2733 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 2734 u8 cos) 2735{ 2736 gen_init->stat_id = bnx2x_stats_id(fp); 2737 gen_init->spcl_id = fp->cl_id; 2738 2739 /* Always use mini-jumbo MTU for FCoE L2 ring */ 2740 if (IS_FCOE_FP(fp)) 2741 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 2742 else 2743 gen_init->mtu = bp->dev->mtu; 2744 2745 gen_init->cos = cos; 2746} 2747 2748static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 2749 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 2750 struct bnx2x_rxq_setup_params *rxq_init) 2751{ 2752 u8 max_sge = 0; 2753 u16 sge_sz = 0; 2754 u16 tpa_agg_size = 0; 2755 2756 if (!fp->disable_tpa) { 2757 pause->sge_th_hi = 250; 2758 pause->sge_th_lo = 150; 2759 tpa_agg_size = min_t(u32, 2760 (min_t(u32, 8, MAX_SKB_FRAGS) * 2761 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); 2762 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 2763 SGE_PAGE_SHIFT; 2764 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 2765 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 2766 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, 2767 0xffff); 2768 } 2769 2770 /* pause - not for e1 */ 2771 if (!CHIP_IS_E1(bp)) { 2772 pause->bd_th_hi = 350; 2773 pause->bd_th_lo = 250; 2774 pause->rcq_th_hi = 350; 2775 pause->rcq_th_lo = 250; 2776 2777 pause->pri_map = 1; 2778 } 2779 2780 /* rxq setup */ 2781 rxq_init->dscr_map = fp->rx_desc_mapping; 2782 rxq_init->sge_map = fp->rx_sge_mapping; 2783 rxq_init->rcq_map = fp->rx_comp_mapping; 2784 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 2785 2786 /* This should be a maximum number of data bytes that may be 2787 * placed on the BD (not including paddings). 2788 */ 2789 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN - 2790 IP_HEADER_ALIGNMENT_PADDING; 2791 2792 rxq_init->cl_qzone_id = fp->cl_qzone_id; 2793 rxq_init->tpa_agg_sz = tpa_agg_size; 2794 rxq_init->sge_buf_sz = sge_sz; 2795 rxq_init->max_sges_pkt = max_sge; 2796 rxq_init->rss_engine_id = BP_FUNC(bp); 2797 2798 /* Maximum number or simultaneous TPA aggregation for this Queue. 2799 * 2800 * For PF Clients it should be the maximum avaliable number. 2801 * VF driver(s) may want to define it to a smaller value. 2802 */ 2803 rxq_init->max_tpa_queues = 2804 (CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 : 2805 ETH_MAX_AGGREGATION_QUEUES_E1H_E2); 2806 2807 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 2808 rxq_init->fw_sb_id = fp->fw_sb_id; 2809 2810 if (IS_FCOE_FP(fp)) 2811 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 2812 else 2813 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 2814} 2815 2816static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 2817 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 2818 u8 cos) 2819{ 2820 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping; 2821 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 2822 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 2823 txq_init->fw_sb_id = fp->fw_sb_id; 2824 2825 /* 2826 * set the tss leading client id for TX classfication == 2827 * leading RSS client id 2828 */ 2829 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 2830 2831 if (IS_FCOE_FP(fp)) { 2832 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 2833 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 2834 } 2835} 2836 2837static void bnx2x_pf_init(struct bnx2x *bp) 2838{ 2839 struct bnx2x_func_init_params func_init = {0}; 2840 struct event_ring_data eq_data = { {0} }; 2841 u16 flags; 2842 2843 if (!CHIP_IS_E1x(bp)) { 2844 /* reset IGU PF statistics: MSIX + ATTN */ 2845 /* PF */ 2846 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2847 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2848 (CHIP_MODE_IS_4_PORT(bp) ? 2849 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2850 /* ATTN */ 2851 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2852 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2853 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 2854 (CHIP_MODE_IS_4_PORT(bp) ? 2855 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2856 } 2857 2858 /* function setup flags */ 2859 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 2860 2861 /* This flag is relevant for E1x only. 2862 * E2 doesn't have a TPA configuration in a function level. 2863 */ 2864 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; 2865 2866 func_init.func_flgs = flags; 2867 func_init.pf_id = BP_FUNC(bp); 2868 func_init.func_id = BP_FUNC(bp); 2869 func_init.spq_map = bp->spq_mapping; 2870 func_init.spq_prod = bp->spq_prod_idx; 2871 2872 bnx2x_func_init(bp, &func_init); 2873 2874 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 2875 2876 /* 2877 * Congestion management values depend on the link rate 2878 * There is no active link so initial link rate is set to 10 Gbps. 2879 * When the link comes up The congestion management values are 2880 * re-calculated according to the actual link rate. 2881 */ 2882 bp->link_vars.line_speed = SPEED_10000; 2883 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 2884 2885 /* Only the PMF sets the HW */ 2886 if (bp->port.pmf) 2887 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2888 2889 /* init Event Queue */ 2890 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 2891 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 2892 eq_data.producer = bp->eq_prod; 2893 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 2894 eq_data.sb_id = DEF_SB_ID; 2895 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 2896} 2897 2898 2899static void bnx2x_e1h_disable(struct bnx2x *bp) 2900{ 2901 int port = BP_PORT(bp); 2902 2903 bnx2x_tx_disable(bp); 2904 2905 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 2906} 2907 2908static void bnx2x_e1h_enable(struct bnx2x *bp) 2909{ 2910 int port = BP_PORT(bp); 2911 2912 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 2913 2914 /* Tx queue should be only reenabled */ 2915 netif_tx_wake_all_queues(bp->dev); 2916 2917 /* 2918 * Should not call netif_carrier_on since it will be called if the link 2919 * is up when checking for link state 2920 */ 2921} 2922 2923/* called due to MCP event (on pmf): 2924 * reread new bandwidth configuration 2925 * configure FW 2926 * notify others function about the change 2927 */ 2928static inline void bnx2x_config_mf_bw(struct bnx2x *bp) 2929{ 2930 if (bp->link_vars.link_up) { 2931 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 2932 bnx2x_link_sync_notify(bp); 2933 } 2934 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2935} 2936 2937static inline void bnx2x_set_mf_bw(struct bnx2x *bp) 2938{ 2939 bnx2x_config_mf_bw(bp); 2940 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 2941} 2942 2943static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) 2944{ 2945 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); 2946 2947 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 2948 2949 /* 2950 * This is the only place besides the function initialization 2951 * where the bp->flags can change so it is done without any 2952 * locks 2953 */ 2954 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 2955 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n"); 2956 bp->flags |= MF_FUNC_DIS; 2957 2958 bnx2x_e1h_disable(bp); 2959 } else { 2960 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); 2961 bp->flags &= ~MF_FUNC_DIS; 2962 2963 bnx2x_e1h_enable(bp); 2964 } 2965 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 2966 } 2967 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 2968 bnx2x_config_mf_bw(bp); 2969 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 2970 } 2971 2972 /* Report results to MCP */ 2973 if (dcc_event) 2974 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); 2975 else 2976 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); 2977} 2978 2979/* must be called under the spq lock */ 2980static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 2981{ 2982 struct eth_spe *next_spe = bp->spq_prod_bd; 2983 2984 if (bp->spq_prod_bd == bp->spq_last_bd) { 2985 bp->spq_prod_bd = bp->spq; 2986 bp->spq_prod_idx = 0; 2987 DP(NETIF_MSG_TIMER, "end of spq\n"); 2988 } else { 2989 bp->spq_prod_bd++; 2990 bp->spq_prod_idx++; 2991 } 2992 return next_spe; 2993} 2994 2995/* must be called under the spq lock */ 2996static inline void bnx2x_sp_prod_update(struct bnx2x *bp) 2997{ 2998 int func = BP_FUNC(bp); 2999 3000 /* 3001 * Make sure that BD data is updated before writing the producer: 3002 * BD data is written to the memory, the producer is read from the 3003 * memory, thus we need a full memory barrier to ensure the ordering. 3004 */ 3005 mb(); 3006 3007 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3008 bp->spq_prod_idx); 3009 mmiowb(); 3010} 3011 3012/** 3013 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3014 * 3015 * @cmd: command to check 3016 * @cmd_type: command type 3017 */ 3018static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3019{ 3020 if ((cmd_type == NONE_CONNECTION_TYPE) || 3021 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3022 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3023 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3024 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3025 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3026 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3027 return true; 3028 else 3029 return false; 3030 3031} 3032 3033 3034/** 3035 * bnx2x_sp_post - place a single command on an SP ring 3036 * 3037 * @bp: driver handle 3038 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3039 * @cid: SW CID the command is related to 3040 * @data_hi: command private data address (high 32 bits) 3041 * @data_lo: command private data address (low 32 bits) 3042 * @cmd_type: command type (e.g. NONE, ETH) 3043 * 3044 * SP data is handled as if it's always an address pair, thus data fields are 3045 * not swapped to little endian in upper functions. Instead this function swaps 3046 * data as if it's two u32 fields. 3047 */ 3048int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3049 u32 data_hi, u32 data_lo, int cmd_type) 3050{ 3051 struct eth_spe *spe; 3052 u16 type; 3053 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3054 3055#ifdef BNX2X_STOP_ON_ERROR 3056 if (unlikely(bp->panic)) 3057 return -EIO; 3058#endif 3059 3060 spin_lock_bh(&bp->spq_lock); 3061 3062 if (common) { 3063 if (!atomic_read(&bp->eq_spq_left)) { 3064 BNX2X_ERR("BUG! EQ ring full!\n"); 3065 spin_unlock_bh(&bp->spq_lock); 3066 bnx2x_panic(); 3067 return -EBUSY; 3068 } 3069 } else if (!atomic_read(&bp->cq_spq_left)) { 3070 BNX2X_ERR("BUG! SPQ ring full!\n"); 3071 spin_unlock_bh(&bp->spq_lock); 3072 bnx2x_panic(); 3073 return -EBUSY; 3074 } 3075 3076 spe = bnx2x_sp_get_next(bp); 3077 3078 /* CID needs port number to be encoded int it */ 3079 spe->hdr.conn_and_cmd_data = 3080 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3081 HW_CID(bp, cid)); 3082 3083 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; 3084 3085 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3086 SPE_HDR_FUNCTION_ID); 3087 3088 spe->hdr.type = cpu_to_le16(type); 3089 3090 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3091 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3092 3093 /* 3094 * It's ok if the actual decrement is issued towards the memory 3095 * somewhere between the spin_lock and spin_unlock. Thus no 3096 * more explict memory barrier is needed. 3097 */ 3098 if (common) 3099 atomic_dec(&bp->eq_spq_left); 3100 else 3101 atomic_dec(&bp->cq_spq_left); 3102 3103 3104 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/, 3105 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) " 3106 "type(0x%x) left (CQ, EQ) (%x,%x)\n", 3107 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3108 (u32)(U64_LO(bp->spq_mapping) + 3109 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3110 HW_CID(bp, cid), data_hi, data_lo, type, 3111 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3112 3113 bnx2x_sp_prod_update(bp); 3114 spin_unlock_bh(&bp->spq_lock); 3115 return 0; 3116} 3117 3118/* acquire split MCP access lock register */ 3119static int bnx2x_acquire_alr(struct bnx2x *bp) 3120{ 3121 u32 j, val; 3122 int rc = 0; 3123 3124 might_sleep(); 3125 for (j = 0; j < 1000; j++) { 3126 val = (1UL << 31); 3127 REG_WR(bp, GRCBASE_MCP + 0x9c, val); 3128 val = REG_RD(bp, GRCBASE_MCP + 0x9c); 3129 if (val & (1L << 31)) 3130 break; 3131 3132 msleep(5); 3133 } 3134 if (!(val & (1L << 31))) { 3135 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3136 rc = -EBUSY; 3137 } 3138 3139 return rc; 3140} 3141 3142/* release split MCP access lock register */ 3143static void bnx2x_release_alr(struct bnx2x *bp) 3144{ 3145 REG_WR(bp, GRCBASE_MCP + 0x9c, 0); 3146} 3147 3148#define BNX2X_DEF_SB_ATT_IDX 0x0001 3149#define BNX2X_DEF_SB_IDX 0x0002 3150 3151static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3152{ 3153 struct host_sp_status_block *def_sb = bp->def_status_blk; 3154 u16 rc = 0; 3155 3156 barrier(); /* status block is written to by the chip */ 3157 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3158 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 3159 rc |= BNX2X_DEF_SB_ATT_IDX; 3160 } 3161 3162 if (bp->def_idx != def_sb->sp_sb.running_index) { 3163 bp->def_idx = def_sb->sp_sb.running_index; 3164 rc |= BNX2X_DEF_SB_IDX; 3165 } 3166 3167 /* Do not reorder: indecies reading should complete before handling */ 3168 barrier(); 3169 return rc; 3170} 3171 3172/* 3173 * slow path service functions 3174 */ 3175 3176static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 3177{ 3178 int port = BP_PORT(bp); 3179 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 3180 MISC_REG_AEU_MASK_ATTN_FUNC_0; 3181 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 3182 NIG_REG_MASK_INTERRUPT_PORT0; 3183 u32 aeu_mask; 3184 u32 nig_mask = 0; 3185 u32 reg_addr; 3186 3187 if (bp->attn_state & asserted) 3188 BNX2X_ERR("IGU ERROR\n"); 3189 3190 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3191 aeu_mask = REG_RD(bp, aeu_addr); 3192 3193 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 3194 aeu_mask, asserted); 3195 aeu_mask &= ~(asserted & 0x3ff); 3196 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 3197 3198 REG_WR(bp, aeu_addr, aeu_mask); 3199 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3200 3201 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 3202 bp->attn_state |= asserted; 3203 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 3204 3205 if (asserted & ATTN_HARD_WIRED_MASK) { 3206 if (asserted & ATTN_NIG_FOR_FUNC) { 3207 3208 bnx2x_acquire_phy_lock(bp); 3209 3210 /* save nig interrupt mask */ 3211 nig_mask = REG_RD(bp, nig_int_mask_addr); 3212 3213 /* If nig_mask is not set, no need to call the update 3214 * function. 3215 */ 3216 if (nig_mask) { 3217 REG_WR(bp, nig_int_mask_addr, 0); 3218 3219 bnx2x_link_attn(bp); 3220 } 3221 3222 /* handle unicore attn? */ 3223 } 3224 if (asserted & ATTN_SW_TIMER_4_FUNC) 3225 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 3226 3227 if (asserted & GPIO_2_FUNC) 3228 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 3229 3230 if (asserted & GPIO_3_FUNC) 3231 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 3232 3233 if (asserted & GPIO_4_FUNC) 3234 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 3235 3236 if (port == 0) { 3237 if (asserted & ATTN_GENERAL_ATTN_1) { 3238 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 3239 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 3240 } 3241 if (asserted & ATTN_GENERAL_ATTN_2) { 3242 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 3243 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 3244 } 3245 if (asserted & ATTN_GENERAL_ATTN_3) { 3246 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 3247 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 3248 } 3249 } else { 3250 if (asserted & ATTN_GENERAL_ATTN_4) { 3251 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 3252 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 3253 } 3254 if (asserted & ATTN_GENERAL_ATTN_5) { 3255 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 3256 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 3257 } 3258 if (asserted & ATTN_GENERAL_ATTN_6) { 3259 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 3260 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 3261 } 3262 } 3263 3264 } /* if hardwired */ 3265 3266 if (bp->common.int_block == INT_BLOCK_HC) 3267 reg_addr = (HC_REG_COMMAND_REG + port*32 + 3268 COMMAND_REG_ATTN_BITS_SET); 3269 else 3270 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 3271 3272 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 3273 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 3274 REG_WR(bp, reg_addr, asserted); 3275 3276 /* now set back the mask */ 3277 if (asserted & ATTN_NIG_FOR_FUNC) { 3278 REG_WR(bp, nig_int_mask_addr, nig_mask); 3279 bnx2x_release_phy_lock(bp); 3280 } 3281} 3282 3283static inline void bnx2x_fan_failure(struct bnx2x *bp) 3284{ 3285 int port = BP_PORT(bp); 3286 u32 ext_phy_config; 3287 /* mark the failure */ 3288 ext_phy_config = 3289 SHMEM_RD(bp, 3290 dev_info.port_hw_config[port].external_phy_config); 3291 3292 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 3293 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 3294 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 3295 ext_phy_config); 3296 3297 /* log the failure */ 3298 netdev_err(bp->dev, "Fan Failure on Network Controller has caused" 3299 " the driver to shutdown the card to prevent permanent" 3300 " damage. Please contact OEM Support for assistance\n"); 3301} 3302 3303static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 3304{ 3305 int port = BP_PORT(bp); 3306 int reg_offset; 3307 u32 val; 3308 3309 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 3310 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 3311 3312 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 3313 3314 val = REG_RD(bp, reg_offset); 3315 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 3316 REG_WR(bp, reg_offset, val); 3317 3318 BNX2X_ERR("SPIO5 hw attention\n"); 3319 3320 /* Fan failure attention */ 3321 bnx2x_hw_reset_phy(&bp->link_params); 3322 bnx2x_fan_failure(bp); 3323 } 3324 3325 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 3326 bnx2x_acquire_phy_lock(bp); 3327 bnx2x_handle_module_detect_int(&bp->link_params); 3328 bnx2x_release_phy_lock(bp); 3329 } 3330 3331 if (attn & HW_INTERRUT_ASSERT_SET_0) { 3332 3333 val = REG_RD(bp, reg_offset); 3334 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 3335 REG_WR(bp, reg_offset, val); 3336 3337 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 3338 (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); 3339 bnx2x_panic(); 3340 } 3341} 3342 3343static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 3344{ 3345 u32 val; 3346 3347 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 3348 3349 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 3350 BNX2X_ERR("DB hw attention 0x%x\n", val); 3351 /* DORQ discard attention */ 3352 if (val & 0x2) 3353 BNX2X_ERR("FATAL error from DORQ\n"); 3354 } 3355 3356 if (attn & HW_INTERRUT_ASSERT_SET_1) { 3357 3358 int port = BP_PORT(bp); 3359 int reg_offset; 3360 3361 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 3362 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 3363 3364 val = REG_RD(bp, reg_offset); 3365 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 3366 REG_WR(bp, reg_offset, val); 3367 3368 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 3369 (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); 3370 bnx2x_panic(); 3371 } 3372} 3373 3374static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 3375{ 3376 u32 val; 3377 3378 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 3379 3380 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 3381 BNX2X_ERR("CFC hw attention 0x%x\n", val); 3382 /* CFC error attention */ 3383 if (val & 0x2) 3384 BNX2X_ERR("FATAL error from CFC\n"); 3385 } 3386 3387 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 3388 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 3389 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 3390 /* RQ_USDMDP_FIFO_OVERFLOW */ 3391 if (val & 0x18000) 3392 BNX2X_ERR("FATAL error from PXP\n"); 3393 3394 if (!CHIP_IS_E1x(bp)) { 3395 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 3396 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 3397 } 3398 } 3399 3400 if (attn & HW_INTERRUT_ASSERT_SET_2) { 3401 3402 int port = BP_PORT(bp); 3403 int reg_offset; 3404 3405 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 3406 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 3407 3408 val = REG_RD(bp, reg_offset); 3409 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 3410 REG_WR(bp, reg_offset, val); 3411 3412 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 3413 (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); 3414 bnx2x_panic(); 3415 } 3416} 3417 3418static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 3419{ 3420 u32 val; 3421 3422 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 3423 3424 if (attn & BNX2X_PMF_LINK_ASSERT) { 3425 int func = BP_FUNC(bp); 3426 3427 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 3428 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 3429 func_mf_config[BP_ABS_FUNC(bp)].config); 3430 val = SHMEM_RD(bp, 3431 func_mb[BP_FW_MB_IDX(bp)].drv_status); 3432 if (val & DRV_STATUS_DCC_EVENT_MASK) 3433 bnx2x_dcc_event(bp, 3434 (val & DRV_STATUS_DCC_EVENT_MASK)); 3435 3436 if (val & DRV_STATUS_SET_MF_BW) 3437 bnx2x_set_mf_bw(bp); 3438 3439 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 3440 bnx2x_pmf_update(bp); 3441 3442 if (bp->port.pmf && 3443 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 3444 bp->dcbx_enabled > 0) 3445 /* start dcbx state machine */ 3446 bnx2x_dcbx_set_params(bp, 3447 BNX2X_DCBX_STATE_NEG_RECEIVED); 3448 if (bp->link_vars.periodic_flags & 3449 PERIODIC_FLAGS_LINK_EVENT) { 3450 /* sync with link */ 3451 bnx2x_acquire_phy_lock(bp); 3452 bp->link_vars.periodic_flags &= 3453 ~PERIODIC_FLAGS_LINK_EVENT; 3454 bnx2x_release_phy_lock(bp); 3455 if (IS_MF(bp)) 3456 bnx2x_link_sync_notify(bp); 3457 bnx2x_link_report(bp); 3458 } 3459 /* Always call it here: bnx2x_link_report() will 3460 * prevent the link indication duplication. 3461 */ 3462 bnx2x__link_status_update(bp); 3463 } else if (attn & BNX2X_MC_ASSERT_BITS) { 3464 3465 BNX2X_ERR("MC assert!\n"); 3466 bnx2x_mc_assert(bp); 3467 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 3468 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 3469 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 3470 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 3471 bnx2x_panic(); 3472 3473 } else if (attn & BNX2X_MCP_ASSERT) { 3474 3475 BNX2X_ERR("MCP assert!\n"); 3476 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 3477 bnx2x_fw_dump(bp); 3478 3479 } else 3480 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 3481 } 3482 3483 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 3484 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 3485 if (attn & BNX2X_GRC_TIMEOUT) { 3486 val = CHIP_IS_E1(bp) ? 0 : 3487 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 3488 BNX2X_ERR("GRC time-out 0x%08x\n", val); 3489 } 3490 if (attn & BNX2X_GRC_RSV) { 3491 val = CHIP_IS_E1(bp) ? 0 : 3492 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 3493 BNX2X_ERR("GRC reserved 0x%08x\n", val); 3494 } 3495 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 3496 } 3497} 3498 3499/* 3500 * Bits map: 3501 * 0-7 - Engine0 load counter. 3502 * 8-15 - Engine1 load counter. 3503 * 16 - Engine0 RESET_IN_PROGRESS bit. 3504 * 17 - Engine1 RESET_IN_PROGRESS bit. 3505 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 3506 * on the engine 3507 * 19 - Engine1 ONE_IS_LOADED. 3508 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 3509 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 3510 * just the one belonging to its engine). 3511 * 3512 */ 3513#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 3514 3515#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 3516#define BNX2X_PATH0_LOAD_CNT_SHIFT 0 3517#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 3518#define BNX2X_PATH1_LOAD_CNT_SHIFT 8 3519#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 3520#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 3521#define BNX2X_GLOBAL_RESET_BIT 0x00040000 3522 3523/* 3524 * Set the GLOBAL_RESET bit. 3525 * 3526 * Should be run under rtnl lock 3527 */ 3528void bnx2x_set_reset_global(struct bnx2x *bp) 3529{ 3530 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3531 3532 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 3533 barrier(); 3534 mmiowb(); 3535} 3536 3537/* 3538 * Clear the GLOBAL_RESET bit. 3539 * 3540 * Should be run under rtnl lock 3541 */ 3542static inline void bnx2x_clear_reset_global(struct bnx2x *bp) 3543{ 3544 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3545 3546 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 3547 barrier(); 3548 mmiowb(); 3549} 3550 3551/* 3552 * Checks the GLOBAL_RESET bit. 3553 * 3554 * should be run under rtnl lock 3555 */ 3556static inline bool bnx2x_reset_is_global(struct bnx2x *bp) 3557{ 3558 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3559 3560 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 3561 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 3562} 3563 3564/* 3565 * Clear RESET_IN_PROGRESS bit for the current engine. 3566 * 3567 * Should be run under rtnl lock 3568 */ 3569static inline void bnx2x_set_reset_done(struct bnx2x *bp) 3570{ 3571 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3572 u32 bit = BP_PATH(bp) ? 3573 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3574 3575 /* Clear the bit */ 3576 val &= ~bit; 3577 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3578 barrier(); 3579 mmiowb(); 3580} 3581 3582/* 3583 * Set RESET_IN_PROGRESS for the current engine. 3584 * 3585 * should be run under rtnl lock 3586 */ 3587void bnx2x_set_reset_in_progress(struct bnx2x *bp) 3588{ 3589 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3590 u32 bit = BP_PATH(bp) ? 3591 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3592 3593 /* Set the bit */ 3594 val |= bit; 3595 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3596 barrier(); 3597 mmiowb(); 3598} 3599 3600/* 3601 * Checks the RESET_IN_PROGRESS bit for the given engine. 3602 * should be run under rtnl lock 3603 */ 3604bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 3605{ 3606 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3607 u32 bit = engine ? 3608 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3609 3610 /* return false if bit is set */ 3611 return (val & bit) ? false : true; 3612} 3613 3614/* 3615 * Increment the load counter for the current engine. 3616 * 3617 * should be run under rtnl lock 3618 */ 3619void bnx2x_inc_load_cnt(struct bnx2x *bp) 3620{ 3621 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3622 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3623 BNX2X_PATH0_LOAD_CNT_MASK; 3624 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3625 BNX2X_PATH0_LOAD_CNT_SHIFT; 3626 3627 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3628 3629 /* get the current counter value */ 3630 val1 = (val & mask) >> shift; 3631 3632 /* increment... */ 3633 val1++; 3634 3635 /* clear the old value */ 3636 val &= ~mask; 3637 3638 /* set the new one */ 3639 val |= ((val1 << shift) & mask); 3640 3641 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3642 barrier(); 3643 mmiowb(); 3644} 3645 3646/** 3647 * bnx2x_dec_load_cnt - decrement the load counter 3648 * 3649 * @bp: driver handle 3650 * 3651 * Should be run under rtnl lock. 3652 * Decrements the load counter for the current engine. Returns 3653 * the new counter value. 3654 */ 3655u32 bnx2x_dec_load_cnt(struct bnx2x *bp) 3656{ 3657 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3658 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3659 BNX2X_PATH0_LOAD_CNT_MASK; 3660 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3661 BNX2X_PATH0_LOAD_CNT_SHIFT; 3662 3663 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3664 3665 /* get the current counter value */ 3666 val1 = (val & mask) >> shift; 3667 3668 /* decrement... */ 3669 val1--; 3670 3671 /* clear the old value */ 3672 val &= ~mask; 3673 3674 /* set the new one */ 3675 val |= ((val1 << shift) & mask); 3676 3677 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3678 barrier(); 3679 mmiowb(); 3680 3681 return val1; 3682} 3683 3684/* 3685 * Read the load counter for the current engine. 3686 * 3687 * should be run under rtnl lock 3688 */ 3689static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine) 3690{ 3691 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 3692 BNX2X_PATH0_LOAD_CNT_MASK); 3693 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3694 BNX2X_PATH0_LOAD_CNT_SHIFT); 3695 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3696 3697 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val); 3698 3699 val = (val & mask) >> shift; 3700 3701 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val); 3702 3703 return val; 3704} 3705 3706/* 3707 * Reset the load counter for the current engine. 3708 * 3709 * should be run under rtnl lock 3710 */ 3711static inline void bnx2x_clear_load_cnt(struct bnx2x *bp) 3712{ 3713 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3714 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3715 BNX2X_PATH0_LOAD_CNT_MASK); 3716 3717 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); 3718} 3719 3720static inline void _print_next_block(int idx, const char *blk) 3721{ 3722 pr_cont("%s%s", idx ? ", " : "", blk); 3723} 3724 3725static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, 3726 bool print) 3727{ 3728 int i = 0; 3729 u32 cur_bit = 0; 3730 for (i = 0; sig; i++) { 3731 cur_bit = ((u32)0x1 << i); 3732 if (sig & cur_bit) { 3733 switch (cur_bit) { 3734 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 3735 if (print) 3736 _print_next_block(par_num++, "BRB"); 3737 break; 3738 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 3739 if (print) 3740 _print_next_block(par_num++, "PARSER"); 3741 break; 3742 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 3743 if (print) 3744 _print_next_block(par_num++, "TSDM"); 3745 break; 3746 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 3747 if (print) 3748 _print_next_block(par_num++, 3749 "SEARCHER"); 3750 break; 3751 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 3752 if (print) 3753 _print_next_block(par_num++, "TCM"); 3754 break; 3755 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 3756 if (print) 3757 _print_next_block(par_num++, "TSEMI"); 3758 break; 3759 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 3760 if (print) 3761 _print_next_block(par_num++, "XPB"); 3762 break; 3763 } 3764 3765 /* Clear the bit */ 3766 sig &= ~cur_bit; 3767 } 3768 } 3769 3770 return par_num; 3771} 3772 3773static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, 3774 bool *global, bool print) 3775{ 3776 int i = 0; 3777 u32 cur_bit = 0; 3778 for (i = 0; sig; i++) { 3779 cur_bit = ((u32)0x1 << i); 3780 if (sig & cur_bit) { 3781 switch (cur_bit) { 3782 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 3783 if (print) 3784 _print_next_block(par_num++, "PBF"); 3785 break; 3786 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 3787 if (print) 3788 _print_next_block(par_num++, "QM"); 3789 break; 3790 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 3791 if (print) 3792 _print_next_block(par_num++, "TM"); 3793 break; 3794 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 3795 if (print) 3796 _print_next_block(par_num++, "XSDM"); 3797 break; 3798 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 3799 if (print) 3800 _print_next_block(par_num++, "XCM"); 3801 break; 3802 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 3803 if (print) 3804 _print_next_block(par_num++, "XSEMI"); 3805 break; 3806 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 3807 if (print) 3808 _print_next_block(par_num++, 3809 "DOORBELLQ"); 3810 break; 3811 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 3812 if (print) 3813 _print_next_block(par_num++, "NIG"); 3814 break; 3815 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 3816 if (print) 3817 _print_next_block(par_num++, 3818 "VAUX PCI CORE"); 3819 *global = true; 3820 break; 3821 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 3822 if (print) 3823 _print_next_block(par_num++, "DEBUG"); 3824 break; 3825 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 3826 if (print) 3827 _print_next_block(par_num++, "USDM"); 3828 break; 3829 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 3830 if (print) 3831 _print_next_block(par_num++, "UCM"); 3832 break; 3833 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 3834 if (print) 3835 _print_next_block(par_num++, "USEMI"); 3836 break; 3837 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 3838 if (print) 3839 _print_next_block(par_num++, "UPB"); 3840 break; 3841 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 3842 if (print) 3843 _print_next_block(par_num++, "CSDM"); 3844 break; 3845 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 3846 if (print) 3847 _print_next_block(par_num++, "CCM"); 3848 break; 3849 } 3850 3851 /* Clear the bit */ 3852 sig &= ~cur_bit; 3853 } 3854 } 3855 3856 return par_num; 3857} 3858 3859static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, 3860 bool print) 3861{ 3862 int i = 0; 3863 u32 cur_bit = 0; 3864 for (i = 0; sig; i++) { 3865 cur_bit = ((u32)0x1 << i); 3866 if (sig & cur_bit) { 3867 switch (cur_bit) { 3868 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 3869 if (print) 3870 _print_next_block(par_num++, "CSEMI"); 3871 break; 3872 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 3873 if (print) 3874 _print_next_block(par_num++, "PXP"); 3875 break; 3876 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 3877 if (print) 3878 _print_next_block(par_num++, 3879 "PXPPCICLOCKCLIENT"); 3880 break; 3881 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 3882 if (print) 3883 _print_next_block(par_num++, "CFC"); 3884 break; 3885 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 3886 if (print) 3887 _print_next_block(par_num++, "CDU"); 3888 break; 3889 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 3890 if (print) 3891 _print_next_block(par_num++, "DMAE"); 3892 break; 3893 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 3894 if (print) 3895 _print_next_block(par_num++, "IGU"); 3896 break; 3897 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 3898 if (print) 3899 _print_next_block(par_num++, "MISC"); 3900 break; 3901 } 3902 3903 /* Clear the bit */ 3904 sig &= ~cur_bit; 3905 } 3906 } 3907 3908 return par_num; 3909} 3910 3911static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, 3912 bool *global, bool print) 3913{ 3914 int i = 0; 3915 u32 cur_bit = 0; 3916 for (i = 0; sig; i++) { 3917 cur_bit = ((u32)0x1 << i); 3918 if (sig & cur_bit) { 3919 switch (cur_bit) { 3920 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 3921 if (print) 3922 _print_next_block(par_num++, "MCP ROM"); 3923 *global = true; 3924 break; 3925 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 3926 if (print) 3927 _print_next_block(par_num++, 3928 "MCP UMP RX"); 3929 *global = true; 3930 break; 3931 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 3932 if (print) 3933 _print_next_block(par_num++, 3934 "MCP UMP TX"); 3935 *global = true; 3936 break; 3937 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 3938 if (print) 3939 _print_next_block(par_num++, 3940 "MCP SCPAD"); 3941 *global = true; 3942 break; 3943 } 3944 3945 /* Clear the bit */ 3946 sig &= ~cur_bit; 3947 } 3948 } 3949 3950 return par_num; 3951} 3952 3953static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, 3954 bool print) 3955{ 3956 int i = 0; 3957 u32 cur_bit = 0; 3958 for (i = 0; sig; i++) { 3959 cur_bit = ((u32)0x1 << i); 3960 if (sig & cur_bit) { 3961 switch (cur_bit) { 3962 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 3963 if (print) 3964 _print_next_block(par_num++, "PGLUE_B"); 3965 break; 3966 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 3967 if (print) 3968 _print_next_block(par_num++, "ATC"); 3969 break; 3970 } 3971 3972 /* Clear the bit */ 3973 sig &= ~cur_bit; 3974 } 3975 } 3976 3977 return par_num; 3978} 3979 3980static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 3981 u32 *sig) 3982{ 3983 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 3984 (sig[1] & HW_PRTY_ASSERT_SET_1) || 3985 (sig[2] & HW_PRTY_ASSERT_SET_2) || 3986 (sig[3] & HW_PRTY_ASSERT_SET_3) || 3987 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 3988 int par_num = 0; 3989 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: " 3990 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x " 3991 "[4]:0x%08x\n", 3992 sig[0] & HW_PRTY_ASSERT_SET_0, 3993 sig[1] & HW_PRTY_ASSERT_SET_1, 3994 sig[2] & HW_PRTY_ASSERT_SET_2, 3995 sig[3] & HW_PRTY_ASSERT_SET_3, 3996 sig[4] & HW_PRTY_ASSERT_SET_4); 3997 if (print) 3998 netdev_err(bp->dev, 3999 "Parity errors detected in blocks: "); 4000 par_num = bnx2x_check_blocks_with_parity0( 4001 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); 4002 par_num = bnx2x_check_blocks_with_parity1( 4003 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); 4004 par_num = bnx2x_check_blocks_with_parity2( 4005 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); 4006 par_num = bnx2x_check_blocks_with_parity3( 4007 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); 4008 par_num = bnx2x_check_blocks_with_parity4( 4009 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); 4010 4011 if (print) 4012 pr_cont("\n"); 4013 4014 return true; 4015 } else 4016 return false; 4017} 4018 4019/** 4020 * bnx2x_chk_parity_attn - checks for parity attentions. 4021 * 4022 * @bp: driver handle 4023 * @global: true if there was a global attention 4024 * @print: show parity attention in syslog 4025 */ 4026bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 4027{ 4028 struct attn_route attn = { {0} }; 4029 int port = BP_PORT(bp); 4030 4031 attn.sig[0] = REG_RD(bp, 4032 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 4033 port*4); 4034 attn.sig[1] = REG_RD(bp, 4035 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 4036 port*4); 4037 attn.sig[2] = REG_RD(bp, 4038 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 4039 port*4); 4040 attn.sig[3] = REG_RD(bp, 4041 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 4042 port*4); 4043 4044 if (!CHIP_IS_E1x(bp)) 4045 attn.sig[4] = REG_RD(bp, 4046 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 4047 port*4); 4048 4049 return bnx2x_parity_attn(bp, global, print, attn.sig); 4050} 4051 4052 4053static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 4054{ 4055 u32 val; 4056 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 4057 4058 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 4059 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 4060 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 4061 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4062 "ADDRESS_ERROR\n"); 4063 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 4064 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4065 "INCORRECT_RCV_BEHAVIOR\n"); 4066 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 4067 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4068 "WAS_ERROR_ATTN\n"); 4069 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 4070 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4071 "VF_LENGTH_VIOLATION_ATTN\n"); 4072 if (val & 4073 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 4074 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4075 "VF_GRC_SPACE_VIOLATION_ATTN\n"); 4076 if (val & 4077 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 4078 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4079 "VF_MSIX_BAR_VIOLATION_ATTN\n"); 4080 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 4081 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4082 "TCPL_ERROR_ATTN\n"); 4083 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 4084 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4085 "TCPL_IN_TWO_RCBS_ATTN\n"); 4086 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 4087 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4088 "CSSNOOP_FIFO_OVERFLOW\n"); 4089 } 4090 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 4091 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 4092 BNX2X_ERR("ATC hw attention 0x%x\n", val); 4093 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 4094 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 4095 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 4096 BNX2X_ERR("ATC_ATC_INT_STS_REG" 4097 "_ATC_TCPL_TO_NOT_PEND\n"); 4098 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 4099 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4100 "ATC_GPA_MULTIPLE_HITS\n"); 4101 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 4102 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4103 "ATC_RCPL_TO_EMPTY_CNT\n"); 4104 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 4105 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 4106 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 4107 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4108 "ATC_IREQ_LESS_THAN_STU\n"); 4109 } 4110 4111 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4112 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 4113 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 4114 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4115 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 4116 } 4117 4118} 4119 4120static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 4121{ 4122 struct attn_route attn, *group_mask; 4123 int port = BP_PORT(bp); 4124 int index; 4125 u32 reg_addr; 4126 u32 val; 4127 u32 aeu_mask; 4128 bool global = false; 4129 4130 /* need to take HW lock because MCP or other port might also 4131 try to handle this event */ 4132 bnx2x_acquire_alr(bp); 4133 4134 if (bnx2x_chk_parity_attn(bp, &global, true)) { 4135#ifndef BNX2X_STOP_ON_ERROR 4136 bp->recovery_state = BNX2X_RECOVERY_INIT; 4137 schedule_delayed_work(&bp->sp_rtnl_task, 0); 4138 /* Disable HW interrupts */ 4139 bnx2x_int_disable(bp); 4140 /* In case of parity errors don't handle attentions so that 4141 * other function would "see" parity errors. 4142 */ 4143#else 4144 bnx2x_panic(); 4145#endif 4146 bnx2x_release_alr(bp); 4147 return; 4148 } 4149 4150 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 4151 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 4152 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 4153 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 4154 if (!CHIP_IS_E1x(bp)) 4155 attn.sig[4] = 4156 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 4157 else 4158 attn.sig[4] = 0; 4159 4160 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 4161 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 4162 4163 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4164 if (deasserted & (1 << index)) { 4165 group_mask = &bp->attn_group[index]; 4166 4167 DP(NETIF_MSG_HW, "group[%d]: %08x %08x " 4168 "%08x %08x %08x\n", 4169 index, 4170 group_mask->sig[0], group_mask->sig[1], 4171 group_mask->sig[2], group_mask->sig[3], 4172 group_mask->sig[4]); 4173 4174 bnx2x_attn_int_deasserted4(bp, 4175 attn.sig[4] & group_mask->sig[4]); 4176 bnx2x_attn_int_deasserted3(bp, 4177 attn.sig[3] & group_mask->sig[3]); 4178 bnx2x_attn_int_deasserted1(bp, 4179 attn.sig[1] & group_mask->sig[1]); 4180 bnx2x_attn_int_deasserted2(bp, 4181 attn.sig[2] & group_mask->sig[2]); 4182 bnx2x_attn_int_deasserted0(bp, 4183 attn.sig[0] & group_mask->sig[0]); 4184 } 4185 } 4186 4187 bnx2x_release_alr(bp); 4188 4189 if (bp->common.int_block == INT_BLOCK_HC) 4190 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4191 COMMAND_REG_ATTN_BITS_CLR); 4192 else 4193 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 4194 4195 val = ~deasserted; 4196 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 4197 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4198 REG_WR(bp, reg_addr, val); 4199 4200 if (~bp->attn_state & deasserted) 4201 BNX2X_ERR("IGU ERROR\n"); 4202 4203 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4204 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4205 4206 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4207 aeu_mask = REG_RD(bp, reg_addr); 4208 4209 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 4210 aeu_mask, deasserted); 4211 aeu_mask |= (deasserted & 0x3ff); 4212 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4213 4214 REG_WR(bp, reg_addr, aeu_mask); 4215 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4216 4217 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4218 bp->attn_state &= ~deasserted; 4219 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4220} 4221 4222static void bnx2x_attn_int(struct bnx2x *bp) 4223{ 4224 /* read local copy of bits */ 4225 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 4226 attn_bits); 4227 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 4228 attn_bits_ack); 4229 u32 attn_state = bp->attn_state; 4230 4231 /* look for changed bits */ 4232 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 4233 u32 deasserted = ~attn_bits & attn_ack & attn_state; 4234 4235 DP(NETIF_MSG_HW, 4236 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 4237 attn_bits, attn_ack, asserted, deasserted); 4238 4239 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 4240 BNX2X_ERR("BAD attention state\n"); 4241 4242 /* handle bits that were raised */ 4243 if (asserted) 4244 bnx2x_attn_int_asserted(bp, asserted); 4245 4246 if (deasserted) 4247 bnx2x_attn_int_deasserted(bp, deasserted); 4248} 4249 4250void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 4251 u16 index, u8 op, u8 update) 4252{ 4253 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 4254 4255 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 4256 igu_addr); 4257} 4258 4259static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 4260{ 4261 /* No memory barriers */ 4262 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 4263 mmiowb(); /* keep prod updates ordered */ 4264} 4265 4266#ifdef BCM_CNIC 4267static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 4268 union event_ring_elem *elem) 4269{ 4270 u8 err = elem->message.error; 4271 4272 if (!bp->cnic_eth_dev.starting_cid || 4273 (cid < bp->cnic_eth_dev.starting_cid && 4274 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 4275 return 1; 4276 4277 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 4278 4279 if (unlikely(err)) { 4280 4281 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 4282 cid); 4283 bnx2x_panic_dump(bp); 4284 } 4285 bnx2x_cnic_cfc_comp(bp, cid, err); 4286 return 0; 4287} 4288#endif 4289 4290static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 4291{ 4292 struct bnx2x_mcast_ramrod_params rparam; 4293 int rc; 4294 4295 memset(&rparam, 0, sizeof(rparam)); 4296 4297 rparam.mcast_obj = &bp->mcast_obj; 4298 4299 netif_addr_lock_bh(bp->dev); 4300 4301 /* Clear pending state for the last command */ 4302 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 4303 4304 /* If there are pending mcast commands - send them */ 4305 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 4306 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 4307 if (rc < 0) 4308 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 4309 rc); 4310 } 4311 4312 netif_addr_unlock_bh(bp->dev); 4313} 4314 4315static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp, 4316 union event_ring_elem *elem) 4317{ 4318 unsigned long ramrod_flags = 0; 4319 int rc = 0; 4320 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; 4321 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 4322 4323 /* Always push next commands out, don't wait here */ 4324 __set_bit(RAMROD_CONT, &ramrod_flags); 4325 4326 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 4327 case BNX2X_FILTER_MAC_PENDING: 4328#ifdef BCM_CNIC 4329 if (cid == BNX2X_ISCSI_ETH_CID) 4330 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 4331 else 4332#endif 4333 vlan_mac_obj = &bp->fp[cid].mac_obj; 4334 4335 break; 4336 vlan_mac_obj = &bp->fp[cid].mac_obj; 4337 4338 case BNX2X_FILTER_MCAST_PENDING: 4339 /* This is only relevant for 57710 where multicast MACs are 4340 * configured as unicast MACs using the same ramrod. 4341 */ 4342 bnx2x_handle_mcast_eqe(bp); 4343 return; 4344 default: 4345 BNX2X_ERR("Unsupported classification command: %d\n", 4346 elem->message.data.eth_event.echo); 4347 return; 4348 } 4349 4350 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 4351 4352 if (rc < 0) 4353 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 4354 else if (rc > 0) 4355 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 4356 4357} 4358 4359#ifdef BCM_CNIC 4360static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 4361#endif 4362 4363static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 4364{ 4365 netif_addr_lock_bh(bp->dev); 4366 4367 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 4368 4369 /* Send rx_mode command again if was requested */ 4370 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 4371 bnx2x_set_storm_rx_mode(bp); 4372#ifdef BCM_CNIC 4373 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 4374 &bp->sp_state)) 4375 bnx2x_set_iscsi_eth_rx_mode(bp, true); 4376 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 4377 &bp->sp_state)) 4378 bnx2x_set_iscsi_eth_rx_mode(bp, false); 4379#endif 4380 4381 netif_addr_unlock_bh(bp->dev); 4382} 4383 4384static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 4385 struct bnx2x *bp, u32 cid) 4386{ 4387 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 4388#ifdef BCM_CNIC 4389 if (cid == BNX2X_FCOE_ETH_CID) 4390 return &bnx2x_fcoe(bp, q_obj); 4391 else 4392#endif 4393 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj); 4394} 4395 4396static void bnx2x_eq_int(struct bnx2x *bp) 4397{ 4398 u16 hw_cons, sw_cons, sw_prod; 4399 union event_ring_elem *elem; 4400 u32 cid; 4401 u8 opcode; 4402 int spqe_cnt = 0; 4403 struct bnx2x_queue_sp_obj *q_obj; 4404 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 4405 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 4406 4407 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 4408 4409 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 4410 * when we get the the next-page we nned to adjust so the loop 4411 * condition below will be met. The next element is the size of a 4412 * regular element and hence incrementing by 1 4413 */ 4414 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 4415 hw_cons++; 4416 4417 /* This function may never run in parallel with itself for a 4418 * specific bp, thus there is no need in "paired" read memory 4419 * barrier here. 4420 */ 4421 sw_cons = bp->eq_cons; 4422 sw_prod = bp->eq_prod; 4423 4424 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 4425 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 4426 4427 for (; sw_cons != hw_cons; 4428 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 4429 4430 4431 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 4432 4433 cid = SW_CID(elem->message.data.cfc_del_event.cid); 4434 opcode = elem->message.opcode; 4435 4436 4437 /* handle eq element */ 4438 switch (opcode) { 4439 case EVENT_RING_OPCODE_STAT_QUERY: 4440 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n", 4441 bp->stats_comp++); 4442 /* nothing to do with stats comp */ 4443 goto next_spqe; 4444 4445 case EVENT_RING_OPCODE_CFC_DEL: 4446 /* handle according to cid range */ 4447 /* 4448 * we may want to verify here that the bp state is 4449 * HALTING 4450 */ 4451 DP(BNX2X_MSG_SP, 4452 "got delete ramrod for MULTI[%d]\n", cid); 4453#ifdef BCM_CNIC 4454 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 4455 goto next_spqe; 4456#endif 4457 q_obj = bnx2x_cid_to_q_obj(bp, cid); 4458 4459 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 4460 break; 4461 4462 4463 4464 goto next_spqe; 4465 4466 case EVENT_RING_OPCODE_STOP_TRAFFIC: 4467 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n"); 4468 if (f_obj->complete_cmd(bp, f_obj, 4469 BNX2X_F_CMD_TX_STOP)) 4470 break; 4471 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 4472 goto next_spqe; 4473 4474 case EVENT_RING_OPCODE_START_TRAFFIC: 4475 DP(BNX2X_MSG_SP, "got START TRAFFIC\n"); 4476 if (f_obj->complete_cmd(bp, f_obj, 4477 BNX2X_F_CMD_TX_START)) 4478 break; 4479 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 4480 goto next_spqe; 4481 case EVENT_RING_OPCODE_FUNCTION_START: 4482 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n"); 4483 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 4484 break; 4485 4486 goto next_spqe; 4487 4488 case EVENT_RING_OPCODE_FUNCTION_STOP: 4489 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n"); 4490 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 4491 break; 4492 4493 goto next_spqe; 4494 } 4495 4496 switch (opcode | bp->state) { 4497 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4498 BNX2X_STATE_OPEN): 4499 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4500 BNX2X_STATE_OPENING_WAIT4_PORT): 4501 cid = elem->message.data.eth_event.echo & 4502 BNX2X_SWCID_MASK; 4503 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 4504 cid); 4505 rss_raw->clear_pending(rss_raw); 4506 break; 4507 4508 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 4509 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 4510 case (EVENT_RING_OPCODE_SET_MAC | 4511 BNX2X_STATE_CLOSING_WAIT4_HALT): 4512 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4513 BNX2X_STATE_OPEN): 4514 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4515 BNX2X_STATE_DIAG): 4516 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4517 BNX2X_STATE_CLOSING_WAIT4_HALT): 4518 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); 4519 bnx2x_handle_classification_eqe(bp, elem); 4520 break; 4521 4522 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4523 BNX2X_STATE_OPEN): 4524 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4525 BNX2X_STATE_DIAG): 4526 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4527 BNX2X_STATE_CLOSING_WAIT4_HALT): 4528 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 4529 bnx2x_handle_mcast_eqe(bp); 4530 break; 4531 4532 case (EVENT_RING_OPCODE_FILTERS_RULES | 4533 BNX2X_STATE_OPEN): 4534 case (EVENT_RING_OPCODE_FILTERS_RULES | 4535 BNX2X_STATE_DIAG): 4536 case (EVENT_RING_OPCODE_FILTERS_RULES | 4537 BNX2X_STATE_CLOSING_WAIT4_HALT): 4538 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 4539 bnx2x_handle_rx_mode_eqe(bp); 4540 break; 4541 default: 4542 /* unknown event log error and continue */ 4543 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 4544 elem->message.opcode, bp->state); 4545 } 4546next_spqe: 4547 spqe_cnt++; 4548 } /* for */ 4549 4550 smp_mb__before_atomic_inc(); 4551 atomic_add(spqe_cnt, &bp->eq_spq_left); 4552 4553 bp->eq_cons = sw_cons; 4554 bp->eq_prod = sw_prod; 4555 /* Make sure that above mem writes were issued towards the memory */ 4556 smp_wmb(); 4557 4558 /* update producer */ 4559 bnx2x_update_eq_prod(bp, bp->eq_prod); 4560} 4561 4562static void bnx2x_sp_task(struct work_struct *work) 4563{ 4564 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 4565 u16 status; 4566 4567 status = bnx2x_update_dsb_idx(bp); 4568/* if (status == 0) */ 4569/* BNX2X_ERR("spurious slowpath interrupt!\n"); */ 4570 4571 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status); 4572 4573 /* HW attentions */ 4574 if (status & BNX2X_DEF_SB_ATT_IDX) { 4575 bnx2x_attn_int(bp); 4576 status &= ~BNX2X_DEF_SB_ATT_IDX; 4577 } 4578 4579 /* SP events: STAT_QUERY and others */ 4580 if (status & BNX2X_DEF_SB_IDX) { 4581#ifdef BCM_CNIC 4582 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 4583 4584 if ((!NO_FCOE(bp)) && 4585 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 4586 /* 4587 * Prevent local bottom-halves from running as 4588 * we are going to change the local NAPI list. 4589 */ 4590 local_bh_disable(); 4591 napi_schedule(&bnx2x_fcoe(bp, napi)); 4592 local_bh_enable(); 4593 } 4594#endif 4595 /* Handle EQ completions */ 4596 bnx2x_eq_int(bp); 4597 4598 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 4599 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 4600 4601 status &= ~BNX2X_DEF_SB_IDX; 4602 } 4603 4604 if (unlikely(status)) 4605 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 4606 status); 4607 4608 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 4609 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 4610} 4611 4612irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 4613{ 4614 struct net_device *dev = dev_instance; 4615 struct bnx2x *bp = netdev_priv(dev); 4616 4617 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 4618 IGU_INT_DISABLE, 0); 4619 4620#ifdef BNX2X_STOP_ON_ERROR 4621 if (unlikely(bp->panic)) 4622 return IRQ_HANDLED; 4623#endif 4624 4625#ifdef BCM_CNIC 4626 { 4627 struct cnic_ops *c_ops; 4628 4629 rcu_read_lock(); 4630 c_ops = rcu_dereference(bp->cnic_ops); 4631 if (c_ops) 4632 c_ops->cnic_handler(bp->cnic_data, NULL); 4633 rcu_read_unlock(); 4634 } 4635#endif 4636 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 4637 4638 return IRQ_HANDLED; 4639} 4640 4641/* end of slow path */ 4642 4643 4644void bnx2x_drv_pulse(struct bnx2x *bp) 4645{ 4646 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 4647 bp->fw_drv_pulse_wr_seq); 4648} 4649 4650 4651static void bnx2x_timer(unsigned long data) 4652{ 4653 u8 cos; 4654 struct bnx2x *bp = (struct bnx2x *) data; 4655 4656 if (!netif_running(bp->dev)) 4657 return; 4658 4659 if (poll) { 4660 struct bnx2x_fastpath *fp = &bp->fp[0]; 4661 4662 for_each_cos_in_tx_queue(fp, cos) 4663 bnx2x_tx_int(bp, &fp->txdata[cos]); 4664 bnx2x_rx_int(fp, 1000); 4665 } 4666 4667 if (!BP_NOMCP(bp)) { 4668 int mb_idx = BP_FW_MB_IDX(bp); 4669 u32 drv_pulse; 4670 u32 mcp_pulse; 4671 4672 ++bp->fw_drv_pulse_wr_seq; 4673 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 4674 /* TBD - add SYSTEM_TIME */ 4675 drv_pulse = bp->fw_drv_pulse_wr_seq; 4676 bnx2x_drv_pulse(bp); 4677 4678 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 4679 MCP_PULSE_SEQ_MASK); 4680 /* The delta between driver pulse and mcp response 4681 * should be 1 (before mcp response) or 0 (after mcp response) 4682 */ 4683 if ((drv_pulse != mcp_pulse) && 4684 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 4685 /* someone lost a heartbeat... */ 4686 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 4687 drv_pulse, mcp_pulse); 4688 } 4689 } 4690 4691 if (bp->state == BNX2X_STATE_OPEN) 4692 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 4693 4694 mod_timer(&bp->timer, jiffies + bp->current_interval); 4695} 4696 4697/* end of Statistics */ 4698 4699/* nic init */ 4700 4701/* 4702 * nic init service functions 4703 */ 4704 4705static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 4706{ 4707 u32 i; 4708 if (!(len%4) && !(addr%4)) 4709 for (i = 0; i < len; i += 4) 4710 REG_WR(bp, addr + i, fill); 4711 else 4712 for (i = 0; i < len; i++) 4713 REG_WR8(bp, addr + i, fill); 4714 4715} 4716 4717/* helper: writes FP SP data to FW - data_size in dwords */ 4718static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 4719 int fw_sb_id, 4720 u32 *sb_data_p, 4721 u32 data_size) 4722{ 4723 int index; 4724 for (index = 0; index < data_size; index++) 4725 REG_WR(bp, BAR_CSTRORM_INTMEM + 4726 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 4727 sizeof(u32)*index, 4728 *(sb_data_p + index)); 4729} 4730 4731static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 4732{ 4733 u32 *sb_data_p; 4734 u32 data_size = 0; 4735 struct hc_status_block_data_e2 sb_data_e2; 4736 struct hc_status_block_data_e1x sb_data_e1x; 4737 4738 /* disable the function first */ 4739 if (!CHIP_IS_E1x(bp)) { 4740 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 4741 sb_data_e2.common.state = SB_DISABLED; 4742 sb_data_e2.common.p_func.vf_valid = false; 4743 sb_data_p = (u32 *)&sb_data_e2; 4744 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 4745 } else { 4746 memset(&sb_data_e1x, 0, 4747 sizeof(struct hc_status_block_data_e1x)); 4748 sb_data_e1x.common.state = SB_DISABLED; 4749 sb_data_e1x.common.p_func.vf_valid = false; 4750 sb_data_p = (u32 *)&sb_data_e1x; 4751 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 4752 } 4753 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 4754 4755 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4756 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 4757 CSTORM_STATUS_BLOCK_SIZE); 4758 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4759 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 4760 CSTORM_SYNC_BLOCK_SIZE); 4761} 4762 4763/* helper: writes SP SB data to FW */ 4764static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 4765 struct hc_sp_status_block_data *sp_sb_data) 4766{ 4767 int func = BP_FUNC(bp); 4768 int i; 4769 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 4770 REG_WR(bp, BAR_CSTRORM_INTMEM + 4771 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 4772 i*sizeof(u32), 4773 *((u32 *)sp_sb_data + i)); 4774} 4775 4776static inline void bnx2x_zero_sp_sb(struct bnx2x *bp) 4777{ 4778 int func = BP_FUNC(bp); 4779 struct hc_sp_status_block_data sp_sb_data; 4780 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 4781 4782 sp_sb_data.state = SB_DISABLED; 4783 sp_sb_data.p_func.vf_valid = false; 4784 4785 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 4786 4787 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4788 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 4789 CSTORM_SP_STATUS_BLOCK_SIZE); 4790 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4791 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 4792 CSTORM_SP_SYNC_BLOCK_SIZE); 4793 4794} 4795 4796 4797static inline 4798void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 4799 int igu_sb_id, int igu_seg_id) 4800{ 4801 hc_sm->igu_sb_id = igu_sb_id; 4802 hc_sm->igu_seg_id = igu_seg_id; 4803 hc_sm->timer_value = 0xFF; 4804 hc_sm->time_to_expire = 0xFFFFFFFF; 4805} 4806 4807static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 4808 u8 vf_valid, int fw_sb_id, int igu_sb_id) 4809{ 4810 int igu_seg_id; 4811 4812 struct hc_status_block_data_e2 sb_data_e2; 4813 struct hc_status_block_data_e1x sb_data_e1x; 4814 struct hc_status_block_sm *hc_sm_p; 4815 int data_size; 4816 u32 *sb_data_p; 4817 4818 if (CHIP_INT_MODE_IS_BC(bp)) 4819 igu_seg_id = HC_SEG_ACCESS_NORM; 4820 else 4821 igu_seg_id = IGU_SEG_ACCESS_NORM; 4822 4823 bnx2x_zero_fp_sb(bp, fw_sb_id); 4824 4825 if (!CHIP_IS_E1x(bp)) { 4826 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 4827 sb_data_e2.common.state = SB_ENABLED; 4828 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 4829 sb_data_e2.common.p_func.vf_id = vfid; 4830 sb_data_e2.common.p_func.vf_valid = vf_valid; 4831 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 4832 sb_data_e2.common.same_igu_sb_1b = true; 4833 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 4834 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 4835 hc_sm_p = sb_data_e2.common.state_machine; 4836 sb_data_p = (u32 *)&sb_data_e2; 4837 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 4838 } else { 4839 memset(&sb_data_e1x, 0, 4840 sizeof(struct hc_status_block_data_e1x)); 4841 sb_data_e1x.common.state = SB_ENABLED; 4842 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 4843 sb_data_e1x.common.p_func.vf_id = 0xff; 4844 sb_data_e1x.common.p_func.vf_valid = false; 4845 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 4846 sb_data_e1x.common.same_igu_sb_1b = true; 4847 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 4848 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 4849 hc_sm_p = sb_data_e1x.common.state_machine; 4850 sb_data_p = (u32 *)&sb_data_e1x; 4851 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 4852 } 4853 4854 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 4855 igu_sb_id, igu_seg_id); 4856 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 4857 igu_sb_id, igu_seg_id); 4858 4859 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id); 4860 4861 /* write indecies to HW */ 4862 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 4863} 4864 4865static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 4866 u16 tx_usec, u16 rx_usec) 4867{ 4868 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 4869 false, rx_usec); 4870 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 4871 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 4872 tx_usec); 4873 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 4874 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 4875 tx_usec); 4876 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 4877 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 4878 tx_usec); 4879} 4880 4881static void bnx2x_init_def_sb(struct bnx2x *bp) 4882{ 4883 struct host_sp_status_block *def_sb = bp->def_status_blk; 4884 dma_addr_t mapping = bp->def_status_blk_mapping; 4885 int igu_sp_sb_index; 4886 int igu_seg_id; 4887 int port = BP_PORT(bp); 4888 int func = BP_FUNC(bp); 4889 int reg_offset; 4890 u64 section; 4891 int index; 4892 struct hc_sp_status_block_data sp_sb_data; 4893 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 4894 4895 if (CHIP_INT_MODE_IS_BC(bp)) { 4896 igu_sp_sb_index = DEF_SB_IGU_ID; 4897 igu_seg_id = HC_SEG_ACCESS_DEF; 4898 } else { 4899 igu_sp_sb_index = bp->igu_dsb_id; 4900 igu_seg_id = IGU_SEG_ACCESS_DEF; 4901 } 4902 4903 /* ATTN */ 4904 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 4905 atten_status_block); 4906 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 4907 4908 bp->attn_state = 0; 4909 4910 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 4911 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 4912 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4913 int sindex; 4914 /* take care of sig[0]..sig[4] */ 4915 for (sindex = 0; sindex < 4; sindex++) 4916 bp->attn_group[index].sig[sindex] = 4917 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 4918 4919 if (!CHIP_IS_E1x(bp)) 4920 /* 4921 * enable5 is separate from the rest of the registers, 4922 * and therefore the address skip is 4 4923 * and not 16 between the different groups 4924 */ 4925 bp->attn_group[index].sig[4] = REG_RD(bp, 4926 reg_offset + 0x10 + 0x4*index); 4927 else 4928 bp->attn_group[index].sig[4] = 0; 4929 } 4930 4931 if (bp->common.int_block == INT_BLOCK_HC) { 4932 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 4933 HC_REG_ATTN_MSG0_ADDR_L); 4934 4935 REG_WR(bp, reg_offset, U64_LO(section)); 4936 REG_WR(bp, reg_offset + 4, U64_HI(section)); 4937 } else if (!CHIP_IS_E1x(bp)) { 4938 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 4939 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 4940 } 4941 4942 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 4943 sp_sb); 4944 4945 bnx2x_zero_sp_sb(bp); 4946 4947 sp_sb_data.state = SB_ENABLED; 4948 sp_sb_data.host_sb_addr.lo = U64_LO(section); 4949 sp_sb_data.host_sb_addr.hi = U64_HI(section); 4950 sp_sb_data.igu_sb_id = igu_sp_sb_index; 4951 sp_sb_data.igu_seg_id = igu_seg_id; 4952 sp_sb_data.p_func.pf_id = func; 4953 sp_sb_data.p_func.vnic_id = BP_VN(bp); 4954 sp_sb_data.p_func.vf_id = 0xff; 4955 4956 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 4957 4958 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 4959} 4960 4961void bnx2x_update_coalesce(struct bnx2x *bp) 4962{ 4963 int i; 4964 4965 for_each_eth_queue(bp, i) 4966 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 4967 bp->tx_ticks, bp->rx_ticks); 4968} 4969 4970static void bnx2x_init_sp_ring(struct bnx2x *bp) 4971{ 4972 spin_lock_init(&bp->spq_lock); 4973 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 4974 4975 bp->spq_prod_idx = 0; 4976 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 4977 bp->spq_prod_bd = bp->spq; 4978 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 4979} 4980 4981static void bnx2x_init_eq_ring(struct bnx2x *bp) 4982{ 4983 int i; 4984 for (i = 1; i <= NUM_EQ_PAGES; i++) { 4985 union event_ring_elem *elem = 4986 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 4987 4988 elem->next_page.addr.hi = 4989 cpu_to_le32(U64_HI(bp->eq_mapping + 4990 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 4991 elem->next_page.addr.lo = 4992 cpu_to_le32(U64_LO(bp->eq_mapping + 4993 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 4994 } 4995 bp->eq_cons = 0; 4996 bp->eq_prod = NUM_EQ_DESC; 4997 bp->eq_cons_sb = BNX2X_EQ_INDEX; 4998 /* we want a warning message before it gets rought... */ 4999 atomic_set(&bp->eq_spq_left, 5000 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 5001} 5002 5003 5004/* called with netif_addr_lock_bh() */ 5005void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 5006 unsigned long rx_mode_flags, 5007 unsigned long rx_accept_flags, 5008 unsigned long tx_accept_flags, 5009 unsigned long ramrod_flags) 5010{ 5011 struct bnx2x_rx_mode_ramrod_params ramrod_param; 5012 int rc; 5013 5014 memset(&ramrod_param, 0, sizeof(ramrod_param)); 5015 5016 /* Prepare ramrod parameters */ 5017 ramrod_param.cid = 0; 5018 ramrod_param.cl_id = cl_id; 5019 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 5020 ramrod_param.func_id = BP_FUNC(bp); 5021 5022 ramrod_param.pstate = &bp->sp_state; 5023 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 5024 5025 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 5026 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 5027 5028 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5029 5030 ramrod_param.ramrod_flags = ramrod_flags; 5031 ramrod_param.rx_mode_flags = rx_mode_flags; 5032 5033 ramrod_param.rx_accept_flags = rx_accept_flags; 5034 ramrod_param.tx_accept_flags = tx_accept_flags; 5035 5036 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 5037 if (rc < 0) { 5038 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 5039 return; 5040 } 5041} 5042 5043/* called with netif_addr_lock_bh() */ 5044void bnx2x_set_storm_rx_mode(struct bnx2x *bp) 5045{ 5046 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 5047 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 5048 5049#ifdef BCM_CNIC 5050 if (!NO_FCOE(bp)) 5051 5052 /* Configure rx_mode of FCoE Queue */ 5053 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 5054#endif 5055 5056 switch (bp->rx_mode) { 5057 case BNX2X_RX_MODE_NONE: 5058 /* 5059 * 'drop all' supersedes any accept flags that may have been 5060 * passed to the function. 5061 */ 5062 break; 5063 case BNX2X_RX_MODE_NORMAL: 5064 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5065 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); 5066 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5067 5068 /* internal switching mode */ 5069 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5070 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); 5071 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5072 5073 break; 5074 case BNX2X_RX_MODE_ALLMULTI: 5075 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5076 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5077 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5078 5079 /* internal switching mode */ 5080 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5081 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5082 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5083 5084 break; 5085 case BNX2X_RX_MODE_PROMISC: 5086 /* According to deffinition of SI mode, iface in promisc mode 5087 * should receive matched and unmatched (in resolution of port) 5088 * unicast packets. 5089 */ 5090 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); 5091 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5092 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5093 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5094 5095 /* internal switching mode */ 5096 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5097 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5098 5099 if (IS_MF_SI(bp)) 5100 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); 5101 else 5102 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5103 5104 break; 5105 default: 5106 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); 5107 return; 5108 } 5109 5110 if (bp->rx_mode != BNX2X_RX_MODE_NONE) { 5111 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); 5112 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); 5113 } 5114 5115 __set_bit(RAMROD_RX, &ramrod_flags); 5116 __set_bit(RAMROD_TX, &ramrod_flags); 5117 5118 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, 5119 tx_accept_flags, ramrod_flags); 5120} 5121 5122static void bnx2x_init_internal_common(struct bnx2x *bp) 5123{ 5124 int i; 5125 5126 if (IS_MF_SI(bp)) 5127 /* 5128 * In switch independent mode, the TSTORM needs to accept 5129 * packets that failed classification, since approximate match 5130 * mac addresses aren't written to NIG LLH 5131 */ 5132 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5133 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); 5134 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ 5135 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5136 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); 5137 5138 /* Zero this manually as its initialization is 5139 currently missing in the initTool */ 5140 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 5141 REG_WR(bp, BAR_USTRORM_INTMEM + 5142 USTORM_AGG_DATA_OFFSET + i * 4, 0); 5143 if (!CHIP_IS_E1x(bp)) { 5144 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 5145 CHIP_INT_MODE_IS_BC(bp) ? 5146 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 5147 } 5148} 5149 5150static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 5151{ 5152 switch (load_code) { 5153 case FW_MSG_CODE_DRV_LOAD_COMMON: 5154 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5155 bnx2x_init_internal_common(bp); 5156 /* no break */ 5157 5158 case FW_MSG_CODE_DRV_LOAD_PORT: 5159 /* nothing to do */ 5160 /* no break */ 5161 5162 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5163 /* internal memory per function is 5164 initialized inside bnx2x_pf_init */ 5165 break; 5166 5167 default: 5168 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5169 break; 5170 } 5171} 5172 5173static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 5174{ 5175 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; 5176} 5177 5178static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 5179{ 5180 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; 5181} 5182 5183static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 5184{ 5185 if (CHIP_IS_E1x(fp->bp)) 5186 return BP_L_ID(fp->bp) + fp->index; 5187 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 5188 return bnx2x_fp_igu_sb_id(fp); 5189} 5190 5191static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 5192{ 5193 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 5194 u8 cos; 5195 unsigned long q_type = 0; 5196 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 5197 5198 fp->cid = fp_idx; 5199 fp->cl_id = bnx2x_fp_cl_id(fp); 5200 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 5201 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 5202 /* qZone id equals to FW (per path) client id */ 5203 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 5204 5205 /* init shortcut */ 5206 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 5207 /* Setup SB indicies */ 5208 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 5209 5210 /* Configure Queue State object */ 5211 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 5212 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 5213 5214 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 5215 5216 /* init tx data */ 5217 for_each_cos_in_tx_queue(fp, cos) { 5218 bnx2x_init_txdata(bp, &fp->txdata[cos], 5219 CID_COS_TO_TX_ONLY_CID(fp->cid, cos), 5220 FP_COS_TO_TXQ(fp, cos), 5221 BNX2X_TX_SB_INDEX_BASE + cos); 5222 cids[cos] = fp->txdata[cos].cid; 5223 } 5224 5225 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos, 5226 BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 5227 bnx2x_sp_mapping(bp, q_rdata), q_type); 5228 5229 /** 5230 * Configure classification DBs: Always enable Tx switching 5231 */ 5232 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 5233 5234 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) " 5235 "cl_id %d fw_sb %d igu_sb %d\n", 5236 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 5237 fp->igu_sb_id); 5238 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 5239 fp->fw_sb_id, fp->igu_sb_id); 5240 5241 bnx2x_update_fpsb_idx(fp); 5242} 5243 5244void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) 5245{ 5246 int i; 5247 5248 for_each_eth_queue(bp, i) 5249 bnx2x_init_eth_fp(bp, i); 5250#ifdef BCM_CNIC 5251 if (!NO_FCOE(bp)) 5252 bnx2x_init_fcoe_fp(bp); 5253 5254 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 5255 BNX2X_VF_ID_INVALID, false, 5256 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 5257 5258#endif 5259 5260 /* Initialize MOD_ABS interrupts */ 5261 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 5262 bp->common.shmem_base, bp->common.shmem2_base, 5263 BP_PORT(bp)); 5264 /* ensure status block indices were read */ 5265 rmb(); 5266 5267 bnx2x_init_def_sb(bp); 5268 bnx2x_update_dsb_idx(bp); 5269 bnx2x_init_rx_rings(bp); 5270 bnx2x_init_tx_rings(bp); 5271 bnx2x_init_sp_ring(bp); 5272 bnx2x_init_eq_ring(bp); 5273 bnx2x_init_internal(bp, load_code); 5274 bnx2x_pf_init(bp); 5275 bnx2x_stats_init(bp); 5276 5277 /* flush all before enabling interrupts */ 5278 mb(); 5279 mmiowb(); 5280 5281 bnx2x_int_enable(bp); 5282 5283 /* Check for SPIO5 */ 5284 bnx2x_attn_int_deasserted0(bp, 5285 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 5286 AEU_INPUTS_ATTN_BITS_SPIO5); 5287} 5288 5289/* end of nic init */ 5290 5291/* 5292 * gzip service functions 5293 */ 5294 5295static int bnx2x_gunzip_init(struct bnx2x *bp) 5296{ 5297 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 5298 &bp->gunzip_mapping, GFP_KERNEL); 5299 if (bp->gunzip_buf == NULL) 5300 goto gunzip_nomem1; 5301 5302 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 5303 if (bp->strm == NULL) 5304 goto gunzip_nomem2; 5305 5306 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 5307 if (bp->strm->workspace == NULL) 5308 goto gunzip_nomem3; 5309 5310 return 0; 5311 5312gunzip_nomem3: 5313 kfree(bp->strm); 5314 bp->strm = NULL; 5315 5316gunzip_nomem2: 5317 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5318 bp->gunzip_mapping); 5319 bp->gunzip_buf = NULL; 5320 5321gunzip_nomem1: 5322 netdev_err(bp->dev, "Cannot allocate firmware buffer for" 5323 " un-compression\n"); 5324 return -ENOMEM; 5325} 5326 5327static void bnx2x_gunzip_end(struct bnx2x *bp) 5328{ 5329 if (bp->strm) { 5330 vfree(bp->strm->workspace); 5331 kfree(bp->strm); 5332 bp->strm = NULL; 5333 } 5334 5335 if (bp->gunzip_buf) { 5336 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5337 bp->gunzip_mapping); 5338 bp->gunzip_buf = NULL; 5339 } 5340} 5341 5342static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 5343{ 5344 int n, rc; 5345 5346 /* check gzip header */ 5347 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 5348 BNX2X_ERR("Bad gzip header\n"); 5349 return -EINVAL; 5350 } 5351 5352 n = 10; 5353 5354#define FNAME 0x8 5355 5356 if (zbuf[3] & FNAME) 5357 while ((zbuf[n++] != 0) && (n < len)); 5358 5359 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 5360 bp->strm->avail_in = len - n; 5361 bp->strm->next_out = bp->gunzip_buf; 5362 bp->strm->avail_out = FW_BUF_SIZE; 5363 5364 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 5365 if (rc != Z_OK) 5366 return rc; 5367 5368 rc = zlib_inflate(bp->strm, Z_FINISH); 5369 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 5370 netdev_err(bp->dev, "Firmware decompression error: %s\n", 5371 bp->strm->msg); 5372 5373 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 5374 if (bp->gunzip_outlen & 0x3) 5375 netdev_err(bp->dev, "Firmware decompression error:" 5376 " gunzip_outlen (%d) not aligned\n", 5377 bp->gunzip_outlen); 5378 bp->gunzip_outlen >>= 2; 5379 5380 zlib_inflateEnd(bp->strm); 5381 5382 if (rc == Z_STREAM_END) 5383 return 0; 5384 5385 return rc; 5386} 5387 5388/* nic load/unload */ 5389 5390/* 5391 * General service functions 5392 */ 5393 5394/* send a NIG loopback debug packet */ 5395static void bnx2x_lb_pckt(struct bnx2x *bp) 5396{ 5397 u32 wb_write[3]; 5398 5399 /* Ethernet source and destination addresses */ 5400 wb_write[0] = 0x55555555; 5401 wb_write[1] = 0x55555555; 5402 wb_write[2] = 0x20; /* SOP */ 5403 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5404 5405 /* NON-IP protocol */ 5406 wb_write[0] = 0x09000000; 5407 wb_write[1] = 0x55555555; 5408 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 5409 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5410} 5411 5412/* some of the internal memories 5413 * are not directly readable from the driver 5414 * to test them we send debug packets 5415 */ 5416static int bnx2x_int_mem_test(struct bnx2x *bp) 5417{ 5418 int factor; 5419 int count, i; 5420 u32 val = 0; 5421 5422 if (CHIP_REV_IS_FPGA(bp)) 5423 factor = 120; 5424 else if (CHIP_REV_IS_EMUL(bp)) 5425 factor = 200; 5426 else 5427 factor = 1; 5428 5429 /* Disable inputs of parser neighbor blocks */ 5430 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5431 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5432 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5433 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5434 5435 /* Write 0 to parser credits for CFC search request */ 5436 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5437 5438 /* send Ethernet packet */ 5439 bnx2x_lb_pckt(bp); 5440 5441 /* TODO do i reset NIG statistic? */ 5442 /* Wait until NIG register shows 1 packet of size 0x10 */ 5443 count = 1000 * factor; 5444 while (count) { 5445 5446 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5447 val = *bnx2x_sp(bp, wb_data[0]); 5448 if (val == 0x10) 5449 break; 5450 5451 msleep(10); 5452 count--; 5453 } 5454 if (val != 0x10) { 5455 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5456 return -1; 5457 } 5458 5459 /* Wait until PRS register shows 1 packet */ 5460 count = 1000 * factor; 5461 while (count) { 5462 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5463 if (val == 1) 5464 break; 5465 5466 msleep(10); 5467 count--; 5468 } 5469 if (val != 0x1) { 5470 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5471 return -2; 5472 } 5473 5474 /* Reset and init BRB, PRS */ 5475 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5476 msleep(50); 5477 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5478 msleep(50); 5479 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5480 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5481 5482 DP(NETIF_MSG_HW, "part2\n"); 5483 5484 /* Disable inputs of parser neighbor blocks */ 5485 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5486 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5487 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5488 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5489 5490 /* Write 0 to parser credits for CFC search request */ 5491 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5492 5493 /* send 10 Ethernet packets */ 5494 for (i = 0; i < 10; i++) 5495 bnx2x_lb_pckt(bp); 5496 5497 /* Wait until NIG register shows 10 + 1 5498 packets of size 11*0x10 = 0xb0 */ 5499 count = 1000 * factor; 5500 while (count) { 5501 5502 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5503 val = *bnx2x_sp(bp, wb_data[0]); 5504 if (val == 0xb0) 5505 break; 5506 5507 msleep(10); 5508 count--; 5509 } 5510 if (val != 0xb0) { 5511 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5512 return -3; 5513 } 5514 5515 /* Wait until PRS register shows 2 packets */ 5516 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5517 if (val != 2) 5518 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5519 5520 /* Write 1 to parser credits for CFC search request */ 5521 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 5522 5523 /* Wait until PRS register shows 3 packets */ 5524 msleep(10 * factor); 5525 /* Wait until NIG register shows 1 packet of size 0x10 */ 5526 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5527 if (val != 3) 5528 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5529 5530 /* clear NIG EOP FIFO */ 5531 for (i = 0; i < 11; i++) 5532 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 5533 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 5534 if (val != 1) { 5535 BNX2X_ERR("clear of NIG failed\n"); 5536 return -4; 5537 } 5538 5539 /* Reset and init BRB, PRS, NIG */ 5540 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5541 msleep(50); 5542 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5543 msleep(50); 5544 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5545 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5546#ifndef BCM_CNIC 5547 /* set NIC mode */ 5548 REG_WR(bp, PRS_REG_NIC_MODE, 1); 5549#endif 5550 5551 /* Enable inputs of parser neighbor blocks */ 5552 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 5553 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 5554 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 5555 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 5556 5557 DP(NETIF_MSG_HW, "done\n"); 5558 5559 return 0; /* OK */ 5560} 5561 5562static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 5563{ 5564 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 5565 if (!CHIP_IS_E1x(bp)) 5566 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 5567 else 5568 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 5569 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 5570 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 5571 /* 5572 * mask read length error interrupts in brb for parser 5573 * (parsing unit and 'checksum and crc' unit) 5574 * these errors are legal (PU reads fixed length and CAC can cause 5575 * read length error on truncated packets) 5576 */ 5577 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 5578 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 5579 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 5580 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 5581 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 5582 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 5583/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 5584/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 5585 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 5586 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 5587 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 5588/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 5589/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 5590 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 5591 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 5592 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 5593 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 5594/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 5595/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 5596 5597 if (CHIP_REV_IS_FPGA(bp)) 5598 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); 5599 else if (!CHIP_IS_E1x(bp)) 5600 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 5601 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF 5602 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT 5603 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN 5604 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED 5605 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); 5606 else 5607 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); 5608 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 5609 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 5610 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 5611/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 5612 5613 if (!CHIP_IS_E1x(bp)) 5614 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 5615 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 5616 5617 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 5618 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 5619/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 5620 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 5621} 5622 5623static void bnx2x_reset_common(struct bnx2x *bp) 5624{ 5625 u32 val = 0x1400; 5626 5627 /* reset_common */ 5628 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 5629 0xd3ffff7f); 5630 5631 if (CHIP_IS_E3(bp)) { 5632 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 5633 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 5634 } 5635 5636 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); 5637} 5638 5639static void bnx2x_setup_dmae(struct bnx2x *bp) 5640{ 5641 bp->dmae_ready = 0; 5642 spin_lock_init(&bp->dmae_lock); 5643} 5644 5645static void bnx2x_init_pxp(struct bnx2x *bp) 5646{ 5647 u16 devctl; 5648 int r_order, w_order; 5649 5650 pci_read_config_word(bp->pdev, 5651 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); 5652 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); 5653 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 5654 if (bp->mrrs == -1) 5655 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); 5656 else { 5657 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); 5658 r_order = bp->mrrs; 5659 } 5660 5661 bnx2x_init_pxp_arb(bp, r_order, w_order); 5662} 5663 5664static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 5665{ 5666 int is_required; 5667 u32 val; 5668 int port; 5669 5670 if (BP_NOMCP(bp)) 5671 return; 5672 5673 is_required = 0; 5674 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 5675 SHARED_HW_CFG_FAN_FAILURE_MASK; 5676 5677 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) 5678 is_required = 1; 5679 5680 /* 5681 * The fan failure mechanism is usually related to the PHY type since 5682 * the power consumption of the board is affected by the PHY. Currently, 5683 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 5684 */ 5685 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 5686 for (port = PORT_0; port < PORT_MAX; port++) { 5687 is_required |= 5688 bnx2x_fan_failure_det_req( 5689 bp, 5690 bp->common.shmem_base, 5691 bp->common.shmem2_base, 5692 port); 5693 } 5694 5695 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 5696 5697 if (is_required == 0) 5698 return; 5699 5700 /* Fan failure is indicated by SPIO 5 */ 5701 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, 5702 MISC_REGISTERS_SPIO_INPUT_HI_Z); 5703 5704 /* set to active low mode */ 5705 val = REG_RD(bp, MISC_REG_SPIO_INT); 5706 val |= ((1 << MISC_REGISTERS_SPIO_5) << 5707 MISC_REGISTERS_SPIO_INT_OLD_SET_POS); 5708 REG_WR(bp, MISC_REG_SPIO_INT, val); 5709 5710 /* enable interrupt to signal the IGU */ 5711 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 5712 val |= (1 << MISC_REGISTERS_SPIO_5); 5713 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 5714} 5715 5716static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) 5717{ 5718 u32 offset = 0; 5719 5720 if (CHIP_IS_E1(bp)) 5721 return; 5722 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) 5723 return; 5724 5725 switch (BP_ABS_FUNC(bp)) { 5726 case 0: 5727 offset = PXP2_REG_PGL_PRETEND_FUNC_F0; 5728 break; 5729 case 1: 5730 offset = PXP2_REG_PGL_PRETEND_FUNC_F1; 5731 break; 5732 case 2: 5733 offset = PXP2_REG_PGL_PRETEND_FUNC_F2; 5734 break; 5735 case 3: 5736 offset = PXP2_REG_PGL_PRETEND_FUNC_F3; 5737 break; 5738 case 4: 5739 offset = PXP2_REG_PGL_PRETEND_FUNC_F4; 5740 break; 5741 case 5: 5742 offset = PXP2_REG_PGL_PRETEND_FUNC_F5; 5743 break; 5744 case 6: 5745 offset = PXP2_REG_PGL_PRETEND_FUNC_F6; 5746 break; 5747 case 7: 5748 offset = PXP2_REG_PGL_PRETEND_FUNC_F7; 5749 break; 5750 default: 5751 return; 5752 } 5753 5754 REG_WR(bp, offset, pretend_func_num); 5755 REG_RD(bp, offset); 5756 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); 5757} 5758 5759void bnx2x_pf_disable(struct bnx2x *bp) 5760{ 5761 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 5762 val &= ~IGU_PF_CONF_FUNC_EN; 5763 5764 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 5765 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 5766 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); 5767} 5768 5769static inline void bnx2x__common_init_phy(struct bnx2x *bp) 5770{ 5771 u32 shmem_base[2], shmem2_base[2]; 5772 shmem_base[0] = bp->common.shmem_base; 5773 shmem2_base[0] = bp->common.shmem2_base; 5774 if (!CHIP_IS_E1x(bp)) { 5775 shmem_base[1] = 5776 SHMEM2_RD(bp, other_shmem_base_addr); 5777 shmem2_base[1] = 5778 SHMEM2_RD(bp, other_shmem2_base_addr); 5779 } 5780 bnx2x_acquire_phy_lock(bp); 5781 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, 5782 bp->common.chip_id); 5783 bnx2x_release_phy_lock(bp); 5784} 5785 5786/** 5787 * bnx2x_init_hw_common - initialize the HW at the COMMON phase. 5788 * 5789 * @bp: driver handle 5790 */ 5791static int bnx2x_init_hw_common(struct bnx2x *bp) 5792{ 5793 u32 val; 5794 5795 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp)); 5796 5797 /* 5798 * take the UNDI lock to protect undi_unload flow from accessing 5799 * registers while we're resetting the chip 5800 */ 5801 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); 5802 5803 bnx2x_reset_common(bp); 5804 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 5805 5806 val = 0xfffc; 5807 if (CHIP_IS_E3(bp)) { 5808 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 5809 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 5810 } 5811 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 5812 5813 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); 5814 5815 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 5816 5817 if (!CHIP_IS_E1x(bp)) { 5818 u8 abs_func_id; 5819 5820 /** 5821 * 4-port mode or 2-port mode we need to turn of master-enable 5822 * for everyone, after that, turn it back on for self. 5823 * so, we disregard multi-function or not, and always disable 5824 * for all functions on the given path, this means 0,2,4,6 for 5825 * path 0 and 1,3,5,7 for path 1 5826 */ 5827 for (abs_func_id = BP_PATH(bp); 5828 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { 5829 if (abs_func_id == BP_ABS_FUNC(bp)) { 5830 REG_WR(bp, 5831 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 5832 1); 5833 continue; 5834 } 5835 5836 bnx2x_pretend_func(bp, abs_func_id); 5837 /* clear pf enable */ 5838 bnx2x_pf_disable(bp); 5839 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 5840 } 5841 } 5842 5843 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); 5844 if (CHIP_IS_E1(bp)) { 5845 /* enable HW interrupt from PXP on USDM overflow 5846 bit 16 on INT_MASK_0 */ 5847 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 5848 } 5849 5850 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); 5851 bnx2x_init_pxp(bp); 5852 5853#ifdef __BIG_ENDIAN 5854 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); 5855 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); 5856 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 5857 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 5858 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 5859 /* make sure this value is 0 */ 5860 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); 5861 5862/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ 5863 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); 5864 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); 5865 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); 5866 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 5867#endif 5868 5869 bnx2x_ilt_init_page_size(bp, INITOP_SET); 5870 5871 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 5872 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 5873 5874 /* let the HW do it's magic ... */ 5875 msleep(100); 5876 /* finish PXP init */ 5877 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); 5878 if (val != 1) { 5879 BNX2X_ERR("PXP2 CFG failed\n"); 5880 return -EBUSY; 5881 } 5882 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); 5883 if (val != 1) { 5884 BNX2X_ERR("PXP2 RD_INIT failed\n"); 5885 return -EBUSY; 5886 } 5887 5888 /* Timers bug workaround E2 only. We need to set the entire ILT to 5889 * have entries with value "0" and valid bit on. 5890 * This needs to be done by the first PF that is loaded in a path 5891 * (i.e. common phase) 5892 */ 5893 if (!CHIP_IS_E1x(bp)) { 5894/* In E2 there is a bug in the timers block that can cause function 6 / 7 5895 * (i.e. vnic3) to start even if it is marked as "scan-off". 5896 * This occurs when a different function (func2,3) is being marked 5897 * as "scan-off". Real-life scenario for example: if a driver is being 5898 * load-unloaded while func6,7 are down. This will cause the timer to access 5899 * the ilt, translate to a logical address and send a request to read/write. 5900 * Since the ilt for the function that is down is not valid, this will cause 5901 * a translation error which is unrecoverable. 5902 * The Workaround is intended to make sure that when this happens nothing fatal 5903 * will occur. The workaround: 5904 * 1. First PF driver which loads on a path will: 5905 * a. After taking the chip out of reset, by using pretend, 5906 * it will write "0" to the following registers of 5907 * the other vnics. 5908 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 5909 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 5910 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 5911 * And for itself it will write '1' to 5912 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 5913 * dmae-operations (writing to pram for example.) 5914 * note: can be done for only function 6,7 but cleaner this 5915 * way. 5916 * b. Write zero+valid to the entire ILT. 5917 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 5918 * VNIC3 (of that port). The range allocated will be the 5919 * entire ILT. This is needed to prevent ILT range error. 5920 * 2. Any PF driver load flow: 5921 * a. ILT update with the physical addresses of the allocated 5922 * logical pages. 5923 * b. Wait 20msec. - note that this timeout is needed to make 5924 * sure there are no requests in one of the PXP internal 5925 * queues with "old" ILT addresses. 5926 * c. PF enable in the PGLC. 5927 * d. Clear the was_error of the PF in the PGLC. (could have 5928 * occured while driver was down) 5929 * e. PF enable in the CFC (WEAK + STRONG) 5930 * f. Timers scan enable 5931 * 3. PF driver unload flow: 5932 * a. Clear the Timers scan_en. 5933 * b. Polling for scan_on=0 for that PF. 5934 * c. Clear the PF enable bit in the PXP. 5935 * d. Clear the PF enable in the CFC (WEAK + STRONG) 5936 * e. Write zero+valid to all ILT entries (The valid bit must 5937 * stay set) 5938 * f. If this is VNIC 3 of a port then also init 5939 * first_timers_ilt_entry to zero and last_timers_ilt_entry 5940 * to the last enrty in the ILT. 5941 * 5942 * Notes: 5943 * Currently the PF error in the PGLC is non recoverable. 5944 * In the future the there will be a recovery routine for this error. 5945 * Currently attention is masked. 5946 * Having an MCP lock on the load/unload process does not guarantee that 5947 * there is no Timer disable during Func6/7 enable. This is because the 5948 * Timers scan is currently being cleared by the MCP on FLR. 5949 * Step 2.d can be done only for PF6/7 and the driver can also check if 5950 * there is error before clearing it. But the flow above is simpler and 5951 * more general. 5952 * All ILT entries are written by zero+valid and not just PF6/7 5953 * ILT entries since in the future the ILT entries allocation for 5954 * PF-s might be dynamic. 5955 */ 5956 struct ilt_client_info ilt_cli; 5957 struct bnx2x_ilt ilt; 5958 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 5959 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); 5960 5961 /* initialize dummy TM client */ 5962 ilt_cli.start = 0; 5963 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 5964 ilt_cli.client_num = ILT_CLIENT_TM; 5965 5966 /* Step 1: set zeroes to all ilt page entries with valid bit on 5967 * Step 2: set the timers first/last ilt entry to point 5968 * to the entire range to prevent ILT range error for 3rd/4th 5969 * vnic (this code assumes existance of the vnic) 5970 * 5971 * both steps performed by call to bnx2x_ilt_client_init_op() 5972 * with dummy TM client 5973 * 5974 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 5975 * and his brother are split registers 5976 */ 5977 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); 5978 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); 5979 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 5980 5981 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); 5982 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); 5983 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 5984 } 5985 5986 5987 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 5988 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 5989 5990 if (!CHIP_IS_E1x(bp)) { 5991 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : 5992 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); 5993 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); 5994 5995 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); 5996 5997 /* let the HW do it's magic ... */ 5998 do { 5999 msleep(200); 6000 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); 6001 } while (factor-- && (val != 1)); 6002 6003 if (val != 1) { 6004 BNX2X_ERR("ATC_INIT failed\n"); 6005 return -EBUSY; 6006 } 6007 } 6008 6009 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); 6010 6011 /* clean the DMAE memory */ 6012 bp->dmae_ready = 1; 6013 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); 6014 6015 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); 6016 6017 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); 6018 6019 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); 6020 6021 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); 6022 6023 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); 6024 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); 6025 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); 6026 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); 6027 6028 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); 6029 6030 6031 /* QM queues pointers table */ 6032 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); 6033 6034 /* soft reset pulse */ 6035 REG_WR(bp, QM_REG_SOFT_RESET, 1); 6036 REG_WR(bp, QM_REG_SOFT_RESET, 0); 6037 6038#ifdef BCM_CNIC 6039 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); 6040#endif 6041 6042 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); 6043 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); 6044 if (!CHIP_REV_IS_SLOW(bp)) 6045 /* enable hw interrupt from doorbell Q */ 6046 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6047 6048 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6049 6050 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6051 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 6052 6053 if (!CHIP_IS_E1(bp)) 6054 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); 6055 6056 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) 6057 /* Bit-map indicating which L2 hdrs may appear 6058 * after the basic Ethernet header 6059 */ 6060 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 6061 bp->path_has_ovlan ? 7 : 6); 6062 6063 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); 6064 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); 6065 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); 6066 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); 6067 6068 if (!CHIP_IS_E1x(bp)) { 6069 /* reset VFC memories */ 6070 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6071 VFC_MEMORIES_RST_REG_CAM_RST | 6072 VFC_MEMORIES_RST_REG_RAM_RST); 6073 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6074 VFC_MEMORIES_RST_REG_CAM_RST | 6075 VFC_MEMORIES_RST_REG_RAM_RST); 6076 6077 msleep(20); 6078 } 6079 6080 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); 6081 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); 6082 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); 6083 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); 6084 6085 /* sync semi rtc */ 6086 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6087 0x80000000); 6088 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 6089 0x80000000); 6090 6091 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); 6092 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); 6093 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); 6094 6095 if (!CHIP_IS_E1x(bp)) 6096 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 6097 bp->path_has_ovlan ? 7 : 6); 6098 6099 REG_WR(bp, SRC_REG_SOFT_RST, 1); 6100 6101 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); 6102 6103#ifdef BCM_CNIC 6104 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 6105 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 6106 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); 6107 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); 6108 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); 6109 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 6110 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); 6111 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 6112 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); 6113 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); 6114#endif 6115 REG_WR(bp, SRC_REG_SOFT_RST, 0); 6116 6117 if (sizeof(union cdu_context) != 1024) 6118 /* we currently assume that a context is 1024 bytes */ 6119 dev_alert(&bp->pdev->dev, "please adjust the size " 6120 "of cdu_context(%ld)\n", 6121 (long)sizeof(union cdu_context)); 6122 6123 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 6124 val = (4 << 24) + (0 << 12) + 1024; 6125 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); 6126 6127 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); 6128 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); 6129 /* enable context validation interrupt from CFC */ 6130 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6131 6132 /* set the thresholds to prevent CFC/CDU race */ 6133 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 6134 6135 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); 6136 6137 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) 6138 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); 6139 6140 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); 6141 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); 6142 6143 /* Reset PCIE errors for debug */ 6144 REG_WR(bp, 0x2814, 0xffffffff); 6145 REG_WR(bp, 0x3820, 0xffffffff); 6146 6147 if (!CHIP_IS_E1x(bp)) { 6148 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 6149 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 6150 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 6151 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 6152 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 6153 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 6154 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 6155 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 6156 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 6157 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 6158 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 6159 } 6160 6161 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); 6162 if (!CHIP_IS_E1(bp)) { 6163 /* in E3 this done in per-port section */ 6164 if (!CHIP_IS_E3(bp)) 6165 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6166 } 6167 if (CHIP_IS_E1H(bp)) 6168 /* not applicable for E2 (and above ...) */ 6169 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); 6170 6171 if (CHIP_REV_IS_SLOW(bp)) 6172 msleep(200); 6173 6174 /* finish CFC init */ 6175 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); 6176 if (val != 1) { 6177 BNX2X_ERR("CFC LL_INIT failed\n"); 6178 return -EBUSY; 6179 } 6180 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); 6181 if (val != 1) { 6182 BNX2X_ERR("CFC AC_INIT failed\n"); 6183 return -EBUSY; 6184 } 6185 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 6186 if (val != 1) { 6187 BNX2X_ERR("CFC CAM_INIT failed\n"); 6188 return -EBUSY; 6189 } 6190 REG_WR(bp, CFC_REG_DEBUG0, 0); 6191 6192 if (CHIP_IS_E1(bp)) { 6193 /* read NIG statistic 6194 to see if this is our first up since powerup */ 6195 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6196 val = *bnx2x_sp(bp, wb_data[0]); 6197 6198 /* do internal memory self test */ 6199 if ((val == 0) && bnx2x_int_mem_test(bp)) { 6200 BNX2X_ERR("internal mem self test failed\n"); 6201 return -EBUSY; 6202 } 6203 } 6204 6205 bnx2x_setup_fan_failure_detection(bp); 6206 6207 /* clear PXP2 attentions */ 6208 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 6209 6210 bnx2x_enable_blocks_attention(bp); 6211 bnx2x_enable_blocks_parity(bp); 6212 6213 if (!BP_NOMCP(bp)) { 6214 if (CHIP_IS_E1x(bp)) 6215 bnx2x__common_init_phy(bp); 6216 } else 6217 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 6218 6219 return 0; 6220} 6221 6222/** 6223 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. 6224 * 6225 * @bp: driver handle 6226 */ 6227static int bnx2x_init_hw_common_chip(struct bnx2x *bp) 6228{ 6229 int rc = bnx2x_init_hw_common(bp); 6230 6231 if (rc) 6232 return rc; 6233 6234 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 6235 if (!BP_NOMCP(bp)) 6236 bnx2x__common_init_phy(bp); 6237 6238 return 0; 6239} 6240 6241static int bnx2x_init_hw_port(struct bnx2x *bp) 6242{ 6243 int port = BP_PORT(bp); 6244 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 6245 u32 low, high; 6246 u32 val; 6247 6248 bnx2x__link_reset(bp); 6249 6250 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port); 6251 6252 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 6253 6254 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6255 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6256 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6257 6258 /* Timers bug workaround: disables the pf_master bit in pglue at 6259 * common phase, we need to enable it here before any dmae access are 6260 * attempted. Therefore we manually added the enable-master to the 6261 * port phase (it also happens in the function phase) 6262 */ 6263 if (!CHIP_IS_E1x(bp)) 6264 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6265 6266 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6267 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6268 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6269 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6270 6271 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6272 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6273 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6274 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6275 6276 /* QM cid (connection) count */ 6277 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); 6278 6279#ifdef BCM_CNIC 6280 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6281 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 6282 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 6283#endif 6284 6285 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6286 6287 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { 6288 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6289 6290 if (IS_MF(bp)) 6291 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 6292 else if (bp->dev->mtu > 4096) { 6293 if (bp->flags & ONE_PORT_FLAG) 6294 low = 160; 6295 else { 6296 val = bp->dev->mtu; 6297 /* (24*1024 + val*4)/256 */ 6298 low = 96 + (val/64) + 6299 ((val % 64) ? 1 : 0); 6300 } 6301 } else 6302 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 6303 high = low + 56; /* 14*1024/256 */ 6304 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 6305 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 6306 } 6307 6308 if (CHIP_MODE_IS_4_PORT(bp)) 6309 REG_WR(bp, (BP_PORT(bp) ? 6310 BRB1_REG_MAC_GUARANTIED_1 : 6311 BRB1_REG_MAC_GUARANTIED_0), 40); 6312 6313 6314 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6315 if (CHIP_IS_E3B0(bp)) 6316 /* Ovlan exists only if we are in multi-function + 6317 * switch-dependent mode, in switch-independent there 6318 * is no ovlan headers 6319 */ 6320 REG_WR(bp, BP_PORT(bp) ? 6321 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 6322 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 6323 (bp->path_has_ovlan ? 7 : 6)); 6324 6325 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6326 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6327 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6328 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6329 6330 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6331 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6332 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6333 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6334 6335 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6336 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6337 6338 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6339 6340 if (CHIP_IS_E1x(bp)) { 6341 /* configure PBF to work without PAUSE mtu 9000 */ 6342 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 6343 6344 /* update threshold */ 6345 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 6346 /* update init credit */ 6347 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 6348 6349 /* probe changes */ 6350 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 6351 udelay(50); 6352 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 6353 } 6354 6355#ifdef BCM_CNIC 6356 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6357#endif 6358 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6359 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6360 6361 if (CHIP_IS_E1(bp)) { 6362 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6363 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6364 } 6365 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6366 6367 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6368 6369 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6370 /* init aeu_mask_attn_func_0/1: 6371 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 6372 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 6373 * bits 4-7 are used for "per vn group attention" */ 6374 val = IS_MF(bp) ? 0xF7 : 0x7; 6375 /* Enable DCBX attention for all but E1 */ 6376 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 6377 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 6378 6379 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6380 6381 if (!CHIP_IS_E1x(bp)) { 6382 /* Bit-map indicating which L2 hdrs may appear after the 6383 * basic Ethernet header 6384 */ 6385 REG_WR(bp, BP_PORT(bp) ? 6386 NIG_REG_P1_HDRS_AFTER_BASIC : 6387 NIG_REG_P0_HDRS_AFTER_BASIC, 6388 IS_MF_SD(bp) ? 7 : 6); 6389 6390 if (CHIP_IS_E3(bp)) 6391 REG_WR(bp, BP_PORT(bp) ? 6392 NIG_REG_LLH1_MF_MODE : 6393 NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6394 } 6395 if (!CHIP_IS_E3(bp)) 6396 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 6397 6398 if (!CHIP_IS_E1(bp)) { 6399 /* 0x2 disable mf_ov, 0x1 enable */ 6400 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 6401 (IS_MF_SD(bp) ? 0x1 : 0x2)); 6402 6403 if (!CHIP_IS_E1x(bp)) { 6404 val = 0; 6405 switch (bp->mf_mode) { 6406 case MULTI_FUNCTION_SD: 6407 val = 1; 6408 break; 6409 case MULTI_FUNCTION_SI: 6410 val = 2; 6411 break; 6412 } 6413 6414 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : 6415 NIG_REG_LLH0_CLS_TYPE), val); 6416 } 6417 { 6418 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 6419 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 6420 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 6421 } 6422 } 6423 6424 6425 /* If SPIO5 is set to generate interrupts, enable it for this port */ 6426 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6427 if (val & (1 << MISC_REGISTERS_SPIO_5)) { 6428 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 6429 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 6430 val = REG_RD(bp, reg_addr); 6431 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 6432 REG_WR(bp, reg_addr, val); 6433 } 6434 6435 return 0; 6436} 6437 6438static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 6439{ 6440 int reg; 6441 6442 if (CHIP_IS_E1(bp)) 6443 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 6444 else 6445 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 6446 6447 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr)); 6448} 6449 6450static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) 6451{ 6452 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); 6453} 6454 6455static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) 6456{ 6457 u32 i, base = FUNC_ILT_BASE(func); 6458 for (i = base; i < base + ILT_PER_FUNC; i++) 6459 bnx2x_ilt_wr(bp, i, 0); 6460} 6461 6462static int bnx2x_init_hw_func(struct bnx2x *bp) 6463{ 6464 int port = BP_PORT(bp); 6465 int func = BP_FUNC(bp); 6466 int init_phase = PHASE_PF0 + func; 6467 struct bnx2x_ilt *ilt = BP_ILT(bp); 6468 u16 cdu_ilt_start; 6469 u32 addr, val; 6470 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 6471 int i, main_mem_width; 6472 6473 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func); 6474 6475 /* FLR cleanup - hmmm */ 6476 if (!CHIP_IS_E1x(bp)) 6477 bnx2x_pf_flr_clnup(bp); 6478 6479 /* set MSI reconfigure capability */ 6480 if (bp->common.int_block == INT_BLOCK_HC) { 6481 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 6482 val = REG_RD(bp, addr); 6483 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 6484 REG_WR(bp, addr, val); 6485 } 6486 6487 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6488 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6489 6490 ilt = BP_ILT(bp); 6491 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 6492 6493 for (i = 0; i < L2_ILT_LINES(bp); i++) { 6494 ilt->lines[cdu_ilt_start + i].page = 6495 bp->context.vcxt + (ILT_PAGE_CIDS * i); 6496 ilt->lines[cdu_ilt_start + i].page_mapping = 6497 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i); 6498 /* cdu ilt pages are allocated manually so there's no need to 6499 set the size */ 6500 } 6501 bnx2x_ilt_init_op(bp, INITOP_SET); 6502 6503#ifdef BCM_CNIC 6504 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); 6505 6506 /* T1 hash bits value determines the T1 number of entries */ 6507 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 6508#endif 6509 6510#ifndef BCM_CNIC 6511 /* set NIC mode */ 6512 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6513#endif /* BCM_CNIC */ 6514 6515 if (!CHIP_IS_E1x(bp)) { 6516 u32 pf_conf = IGU_PF_CONF_FUNC_EN; 6517 6518 /* Turn on a single ISR mode in IGU if driver is going to use 6519 * INT#x or MSI 6520 */ 6521 if (!(bp->flags & USING_MSIX_FLAG)) 6522 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 6523 /* 6524 * Timers workaround bug: function init part. 6525 * Need to wait 20msec after initializing ILT, 6526 * needed to make sure there are no requests in 6527 * one of the PXP internal queues with "old" ILT addresses 6528 */ 6529 msleep(20); 6530 /* 6531 * Master enable - Due to WB DMAE writes performed before this 6532 * register is re-initialized as part of the regular function 6533 * init 6534 */ 6535 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6536 /* Enable the function in IGU */ 6537 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); 6538 } 6539 6540 bp->dmae_ready = 1; 6541 6542 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6543 6544 if (!CHIP_IS_E1x(bp)) 6545 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); 6546 6547 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6548 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6549 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6550 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6551 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6552 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6553 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6554 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6555 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6556 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6557 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6558 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6559 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6560 6561 if (!CHIP_IS_E1x(bp)) 6562 REG_WR(bp, QM_REG_PF_EN, 1); 6563 6564 if (!CHIP_IS_E1x(bp)) { 6565 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6566 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6567 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6568 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6569 } 6570 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6571 6572 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6573 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6574 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6575 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6576 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6577 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6578 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6579 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6580 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6581 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6582 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6583 if (!CHIP_IS_E1x(bp)) 6584 REG_WR(bp, PBF_REG_DISABLE_PF, 0); 6585 6586 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6587 6588 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6589 6590 if (!CHIP_IS_E1x(bp)) 6591 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); 6592 6593 if (IS_MF(bp)) { 6594 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 6595 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); 6596 } 6597 6598 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6599 6600 /* HC init per function */ 6601 if (bp->common.int_block == INT_BLOCK_HC) { 6602 if (CHIP_IS_E1H(bp)) { 6603 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6604 6605 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6606 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6607 } 6608 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6609 6610 } else { 6611 int num_segs, sb_idx, prod_offset; 6612 6613 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6614 6615 if (!CHIP_IS_E1x(bp)) { 6616 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 6617 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 6618 } 6619 6620 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6621 6622 if (!CHIP_IS_E1x(bp)) { 6623 int dsb_idx = 0; 6624 /** 6625 * Producer memory: 6626 * E2 mode: address 0-135 match to the mapping memory; 6627 * 136 - PF0 default prod; 137 - PF1 default prod; 6628 * 138 - PF2 default prod; 139 - PF3 default prod; 6629 * 140 - PF0 attn prod; 141 - PF1 attn prod; 6630 * 142 - PF2 attn prod; 143 - PF3 attn prod; 6631 * 144-147 reserved. 6632 * 6633 * E1.5 mode - In backward compatible mode; 6634 * for non default SB; each even line in the memory 6635 * holds the U producer and each odd line hold 6636 * the C producer. The first 128 producers are for 6637 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 6638 * producers are for the DSB for each PF. 6639 * Each PF has five segments: (the order inside each 6640 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 6641 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 6642 * 144-147 attn prods; 6643 */ 6644 /* non-default-status-blocks */ 6645 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6646 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 6647 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { 6648 prod_offset = (bp->igu_base_sb + sb_idx) * 6649 num_segs; 6650 6651 for (i = 0; i < num_segs; i++) { 6652 addr = IGU_REG_PROD_CONS_MEMORY + 6653 (prod_offset + i) * 4; 6654 REG_WR(bp, addr, 0); 6655 } 6656 /* send consumer update with value 0 */ 6657 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, 6658 USTORM_ID, 0, IGU_INT_NOP, 1); 6659 bnx2x_igu_clear_sb(bp, 6660 bp->igu_base_sb + sb_idx); 6661 } 6662 6663 /* default-status-blocks */ 6664 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6665 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 6666 6667 if (CHIP_MODE_IS_4_PORT(bp)) 6668 dsb_idx = BP_FUNC(bp); 6669 else 6670 dsb_idx = BP_E1HVN(bp); 6671 6672 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 6673 IGU_BC_BASE_DSB_PROD + dsb_idx : 6674 IGU_NORM_BASE_DSB_PROD + dsb_idx); 6675 6676 for (i = 0; i < (num_segs * E1HVN_MAX); 6677 i += E1HVN_MAX) { 6678 addr = IGU_REG_PROD_CONS_MEMORY + 6679 (prod_offset + i)*4; 6680 REG_WR(bp, addr, 0); 6681 } 6682 /* send consumer update with 0 */ 6683 if (CHIP_INT_MODE_IS_BC(bp)) { 6684 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6685 USTORM_ID, 0, IGU_INT_NOP, 1); 6686 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6687 CSTORM_ID, 0, IGU_INT_NOP, 1); 6688 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6689 XSTORM_ID, 0, IGU_INT_NOP, 1); 6690 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6691 TSTORM_ID, 0, IGU_INT_NOP, 1); 6692 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6693 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6694 } else { 6695 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6696 USTORM_ID, 0, IGU_INT_NOP, 1); 6697 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6698 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6699 } 6700 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); 6701 6702 /* !!! these should become driver const once 6703 rf-tool supports split-68 const */ 6704 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 6705 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 6706 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 6707 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 6708 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 6709 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 6710 } 6711 } 6712 6713 /* Reset PCIE errors for debug */ 6714 REG_WR(bp, 0x2114, 0xffffffff); 6715 REG_WR(bp, 0x2120, 0xffffffff); 6716 6717 if (CHIP_IS_E1x(bp)) { 6718 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 6719 main_mem_base = HC_REG_MAIN_MEMORY + 6720 BP_PORT(bp) * (main_mem_size * 4); 6721 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 6722 main_mem_width = 8; 6723 6724 val = REG_RD(bp, main_mem_prty_clr); 6725 if (val) 6726 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC " 6727 "block during " 6728 "function init (0x%x)!\n", val); 6729 6730 /* Clear "false" parity errors in MSI-X table */ 6731 for (i = main_mem_base; 6732 i < main_mem_base + main_mem_size * 4; 6733 i += main_mem_width) { 6734 bnx2x_read_dmae(bp, i, main_mem_width / 4); 6735 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), 6736 i, main_mem_width / 4); 6737 } 6738 /* Clear HC parity attention */ 6739 REG_RD(bp, main_mem_prty_clr); 6740 } 6741 6742#ifdef BNX2X_STOP_ON_ERROR 6743 /* Enable STORMs SP logging */ 6744 REG_WR8(bp, BAR_USTRORM_INTMEM + 6745 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6746 REG_WR8(bp, BAR_TSTRORM_INTMEM + 6747 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6748 REG_WR8(bp, BAR_CSTRORM_INTMEM + 6749 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6750 REG_WR8(bp, BAR_XSTRORM_INTMEM + 6751 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6752#endif 6753 6754 bnx2x_phy_probe(&bp->link_params); 6755 6756 return 0; 6757} 6758 6759 6760void bnx2x_free_mem(struct bnx2x *bp) 6761{ 6762 /* fastpath */ 6763 bnx2x_free_fp_mem(bp); 6764 /* end of fastpath */ 6765 6766 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 6767 sizeof(struct host_sp_status_block)); 6768 6769 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 6770 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 6771 6772 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 6773 sizeof(struct bnx2x_slowpath)); 6774 6775 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping, 6776 bp->context.size); 6777 6778 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); 6779 6780 BNX2X_FREE(bp->ilt->lines); 6781 6782#ifdef BCM_CNIC 6783 if (!CHIP_IS_E1x(bp)) 6784 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, 6785 sizeof(struct host_hc_status_block_e2)); 6786 else 6787 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, 6788 sizeof(struct host_hc_status_block_e1x)); 6789 6790 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 6791#endif 6792 6793 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 6794 6795 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, 6796 BCM_PAGE_SIZE * NUM_EQ_PAGES); 6797} 6798 6799static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) 6800{ 6801 int num_groups; 6802 6803 /* number of eth_queues */ 6804 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp); 6805 6806 /* Total number of FW statistics requests = 6807 * 1 for port stats + 1 for PF stats + num_eth_queues */ 6808 bp->fw_stats_num = 2 + num_queue_stats; 6809 6810 6811 /* Request is built from stats_query_header and an array of 6812 * stats_query_cmd_group each of which contains 6813 * STATS_QUERY_CMD_COUNT rules. The real number or requests is 6814 * configured in the stats_query_header. 6815 */ 6816 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT + 6817 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0); 6818 6819 bp->fw_stats_req_sz = sizeof(struct stats_query_header) + 6820 num_groups * sizeof(struct stats_query_cmd_group); 6821 6822 /* Data for statistics requests + stats_conter 6823 * 6824 * stats_counter holds per-STORM counters that are incremented 6825 * when STORM has finished with the current request. 6826 */ 6827 bp->fw_stats_data_sz = sizeof(struct per_port_stats) + 6828 sizeof(struct per_pf_stats) + 6829 sizeof(struct per_queue_stats) * num_queue_stats + 6830 sizeof(struct stats_counter); 6831 6832 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, 6833 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 6834 6835 /* Set shortcuts */ 6836 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; 6837 bp->fw_stats_req_mapping = bp->fw_stats_mapping; 6838 6839 bp->fw_stats_data = (struct bnx2x_fw_stats_data *) 6840 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); 6841 6842 bp->fw_stats_data_mapping = bp->fw_stats_mapping + 6843 bp->fw_stats_req_sz; 6844 return 0; 6845 6846alloc_mem_err: 6847 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 6848 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 6849 return -ENOMEM; 6850} 6851 6852 6853int bnx2x_alloc_mem(struct bnx2x *bp) 6854{ 6855#ifdef BCM_CNIC 6856 if (!CHIP_IS_E1x(bp)) 6857 /* size = the status block + ramrod buffers */ 6858 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, 6859 sizeof(struct host_hc_status_block_e2)); 6860 else 6861 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, 6862 sizeof(struct host_hc_status_block_e1x)); 6863 6864 /* allocate searcher T2 table */ 6865 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); 6866#endif 6867 6868 6869 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, 6870 sizeof(struct host_sp_status_block)); 6871 6872 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, 6873 sizeof(struct bnx2x_slowpath)); 6874 6875 /* Allocated memory for FW statistics */ 6876 if (bnx2x_alloc_fw_stats_mem(bp)) 6877 goto alloc_mem_err; 6878 6879 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); 6880 6881 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping, 6882 bp->context.size); 6883 6884 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); 6885 6886 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) 6887 goto alloc_mem_err; 6888 6889 /* Slow path ring */ 6890 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); 6891 6892 /* EQ */ 6893 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, 6894 BCM_PAGE_SIZE * NUM_EQ_PAGES); 6895 6896 6897 /* fastpath */ 6898 /* need to be done at the end, since it's self adjusting to amount 6899 * of memory available for RSS queues 6900 */ 6901 if (bnx2x_alloc_fp_mem(bp)) 6902 goto alloc_mem_err; 6903 return 0; 6904 6905alloc_mem_err: 6906 bnx2x_free_mem(bp); 6907 return -ENOMEM; 6908} 6909 6910/* 6911 * Init service functions 6912 */ 6913 6914int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 6915 struct bnx2x_vlan_mac_obj *obj, bool set, 6916 int mac_type, unsigned long *ramrod_flags) 6917{ 6918 int rc; 6919 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 6920 6921 memset(&ramrod_param, 0, sizeof(ramrod_param)); 6922 6923 /* Fill general parameters */ 6924 ramrod_param.vlan_mac_obj = obj; 6925 ramrod_param.ramrod_flags = *ramrod_flags; 6926 6927 /* Fill a user request section if needed */ 6928 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 6929 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 6930 6931 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 6932 6933 /* Set the command: ADD or DEL */ 6934 if (set) 6935 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 6936 else 6937 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 6938 } 6939 6940 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 6941 if (rc < 0) 6942 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); 6943 return rc; 6944} 6945 6946int bnx2x_del_all_macs(struct bnx2x *bp, 6947 struct bnx2x_vlan_mac_obj *mac_obj, 6948 int mac_type, bool wait_for_comp) 6949{ 6950 int rc; 6951 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 6952 6953 /* Wait for completion of requested */ 6954 if (wait_for_comp) 6955 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 6956 6957 /* Set the mac type of addresses we want to clear */ 6958 __set_bit(mac_type, &vlan_mac_flags); 6959 6960 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); 6961 if (rc < 0) 6962 BNX2X_ERR("Failed to delete MACs: %d\n", rc); 6963 6964 return rc; 6965} 6966 6967int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) 6968{ 6969 unsigned long ramrod_flags = 0; 6970 6971 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); 6972 6973 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 6974 /* Eth MAC is set on RSS leading client (fp[0]) */ 6975 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set, 6976 BNX2X_ETH_MAC, &ramrod_flags); 6977} 6978 6979int bnx2x_setup_leading(struct bnx2x *bp) 6980{ 6981 return bnx2x_setup_queue(bp, &bp->fp[0], 1); 6982} 6983 6984/** 6985 * bnx2x_set_int_mode - configure interrupt mode 6986 * 6987 * @bp: driver handle 6988 * 6989 * In case of MSI-X it will also try to enable MSI-X. 6990 */ 6991static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) 6992{ 6993 switch (int_mode) { 6994 case INT_MODE_MSI: 6995 bnx2x_enable_msi(bp); 6996 /* falling through... */ 6997 case INT_MODE_INTx: 6998 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 6999 DP(NETIF_MSG_IFUP, "set number of queues to 1\n"); 7000 break; 7001 default: 7002 /* Set number of queues according to bp->multi_mode value */ 7003 bnx2x_set_num_queues(bp); 7004 7005 DP(NETIF_MSG_IFUP, "set number of queues to %d\n", 7006 bp->num_queues); 7007 7008 /* if we can't use MSI-X we only need one fp, 7009 * so try to enable MSI-X with the requested number of fp's 7010 * and fallback to MSI or legacy INTx with one fp 7011 */ 7012 if (bnx2x_enable_msix(bp)) { 7013 /* failed to enable MSI-X */ 7014 if (bp->multi_mode) 7015 DP(NETIF_MSG_IFUP, 7016 "Multi requested but failed to " 7017 "enable MSI-X (%d), " 7018 "set number of queues to %d\n", 7019 bp->num_queues, 7020 1 + NON_ETH_CONTEXT_USE); 7021 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7022 7023 /* Try to enable MSI */ 7024 if (!(bp->flags & DISABLE_MSI_FLAG)) 7025 bnx2x_enable_msi(bp); 7026 } 7027 break; 7028 } 7029} 7030 7031/* must be called prioir to any HW initializations */ 7032static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) 7033{ 7034 return L2_ILT_LINES(bp); 7035} 7036 7037void bnx2x_ilt_set_info(struct bnx2x *bp) 7038{ 7039 struct ilt_client_info *ilt_client; 7040 struct bnx2x_ilt *ilt = BP_ILT(bp); 7041 u16 line = 0; 7042 7043 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); 7044 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); 7045 7046 /* CDU */ 7047 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 7048 ilt_client->client_num = ILT_CLIENT_CDU; 7049 ilt_client->page_size = CDU_ILT_PAGE_SZ; 7050 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 7051 ilt_client->start = line; 7052 line += bnx2x_cid_ilt_lines(bp); 7053#ifdef BCM_CNIC 7054 line += CNIC_ILT_LINES; 7055#endif 7056 ilt_client->end = line - 1; 7057 7058 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, " 7059 "flags 0x%x, hw psz %d\n", 7060 ilt_client->start, 7061 ilt_client->end, 7062 ilt_client->page_size, 7063 ilt_client->flags, 7064 ilog2(ilt_client->page_size >> 12)); 7065 7066 /* QM */ 7067 if (QM_INIT(bp->qm_cid_count)) { 7068 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 7069 ilt_client->client_num = ILT_CLIENT_QM; 7070 ilt_client->page_size = QM_ILT_PAGE_SZ; 7071 ilt_client->flags = 0; 7072 ilt_client->start = line; 7073 7074 /* 4 bytes for each cid */ 7075 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 7076 QM_ILT_PAGE_SZ); 7077 7078 ilt_client->end = line - 1; 7079 7080 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, " 7081 "flags 0x%x, hw psz %d\n", 7082 ilt_client->start, 7083 ilt_client->end, 7084 ilt_client->page_size, 7085 ilt_client->flags, 7086 ilog2(ilt_client->page_size >> 12)); 7087 7088 } 7089 /* SRC */ 7090 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 7091#ifdef BCM_CNIC 7092 ilt_client->client_num = ILT_CLIENT_SRC; 7093 ilt_client->page_size = SRC_ILT_PAGE_SZ; 7094 ilt_client->flags = 0; 7095 ilt_client->start = line; 7096 line += SRC_ILT_LINES; 7097 ilt_client->end = line - 1; 7098 7099 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, " 7100 "flags 0x%x, hw psz %d\n", 7101 ilt_client->start, 7102 ilt_client->end, 7103 ilt_client->page_size, 7104 ilt_client->flags, 7105 ilog2(ilt_client->page_size >> 12)); 7106 7107#else 7108 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7109#endif 7110 7111 /* TM */ 7112 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 7113#ifdef BCM_CNIC 7114 ilt_client->client_num = ILT_CLIENT_TM; 7115 ilt_client->page_size = TM_ILT_PAGE_SZ; 7116 ilt_client->flags = 0; 7117 ilt_client->start = line; 7118 line += TM_ILT_LINES; 7119 ilt_client->end = line - 1; 7120 7121 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, " 7122 "flags 0x%x, hw psz %d\n", 7123 ilt_client->start, 7124 ilt_client->end, 7125 ilt_client->page_size, 7126 ilt_client->flags, 7127 ilog2(ilt_client->page_size >> 12)); 7128 7129#else 7130 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7131#endif 7132 BUG_ON(line > ILT_MAX_LINES); 7133} 7134 7135/** 7136 * bnx2x_pf_q_prep_init - prepare INIT transition parameters 7137 * 7138 * @bp: driver handle 7139 * @fp: pointer to fastpath 7140 * @init_params: pointer to parameters structure 7141 * 7142 * parameters configured: 7143 * - HC configuration 7144 * - Queue's CDU context 7145 */ 7146static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp, 7147 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) 7148{ 7149 7150 u8 cos; 7151 /* FCoE Queue uses Default SB, thus has no HC capabilities */ 7152 if (!IS_FCOE_FP(fp)) { 7153 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); 7154 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); 7155 7156 /* If HC is supporterd, enable host coalescing in the transition 7157 * to INIT state. 7158 */ 7159 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); 7160 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); 7161 7162 /* HC rate */ 7163 init_params->rx.hc_rate = bp->rx_ticks ? 7164 (1000000 / bp->rx_ticks) : 0; 7165 init_params->tx.hc_rate = bp->tx_ticks ? 7166 (1000000 / bp->tx_ticks) : 0; 7167 7168 /* FW SB ID */ 7169 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = 7170 fp->fw_sb_id; 7171 7172 /* 7173 * CQ index among the SB indices: FCoE clients uses the default 7174 * SB, therefore it's different. 7175 */ 7176 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 7177 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 7178 } 7179 7180 /* set maximum number of COSs supported by this queue */ 7181 init_params->max_cos = fp->max_cos; 7182 7183 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n", 7184 fp->index, init_params->max_cos); 7185 7186 /* set the context pointers queue object */ 7187 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) 7188 init_params->cxts[cos] = 7189 &bp->context.vcxt[fp->txdata[cos].cid].eth; 7190} 7191 7192int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7193 struct bnx2x_queue_state_params *q_params, 7194 struct bnx2x_queue_setup_tx_only_params *tx_only_params, 7195 int tx_index, bool leading) 7196{ 7197 memset(tx_only_params, 0, sizeof(*tx_only_params)); 7198 7199 /* Set the command */ 7200 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 7201 7202 /* Set tx-only QUEUE flags: don't zero statistics */ 7203 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); 7204 7205 /* choose the index of the cid to send the slow path on */ 7206 tx_only_params->cid_index = tx_index; 7207 7208 /* Set general TX_ONLY_SETUP parameters */ 7209 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); 7210 7211 /* Set Tx TX_ONLY_SETUP parameters */ 7212 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 7213 7214 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:" 7215 "cos %d, primary cid %d, cid %d, " 7216 "client id %d, sp-client id %d, flags %lx\n", 7217 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 7218 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 7219 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 7220 7221 /* send the ramrod */ 7222 return bnx2x_queue_state_change(bp, q_params); 7223} 7224 7225 7226/** 7227 * bnx2x_setup_queue - setup queue 7228 * 7229 * @bp: driver handle 7230 * @fp: pointer to fastpath 7231 * @leading: is leading 7232 * 7233 * This function performs 2 steps in a Queue state machine 7234 * actually: 1) RESET->INIT 2) INIT->SETUP 7235 */ 7236 7237int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7238 bool leading) 7239{ 7240 struct bnx2x_queue_state_params q_params = {0}; 7241 struct bnx2x_queue_setup_params *setup_params = 7242 &q_params.params.setup; 7243 struct bnx2x_queue_setup_tx_only_params *tx_only_params = 7244 &q_params.params.tx_only; 7245 int rc; 7246 u8 tx_index; 7247 7248 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index); 7249 7250 /* reset IGU state skip FCoE L2 queue */ 7251 if (!IS_FCOE_FP(fp)) 7252 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, 7253 IGU_INT_ENABLE, 0); 7254 7255 q_params.q_obj = &fp->q_obj; 7256 /* We want to wait for completion in this context */ 7257 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7258 7259 /* Prepare the INIT parameters */ 7260 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); 7261 7262 /* Set the command */ 7263 q_params.cmd = BNX2X_Q_CMD_INIT; 7264 7265 /* Change the state to INIT */ 7266 rc = bnx2x_queue_state_change(bp, &q_params); 7267 if (rc) { 7268 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); 7269 return rc; 7270 } 7271 7272 DP(BNX2X_MSG_SP, "init complete\n"); 7273 7274 7275 /* Now move the Queue to the SETUP state... */ 7276 memset(setup_params, 0, sizeof(*setup_params)); 7277 7278 /* Set QUEUE flags */ 7279 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); 7280 7281 /* Set general SETUP parameters */ 7282 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, 7283 FIRST_TX_COS_INDEX); 7284 7285 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, 7286 &setup_params->rxq_params); 7287 7288 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, 7289 FIRST_TX_COS_INDEX); 7290 7291 /* Set the command */ 7292 q_params.cmd = BNX2X_Q_CMD_SETUP; 7293 7294 /* Change the state to SETUP */ 7295 rc = bnx2x_queue_state_change(bp, &q_params); 7296 if (rc) { 7297 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); 7298 return rc; 7299 } 7300 7301 /* loop through the relevant tx-only indices */ 7302 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7303 tx_index < fp->max_cos; 7304 tx_index++) { 7305 7306 /* prepare and send tx-only ramrod*/ 7307 rc = bnx2x_setup_tx_only(bp, fp, &q_params, 7308 tx_only_params, tx_index, leading); 7309 if (rc) { 7310 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", 7311 fp->index, tx_index); 7312 return rc; 7313 } 7314 } 7315 7316 return rc; 7317} 7318 7319static int bnx2x_stop_queue(struct bnx2x *bp, int index) 7320{ 7321 struct bnx2x_fastpath *fp = &bp->fp[index]; 7322 struct bnx2x_fp_txdata *txdata; 7323 struct bnx2x_queue_state_params q_params = {0}; 7324 int rc, tx_index; 7325 7326 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid); 7327 7328 q_params.q_obj = &fp->q_obj; 7329 /* We want to wait for completion in this context */ 7330 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7331 7332 7333 /* close tx-only connections */ 7334 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7335 tx_index < fp->max_cos; 7336 tx_index++){ 7337 7338 /* ascertain this is a normal queue*/ 7339 txdata = &fp->txdata[tx_index]; 7340 7341 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n", 7342 txdata->txq_index); 7343 7344 /* send halt terminate on tx-only connection */ 7345 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7346 memset(&q_params.params.terminate, 0, 7347 sizeof(q_params.params.terminate)); 7348 q_params.params.terminate.cid_index = tx_index; 7349 7350 rc = bnx2x_queue_state_change(bp, &q_params); 7351 if (rc) 7352 return rc; 7353 7354 /* send halt terminate on tx-only connection */ 7355 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7356 memset(&q_params.params.cfc_del, 0, 7357 sizeof(q_params.params.cfc_del)); 7358 q_params.params.cfc_del.cid_index = tx_index; 7359 rc = bnx2x_queue_state_change(bp, &q_params); 7360 if (rc) 7361 return rc; 7362 } 7363 /* Stop the primary connection: */ 7364 /* ...halt the connection */ 7365 q_params.cmd = BNX2X_Q_CMD_HALT; 7366 rc = bnx2x_queue_state_change(bp, &q_params); 7367 if (rc) 7368 return rc; 7369 7370 /* ...terminate the connection */ 7371 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7372 memset(&q_params.params.terminate, 0, 7373 sizeof(q_params.params.terminate)); 7374 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 7375 rc = bnx2x_queue_state_change(bp, &q_params); 7376 if (rc) 7377 return rc; 7378 /* ...delete cfc entry */ 7379 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7380 memset(&q_params.params.cfc_del, 0, 7381 sizeof(q_params.params.cfc_del)); 7382 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 7383 return bnx2x_queue_state_change(bp, &q_params); 7384} 7385 7386 7387static void bnx2x_reset_func(struct bnx2x *bp) 7388{ 7389 int port = BP_PORT(bp); 7390 int func = BP_FUNC(bp); 7391 int i; 7392 7393 /* Disable the function in the FW */ 7394 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 7395 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 7396 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 7397 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 7398 7399 /* FP SBs */ 7400 for_each_eth_queue(bp, i) { 7401 struct bnx2x_fastpath *fp = &bp->fp[i]; 7402 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7403 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 7404 SB_DISABLED); 7405 } 7406 7407#ifdef BCM_CNIC 7408 /* CNIC SB */ 7409 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7410 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), 7411 SB_DISABLED); 7412#endif 7413 /* SP SB */ 7414 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7415 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 7416 SB_DISABLED); 7417 7418 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) 7419 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 7420 0); 7421 7422 /* Configure IGU */ 7423 if (bp->common.int_block == INT_BLOCK_HC) { 7424 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7425 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7426 } else { 7427 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 7428 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 7429 } 7430 7431#ifdef BCM_CNIC 7432 /* Disable Timer scan */ 7433 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 7434 /* 7435 * Wait for at least 10ms and up to 2 second for the timers scan to 7436 * complete 7437 */ 7438 for (i = 0; i < 200; i++) { 7439 msleep(10); 7440 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) 7441 break; 7442 } 7443#endif 7444 /* Clear ILT */ 7445 bnx2x_clear_func_ilt(bp, func); 7446 7447 /* Timers workaround bug for E2: if this is vnic-3, 7448 * we need to set the entire ilt range for this timers. 7449 */ 7450 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { 7451 struct ilt_client_info ilt_cli; 7452 /* use dummy TM client */ 7453 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 7454 ilt_cli.start = 0; 7455 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 7456 ilt_cli.client_num = ILT_CLIENT_TM; 7457 7458 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); 7459 } 7460 7461 /* this assumes that reset_port() called before reset_func()*/ 7462 if (!CHIP_IS_E1x(bp)) 7463 bnx2x_pf_disable(bp); 7464 7465 bp->dmae_ready = 0; 7466} 7467 7468static void bnx2x_reset_port(struct bnx2x *bp) 7469{ 7470 int port = BP_PORT(bp); 7471 u32 val; 7472 7473 /* Reset physical Link */ 7474 bnx2x__link_reset(bp); 7475 7476 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 7477 7478 /* Do not rcv packets to BRB */ 7479 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 7480 /* Do not direct rcv packets that are not for MCP to the BRB */ 7481 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 7482 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 7483 7484 /* Configure AEU */ 7485 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 7486 7487 msleep(100); 7488 /* Check for BRB port occupancy */ 7489 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 7490 if (val) 7491 DP(NETIF_MSG_IFDOWN, 7492 "BRB1 is not empty %d blocks are occupied\n", val); 7493 7494 /* TODO: Close Doorbell port? */ 7495} 7496 7497static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) 7498{ 7499 struct bnx2x_func_state_params func_params = {0}; 7500 7501 /* Prepare parameters for function state transitions */ 7502 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7503 7504 func_params.f_obj = &bp->func_obj; 7505 func_params.cmd = BNX2X_F_CMD_HW_RESET; 7506 7507 func_params.params.hw_init.load_phase = load_code; 7508 7509 return bnx2x_func_state_change(bp, &func_params); 7510} 7511 7512static inline int bnx2x_func_stop(struct bnx2x *bp) 7513{ 7514 struct bnx2x_func_state_params func_params = {0}; 7515 int rc; 7516 7517 /* Prepare parameters for function state transitions */ 7518 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7519 func_params.f_obj = &bp->func_obj; 7520 func_params.cmd = BNX2X_F_CMD_STOP; 7521 7522 /* 7523 * Try to stop the function the 'good way'. If fails (in case 7524 * of a parity error during bnx2x_chip_cleanup()) and we are 7525 * not in a debug mode, perform a state transaction in order to 7526 * enable further HW_RESET transaction. 7527 */ 7528 rc = bnx2x_func_state_change(bp, &func_params); 7529 if (rc) { 7530#ifdef BNX2X_STOP_ON_ERROR 7531 return rc; 7532#else 7533 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry " 7534 "transaction\n"); 7535 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 7536 return bnx2x_func_state_change(bp, &func_params); 7537#endif 7538 } 7539 7540 return 0; 7541} 7542 7543/** 7544 * bnx2x_send_unload_req - request unload mode from the MCP. 7545 * 7546 * @bp: driver handle 7547 * @unload_mode: requested function's unload mode 7548 * 7549 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 7550 */ 7551u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 7552{ 7553 u32 reset_code = 0; 7554 int port = BP_PORT(bp); 7555 7556 /* Select the UNLOAD request mode */ 7557 if (unload_mode == UNLOAD_NORMAL) 7558 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7559 7560 else if (bp->flags & NO_WOL_FLAG) 7561 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 7562 7563 else if (bp->wol) { 7564 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 7565 u8 *mac_addr = bp->dev->dev_addr; 7566 u32 val; 7567 /* The mac address is written to entries 1-4 to 7568 preserve entry 0 which is used by the PMF */ 7569 u8 entry = (BP_E1HVN(bp) + 1)*8; 7570 7571 val = (mac_addr[0] << 8) | mac_addr[1]; 7572 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 7573 7574 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 7575 (mac_addr[4] << 8) | mac_addr[5]; 7576 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 7577 7578 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 7579 7580 } else 7581 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7582 7583 /* Send the request to the MCP */ 7584 if (!BP_NOMCP(bp)) 7585 reset_code = bnx2x_fw_command(bp, reset_code, 0); 7586 else { 7587 int path = BP_PATH(bp); 7588 7589 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] " 7590 "%d, %d, %d\n", 7591 path, load_count[path][0], load_count[path][1], 7592 load_count[path][2]); 7593 load_count[path][0]--; 7594 load_count[path][1 + port]--; 7595 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] " 7596 "%d, %d, %d\n", 7597 path, load_count[path][0], load_count[path][1], 7598 load_count[path][2]); 7599 if (load_count[path][0] == 0) 7600 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 7601 else if (load_count[path][1 + port] == 0) 7602 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 7603 else 7604 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 7605 } 7606 7607 return reset_code; 7608} 7609 7610/** 7611 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 7612 * 7613 * @bp: driver handle 7614 */ 7615void bnx2x_send_unload_done(struct bnx2x *bp) 7616{ 7617 /* Report UNLOAD_DONE to MCP */ 7618 if (!BP_NOMCP(bp)) 7619 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 7620} 7621 7622static inline int bnx2x_func_wait_started(struct bnx2x *bp) 7623{ 7624 int tout = 50; 7625 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 7626 7627 if (!bp->port.pmf) 7628 return 0; 7629 7630 /* 7631 * (assumption: No Attention from MCP at this stage) 7632 * PMF probably in the middle of TXdisable/enable transaction 7633 * 1. Sync IRS for default SB 7634 * 2. Sync SP queue - this guarantes us that attention handling started 7635 * 3. Wait, that TXdisable/enable transaction completes 7636 * 7637 * 1+2 guranty that if DCBx attention was scheduled it already changed 7638 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy 7639 * received complettion for the transaction the state is TX_STOPPED. 7640 * State will return to STARTED after completion of TX_STOPPED-->STARTED 7641 * transaction. 7642 */ 7643 7644 /* make sure default SB ISR is done */ 7645 if (msix) 7646 synchronize_irq(bp->msix_table[0].vector); 7647 else 7648 synchronize_irq(bp->pdev->irq); 7649 7650 flush_workqueue(bnx2x_wq); 7651 7652 while (bnx2x_func_get_state(bp, &bp->func_obj) != 7653 BNX2X_F_STATE_STARTED && tout--) 7654 msleep(20); 7655 7656 if (bnx2x_func_get_state(bp, &bp->func_obj) != 7657 BNX2X_F_STATE_STARTED) { 7658#ifdef BNX2X_STOP_ON_ERROR 7659 return -EBUSY; 7660#else 7661 /* 7662 * Failed to complete the transaction in a "good way" 7663 * Force both transactions with CLR bit 7664 */ 7665 struct bnx2x_func_state_params func_params = {0}; 7666 7667 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! " 7668 "Forcing STARTED-->TX_ST0PPED-->STARTED\n"); 7669 7670 func_params.f_obj = &bp->func_obj; 7671 __set_bit(RAMROD_DRV_CLR_ONLY, 7672 &func_params.ramrod_flags); 7673 7674 /* STARTED-->TX_ST0PPED */ 7675 func_params.cmd = BNX2X_F_CMD_TX_STOP; 7676 bnx2x_func_state_change(bp, &func_params); 7677 7678 /* TX_ST0PPED-->STARTED */ 7679 func_params.cmd = BNX2X_F_CMD_TX_START; 7680 return bnx2x_func_state_change(bp, &func_params); 7681#endif 7682 } 7683 7684 return 0; 7685} 7686 7687void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) 7688{ 7689 int port = BP_PORT(bp); 7690 int i, rc = 0; 7691 u8 cos; 7692 struct bnx2x_mcast_ramrod_params rparam = {0}; 7693 u32 reset_code; 7694 7695 /* Wait until tx fastpath tasks complete */ 7696 for_each_tx_queue(bp, i) { 7697 struct bnx2x_fastpath *fp = &bp->fp[i]; 7698 7699 for_each_cos_in_tx_queue(fp, cos) 7700 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]); 7701#ifdef BNX2X_STOP_ON_ERROR 7702 if (rc) 7703 return; 7704#endif 7705 } 7706 7707 /* Give HW time to discard old tx messages */ 7708 usleep_range(1000, 1000); 7709 7710 /* Clean all ETH MACs */ 7711 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false); 7712 if (rc < 0) 7713 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); 7714 7715 /* Clean up UC list */ 7716 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, 7717 true); 7718 if (rc < 0) 7719 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: " 7720 "%d\n", rc); 7721 7722 /* Disable LLH */ 7723 if (!CHIP_IS_E1(bp)) 7724 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 7725 7726 /* Set "drop all" (stop Rx). 7727 * We need to take a netif_addr_lock() here in order to prevent 7728 * a race between the completion code and this code. 7729 */ 7730 netif_addr_lock_bh(bp->dev); 7731 /* Schedule the rx_mode command */ 7732 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 7733 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 7734 else 7735 bnx2x_set_storm_rx_mode(bp); 7736 7737 /* Cleanup multicast configuration */ 7738 rparam.mcast_obj = &bp->mcast_obj; 7739 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 7740 if (rc < 0) 7741 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); 7742 7743 netif_addr_unlock_bh(bp->dev); 7744 7745 7746 7747 /* 7748 * Send the UNLOAD_REQUEST to the MCP. This will return if 7749 * this function should perform FUNC, PORT or COMMON HW 7750 * reset. 7751 */ 7752 reset_code = bnx2x_send_unload_req(bp, unload_mode); 7753 7754 /* 7755 * (assumption: No Attention from MCP at this stage) 7756 * PMF probably in the middle of TXdisable/enable transaction 7757 */ 7758 rc = bnx2x_func_wait_started(bp); 7759 if (rc) { 7760 BNX2X_ERR("bnx2x_func_wait_started failed\n"); 7761#ifdef BNX2X_STOP_ON_ERROR 7762 return; 7763#endif 7764 } 7765 7766 /* Close multi and leading connections 7767 * Completions for ramrods are collected in a synchronous way 7768 */ 7769 for_each_queue(bp, i) 7770 if (bnx2x_stop_queue(bp, i)) 7771#ifdef BNX2X_STOP_ON_ERROR 7772 return; 7773#else 7774 goto unload_error; 7775#endif 7776 /* If SP settings didn't get completed so far - something 7777 * very wrong has happen. 7778 */ 7779 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) 7780 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); 7781 7782#ifndef BNX2X_STOP_ON_ERROR 7783unload_error: 7784#endif 7785 rc = bnx2x_func_stop(bp); 7786 if (rc) { 7787 BNX2X_ERR("Function stop failed!\n"); 7788#ifdef BNX2X_STOP_ON_ERROR 7789 return; 7790#endif 7791 } 7792 7793 /* Disable HW interrupts, NAPI */ 7794 bnx2x_netif_stop(bp, 1); 7795 7796 /* Release IRQs */ 7797 bnx2x_free_irq(bp); 7798 7799 /* Reset the chip */ 7800 rc = bnx2x_reset_hw(bp, reset_code); 7801 if (rc) 7802 BNX2X_ERR("HW_RESET failed\n"); 7803 7804 7805 /* Report UNLOAD_DONE to MCP */ 7806 bnx2x_send_unload_done(bp); 7807} 7808 7809void bnx2x_disable_close_the_gate(struct bnx2x *bp) 7810{ 7811 u32 val; 7812 7813 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n"); 7814 7815 if (CHIP_IS_E1(bp)) { 7816 int port = BP_PORT(bp); 7817 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 7818 MISC_REG_AEU_MASK_ATTN_FUNC_0; 7819 7820 val = REG_RD(bp, addr); 7821 val &= ~(0x300); 7822 REG_WR(bp, addr, val); 7823 } else { 7824 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); 7825 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 7826 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 7827 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); 7828 } 7829} 7830 7831/* Close gates #2, #3 and #4: */ 7832static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 7833{ 7834 u32 val; 7835 7836 /* Gates #2 and #4a are closed/opened for "not E1" only */ 7837 if (!CHIP_IS_E1(bp)) { 7838 /* #4 */ 7839 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 7840 /* #2 */ 7841 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 7842 } 7843 7844 /* #3 */ 7845 if (CHIP_IS_E1x(bp)) { 7846 /* Prevent interrupts from HC on both ports */ 7847 val = REG_RD(bp, HC_REG_CONFIG_1); 7848 REG_WR(bp, HC_REG_CONFIG_1, 7849 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 7850 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 7851 7852 val = REG_RD(bp, HC_REG_CONFIG_0); 7853 REG_WR(bp, HC_REG_CONFIG_0, 7854 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 7855 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 7856 } else { 7857 /* Prevent incomming interrupts in IGU */ 7858 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 7859 7860 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, 7861 (!close) ? 7862 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 7863 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 7864 } 7865 7866 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n", 7867 close ? "closing" : "opening"); 7868 mmiowb(); 7869} 7870 7871#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ 7872 7873static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) 7874{ 7875 /* Do some magic... */ 7876 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 7877 *magic_val = val & SHARED_MF_CLP_MAGIC; 7878 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 7879} 7880 7881/** 7882 * bnx2x_clp_reset_done - restore the value of the `magic' bit. 7883 * 7884 * @bp: driver handle 7885 * @magic_val: old value of the `magic' bit. 7886 */ 7887static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 7888{ 7889 /* Restore the `magic' bit value... */ 7890 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 7891 MF_CFG_WR(bp, shared_mf_config.clp_mb, 7892 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 7893} 7894 7895/** 7896 * bnx2x_reset_mcp_prep - prepare for MCP reset. 7897 * 7898 * @bp: driver handle 7899 * @magic_val: old value of 'magic' bit. 7900 * 7901 * Takes care of CLP configurations. 7902 */ 7903static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 7904{ 7905 u32 shmem; 7906 u32 validity_offset; 7907 7908 DP(NETIF_MSG_HW, "Starting\n"); 7909 7910 /* Set `magic' bit in order to save MF config */ 7911 if (!CHIP_IS_E1(bp)) 7912 bnx2x_clp_reset_prep(bp, magic_val); 7913 7914 /* Get shmem offset */ 7915 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 7916 validity_offset = offsetof(struct shmem_region, validity_map[0]); 7917 7918 /* Clear validity map flags */ 7919 if (shmem > 0) 7920 REG_WR(bp, shmem + validity_offset, 0); 7921} 7922 7923#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 7924#define MCP_ONE_TIMEOUT 100 /* 100 ms */ 7925 7926/** 7927 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT 7928 * 7929 * @bp: driver handle 7930 */ 7931static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) 7932{ 7933 /* special handling for emulation and FPGA, 7934 wait 10 times longer */ 7935 if (CHIP_REV_IS_SLOW(bp)) 7936 msleep(MCP_ONE_TIMEOUT*10); 7937 else 7938 msleep(MCP_ONE_TIMEOUT); 7939} 7940 7941/* 7942 * initializes bp->common.shmem_base and waits for validity signature to appear 7943 */ 7944static int bnx2x_init_shmem(struct bnx2x *bp) 7945{ 7946 int cnt = 0; 7947 u32 val = 0; 7948 7949 do { 7950 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 7951 if (bp->common.shmem_base) { 7952 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 7953 if (val & SHR_MEM_VALIDITY_MB) 7954 return 0; 7955 } 7956 7957 bnx2x_mcp_wait_one(bp); 7958 7959 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 7960 7961 BNX2X_ERR("BAD MCP validity signature\n"); 7962 7963 return -ENODEV; 7964} 7965 7966static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 7967{ 7968 int rc = bnx2x_init_shmem(bp); 7969 7970 /* Restore the `magic' bit value */ 7971 if (!CHIP_IS_E1(bp)) 7972 bnx2x_clp_reset_done(bp, magic_val); 7973 7974 return rc; 7975} 7976 7977static void bnx2x_pxp_prep(struct bnx2x *bp) 7978{ 7979 if (!CHIP_IS_E1(bp)) { 7980 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 7981 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 7982 mmiowb(); 7983 } 7984} 7985 7986/* 7987 * Reset the whole chip except for: 7988 * - PCIE core 7989 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by 7990 * one reset bit) 7991 * - IGU 7992 * - MISC (including AEU) 7993 * - GRC 7994 * - RBCN, RBCP 7995 */ 7996static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) 7997{ 7998 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 7999 u32 global_bits2, stay_reset2; 8000 8001 /* 8002 * Bits that have to be set in reset_mask2 if we want to reset 'global' 8003 * (per chip) blocks. 8004 */ 8005 global_bits2 = 8006 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 8007 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 8008 8009 /* Don't reset the following blocks */ 8010 not_reset_mask1 = 8011 MISC_REGISTERS_RESET_REG_1_RST_HC | 8012 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 8013 MISC_REGISTERS_RESET_REG_1_RST_PXP; 8014 8015 not_reset_mask2 = 8016 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 8017 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 8018 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 8019 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 8020 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 8021 MISC_REGISTERS_RESET_REG_2_RST_GRC | 8022 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 8023 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 8024 MISC_REGISTERS_RESET_REG_2_RST_ATC | 8025 MISC_REGISTERS_RESET_REG_2_PGLC; 8026 8027 /* 8028 * Keep the following blocks in reset: 8029 * - all xxMACs are handled by the bnx2x_link code. 8030 */ 8031 stay_reset2 = 8032 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 8033 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 8034 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 8035 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 8036 MISC_REGISTERS_RESET_REG_2_UMAC0 | 8037 MISC_REGISTERS_RESET_REG_2_UMAC1 | 8038 MISC_REGISTERS_RESET_REG_2_XMAC | 8039 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 8040 8041 /* Full reset masks according to the chip */ 8042 reset_mask1 = 0xffffffff; 8043 8044 if (CHIP_IS_E1(bp)) 8045 reset_mask2 = 0xffff; 8046 else if (CHIP_IS_E1H(bp)) 8047 reset_mask2 = 0x1ffff; 8048 else if (CHIP_IS_E2(bp)) 8049 reset_mask2 = 0xfffff; 8050 else /* CHIP_IS_E3 */ 8051 reset_mask2 = 0x3ffffff; 8052 8053 /* Don't reset global blocks unless we need to */ 8054 if (!global) 8055 reset_mask2 &= ~global_bits2; 8056 8057 /* 8058 * In case of attention in the QM, we need to reset PXP 8059 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 8060 * because otherwise QM reset would release 'close the gates' shortly 8061 * before resetting the PXP, then the PSWRQ would send a write 8062 * request to PGLUE. Then when PXP is reset, PGLUE would try to 8063 * read the payload data from PSWWR, but PSWWR would not 8064 * respond. The write queue in PGLUE would stuck, dmae commands 8065 * would not return. Therefore it's important to reset the second 8066 * reset register (containing the 8067 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 8068 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 8069 * bit). 8070 */ 8071 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8072 reset_mask2 & (~not_reset_mask2)); 8073 8074 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8075 reset_mask1 & (~not_reset_mask1)); 8076 8077 barrier(); 8078 mmiowb(); 8079 8080 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 8081 reset_mask2 & (~stay_reset2)); 8082 8083 barrier(); 8084 mmiowb(); 8085 8086 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 8087 mmiowb(); 8088} 8089 8090/** 8091 * bnx2x_er_poll_igu_vq - poll for pending writes bit. 8092 * It should get cleared in no more than 1s. 8093 * 8094 * @bp: driver handle 8095 * 8096 * It should get cleared in no more than 1s. Returns 0 if 8097 * pending writes bit gets cleared. 8098 */ 8099static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) 8100{ 8101 u32 cnt = 1000; 8102 u32 pend_bits = 0; 8103 8104 do { 8105 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); 8106 8107 if (pend_bits == 0) 8108 break; 8109 8110 usleep_range(1000, 1000); 8111 } while (cnt-- > 0); 8112 8113 if (cnt <= 0) { 8114 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", 8115 pend_bits); 8116 return -EBUSY; 8117 } 8118 8119 return 0; 8120} 8121 8122static int bnx2x_process_kill(struct bnx2x *bp, bool global) 8123{ 8124 int cnt = 1000; 8125 u32 val = 0; 8126 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 8127 8128 8129 /* Empty the Tetris buffer, wait for 1s */ 8130 do { 8131 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); 8132 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); 8133 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); 8134 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); 8135 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); 8136 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 8137 ((port_is_idle_0 & 0x1) == 0x1) && 8138 ((port_is_idle_1 & 0x1) == 0x1) && 8139 (pgl_exp_rom2 == 0xffffffff)) 8140 break; 8141 usleep_range(1000, 1000); 8142 } while (cnt-- > 0); 8143 8144 if (cnt <= 0) { 8145 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there" 8146 " are still" 8147 " outstanding read requests after 1s!\n"); 8148 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x," 8149 " port_is_idle_0=0x%08x," 8150 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 8151 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 8152 pgl_exp_rom2); 8153 return -EAGAIN; 8154 } 8155 8156 barrier(); 8157 8158 /* Close gates #2, #3 and #4 */ 8159 bnx2x_set_234_gates(bp, true); 8160 8161 /* Poll for IGU VQs for 57712 and newer chips */ 8162 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) 8163 return -EAGAIN; 8164 8165 8166 /* TBD: Indicate that "process kill" is in progress to MCP */ 8167 8168 /* Clear "unprepared" bit */ 8169 REG_WR(bp, MISC_REG_UNPREPARED, 0); 8170 barrier(); 8171 8172 /* Make sure all is written to the chip before the reset */ 8173 mmiowb(); 8174 8175 /* Wait for 1ms to empty GLUE and PCI-E core queues, 8176 * PSWHST, GRC and PSWRD Tetris buffer. 8177 */ 8178 usleep_range(1000, 1000); 8179 8180 /* Prepare to chip reset: */ 8181 /* MCP */ 8182 if (global) 8183 bnx2x_reset_mcp_prep(bp, &val); 8184 8185 /* PXP */ 8186 bnx2x_pxp_prep(bp); 8187 barrier(); 8188 8189 /* reset the chip */ 8190 bnx2x_process_kill_chip_reset(bp, global); 8191 barrier(); 8192 8193 /* Recover after reset: */ 8194 /* MCP */ 8195 if (global && bnx2x_reset_mcp_comp(bp, val)) 8196 return -EAGAIN; 8197 8198 /* TBD: Add resetting the NO_MCP mode DB here */ 8199 8200 /* PXP */ 8201 bnx2x_pxp_prep(bp); 8202 8203 /* Open the gates #2, #3 and #4 */ 8204 bnx2x_set_234_gates(bp, false); 8205 8206 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a 8207 * reset state, re-enable attentions. */ 8208 8209 return 0; 8210} 8211 8212int bnx2x_leader_reset(struct bnx2x *bp) 8213{ 8214 int rc = 0; 8215 bool global = bnx2x_reset_is_global(bp); 8216 8217 /* Try to recover after the failure */ 8218 if (bnx2x_process_kill(bp, global)) { 8219 netdev_err(bp->dev, "Something bad had happen on engine %d! " 8220 "Aii!\n", BP_PATH(bp)); 8221 rc = -EAGAIN; 8222 goto exit_leader_reset; 8223 } 8224 8225 /* 8226 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver 8227 * state. 8228 */ 8229 bnx2x_set_reset_done(bp); 8230 if (global) 8231 bnx2x_clear_reset_global(bp); 8232 8233exit_leader_reset: 8234 bp->is_leader = 0; 8235 bnx2x_release_leader_lock(bp); 8236 smp_mb(); 8237 return rc; 8238} 8239 8240static inline void bnx2x_recovery_failed(struct bnx2x *bp) 8241{ 8242 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); 8243 8244 /* Disconnect this device */ 8245 netif_device_detach(bp->dev); 8246 8247 /* 8248 * Block ifup for all function on this engine until "process kill" 8249 * or power cycle. 8250 */ 8251 bnx2x_set_reset_in_progress(bp); 8252 8253 /* Shut down the power */ 8254 bnx2x_set_power_state(bp, PCI_D3hot); 8255 8256 bp->recovery_state = BNX2X_RECOVERY_FAILED; 8257 8258 smp_mb(); 8259} 8260 8261/* 8262 * Assumption: runs under rtnl lock. This together with the fact 8263 * that it's called only from bnx2x_sp_rtnl() ensure that it 8264 * will never be called when netif_running(bp->dev) is false. 8265 */ 8266static void bnx2x_parity_recover(struct bnx2x *bp) 8267{ 8268 bool global = false; 8269 8270 DP(NETIF_MSG_HW, "Handling parity\n"); 8271 while (1) { 8272 switch (bp->recovery_state) { 8273 case BNX2X_RECOVERY_INIT: 8274 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 8275 bnx2x_chk_parity_attn(bp, &global, false); 8276 8277 /* Try to get a LEADER_LOCK HW lock */ 8278 if (bnx2x_trylock_leader_lock(bp)) { 8279 bnx2x_set_reset_in_progress(bp); 8280 /* 8281 * Check if there is a global attention and if 8282 * there was a global attention, set the global 8283 * reset bit. 8284 */ 8285 8286 if (global) 8287 bnx2x_set_reset_global(bp); 8288 8289 bp->is_leader = 1; 8290 } 8291 8292 /* Stop the driver */ 8293 /* If interface has been removed - break */ 8294 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) 8295 return; 8296 8297 bp->recovery_state = BNX2X_RECOVERY_WAIT; 8298 8299 /* 8300 * Reset MCP command sequence number and MCP mail box 8301 * sequence as we are going to reset the MCP. 8302 */ 8303 if (global) { 8304 bp->fw_seq = 0; 8305 bp->fw_drv_pulse_wr_seq = 0; 8306 } 8307 8308 /* Ensure "is_leader", MCP command sequence and 8309 * "recovery_state" update values are seen on other 8310 * CPUs. 8311 */ 8312 smp_mb(); 8313 break; 8314 8315 case BNX2X_RECOVERY_WAIT: 8316 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 8317 if (bp->is_leader) { 8318 int other_engine = BP_PATH(bp) ? 0 : 1; 8319 u32 other_load_counter = 8320 bnx2x_get_load_cnt(bp, other_engine); 8321 u32 load_counter = 8322 bnx2x_get_load_cnt(bp, BP_PATH(bp)); 8323 global = bnx2x_reset_is_global(bp); 8324 8325 /* 8326 * In case of a parity in a global block, let 8327 * the first leader that performs a 8328 * leader_reset() reset the global blocks in 8329 * order to clear global attentions. Otherwise 8330 * the the gates will remain closed for that 8331 * engine. 8332 */ 8333 if (load_counter || 8334 (global && other_load_counter)) { 8335 /* Wait until all other functions get 8336 * down. 8337 */ 8338 schedule_delayed_work(&bp->sp_rtnl_task, 8339 HZ/10); 8340 return; 8341 } else { 8342 /* If all other functions got down - 8343 * try to bring the chip back to 8344 * normal. In any case it's an exit 8345 * point for a leader. 8346 */ 8347 if (bnx2x_leader_reset(bp)) { 8348 bnx2x_recovery_failed(bp); 8349 return; 8350 } 8351 8352 /* If we are here, means that the 8353 * leader has succeeded and doesn't 8354 * want to be a leader any more. Try 8355 * to continue as a none-leader. 8356 */ 8357 break; 8358 } 8359 } else { /* non-leader */ 8360 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { 8361 /* Try to get a LEADER_LOCK HW lock as 8362 * long as a former leader may have 8363 * been unloaded by the user or 8364 * released a leadership by another 8365 * reason. 8366 */ 8367 if (bnx2x_trylock_leader_lock(bp)) { 8368 /* I'm a leader now! Restart a 8369 * switch case. 8370 */ 8371 bp->is_leader = 1; 8372 break; 8373 } 8374 8375 schedule_delayed_work(&bp->sp_rtnl_task, 8376 HZ/10); 8377 return; 8378 8379 } else { 8380 /* 8381 * If there was a global attention, wait 8382 * for it to be cleared. 8383 */ 8384 if (bnx2x_reset_is_global(bp)) { 8385 schedule_delayed_work( 8386 &bp->sp_rtnl_task, 8387 HZ/10); 8388 return; 8389 } 8390 8391 if (bnx2x_nic_load(bp, LOAD_NORMAL)) 8392 bnx2x_recovery_failed(bp); 8393 else { 8394 bp->recovery_state = 8395 BNX2X_RECOVERY_DONE; 8396 smp_mb(); 8397 } 8398 8399 return; 8400 } 8401 } 8402 default: 8403 return; 8404 } 8405 } 8406} 8407 8408/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is 8409 * scheduled on a general queue in order to prevent a dead lock. 8410 */ 8411static void bnx2x_sp_rtnl_task(struct work_struct *work) 8412{ 8413 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); 8414 8415 rtnl_lock(); 8416 8417 if (!netif_running(bp->dev)) 8418 goto sp_rtnl_exit; 8419 8420 /* if stop on error is defined no recovery flows should be executed */ 8421#ifdef BNX2X_STOP_ON_ERROR 8422 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined " 8423 "so reset not done to allow debug dump,\n" 8424 "you will need to reboot when done\n"); 8425 goto sp_rtnl_not_reset; 8426#endif 8427 8428 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { 8429 /* 8430 * Clear all pending SP commands as we are going to reset the 8431 * function anyway. 8432 */ 8433 bp->sp_rtnl_state = 0; 8434 smp_mb(); 8435 8436 bnx2x_parity_recover(bp); 8437 8438 goto sp_rtnl_exit; 8439 } 8440 8441 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { 8442 /* 8443 * Clear all pending SP commands as we are going to reset the 8444 * function anyway. 8445 */ 8446 bp->sp_rtnl_state = 0; 8447 smp_mb(); 8448 8449 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 8450 bnx2x_nic_load(bp, LOAD_NORMAL); 8451 8452 goto sp_rtnl_exit; 8453 } 8454#ifdef BNX2X_STOP_ON_ERROR 8455sp_rtnl_not_reset: 8456#endif 8457 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) 8458 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); 8459 8460sp_rtnl_exit: 8461 rtnl_unlock(); 8462} 8463 8464/* end of nic load/unload */ 8465 8466static void bnx2x_period_task(struct work_struct *work) 8467{ 8468 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); 8469 8470 if (!netif_running(bp->dev)) 8471 goto period_task_exit; 8472 8473 if (CHIP_REV_IS_SLOW(bp)) { 8474 BNX2X_ERR("period task called on emulation, ignoring\n"); 8475 goto period_task_exit; 8476 } 8477 8478 bnx2x_acquire_phy_lock(bp); 8479 /* 8480 * The barrier is needed to ensure the ordering between the writing to 8481 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and 8482 * the reading here. 8483 */ 8484 smp_mb(); 8485 if (bp->port.pmf) { 8486 bnx2x_period_func(&bp->link_params, &bp->link_vars); 8487 8488 /* Re-queue task in 1 sec */ 8489 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); 8490 } 8491 8492 bnx2x_release_phy_lock(bp); 8493period_task_exit: 8494 return; 8495} 8496 8497/* 8498 * Init service functions 8499 */ 8500 8501static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) 8502{ 8503 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; 8504 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; 8505 return base + (BP_ABS_FUNC(bp)) * stride; 8506} 8507 8508static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) 8509{ 8510 u32 reg = bnx2x_get_pretend_reg(bp); 8511 8512 /* Flush all outstanding writes */ 8513 mmiowb(); 8514 8515 /* Pretend to be function 0 */ 8516 REG_WR(bp, reg, 0); 8517 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ 8518 8519 /* From now we are in the "like-E1" mode */ 8520 bnx2x_int_disable(bp); 8521 8522 /* Flush all outstanding writes */ 8523 mmiowb(); 8524 8525 /* Restore the original function */ 8526 REG_WR(bp, reg, BP_ABS_FUNC(bp)); 8527 REG_RD(bp, reg); 8528} 8529 8530static inline void bnx2x_undi_int_disable(struct bnx2x *bp) 8531{ 8532 if (CHIP_IS_E1(bp)) 8533 bnx2x_int_disable(bp); 8534 else 8535 bnx2x_undi_int_disable_e1h(bp); 8536} 8537 8538static void __devinit bnx2x_undi_unload(struct bnx2x *bp) 8539{ 8540 u32 val; 8541 8542 /* Check if there is any driver already loaded */ 8543 val = REG_RD(bp, MISC_REG_UNPREPARED); 8544 if (val == 0x1) { 8545 /* Check if it is the UNDI driver 8546 * UNDI driver initializes CID offset for normal bell to 0x7 8547 */ 8548 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); 8549 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 8550 if (val == 0x7) { 8551 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8552 /* save our pf_num */ 8553 int orig_pf_num = bp->pf_num; 8554 int port; 8555 u32 swap_en, swap_val, value; 8556 8557 /* clear the UNDI indication */ 8558 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 8559 8560 BNX2X_DEV_INFO("UNDI is active! reset device\n"); 8561 8562 /* try unload UNDI on port 0 */ 8563 bp->pf_num = 0; 8564 bp->fw_seq = 8565 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8566 DRV_MSG_SEQ_NUMBER_MASK); 8567 reset_code = bnx2x_fw_command(bp, reset_code, 0); 8568 8569 /* if UNDI is loaded on the other port */ 8570 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { 8571 8572 /* send "DONE" for previous unload */ 8573 bnx2x_fw_command(bp, 8574 DRV_MSG_CODE_UNLOAD_DONE, 0); 8575 8576 /* unload UNDI on port 1 */ 8577 bp->pf_num = 1; 8578 bp->fw_seq = 8579 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8580 DRV_MSG_SEQ_NUMBER_MASK); 8581 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8582 8583 bnx2x_fw_command(bp, reset_code, 0); 8584 } 8585 8586 /* now it's safe to release the lock */ 8587 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); 8588 8589 bnx2x_undi_int_disable(bp); 8590 port = BP_PORT(bp); 8591 8592 /* close input traffic and wait for it */ 8593 /* Do not rcv packets to BRB */ 8594 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK : 8595 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0); 8596 /* Do not direct rcv packets that are not for MCP to 8597 * the BRB */ 8598 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 8599 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 8600 /* clear AEU */ 8601 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8602 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0); 8603 msleep(10); 8604 8605 /* save NIG port swap info */ 8606 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 8607 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 8608 /* reset device */ 8609 REG_WR(bp, 8610 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8611 0xd3ffffff); 8612 8613 value = 0x1400; 8614 if (CHIP_IS_E3(bp)) { 8615 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 8616 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 8617 } 8618 8619 REG_WR(bp, 8620 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8621 value); 8622 8623 /* take the NIG out of reset and restore swap values */ 8624 REG_WR(bp, 8625 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 8626 MISC_REGISTERS_RESET_REG_1_RST_NIG); 8627 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val); 8628 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en); 8629 8630 /* send unload done to the MCP */ 8631 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 8632 8633 /* restore our func and fw_seq */ 8634 bp->pf_num = orig_pf_num; 8635 bp->fw_seq = 8636 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8637 DRV_MSG_SEQ_NUMBER_MASK); 8638 } else 8639 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); 8640 } 8641} 8642 8643static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) 8644{ 8645 u32 val, val2, val3, val4, id; 8646 u16 pmc; 8647 8648 /* Get the chip revision id and number. */ 8649 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 8650 val = REG_RD(bp, MISC_REG_CHIP_NUM); 8651 id = ((val & 0xffff) << 16); 8652 val = REG_RD(bp, MISC_REG_CHIP_REV); 8653 id |= ((val & 0xf) << 12); 8654 val = REG_RD(bp, MISC_REG_CHIP_METAL); 8655 id |= ((val & 0xff) << 4); 8656 val = REG_RD(bp, MISC_REG_BOND_ID); 8657 id |= (val & 0xf); 8658 bp->common.chip_id = id; 8659 8660 /* Set doorbell size */ 8661 bp->db_size = (1 << BNX2X_DB_SHIFT); 8662 8663 if (!CHIP_IS_E1x(bp)) { 8664 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 8665 if ((val & 1) == 0) 8666 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); 8667 else 8668 val = (val >> 1) & 1; 8669 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : 8670 "2_PORT_MODE"); 8671 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : 8672 CHIP_2_PORT_MODE; 8673 8674 if (CHIP_MODE_IS_4_PORT(bp)) 8675 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ 8676 else 8677 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ 8678 } else { 8679 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ 8680 bp->pfid = bp->pf_num; /* 0..7 */ 8681 } 8682 8683 bp->link_params.chip_id = bp->common.chip_id; 8684 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 8685 8686 val = (REG_RD(bp, 0x2874) & 0x55); 8687 if ((bp->common.chip_id & 0x1) || 8688 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { 8689 bp->flags |= ONE_PORT_FLAG; 8690 BNX2X_DEV_INFO("single port device\n"); 8691 } 8692 8693 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); 8694 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << 8695 (val & MCPR_NVM_CFG4_FLASH_SIZE)); 8696 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 8697 bp->common.flash_size, bp->common.flash_size); 8698 8699 bnx2x_init_shmem(bp); 8700 8701 8702 8703 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? 8704 MISC_REG_GENERIC_CR_1 : 8705 MISC_REG_GENERIC_CR_0)); 8706 8707 bp->link_params.shmem_base = bp->common.shmem_base; 8708 bp->link_params.shmem2_base = bp->common.shmem2_base; 8709 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 8710 bp->common.shmem_base, bp->common.shmem2_base); 8711 8712 if (!bp->common.shmem_base) { 8713 BNX2X_DEV_INFO("MCP not active\n"); 8714 bp->flags |= NO_MCP_FLAG; 8715 return; 8716 } 8717 8718 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 8719 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 8720 8721 bp->link_params.hw_led_mode = ((bp->common.hw_config & 8722 SHARED_HW_CFG_LED_MODE_MASK) >> 8723 SHARED_HW_CFG_LED_MODE_SHIFT); 8724 8725 bp->link_params.feature_config_flags = 0; 8726 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); 8727 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) 8728 bp->link_params.feature_config_flags |= 8729 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 8730 else 8731 bp->link_params.feature_config_flags &= 8732 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 8733 8734 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 8735 bp->common.bc_ver = val; 8736 BNX2X_DEV_INFO("bc_ver %X\n", val); 8737 if (val < BNX2X_BC_VER) { 8738 /* for now only warn 8739 * later we might need to enforce this */ 8740 BNX2X_ERR("This driver needs bc_ver %X but found %X, " 8741 "please upgrade BC\n", BNX2X_BC_VER, val); 8742 } 8743 bp->link_params.feature_config_flags |= 8744 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 8745 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 8746 8747 bp->link_params.feature_config_flags |= 8748 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? 8749 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; 8750 8751 bp->link_params.feature_config_flags |= 8752 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? 8753 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; 8754 8755 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); 8756 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; 8757 8758 BNX2X_DEV_INFO("%sWoL capable\n", 8759 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 8760 8761 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 8762 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 8763 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); 8764 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); 8765 8766 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", 8767 val, val2, val3, val4); 8768} 8769 8770#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 8771#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 8772 8773static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) 8774{ 8775 int pfid = BP_FUNC(bp); 8776 int vn = BP_E1HVN(bp); 8777 int igu_sb_id; 8778 u32 val; 8779 u8 fid, igu_sb_cnt = 0; 8780 8781 bp->igu_base_sb = 0xff; 8782 if (CHIP_INT_MODE_IS_BC(bp)) { 8783 igu_sb_cnt = bp->igu_sb_cnt; 8784 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 8785 FP_SB_MAX_E1x; 8786 8787 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + 8788 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); 8789 8790 return; 8791 } 8792 8793 /* IGU in normal mode - read CAM */ 8794 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 8795 igu_sb_id++) { 8796 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 8797 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 8798 continue; 8799 fid = IGU_FID(val); 8800 if ((fid & IGU_FID_ENCODE_IS_PF)) { 8801 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) 8802 continue; 8803 if (IGU_VEC(val) == 0) 8804 /* default status block */ 8805 bp->igu_dsb_id = igu_sb_id; 8806 else { 8807 if (bp->igu_base_sb == 0xff) 8808 bp->igu_base_sb = igu_sb_id; 8809 igu_sb_cnt++; 8810 } 8811 } 8812 } 8813 8814#ifdef CONFIG_PCI_MSI 8815 /* 8816 * It's expected that number of CAM entries for this functions is equal 8817 * to the number evaluated based on the MSI-X table size. We want a 8818 * harsh warning if these values are different! 8819 */ 8820 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); 8821#endif 8822 8823 if (igu_sb_cnt == 0) 8824 BNX2X_ERR("CAM configuration error\n"); 8825} 8826 8827static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, 8828 u32 switch_cfg) 8829{ 8830 int cfg_size = 0, idx, port = BP_PORT(bp); 8831 8832 /* Aggregation of supported attributes of all external phys */ 8833 bp->port.supported[0] = 0; 8834 bp->port.supported[1] = 0; 8835 switch (bp->link_params.num_phys) { 8836 case 1: 8837 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; 8838 cfg_size = 1; 8839 break; 8840 case 2: 8841 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; 8842 cfg_size = 1; 8843 break; 8844 case 3: 8845 if (bp->link_params.multi_phy_config & 8846 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 8847 bp->port.supported[1] = 8848 bp->link_params.phy[EXT_PHY1].supported; 8849 bp->port.supported[0] = 8850 bp->link_params.phy[EXT_PHY2].supported; 8851 } else { 8852 bp->port.supported[0] = 8853 bp->link_params.phy[EXT_PHY1].supported; 8854 bp->port.supported[1] = 8855 bp->link_params.phy[EXT_PHY2].supported; 8856 } 8857 cfg_size = 2; 8858 break; 8859 } 8860 8861 if (!(bp->port.supported[0] || bp->port.supported[1])) { 8862 BNX2X_ERR("NVRAM config error. BAD phy config." 8863 "PHY1 config 0x%x, PHY2 config 0x%x\n", 8864 SHMEM_RD(bp, 8865 dev_info.port_hw_config[port].external_phy_config), 8866 SHMEM_RD(bp, 8867 dev_info.port_hw_config[port].external_phy_config2)); 8868 return; 8869 } 8870 8871 if (CHIP_IS_E3(bp)) 8872 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); 8873 else { 8874 switch (switch_cfg) { 8875 case SWITCH_CFG_1G: 8876 bp->port.phy_addr = REG_RD( 8877 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 8878 break; 8879 case SWITCH_CFG_10G: 8880 bp->port.phy_addr = REG_RD( 8881 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 8882 break; 8883 default: 8884 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 8885 bp->port.link_config[0]); 8886 return; 8887 } 8888 } 8889 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 8890 /* mask what we support according to speed_cap_mask per configuration */ 8891 for (idx = 0; idx < cfg_size; idx++) { 8892 if (!(bp->link_params.speed_cap_mask[idx] & 8893 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 8894 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; 8895 8896 if (!(bp->link_params.speed_cap_mask[idx] & 8897 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 8898 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; 8899 8900 if (!(bp->link_params.speed_cap_mask[idx] & 8901 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 8902 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; 8903 8904 if (!(bp->link_params.speed_cap_mask[idx] & 8905 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 8906 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; 8907 8908 if (!(bp->link_params.speed_cap_mask[idx] & 8909 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 8910 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | 8911 SUPPORTED_1000baseT_Full); 8912 8913 if (!(bp->link_params.speed_cap_mask[idx] & 8914 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 8915 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; 8916 8917 if (!(bp->link_params.speed_cap_mask[idx] & 8918 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 8919 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; 8920 8921 } 8922 8923 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], 8924 bp->port.supported[1]); 8925} 8926 8927static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) 8928{ 8929 u32 link_config, idx, cfg_size = 0; 8930 bp->port.advertising[0] = 0; 8931 bp->port.advertising[1] = 0; 8932 switch (bp->link_params.num_phys) { 8933 case 1: 8934 case 2: 8935 cfg_size = 1; 8936 break; 8937 case 3: 8938 cfg_size = 2; 8939 break; 8940 } 8941 for (idx = 0; idx < cfg_size; idx++) { 8942 bp->link_params.req_duplex[idx] = DUPLEX_FULL; 8943 link_config = bp->port.link_config[idx]; 8944 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 8945 case PORT_FEATURE_LINK_SPEED_AUTO: 8946 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { 8947 bp->link_params.req_line_speed[idx] = 8948 SPEED_AUTO_NEG; 8949 bp->port.advertising[idx] |= 8950 bp->port.supported[idx]; 8951 } else { 8952 /* force 10G, no AN */ 8953 bp->link_params.req_line_speed[idx] = 8954 SPEED_10000; 8955 bp->port.advertising[idx] |= 8956 (ADVERTISED_10000baseT_Full | 8957 ADVERTISED_FIBRE); 8958 continue; 8959 } 8960 break; 8961 8962 case PORT_FEATURE_LINK_SPEED_10M_FULL: 8963 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { 8964 bp->link_params.req_line_speed[idx] = 8965 SPEED_10; 8966 bp->port.advertising[idx] |= 8967 (ADVERTISED_10baseT_Full | 8968 ADVERTISED_TP); 8969 } else { 8970 BNX2X_ERR("NVRAM config error. " 8971 "Invalid link_config 0x%x" 8972 " speed_cap_mask 0x%x\n", 8973 link_config, 8974 bp->link_params.speed_cap_mask[idx]); 8975 return; 8976 } 8977 break; 8978 8979 case PORT_FEATURE_LINK_SPEED_10M_HALF: 8980 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { 8981 bp->link_params.req_line_speed[idx] = 8982 SPEED_10; 8983 bp->link_params.req_duplex[idx] = 8984 DUPLEX_HALF; 8985 bp->port.advertising[idx] |= 8986 (ADVERTISED_10baseT_Half | 8987 ADVERTISED_TP); 8988 } else { 8989 BNX2X_ERR("NVRAM config error. " 8990 "Invalid link_config 0x%x" 8991 " speed_cap_mask 0x%x\n", 8992 link_config, 8993 bp->link_params.speed_cap_mask[idx]); 8994 return; 8995 } 8996 break; 8997 8998 case PORT_FEATURE_LINK_SPEED_100M_FULL: 8999 if (bp->port.supported[idx] & 9000 SUPPORTED_100baseT_Full) { 9001 bp->link_params.req_line_speed[idx] = 9002 SPEED_100; 9003 bp->port.advertising[idx] |= 9004 (ADVERTISED_100baseT_Full | 9005 ADVERTISED_TP); 9006 } else { 9007 BNX2X_ERR("NVRAM config error. " 9008 "Invalid link_config 0x%x" 9009 " speed_cap_mask 0x%x\n", 9010 link_config, 9011 bp->link_params.speed_cap_mask[idx]); 9012 return; 9013 } 9014 break; 9015 9016 case PORT_FEATURE_LINK_SPEED_100M_HALF: 9017 if (bp->port.supported[idx] & 9018 SUPPORTED_100baseT_Half) { 9019 bp->link_params.req_line_speed[idx] = 9020 SPEED_100; 9021 bp->link_params.req_duplex[idx] = 9022 DUPLEX_HALF; 9023 bp->port.advertising[idx] |= 9024 (ADVERTISED_100baseT_Half | 9025 ADVERTISED_TP); 9026 } else { 9027 BNX2X_ERR("NVRAM config error. " 9028 "Invalid link_config 0x%x" 9029 " speed_cap_mask 0x%x\n", 9030 link_config, 9031 bp->link_params.speed_cap_mask[idx]); 9032 return; 9033 } 9034 break; 9035 9036 case PORT_FEATURE_LINK_SPEED_1G: 9037 if (bp->port.supported[idx] & 9038 SUPPORTED_1000baseT_Full) { 9039 bp->link_params.req_line_speed[idx] = 9040 SPEED_1000; 9041 bp->port.advertising[idx] |= 9042 (ADVERTISED_1000baseT_Full | 9043 ADVERTISED_TP); 9044 } else { 9045 BNX2X_ERR("NVRAM config error. " 9046 "Invalid link_config 0x%x" 9047 " speed_cap_mask 0x%x\n", 9048 link_config, 9049 bp->link_params.speed_cap_mask[idx]); 9050 return; 9051 } 9052 break; 9053 9054 case PORT_FEATURE_LINK_SPEED_2_5G: 9055 if (bp->port.supported[idx] & 9056 SUPPORTED_2500baseX_Full) { 9057 bp->link_params.req_line_speed[idx] = 9058 SPEED_2500; 9059 bp->port.advertising[idx] |= 9060 (ADVERTISED_2500baseX_Full | 9061 ADVERTISED_TP); 9062 } else { 9063 BNX2X_ERR("NVRAM config error. " 9064 "Invalid link_config 0x%x" 9065 " speed_cap_mask 0x%x\n", 9066 link_config, 9067 bp->link_params.speed_cap_mask[idx]); 9068 return; 9069 } 9070 break; 9071 9072 case PORT_FEATURE_LINK_SPEED_10G_CX4: 9073 if (bp->port.supported[idx] & 9074 SUPPORTED_10000baseT_Full) { 9075 bp->link_params.req_line_speed[idx] = 9076 SPEED_10000; 9077 bp->port.advertising[idx] |= 9078 (ADVERTISED_10000baseT_Full | 9079 ADVERTISED_FIBRE); 9080 } else { 9081 BNX2X_ERR("NVRAM config error. " 9082 "Invalid link_config 0x%x" 9083 " speed_cap_mask 0x%x\n", 9084 link_config, 9085 bp->link_params.speed_cap_mask[idx]); 9086 return; 9087 } 9088 break; 9089 case PORT_FEATURE_LINK_SPEED_20G: 9090 bp->link_params.req_line_speed[idx] = SPEED_20000; 9091 9092 break; 9093 default: 9094 BNX2X_ERR("NVRAM config error. " 9095 "BAD link speed link_config 0x%x\n", 9096 link_config); 9097 bp->link_params.req_line_speed[idx] = 9098 SPEED_AUTO_NEG; 9099 bp->port.advertising[idx] = 9100 bp->port.supported[idx]; 9101 break; 9102 } 9103 9104 bp->link_params.req_flow_ctrl[idx] = (link_config & 9105 PORT_FEATURE_FLOW_CONTROL_MASK); 9106 if ((bp->link_params.req_flow_ctrl[idx] == 9107 BNX2X_FLOW_CTRL_AUTO) && 9108 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { 9109 bp->link_params.req_flow_ctrl[idx] = 9110 BNX2X_FLOW_CTRL_NONE; 9111 } 9112 9113 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl" 9114 " 0x%x advertising 0x%x\n", 9115 bp->link_params.req_line_speed[idx], 9116 bp->link_params.req_duplex[idx], 9117 bp->link_params.req_flow_ctrl[idx], 9118 bp->port.advertising[idx]); 9119 } 9120} 9121 9122static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 9123{ 9124 mac_hi = cpu_to_be16(mac_hi); 9125 mac_lo = cpu_to_be32(mac_lo); 9126 memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); 9127 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); 9128} 9129 9130static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) 9131{ 9132 int port = BP_PORT(bp); 9133 u32 config; 9134 u32 ext_phy_type, ext_phy_config; 9135 9136 bp->link_params.bp = bp; 9137 bp->link_params.port = port; 9138 9139 bp->link_params.lane_config = 9140 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 9141 9142 bp->link_params.speed_cap_mask[0] = 9143 SHMEM_RD(bp, 9144 dev_info.port_hw_config[port].speed_capability_mask); 9145 bp->link_params.speed_cap_mask[1] = 9146 SHMEM_RD(bp, 9147 dev_info.port_hw_config[port].speed_capability_mask2); 9148 bp->port.link_config[0] = 9149 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 9150 9151 bp->port.link_config[1] = 9152 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); 9153 9154 bp->link_params.multi_phy_config = 9155 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); 9156 /* If the device is capable of WoL, set the default state according 9157 * to the HW 9158 */ 9159 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 9160 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 9161 (config & PORT_FEATURE_WOL_ENABLED)); 9162 9163 BNX2X_DEV_INFO("lane_config 0x%08x " 9164 "speed_cap_mask0 0x%08x link_config0 0x%08x\n", 9165 bp->link_params.lane_config, 9166 bp->link_params.speed_cap_mask[0], 9167 bp->port.link_config[0]); 9168 9169 bp->link_params.switch_cfg = (bp->port.link_config[0] & 9170 PORT_FEATURE_CONNECTED_SWITCH_MASK); 9171 bnx2x_phy_probe(&bp->link_params); 9172 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 9173 9174 bnx2x_link_settings_requested(bp); 9175 9176 /* 9177 * If connected directly, work with the internal PHY, otherwise, work 9178 * with the external PHY 9179 */ 9180 ext_phy_config = 9181 SHMEM_RD(bp, 9182 dev_info.port_hw_config[port].external_phy_config); 9183 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 9184 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 9185 bp->mdio.prtad = bp->port.phy_addr; 9186 9187 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 9188 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 9189 bp->mdio.prtad = 9190 XGXS_EXT_PHY_ADDR(ext_phy_config); 9191 9192 /* 9193 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) 9194 * In MF mode, it is set to cover self test cases 9195 */ 9196 if (IS_MF(bp)) 9197 bp->port.need_hw_lock = 1; 9198 else 9199 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, 9200 bp->common.shmem_base, 9201 bp->common.shmem2_base); 9202} 9203 9204#ifdef BCM_CNIC 9205static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) 9206{ 9207 int port = BP_PORT(bp); 9208 int func = BP_ABS_FUNC(bp); 9209 9210 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9211 drv_lic_key[port].max_iscsi_conn); 9212 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9213 drv_lic_key[port].max_fcoe_conn); 9214 9215 /* Get the number of maximum allowed iSCSI and FCoE connections */ 9216 bp->cnic_eth_dev.max_iscsi_conn = 9217 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> 9218 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; 9219 9220 bp->cnic_eth_dev.max_fcoe_conn = 9221 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> 9222 BNX2X_MAX_FCOE_INIT_CONN_SHIFT; 9223 9224 /* Read the WWN: */ 9225 if (!IS_MF(bp)) { 9226 /* Port info */ 9227 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9228 SHMEM_RD(bp, 9229 dev_info.port_hw_config[port]. 9230 fcoe_wwn_port_name_upper); 9231 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9232 SHMEM_RD(bp, 9233 dev_info.port_hw_config[port]. 9234 fcoe_wwn_port_name_lower); 9235 9236 /* Node info */ 9237 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9238 SHMEM_RD(bp, 9239 dev_info.port_hw_config[port]. 9240 fcoe_wwn_node_name_upper); 9241 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9242 SHMEM_RD(bp, 9243 dev_info.port_hw_config[port]. 9244 fcoe_wwn_node_name_lower); 9245 } else if (!IS_MF_SD(bp)) { 9246 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9247 9248 /* 9249 * Read the WWN info only if the FCoE feature is enabled for 9250 * this function. 9251 */ 9252 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9253 /* Port info */ 9254 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9255 MF_CFG_RD(bp, func_ext_config[func]. 9256 fcoe_wwn_port_name_upper); 9257 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9258 MF_CFG_RD(bp, func_ext_config[func]. 9259 fcoe_wwn_port_name_lower); 9260 9261 /* Node info */ 9262 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9263 MF_CFG_RD(bp, func_ext_config[func]. 9264 fcoe_wwn_node_name_upper); 9265 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9266 MF_CFG_RD(bp, func_ext_config[func]. 9267 fcoe_wwn_node_name_lower); 9268 } 9269 } 9270 9271 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n", 9272 bp->cnic_eth_dev.max_iscsi_conn, 9273 bp->cnic_eth_dev.max_fcoe_conn); 9274 9275 /* 9276 * If maximum allowed number of connections is zero - 9277 * disable the feature. 9278 */ 9279 if (!bp->cnic_eth_dev.max_iscsi_conn) 9280 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 9281 9282 if (!bp->cnic_eth_dev.max_fcoe_conn) 9283 bp->flags |= NO_FCOE_FLAG; 9284} 9285#endif 9286 9287static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) 9288{ 9289 u32 val, val2; 9290 int func = BP_ABS_FUNC(bp); 9291 int port = BP_PORT(bp); 9292#ifdef BCM_CNIC 9293 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; 9294 u8 *fip_mac = bp->fip_mac; 9295#endif 9296 9297 /* Zero primary MAC configuration */ 9298 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9299 9300 if (BP_NOMCP(bp)) { 9301 BNX2X_ERROR("warning: random MAC workaround active\n"); 9302 random_ether_addr(bp->dev->dev_addr); 9303 } else if (IS_MF(bp)) { 9304 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 9305 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); 9306 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && 9307 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) 9308 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9309 9310#ifdef BCM_CNIC 9311 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or 9312 * FCoE MAC then the appropriate feature should be disabled. 9313 */ 9314 if (IS_MF_SI(bp)) { 9315 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9316 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 9317 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9318 iscsi_mac_addr_upper); 9319 val = MF_CFG_RD(bp, func_ext_config[func]. 9320 iscsi_mac_addr_lower); 9321 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9322 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9323 iscsi_mac); 9324 } else 9325 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 9326 9327 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9328 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9329 fcoe_mac_addr_upper); 9330 val = MF_CFG_RD(bp, func_ext_config[func]. 9331 fcoe_mac_addr_lower); 9332 bnx2x_set_mac_buf(fip_mac, val, val2); 9333 BNX2X_DEV_INFO("Read FCoE L2 MAC to %pM\n", 9334 fip_mac); 9335 9336 } else 9337 bp->flags |= NO_FCOE_FLAG; 9338 } 9339#endif 9340 } else { 9341 /* in SF read MACs from port configuration */ 9342 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 9343 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 9344 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9345 9346#ifdef BCM_CNIC 9347 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9348 iscsi_mac_upper); 9349 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9350 iscsi_mac_lower); 9351 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9352 9353 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9354 fcoe_fip_mac_upper); 9355 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9356 fcoe_fip_mac_lower); 9357 bnx2x_set_mac_buf(fip_mac, val, val2); 9358#endif 9359 } 9360 9361 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 9362 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); 9363 9364#ifdef BCM_CNIC 9365 /* Set the FCoE MAC in MF_SD mode */ 9366 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp)) 9367 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); 9368 9369 /* Disable iSCSI if MAC configuration is 9370 * invalid. 9371 */ 9372 if (!is_valid_ether_addr(iscsi_mac)) { 9373 bp->flags |= NO_ISCSI_FLAG; 9374 memset(iscsi_mac, 0, ETH_ALEN); 9375 } 9376 9377 /* Disable FCoE if MAC configuration is 9378 * invalid. 9379 */ 9380 if (!is_valid_ether_addr(fip_mac)) { 9381 bp->flags |= NO_FCOE_FLAG; 9382 memset(bp->fip_mac, 0, ETH_ALEN); 9383 } 9384#endif 9385 9386 if (!is_valid_ether_addr(bp->dev->dev_addr)) 9387 dev_err(&bp->pdev->dev, 9388 "bad Ethernet MAC address configuration: " 9389 "%pM, change it manually before bringing up " 9390 "the appropriate network interface\n", 9391 bp->dev->dev_addr); 9392} 9393 9394static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) 9395{ 9396 int /*abs*/func = BP_ABS_FUNC(bp); 9397 int vn; 9398 u32 val = 0; 9399 int rc = 0; 9400 9401 bnx2x_get_common_hwinfo(bp); 9402 9403 /* 9404 * initialize IGU parameters 9405 */ 9406 if (CHIP_IS_E1x(bp)) { 9407 bp->common.int_block = INT_BLOCK_HC; 9408 9409 bp->igu_dsb_id = DEF_SB_IGU_ID; 9410 bp->igu_base_sb = 0; 9411 } else { 9412 bp->common.int_block = INT_BLOCK_IGU; 9413 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 9414 9415 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9416 int tout = 5000; 9417 9418 BNX2X_DEV_INFO("FORCING Normal Mode\n"); 9419 9420 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 9421 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); 9422 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); 9423 9424 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9425 tout--; 9426 usleep_range(1000, 1000); 9427 } 9428 9429 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9430 dev_err(&bp->pdev->dev, 9431 "FORCING Normal Mode failed!!!\n"); 9432 return -EPERM; 9433 } 9434 } 9435 9436 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9437 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); 9438 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; 9439 } else 9440 BNX2X_DEV_INFO("IGU Normal Mode\n"); 9441 9442 bnx2x_get_igu_cam_info(bp); 9443 9444 } 9445 9446 /* 9447 * set base FW non-default (fast path) status block id, this value is 9448 * used to initialize the fw_sb_id saved on the fp/queue structure to 9449 * determine the id used by the FW. 9450 */ 9451 if (CHIP_IS_E1x(bp)) 9452 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); 9453 else /* 9454 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of 9455 * the same queue are indicated on the same IGU SB). So we prefer 9456 * FW and IGU SBs to be the same value. 9457 */ 9458 bp->base_fw_ndsb = bp->igu_base_sb; 9459 9460 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" 9461 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, 9462 bp->igu_sb_cnt, bp->base_fw_ndsb); 9463 9464 /* 9465 * Initialize MF configuration 9466 */ 9467 9468 bp->mf_ov = 0; 9469 bp->mf_mode = 0; 9470 vn = BP_E1HVN(bp); 9471 9472 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 9473 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 9474 bp->common.shmem2_base, SHMEM2_RD(bp, size), 9475 (u32)offsetof(struct shmem2_region, mf_cfg_addr)); 9476 9477 if (SHMEM2_HAS(bp, mf_cfg_addr)) 9478 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); 9479 else 9480 bp->common.mf_cfg_base = bp->common.shmem_base + 9481 offsetof(struct shmem_region, func_mb) + 9482 E1H_FUNC_MAX * sizeof(struct drv_func_mb); 9483 /* 9484 * get mf configuration: 9485 * 1. existence of MF configuration 9486 * 2. MAC address must be legal (check only upper bytes) 9487 * for Switch-Independent mode; 9488 * OVLAN must be legal for Switch-Dependent mode 9489 * 3. SF_MODE configures specific MF mode 9490 */ 9491 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9492 /* get mf configuration */ 9493 val = SHMEM_RD(bp, 9494 dev_info.shared_feature_config.config); 9495 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; 9496 9497 switch (val) { 9498 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 9499 val = MF_CFG_RD(bp, func_mf_config[func]. 9500 mac_upper); 9501 /* check for legal mac (upper bytes)*/ 9502 if (val != 0xffff) { 9503 bp->mf_mode = MULTI_FUNCTION_SI; 9504 bp->mf_config[vn] = MF_CFG_RD(bp, 9505 func_mf_config[func].config); 9506 } else 9507 BNX2X_DEV_INFO("illegal MAC address " 9508 "for SI\n"); 9509 break; 9510 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 9511 /* get OV configuration */ 9512 val = MF_CFG_RD(bp, 9513 func_mf_config[FUNC_0].e1hov_tag); 9514 val &= FUNC_MF_CFG_E1HOV_TAG_MASK; 9515 9516 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9517 bp->mf_mode = MULTI_FUNCTION_SD; 9518 bp->mf_config[vn] = MF_CFG_RD(bp, 9519 func_mf_config[func].config); 9520 } else 9521 BNX2X_DEV_INFO("illegal OV for SD\n"); 9522 break; 9523 default: 9524 /* Unknown configuration: reset mf_config */ 9525 bp->mf_config[vn] = 0; 9526 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val); 9527 } 9528 } 9529 9530 BNX2X_DEV_INFO("%s function mode\n", 9531 IS_MF(bp) ? "multi" : "single"); 9532 9533 switch (bp->mf_mode) { 9534 case MULTI_FUNCTION_SD: 9535 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 9536 FUNC_MF_CFG_E1HOV_TAG_MASK; 9537 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9538 bp->mf_ov = val; 9539 bp->path_has_ovlan = true; 9540 9541 BNX2X_DEV_INFO("MF OV for func %d is %d " 9542 "(0x%04x)\n", func, bp->mf_ov, 9543 bp->mf_ov); 9544 } else { 9545 dev_err(&bp->pdev->dev, 9546 "No valid MF OV for func %d, " 9547 "aborting\n", func); 9548 return -EPERM; 9549 } 9550 break; 9551 case MULTI_FUNCTION_SI: 9552 BNX2X_DEV_INFO("func %d is in MF " 9553 "switch-independent mode\n", func); 9554 break; 9555 default: 9556 if (vn) { 9557 dev_err(&bp->pdev->dev, 9558 "VN %d is in a single function mode, " 9559 "aborting\n", vn); 9560 return -EPERM; 9561 } 9562 break; 9563 } 9564 9565 /* check if other port on the path needs ovlan: 9566 * Since MF configuration is shared between ports 9567 * Possible mixed modes are only 9568 * {SF, SI} {SF, SD} {SD, SF} {SI, SF} 9569 */ 9570 if (CHIP_MODE_IS_4_PORT(bp) && 9571 !bp->path_has_ovlan && 9572 !IS_MF(bp) && 9573 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9574 u8 other_port = !BP_PORT(bp); 9575 u8 other_func = BP_PATH(bp) + 2*other_port; 9576 val = MF_CFG_RD(bp, 9577 func_mf_config[other_func].e1hov_tag); 9578 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) 9579 bp->path_has_ovlan = true; 9580 } 9581 } 9582 9583 /* adjust igu_sb_cnt to MF for E1x */ 9584 if (CHIP_IS_E1x(bp) && IS_MF(bp)) 9585 bp->igu_sb_cnt /= E1HVN_MAX; 9586 9587 /* port info */ 9588 bnx2x_get_port_hwinfo(bp); 9589 9590 if (!BP_NOMCP(bp)) { 9591 bp->fw_seq = 9592 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 9593 DRV_MSG_SEQ_NUMBER_MASK); 9594 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 9595 } 9596 9597 /* Get MAC addresses */ 9598 bnx2x_get_mac_hwinfo(bp); 9599 9600#ifdef BCM_CNIC 9601 bnx2x_get_cnic_info(bp); 9602#endif 9603 9604 /* Get current FW pulse sequence */ 9605 if (!BP_NOMCP(bp)) { 9606 int mb_idx = BP_FW_MB_IDX(bp); 9607 9608 bp->fw_drv_pulse_wr_seq = 9609 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) & 9610 DRV_PULSE_SEQ_MASK); 9611 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq); 9612 } 9613 9614 return rc; 9615} 9616 9617static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) 9618{ 9619 int cnt, i, block_end, rodi; 9620 char vpd_data[BNX2X_VPD_LEN+1]; 9621 char str_id_reg[VENDOR_ID_LEN+1]; 9622 char str_id_cap[VENDOR_ID_LEN+1]; 9623 u8 len; 9624 9625 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data); 9626 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); 9627 9628 if (cnt < BNX2X_VPD_LEN) 9629 goto out_not_found; 9630 9631 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN, 9632 PCI_VPD_LRDT_RO_DATA); 9633 if (i < 0) 9634 goto out_not_found; 9635 9636 9637 block_end = i + PCI_VPD_LRDT_TAG_SIZE + 9638 pci_vpd_lrdt_size(&vpd_data[i]); 9639 9640 i += PCI_VPD_LRDT_TAG_SIZE; 9641 9642 if (block_end > BNX2X_VPD_LEN) 9643 goto out_not_found; 9644 9645 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 9646 PCI_VPD_RO_KEYWORD_MFR_ID); 9647 if (rodi < 0) 9648 goto out_not_found; 9649 9650 len = pci_vpd_info_field_size(&vpd_data[rodi]); 9651 9652 if (len != VENDOR_ID_LEN) 9653 goto out_not_found; 9654 9655 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 9656 9657 /* vendor specific info */ 9658 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); 9659 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); 9660 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || 9661 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { 9662 9663 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 9664 PCI_VPD_RO_KEYWORD_VENDOR0); 9665 if (rodi >= 0) { 9666 len = pci_vpd_info_field_size(&vpd_data[rodi]); 9667 9668 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 9669 9670 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { 9671 memcpy(bp->fw_ver, &vpd_data[rodi], len); 9672 bp->fw_ver[len] = ' '; 9673 } 9674 } 9675 return; 9676 } 9677out_not_found: 9678 return; 9679} 9680 9681static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) 9682{ 9683 u32 flags = 0; 9684 9685 if (CHIP_REV_IS_FPGA(bp)) 9686 SET_FLAGS(flags, MODE_FPGA); 9687 else if (CHIP_REV_IS_EMUL(bp)) 9688 SET_FLAGS(flags, MODE_EMUL); 9689 else 9690 SET_FLAGS(flags, MODE_ASIC); 9691 9692 if (CHIP_MODE_IS_4_PORT(bp)) 9693 SET_FLAGS(flags, MODE_PORT4); 9694 else 9695 SET_FLAGS(flags, MODE_PORT2); 9696 9697 if (CHIP_IS_E2(bp)) 9698 SET_FLAGS(flags, MODE_E2); 9699 else if (CHIP_IS_E3(bp)) { 9700 SET_FLAGS(flags, MODE_E3); 9701 if (CHIP_REV(bp) == CHIP_REV_Ax) 9702 SET_FLAGS(flags, MODE_E3_A0); 9703 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ 9704 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 9705 } 9706 9707 if (IS_MF(bp)) { 9708 SET_FLAGS(flags, MODE_MF); 9709 switch (bp->mf_mode) { 9710 case MULTI_FUNCTION_SD: 9711 SET_FLAGS(flags, MODE_MF_SD); 9712 break; 9713 case MULTI_FUNCTION_SI: 9714 SET_FLAGS(flags, MODE_MF_SI); 9715 break; 9716 } 9717 } else 9718 SET_FLAGS(flags, MODE_SF); 9719 9720#if defined(__LITTLE_ENDIAN) 9721 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 9722#else /*(__BIG_ENDIAN)*/ 9723 SET_FLAGS(flags, MODE_BIG_ENDIAN); 9724#endif 9725 INIT_MODE_FLAGS(bp) = flags; 9726} 9727 9728static int __devinit bnx2x_init_bp(struct bnx2x *bp) 9729{ 9730 int func; 9731 int timer_interval; 9732 int rc; 9733 9734 mutex_init(&bp->port.phy_mutex); 9735 mutex_init(&bp->fw_mb_mutex); 9736 spin_lock_init(&bp->stats_lock); 9737#ifdef BCM_CNIC 9738 mutex_init(&bp->cnic_mutex); 9739#endif 9740 9741 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); 9742 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); 9743 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); 9744 rc = bnx2x_get_hwinfo(bp); 9745 if (rc) 9746 return rc; 9747 9748 bnx2x_set_modes_bitmap(bp); 9749 9750 rc = bnx2x_alloc_mem_bp(bp); 9751 if (rc) 9752 return rc; 9753 9754 bnx2x_read_fwinfo(bp); 9755 9756 func = BP_FUNC(bp); 9757 9758 /* need to reset chip if undi was active */ 9759 if (!BP_NOMCP(bp)) 9760 bnx2x_undi_unload(bp); 9761 9762 if (CHIP_REV_IS_FPGA(bp)) 9763 dev_err(&bp->pdev->dev, "FPGA detected\n"); 9764 9765 if (BP_NOMCP(bp) && (func == 0)) 9766 dev_err(&bp->pdev->dev, "MCP disabled, " 9767 "must load devices in order!\n"); 9768 9769 bp->multi_mode = multi_mode; 9770 9771 /* Set TPA flags */ 9772 if (disable_tpa) { 9773 bp->flags &= ~TPA_ENABLE_FLAG; 9774 bp->dev->features &= ~NETIF_F_LRO; 9775 } else { 9776 bp->flags |= TPA_ENABLE_FLAG; 9777 bp->dev->features |= NETIF_F_LRO; 9778 } 9779 bp->disable_tpa = disable_tpa; 9780 9781 if (CHIP_IS_E1(bp)) 9782 bp->dropless_fc = 0; 9783 else 9784 bp->dropless_fc = dropless_fc; 9785 9786 bp->mrrs = mrrs; 9787 9788 bp->tx_ring_size = MAX_TX_AVAIL; 9789 9790 /* make sure that the numbers are in the right granularity */ 9791 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; 9792 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; 9793 9794 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ); 9795 bp->current_interval = (poll ? poll : timer_interval); 9796 9797 init_timer(&bp->timer); 9798 bp->timer.expires = jiffies + bp->current_interval; 9799 bp->timer.data = (unsigned long) bp; 9800 bp->timer.function = bnx2x_timer; 9801 9802 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); 9803 bnx2x_dcbx_init_params(bp); 9804 9805#ifdef BCM_CNIC 9806 if (CHIP_IS_E1x(bp)) 9807 bp->cnic_base_cl_id = FP_SB_MAX_E1x; 9808 else 9809 bp->cnic_base_cl_id = FP_SB_MAX_E2; 9810#endif 9811 9812 /* multiple tx priority */ 9813 if (CHIP_IS_E1x(bp)) 9814 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; 9815 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) 9816 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; 9817 if (CHIP_IS_E3B0(bp)) 9818 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; 9819 9820 return rc; 9821} 9822 9823 9824/**************************************************************************** 9825* General service functions 9826****************************************************************************/ 9827 9828/* 9829 * net_device service functions 9830 */ 9831 9832/* called with rtnl_lock */ 9833static int bnx2x_open(struct net_device *dev) 9834{ 9835 struct bnx2x *bp = netdev_priv(dev); 9836 bool global = false; 9837 int other_engine = BP_PATH(bp) ? 0 : 1; 9838 u32 other_load_counter, load_counter; 9839 9840 netif_carrier_off(dev); 9841 9842 bnx2x_set_power_state(bp, PCI_D0); 9843 9844 other_load_counter = bnx2x_get_load_cnt(bp, other_engine); 9845 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp)); 9846 9847 /* 9848 * If parity had happen during the unload, then attentions 9849 * and/or RECOVERY_IN_PROGRES may still be set. In this case we 9850 * want the first function loaded on the current engine to 9851 * complete the recovery. 9852 */ 9853 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 9854 bnx2x_chk_parity_attn(bp, &global, true)) 9855 do { 9856 /* 9857 * If there are attentions and they are in a global 9858 * blocks, set the GLOBAL_RESET bit regardless whether 9859 * it will be this function that will complete the 9860 * recovery or not. 9861 */ 9862 if (global) 9863 bnx2x_set_reset_global(bp); 9864 9865 /* 9866 * Only the first function on the current engine should 9867 * try to recover in open. In case of attentions in 9868 * global blocks only the first in the chip should try 9869 * to recover. 9870 */ 9871 if ((!load_counter && 9872 (!global || !other_load_counter)) && 9873 bnx2x_trylock_leader_lock(bp) && 9874 !bnx2x_leader_reset(bp)) { 9875 netdev_info(bp->dev, "Recovered in open\n"); 9876 break; 9877 } 9878 9879 /* recovery has failed... */ 9880 bnx2x_set_power_state(bp, PCI_D3hot); 9881 bp->recovery_state = BNX2X_RECOVERY_FAILED; 9882 9883 netdev_err(bp->dev, "Recovery flow hasn't been properly" 9884 " completed yet. Try again later. If u still see this" 9885 " message after a few retries then power cycle is" 9886 " required.\n"); 9887 9888 return -EAGAIN; 9889 } while (0); 9890 9891 bp->recovery_state = BNX2X_RECOVERY_DONE; 9892 return bnx2x_nic_load(bp, LOAD_OPEN); 9893} 9894 9895/* called with rtnl_lock */ 9896static int bnx2x_close(struct net_device *dev) 9897{ 9898 struct bnx2x *bp = netdev_priv(dev); 9899 9900 /* Unload the driver, release IRQs */ 9901 bnx2x_nic_unload(bp, UNLOAD_CLOSE); 9902 9903 /* Power off */ 9904 bnx2x_set_power_state(bp, PCI_D3hot); 9905 9906 return 0; 9907} 9908 9909static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp, 9910 struct bnx2x_mcast_ramrod_params *p) 9911{ 9912 int mc_count = netdev_mc_count(bp->dev); 9913 struct bnx2x_mcast_list_elem *mc_mac = 9914 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); 9915 struct netdev_hw_addr *ha; 9916 9917 if (!mc_mac) 9918 return -ENOMEM; 9919 9920 INIT_LIST_HEAD(&p->mcast_list); 9921 9922 netdev_for_each_mc_addr(ha, bp->dev) { 9923 mc_mac->mac = bnx2x_mc_addr(ha); 9924 list_add_tail(&mc_mac->link, &p->mcast_list); 9925 mc_mac++; 9926 } 9927 9928 p->mcast_list_len = mc_count; 9929 9930 return 0; 9931} 9932 9933static inline void bnx2x_free_mcast_macs_list( 9934 struct bnx2x_mcast_ramrod_params *p) 9935{ 9936 struct bnx2x_mcast_list_elem *mc_mac = 9937 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, 9938 link); 9939 9940 WARN_ON(!mc_mac); 9941 kfree(mc_mac); 9942} 9943 9944/** 9945 * bnx2x_set_uc_list - configure a new unicast MACs list. 9946 * 9947 * @bp: driver handle 9948 * 9949 * We will use zero (0) as a MAC type for these MACs. 9950 */ 9951static inline int bnx2x_set_uc_list(struct bnx2x *bp) 9952{ 9953 int rc; 9954 struct net_device *dev = bp->dev; 9955 struct netdev_hw_addr *ha; 9956 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj; 9957 unsigned long ramrod_flags = 0; 9958 9959 /* First schedule a cleanup up of old configuration */ 9960 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); 9961 if (rc < 0) { 9962 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); 9963 return rc; 9964 } 9965 9966 netdev_for_each_uc_addr(ha, dev) { 9967 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, 9968 BNX2X_UC_LIST_MAC, &ramrod_flags); 9969 if (rc < 0) { 9970 BNX2X_ERR("Failed to schedule ADD operations: %d\n", 9971 rc); 9972 return rc; 9973 } 9974 } 9975 9976 /* Execute the pending commands */ 9977 __set_bit(RAMROD_CONT, &ramrod_flags); 9978 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, 9979 BNX2X_UC_LIST_MAC, &ramrod_flags); 9980} 9981 9982static inline int bnx2x_set_mc_list(struct bnx2x *bp) 9983{ 9984 struct net_device *dev = bp->dev; 9985 struct bnx2x_mcast_ramrod_params rparam = {0}; 9986 int rc = 0; 9987 9988 rparam.mcast_obj = &bp->mcast_obj; 9989 9990 /* first, clear all configured multicast MACs */ 9991 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 9992 if (rc < 0) { 9993 BNX2X_ERR("Failed to clear multicast " 9994 "configuration: %d\n", rc); 9995 return rc; 9996 } 9997 9998 /* then, configure a new MACs list */ 9999 if (netdev_mc_count(dev)) { 10000 rc = bnx2x_init_mcast_macs_list(bp, &rparam); 10001 if (rc) { 10002 BNX2X_ERR("Failed to create multicast MACs " 10003 "list: %d\n", rc); 10004 return rc; 10005 } 10006 10007 /* Now add the new MACs */ 10008 rc = bnx2x_config_mcast(bp, &rparam, 10009 BNX2X_MCAST_CMD_ADD); 10010 if (rc < 0) 10011 BNX2X_ERR("Failed to set a new multicast " 10012 "configuration: %d\n", rc); 10013 10014 bnx2x_free_mcast_macs_list(&rparam); 10015 } 10016 10017 return rc; 10018} 10019 10020 10021/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ 10022void bnx2x_set_rx_mode(struct net_device *dev) 10023{ 10024 struct bnx2x *bp = netdev_priv(dev); 10025 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 10026 10027 if (bp->state != BNX2X_STATE_OPEN) { 10028 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 10029 return; 10030 } 10031 10032 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); 10033 10034 if (dev->flags & IFF_PROMISC) 10035 rx_mode = BNX2X_RX_MODE_PROMISC; 10036 else if ((dev->flags & IFF_ALLMULTI) || 10037 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && 10038 CHIP_IS_E1(bp))) 10039 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10040 else { 10041 /* some multicasts */ 10042 if (bnx2x_set_mc_list(bp) < 0) 10043 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10044 10045 if (bnx2x_set_uc_list(bp) < 0) 10046 rx_mode = BNX2X_RX_MODE_PROMISC; 10047 } 10048 10049 bp->rx_mode = rx_mode; 10050 10051 /* Schedule the rx_mode command */ 10052 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { 10053 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 10054 return; 10055 } 10056 10057 bnx2x_set_storm_rx_mode(bp); 10058} 10059 10060/* called with rtnl_lock */ 10061static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 10062 int devad, u16 addr) 10063{ 10064 struct bnx2x *bp = netdev_priv(netdev); 10065 u16 value; 10066 int rc; 10067 10068 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 10069 prtad, devad, addr); 10070 10071 /* The HW expects different devad if CL22 is used */ 10072 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10073 10074 bnx2x_acquire_phy_lock(bp); 10075 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); 10076 bnx2x_release_phy_lock(bp); 10077 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 10078 10079 if (!rc) 10080 rc = value; 10081 return rc; 10082} 10083 10084/* called with rtnl_lock */ 10085static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, 10086 u16 addr, u16 value) 10087{ 10088 struct bnx2x *bp = netdev_priv(netdev); 10089 int rc; 10090 10091 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x," 10092 " value 0x%x\n", prtad, devad, addr, value); 10093 10094 /* The HW expects different devad if CL22 is used */ 10095 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10096 10097 bnx2x_acquire_phy_lock(bp); 10098 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); 10099 bnx2x_release_phy_lock(bp); 10100 return rc; 10101} 10102 10103/* called with rtnl_lock */ 10104static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 10105{ 10106 struct bnx2x *bp = netdev_priv(dev); 10107 struct mii_ioctl_data *mdio = if_mii(ifr); 10108 10109 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", 10110 mdio->phy_id, mdio->reg_num, mdio->val_in); 10111 10112 if (!netif_running(dev)) 10113 return -EAGAIN; 10114 10115 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); 10116} 10117 10118#ifdef CONFIG_NET_POLL_CONTROLLER 10119static void poll_bnx2x(struct net_device *dev) 10120{ 10121 struct bnx2x *bp = netdev_priv(dev); 10122 10123 disable_irq(bp->pdev->irq); 10124 bnx2x_interrupt(bp->pdev->irq, dev); 10125 enable_irq(bp->pdev->irq); 10126} 10127#endif 10128 10129static const struct net_device_ops bnx2x_netdev_ops = { 10130 .ndo_open = bnx2x_open, 10131 .ndo_stop = bnx2x_close, 10132 .ndo_start_xmit = bnx2x_start_xmit, 10133 .ndo_select_queue = bnx2x_select_queue, 10134 .ndo_set_rx_mode = bnx2x_set_rx_mode, 10135 .ndo_set_mac_address = bnx2x_change_mac_addr, 10136 .ndo_validate_addr = eth_validate_addr, 10137 .ndo_do_ioctl = bnx2x_ioctl, 10138 .ndo_change_mtu = bnx2x_change_mtu, 10139 .ndo_fix_features = bnx2x_fix_features, 10140 .ndo_set_features = bnx2x_set_features, 10141 .ndo_tx_timeout = bnx2x_tx_timeout, 10142#ifdef CONFIG_NET_POLL_CONTROLLER 10143 .ndo_poll_controller = poll_bnx2x, 10144#endif 10145 .ndo_setup_tc = bnx2x_setup_tc, 10146 10147#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) 10148 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, 10149#endif 10150}; 10151 10152static inline int bnx2x_set_coherency_mask(struct bnx2x *bp) 10153{ 10154 struct device *dev = &bp->pdev->dev; 10155 10156 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 10157 bp->flags |= USING_DAC_FLAG; 10158 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 10159 dev_err(dev, "dma_set_coherent_mask failed, " 10160 "aborting\n"); 10161 return -EIO; 10162 } 10163 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 10164 dev_err(dev, "System does not support DMA, aborting\n"); 10165 return -EIO; 10166 } 10167 10168 return 0; 10169} 10170 10171static int __devinit bnx2x_init_dev(struct pci_dev *pdev, 10172 struct net_device *dev, 10173 unsigned long board_type) 10174{ 10175 struct bnx2x *bp; 10176 int rc; 10177 10178 SET_NETDEV_DEV(dev, &pdev->dev); 10179 bp = netdev_priv(dev); 10180 10181 bp->dev = dev; 10182 bp->pdev = pdev; 10183 bp->flags = 0; 10184 bp->pf_num = PCI_FUNC(pdev->devfn); 10185 10186 rc = pci_enable_device(pdev); 10187 if (rc) { 10188 dev_err(&bp->pdev->dev, 10189 "Cannot enable PCI device, aborting\n"); 10190 goto err_out; 10191 } 10192 10193 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 10194 dev_err(&bp->pdev->dev, 10195 "Cannot find PCI device base address, aborting\n"); 10196 rc = -ENODEV; 10197 goto err_out_disable; 10198 } 10199 10200 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 10201 dev_err(&bp->pdev->dev, "Cannot find second PCI device" 10202 " base address, aborting\n"); 10203 rc = -ENODEV; 10204 goto err_out_disable; 10205 } 10206 10207 if (atomic_read(&pdev->enable_cnt) == 1) { 10208 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 10209 if (rc) { 10210 dev_err(&bp->pdev->dev, 10211 "Cannot obtain PCI resources, aborting\n"); 10212 goto err_out_disable; 10213 } 10214 10215 pci_set_master(pdev); 10216 pci_save_state(pdev); 10217 } 10218 10219 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 10220 if (bp->pm_cap == 0) { 10221 dev_err(&bp->pdev->dev, 10222 "Cannot find power management capability, aborting\n"); 10223 rc = -EIO; 10224 goto err_out_release; 10225 } 10226 10227 if (!pci_is_pcie(pdev)) { 10228 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 10229 rc = -EIO; 10230 goto err_out_release; 10231 } 10232 10233 rc = bnx2x_set_coherency_mask(bp); 10234 if (rc) 10235 goto err_out_release; 10236 10237 dev->mem_start = pci_resource_start(pdev, 0); 10238 dev->base_addr = dev->mem_start; 10239 dev->mem_end = pci_resource_end(pdev, 0); 10240 10241 dev->irq = pdev->irq; 10242 10243 bp->regview = pci_ioremap_bar(pdev, 0); 10244 if (!bp->regview) { 10245 dev_err(&bp->pdev->dev, 10246 "Cannot map register space, aborting\n"); 10247 rc = -ENOMEM; 10248 goto err_out_release; 10249 } 10250 10251 bnx2x_set_power_state(bp, PCI_D0); 10252 10253 /* clean indirect addresses */ 10254 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 10255 PCICFG_VENDOR_ID_OFFSET); 10256 /* Clean the following indirect addresses for all functions since it 10257 * is not used by the driver. 10258 */ 10259 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); 10260 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); 10261 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 10262 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 10263 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 10264 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 10265 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 10266 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); 10267 10268 /* 10269 * Enable internal target-read (in case we are probed after PF FLR). 10270 * Must be done prior to any BAR read access. Only for 57712 and up 10271 */ 10272 if (board_type != BCM57710 && 10273 board_type != BCM57711 && 10274 board_type != BCM57711E) 10275 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 10276 10277 /* Reset the load counter */ 10278 bnx2x_clear_load_cnt(bp); 10279 10280 dev->watchdog_timeo = TX_TIMEOUT; 10281 10282 dev->netdev_ops = &bnx2x_netdev_ops; 10283 bnx2x_set_ethtool_ops(dev); 10284 10285 dev->priv_flags |= IFF_UNICAST_FLT; 10286 10287 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10288 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_LRO | 10289 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; 10290 10291 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10292 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 10293 10294 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; 10295 if (bp->flags & USING_DAC_FLAG) 10296 dev->features |= NETIF_F_HIGHDMA; 10297 10298 /* Add Loopback capability to the device */ 10299 dev->hw_features |= NETIF_F_LOOPBACK; 10300 10301#ifdef BCM_DCBNL 10302 dev->dcbnl_ops = &bnx2x_dcbnl_ops; 10303#endif 10304 10305 /* get_port_hwinfo() will set prtad and mmds properly */ 10306 bp->mdio.prtad = MDIO_PRTAD_NONE; 10307 bp->mdio.mmds = 0; 10308 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10309 bp->mdio.dev = dev; 10310 bp->mdio.mdio_read = bnx2x_mdio_read; 10311 bp->mdio.mdio_write = bnx2x_mdio_write; 10312 10313 return 0; 10314 10315err_out_release: 10316 if (atomic_read(&pdev->enable_cnt) == 1) 10317 pci_release_regions(pdev); 10318 10319err_out_disable: 10320 pci_disable_device(pdev); 10321 pci_set_drvdata(pdev, NULL); 10322 10323err_out: 10324 return rc; 10325} 10326 10327static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, 10328 int *width, int *speed) 10329{ 10330 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); 10331 10332 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; 10333 10334 /* return value of 1=2.5GHz 2=5GHz */ 10335 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; 10336} 10337 10338static int bnx2x_check_firmware(struct bnx2x *bp) 10339{ 10340 const struct firmware *firmware = bp->firmware; 10341 struct bnx2x_fw_file_hdr *fw_hdr; 10342 struct bnx2x_fw_file_section *sections; 10343 u32 offset, len, num_ops; 10344 u16 *ops_offsets; 10345 int i; 10346 const u8 *fw_ver; 10347 10348 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) 10349 return -EINVAL; 10350 10351 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 10352 sections = (struct bnx2x_fw_file_section *)fw_hdr; 10353 10354 /* Make sure none of the offsets and sizes make us read beyond 10355 * the end of the firmware data */ 10356 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { 10357 offset = be32_to_cpu(sections[i].offset); 10358 len = be32_to_cpu(sections[i].len); 10359 if (offset + len > firmware->size) { 10360 dev_err(&bp->pdev->dev, 10361 "Section %d length is out of bounds\n", i); 10362 return -EINVAL; 10363 } 10364 } 10365 10366 /* Likewise for the init_ops offsets */ 10367 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); 10368 ops_offsets = (u16 *)(firmware->data + offset); 10369 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); 10370 10371 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 10372 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 10373 dev_err(&bp->pdev->dev, 10374 "Section offset %d is out of bounds\n", i); 10375 return -EINVAL; 10376 } 10377 } 10378 10379 /* Check FW version */ 10380 offset = be32_to_cpu(fw_hdr->fw_version.offset); 10381 fw_ver = firmware->data + offset; 10382 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || 10383 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || 10384 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || 10385 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { 10386 dev_err(&bp->pdev->dev, 10387 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 10388 fw_ver[0], fw_ver[1], fw_ver[2], 10389 fw_ver[3], BCM_5710_FW_MAJOR_VERSION, 10390 BCM_5710_FW_MINOR_VERSION, 10391 BCM_5710_FW_REVISION_VERSION, 10392 BCM_5710_FW_ENGINEERING_VERSION); 10393 return -EINVAL; 10394 } 10395 10396 return 0; 10397} 10398 10399static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10400{ 10401 const __be32 *source = (const __be32 *)_source; 10402 u32 *target = (u32 *)_target; 10403 u32 i; 10404 10405 for (i = 0; i < n/4; i++) 10406 target[i] = be32_to_cpu(source[i]); 10407} 10408 10409/* 10410 Ops array is stored in the following format: 10411 {op(8bit), offset(24bit, big endian), data(32bit, big endian)} 10412 */ 10413static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) 10414{ 10415 const __be32 *source = (const __be32 *)_source; 10416 struct raw_op *target = (struct raw_op *)_target; 10417 u32 i, j, tmp; 10418 10419 for (i = 0, j = 0; i < n/8; i++, j += 2) { 10420 tmp = be32_to_cpu(source[j]); 10421 target[i].op = (tmp >> 24) & 0xff; 10422 target[i].offset = tmp & 0xffffff; 10423 target[i].raw_data = be32_to_cpu(source[j + 1]); 10424 } 10425} 10426 10427/** 10428 * IRO array is stored in the following format: 10429 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } 10430 */ 10431static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) 10432{ 10433 const __be32 *source = (const __be32 *)_source; 10434 struct iro *target = (struct iro *)_target; 10435 u32 i, j, tmp; 10436 10437 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { 10438 target[i].base = be32_to_cpu(source[j]); 10439 j++; 10440 tmp = be32_to_cpu(source[j]); 10441 target[i].m1 = (tmp >> 16) & 0xffff; 10442 target[i].m2 = tmp & 0xffff; 10443 j++; 10444 tmp = be32_to_cpu(source[j]); 10445 target[i].m3 = (tmp >> 16) & 0xffff; 10446 target[i].size = tmp & 0xffff; 10447 j++; 10448 } 10449} 10450 10451static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10452{ 10453 const __be16 *source = (const __be16 *)_source; 10454 u16 *target = (u16 *)_target; 10455 u32 i; 10456 10457 for (i = 0; i < n/2; i++) 10458 target[i] = be16_to_cpu(source[i]); 10459} 10460 10461#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ 10462do { \ 10463 u32 len = be32_to_cpu(fw_hdr->arr.len); \ 10464 bp->arr = kmalloc(len, GFP_KERNEL); \ 10465 if (!bp->arr) { \ 10466 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \ 10467 goto lbl; \ 10468 } \ 10469 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ 10470 (u8 *)bp->arr, len); \ 10471} while (0) 10472 10473int bnx2x_init_firmware(struct bnx2x *bp) 10474{ 10475 const char *fw_file_name; 10476 struct bnx2x_fw_file_hdr *fw_hdr; 10477 int rc; 10478 10479 if (CHIP_IS_E1(bp)) 10480 fw_file_name = FW_FILE_NAME_E1; 10481 else if (CHIP_IS_E1H(bp)) 10482 fw_file_name = FW_FILE_NAME_E1H; 10483 else if (!CHIP_IS_E1x(bp)) 10484 fw_file_name = FW_FILE_NAME_E2; 10485 else { 10486 BNX2X_ERR("Unsupported chip revision\n"); 10487 return -EINVAL; 10488 } 10489 10490 BNX2X_DEV_INFO("Loading %s\n", fw_file_name); 10491 10492 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); 10493 if (rc) { 10494 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name); 10495 goto request_firmware_exit; 10496 } 10497 10498 rc = bnx2x_check_firmware(bp); 10499 if (rc) { 10500 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); 10501 goto request_firmware_exit; 10502 } 10503 10504 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; 10505 10506 /* Initialize the pointers to the init arrays */ 10507 /* Blob */ 10508 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); 10509 10510 /* Opcodes */ 10511 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); 10512 10513 /* Offsets */ 10514 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, 10515 be16_to_cpu_n); 10516 10517 /* STORMs firmware */ 10518 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10519 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); 10520 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + 10521 be32_to_cpu(fw_hdr->tsem_pram_data.offset); 10522 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10523 be32_to_cpu(fw_hdr->usem_int_table_data.offset); 10524 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + 10525 be32_to_cpu(fw_hdr->usem_pram_data.offset); 10526 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10527 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); 10528 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + 10529 be32_to_cpu(fw_hdr->xsem_pram_data.offset); 10530 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10531 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 10532 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 10533 be32_to_cpu(fw_hdr->csem_pram_data.offset); 10534 /* IRO */ 10535 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); 10536 10537 return 0; 10538 10539iro_alloc_err: 10540 kfree(bp->init_ops_offsets); 10541init_offsets_alloc_err: 10542 kfree(bp->init_ops); 10543init_ops_alloc_err: 10544 kfree(bp->init_data); 10545request_firmware_exit: 10546 release_firmware(bp->firmware); 10547 10548 return rc; 10549} 10550 10551static void bnx2x_release_firmware(struct bnx2x *bp) 10552{ 10553 kfree(bp->init_ops_offsets); 10554 kfree(bp->init_ops); 10555 kfree(bp->init_data); 10556 release_firmware(bp->firmware); 10557} 10558 10559 10560static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { 10561 .init_hw_cmn_chip = bnx2x_init_hw_common_chip, 10562 .init_hw_cmn = bnx2x_init_hw_common, 10563 .init_hw_port = bnx2x_init_hw_port, 10564 .init_hw_func = bnx2x_init_hw_func, 10565 10566 .reset_hw_cmn = bnx2x_reset_common, 10567 .reset_hw_port = bnx2x_reset_port, 10568 .reset_hw_func = bnx2x_reset_func, 10569 10570 .gunzip_init = bnx2x_gunzip_init, 10571 .gunzip_end = bnx2x_gunzip_end, 10572 10573 .init_fw = bnx2x_init_firmware, 10574 .release_fw = bnx2x_release_firmware, 10575}; 10576 10577void bnx2x__init_func_obj(struct bnx2x *bp) 10578{ 10579 /* Prepare DMAE related driver resources */ 10580 bnx2x_setup_dmae(bp); 10581 10582 bnx2x_init_func_obj(bp, &bp->func_obj, 10583 bnx2x_sp(bp, func_rdata), 10584 bnx2x_sp_mapping(bp, func_rdata), 10585 &bnx2x_func_sp_drv); 10586} 10587 10588/* must be called after sriov-enable */ 10589static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp) 10590{ 10591 int cid_count = BNX2X_L2_CID_COUNT(bp); 10592 10593#ifdef BCM_CNIC 10594 cid_count += CNIC_CID_MAX; 10595#endif 10596 return roundup(cid_count, QM_CID_ROUND); 10597} 10598 10599/** 10600 * bnx2x_get_num_none_def_sbs - return the number of none default SBs 10601 * 10602 * @dev: pci device 10603 * 10604 */ 10605static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) 10606{ 10607 int pos; 10608 u16 control; 10609 10610 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 10611 10612 /* 10613 * If MSI-X is not supported - return number of SBs needed to support 10614 * one fast path queue: one FP queue + SB for CNIC 10615 */ 10616 if (!pos) 10617 return 1 + CNIC_PRESENT; 10618 10619 /* 10620 * The value in the PCI configuration space is the index of the last 10621 * entry, namely one less than the actual size of the table, which is 10622 * exactly what we want to return from this function: number of all SBs 10623 * without the default SB. 10624 */ 10625 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 10626 return control & PCI_MSIX_FLAGS_QSIZE; 10627} 10628 10629static int __devinit bnx2x_init_one(struct pci_dev *pdev, 10630 const struct pci_device_id *ent) 10631{ 10632 struct net_device *dev = NULL; 10633 struct bnx2x *bp; 10634 int pcie_width, pcie_speed; 10635 int rc, max_non_def_sbs; 10636 int rx_count, tx_count, rss_count; 10637 /* 10638 * An estimated maximum supported CoS number according to the chip 10639 * version. 10640 * We will try to roughly estimate the maximum number of CoSes this chip 10641 * may support in order to minimize the memory allocated for Tx 10642 * netdev_queue's. This number will be accurately calculated during the 10643 * initialization of bp->max_cos based on the chip versions AND chip 10644 * revision in the bnx2x_init_bp(). 10645 */ 10646 u8 max_cos_est = 0; 10647 10648 switch (ent->driver_data) { 10649 case BCM57710: 10650 case BCM57711: 10651 case BCM57711E: 10652 max_cos_est = BNX2X_MULTI_TX_COS_E1X; 10653 break; 10654 10655 case BCM57712: 10656 case BCM57712_MF: 10657 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; 10658 break; 10659 10660 case BCM57800: 10661 case BCM57800_MF: 10662 case BCM57810: 10663 case BCM57810_MF: 10664 case BCM57840: 10665 case BCM57840_MF: 10666 max_cos_est = BNX2X_MULTI_TX_COS_E3B0; 10667 break; 10668 10669 default: 10670 pr_err("Unknown board_type (%ld), aborting\n", 10671 ent->driver_data); 10672 return -ENODEV; 10673 } 10674 10675 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); 10676 10677 /* !!! FIXME !!! 10678 * Do not allow the maximum SB count to grow above 16 10679 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48. 10680 * We will use the FP_SB_MAX_E1x macro for this matter. 10681 */ 10682 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs); 10683 10684 WARN_ON(!max_non_def_sbs); 10685 10686 /* Maximum number of RSS queues: one IGU SB goes to CNIC */ 10687 rss_count = max_non_def_sbs - CNIC_PRESENT; 10688 10689 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ 10690 rx_count = rss_count + FCOE_PRESENT; 10691 10692 /* 10693 * Maximum number of netdev Tx queues: 10694 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 10695 */ 10696 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT; 10697 10698 /* dev zeroed in init_etherdev */ 10699 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); 10700 if (!dev) { 10701 dev_err(&pdev->dev, "Cannot allocate net device\n"); 10702 return -ENOMEM; 10703 } 10704 10705 bp = netdev_priv(dev); 10706 10707 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n", 10708 tx_count, rx_count); 10709 10710 bp->igu_sb_cnt = max_non_def_sbs; 10711 bp->msg_enable = debug; 10712 pci_set_drvdata(pdev, dev); 10713 10714 rc = bnx2x_init_dev(pdev, dev, ent->driver_data); 10715 if (rc < 0) { 10716 free_netdev(dev); 10717 return rc; 10718 } 10719 10720 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs); 10721 10722 rc = bnx2x_init_bp(bp); 10723 if (rc) 10724 goto init_one_exit; 10725 10726 /* 10727 * Map doorbels here as we need the real value of bp->max_cos which 10728 * is initialized in bnx2x_init_bp(). 10729 */ 10730 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), 10731 min_t(u64, BNX2X_DB_SIZE(bp), 10732 pci_resource_len(pdev, 2))); 10733 if (!bp->doorbells) { 10734 dev_err(&bp->pdev->dev, 10735 "Cannot map doorbell space, aborting\n"); 10736 rc = -ENOMEM; 10737 goto init_one_exit; 10738 } 10739 10740 /* calc qm_cid_count */ 10741 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); 10742 10743#ifdef BCM_CNIC 10744 /* disable FCOE L2 queue for E1x and E3*/ 10745 if (CHIP_IS_E1x(bp) || CHIP_IS_E3(bp)) 10746 bp->flags |= NO_FCOE_FLAG; 10747 10748#endif 10749 10750 /* Configure interrupt mode: try to enable MSI-X/MSI if 10751 * needed, set bp->num_queues appropriately. 10752 */ 10753 bnx2x_set_int_mode(bp); 10754 10755 /* Add all NAPI objects */ 10756 bnx2x_add_all_napi(bp); 10757 10758 rc = register_netdev(dev); 10759 if (rc) { 10760 dev_err(&pdev->dev, "Cannot register net device\n"); 10761 goto init_one_exit; 10762 } 10763 10764#ifdef BCM_CNIC 10765 if (!NO_FCOE(bp)) { 10766 /* Add storage MAC address */ 10767 rtnl_lock(); 10768 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 10769 rtnl_unlock(); 10770 } 10771#endif 10772 10773 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); 10774 10775 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", 10776 board_info[ent->driver_data].name, 10777 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 10778 pcie_width, 10779 ((!CHIP_IS_E2(bp) && pcie_speed == 2) || 10780 (CHIP_IS_E2(bp) && pcie_speed == 1)) ? 10781 "5GHz (Gen2)" : "2.5GHz", 10782 dev->base_addr, bp->pdev->irq, dev->dev_addr); 10783 10784 return 0; 10785 10786init_one_exit: 10787 if (bp->regview) 10788 iounmap(bp->regview); 10789 10790 if (bp->doorbells) 10791 iounmap(bp->doorbells); 10792 10793 free_netdev(dev); 10794 10795 if (atomic_read(&pdev->enable_cnt) == 1) 10796 pci_release_regions(pdev); 10797 10798 pci_disable_device(pdev); 10799 pci_set_drvdata(pdev, NULL); 10800 10801 return rc; 10802} 10803 10804static void __devexit bnx2x_remove_one(struct pci_dev *pdev) 10805{ 10806 struct net_device *dev = pci_get_drvdata(pdev); 10807 struct bnx2x *bp; 10808 10809 if (!dev) { 10810 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); 10811 return; 10812 } 10813 bp = netdev_priv(dev); 10814 10815#ifdef BCM_CNIC 10816 /* Delete storage MAC address */ 10817 if (!NO_FCOE(bp)) { 10818 rtnl_lock(); 10819 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 10820 rtnl_unlock(); 10821 } 10822#endif 10823 10824#ifdef BCM_DCBNL 10825 /* Delete app tlvs from dcbnl */ 10826 bnx2x_dcbnl_update_applist(bp, true); 10827#endif 10828 10829 unregister_netdev(dev); 10830 10831 /* Delete all NAPI objects */ 10832 bnx2x_del_all_napi(bp); 10833 10834 /* Power on: we can't let PCI layer write to us while we are in D3 */ 10835 bnx2x_set_power_state(bp, PCI_D0); 10836 10837 /* Disable MSI/MSI-X */ 10838 bnx2x_disable_msi(bp); 10839 10840 /* Power off */ 10841 bnx2x_set_power_state(bp, PCI_D3hot); 10842 10843 /* Make sure RESET task is not scheduled before continuing */ 10844 cancel_delayed_work_sync(&bp->sp_rtnl_task); 10845 10846 if (bp->regview) 10847 iounmap(bp->regview); 10848 10849 if (bp->doorbells) 10850 iounmap(bp->doorbells); 10851 10852 bnx2x_free_mem_bp(bp); 10853 10854 free_netdev(dev); 10855 10856 if (atomic_read(&pdev->enable_cnt) == 1) 10857 pci_release_regions(pdev); 10858 10859 pci_disable_device(pdev); 10860 pci_set_drvdata(pdev, NULL); 10861} 10862 10863static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 10864{ 10865 int i; 10866 10867 bp->state = BNX2X_STATE_ERROR; 10868 10869 bp->rx_mode = BNX2X_RX_MODE_NONE; 10870 10871#ifdef BCM_CNIC 10872 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); 10873#endif 10874 /* Stop Tx */ 10875 bnx2x_tx_disable(bp); 10876 10877 bnx2x_netif_stop(bp, 0); 10878 10879 del_timer_sync(&bp->timer); 10880 10881 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 10882 10883 /* Release IRQs */ 10884 bnx2x_free_irq(bp); 10885 10886 /* Free SKBs, SGEs, TPA pool and driver internals */ 10887 bnx2x_free_skbs(bp); 10888 10889 for_each_rx_queue(bp, i) 10890 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 10891 10892 bnx2x_free_mem(bp); 10893 10894 bp->state = BNX2X_STATE_CLOSED; 10895 10896 netif_carrier_off(bp->dev); 10897 10898 return 0; 10899} 10900 10901static void bnx2x_eeh_recover(struct bnx2x *bp) 10902{ 10903 u32 val; 10904 10905 mutex_init(&bp->port.phy_mutex); 10906 10907 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 10908 bp->link_params.shmem_base = bp->common.shmem_base; 10909 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base); 10910 10911 if (!bp->common.shmem_base || 10912 (bp->common.shmem_base < 0xA0000) || 10913 (bp->common.shmem_base >= 0xC0000)) { 10914 BNX2X_DEV_INFO("MCP not active\n"); 10915 bp->flags |= NO_MCP_FLAG; 10916 return; 10917 } 10918 10919 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 10920 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 10921 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 10922 BNX2X_ERR("BAD MCP validity signature\n"); 10923 10924 if (!BP_NOMCP(bp)) { 10925 bp->fw_seq = 10926 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 10927 DRV_MSG_SEQ_NUMBER_MASK); 10928 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 10929 } 10930} 10931 10932/** 10933 * bnx2x_io_error_detected - called when PCI error is detected 10934 * @pdev: Pointer to PCI device 10935 * @state: The current pci connection state 10936 * 10937 * This function is called after a PCI bus error affecting 10938 * this device has been detected. 10939 */ 10940static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, 10941 pci_channel_state_t state) 10942{ 10943 struct net_device *dev = pci_get_drvdata(pdev); 10944 struct bnx2x *bp = netdev_priv(dev); 10945 10946 rtnl_lock(); 10947 10948 netif_device_detach(dev); 10949 10950 if (state == pci_channel_io_perm_failure) { 10951 rtnl_unlock(); 10952 return PCI_ERS_RESULT_DISCONNECT; 10953 } 10954 10955 if (netif_running(dev)) 10956 bnx2x_eeh_nic_unload(bp); 10957 10958 pci_disable_device(pdev); 10959 10960 rtnl_unlock(); 10961 10962 /* Request a slot reset */ 10963 return PCI_ERS_RESULT_NEED_RESET; 10964} 10965 10966/** 10967 * bnx2x_io_slot_reset - called after the PCI bus has been reset 10968 * @pdev: Pointer to PCI device 10969 * 10970 * Restart the card from scratch, as if from a cold-boot. 10971 */ 10972static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) 10973{ 10974 struct net_device *dev = pci_get_drvdata(pdev); 10975 struct bnx2x *bp = netdev_priv(dev); 10976 10977 rtnl_lock(); 10978 10979 if (pci_enable_device(pdev)) { 10980 dev_err(&pdev->dev, 10981 "Cannot re-enable PCI device after reset\n"); 10982 rtnl_unlock(); 10983 return PCI_ERS_RESULT_DISCONNECT; 10984 } 10985 10986 pci_set_master(pdev); 10987 pci_restore_state(pdev); 10988 10989 if (netif_running(dev)) 10990 bnx2x_set_power_state(bp, PCI_D0); 10991 10992 rtnl_unlock(); 10993 10994 return PCI_ERS_RESULT_RECOVERED; 10995} 10996 10997/** 10998 * bnx2x_io_resume - called when traffic can start flowing again 10999 * @pdev: Pointer to PCI device 11000 * 11001 * This callback is called when the error recovery driver tells us that 11002 * its OK to resume normal operation. 11003 */ 11004static void bnx2x_io_resume(struct pci_dev *pdev) 11005{ 11006 struct net_device *dev = pci_get_drvdata(pdev); 11007 struct bnx2x *bp = netdev_priv(dev); 11008 11009 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 11010 netdev_err(bp->dev, "Handling parity error recovery. " 11011 "Try again later\n"); 11012 return; 11013 } 11014 11015 rtnl_lock(); 11016 11017 bnx2x_eeh_recover(bp); 11018 11019 if (netif_running(dev)) 11020 bnx2x_nic_load(bp, LOAD_NORMAL); 11021 11022 netif_device_attach(dev); 11023 11024 rtnl_unlock(); 11025} 11026 11027static struct pci_error_handlers bnx2x_err_handler = { 11028 .error_detected = bnx2x_io_error_detected, 11029 .slot_reset = bnx2x_io_slot_reset, 11030 .resume = bnx2x_io_resume, 11031}; 11032 11033static struct pci_driver bnx2x_pci_driver = { 11034 .name = DRV_MODULE_NAME, 11035 .id_table = bnx2x_pci_tbl, 11036 .probe = bnx2x_init_one, 11037 .remove = __devexit_p(bnx2x_remove_one), 11038 .suspend = bnx2x_suspend, 11039 .resume = bnx2x_resume, 11040 .err_handler = &bnx2x_err_handler, 11041}; 11042 11043static int __init bnx2x_init(void) 11044{ 11045 int ret; 11046 11047 pr_info("%s", version); 11048 11049 bnx2x_wq = create_singlethread_workqueue("bnx2x"); 11050 if (bnx2x_wq == NULL) { 11051 pr_err("Cannot create workqueue\n"); 11052 return -ENOMEM; 11053 } 11054 11055 ret = pci_register_driver(&bnx2x_pci_driver); 11056 if (ret) { 11057 pr_err("Cannot register driver\n"); 11058 destroy_workqueue(bnx2x_wq); 11059 } 11060 return ret; 11061} 11062 11063static void __exit bnx2x_cleanup(void) 11064{ 11065 pci_unregister_driver(&bnx2x_pci_driver); 11066 11067 destroy_workqueue(bnx2x_wq); 11068} 11069 11070void bnx2x_notify_link_changed(struct bnx2x *bp) 11071{ 11072 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); 11073} 11074 11075module_init(bnx2x_init); 11076module_exit(bnx2x_cleanup); 11077 11078#ifdef BCM_CNIC 11079/** 11080 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). 11081 * 11082 * @bp: driver handle 11083 * @set: set or clear the CAM entry 11084 * 11085 * This function will wait until the ramdord completion returns. 11086 * Return 0 if success, -ENODEV if ramrod doesn't return. 11087 */ 11088static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) 11089{ 11090 unsigned long ramrod_flags = 0; 11091 11092 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 11093 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, 11094 &bp->iscsi_l2_mac_obj, true, 11095 BNX2X_ISCSI_ETH_MAC, &ramrod_flags); 11096} 11097 11098/* count denotes the number of new completions we have seen */ 11099static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) 11100{ 11101 struct eth_spe *spe; 11102 11103#ifdef BNX2X_STOP_ON_ERROR 11104 if (unlikely(bp->panic)) 11105 return; 11106#endif 11107 11108 spin_lock_bh(&bp->spq_lock); 11109 BUG_ON(bp->cnic_spq_pending < count); 11110 bp->cnic_spq_pending -= count; 11111 11112 11113 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { 11114 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) 11115 & SPE_HDR_CONN_TYPE) >> 11116 SPE_HDR_CONN_TYPE_SHIFT; 11117 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) 11118 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; 11119 11120 /* Set validation for iSCSI L2 client before sending SETUP 11121 * ramrod 11122 */ 11123 if (type == ETH_CONNECTION_TYPE) { 11124 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) 11125 bnx2x_set_ctx_validation(bp, &bp->context. 11126 vcxt[BNX2X_ISCSI_ETH_CID].eth, 11127 BNX2X_ISCSI_ETH_CID); 11128 } 11129 11130 /* 11131 * There may be not more than 8 L2, not more than 8 L5 SPEs 11132 * and in the air. We also check that number of outstanding 11133 * COMMON ramrods is not more than the EQ and SPQ can 11134 * accommodate. 11135 */ 11136 if (type == ETH_CONNECTION_TYPE) { 11137 if (!atomic_read(&bp->cq_spq_left)) 11138 break; 11139 else 11140 atomic_dec(&bp->cq_spq_left); 11141 } else if (type == NONE_CONNECTION_TYPE) { 11142 if (!atomic_read(&bp->eq_spq_left)) 11143 break; 11144 else 11145 atomic_dec(&bp->eq_spq_left); 11146 } else if ((type == ISCSI_CONNECTION_TYPE) || 11147 (type == FCOE_CONNECTION_TYPE)) { 11148 if (bp->cnic_spq_pending >= 11149 bp->cnic_eth_dev.max_kwqe_pending) 11150 break; 11151 else 11152 bp->cnic_spq_pending++; 11153 } else { 11154 BNX2X_ERR("Unknown SPE type: %d\n", type); 11155 bnx2x_panic(); 11156 break; 11157 } 11158 11159 spe = bnx2x_sp_get_next(bp); 11160 *spe = *bp->cnic_kwq_cons; 11161 11162 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n", 11163 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 11164 11165 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 11166 bp->cnic_kwq_cons = bp->cnic_kwq; 11167 else 11168 bp->cnic_kwq_cons++; 11169 } 11170 bnx2x_sp_prod_update(bp); 11171 spin_unlock_bh(&bp->spq_lock); 11172} 11173 11174static int bnx2x_cnic_sp_queue(struct net_device *dev, 11175 struct kwqe_16 *kwqes[], u32 count) 11176{ 11177 struct bnx2x *bp = netdev_priv(dev); 11178 int i; 11179 11180#ifdef BNX2X_STOP_ON_ERROR 11181 if (unlikely(bp->panic)) 11182 return -EIO; 11183#endif 11184 11185 spin_lock_bh(&bp->spq_lock); 11186 11187 for (i = 0; i < count; i++) { 11188 struct eth_spe *spe = (struct eth_spe *)kwqes[i]; 11189 11190 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) 11191 break; 11192 11193 *bp->cnic_kwq_prod = *spe; 11194 11195 bp->cnic_kwq_pending++; 11196 11197 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n", 11198 spe->hdr.conn_and_cmd_data, spe->hdr.type, 11199 spe->data.update_data_addr.hi, 11200 spe->data.update_data_addr.lo, 11201 bp->cnic_kwq_pending); 11202 11203 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 11204 bp->cnic_kwq_prod = bp->cnic_kwq; 11205 else 11206 bp->cnic_kwq_prod++; 11207 } 11208 11209 spin_unlock_bh(&bp->spq_lock); 11210 11211 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) 11212 bnx2x_cnic_sp_post(bp, 0); 11213 11214 return i; 11215} 11216 11217static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11218{ 11219 struct cnic_ops *c_ops; 11220 int rc = 0; 11221 11222 mutex_lock(&bp->cnic_mutex); 11223 c_ops = rcu_dereference_protected(bp->cnic_ops, 11224 lockdep_is_held(&bp->cnic_mutex)); 11225 if (c_ops) 11226 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11227 mutex_unlock(&bp->cnic_mutex); 11228 11229 return rc; 11230} 11231 11232static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11233{ 11234 struct cnic_ops *c_ops; 11235 int rc = 0; 11236 11237 rcu_read_lock(); 11238 c_ops = rcu_dereference(bp->cnic_ops); 11239 if (c_ops) 11240 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11241 rcu_read_unlock(); 11242 11243 return rc; 11244} 11245 11246/* 11247 * for commands that have no data 11248 */ 11249int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) 11250{ 11251 struct cnic_ctl_info ctl = {0}; 11252 11253 ctl.cmd = cmd; 11254 11255 return bnx2x_cnic_ctl_send(bp, &ctl); 11256} 11257 11258static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) 11259{ 11260 struct cnic_ctl_info ctl = {0}; 11261 11262 /* first we tell CNIC and only then we count this as a completion */ 11263 ctl.cmd = CNIC_CTL_COMPLETION_CMD; 11264 ctl.data.comp.cid = cid; 11265 ctl.data.comp.error = err; 11266 11267 bnx2x_cnic_ctl_send_bh(bp, &ctl); 11268 bnx2x_cnic_sp_post(bp, 0); 11269} 11270 11271 11272/* Called with netif_addr_lock_bh() taken. 11273 * Sets an rx_mode config for an iSCSI ETH client. 11274 * Doesn't block. 11275 * Completion should be checked outside. 11276 */ 11277static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) 11278{ 11279 unsigned long accept_flags = 0, ramrod_flags = 0; 11280 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11281 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; 11282 11283 if (start) { 11284 /* Start accepting on iSCSI L2 ring. Accept all multicasts 11285 * because it's the only way for UIO Queue to accept 11286 * multicasts (in non-promiscuous mode only one Queue per 11287 * function will receive multicast packets (leading in our 11288 * case). 11289 */ 11290 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); 11291 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); 11292 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); 11293 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 11294 11295 /* Clear STOP_PENDING bit if START is requested */ 11296 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); 11297 11298 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; 11299 } else 11300 /* Clear START_PENDING bit if STOP is requested */ 11301 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); 11302 11303 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 11304 set_bit(sched_state, &bp->sp_state); 11305 else { 11306 __set_bit(RAMROD_RX, &ramrod_flags); 11307 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, 11308 ramrod_flags); 11309 } 11310} 11311 11312 11313static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 11314{ 11315 struct bnx2x *bp = netdev_priv(dev); 11316 int rc = 0; 11317 11318 switch (ctl->cmd) { 11319 case DRV_CTL_CTXTBL_WR_CMD: { 11320 u32 index = ctl->data.io.offset; 11321 dma_addr_t addr = ctl->data.io.dma_addr; 11322 11323 bnx2x_ilt_wr(bp, index, addr); 11324 break; 11325 } 11326 11327 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { 11328 int count = ctl->data.credit.credit_count; 11329 11330 bnx2x_cnic_sp_post(bp, count); 11331 break; 11332 } 11333 11334 /* rtnl_lock is held. */ 11335 case DRV_CTL_START_L2_CMD: { 11336 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11337 unsigned long sp_bits = 0; 11338 11339 /* Configure the iSCSI classification object */ 11340 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, 11341 cp->iscsi_l2_client_id, 11342 cp->iscsi_l2_cid, BP_FUNC(bp), 11343 bnx2x_sp(bp, mac_rdata), 11344 bnx2x_sp_mapping(bp, mac_rdata), 11345 BNX2X_FILTER_MAC_PENDING, 11346 &bp->sp_state, BNX2X_OBJ_TYPE_RX, 11347 &bp->macs_pool); 11348 11349 /* Set iSCSI MAC address */ 11350 rc = bnx2x_set_iscsi_eth_mac_addr(bp); 11351 if (rc) 11352 break; 11353 11354 mmiowb(); 11355 barrier(); 11356 11357 /* Start accepting on iSCSI L2 ring */ 11358 11359 netif_addr_lock_bh(dev); 11360 bnx2x_set_iscsi_eth_rx_mode(bp, true); 11361 netif_addr_unlock_bh(dev); 11362 11363 /* bits to wait on */ 11364 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11365 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); 11366 11367 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11368 BNX2X_ERR("rx_mode completion timed out!\n"); 11369 11370 break; 11371 } 11372 11373 /* rtnl_lock is held. */ 11374 case DRV_CTL_STOP_L2_CMD: { 11375 unsigned long sp_bits = 0; 11376 11377 /* Stop accepting on iSCSI L2 ring */ 11378 netif_addr_lock_bh(dev); 11379 bnx2x_set_iscsi_eth_rx_mode(bp, false); 11380 netif_addr_unlock_bh(dev); 11381 11382 /* bits to wait on */ 11383 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11384 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); 11385 11386 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11387 BNX2X_ERR("rx_mode completion timed out!\n"); 11388 11389 mmiowb(); 11390 barrier(); 11391 11392 /* Unset iSCSI L2 MAC */ 11393 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, 11394 BNX2X_ISCSI_ETH_MAC, true); 11395 break; 11396 } 11397 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { 11398 int count = ctl->data.credit.credit_count; 11399 11400 smp_mb__before_atomic_inc(); 11401 atomic_add(count, &bp->cq_spq_left); 11402 smp_mb__after_atomic_inc(); 11403 break; 11404 } 11405 11406 default: 11407 BNX2X_ERR("unknown command %x\n", ctl->cmd); 11408 rc = -EINVAL; 11409 } 11410 11411 return rc; 11412} 11413 11414void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) 11415{ 11416 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11417 11418 if (bp->flags & USING_MSIX_FLAG) { 11419 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 11420 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 11421 cp->irq_arr[0].vector = bp->msix_table[1].vector; 11422 } else { 11423 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 11424 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 11425 } 11426 if (!CHIP_IS_E1x(bp)) 11427 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; 11428 else 11429 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; 11430 11431 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); 11432 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); 11433 cp->irq_arr[1].status_blk = bp->def_status_blk; 11434 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 11435 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; 11436 11437 cp->num_irq = 2; 11438} 11439 11440static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, 11441 void *data) 11442{ 11443 struct bnx2x *bp = netdev_priv(dev); 11444 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11445 11446 if (ops == NULL) 11447 return -EINVAL; 11448 11449 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 11450 if (!bp->cnic_kwq) 11451 return -ENOMEM; 11452 11453 bp->cnic_kwq_cons = bp->cnic_kwq; 11454 bp->cnic_kwq_prod = bp->cnic_kwq; 11455 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; 11456 11457 bp->cnic_spq_pending = 0; 11458 bp->cnic_kwq_pending = 0; 11459 11460 bp->cnic_data = data; 11461 11462 cp->num_irq = 0; 11463 cp->drv_state |= CNIC_DRV_STATE_REGD; 11464 cp->iro_arr = bp->iro_arr; 11465 11466 bnx2x_setup_cnic_irq_info(bp); 11467 11468 rcu_assign_pointer(bp->cnic_ops, ops); 11469 11470 return 0; 11471} 11472 11473static int bnx2x_unregister_cnic(struct net_device *dev) 11474{ 11475 struct bnx2x *bp = netdev_priv(dev); 11476 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11477 11478 mutex_lock(&bp->cnic_mutex); 11479 cp->drv_state = 0; 11480 rcu_assign_pointer(bp->cnic_ops, NULL); 11481 mutex_unlock(&bp->cnic_mutex); 11482 synchronize_rcu(); 11483 kfree(bp->cnic_kwq); 11484 bp->cnic_kwq = NULL; 11485 11486 return 0; 11487} 11488 11489struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) 11490{ 11491 struct bnx2x *bp = netdev_priv(dev); 11492 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11493 11494 /* If both iSCSI and FCoE are disabled - return NULL in 11495 * order to indicate CNIC that it should not try to work 11496 * with this device. 11497 */ 11498 if (NO_ISCSI(bp) && NO_FCOE(bp)) 11499 return NULL; 11500 11501 cp->drv_owner = THIS_MODULE; 11502 cp->chip_id = CHIP_ID(bp); 11503 cp->pdev = bp->pdev; 11504 cp->io_base = bp->regview; 11505 cp->io_base2 = bp->doorbells; 11506 cp->max_kwqe_pending = 8; 11507 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; 11508 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 11509 bnx2x_cid_ilt_lines(bp); 11510 cp->ctx_tbl_len = CNIC_ILT_LINES; 11511 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 11512 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 11513 cp->drv_ctl = bnx2x_drv_ctl; 11514 cp->drv_register_cnic = bnx2x_register_cnic; 11515 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 11516 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID; 11517 cp->iscsi_l2_client_id = 11518 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11519 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID; 11520 11521 if (NO_ISCSI_OOO(bp)) 11522 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 11523 11524 if (NO_ISCSI(bp)) 11525 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; 11526 11527 if (NO_FCOE(bp)) 11528 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 11529 11530 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, " 11531 "starting cid %d\n", 11532 cp->ctx_blk_size, 11533 cp->ctx_tbl_offset, 11534 cp->ctx_tbl_len, 11535 cp->starting_cid); 11536 return cp; 11537} 11538EXPORT_SYMBOL(bnx2x_cnic_probe); 11539 11540#endif /* BCM_CNIC */ 11541 11542