bnx2x_main.c revision 7a752993fe90adf8e150cc1a85beef5f782429e7
1/* bnx2x_main.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2011 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20#include <linux/module.h> 21#include <linux/moduleparam.h> 22#include <linux/kernel.h> 23#include <linux/device.h> /* for dev_info() */ 24#include <linux/timer.h> 25#include <linux/errno.h> 26#include <linux/ioport.h> 27#include <linux/slab.h> 28#include <linux/interrupt.h> 29#include <linux/pci.h> 30#include <linux/init.h> 31#include <linux/netdevice.h> 32#include <linux/etherdevice.h> 33#include <linux/skbuff.h> 34#include <linux/dma-mapping.h> 35#include <linux/bitops.h> 36#include <linux/irq.h> 37#include <linux/delay.h> 38#include <asm/byteorder.h> 39#include <linux/time.h> 40#include <linux/ethtool.h> 41#include <linux/mii.h> 42#include <linux/if.h> 43#include <linux/if_vlan.h> 44#include <net/ip.h> 45#include <net/ipv6.h> 46#include <net/tcp.h> 47#include <net/checksum.h> 48#include <net/ip6_checksum.h> 49#include <linux/workqueue.h> 50#include <linux/crc32.h> 51#include <linux/crc32c.h> 52#include <linux/prefetch.h> 53#include <linux/zlib.h> 54#include <linux/io.h> 55#include <linux/stringify.h> 56#include <linux/vmalloc.h> 57 58#include "bnx2x.h" 59#include "bnx2x_init.h" 60#include "bnx2x_init_ops.h" 61#include "bnx2x_cmn.h" 62#include "bnx2x_dcb.h" 63#include "bnx2x_sp.h" 64 65#include <linux/firmware.h> 66#include "bnx2x_fw_file_hdr.h" 67/* FW files */ 68#define FW_FILE_VERSION \ 69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 72 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 73#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 74#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 75#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 76 77/* Time in jiffies before concluding the transmitter is hung */ 78#define TX_TIMEOUT (5*HZ) 79 80static char version[] __devinitdata = 81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " 82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 83 84MODULE_AUTHOR("Eliezer Tamir"); 85MODULE_DESCRIPTION("Broadcom NetXtreme II " 86 "BCM57710/57711/57711E/" 87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 88 "57840/57840_MF Driver"); 89MODULE_LICENSE("GPL"); 90MODULE_VERSION(DRV_MODULE_VERSION); 91MODULE_FIRMWARE(FW_FILE_NAME_E1); 92MODULE_FIRMWARE(FW_FILE_NAME_E1H); 93MODULE_FIRMWARE(FW_FILE_NAME_E2); 94 95static int multi_mode = 1; 96module_param(multi_mode, int, 0); 97MODULE_PARM_DESC(multi_mode, " Multi queue mode " 98 "(0 Disable; 1 Enable (default))"); 99 100int num_queues; 101module_param(num_queues, int, 0); 102MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1" 103 " (default is as a number of CPUs)"); 104 105static int disable_tpa; 106module_param(disable_tpa, int, 0); 107MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 108 109#define INT_MODE_INTx 1 110#define INT_MODE_MSI 2 111static int int_mode; 112module_param(int_mode, int, 0); 113MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 114 "(1 INT#x; 2 MSI)"); 115 116static int dropless_fc; 117module_param(dropless_fc, int, 0); 118MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 119 120static int poll; 121module_param(poll, int, 0); 122MODULE_PARM_DESC(poll, " Use polling (for debug)"); 123 124static int mrrs = -1; 125module_param(mrrs, int, 0); 126MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 127 128static int debug; 129module_param(debug, int, 0); 130MODULE_PARM_DESC(debug, " Default debug msglevel"); 131 132 133 134struct workqueue_struct *bnx2x_wq; 135 136enum bnx2x_board_type { 137 BCM57710 = 0, 138 BCM57711, 139 BCM57711E, 140 BCM57712, 141 BCM57712_MF, 142 BCM57800, 143 BCM57800_MF, 144 BCM57810, 145 BCM57810_MF, 146 BCM57840, 147 BCM57840_MF 148}; 149 150/* indexed by board_type, above */ 151static struct { 152 char *name; 153} board_info[] __devinitdata = { 154 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, 155 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, 156 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, 157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, 158 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, 159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, 160 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, 161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, 162 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, 163 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, 164 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit " 165 "Ethernet Multi Function"} 166}; 167 168#ifndef PCI_DEVICE_ID_NX2_57710 169#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 170#endif 171#ifndef PCI_DEVICE_ID_NX2_57711 172#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 173#endif 174#ifndef PCI_DEVICE_ID_NX2_57711E 175#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 176#endif 177#ifndef PCI_DEVICE_ID_NX2_57712 178#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 179#endif 180#ifndef PCI_DEVICE_ID_NX2_57712_MF 181#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 182#endif 183#ifndef PCI_DEVICE_ID_NX2_57800 184#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 185#endif 186#ifndef PCI_DEVICE_ID_NX2_57800_MF 187#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 188#endif 189#ifndef PCI_DEVICE_ID_NX2_57810 190#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 191#endif 192#ifndef PCI_DEVICE_ID_NX2_57810_MF 193#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 194#endif 195#ifndef PCI_DEVICE_ID_NX2_57840 196#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 197#endif 198#ifndef PCI_DEVICE_ID_NX2_57840_MF 199#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 200#endif 201static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 210 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 211 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, 212 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 213 { 0 } 214}; 215 216MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 217 218/**************************************************************************** 219* General service functions 220****************************************************************************/ 221 222static inline void __storm_memset_dma_mapping(struct bnx2x *bp, 223 u32 addr, dma_addr_t mapping) 224{ 225 REG_WR(bp, addr, U64_LO(mapping)); 226 REG_WR(bp, addr + 4, U64_HI(mapping)); 227} 228 229static inline void storm_memset_spq_addr(struct bnx2x *bp, 230 dma_addr_t mapping, u16 abs_fid) 231{ 232 u32 addr = XSEM_REG_FAST_MEMORY + 233 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 234 235 __storm_memset_dma_mapping(bp, addr, mapping); 236} 237 238static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 239 u16 pf_id) 240{ 241 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 242 pf_id); 243 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 244 pf_id); 245 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 246 pf_id); 247 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 248 pf_id); 249} 250 251static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 252 u8 enable) 253{ 254 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 255 enable); 256 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 257 enable); 258 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 259 enable); 260 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 261 enable); 262} 263 264static inline void storm_memset_eq_data(struct bnx2x *bp, 265 struct event_ring_data *eq_data, 266 u16 pfid) 267{ 268 size_t size = sizeof(struct event_ring_data); 269 270 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 271 272 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 273} 274 275static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 276 u16 pfid) 277{ 278 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 279 REG_WR16(bp, addr, eq_prod); 280} 281 282/* used only at init 283 * locking is done by mcp 284 */ 285static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 286{ 287 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 288 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 289 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 290 PCICFG_VENDOR_ID_OFFSET); 291} 292 293static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 294{ 295 u32 val; 296 297 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 298 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 299 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 300 PCICFG_VENDOR_ID_OFFSET); 301 302 return val; 303} 304 305#define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 306#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 307#define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 308#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 309#define DMAE_DP_DST_NONE "dst_addr [none]" 310 311static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, 312 int msglvl) 313{ 314 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 315 316 switch (dmae->opcode & DMAE_COMMAND_DST) { 317 case DMAE_CMD_DST_PCI: 318 if (src_type == DMAE_CMD_SRC_PCI) 319 DP(msglvl, "DMAE: opcode 0x%08x\n" 320 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 321 "comp_addr [%x:%08x], comp_val 0x%08x\n", 322 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 323 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 324 dmae->comp_addr_hi, dmae->comp_addr_lo, 325 dmae->comp_val); 326 else 327 DP(msglvl, "DMAE: opcode 0x%08x\n" 328 "src [%08x], len [%d*4], dst [%x:%08x]\n" 329 "comp_addr [%x:%08x], comp_val 0x%08x\n", 330 dmae->opcode, dmae->src_addr_lo >> 2, 331 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 332 dmae->comp_addr_hi, dmae->comp_addr_lo, 333 dmae->comp_val); 334 break; 335 case DMAE_CMD_DST_GRC: 336 if (src_type == DMAE_CMD_SRC_PCI) 337 DP(msglvl, "DMAE: opcode 0x%08x\n" 338 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 339 "comp_addr [%x:%08x], comp_val 0x%08x\n", 340 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 341 dmae->len, dmae->dst_addr_lo >> 2, 342 dmae->comp_addr_hi, dmae->comp_addr_lo, 343 dmae->comp_val); 344 else 345 DP(msglvl, "DMAE: opcode 0x%08x\n" 346 "src [%08x], len [%d*4], dst [%08x]\n" 347 "comp_addr [%x:%08x], comp_val 0x%08x\n", 348 dmae->opcode, dmae->src_addr_lo >> 2, 349 dmae->len, dmae->dst_addr_lo >> 2, 350 dmae->comp_addr_hi, dmae->comp_addr_lo, 351 dmae->comp_val); 352 break; 353 default: 354 if (src_type == DMAE_CMD_SRC_PCI) 355 DP(msglvl, "DMAE: opcode 0x%08x\n" 356 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 357 "comp_addr [%x:%08x] comp_val 0x%08x\n", 358 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 359 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 360 dmae->comp_val); 361 else 362 DP(msglvl, "DMAE: opcode 0x%08x\n" 363 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 364 "comp_addr [%x:%08x] comp_val 0x%08x\n", 365 dmae->opcode, dmae->src_addr_lo >> 2, 366 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 367 dmae->comp_val); 368 break; 369 } 370 371} 372 373/* copy command into DMAE command memory and set DMAE command go */ 374void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 375{ 376 u32 cmd_offset; 377 int i; 378 379 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 380 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 381 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 382 383 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n", 384 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); 385 } 386 REG_WR(bp, dmae_reg_go_c[idx], 1); 387} 388 389u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 390{ 391 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 392 DMAE_CMD_C_ENABLE); 393} 394 395u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 396{ 397 return opcode & ~DMAE_CMD_SRC_RESET; 398} 399 400u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 401 bool with_comp, u8 comp_type) 402{ 403 u32 opcode = 0; 404 405 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 406 (dst_type << DMAE_COMMAND_DST_SHIFT)); 407 408 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 409 410 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 411 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | 412 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 413 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 414 415#ifdef __BIG_ENDIAN 416 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 417#else 418 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 419#endif 420 if (with_comp) 421 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 422 return opcode; 423} 424 425static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 426 struct dmae_command *dmae, 427 u8 src_type, u8 dst_type) 428{ 429 memset(dmae, 0, sizeof(struct dmae_command)); 430 431 /* set the opcode */ 432 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 433 true, DMAE_COMP_PCI); 434 435 /* fill in the completion parameters */ 436 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 437 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 438 dmae->comp_val = DMAE_COMP_VAL; 439} 440 441/* issue a dmae command over the init-channel and wailt for completion */ 442static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, 443 struct dmae_command *dmae) 444{ 445 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 446 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 447 int rc = 0; 448 449 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n", 450 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 451 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 452 453 /* 454 * Lock the dmae channel. Disable BHs to prevent a dead-lock 455 * as long as this code is called both from syscall context and 456 * from ndo_set_rx_mode() flow that may be called from BH. 457 */ 458 spin_lock_bh(&bp->dmae_lock); 459 460 /* reset completion */ 461 *wb_comp = 0; 462 463 /* post the command on the channel used for initializations */ 464 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 465 466 /* wait for completion */ 467 udelay(5); 468 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 469 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); 470 471 if (!cnt || 472 (bp->recovery_state != BNX2X_RECOVERY_DONE && 473 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 474 BNX2X_ERR("DMAE timeout!\n"); 475 rc = DMAE_TIMEOUT; 476 goto unlock; 477 } 478 cnt--; 479 udelay(50); 480 } 481 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 482 BNX2X_ERR("DMAE PCI error!\n"); 483 rc = DMAE_PCI_ERROR; 484 } 485 486 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n", 487 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 488 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 489 490unlock: 491 spin_unlock_bh(&bp->dmae_lock); 492 return rc; 493} 494 495void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 496 u32 len32) 497{ 498 struct dmae_command dmae; 499 500 if (!bp->dmae_ready) { 501 u32 *data = bnx2x_sp(bp, wb_data[0]); 502 503 DP(BNX2X_MSG_OFF, 504 "DMAE is not ready (dst_addr %08x len32 %d) using indirect\n", 505 dst_addr, len32); 506 if (CHIP_IS_E1(bp)) 507 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 508 else 509 bnx2x_init_str_wr(bp, dst_addr, data, len32); 510 return; 511 } 512 513 /* set opcode and fixed command fields */ 514 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 515 516 /* fill in addresses and len */ 517 dmae.src_addr_lo = U64_LO(dma_addr); 518 dmae.src_addr_hi = U64_HI(dma_addr); 519 dmae.dst_addr_lo = dst_addr >> 2; 520 dmae.dst_addr_hi = 0; 521 dmae.len = len32; 522 523 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 524 525 /* issue the command and wait for completion */ 526 bnx2x_issue_dmae_with_comp(bp, &dmae); 527} 528 529void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 530{ 531 struct dmae_command dmae; 532 533 if (!bp->dmae_ready) { 534 u32 *data = bnx2x_sp(bp, wb_data[0]); 535 int i; 536 537 if (CHIP_IS_E1(bp)) { 538 DP(BNX2X_MSG_OFF, 539 "DMAE is not ready (src_addr %08x len32 %d) using indirect\n", 540 src_addr, len32); 541 for (i = 0; i < len32; i++) 542 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 543 } else 544 for (i = 0; i < len32; i++) 545 data[i] = REG_RD(bp, src_addr + i*4); 546 547 return; 548 } 549 550 /* set opcode and fixed command fields */ 551 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 552 553 /* fill in addresses and len */ 554 dmae.src_addr_lo = src_addr >> 2; 555 dmae.src_addr_hi = 0; 556 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 557 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 558 dmae.len = len32; 559 560 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 561 562 /* issue the command and wait for completion */ 563 bnx2x_issue_dmae_with_comp(bp, &dmae); 564} 565 566static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 567 u32 addr, u32 len) 568{ 569 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 570 int offset = 0; 571 572 while (len > dmae_wr_max) { 573 bnx2x_write_dmae(bp, phys_addr + offset, 574 addr + offset, dmae_wr_max); 575 offset += dmae_wr_max * 4; 576 len -= dmae_wr_max; 577 } 578 579 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 580} 581 582/* used only for slowpath so not inlined */ 583static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo) 584{ 585 u32 wb_write[2]; 586 587 wb_write[0] = val_hi; 588 wb_write[1] = val_lo; 589 REG_WR_DMAE(bp, reg, wb_write, 2); 590} 591 592#ifdef USE_WB_RD 593static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg) 594{ 595 u32 wb_data[2]; 596 597 REG_RD_DMAE(bp, reg, wb_data, 2); 598 599 return HILO_U64(wb_data[0], wb_data[1]); 600} 601#endif 602 603static int bnx2x_mc_assert(struct bnx2x *bp) 604{ 605 char last_idx; 606 int i, rc = 0; 607 u32 row0, row1, row2, row3; 608 609 /* XSTORM */ 610 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + 611 XSTORM_ASSERT_LIST_INDEX_OFFSET); 612 if (last_idx) 613 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 614 615 /* print the asserts */ 616 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 617 618 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + 619 XSTORM_ASSERT_LIST_OFFSET(i)); 620 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + 621 XSTORM_ASSERT_LIST_OFFSET(i) + 4); 622 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + 623 XSTORM_ASSERT_LIST_OFFSET(i) + 8); 624 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + 625 XSTORM_ASSERT_LIST_OFFSET(i) + 12); 626 627 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 628 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x" 629 " 0x%08x 0x%08x 0x%08x\n", 630 i, row3, row2, row1, row0); 631 rc++; 632 } else { 633 break; 634 } 635 } 636 637 /* TSTORM */ 638 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + 639 TSTORM_ASSERT_LIST_INDEX_OFFSET); 640 if (last_idx) 641 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 642 643 /* print the asserts */ 644 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 645 646 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + 647 TSTORM_ASSERT_LIST_OFFSET(i)); 648 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + 649 TSTORM_ASSERT_LIST_OFFSET(i) + 4); 650 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + 651 TSTORM_ASSERT_LIST_OFFSET(i) + 8); 652 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + 653 TSTORM_ASSERT_LIST_OFFSET(i) + 12); 654 655 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 656 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x" 657 " 0x%08x 0x%08x 0x%08x\n", 658 i, row3, row2, row1, row0); 659 rc++; 660 } else { 661 break; 662 } 663 } 664 665 /* CSTORM */ 666 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + 667 CSTORM_ASSERT_LIST_INDEX_OFFSET); 668 if (last_idx) 669 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 670 671 /* print the asserts */ 672 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 673 674 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + 675 CSTORM_ASSERT_LIST_OFFSET(i)); 676 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + 677 CSTORM_ASSERT_LIST_OFFSET(i) + 4); 678 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + 679 CSTORM_ASSERT_LIST_OFFSET(i) + 8); 680 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + 681 CSTORM_ASSERT_LIST_OFFSET(i) + 12); 682 683 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 684 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x" 685 " 0x%08x 0x%08x 0x%08x\n", 686 i, row3, row2, row1, row0); 687 rc++; 688 } else { 689 break; 690 } 691 } 692 693 /* USTORM */ 694 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + 695 USTORM_ASSERT_LIST_INDEX_OFFSET); 696 if (last_idx) 697 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 698 699 /* print the asserts */ 700 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 701 702 row0 = REG_RD(bp, BAR_USTRORM_INTMEM + 703 USTORM_ASSERT_LIST_OFFSET(i)); 704 row1 = REG_RD(bp, BAR_USTRORM_INTMEM + 705 USTORM_ASSERT_LIST_OFFSET(i) + 4); 706 row2 = REG_RD(bp, BAR_USTRORM_INTMEM + 707 USTORM_ASSERT_LIST_OFFSET(i) + 8); 708 row3 = REG_RD(bp, BAR_USTRORM_INTMEM + 709 USTORM_ASSERT_LIST_OFFSET(i) + 12); 710 711 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 712 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x" 713 " 0x%08x 0x%08x 0x%08x\n", 714 i, row3, row2, row1, row0); 715 rc++; 716 } else { 717 break; 718 } 719 } 720 721 return rc; 722} 723 724void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 725{ 726 u32 addr, val; 727 u32 mark, offset; 728 __be32 data[9]; 729 int word; 730 u32 trace_shmem_base; 731 if (BP_NOMCP(bp)) { 732 BNX2X_ERR("NO MCP - can not dump\n"); 733 return; 734 } 735 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 736 (bp->common.bc_ver & 0xff0000) >> 16, 737 (bp->common.bc_ver & 0xff00) >> 8, 738 (bp->common.bc_ver & 0xff)); 739 740 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 741 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 742 printk("%s" "MCP PC at 0x%x\n", lvl, val); 743 744 if (BP_PATH(bp) == 0) 745 trace_shmem_base = bp->common.shmem_base; 746 else 747 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 748 addr = trace_shmem_base - 0x0800 + 4; 749 mark = REG_RD(bp, addr); 750 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 751 + ((mark + 0x3) & ~0x3) - 0x08000000; 752 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 753 754 printk("%s", lvl); 755 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { 756 for (word = 0; word < 8; word++) 757 data[word] = htonl(REG_RD(bp, offset + 4*word)); 758 data[8] = 0x0; 759 pr_cont("%s", (char *)data); 760 } 761 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 762 for (word = 0; word < 8; word++) 763 data[word] = htonl(REG_RD(bp, offset + 4*word)); 764 data[8] = 0x0; 765 pr_cont("%s", (char *)data); 766 } 767 printk("%s" "end of fw dump\n", lvl); 768} 769 770static inline void bnx2x_fw_dump(struct bnx2x *bp) 771{ 772 bnx2x_fw_dump_lvl(bp, KERN_ERR); 773} 774 775void bnx2x_panic_dump(struct bnx2x *bp) 776{ 777 int i; 778 u16 j; 779 struct hc_sp_status_block_data sp_sb_data; 780 int func = BP_FUNC(bp); 781#ifdef BNX2X_STOP_ON_ERROR 782 u16 start = 0, end = 0; 783 u8 cos; 784#endif 785 786 bp->stats_state = STATS_STATE_DISABLED; 787 bp->eth_stats.unrecoverable_error++; 788 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 789 790 BNX2X_ERR("begin crash dump -----------------\n"); 791 792 /* Indices */ 793 /* Common */ 794 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)" 795 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 796 bp->def_idx, bp->def_att_idx, bp->attn_state, 797 bp->spq_prod_idx, bp->stats_counter); 798 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 799 bp->def_status_blk->atten_status_block.attn_bits, 800 bp->def_status_blk->atten_status_block.attn_bits_ack, 801 bp->def_status_blk->atten_status_block.status_block_id, 802 bp->def_status_blk->atten_status_block.attn_bits_index); 803 BNX2X_ERR(" def ("); 804 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 805 pr_cont("0x%x%s", 806 bp->def_status_blk->sp_sb.index_values[i], 807 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 808 809 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 810 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + 811 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 812 i*sizeof(u32)); 813 814 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 815 sp_sb_data.igu_sb_id, 816 sp_sb_data.igu_seg_id, 817 sp_sb_data.p_func.pf_id, 818 sp_sb_data.p_func.vnic_id, 819 sp_sb_data.p_func.vf_id, 820 sp_sb_data.p_func.vf_valid, 821 sp_sb_data.state); 822 823 824 for_each_eth_queue(bp, i) { 825 struct bnx2x_fastpath *fp = &bp->fp[i]; 826 int loop; 827 struct hc_status_block_data_e2 sb_data_e2; 828 struct hc_status_block_data_e1x sb_data_e1x; 829 struct hc_status_block_sm *hc_sm_p = 830 CHIP_IS_E1x(bp) ? 831 sb_data_e1x.common.state_machine : 832 sb_data_e2.common.state_machine; 833 struct hc_index_data *hc_index_p = 834 CHIP_IS_E1x(bp) ? 835 sb_data_e1x.index_data : 836 sb_data_e2.index_data; 837 u8 data_size, cos; 838 u32 *sb_data_p; 839 struct bnx2x_fp_txdata txdata; 840 841 /* Rx */ 842 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)" 843 " rx_comp_prod(0x%x)" 844 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 845 i, fp->rx_bd_prod, fp->rx_bd_cons, 846 fp->rx_comp_prod, 847 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 848 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)" 849 " fp_hc_idx(0x%x)\n", 850 fp->rx_sge_prod, fp->last_max_sge, 851 le16_to_cpu(fp->fp_hc_idx)); 852 853 /* Tx */ 854 for_each_cos_in_tx_queue(fp, cos) 855 { 856 txdata = fp->txdata[cos]; 857 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)" 858 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)" 859 " *tx_cons_sb(0x%x)\n", 860 i, txdata.tx_pkt_prod, 861 txdata.tx_pkt_cons, txdata.tx_bd_prod, 862 txdata.tx_bd_cons, 863 le16_to_cpu(*txdata.tx_cons_sb)); 864 } 865 866 loop = CHIP_IS_E1x(bp) ? 867 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 868 869 /* host sb data */ 870 871#ifdef BCM_CNIC 872 if (IS_FCOE_FP(fp)) 873 continue; 874#endif 875 BNX2X_ERR(" run indexes ("); 876 for (j = 0; j < HC_SB_MAX_SM; j++) 877 pr_cont("0x%x%s", 878 fp->sb_running_index[j], 879 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 880 881 BNX2X_ERR(" indexes ("); 882 for (j = 0; j < loop; j++) 883 pr_cont("0x%x%s", 884 fp->sb_index_values[j], 885 (j == loop - 1) ? ")" : " "); 886 /* fw sb data */ 887 data_size = CHIP_IS_E1x(bp) ? 888 sizeof(struct hc_status_block_data_e1x) : 889 sizeof(struct hc_status_block_data_e2); 890 data_size /= sizeof(u32); 891 sb_data_p = CHIP_IS_E1x(bp) ? 892 (u32 *)&sb_data_e1x : 893 (u32 *)&sb_data_e2; 894 /* copy sb data in here */ 895 for (j = 0; j < data_size; j++) 896 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 897 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 898 j * sizeof(u32)); 899 900 if (!CHIP_IS_E1x(bp)) { 901 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 902 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 903 "state(0x%x)\n", 904 sb_data_e2.common.p_func.pf_id, 905 sb_data_e2.common.p_func.vf_id, 906 sb_data_e2.common.p_func.vf_valid, 907 sb_data_e2.common.p_func.vnic_id, 908 sb_data_e2.common.same_igu_sb_1b, 909 sb_data_e2.common.state); 910 } else { 911 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 912 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 913 "state(0x%x)\n", 914 sb_data_e1x.common.p_func.pf_id, 915 sb_data_e1x.common.p_func.vf_id, 916 sb_data_e1x.common.p_func.vf_valid, 917 sb_data_e1x.common.p_func.vnic_id, 918 sb_data_e1x.common.same_igu_sb_1b, 919 sb_data_e1x.common.state); 920 } 921 922 /* SB_SMs data */ 923 for (j = 0; j < HC_SB_MAX_SM; j++) { 924 pr_cont("SM[%d] __flags (0x%x) " 925 "igu_sb_id (0x%x) igu_seg_id(0x%x) " 926 "time_to_expire (0x%x) " 927 "timer_value(0x%x)\n", j, 928 hc_sm_p[j].__flags, 929 hc_sm_p[j].igu_sb_id, 930 hc_sm_p[j].igu_seg_id, 931 hc_sm_p[j].time_to_expire, 932 hc_sm_p[j].timer_value); 933 } 934 935 /* Indecies data */ 936 for (j = 0; j < loop; j++) { 937 pr_cont("INDEX[%d] flags (0x%x) " 938 "timeout (0x%x)\n", j, 939 hc_index_p[j].flags, 940 hc_index_p[j].timeout); 941 } 942 } 943 944#ifdef BNX2X_STOP_ON_ERROR 945 /* Rings */ 946 /* Rx */ 947 for_each_rx_queue(bp, i) { 948 struct bnx2x_fastpath *fp = &bp->fp[i]; 949 950 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 951 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 952 for (j = start; j != end; j = RX_BD(j + 1)) { 953 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 954 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 955 956 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 957 i, j, rx_bd[1], rx_bd[0], sw_bd->data); 958 } 959 960 start = RX_SGE(fp->rx_sge_prod); 961 end = RX_SGE(fp->last_max_sge); 962 for (j = start; j != end; j = RX_SGE(j + 1)) { 963 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 964 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 965 966 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 967 i, j, rx_sge[1], rx_sge[0], sw_page->page); 968 } 969 970 start = RCQ_BD(fp->rx_comp_cons - 10); 971 end = RCQ_BD(fp->rx_comp_cons + 503); 972 for (j = start; j != end; j = RCQ_BD(j + 1)) { 973 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 974 975 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 976 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 977 } 978 } 979 980 /* Tx */ 981 for_each_tx_queue(bp, i) { 982 struct bnx2x_fastpath *fp = &bp->fp[i]; 983 for_each_cos_in_tx_queue(fp, cos) { 984 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; 985 986 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 987 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 988 for (j = start; j != end; j = TX_BD(j + 1)) { 989 struct sw_tx_bd *sw_bd = 990 &txdata->tx_buf_ring[j]; 991 992 BNX2X_ERR("fp%d: txdata %d, " 993 "packet[%x]=[%p,%x]\n", 994 i, cos, j, sw_bd->skb, 995 sw_bd->first_bd); 996 } 997 998 start = TX_BD(txdata->tx_bd_cons - 10); 999 end = TX_BD(txdata->tx_bd_cons + 254); 1000 for (j = start; j != end; j = TX_BD(j + 1)) { 1001 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 1002 1003 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=" 1004 "[%x:%x:%x:%x]\n", 1005 i, cos, j, tx_bd[0], tx_bd[1], 1006 tx_bd[2], tx_bd[3]); 1007 } 1008 } 1009 } 1010#endif 1011 bnx2x_fw_dump(bp); 1012 bnx2x_mc_assert(bp); 1013 BNX2X_ERR("end crash dump -----------------\n"); 1014} 1015 1016/* 1017 * FLR Support for E2 1018 * 1019 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 1020 * initialization. 1021 */ 1022#define FLR_WAIT_USEC 10000 /* 10 miliseconds */ 1023#define FLR_WAIT_INTERVAL 50 /* usec */ 1024#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ 1025 1026struct pbf_pN_buf_regs { 1027 int pN; 1028 u32 init_crd; 1029 u32 crd; 1030 u32 crd_freed; 1031}; 1032 1033struct pbf_pN_cmd_regs { 1034 int pN; 1035 u32 lines_occup; 1036 u32 lines_freed; 1037}; 1038 1039static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1040 struct pbf_pN_buf_regs *regs, 1041 u32 poll_count) 1042{ 1043 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1044 u32 cur_cnt = poll_count; 1045 1046 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1047 crd = crd_start = REG_RD(bp, regs->crd); 1048 init_crd = REG_RD(bp, regs->init_crd); 1049 1050 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1051 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1052 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1053 1054 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1055 (init_crd - crd_start))) { 1056 if (cur_cnt--) { 1057 udelay(FLR_WAIT_INTERVAL); 1058 crd = REG_RD(bp, regs->crd); 1059 crd_freed = REG_RD(bp, regs->crd_freed); 1060 } else { 1061 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1062 regs->pN); 1063 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1064 regs->pN, crd); 1065 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1066 regs->pN, crd_freed); 1067 break; 1068 } 1069 } 1070 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1071 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1072} 1073 1074static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1075 struct pbf_pN_cmd_regs *regs, 1076 u32 poll_count) 1077{ 1078 u32 occup, to_free, freed, freed_start; 1079 u32 cur_cnt = poll_count; 1080 1081 occup = to_free = REG_RD(bp, regs->lines_occup); 1082 freed = freed_start = REG_RD(bp, regs->lines_freed); 1083 1084 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1085 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1086 1087 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1088 if (cur_cnt--) { 1089 udelay(FLR_WAIT_INTERVAL); 1090 occup = REG_RD(bp, regs->lines_occup); 1091 freed = REG_RD(bp, regs->lines_freed); 1092 } else { 1093 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1094 regs->pN); 1095 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1096 regs->pN, occup); 1097 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1098 regs->pN, freed); 1099 break; 1100 } 1101 } 1102 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1103 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1104} 1105 1106static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1107 u32 expected, u32 poll_count) 1108{ 1109 u32 cur_cnt = poll_count; 1110 u32 val; 1111 1112 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1113 udelay(FLR_WAIT_INTERVAL); 1114 1115 return val; 1116} 1117 1118static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1119 char *msg, u32 poll_cnt) 1120{ 1121 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1122 if (val != 0) { 1123 BNX2X_ERR("%s usage count=%d\n", msg, val); 1124 return 1; 1125 } 1126 return 0; 1127} 1128 1129static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1130{ 1131 /* adjust polling timeout */ 1132 if (CHIP_REV_IS_EMUL(bp)) 1133 return FLR_POLL_CNT * 2000; 1134 1135 if (CHIP_REV_IS_FPGA(bp)) 1136 return FLR_POLL_CNT * 120; 1137 1138 return FLR_POLL_CNT; 1139} 1140 1141static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1142{ 1143 struct pbf_pN_cmd_regs cmd_regs[] = { 1144 {0, (CHIP_IS_E3B0(bp)) ? 1145 PBF_REG_TQ_OCCUPANCY_Q0 : 1146 PBF_REG_P0_TQ_OCCUPANCY, 1147 (CHIP_IS_E3B0(bp)) ? 1148 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1149 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1150 {1, (CHIP_IS_E3B0(bp)) ? 1151 PBF_REG_TQ_OCCUPANCY_Q1 : 1152 PBF_REG_P1_TQ_OCCUPANCY, 1153 (CHIP_IS_E3B0(bp)) ? 1154 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1155 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1156 {4, (CHIP_IS_E3B0(bp)) ? 1157 PBF_REG_TQ_OCCUPANCY_LB_Q : 1158 PBF_REG_P4_TQ_OCCUPANCY, 1159 (CHIP_IS_E3B0(bp)) ? 1160 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1161 PBF_REG_P4_TQ_LINES_FREED_CNT} 1162 }; 1163 1164 struct pbf_pN_buf_regs buf_regs[] = { 1165 {0, (CHIP_IS_E3B0(bp)) ? 1166 PBF_REG_INIT_CRD_Q0 : 1167 PBF_REG_P0_INIT_CRD , 1168 (CHIP_IS_E3B0(bp)) ? 1169 PBF_REG_CREDIT_Q0 : 1170 PBF_REG_P0_CREDIT, 1171 (CHIP_IS_E3B0(bp)) ? 1172 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1173 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1174 {1, (CHIP_IS_E3B0(bp)) ? 1175 PBF_REG_INIT_CRD_Q1 : 1176 PBF_REG_P1_INIT_CRD, 1177 (CHIP_IS_E3B0(bp)) ? 1178 PBF_REG_CREDIT_Q1 : 1179 PBF_REG_P1_CREDIT, 1180 (CHIP_IS_E3B0(bp)) ? 1181 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1182 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1183 {4, (CHIP_IS_E3B0(bp)) ? 1184 PBF_REG_INIT_CRD_LB_Q : 1185 PBF_REG_P4_INIT_CRD, 1186 (CHIP_IS_E3B0(bp)) ? 1187 PBF_REG_CREDIT_LB_Q : 1188 PBF_REG_P4_CREDIT, 1189 (CHIP_IS_E3B0(bp)) ? 1190 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1191 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1192 }; 1193 1194 int i; 1195 1196 /* Verify the command queues are flushed P0, P1, P4 */ 1197 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1198 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1199 1200 1201 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1202 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1203 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1204} 1205 1206#define OP_GEN_PARAM(param) \ 1207 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1208 1209#define OP_GEN_TYPE(type) \ 1210 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1211 1212#define OP_GEN_AGG_VECT(index) \ 1213 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1214 1215 1216static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, 1217 u32 poll_cnt) 1218{ 1219 struct sdm_op_gen op_gen = {0}; 1220 1221 u32 comp_addr = BAR_CSTRORM_INTMEM + 1222 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1223 int ret = 0; 1224 1225 if (REG_RD(bp, comp_addr)) { 1226 BNX2X_ERR("Cleanup complete was not 0 before sending\n"); 1227 return 1; 1228 } 1229 1230 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1231 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1232 op_gen.command |= OP_GEN_AGG_VECT(clnup_func); 1233 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1234 1235 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); 1236 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); 1237 1238 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1239 BNX2X_ERR("FW final cleanup did not succeed\n"); 1240 ret = 1; 1241 } 1242 /* Zero completion for nxt FLR */ 1243 REG_WR(bp, comp_addr, 0); 1244 1245 return ret; 1246} 1247 1248static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1249{ 1250 int pos; 1251 u16 status; 1252 1253 pos = pci_pcie_cap(dev); 1254 if (!pos) 1255 return false; 1256 1257 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 1258 return status & PCI_EXP_DEVSTA_TRPND; 1259} 1260 1261/* PF FLR specific routines 1262*/ 1263static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1264{ 1265 1266 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1267 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1268 CFC_REG_NUM_LCIDS_INSIDE_PF, 1269 "CFC PF usage counter timed out", 1270 poll_cnt)) 1271 return 1; 1272 1273 1274 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1275 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1276 DORQ_REG_PF_USAGE_CNT, 1277 "DQ PF usage counter timed out", 1278 poll_cnt)) 1279 return 1; 1280 1281 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1282 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1283 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1284 "QM PF usage counter timed out", 1285 poll_cnt)) 1286 return 1; 1287 1288 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1289 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1290 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1291 "Timers VNIC usage counter timed out", 1292 poll_cnt)) 1293 return 1; 1294 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1295 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1296 "Timers NUM_SCANS usage counter timed out", 1297 poll_cnt)) 1298 return 1; 1299 1300 /* Wait DMAE PF usage counter to zero */ 1301 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1302 dmae_reg_go_c[INIT_DMAE_C(bp)], 1303 "DMAE dommand register timed out", 1304 poll_cnt)) 1305 return 1; 1306 1307 return 0; 1308} 1309 1310static void bnx2x_hw_enable_status(struct bnx2x *bp) 1311{ 1312 u32 val; 1313 1314 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1315 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1316 1317 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1318 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1319 1320 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1321 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1322 1323 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1324 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1325 1326 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1327 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1328 1329 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1330 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1331 1332 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1333 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1334 1335 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1336 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1337 val); 1338} 1339 1340static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1341{ 1342 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1343 1344 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1345 1346 /* Re-enable PF target read access */ 1347 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1348 1349 /* Poll HW usage counters */ 1350 DP(BNX2X_MSG_SP, "Polling usage counters\n"); 1351 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1352 return -EBUSY; 1353 1354 /* Zero the igu 'trailing edge' and 'leading edge' */ 1355 1356 /* Send the FW cleanup command */ 1357 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1358 return -EBUSY; 1359 1360 /* ATC cleanup */ 1361 1362 /* Verify TX hw is flushed */ 1363 bnx2x_tx_hw_flushed(bp, poll_cnt); 1364 1365 /* Wait 100ms (not adjusted according to platform) */ 1366 msleep(100); 1367 1368 /* Verify no pending pci transactions */ 1369 if (bnx2x_is_pcie_pending(bp->pdev)) 1370 BNX2X_ERR("PCIE Transactions still pending\n"); 1371 1372 /* Debug */ 1373 bnx2x_hw_enable_status(bp); 1374 1375 /* 1376 * Master enable - Due to WB DMAE writes performed before this 1377 * register is re-initialized as part of the regular function init 1378 */ 1379 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1380 1381 return 0; 1382} 1383 1384static void bnx2x_hc_int_enable(struct bnx2x *bp) 1385{ 1386 int port = BP_PORT(bp); 1387 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1388 u32 val = REG_RD(bp, addr); 1389 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1390 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1391 1392 if (msix) { 1393 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1394 HC_CONFIG_0_REG_INT_LINE_EN_0); 1395 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1396 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1397 } else if (msi) { 1398 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1399 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1400 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1401 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1402 } else { 1403 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1404 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1405 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1406 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1407 1408 if (!CHIP_IS_E1(bp)) { 1409 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1410 val, port, addr); 1411 1412 REG_WR(bp, addr, val); 1413 1414 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1415 } 1416 } 1417 1418 if (CHIP_IS_E1(bp)) 1419 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1420 1421 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", 1422 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1423 1424 REG_WR(bp, addr, val); 1425 /* 1426 * Ensure that HC_CONFIG is written before leading/trailing edge config 1427 */ 1428 mmiowb(); 1429 barrier(); 1430 1431 if (!CHIP_IS_E1(bp)) { 1432 /* init leading/trailing edge */ 1433 if (IS_MF(bp)) { 1434 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1435 if (bp->port.pmf) 1436 /* enable nig and gpio3 attention */ 1437 val |= 0x1100; 1438 } else 1439 val = 0xffff; 1440 1441 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1442 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1443 } 1444 1445 /* Make sure that interrupts are indeed enabled from here on */ 1446 mmiowb(); 1447} 1448 1449static void bnx2x_igu_int_enable(struct bnx2x *bp) 1450{ 1451 u32 val; 1452 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1453 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1454 1455 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1456 1457 if (msix) { 1458 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1459 IGU_PF_CONF_SINGLE_ISR_EN); 1460 val |= (IGU_PF_CONF_FUNC_EN | 1461 IGU_PF_CONF_MSI_MSIX_EN | 1462 IGU_PF_CONF_ATTN_BIT_EN); 1463 } else if (msi) { 1464 val &= ~IGU_PF_CONF_INT_LINE_EN; 1465 val |= (IGU_PF_CONF_FUNC_EN | 1466 IGU_PF_CONF_MSI_MSIX_EN | 1467 IGU_PF_CONF_ATTN_BIT_EN | 1468 IGU_PF_CONF_SINGLE_ISR_EN); 1469 } else { 1470 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1471 val |= (IGU_PF_CONF_FUNC_EN | 1472 IGU_PF_CONF_INT_LINE_EN | 1473 IGU_PF_CONF_ATTN_BIT_EN | 1474 IGU_PF_CONF_SINGLE_ISR_EN); 1475 } 1476 1477 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n", 1478 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1479 1480 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1481 1482 barrier(); 1483 1484 /* init leading/trailing edge */ 1485 if (IS_MF(bp)) { 1486 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1487 if (bp->port.pmf) 1488 /* enable nig and gpio3 attention */ 1489 val |= 0x1100; 1490 } else 1491 val = 0xffff; 1492 1493 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1494 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1495 1496 /* Make sure that interrupts are indeed enabled from here on */ 1497 mmiowb(); 1498} 1499 1500void bnx2x_int_enable(struct bnx2x *bp) 1501{ 1502 if (bp->common.int_block == INT_BLOCK_HC) 1503 bnx2x_hc_int_enable(bp); 1504 else 1505 bnx2x_igu_int_enable(bp); 1506} 1507 1508static void bnx2x_hc_int_disable(struct bnx2x *bp) 1509{ 1510 int port = BP_PORT(bp); 1511 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1512 u32 val = REG_RD(bp, addr); 1513 1514 /* 1515 * in E1 we must use only PCI configuration space to disable 1516 * MSI/MSIX capablility 1517 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 1518 */ 1519 if (CHIP_IS_E1(bp)) { 1520 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 1521 * Use mask register to prevent from HC sending interrupts 1522 * after we exit the function 1523 */ 1524 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 1525 1526 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1527 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1528 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1529 } else 1530 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1531 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1532 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1533 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1534 1535 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1536 val, port, addr); 1537 1538 /* flush all outstanding writes */ 1539 mmiowb(); 1540 1541 REG_WR(bp, addr, val); 1542 if (REG_RD(bp, addr) != val) 1543 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1544} 1545 1546static void bnx2x_igu_int_disable(struct bnx2x *bp) 1547{ 1548 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1549 1550 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 1551 IGU_PF_CONF_INT_LINE_EN | 1552 IGU_PF_CONF_ATTN_BIT_EN); 1553 1554 DP(NETIF_MSG_INTR, "write %x to IGU\n", val); 1555 1556 /* flush all outstanding writes */ 1557 mmiowb(); 1558 1559 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1560 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 1561 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1562} 1563 1564void bnx2x_int_disable(struct bnx2x *bp) 1565{ 1566 if (bp->common.int_block == INT_BLOCK_HC) 1567 bnx2x_hc_int_disable(bp); 1568 else 1569 bnx2x_igu_int_disable(bp); 1570} 1571 1572void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1573{ 1574 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1575 int i, offset; 1576 1577 if (disable_hw) 1578 /* prevent the HW from sending interrupts */ 1579 bnx2x_int_disable(bp); 1580 1581 /* make sure all ISRs are done */ 1582 if (msix) { 1583 synchronize_irq(bp->msix_table[0].vector); 1584 offset = 1; 1585#ifdef BCM_CNIC 1586 offset++; 1587#endif 1588 for_each_eth_queue(bp, i) 1589 synchronize_irq(bp->msix_table[offset++].vector); 1590 } else 1591 synchronize_irq(bp->pdev->irq); 1592 1593 /* make sure sp_task is not running */ 1594 cancel_delayed_work(&bp->sp_task); 1595 cancel_delayed_work(&bp->period_task); 1596 flush_workqueue(bnx2x_wq); 1597} 1598 1599/* fast path */ 1600 1601/* 1602 * General service functions 1603 */ 1604 1605/* Return true if succeeded to acquire the lock */ 1606static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1607{ 1608 u32 lock_status; 1609 u32 resource_bit = (1 << resource); 1610 int func = BP_FUNC(bp); 1611 u32 hw_lock_control_reg; 1612 1613 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource); 1614 1615 /* Validating that the resource is within range */ 1616 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1617 DP(NETIF_MSG_HW, 1618 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1619 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1620 return false; 1621 } 1622 1623 if (func <= 5) 1624 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1625 else 1626 hw_lock_control_reg = 1627 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1628 1629 /* Try to acquire the lock */ 1630 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1631 lock_status = REG_RD(bp, hw_lock_control_reg); 1632 if (lock_status & resource_bit) 1633 return true; 1634 1635 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource); 1636 return false; 1637} 1638 1639/** 1640 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1641 * 1642 * @bp: driver handle 1643 * 1644 * Returns the recovery leader resource id according to the engine this function 1645 * belongs to. Currently only only 2 engines is supported. 1646 */ 1647static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1648{ 1649 if (BP_PATH(bp)) 1650 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1651 else 1652 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1653} 1654 1655/** 1656 * bnx2x_trylock_leader_lock- try to aquire a leader lock. 1657 * 1658 * @bp: driver handle 1659 * 1660 * Tries to aquire a leader lock for cuurent engine. 1661 */ 1662static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1663{ 1664 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1665} 1666 1667#ifdef BCM_CNIC 1668static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1669#endif 1670 1671void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1672{ 1673 struct bnx2x *bp = fp->bp; 1674 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1675 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1676 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1677 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj; 1678 1679 DP(BNX2X_MSG_SP, 1680 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1681 fp->index, cid, command, bp->state, 1682 rr_cqe->ramrod_cqe.ramrod_type); 1683 1684 switch (command) { 1685 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1686 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1687 drv_cmd = BNX2X_Q_CMD_UPDATE; 1688 break; 1689 1690 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1691 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1692 drv_cmd = BNX2X_Q_CMD_SETUP; 1693 break; 1694 1695 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1696 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1697 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1698 break; 1699 1700 case (RAMROD_CMD_ID_ETH_HALT): 1701 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1702 drv_cmd = BNX2X_Q_CMD_HALT; 1703 break; 1704 1705 case (RAMROD_CMD_ID_ETH_TERMINATE): 1706 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); 1707 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1708 break; 1709 1710 case (RAMROD_CMD_ID_ETH_EMPTY): 1711 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1712 drv_cmd = BNX2X_Q_CMD_EMPTY; 1713 break; 1714 1715 default: 1716 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1717 command, fp->index); 1718 return; 1719 } 1720 1721 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1722 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1723 /* q_obj->complete_cmd() failure means that this was 1724 * an unexpected completion. 1725 * 1726 * In this case we don't want to increase the bp->spq_left 1727 * because apparently we haven't sent this command the first 1728 * place. 1729 */ 1730#ifdef BNX2X_STOP_ON_ERROR 1731 bnx2x_panic(); 1732#else 1733 return; 1734#endif 1735 1736 smp_mb__before_atomic_inc(); 1737 atomic_inc(&bp->cq_spq_left); 1738 /* push the change in bp->spq_left and towards the memory */ 1739 smp_mb__after_atomic_inc(); 1740 1741 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1742 1743 return; 1744} 1745 1746void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 1747 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) 1748{ 1749 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; 1750 1751 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, 1752 start); 1753} 1754 1755irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1756{ 1757 struct bnx2x *bp = netdev_priv(dev_instance); 1758 u16 status = bnx2x_ack_int(bp); 1759 u16 mask; 1760 int i; 1761 u8 cos; 1762 1763 /* Return here if interrupt is shared and it's not for us */ 1764 if (unlikely(status == 0)) { 1765 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1766 return IRQ_NONE; 1767 } 1768 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1769 1770#ifdef BNX2X_STOP_ON_ERROR 1771 if (unlikely(bp->panic)) 1772 return IRQ_HANDLED; 1773#endif 1774 1775 for_each_eth_queue(bp, i) { 1776 struct bnx2x_fastpath *fp = &bp->fp[i]; 1777 1778 mask = 0x2 << (fp->index + CNIC_PRESENT); 1779 if (status & mask) { 1780 /* Handle Rx or Tx according to SB id */ 1781 prefetch(fp->rx_cons_sb); 1782 for_each_cos_in_tx_queue(fp, cos) 1783 prefetch(fp->txdata[cos].tx_cons_sb); 1784 prefetch(&fp->sb_running_index[SM_RX_ID]); 1785 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 1786 status &= ~mask; 1787 } 1788 } 1789 1790#ifdef BCM_CNIC 1791 mask = 0x2; 1792 if (status & (mask | 0x1)) { 1793 struct cnic_ops *c_ops = NULL; 1794 1795 if (likely(bp->state == BNX2X_STATE_OPEN)) { 1796 rcu_read_lock(); 1797 c_ops = rcu_dereference(bp->cnic_ops); 1798 if (c_ops) 1799 c_ops->cnic_handler(bp->cnic_data, NULL); 1800 rcu_read_unlock(); 1801 } 1802 1803 status &= ~mask; 1804 } 1805#endif 1806 1807 if (unlikely(status & 0x1)) { 1808 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1809 1810 status &= ~0x1; 1811 if (!status) 1812 return IRQ_HANDLED; 1813 } 1814 1815 if (unlikely(status)) 1816 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1817 status); 1818 1819 return IRQ_HANDLED; 1820} 1821 1822/* Link */ 1823 1824/* 1825 * General service functions 1826 */ 1827 1828int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 1829{ 1830 u32 lock_status; 1831 u32 resource_bit = (1 << resource); 1832 int func = BP_FUNC(bp); 1833 u32 hw_lock_control_reg; 1834 int cnt; 1835 1836 /* Validating that the resource is within range */ 1837 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1838 DP(NETIF_MSG_HW, 1839 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1840 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1841 return -EINVAL; 1842 } 1843 1844 if (func <= 5) { 1845 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1846 } else { 1847 hw_lock_control_reg = 1848 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1849 } 1850 1851 /* Validating that the resource is not already taken */ 1852 lock_status = REG_RD(bp, hw_lock_control_reg); 1853 if (lock_status & resource_bit) { 1854 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1855 lock_status, resource_bit); 1856 return -EEXIST; 1857 } 1858 1859 /* Try for 5 second every 5ms */ 1860 for (cnt = 0; cnt < 1000; cnt++) { 1861 /* Try to acquire the lock */ 1862 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1863 lock_status = REG_RD(bp, hw_lock_control_reg); 1864 if (lock_status & resource_bit) 1865 return 0; 1866 1867 msleep(5); 1868 } 1869 DP(NETIF_MSG_HW, "Timeout\n"); 1870 return -EAGAIN; 1871} 1872 1873int bnx2x_release_leader_lock(struct bnx2x *bp) 1874{ 1875 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1876} 1877 1878int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 1879{ 1880 u32 lock_status; 1881 u32 resource_bit = (1 << resource); 1882 int func = BP_FUNC(bp); 1883 u32 hw_lock_control_reg; 1884 1885 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource); 1886 1887 /* Validating that the resource is within range */ 1888 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1889 DP(NETIF_MSG_HW, 1890 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1891 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1892 return -EINVAL; 1893 } 1894 1895 if (func <= 5) { 1896 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1897 } else { 1898 hw_lock_control_reg = 1899 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1900 } 1901 1902 /* Validating that the resource is currently taken */ 1903 lock_status = REG_RD(bp, hw_lock_control_reg); 1904 if (!(lock_status & resource_bit)) { 1905 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1906 lock_status, resource_bit); 1907 return -EFAULT; 1908 } 1909 1910 REG_WR(bp, hw_lock_control_reg, resource_bit); 1911 return 0; 1912} 1913 1914 1915int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 1916{ 1917 /* The GPIO should be swapped if swap register is set and active */ 1918 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1919 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1920 int gpio_shift = gpio_num + 1921 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1922 u32 gpio_mask = (1 << gpio_shift); 1923 u32 gpio_reg; 1924 int value; 1925 1926 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1927 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1928 return -EINVAL; 1929 } 1930 1931 /* read GPIO value */ 1932 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1933 1934 /* get the requested pin value */ 1935 if ((gpio_reg & gpio_mask) == gpio_mask) 1936 value = 1; 1937 else 1938 value = 0; 1939 1940 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); 1941 1942 return value; 1943} 1944 1945int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 1946{ 1947 /* The GPIO should be swapped if swap register is set and active */ 1948 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1949 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1950 int gpio_shift = gpio_num + 1951 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1952 u32 gpio_mask = (1 << gpio_shift); 1953 u32 gpio_reg; 1954 1955 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1956 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1957 return -EINVAL; 1958 } 1959 1960 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1961 /* read GPIO and mask except the float bits */ 1962 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 1963 1964 switch (mode) { 1965 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1966 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n", 1967 gpio_num, gpio_shift); 1968 /* clear FLOAT and set CLR */ 1969 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1970 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 1971 break; 1972 1973 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 1974 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n", 1975 gpio_num, gpio_shift); 1976 /* clear FLOAT and set SET */ 1977 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1978 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 1979 break; 1980 1981 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 1982 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", 1983 gpio_num, gpio_shift); 1984 /* set FLOAT */ 1985 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1986 break; 1987 1988 default: 1989 break; 1990 } 1991 1992 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 1993 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1994 1995 return 0; 1996} 1997 1998int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 1999{ 2000 u32 gpio_reg = 0; 2001 int rc = 0; 2002 2003 /* Any port swapping should be handled by caller. */ 2004 2005 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2006 /* read GPIO and mask except the float bits */ 2007 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 2008 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2009 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 2010 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 2011 2012 switch (mode) { 2013 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2014 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 2015 /* set CLR */ 2016 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2017 break; 2018 2019 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2020 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 2021 /* set SET */ 2022 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2023 break; 2024 2025 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2026 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2027 /* set FLOAT */ 2028 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2029 break; 2030 2031 default: 2032 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2033 rc = -EINVAL; 2034 break; 2035 } 2036 2037 if (rc == 0) 2038 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2039 2040 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2041 2042 return rc; 2043} 2044 2045int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2046{ 2047 /* The GPIO should be swapped if swap register is set and active */ 2048 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2049 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2050 int gpio_shift = gpio_num + 2051 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2052 u32 gpio_mask = (1 << gpio_shift); 2053 u32 gpio_reg; 2054 2055 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2056 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2057 return -EINVAL; 2058 } 2059 2060 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2061 /* read GPIO int */ 2062 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2063 2064 switch (mode) { 2065 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2066 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> " 2067 "output low\n", gpio_num, gpio_shift); 2068 /* clear SET and set CLR */ 2069 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2070 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2071 break; 2072 2073 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2074 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> " 2075 "output high\n", gpio_num, gpio_shift); 2076 /* clear CLR and set SET */ 2077 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2078 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2079 break; 2080 2081 default: 2082 break; 2083 } 2084 2085 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2086 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2087 2088 return 0; 2089} 2090 2091static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) 2092{ 2093 u32 spio_mask = (1 << spio_num); 2094 u32 spio_reg; 2095 2096 if ((spio_num < MISC_REGISTERS_SPIO_4) || 2097 (spio_num > MISC_REGISTERS_SPIO_7)) { 2098 BNX2X_ERR("Invalid SPIO %d\n", spio_num); 2099 return -EINVAL; 2100 } 2101 2102 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2103 /* read SPIO and mask except the float bits */ 2104 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); 2105 2106 switch (mode) { 2107 case MISC_REGISTERS_SPIO_OUTPUT_LOW: 2108 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); 2109 /* clear FLOAT and set CLR */ 2110 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2111 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); 2112 break; 2113 2114 case MISC_REGISTERS_SPIO_OUTPUT_HIGH: 2115 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); 2116 /* clear FLOAT and set SET */ 2117 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2118 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); 2119 break; 2120 2121 case MISC_REGISTERS_SPIO_INPUT_HI_Z: 2122 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num); 2123 /* set FLOAT */ 2124 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2125 break; 2126 2127 default: 2128 break; 2129 } 2130 2131 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2132 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2133 2134 return 0; 2135} 2136 2137void bnx2x_calc_fc_adv(struct bnx2x *bp) 2138{ 2139 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2140 switch (bp->link_vars.ieee_fc & 2141 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2142 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 2143 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2144 ADVERTISED_Pause); 2145 break; 2146 2147 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2148 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2149 ADVERTISED_Pause); 2150 break; 2151 2152 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2153 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2154 break; 2155 2156 default: 2157 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2158 ADVERTISED_Pause); 2159 break; 2160 } 2161} 2162 2163u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2164{ 2165 if (!BP_NOMCP(bp)) { 2166 u8 rc; 2167 int cfx_idx = bnx2x_get_link_cfg_idx(bp); 2168 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2169 /* 2170 * Initialize link parameters structure variables 2171 * It is recommended to turn off RX FC for jumbo frames 2172 * for better performance 2173 */ 2174 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2175 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2176 else 2177 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2178 2179 bnx2x_acquire_phy_lock(bp); 2180 2181 if (load_mode == LOAD_DIAG) { 2182 struct link_params *lp = &bp->link_params; 2183 lp->loopback_mode = LOOPBACK_XGXS; 2184 /* do PHY loopback at 10G speed, if possible */ 2185 if (lp->req_line_speed[cfx_idx] < SPEED_10000) { 2186 if (lp->speed_cap_mask[cfx_idx] & 2187 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2188 lp->req_line_speed[cfx_idx] = 2189 SPEED_10000; 2190 else 2191 lp->req_line_speed[cfx_idx] = 2192 SPEED_1000; 2193 } 2194 } 2195 2196 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2197 2198 bnx2x_release_phy_lock(bp); 2199 2200 bnx2x_calc_fc_adv(bp); 2201 2202 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { 2203 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2204 bnx2x_link_report(bp); 2205 } else 2206 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2207 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2208 return rc; 2209 } 2210 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2211 return -EINVAL; 2212} 2213 2214void bnx2x_link_set(struct bnx2x *bp) 2215{ 2216 if (!BP_NOMCP(bp)) { 2217 bnx2x_acquire_phy_lock(bp); 2218 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2219 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2220 bnx2x_release_phy_lock(bp); 2221 2222 bnx2x_calc_fc_adv(bp); 2223 } else 2224 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2225} 2226 2227static void bnx2x__link_reset(struct bnx2x *bp) 2228{ 2229 if (!BP_NOMCP(bp)) { 2230 bnx2x_acquire_phy_lock(bp); 2231 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2232 bnx2x_release_phy_lock(bp); 2233 } else 2234 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2235} 2236 2237u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2238{ 2239 u8 rc = 0; 2240 2241 if (!BP_NOMCP(bp)) { 2242 bnx2x_acquire_phy_lock(bp); 2243 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2244 is_serdes); 2245 bnx2x_release_phy_lock(bp); 2246 } else 2247 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2248 2249 return rc; 2250} 2251 2252static void bnx2x_init_port_minmax(struct bnx2x *bp) 2253{ 2254 u32 r_param = bp->link_vars.line_speed / 8; 2255 u32 fair_periodic_timeout_usec; 2256 u32 t_fair; 2257 2258 memset(&(bp->cmng.rs_vars), 0, 2259 sizeof(struct rate_shaping_vars_per_port)); 2260 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port)); 2261 2262 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ 2263 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4; 2264 2265 /* this is the threshold below which no timer arming will occur 2266 1.25 coefficient is for the threshold to be a little bigger 2267 than the real time, to compensate for timer in-accuracy */ 2268 bp->cmng.rs_vars.rs_threshold = 2269 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; 2270 2271 /* resolution of fairness timer */ 2272 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; 2273 /* for 10G it is 1000usec. for 1G it is 10000usec. */ 2274 t_fair = T_FAIR_COEF / bp->link_vars.line_speed; 2275 2276 /* this is the threshold below which we won't arm the timer anymore */ 2277 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES; 2278 2279 /* we multiply by 1e3/8 to get bytes/msec. 2280 We don't want the credits to pass a credit 2281 of the t_fair*FAIR_MEM (algorithm resolution) */ 2282 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM; 2283 /* since each tick is 4 usec */ 2284 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4; 2285} 2286 2287/* Calculates the sum of vn_min_rates. 2288 It's needed for further normalizing of the min_rates. 2289 Returns: 2290 sum of vn_min_rates. 2291 or 2292 0 - if all the min_rates are 0. 2293 In the later case fainess algorithm should be deactivated. 2294 If not all min_rates are zero then those that are zeroes will be set to 1. 2295 */ 2296static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) 2297{ 2298 int all_zero = 1; 2299 int vn; 2300 2301 bp->vn_weight_sum = 0; 2302 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2303 u32 vn_cfg = bp->mf_config[vn]; 2304 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2305 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2306 2307 /* Skip hidden vns */ 2308 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2309 continue; 2310 2311 /* If min rate is zero - set it to 1 */ 2312 if (!vn_min_rate) 2313 vn_min_rate = DEF_MIN_RATE; 2314 else 2315 all_zero = 0; 2316 2317 bp->vn_weight_sum += vn_min_rate; 2318 } 2319 2320 /* if ETS or all min rates are zeros - disable fairness */ 2321 if (BNX2X_IS_ETS_ENABLED(bp)) { 2322 bp->cmng.flags.cmng_enables &= 2323 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2324 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2325 } else if (all_zero) { 2326 bp->cmng.flags.cmng_enables &= 2327 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2328 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2329 " fairness will be disabled\n"); 2330 } else 2331 bp->cmng.flags.cmng_enables |= 2332 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2333} 2334 2335static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) 2336{ 2337 struct rate_shaping_vars_per_vn m_rs_vn; 2338 struct fairness_vars_per_vn m_fair_vn; 2339 u32 vn_cfg = bp->mf_config[vn]; 2340 int func = func_by_vn(bp, vn); 2341 u16 vn_min_rate, vn_max_rate; 2342 int i; 2343 2344 /* If function is hidden - set min and max to zeroes */ 2345 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 2346 vn_min_rate = 0; 2347 vn_max_rate = 0; 2348 2349 } else { 2350 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2351 2352 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2353 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2354 /* If fairness is enabled (not all min rates are zeroes) and 2355 if current min rate is zero - set it to 1. 2356 This is a requirement of the algorithm. */ 2357 if (bp->vn_weight_sum && (vn_min_rate == 0)) 2358 vn_min_rate = DEF_MIN_RATE; 2359 2360 if (IS_MF_SI(bp)) 2361 /* maxCfg in percents of linkspeed */ 2362 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2363 else 2364 /* maxCfg is absolute in 100Mb units */ 2365 vn_max_rate = maxCfg * 100; 2366 } 2367 2368 DP(NETIF_MSG_IFUP, 2369 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n", 2370 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); 2371 2372 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn)); 2373 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); 2374 2375 /* global vn counter - maximal Mbps for this vn */ 2376 m_rs_vn.vn_counter.rate = vn_max_rate; 2377 2378 /* quota - number of bytes transmitted in this period */ 2379 m_rs_vn.vn_counter.quota = 2380 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8; 2381 2382 if (bp->vn_weight_sum) { 2383 /* credit for each period of the fairness algorithm: 2384 number of bytes in T_FAIR (the vn share the port rate). 2385 vn_weight_sum should not be larger than 10000, thus 2386 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater 2387 than zero */ 2388 m_fair_vn.vn_credit_delta = 2389 max_t(u32, (vn_min_rate * (T_FAIR_COEF / 2390 (8 * bp->vn_weight_sum))), 2391 (bp->cmng.fair_vars.fair_threshold + 2392 MIN_ABOVE_THRESH)); 2393 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n", 2394 m_fair_vn.vn_credit_delta); 2395 } 2396 2397 /* Store it to internal memory */ 2398 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++) 2399 REG_WR(bp, BAR_XSTRORM_INTMEM + 2400 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4, 2401 ((u32 *)(&m_rs_vn))[i]); 2402 2403 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++) 2404 REG_WR(bp, BAR_XSTRORM_INTMEM + 2405 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4, 2406 ((u32 *)(&m_fair_vn))[i]); 2407} 2408 2409static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2410{ 2411 if (CHIP_REV_IS_SLOW(bp)) 2412 return CMNG_FNS_NONE; 2413 if (IS_MF(bp)) 2414 return CMNG_FNS_MINMAX; 2415 2416 return CMNG_FNS_NONE; 2417} 2418 2419void bnx2x_read_mf_cfg(struct bnx2x *bp) 2420{ 2421 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2422 2423 if (BP_NOMCP(bp)) 2424 return; /* what should be the default bvalue in this case */ 2425 2426 /* For 2 port configuration the absolute function number formula 2427 * is: 2428 * abs_func = 2 * vn + BP_PORT + BP_PATH 2429 * 2430 * and there are 4 functions per port 2431 * 2432 * For 4 port configuration it is 2433 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2434 * 2435 * and there are 2 functions per port 2436 */ 2437 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2438 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2439 2440 if (func >= E1H_FUNC_MAX) 2441 break; 2442 2443 bp->mf_config[vn] = 2444 MF_CFG_RD(bp, func_mf_config[func].config); 2445 } 2446} 2447 2448static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2449{ 2450 2451 if (cmng_type == CMNG_FNS_MINMAX) { 2452 int vn; 2453 2454 /* clear cmng_enables */ 2455 bp->cmng.flags.cmng_enables = 0; 2456 2457 /* read mf conf from shmem */ 2458 if (read_cfg) 2459 bnx2x_read_mf_cfg(bp); 2460 2461 /* Init rate shaping and fairness contexts */ 2462 bnx2x_init_port_minmax(bp); 2463 2464 /* vn_weight_sum and enable fairness if not 0 */ 2465 bnx2x_calc_vn_weight_sum(bp); 2466 2467 /* calculate and set min-max rate for each vn */ 2468 if (bp->port.pmf) 2469 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) 2470 bnx2x_init_vn_minmax(bp, vn); 2471 2472 /* always enable rate shaping and fairness */ 2473 bp->cmng.flags.cmng_enables |= 2474 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2475 if (!bp->vn_weight_sum) 2476 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2477 " fairness will be disabled\n"); 2478 return; 2479 } 2480 2481 /* rate shaping and fairness are disabled */ 2482 DP(NETIF_MSG_IFUP, 2483 "rate shaping and fairness are disabled\n"); 2484} 2485 2486/* This function is called upon link interrupt */ 2487static void bnx2x_link_attn(struct bnx2x *bp) 2488{ 2489 /* Make sure that we are synced with the current statistics */ 2490 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2491 2492 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2493 2494 if (bp->link_vars.link_up) { 2495 2496 /* dropless flow control */ 2497 if (!CHIP_IS_E1(bp) && bp->dropless_fc) { 2498 int port = BP_PORT(bp); 2499 u32 pause_enabled = 0; 2500 2501 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2502 pause_enabled = 1; 2503 2504 REG_WR(bp, BAR_USTRORM_INTMEM + 2505 USTORM_ETH_PAUSE_ENABLED_OFFSET(port), 2506 pause_enabled); 2507 } 2508 2509 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2510 struct host_port_stats *pstats; 2511 2512 pstats = bnx2x_sp(bp, port_stats); 2513 /* reset old mac stats */ 2514 memset(&(pstats->mac_stx[0]), 0, 2515 sizeof(struct mac_stx)); 2516 } 2517 if (bp->state == BNX2X_STATE_OPEN) 2518 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2519 } 2520 2521 if (bp->link_vars.link_up && bp->link_vars.line_speed) { 2522 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2523 2524 if (cmng_fns != CMNG_FNS_NONE) { 2525 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2526 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2527 } else 2528 /* rate shaping and fairness are disabled */ 2529 DP(NETIF_MSG_IFUP, 2530 "single function mode without fairness\n"); 2531 } 2532 2533 __bnx2x_link_report(bp); 2534 2535 if (IS_MF(bp)) 2536 bnx2x_link_sync_notify(bp); 2537} 2538 2539void bnx2x__link_status_update(struct bnx2x *bp) 2540{ 2541 if (bp->state != BNX2X_STATE_OPEN) 2542 return; 2543 2544 /* read updated dcb configuration */ 2545 bnx2x_dcbx_pmf_update(bp); 2546 2547 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2548 2549 if (bp->link_vars.link_up) 2550 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2551 else 2552 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2553 2554 /* indicate link status */ 2555 bnx2x_link_report(bp); 2556} 2557 2558static void bnx2x_pmf_update(struct bnx2x *bp) 2559{ 2560 int port = BP_PORT(bp); 2561 u32 val; 2562 2563 bp->port.pmf = 1; 2564 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf); 2565 2566 /* 2567 * We need the mb() to ensure the ordering between the writing to 2568 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2569 */ 2570 smp_mb(); 2571 2572 /* queue a periodic task */ 2573 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2574 2575 bnx2x_dcbx_pmf_update(bp); 2576 2577 /* enable nig attention */ 2578 val = (0xff0f | (1 << (BP_VN(bp) + 4))); 2579 if (bp->common.int_block == INT_BLOCK_HC) { 2580 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 2581 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 2582 } else if (!CHIP_IS_E1x(bp)) { 2583 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 2584 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 2585 } 2586 2587 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 2588} 2589 2590/* end of Link */ 2591 2592/* slow path */ 2593 2594/* 2595 * General service functions 2596 */ 2597 2598/* send the MCP a request, block until there is a reply */ 2599u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 2600{ 2601 int mb_idx = BP_FW_MB_IDX(bp); 2602 u32 seq; 2603 u32 rc = 0; 2604 u32 cnt = 1; 2605 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 2606 2607 mutex_lock(&bp->fw_mb_mutex); 2608 seq = ++bp->fw_seq; 2609 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 2610 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 2611 2612 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 2613 (command | seq), param); 2614 2615 do { 2616 /* let the FW do it's magic ... */ 2617 msleep(delay); 2618 2619 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 2620 2621 /* Give the FW up to 5 second (500*10ms) */ 2622 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2623 2624 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 2625 cnt*delay, rc, seq); 2626 2627 /* is this a reply to our command? */ 2628 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 2629 rc &= FW_MSG_CODE_MASK; 2630 else { 2631 /* FW BUG! */ 2632 BNX2X_ERR("FW failed to respond!\n"); 2633 bnx2x_fw_dump(bp); 2634 rc = 0; 2635 } 2636 mutex_unlock(&bp->fw_mb_mutex); 2637 2638 return rc; 2639} 2640 2641 2642void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 2643{ 2644 if (CHIP_IS_E1x(bp)) { 2645 struct tstorm_eth_function_common_config tcfg = {0}; 2646 2647 storm_memset_func_cfg(bp, &tcfg, p->func_id); 2648 } 2649 2650 /* Enable the function in the FW */ 2651 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 2652 storm_memset_func_en(bp, p->func_id, 1); 2653 2654 /* spq */ 2655 if (p->func_flgs & FUNC_FLG_SPQ) { 2656 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 2657 REG_WR(bp, XSEM_REG_FAST_MEMORY + 2658 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 2659 } 2660} 2661 2662/** 2663 * bnx2x_get_tx_only_flags - Return common flags 2664 * 2665 * @bp device handle 2666 * @fp queue handle 2667 * @zero_stats TRUE if statistics zeroing is needed 2668 * 2669 * Return the flags that are common for the Tx-only and not normal connections. 2670 */ 2671static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 2672 struct bnx2x_fastpath *fp, 2673 bool zero_stats) 2674{ 2675 unsigned long flags = 0; 2676 2677 /* PF driver will always initialize the Queue to an ACTIVE state */ 2678 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 2679 2680 /* tx only connections collect statistics (on the same index as the 2681 * parent connection). The statistics are zeroed when the parent 2682 * connection is initialized. 2683 */ 2684 2685 __set_bit(BNX2X_Q_FLG_STATS, &flags); 2686 if (zero_stats) 2687 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 2688 2689 2690 return flags; 2691} 2692 2693static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 2694 struct bnx2x_fastpath *fp, 2695 bool leading) 2696{ 2697 unsigned long flags = 0; 2698 2699 /* calculate other queue flags */ 2700 if (IS_MF_SD(bp)) 2701 __set_bit(BNX2X_Q_FLG_OV, &flags); 2702 2703 if (IS_FCOE_FP(fp)) 2704 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 2705 2706 if (!fp->disable_tpa) { 2707 __set_bit(BNX2X_Q_FLG_TPA, &flags); 2708 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 2709 } 2710 2711 if (leading) { 2712 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 2713 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 2714 } 2715 2716 /* Always set HW VLAN stripping */ 2717 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 2718 2719 2720 return flags | bnx2x_get_common_flags(bp, fp, true); 2721} 2722 2723static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 2724 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 2725 u8 cos) 2726{ 2727 gen_init->stat_id = bnx2x_stats_id(fp); 2728 gen_init->spcl_id = fp->cl_id; 2729 2730 /* Always use mini-jumbo MTU for FCoE L2 ring */ 2731 if (IS_FCOE_FP(fp)) 2732 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 2733 else 2734 gen_init->mtu = bp->dev->mtu; 2735 2736 gen_init->cos = cos; 2737} 2738 2739static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 2740 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 2741 struct bnx2x_rxq_setup_params *rxq_init) 2742{ 2743 u8 max_sge = 0; 2744 u16 sge_sz = 0; 2745 u16 tpa_agg_size = 0; 2746 2747 if (!fp->disable_tpa) { 2748 pause->sge_th_lo = SGE_TH_LO(bp); 2749 pause->sge_th_hi = SGE_TH_HI(bp); 2750 2751 /* validate SGE ring has enough to cross high threshold */ 2752 WARN_ON(bp->dropless_fc && 2753 pause->sge_th_hi + FW_PREFETCH_CNT > 2754 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); 2755 2756 tpa_agg_size = min_t(u32, 2757 (min_t(u32, 8, MAX_SKB_FRAGS) * 2758 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); 2759 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 2760 SGE_PAGE_SHIFT; 2761 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 2762 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 2763 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, 2764 0xffff); 2765 } 2766 2767 /* pause - not for e1 */ 2768 if (!CHIP_IS_E1(bp)) { 2769 pause->bd_th_lo = BD_TH_LO(bp); 2770 pause->bd_th_hi = BD_TH_HI(bp); 2771 2772 pause->rcq_th_lo = RCQ_TH_LO(bp); 2773 pause->rcq_th_hi = RCQ_TH_HI(bp); 2774 /* 2775 * validate that rings have enough entries to cross 2776 * high thresholds 2777 */ 2778 WARN_ON(bp->dropless_fc && 2779 pause->bd_th_hi + FW_PREFETCH_CNT > 2780 bp->rx_ring_size); 2781 WARN_ON(bp->dropless_fc && 2782 pause->rcq_th_hi + FW_PREFETCH_CNT > 2783 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); 2784 2785 pause->pri_map = 1; 2786 } 2787 2788 /* rxq setup */ 2789 rxq_init->dscr_map = fp->rx_desc_mapping; 2790 rxq_init->sge_map = fp->rx_sge_mapping; 2791 rxq_init->rcq_map = fp->rx_comp_mapping; 2792 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 2793 2794 /* This should be a maximum number of data bytes that may be 2795 * placed on the BD (not including paddings). 2796 */ 2797 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - 2798 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; 2799 2800 rxq_init->cl_qzone_id = fp->cl_qzone_id; 2801 rxq_init->tpa_agg_sz = tpa_agg_size; 2802 rxq_init->sge_buf_sz = sge_sz; 2803 rxq_init->max_sges_pkt = max_sge; 2804 rxq_init->rss_engine_id = BP_FUNC(bp); 2805 2806 /* Maximum number or simultaneous TPA aggregation for this Queue. 2807 * 2808 * For PF Clients it should be the maximum avaliable number. 2809 * VF driver(s) may want to define it to a smaller value. 2810 */ 2811 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); 2812 2813 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 2814 rxq_init->fw_sb_id = fp->fw_sb_id; 2815 2816 if (IS_FCOE_FP(fp)) 2817 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 2818 else 2819 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 2820} 2821 2822static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 2823 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 2824 u8 cos) 2825{ 2826 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping; 2827 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 2828 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 2829 txq_init->fw_sb_id = fp->fw_sb_id; 2830 2831 /* 2832 * set the tss leading client id for TX classfication == 2833 * leading RSS client id 2834 */ 2835 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 2836 2837 if (IS_FCOE_FP(fp)) { 2838 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 2839 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 2840 } 2841} 2842 2843static void bnx2x_pf_init(struct bnx2x *bp) 2844{ 2845 struct bnx2x_func_init_params func_init = {0}; 2846 struct event_ring_data eq_data = { {0} }; 2847 u16 flags; 2848 2849 if (!CHIP_IS_E1x(bp)) { 2850 /* reset IGU PF statistics: MSIX + ATTN */ 2851 /* PF */ 2852 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2853 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2854 (CHIP_MODE_IS_4_PORT(bp) ? 2855 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2856 /* ATTN */ 2857 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2858 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2859 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 2860 (CHIP_MODE_IS_4_PORT(bp) ? 2861 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2862 } 2863 2864 /* function setup flags */ 2865 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 2866 2867 /* This flag is relevant for E1x only. 2868 * E2 doesn't have a TPA configuration in a function level. 2869 */ 2870 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; 2871 2872 func_init.func_flgs = flags; 2873 func_init.pf_id = BP_FUNC(bp); 2874 func_init.func_id = BP_FUNC(bp); 2875 func_init.spq_map = bp->spq_mapping; 2876 func_init.spq_prod = bp->spq_prod_idx; 2877 2878 bnx2x_func_init(bp, &func_init); 2879 2880 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 2881 2882 /* 2883 * Congestion management values depend on the link rate 2884 * There is no active link so initial link rate is set to 10 Gbps. 2885 * When the link comes up The congestion management values are 2886 * re-calculated according to the actual link rate. 2887 */ 2888 bp->link_vars.line_speed = SPEED_10000; 2889 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 2890 2891 /* Only the PMF sets the HW */ 2892 if (bp->port.pmf) 2893 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2894 2895 /* init Event Queue */ 2896 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 2897 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 2898 eq_data.producer = bp->eq_prod; 2899 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 2900 eq_data.sb_id = DEF_SB_ID; 2901 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 2902} 2903 2904 2905static void bnx2x_e1h_disable(struct bnx2x *bp) 2906{ 2907 int port = BP_PORT(bp); 2908 2909 bnx2x_tx_disable(bp); 2910 2911 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 2912} 2913 2914static void bnx2x_e1h_enable(struct bnx2x *bp) 2915{ 2916 int port = BP_PORT(bp); 2917 2918 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 2919 2920 /* Tx queue should be only reenabled */ 2921 netif_tx_wake_all_queues(bp->dev); 2922 2923 /* 2924 * Should not call netif_carrier_on since it will be called if the link 2925 * is up when checking for link state 2926 */ 2927} 2928 2929#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 2930 2931static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) 2932{ 2933 struct eth_stats_info *ether_stat = 2934 &bp->slowpath->drv_info_to_mcp.ether_stat; 2935 2936 /* leave last char as NULL */ 2937 memcpy(ether_stat->version, DRV_MODULE_VERSION, 2938 ETH_STAT_INFO_VERSION_LEN - 1); 2939 2940 bp->fp[0].mac_obj.get_n_elements(bp, &bp->fp[0].mac_obj, 2941 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 2942 ether_stat->mac_local); 2943 2944 ether_stat->mtu_size = bp->dev->mtu; 2945 2946 if (bp->dev->features & NETIF_F_RXCSUM) 2947 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 2948 if (bp->dev->features & NETIF_F_TSO) 2949 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 2950 ether_stat->feature_flags |= bp->common.boot_mode; 2951 2952 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; 2953 2954 ether_stat->txq_size = bp->tx_ring_size; 2955 ether_stat->rxq_size = bp->rx_ring_size; 2956} 2957 2958static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) 2959{ 2960#ifdef BCM_CNIC 2961 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 2962 struct fcoe_stats_info *fcoe_stat = 2963 &bp->slowpath->drv_info_to_mcp.fcoe_stat; 2964 2965 memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN); 2966 2967 fcoe_stat->qos_priority = 2968 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; 2969 2970 /* insert FCoE stats from ramrod response */ 2971 if (!NO_FCOE(bp)) { 2972 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = 2973 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2974 tstorm_queue_statistics; 2975 2976 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = 2977 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2978 xstorm_queue_statistics; 2979 2980 struct fcoe_statistics_params *fw_fcoe_stat = 2981 &bp->fw_stats_data->fcoe; 2982 2983 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo, 2984 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); 2985 2986 ADD_64(fcoe_stat->rx_bytes_hi, 2987 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, 2988 fcoe_stat->rx_bytes_lo, 2989 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); 2990 2991 ADD_64(fcoe_stat->rx_bytes_hi, 2992 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, 2993 fcoe_stat->rx_bytes_lo, 2994 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); 2995 2996 ADD_64(fcoe_stat->rx_bytes_hi, 2997 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, 2998 fcoe_stat->rx_bytes_lo, 2999 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); 3000 3001 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3002 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); 3003 3004 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3005 fcoe_q_tstorm_stats->rcv_ucast_pkts); 3006 3007 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3008 fcoe_q_tstorm_stats->rcv_bcast_pkts); 3009 3010 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3011 fcoe_q_tstorm_stats->rcv_mcast_pkts); 3012 3013 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo, 3014 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); 3015 3016 ADD_64(fcoe_stat->tx_bytes_hi, 3017 fcoe_q_xstorm_stats->ucast_bytes_sent.hi, 3018 fcoe_stat->tx_bytes_lo, 3019 fcoe_q_xstorm_stats->ucast_bytes_sent.lo); 3020 3021 ADD_64(fcoe_stat->tx_bytes_hi, 3022 fcoe_q_xstorm_stats->bcast_bytes_sent.hi, 3023 fcoe_stat->tx_bytes_lo, 3024 fcoe_q_xstorm_stats->bcast_bytes_sent.lo); 3025 3026 ADD_64(fcoe_stat->tx_bytes_hi, 3027 fcoe_q_xstorm_stats->mcast_bytes_sent.hi, 3028 fcoe_stat->tx_bytes_lo, 3029 fcoe_q_xstorm_stats->mcast_bytes_sent.lo); 3030 3031 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3032 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); 3033 3034 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3035 fcoe_q_xstorm_stats->ucast_pkts_sent); 3036 3037 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3038 fcoe_q_xstorm_stats->bcast_pkts_sent); 3039 3040 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3041 fcoe_q_xstorm_stats->mcast_pkts_sent); 3042 } 3043 3044 /* ask L5 driver to add data to the struct */ 3045 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); 3046#endif 3047} 3048 3049static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) 3050{ 3051#ifdef BCM_CNIC 3052 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3053 struct iscsi_stats_info *iscsi_stat = 3054 &bp->slowpath->drv_info_to_mcp.iscsi_stat; 3055 3056 memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); 3057 3058 iscsi_stat->qos_priority = 3059 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; 3060 3061 /* ask L5 driver to add data to the struct */ 3062 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); 3063#endif 3064} 3065 3066/* called due to MCP event (on pmf): 3067 * reread new bandwidth configuration 3068 * configure FW 3069 * notify others function about the change 3070 */ 3071static inline void bnx2x_config_mf_bw(struct bnx2x *bp) 3072{ 3073 if (bp->link_vars.link_up) { 3074 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 3075 bnx2x_link_sync_notify(bp); 3076 } 3077 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3078} 3079 3080static inline void bnx2x_set_mf_bw(struct bnx2x *bp) 3081{ 3082 bnx2x_config_mf_bw(bp); 3083 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 3084} 3085 3086static void bnx2x_handle_drv_info_req(struct bnx2x *bp) 3087{ 3088 enum drv_info_opcode op_code; 3089 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); 3090 3091 /* if drv_info version supported by MFW doesn't match - send NACK */ 3092 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 3093 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3094 return; 3095 } 3096 3097 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 3098 DRV_INFO_CONTROL_OP_CODE_SHIFT; 3099 3100 memset(&bp->slowpath->drv_info_to_mcp, 0, 3101 sizeof(union drv_info_to_mcp)); 3102 3103 switch (op_code) { 3104 case ETH_STATS_OPCODE: 3105 bnx2x_drv_info_ether_stat(bp); 3106 break; 3107 case FCOE_STATS_OPCODE: 3108 bnx2x_drv_info_fcoe_stat(bp); 3109 break; 3110 case ISCSI_STATS_OPCODE: 3111 bnx2x_drv_info_iscsi_stat(bp); 3112 break; 3113 default: 3114 /* if op code isn't supported - send NACK */ 3115 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3116 return; 3117 } 3118 3119 /* if we got drv_info attn from MFW then these fields are defined in 3120 * shmem2 for sure 3121 */ 3122 SHMEM2_WR(bp, drv_info_host_addr_lo, 3123 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3124 SHMEM2_WR(bp, drv_info_host_addr_hi, 3125 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3126 3127 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); 3128} 3129 3130static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) 3131{ 3132 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); 3133 3134 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 3135 3136 /* 3137 * This is the only place besides the function initialization 3138 * where the bp->flags can change so it is done without any 3139 * locks 3140 */ 3141 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 3142 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n"); 3143 bp->flags |= MF_FUNC_DIS; 3144 3145 bnx2x_e1h_disable(bp); 3146 } else { 3147 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); 3148 bp->flags &= ~MF_FUNC_DIS; 3149 3150 bnx2x_e1h_enable(bp); 3151 } 3152 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 3153 } 3154 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 3155 bnx2x_config_mf_bw(bp); 3156 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 3157 } 3158 3159 /* Report results to MCP */ 3160 if (dcc_event) 3161 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); 3162 else 3163 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); 3164} 3165 3166/* must be called under the spq lock */ 3167static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 3168{ 3169 struct eth_spe *next_spe = bp->spq_prod_bd; 3170 3171 if (bp->spq_prod_bd == bp->spq_last_bd) { 3172 bp->spq_prod_bd = bp->spq; 3173 bp->spq_prod_idx = 0; 3174 DP(NETIF_MSG_TIMER, "end of spq\n"); 3175 } else { 3176 bp->spq_prod_bd++; 3177 bp->spq_prod_idx++; 3178 } 3179 return next_spe; 3180} 3181 3182/* must be called under the spq lock */ 3183static inline void bnx2x_sp_prod_update(struct bnx2x *bp) 3184{ 3185 int func = BP_FUNC(bp); 3186 3187 /* 3188 * Make sure that BD data is updated before writing the producer: 3189 * BD data is written to the memory, the producer is read from the 3190 * memory, thus we need a full memory barrier to ensure the ordering. 3191 */ 3192 mb(); 3193 3194 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3195 bp->spq_prod_idx); 3196 mmiowb(); 3197} 3198 3199/** 3200 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3201 * 3202 * @cmd: command to check 3203 * @cmd_type: command type 3204 */ 3205static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3206{ 3207 if ((cmd_type == NONE_CONNECTION_TYPE) || 3208 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3209 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3210 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3211 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3212 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3213 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3214 return true; 3215 else 3216 return false; 3217 3218} 3219 3220 3221/** 3222 * bnx2x_sp_post - place a single command on an SP ring 3223 * 3224 * @bp: driver handle 3225 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3226 * @cid: SW CID the command is related to 3227 * @data_hi: command private data address (high 32 bits) 3228 * @data_lo: command private data address (low 32 bits) 3229 * @cmd_type: command type (e.g. NONE, ETH) 3230 * 3231 * SP data is handled as if it's always an address pair, thus data fields are 3232 * not swapped to little endian in upper functions. Instead this function swaps 3233 * data as if it's two u32 fields. 3234 */ 3235int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3236 u32 data_hi, u32 data_lo, int cmd_type) 3237{ 3238 struct eth_spe *spe; 3239 u16 type; 3240 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3241 3242#ifdef BNX2X_STOP_ON_ERROR 3243 if (unlikely(bp->panic)) 3244 return -EIO; 3245#endif 3246 3247 spin_lock_bh(&bp->spq_lock); 3248 3249 if (common) { 3250 if (!atomic_read(&bp->eq_spq_left)) { 3251 BNX2X_ERR("BUG! EQ ring full!\n"); 3252 spin_unlock_bh(&bp->spq_lock); 3253 bnx2x_panic(); 3254 return -EBUSY; 3255 } 3256 } else if (!atomic_read(&bp->cq_spq_left)) { 3257 BNX2X_ERR("BUG! SPQ ring full!\n"); 3258 spin_unlock_bh(&bp->spq_lock); 3259 bnx2x_panic(); 3260 return -EBUSY; 3261 } 3262 3263 spe = bnx2x_sp_get_next(bp); 3264 3265 /* CID needs port number to be encoded int it */ 3266 spe->hdr.conn_and_cmd_data = 3267 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3268 HW_CID(bp, cid)); 3269 3270 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; 3271 3272 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3273 SPE_HDR_FUNCTION_ID); 3274 3275 spe->hdr.type = cpu_to_le16(type); 3276 3277 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3278 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3279 3280 /* 3281 * It's ok if the actual decrement is issued towards the memory 3282 * somewhere between the spin_lock and spin_unlock. Thus no 3283 * more explict memory barrier is needed. 3284 */ 3285 if (common) 3286 atomic_dec(&bp->eq_spq_left); 3287 else 3288 atomic_dec(&bp->cq_spq_left); 3289 3290 3291 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/, 3292 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) " 3293 "type(0x%x) left (CQ, EQ) (%x,%x)\n", 3294 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3295 (u32)(U64_LO(bp->spq_mapping) + 3296 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3297 HW_CID(bp, cid), data_hi, data_lo, type, 3298 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3299 3300 bnx2x_sp_prod_update(bp); 3301 spin_unlock_bh(&bp->spq_lock); 3302 return 0; 3303} 3304 3305/* acquire split MCP access lock register */ 3306static int bnx2x_acquire_alr(struct bnx2x *bp) 3307{ 3308 u32 j, val; 3309 int rc = 0; 3310 3311 might_sleep(); 3312 for (j = 0; j < 1000; j++) { 3313 val = (1UL << 31); 3314 REG_WR(bp, GRCBASE_MCP + 0x9c, val); 3315 val = REG_RD(bp, GRCBASE_MCP + 0x9c); 3316 if (val & (1L << 31)) 3317 break; 3318 3319 msleep(5); 3320 } 3321 if (!(val & (1L << 31))) { 3322 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3323 rc = -EBUSY; 3324 } 3325 3326 return rc; 3327} 3328 3329/* release split MCP access lock register */ 3330static void bnx2x_release_alr(struct bnx2x *bp) 3331{ 3332 REG_WR(bp, GRCBASE_MCP + 0x9c, 0); 3333} 3334 3335#define BNX2X_DEF_SB_ATT_IDX 0x0001 3336#define BNX2X_DEF_SB_IDX 0x0002 3337 3338static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3339{ 3340 struct host_sp_status_block *def_sb = bp->def_status_blk; 3341 u16 rc = 0; 3342 3343 barrier(); /* status block is written to by the chip */ 3344 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3345 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 3346 rc |= BNX2X_DEF_SB_ATT_IDX; 3347 } 3348 3349 if (bp->def_idx != def_sb->sp_sb.running_index) { 3350 bp->def_idx = def_sb->sp_sb.running_index; 3351 rc |= BNX2X_DEF_SB_IDX; 3352 } 3353 3354 /* Do not reorder: indecies reading should complete before handling */ 3355 barrier(); 3356 return rc; 3357} 3358 3359/* 3360 * slow path service functions 3361 */ 3362 3363static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 3364{ 3365 int port = BP_PORT(bp); 3366 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 3367 MISC_REG_AEU_MASK_ATTN_FUNC_0; 3368 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 3369 NIG_REG_MASK_INTERRUPT_PORT0; 3370 u32 aeu_mask; 3371 u32 nig_mask = 0; 3372 u32 reg_addr; 3373 3374 if (bp->attn_state & asserted) 3375 BNX2X_ERR("IGU ERROR\n"); 3376 3377 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3378 aeu_mask = REG_RD(bp, aeu_addr); 3379 3380 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 3381 aeu_mask, asserted); 3382 aeu_mask &= ~(asserted & 0x3ff); 3383 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 3384 3385 REG_WR(bp, aeu_addr, aeu_mask); 3386 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3387 3388 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 3389 bp->attn_state |= asserted; 3390 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 3391 3392 if (asserted & ATTN_HARD_WIRED_MASK) { 3393 if (asserted & ATTN_NIG_FOR_FUNC) { 3394 3395 bnx2x_acquire_phy_lock(bp); 3396 3397 /* save nig interrupt mask */ 3398 nig_mask = REG_RD(bp, nig_int_mask_addr); 3399 3400 /* If nig_mask is not set, no need to call the update 3401 * function. 3402 */ 3403 if (nig_mask) { 3404 REG_WR(bp, nig_int_mask_addr, 0); 3405 3406 bnx2x_link_attn(bp); 3407 } 3408 3409 /* handle unicore attn? */ 3410 } 3411 if (asserted & ATTN_SW_TIMER_4_FUNC) 3412 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 3413 3414 if (asserted & GPIO_2_FUNC) 3415 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 3416 3417 if (asserted & GPIO_3_FUNC) 3418 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 3419 3420 if (asserted & GPIO_4_FUNC) 3421 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 3422 3423 if (port == 0) { 3424 if (asserted & ATTN_GENERAL_ATTN_1) { 3425 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 3426 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 3427 } 3428 if (asserted & ATTN_GENERAL_ATTN_2) { 3429 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 3430 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 3431 } 3432 if (asserted & ATTN_GENERAL_ATTN_3) { 3433 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 3434 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 3435 } 3436 } else { 3437 if (asserted & ATTN_GENERAL_ATTN_4) { 3438 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 3439 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 3440 } 3441 if (asserted & ATTN_GENERAL_ATTN_5) { 3442 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 3443 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 3444 } 3445 if (asserted & ATTN_GENERAL_ATTN_6) { 3446 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 3447 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 3448 } 3449 } 3450 3451 } /* if hardwired */ 3452 3453 if (bp->common.int_block == INT_BLOCK_HC) 3454 reg_addr = (HC_REG_COMMAND_REG + port*32 + 3455 COMMAND_REG_ATTN_BITS_SET); 3456 else 3457 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 3458 3459 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 3460 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 3461 REG_WR(bp, reg_addr, asserted); 3462 3463 /* now set back the mask */ 3464 if (asserted & ATTN_NIG_FOR_FUNC) { 3465 REG_WR(bp, nig_int_mask_addr, nig_mask); 3466 bnx2x_release_phy_lock(bp); 3467 } 3468} 3469 3470static inline void bnx2x_fan_failure(struct bnx2x *bp) 3471{ 3472 int port = BP_PORT(bp); 3473 u32 ext_phy_config; 3474 /* mark the failure */ 3475 ext_phy_config = 3476 SHMEM_RD(bp, 3477 dev_info.port_hw_config[port].external_phy_config); 3478 3479 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 3480 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 3481 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 3482 ext_phy_config); 3483 3484 /* log the failure */ 3485 netdev_err(bp->dev, "Fan Failure on Network Controller has caused" 3486 " the driver to shutdown the card to prevent permanent" 3487 " damage. Please contact OEM Support for assistance\n"); 3488 3489 /* 3490 * Scheudle device reset (unload) 3491 * This is due to some boards consuming sufficient power when driver is 3492 * up to overheat if fan fails. 3493 */ 3494 smp_mb__before_clear_bit(); 3495 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); 3496 smp_mb__after_clear_bit(); 3497 schedule_delayed_work(&bp->sp_rtnl_task, 0); 3498 3499} 3500 3501static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 3502{ 3503 int port = BP_PORT(bp); 3504 int reg_offset; 3505 u32 val; 3506 3507 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 3508 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 3509 3510 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 3511 3512 val = REG_RD(bp, reg_offset); 3513 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 3514 REG_WR(bp, reg_offset, val); 3515 3516 BNX2X_ERR("SPIO5 hw attention\n"); 3517 3518 /* Fan failure attention */ 3519 bnx2x_hw_reset_phy(&bp->link_params); 3520 bnx2x_fan_failure(bp); 3521 } 3522 3523 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 3524 bnx2x_acquire_phy_lock(bp); 3525 bnx2x_handle_module_detect_int(&bp->link_params); 3526 bnx2x_release_phy_lock(bp); 3527 } 3528 3529 if (attn & HW_INTERRUT_ASSERT_SET_0) { 3530 3531 val = REG_RD(bp, reg_offset); 3532 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 3533 REG_WR(bp, reg_offset, val); 3534 3535 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 3536 (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); 3537 bnx2x_panic(); 3538 } 3539} 3540 3541static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 3542{ 3543 u32 val; 3544 3545 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 3546 3547 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 3548 BNX2X_ERR("DB hw attention 0x%x\n", val); 3549 /* DORQ discard attention */ 3550 if (val & 0x2) 3551 BNX2X_ERR("FATAL error from DORQ\n"); 3552 } 3553 3554 if (attn & HW_INTERRUT_ASSERT_SET_1) { 3555 3556 int port = BP_PORT(bp); 3557 int reg_offset; 3558 3559 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 3560 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 3561 3562 val = REG_RD(bp, reg_offset); 3563 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 3564 REG_WR(bp, reg_offset, val); 3565 3566 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 3567 (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); 3568 bnx2x_panic(); 3569 } 3570} 3571 3572static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 3573{ 3574 u32 val; 3575 3576 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 3577 3578 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 3579 BNX2X_ERR("CFC hw attention 0x%x\n", val); 3580 /* CFC error attention */ 3581 if (val & 0x2) 3582 BNX2X_ERR("FATAL error from CFC\n"); 3583 } 3584 3585 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 3586 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 3587 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 3588 /* RQ_USDMDP_FIFO_OVERFLOW */ 3589 if (val & 0x18000) 3590 BNX2X_ERR("FATAL error from PXP\n"); 3591 3592 if (!CHIP_IS_E1x(bp)) { 3593 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 3594 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 3595 } 3596 } 3597 3598 if (attn & HW_INTERRUT_ASSERT_SET_2) { 3599 3600 int port = BP_PORT(bp); 3601 int reg_offset; 3602 3603 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 3604 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 3605 3606 val = REG_RD(bp, reg_offset); 3607 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 3608 REG_WR(bp, reg_offset, val); 3609 3610 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 3611 (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); 3612 bnx2x_panic(); 3613 } 3614} 3615 3616static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 3617{ 3618 u32 val; 3619 3620 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 3621 3622 if (attn & BNX2X_PMF_LINK_ASSERT) { 3623 int func = BP_FUNC(bp); 3624 3625 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 3626 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 3627 func_mf_config[BP_ABS_FUNC(bp)].config); 3628 val = SHMEM_RD(bp, 3629 func_mb[BP_FW_MB_IDX(bp)].drv_status); 3630 if (val & DRV_STATUS_DCC_EVENT_MASK) 3631 bnx2x_dcc_event(bp, 3632 (val & DRV_STATUS_DCC_EVENT_MASK)); 3633 3634 if (val & DRV_STATUS_SET_MF_BW) 3635 bnx2x_set_mf_bw(bp); 3636 3637 if (val & DRV_STATUS_DRV_INFO_REQ) 3638 bnx2x_handle_drv_info_req(bp); 3639 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 3640 bnx2x_pmf_update(bp); 3641 3642 if (bp->port.pmf && 3643 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 3644 bp->dcbx_enabled > 0) 3645 /* start dcbx state machine */ 3646 bnx2x_dcbx_set_params(bp, 3647 BNX2X_DCBX_STATE_NEG_RECEIVED); 3648 if (bp->link_vars.periodic_flags & 3649 PERIODIC_FLAGS_LINK_EVENT) { 3650 /* sync with link */ 3651 bnx2x_acquire_phy_lock(bp); 3652 bp->link_vars.periodic_flags &= 3653 ~PERIODIC_FLAGS_LINK_EVENT; 3654 bnx2x_release_phy_lock(bp); 3655 if (IS_MF(bp)) 3656 bnx2x_link_sync_notify(bp); 3657 bnx2x_link_report(bp); 3658 } 3659 /* Always call it here: bnx2x_link_report() will 3660 * prevent the link indication duplication. 3661 */ 3662 bnx2x__link_status_update(bp); 3663 } else if (attn & BNX2X_MC_ASSERT_BITS) { 3664 3665 BNX2X_ERR("MC assert!\n"); 3666 bnx2x_mc_assert(bp); 3667 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 3668 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 3669 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 3670 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 3671 bnx2x_panic(); 3672 3673 } else if (attn & BNX2X_MCP_ASSERT) { 3674 3675 BNX2X_ERR("MCP assert!\n"); 3676 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 3677 bnx2x_fw_dump(bp); 3678 3679 } else 3680 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 3681 } 3682 3683 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 3684 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 3685 if (attn & BNX2X_GRC_TIMEOUT) { 3686 val = CHIP_IS_E1(bp) ? 0 : 3687 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 3688 BNX2X_ERR("GRC time-out 0x%08x\n", val); 3689 } 3690 if (attn & BNX2X_GRC_RSV) { 3691 val = CHIP_IS_E1(bp) ? 0 : 3692 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 3693 BNX2X_ERR("GRC reserved 0x%08x\n", val); 3694 } 3695 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 3696 } 3697} 3698 3699/* 3700 * Bits map: 3701 * 0-7 - Engine0 load counter. 3702 * 8-15 - Engine1 load counter. 3703 * 16 - Engine0 RESET_IN_PROGRESS bit. 3704 * 17 - Engine1 RESET_IN_PROGRESS bit. 3705 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 3706 * on the engine 3707 * 19 - Engine1 ONE_IS_LOADED. 3708 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 3709 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 3710 * just the one belonging to its engine). 3711 * 3712 */ 3713#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 3714 3715#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 3716#define BNX2X_PATH0_LOAD_CNT_SHIFT 0 3717#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 3718#define BNX2X_PATH1_LOAD_CNT_SHIFT 8 3719#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 3720#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 3721#define BNX2X_GLOBAL_RESET_BIT 0x00040000 3722 3723/* 3724 * Set the GLOBAL_RESET bit. 3725 * 3726 * Should be run under rtnl lock 3727 */ 3728void bnx2x_set_reset_global(struct bnx2x *bp) 3729{ 3730 u32 val; 3731 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3732 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3733 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 3734 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3735} 3736 3737/* 3738 * Clear the GLOBAL_RESET bit. 3739 * 3740 * Should be run under rtnl lock 3741 */ 3742static inline void bnx2x_clear_reset_global(struct bnx2x *bp) 3743{ 3744 u32 val; 3745 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3746 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3747 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 3748 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3749} 3750 3751/* 3752 * Checks the GLOBAL_RESET bit. 3753 * 3754 * should be run under rtnl lock 3755 */ 3756static inline bool bnx2x_reset_is_global(struct bnx2x *bp) 3757{ 3758 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3759 3760 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 3761 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 3762} 3763 3764/* 3765 * Clear RESET_IN_PROGRESS bit for the current engine. 3766 * 3767 * Should be run under rtnl lock 3768 */ 3769static inline void bnx2x_set_reset_done(struct bnx2x *bp) 3770{ 3771 u32 val; 3772 u32 bit = BP_PATH(bp) ? 3773 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3774 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3775 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3776 3777 /* Clear the bit */ 3778 val &= ~bit; 3779 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3780 3781 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3782} 3783 3784/* 3785 * Set RESET_IN_PROGRESS for the current engine. 3786 * 3787 * should be run under rtnl lock 3788 */ 3789void bnx2x_set_reset_in_progress(struct bnx2x *bp) 3790{ 3791 u32 val; 3792 u32 bit = BP_PATH(bp) ? 3793 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3794 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3795 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3796 3797 /* Set the bit */ 3798 val |= bit; 3799 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3800 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3801} 3802 3803/* 3804 * Checks the RESET_IN_PROGRESS bit for the given engine. 3805 * should be run under rtnl lock 3806 */ 3807bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 3808{ 3809 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3810 u32 bit = engine ? 3811 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3812 3813 /* return false if bit is set */ 3814 return (val & bit) ? false : true; 3815} 3816 3817/* 3818 * set pf load for the current pf. 3819 * 3820 * should be run under rtnl lock 3821 */ 3822void bnx2x_set_pf_load(struct bnx2x *bp) 3823{ 3824 u32 val1, val; 3825 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3826 BNX2X_PATH0_LOAD_CNT_MASK; 3827 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3828 BNX2X_PATH0_LOAD_CNT_SHIFT; 3829 3830 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3831 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3832 3833 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3834 3835 /* get the current counter value */ 3836 val1 = (val & mask) >> shift; 3837 3838 /* set bit of that PF */ 3839 val1 |= (1 << bp->pf_num); 3840 3841 /* clear the old value */ 3842 val &= ~mask; 3843 3844 /* set the new one */ 3845 val |= ((val1 << shift) & mask); 3846 3847 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3848 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3849} 3850 3851/** 3852 * bnx2x_clear_pf_load - clear pf load mark 3853 * 3854 * @bp: driver handle 3855 * 3856 * Should be run under rtnl lock. 3857 * Decrements the load counter for the current engine. Returns 3858 * whether other functions are still loaded 3859 */ 3860bool bnx2x_clear_pf_load(struct bnx2x *bp) 3861{ 3862 u32 val1, val; 3863 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3864 BNX2X_PATH0_LOAD_CNT_MASK; 3865 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3866 BNX2X_PATH0_LOAD_CNT_SHIFT; 3867 3868 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3869 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3870 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3871 3872 /* get the current counter value */ 3873 val1 = (val & mask) >> shift; 3874 3875 /* clear bit of that PF */ 3876 val1 &= ~(1 << bp->pf_num); 3877 3878 /* clear the old value */ 3879 val &= ~mask; 3880 3881 /* set the new one */ 3882 val |= ((val1 << shift) & mask); 3883 3884 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3885 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3886 return val1 != 0; 3887} 3888 3889/* 3890 * Read the load status for the current engine. 3891 * 3892 * should be run under rtnl lock 3893 */ 3894static inline bool bnx2x_get_load_status(struct bnx2x *bp, int engine) 3895{ 3896 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 3897 BNX2X_PATH0_LOAD_CNT_MASK); 3898 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3899 BNX2X_PATH0_LOAD_CNT_SHIFT); 3900 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3901 3902 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val); 3903 3904 val = (val & mask) >> shift; 3905 3906 DP(NETIF_MSG_HW, "load mask for engine %d = 0x%x\n", engine, val); 3907 3908 return val != 0; 3909} 3910 3911/* 3912 * Reset the load status for the current engine. 3913 */ 3914static inline void bnx2x_clear_load_status(struct bnx2x *bp) 3915{ 3916 u32 val; 3917 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3918 BNX2X_PATH0_LOAD_CNT_MASK); 3919 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3920 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3921 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); 3922 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3923} 3924 3925static inline void _print_next_block(int idx, const char *blk) 3926{ 3927 pr_cont("%s%s", idx ? ", " : "", blk); 3928} 3929 3930static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, 3931 bool print) 3932{ 3933 int i = 0; 3934 u32 cur_bit = 0; 3935 for (i = 0; sig; i++) { 3936 cur_bit = ((u32)0x1 << i); 3937 if (sig & cur_bit) { 3938 switch (cur_bit) { 3939 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 3940 if (print) 3941 _print_next_block(par_num++, "BRB"); 3942 break; 3943 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 3944 if (print) 3945 _print_next_block(par_num++, "PARSER"); 3946 break; 3947 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 3948 if (print) 3949 _print_next_block(par_num++, "TSDM"); 3950 break; 3951 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 3952 if (print) 3953 _print_next_block(par_num++, 3954 "SEARCHER"); 3955 break; 3956 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 3957 if (print) 3958 _print_next_block(par_num++, "TCM"); 3959 break; 3960 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 3961 if (print) 3962 _print_next_block(par_num++, "TSEMI"); 3963 break; 3964 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 3965 if (print) 3966 _print_next_block(par_num++, "XPB"); 3967 break; 3968 } 3969 3970 /* Clear the bit */ 3971 sig &= ~cur_bit; 3972 } 3973 } 3974 3975 return par_num; 3976} 3977 3978static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, 3979 bool *global, bool print) 3980{ 3981 int i = 0; 3982 u32 cur_bit = 0; 3983 for (i = 0; sig; i++) { 3984 cur_bit = ((u32)0x1 << i); 3985 if (sig & cur_bit) { 3986 switch (cur_bit) { 3987 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 3988 if (print) 3989 _print_next_block(par_num++, "PBF"); 3990 break; 3991 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 3992 if (print) 3993 _print_next_block(par_num++, "QM"); 3994 break; 3995 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 3996 if (print) 3997 _print_next_block(par_num++, "TM"); 3998 break; 3999 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 4000 if (print) 4001 _print_next_block(par_num++, "XSDM"); 4002 break; 4003 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 4004 if (print) 4005 _print_next_block(par_num++, "XCM"); 4006 break; 4007 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 4008 if (print) 4009 _print_next_block(par_num++, "XSEMI"); 4010 break; 4011 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 4012 if (print) 4013 _print_next_block(par_num++, 4014 "DOORBELLQ"); 4015 break; 4016 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 4017 if (print) 4018 _print_next_block(par_num++, "NIG"); 4019 break; 4020 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 4021 if (print) 4022 _print_next_block(par_num++, 4023 "VAUX PCI CORE"); 4024 *global = true; 4025 break; 4026 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 4027 if (print) 4028 _print_next_block(par_num++, "DEBUG"); 4029 break; 4030 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 4031 if (print) 4032 _print_next_block(par_num++, "USDM"); 4033 break; 4034 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 4035 if (print) 4036 _print_next_block(par_num++, "UCM"); 4037 break; 4038 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 4039 if (print) 4040 _print_next_block(par_num++, "USEMI"); 4041 break; 4042 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 4043 if (print) 4044 _print_next_block(par_num++, "UPB"); 4045 break; 4046 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 4047 if (print) 4048 _print_next_block(par_num++, "CSDM"); 4049 break; 4050 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 4051 if (print) 4052 _print_next_block(par_num++, "CCM"); 4053 break; 4054 } 4055 4056 /* Clear the bit */ 4057 sig &= ~cur_bit; 4058 } 4059 } 4060 4061 return par_num; 4062} 4063 4064static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, 4065 bool print) 4066{ 4067 int i = 0; 4068 u32 cur_bit = 0; 4069 for (i = 0; sig; i++) { 4070 cur_bit = ((u32)0x1 << i); 4071 if (sig & cur_bit) { 4072 switch (cur_bit) { 4073 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 4074 if (print) 4075 _print_next_block(par_num++, "CSEMI"); 4076 break; 4077 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 4078 if (print) 4079 _print_next_block(par_num++, "PXP"); 4080 break; 4081 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 4082 if (print) 4083 _print_next_block(par_num++, 4084 "PXPPCICLOCKCLIENT"); 4085 break; 4086 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 4087 if (print) 4088 _print_next_block(par_num++, "CFC"); 4089 break; 4090 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 4091 if (print) 4092 _print_next_block(par_num++, "CDU"); 4093 break; 4094 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 4095 if (print) 4096 _print_next_block(par_num++, "DMAE"); 4097 break; 4098 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 4099 if (print) 4100 _print_next_block(par_num++, "IGU"); 4101 break; 4102 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 4103 if (print) 4104 _print_next_block(par_num++, "MISC"); 4105 break; 4106 } 4107 4108 /* Clear the bit */ 4109 sig &= ~cur_bit; 4110 } 4111 } 4112 4113 return par_num; 4114} 4115 4116static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, 4117 bool *global, bool print) 4118{ 4119 int i = 0; 4120 u32 cur_bit = 0; 4121 for (i = 0; sig; i++) { 4122 cur_bit = ((u32)0x1 << i); 4123 if (sig & cur_bit) { 4124 switch (cur_bit) { 4125 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 4126 if (print) 4127 _print_next_block(par_num++, "MCP ROM"); 4128 *global = true; 4129 break; 4130 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 4131 if (print) 4132 _print_next_block(par_num++, 4133 "MCP UMP RX"); 4134 *global = true; 4135 break; 4136 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 4137 if (print) 4138 _print_next_block(par_num++, 4139 "MCP UMP TX"); 4140 *global = true; 4141 break; 4142 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 4143 if (print) 4144 _print_next_block(par_num++, 4145 "MCP SCPAD"); 4146 *global = true; 4147 break; 4148 } 4149 4150 /* Clear the bit */ 4151 sig &= ~cur_bit; 4152 } 4153 } 4154 4155 return par_num; 4156} 4157 4158static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, 4159 bool print) 4160{ 4161 int i = 0; 4162 u32 cur_bit = 0; 4163 for (i = 0; sig; i++) { 4164 cur_bit = ((u32)0x1 << i); 4165 if (sig & cur_bit) { 4166 switch (cur_bit) { 4167 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 4168 if (print) 4169 _print_next_block(par_num++, "PGLUE_B"); 4170 break; 4171 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 4172 if (print) 4173 _print_next_block(par_num++, "ATC"); 4174 break; 4175 } 4176 4177 /* Clear the bit */ 4178 sig &= ~cur_bit; 4179 } 4180 } 4181 4182 return par_num; 4183} 4184 4185static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4186 u32 *sig) 4187{ 4188 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4189 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4190 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4191 (sig[3] & HW_PRTY_ASSERT_SET_3) || 4192 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4193 int par_num = 0; 4194 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: " 4195 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x " 4196 "[4]:0x%08x\n", 4197 sig[0] & HW_PRTY_ASSERT_SET_0, 4198 sig[1] & HW_PRTY_ASSERT_SET_1, 4199 sig[2] & HW_PRTY_ASSERT_SET_2, 4200 sig[3] & HW_PRTY_ASSERT_SET_3, 4201 sig[4] & HW_PRTY_ASSERT_SET_4); 4202 if (print) 4203 netdev_err(bp->dev, 4204 "Parity errors detected in blocks: "); 4205 par_num = bnx2x_check_blocks_with_parity0( 4206 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); 4207 par_num = bnx2x_check_blocks_with_parity1( 4208 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); 4209 par_num = bnx2x_check_blocks_with_parity2( 4210 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); 4211 par_num = bnx2x_check_blocks_with_parity3( 4212 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); 4213 par_num = bnx2x_check_blocks_with_parity4( 4214 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); 4215 4216 if (print) 4217 pr_cont("\n"); 4218 4219 return true; 4220 } else 4221 return false; 4222} 4223 4224/** 4225 * bnx2x_chk_parity_attn - checks for parity attentions. 4226 * 4227 * @bp: driver handle 4228 * @global: true if there was a global attention 4229 * @print: show parity attention in syslog 4230 */ 4231bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 4232{ 4233 struct attn_route attn = { {0} }; 4234 int port = BP_PORT(bp); 4235 4236 attn.sig[0] = REG_RD(bp, 4237 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 4238 port*4); 4239 attn.sig[1] = REG_RD(bp, 4240 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 4241 port*4); 4242 attn.sig[2] = REG_RD(bp, 4243 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 4244 port*4); 4245 attn.sig[3] = REG_RD(bp, 4246 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 4247 port*4); 4248 4249 if (!CHIP_IS_E1x(bp)) 4250 attn.sig[4] = REG_RD(bp, 4251 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 4252 port*4); 4253 4254 return bnx2x_parity_attn(bp, global, print, attn.sig); 4255} 4256 4257 4258static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 4259{ 4260 u32 val; 4261 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 4262 4263 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 4264 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 4265 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 4266 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4267 "ADDRESS_ERROR\n"); 4268 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 4269 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4270 "INCORRECT_RCV_BEHAVIOR\n"); 4271 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 4272 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4273 "WAS_ERROR_ATTN\n"); 4274 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 4275 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4276 "VF_LENGTH_VIOLATION_ATTN\n"); 4277 if (val & 4278 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 4279 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4280 "VF_GRC_SPACE_VIOLATION_ATTN\n"); 4281 if (val & 4282 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 4283 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4284 "VF_MSIX_BAR_VIOLATION_ATTN\n"); 4285 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 4286 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4287 "TCPL_ERROR_ATTN\n"); 4288 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 4289 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4290 "TCPL_IN_TWO_RCBS_ATTN\n"); 4291 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 4292 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4293 "CSSNOOP_FIFO_OVERFLOW\n"); 4294 } 4295 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 4296 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 4297 BNX2X_ERR("ATC hw attention 0x%x\n", val); 4298 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 4299 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 4300 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 4301 BNX2X_ERR("ATC_ATC_INT_STS_REG" 4302 "_ATC_TCPL_TO_NOT_PEND\n"); 4303 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 4304 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4305 "ATC_GPA_MULTIPLE_HITS\n"); 4306 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 4307 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4308 "ATC_RCPL_TO_EMPTY_CNT\n"); 4309 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 4310 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 4311 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 4312 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4313 "ATC_IREQ_LESS_THAN_STU\n"); 4314 } 4315 4316 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4317 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 4318 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 4319 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4320 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 4321 } 4322 4323} 4324 4325static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 4326{ 4327 struct attn_route attn, *group_mask; 4328 int port = BP_PORT(bp); 4329 int index; 4330 u32 reg_addr; 4331 u32 val; 4332 u32 aeu_mask; 4333 bool global = false; 4334 4335 /* need to take HW lock because MCP or other port might also 4336 try to handle this event */ 4337 bnx2x_acquire_alr(bp); 4338 4339 if (bnx2x_chk_parity_attn(bp, &global, true)) { 4340#ifndef BNX2X_STOP_ON_ERROR 4341 bp->recovery_state = BNX2X_RECOVERY_INIT; 4342 schedule_delayed_work(&bp->sp_rtnl_task, 0); 4343 /* Disable HW interrupts */ 4344 bnx2x_int_disable(bp); 4345 /* In case of parity errors don't handle attentions so that 4346 * other function would "see" parity errors. 4347 */ 4348#else 4349 bnx2x_panic(); 4350#endif 4351 bnx2x_release_alr(bp); 4352 return; 4353 } 4354 4355 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 4356 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 4357 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 4358 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 4359 if (!CHIP_IS_E1x(bp)) 4360 attn.sig[4] = 4361 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 4362 else 4363 attn.sig[4] = 0; 4364 4365 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 4366 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 4367 4368 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4369 if (deasserted & (1 << index)) { 4370 group_mask = &bp->attn_group[index]; 4371 4372 DP(NETIF_MSG_HW, "group[%d]: %08x %08x " 4373 "%08x %08x %08x\n", 4374 index, 4375 group_mask->sig[0], group_mask->sig[1], 4376 group_mask->sig[2], group_mask->sig[3], 4377 group_mask->sig[4]); 4378 4379 bnx2x_attn_int_deasserted4(bp, 4380 attn.sig[4] & group_mask->sig[4]); 4381 bnx2x_attn_int_deasserted3(bp, 4382 attn.sig[3] & group_mask->sig[3]); 4383 bnx2x_attn_int_deasserted1(bp, 4384 attn.sig[1] & group_mask->sig[1]); 4385 bnx2x_attn_int_deasserted2(bp, 4386 attn.sig[2] & group_mask->sig[2]); 4387 bnx2x_attn_int_deasserted0(bp, 4388 attn.sig[0] & group_mask->sig[0]); 4389 } 4390 } 4391 4392 bnx2x_release_alr(bp); 4393 4394 if (bp->common.int_block == INT_BLOCK_HC) 4395 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4396 COMMAND_REG_ATTN_BITS_CLR); 4397 else 4398 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 4399 4400 val = ~deasserted; 4401 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 4402 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4403 REG_WR(bp, reg_addr, val); 4404 4405 if (~bp->attn_state & deasserted) 4406 BNX2X_ERR("IGU ERROR\n"); 4407 4408 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4409 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4410 4411 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4412 aeu_mask = REG_RD(bp, reg_addr); 4413 4414 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 4415 aeu_mask, deasserted); 4416 aeu_mask |= (deasserted & 0x3ff); 4417 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4418 4419 REG_WR(bp, reg_addr, aeu_mask); 4420 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4421 4422 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4423 bp->attn_state &= ~deasserted; 4424 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4425} 4426 4427static void bnx2x_attn_int(struct bnx2x *bp) 4428{ 4429 /* read local copy of bits */ 4430 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 4431 attn_bits); 4432 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 4433 attn_bits_ack); 4434 u32 attn_state = bp->attn_state; 4435 4436 /* look for changed bits */ 4437 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 4438 u32 deasserted = ~attn_bits & attn_ack & attn_state; 4439 4440 DP(NETIF_MSG_HW, 4441 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 4442 attn_bits, attn_ack, asserted, deasserted); 4443 4444 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 4445 BNX2X_ERR("BAD attention state\n"); 4446 4447 /* handle bits that were raised */ 4448 if (asserted) 4449 bnx2x_attn_int_asserted(bp, asserted); 4450 4451 if (deasserted) 4452 bnx2x_attn_int_deasserted(bp, deasserted); 4453} 4454 4455void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 4456 u16 index, u8 op, u8 update) 4457{ 4458 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 4459 4460 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 4461 igu_addr); 4462} 4463 4464static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 4465{ 4466 /* No memory barriers */ 4467 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 4468 mmiowb(); /* keep prod updates ordered */ 4469} 4470 4471#ifdef BCM_CNIC 4472static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 4473 union event_ring_elem *elem) 4474{ 4475 u8 err = elem->message.error; 4476 4477 if (!bp->cnic_eth_dev.starting_cid || 4478 (cid < bp->cnic_eth_dev.starting_cid && 4479 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 4480 return 1; 4481 4482 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 4483 4484 if (unlikely(err)) { 4485 4486 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 4487 cid); 4488 bnx2x_panic_dump(bp); 4489 } 4490 bnx2x_cnic_cfc_comp(bp, cid, err); 4491 return 0; 4492} 4493#endif 4494 4495static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 4496{ 4497 struct bnx2x_mcast_ramrod_params rparam; 4498 int rc; 4499 4500 memset(&rparam, 0, sizeof(rparam)); 4501 4502 rparam.mcast_obj = &bp->mcast_obj; 4503 4504 netif_addr_lock_bh(bp->dev); 4505 4506 /* Clear pending state for the last command */ 4507 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 4508 4509 /* If there are pending mcast commands - send them */ 4510 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 4511 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 4512 if (rc < 0) 4513 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 4514 rc); 4515 } 4516 4517 netif_addr_unlock_bh(bp->dev); 4518} 4519 4520static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp, 4521 union event_ring_elem *elem) 4522{ 4523 unsigned long ramrod_flags = 0; 4524 int rc = 0; 4525 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; 4526 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 4527 4528 /* Always push next commands out, don't wait here */ 4529 __set_bit(RAMROD_CONT, &ramrod_flags); 4530 4531 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 4532 case BNX2X_FILTER_MAC_PENDING: 4533#ifdef BCM_CNIC 4534 if (cid == BNX2X_ISCSI_ETH_CID) 4535 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 4536 else 4537#endif 4538 vlan_mac_obj = &bp->fp[cid].mac_obj; 4539 4540 break; 4541 case BNX2X_FILTER_MCAST_PENDING: 4542 /* This is only relevant for 57710 where multicast MACs are 4543 * configured as unicast MACs using the same ramrod. 4544 */ 4545 bnx2x_handle_mcast_eqe(bp); 4546 return; 4547 default: 4548 BNX2X_ERR("Unsupported classification command: %d\n", 4549 elem->message.data.eth_event.echo); 4550 return; 4551 } 4552 4553 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 4554 4555 if (rc < 0) 4556 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 4557 else if (rc > 0) 4558 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 4559 4560} 4561 4562#ifdef BCM_CNIC 4563static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 4564#endif 4565 4566static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 4567{ 4568 netif_addr_lock_bh(bp->dev); 4569 4570 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 4571 4572 /* Send rx_mode command again if was requested */ 4573 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 4574 bnx2x_set_storm_rx_mode(bp); 4575#ifdef BCM_CNIC 4576 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 4577 &bp->sp_state)) 4578 bnx2x_set_iscsi_eth_rx_mode(bp, true); 4579 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 4580 &bp->sp_state)) 4581 bnx2x_set_iscsi_eth_rx_mode(bp, false); 4582#endif 4583 4584 netif_addr_unlock_bh(bp->dev); 4585} 4586 4587static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 4588 struct bnx2x *bp, u32 cid) 4589{ 4590 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 4591#ifdef BCM_CNIC 4592 if (cid == BNX2X_FCOE_ETH_CID) 4593 return &bnx2x_fcoe(bp, q_obj); 4594 else 4595#endif 4596 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj); 4597} 4598 4599static void bnx2x_eq_int(struct bnx2x *bp) 4600{ 4601 u16 hw_cons, sw_cons, sw_prod; 4602 union event_ring_elem *elem; 4603 u32 cid; 4604 u8 opcode; 4605 int spqe_cnt = 0; 4606 struct bnx2x_queue_sp_obj *q_obj; 4607 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 4608 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 4609 4610 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 4611 4612 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 4613 * when we get the the next-page we nned to adjust so the loop 4614 * condition below will be met. The next element is the size of a 4615 * regular element and hence incrementing by 1 4616 */ 4617 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 4618 hw_cons++; 4619 4620 /* This function may never run in parallel with itself for a 4621 * specific bp, thus there is no need in "paired" read memory 4622 * barrier here. 4623 */ 4624 sw_cons = bp->eq_cons; 4625 sw_prod = bp->eq_prod; 4626 4627 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 4628 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 4629 4630 for (; sw_cons != hw_cons; 4631 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 4632 4633 4634 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 4635 4636 cid = SW_CID(elem->message.data.cfc_del_event.cid); 4637 opcode = elem->message.opcode; 4638 4639 4640 /* handle eq element */ 4641 switch (opcode) { 4642 case EVENT_RING_OPCODE_STAT_QUERY: 4643 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n", 4644 bp->stats_comp++); 4645 /* nothing to do with stats comp */ 4646 goto next_spqe; 4647 4648 case EVENT_RING_OPCODE_CFC_DEL: 4649 /* handle according to cid range */ 4650 /* 4651 * we may want to verify here that the bp state is 4652 * HALTING 4653 */ 4654 DP(BNX2X_MSG_SP, 4655 "got delete ramrod for MULTI[%d]\n", cid); 4656#ifdef BCM_CNIC 4657 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 4658 goto next_spqe; 4659#endif 4660 q_obj = bnx2x_cid_to_q_obj(bp, cid); 4661 4662 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 4663 break; 4664 4665 4666 4667 goto next_spqe; 4668 4669 case EVENT_RING_OPCODE_STOP_TRAFFIC: 4670 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n"); 4671 if (f_obj->complete_cmd(bp, f_obj, 4672 BNX2X_F_CMD_TX_STOP)) 4673 break; 4674 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 4675 goto next_spqe; 4676 4677 case EVENT_RING_OPCODE_START_TRAFFIC: 4678 DP(BNX2X_MSG_SP, "got START TRAFFIC\n"); 4679 if (f_obj->complete_cmd(bp, f_obj, 4680 BNX2X_F_CMD_TX_START)) 4681 break; 4682 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 4683 goto next_spqe; 4684 case EVENT_RING_OPCODE_FUNCTION_START: 4685 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n"); 4686 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 4687 break; 4688 4689 goto next_spqe; 4690 4691 case EVENT_RING_OPCODE_FUNCTION_STOP: 4692 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n"); 4693 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 4694 break; 4695 4696 goto next_spqe; 4697 } 4698 4699 switch (opcode | bp->state) { 4700 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4701 BNX2X_STATE_OPEN): 4702 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4703 BNX2X_STATE_OPENING_WAIT4_PORT): 4704 cid = elem->message.data.eth_event.echo & 4705 BNX2X_SWCID_MASK; 4706 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 4707 cid); 4708 rss_raw->clear_pending(rss_raw); 4709 break; 4710 4711 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 4712 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 4713 case (EVENT_RING_OPCODE_SET_MAC | 4714 BNX2X_STATE_CLOSING_WAIT4_HALT): 4715 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4716 BNX2X_STATE_OPEN): 4717 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4718 BNX2X_STATE_DIAG): 4719 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4720 BNX2X_STATE_CLOSING_WAIT4_HALT): 4721 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); 4722 bnx2x_handle_classification_eqe(bp, elem); 4723 break; 4724 4725 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4726 BNX2X_STATE_OPEN): 4727 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4728 BNX2X_STATE_DIAG): 4729 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4730 BNX2X_STATE_CLOSING_WAIT4_HALT): 4731 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 4732 bnx2x_handle_mcast_eqe(bp); 4733 break; 4734 4735 case (EVENT_RING_OPCODE_FILTERS_RULES | 4736 BNX2X_STATE_OPEN): 4737 case (EVENT_RING_OPCODE_FILTERS_RULES | 4738 BNX2X_STATE_DIAG): 4739 case (EVENT_RING_OPCODE_FILTERS_RULES | 4740 BNX2X_STATE_CLOSING_WAIT4_HALT): 4741 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 4742 bnx2x_handle_rx_mode_eqe(bp); 4743 break; 4744 default: 4745 /* unknown event log error and continue */ 4746 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 4747 elem->message.opcode, bp->state); 4748 } 4749next_spqe: 4750 spqe_cnt++; 4751 } /* for */ 4752 4753 smp_mb__before_atomic_inc(); 4754 atomic_add(spqe_cnt, &bp->eq_spq_left); 4755 4756 bp->eq_cons = sw_cons; 4757 bp->eq_prod = sw_prod; 4758 /* Make sure that above mem writes were issued towards the memory */ 4759 smp_wmb(); 4760 4761 /* update producer */ 4762 bnx2x_update_eq_prod(bp, bp->eq_prod); 4763} 4764 4765static void bnx2x_sp_task(struct work_struct *work) 4766{ 4767 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 4768 u16 status; 4769 4770 status = bnx2x_update_dsb_idx(bp); 4771/* if (status == 0) */ 4772/* BNX2X_ERR("spurious slowpath interrupt!\n"); */ 4773 4774 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status); 4775 4776 /* HW attentions */ 4777 if (status & BNX2X_DEF_SB_ATT_IDX) { 4778 bnx2x_attn_int(bp); 4779 status &= ~BNX2X_DEF_SB_ATT_IDX; 4780 } 4781 4782 /* SP events: STAT_QUERY and others */ 4783 if (status & BNX2X_DEF_SB_IDX) { 4784#ifdef BCM_CNIC 4785 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 4786 4787 if ((!NO_FCOE(bp)) && 4788 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 4789 /* 4790 * Prevent local bottom-halves from running as 4791 * we are going to change the local NAPI list. 4792 */ 4793 local_bh_disable(); 4794 napi_schedule(&bnx2x_fcoe(bp, napi)); 4795 local_bh_enable(); 4796 } 4797#endif 4798 /* Handle EQ completions */ 4799 bnx2x_eq_int(bp); 4800 4801 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 4802 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 4803 4804 status &= ~BNX2X_DEF_SB_IDX; 4805 } 4806 4807 if (unlikely(status)) 4808 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 4809 status); 4810 4811 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 4812 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 4813} 4814 4815irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 4816{ 4817 struct net_device *dev = dev_instance; 4818 struct bnx2x *bp = netdev_priv(dev); 4819 4820 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 4821 IGU_INT_DISABLE, 0); 4822 4823#ifdef BNX2X_STOP_ON_ERROR 4824 if (unlikely(bp->panic)) 4825 return IRQ_HANDLED; 4826#endif 4827 4828#ifdef BCM_CNIC 4829 { 4830 struct cnic_ops *c_ops; 4831 4832 rcu_read_lock(); 4833 c_ops = rcu_dereference(bp->cnic_ops); 4834 if (c_ops) 4835 c_ops->cnic_handler(bp->cnic_data, NULL); 4836 rcu_read_unlock(); 4837 } 4838#endif 4839 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 4840 4841 return IRQ_HANDLED; 4842} 4843 4844/* end of slow path */ 4845 4846 4847void bnx2x_drv_pulse(struct bnx2x *bp) 4848{ 4849 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 4850 bp->fw_drv_pulse_wr_seq); 4851} 4852 4853 4854static void bnx2x_timer(unsigned long data) 4855{ 4856 u8 cos; 4857 struct bnx2x *bp = (struct bnx2x *) data; 4858 4859 if (!netif_running(bp->dev)) 4860 return; 4861 4862 if (poll) { 4863 struct bnx2x_fastpath *fp = &bp->fp[0]; 4864 4865 for_each_cos_in_tx_queue(fp, cos) 4866 bnx2x_tx_int(bp, &fp->txdata[cos]); 4867 bnx2x_rx_int(fp, 1000); 4868 } 4869 4870 if (!BP_NOMCP(bp)) { 4871 int mb_idx = BP_FW_MB_IDX(bp); 4872 u32 drv_pulse; 4873 u32 mcp_pulse; 4874 4875 ++bp->fw_drv_pulse_wr_seq; 4876 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 4877 /* TBD - add SYSTEM_TIME */ 4878 drv_pulse = bp->fw_drv_pulse_wr_seq; 4879 bnx2x_drv_pulse(bp); 4880 4881 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 4882 MCP_PULSE_SEQ_MASK); 4883 /* The delta between driver pulse and mcp response 4884 * should be 1 (before mcp response) or 0 (after mcp response) 4885 */ 4886 if ((drv_pulse != mcp_pulse) && 4887 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 4888 /* someone lost a heartbeat... */ 4889 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 4890 drv_pulse, mcp_pulse); 4891 } 4892 } 4893 4894 if (bp->state == BNX2X_STATE_OPEN) 4895 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 4896 4897 mod_timer(&bp->timer, jiffies + bp->current_interval); 4898} 4899 4900/* end of Statistics */ 4901 4902/* nic init */ 4903 4904/* 4905 * nic init service functions 4906 */ 4907 4908static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 4909{ 4910 u32 i; 4911 if (!(len%4) && !(addr%4)) 4912 for (i = 0; i < len; i += 4) 4913 REG_WR(bp, addr + i, fill); 4914 else 4915 for (i = 0; i < len; i++) 4916 REG_WR8(bp, addr + i, fill); 4917 4918} 4919 4920/* helper: writes FP SP data to FW - data_size in dwords */ 4921static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 4922 int fw_sb_id, 4923 u32 *sb_data_p, 4924 u32 data_size) 4925{ 4926 int index; 4927 for (index = 0; index < data_size; index++) 4928 REG_WR(bp, BAR_CSTRORM_INTMEM + 4929 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 4930 sizeof(u32)*index, 4931 *(sb_data_p + index)); 4932} 4933 4934static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 4935{ 4936 u32 *sb_data_p; 4937 u32 data_size = 0; 4938 struct hc_status_block_data_e2 sb_data_e2; 4939 struct hc_status_block_data_e1x sb_data_e1x; 4940 4941 /* disable the function first */ 4942 if (!CHIP_IS_E1x(bp)) { 4943 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 4944 sb_data_e2.common.state = SB_DISABLED; 4945 sb_data_e2.common.p_func.vf_valid = false; 4946 sb_data_p = (u32 *)&sb_data_e2; 4947 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 4948 } else { 4949 memset(&sb_data_e1x, 0, 4950 sizeof(struct hc_status_block_data_e1x)); 4951 sb_data_e1x.common.state = SB_DISABLED; 4952 sb_data_e1x.common.p_func.vf_valid = false; 4953 sb_data_p = (u32 *)&sb_data_e1x; 4954 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 4955 } 4956 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 4957 4958 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4959 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 4960 CSTORM_STATUS_BLOCK_SIZE); 4961 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4962 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 4963 CSTORM_SYNC_BLOCK_SIZE); 4964} 4965 4966/* helper: writes SP SB data to FW */ 4967static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 4968 struct hc_sp_status_block_data *sp_sb_data) 4969{ 4970 int func = BP_FUNC(bp); 4971 int i; 4972 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 4973 REG_WR(bp, BAR_CSTRORM_INTMEM + 4974 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 4975 i*sizeof(u32), 4976 *((u32 *)sp_sb_data + i)); 4977} 4978 4979static inline void bnx2x_zero_sp_sb(struct bnx2x *bp) 4980{ 4981 int func = BP_FUNC(bp); 4982 struct hc_sp_status_block_data sp_sb_data; 4983 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 4984 4985 sp_sb_data.state = SB_DISABLED; 4986 sp_sb_data.p_func.vf_valid = false; 4987 4988 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 4989 4990 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4991 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 4992 CSTORM_SP_STATUS_BLOCK_SIZE); 4993 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4994 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 4995 CSTORM_SP_SYNC_BLOCK_SIZE); 4996 4997} 4998 4999 5000static inline 5001void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 5002 int igu_sb_id, int igu_seg_id) 5003{ 5004 hc_sm->igu_sb_id = igu_sb_id; 5005 hc_sm->igu_seg_id = igu_seg_id; 5006 hc_sm->timer_value = 0xFF; 5007 hc_sm->time_to_expire = 0xFFFFFFFF; 5008} 5009 5010 5011/* allocates state machine ids. */ 5012static inline 5013void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) 5014{ 5015 /* zero out state machine indices */ 5016 /* rx indices */ 5017 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5018 5019 /* tx indices */ 5020 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5021 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 5022 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 5023 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 5024 5025 /* map indices */ 5026 /* rx indices */ 5027 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 5028 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5029 5030 /* tx indices */ 5031 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 5032 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5033 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 5034 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5035 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 5036 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5037 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 5038 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5039} 5040 5041static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 5042 u8 vf_valid, int fw_sb_id, int igu_sb_id) 5043{ 5044 int igu_seg_id; 5045 5046 struct hc_status_block_data_e2 sb_data_e2; 5047 struct hc_status_block_data_e1x sb_data_e1x; 5048 struct hc_status_block_sm *hc_sm_p; 5049 int data_size; 5050 u32 *sb_data_p; 5051 5052 if (CHIP_INT_MODE_IS_BC(bp)) 5053 igu_seg_id = HC_SEG_ACCESS_NORM; 5054 else 5055 igu_seg_id = IGU_SEG_ACCESS_NORM; 5056 5057 bnx2x_zero_fp_sb(bp, fw_sb_id); 5058 5059 if (!CHIP_IS_E1x(bp)) { 5060 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5061 sb_data_e2.common.state = SB_ENABLED; 5062 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 5063 sb_data_e2.common.p_func.vf_id = vfid; 5064 sb_data_e2.common.p_func.vf_valid = vf_valid; 5065 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 5066 sb_data_e2.common.same_igu_sb_1b = true; 5067 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 5068 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 5069 hc_sm_p = sb_data_e2.common.state_machine; 5070 sb_data_p = (u32 *)&sb_data_e2; 5071 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5072 bnx2x_map_sb_state_machines(sb_data_e2.index_data); 5073 } else { 5074 memset(&sb_data_e1x, 0, 5075 sizeof(struct hc_status_block_data_e1x)); 5076 sb_data_e1x.common.state = SB_ENABLED; 5077 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 5078 sb_data_e1x.common.p_func.vf_id = 0xff; 5079 sb_data_e1x.common.p_func.vf_valid = false; 5080 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 5081 sb_data_e1x.common.same_igu_sb_1b = true; 5082 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 5083 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 5084 hc_sm_p = sb_data_e1x.common.state_machine; 5085 sb_data_p = (u32 *)&sb_data_e1x; 5086 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5087 bnx2x_map_sb_state_machines(sb_data_e1x.index_data); 5088 } 5089 5090 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 5091 igu_sb_id, igu_seg_id); 5092 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 5093 igu_sb_id, igu_seg_id); 5094 5095 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id); 5096 5097 /* write indecies to HW */ 5098 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5099} 5100 5101static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 5102 u16 tx_usec, u16 rx_usec) 5103{ 5104 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 5105 false, rx_usec); 5106 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5107 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 5108 tx_usec); 5109 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5110 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 5111 tx_usec); 5112 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5113 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 5114 tx_usec); 5115} 5116 5117static void bnx2x_init_def_sb(struct bnx2x *bp) 5118{ 5119 struct host_sp_status_block *def_sb = bp->def_status_blk; 5120 dma_addr_t mapping = bp->def_status_blk_mapping; 5121 int igu_sp_sb_index; 5122 int igu_seg_id; 5123 int port = BP_PORT(bp); 5124 int func = BP_FUNC(bp); 5125 int reg_offset, reg_offset_en5; 5126 u64 section; 5127 int index; 5128 struct hc_sp_status_block_data sp_sb_data; 5129 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5130 5131 if (CHIP_INT_MODE_IS_BC(bp)) { 5132 igu_sp_sb_index = DEF_SB_IGU_ID; 5133 igu_seg_id = HC_SEG_ACCESS_DEF; 5134 } else { 5135 igu_sp_sb_index = bp->igu_dsb_id; 5136 igu_seg_id = IGU_SEG_ACCESS_DEF; 5137 } 5138 5139 /* ATTN */ 5140 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5141 atten_status_block); 5142 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 5143 5144 bp->attn_state = 0; 5145 5146 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 5147 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 5148 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 5149 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); 5150 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 5151 int sindex; 5152 /* take care of sig[0]..sig[4] */ 5153 for (sindex = 0; sindex < 4; sindex++) 5154 bp->attn_group[index].sig[sindex] = 5155 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 5156 5157 if (!CHIP_IS_E1x(bp)) 5158 /* 5159 * enable5 is separate from the rest of the registers, 5160 * and therefore the address skip is 4 5161 * and not 16 between the different groups 5162 */ 5163 bp->attn_group[index].sig[4] = REG_RD(bp, 5164 reg_offset_en5 + 0x4*index); 5165 else 5166 bp->attn_group[index].sig[4] = 0; 5167 } 5168 5169 if (bp->common.int_block == INT_BLOCK_HC) { 5170 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 5171 HC_REG_ATTN_MSG0_ADDR_L); 5172 5173 REG_WR(bp, reg_offset, U64_LO(section)); 5174 REG_WR(bp, reg_offset + 4, U64_HI(section)); 5175 } else if (!CHIP_IS_E1x(bp)) { 5176 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 5177 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 5178 } 5179 5180 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5181 sp_sb); 5182 5183 bnx2x_zero_sp_sb(bp); 5184 5185 sp_sb_data.state = SB_ENABLED; 5186 sp_sb_data.host_sb_addr.lo = U64_LO(section); 5187 sp_sb_data.host_sb_addr.hi = U64_HI(section); 5188 sp_sb_data.igu_sb_id = igu_sp_sb_index; 5189 sp_sb_data.igu_seg_id = igu_seg_id; 5190 sp_sb_data.p_func.pf_id = func; 5191 sp_sb_data.p_func.vnic_id = BP_VN(bp); 5192 sp_sb_data.p_func.vf_id = 0xff; 5193 5194 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5195 5196 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 5197} 5198 5199void bnx2x_update_coalesce(struct bnx2x *bp) 5200{ 5201 int i; 5202 5203 for_each_eth_queue(bp, i) 5204 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 5205 bp->tx_ticks, bp->rx_ticks); 5206} 5207 5208static void bnx2x_init_sp_ring(struct bnx2x *bp) 5209{ 5210 spin_lock_init(&bp->spq_lock); 5211 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 5212 5213 bp->spq_prod_idx = 0; 5214 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 5215 bp->spq_prod_bd = bp->spq; 5216 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 5217} 5218 5219static void bnx2x_init_eq_ring(struct bnx2x *bp) 5220{ 5221 int i; 5222 for (i = 1; i <= NUM_EQ_PAGES; i++) { 5223 union event_ring_elem *elem = 5224 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 5225 5226 elem->next_page.addr.hi = 5227 cpu_to_le32(U64_HI(bp->eq_mapping + 5228 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 5229 elem->next_page.addr.lo = 5230 cpu_to_le32(U64_LO(bp->eq_mapping + 5231 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 5232 } 5233 bp->eq_cons = 0; 5234 bp->eq_prod = NUM_EQ_DESC; 5235 bp->eq_cons_sb = BNX2X_EQ_INDEX; 5236 /* we want a warning message before it gets rought... */ 5237 atomic_set(&bp->eq_spq_left, 5238 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 5239} 5240 5241 5242/* called with netif_addr_lock_bh() */ 5243void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 5244 unsigned long rx_mode_flags, 5245 unsigned long rx_accept_flags, 5246 unsigned long tx_accept_flags, 5247 unsigned long ramrod_flags) 5248{ 5249 struct bnx2x_rx_mode_ramrod_params ramrod_param; 5250 int rc; 5251 5252 memset(&ramrod_param, 0, sizeof(ramrod_param)); 5253 5254 /* Prepare ramrod parameters */ 5255 ramrod_param.cid = 0; 5256 ramrod_param.cl_id = cl_id; 5257 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 5258 ramrod_param.func_id = BP_FUNC(bp); 5259 5260 ramrod_param.pstate = &bp->sp_state; 5261 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 5262 5263 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 5264 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 5265 5266 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5267 5268 ramrod_param.ramrod_flags = ramrod_flags; 5269 ramrod_param.rx_mode_flags = rx_mode_flags; 5270 5271 ramrod_param.rx_accept_flags = rx_accept_flags; 5272 ramrod_param.tx_accept_flags = tx_accept_flags; 5273 5274 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 5275 if (rc < 0) { 5276 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 5277 return; 5278 } 5279} 5280 5281/* called with netif_addr_lock_bh() */ 5282void bnx2x_set_storm_rx_mode(struct bnx2x *bp) 5283{ 5284 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 5285 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 5286 5287#ifdef BCM_CNIC 5288 if (!NO_FCOE(bp)) 5289 5290 /* Configure rx_mode of FCoE Queue */ 5291 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 5292#endif 5293 5294 switch (bp->rx_mode) { 5295 case BNX2X_RX_MODE_NONE: 5296 /* 5297 * 'drop all' supersedes any accept flags that may have been 5298 * passed to the function. 5299 */ 5300 break; 5301 case BNX2X_RX_MODE_NORMAL: 5302 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5303 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); 5304 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5305 5306 /* internal switching mode */ 5307 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5308 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); 5309 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5310 5311 break; 5312 case BNX2X_RX_MODE_ALLMULTI: 5313 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5314 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5315 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5316 5317 /* internal switching mode */ 5318 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5319 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5320 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5321 5322 break; 5323 case BNX2X_RX_MODE_PROMISC: 5324 /* According to deffinition of SI mode, iface in promisc mode 5325 * should receive matched and unmatched (in resolution of port) 5326 * unicast packets. 5327 */ 5328 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); 5329 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5330 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5331 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5332 5333 /* internal switching mode */ 5334 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5335 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5336 5337 if (IS_MF_SI(bp)) 5338 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); 5339 else 5340 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5341 5342 break; 5343 default: 5344 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); 5345 return; 5346 } 5347 5348 if (bp->rx_mode != BNX2X_RX_MODE_NONE) { 5349 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); 5350 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); 5351 } 5352 5353 __set_bit(RAMROD_RX, &ramrod_flags); 5354 __set_bit(RAMROD_TX, &ramrod_flags); 5355 5356 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, 5357 tx_accept_flags, ramrod_flags); 5358} 5359 5360static void bnx2x_init_internal_common(struct bnx2x *bp) 5361{ 5362 int i; 5363 5364 if (IS_MF_SI(bp)) 5365 /* 5366 * In switch independent mode, the TSTORM needs to accept 5367 * packets that failed classification, since approximate match 5368 * mac addresses aren't written to NIG LLH 5369 */ 5370 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5371 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); 5372 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ 5373 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5374 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); 5375 5376 /* Zero this manually as its initialization is 5377 currently missing in the initTool */ 5378 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 5379 REG_WR(bp, BAR_USTRORM_INTMEM + 5380 USTORM_AGG_DATA_OFFSET + i * 4, 0); 5381 if (!CHIP_IS_E1x(bp)) { 5382 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 5383 CHIP_INT_MODE_IS_BC(bp) ? 5384 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 5385 } 5386} 5387 5388static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 5389{ 5390 switch (load_code) { 5391 case FW_MSG_CODE_DRV_LOAD_COMMON: 5392 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5393 bnx2x_init_internal_common(bp); 5394 /* no break */ 5395 5396 case FW_MSG_CODE_DRV_LOAD_PORT: 5397 /* nothing to do */ 5398 /* no break */ 5399 5400 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5401 /* internal memory per function is 5402 initialized inside bnx2x_pf_init */ 5403 break; 5404 5405 default: 5406 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5407 break; 5408 } 5409} 5410 5411static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 5412{ 5413 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; 5414} 5415 5416static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 5417{ 5418 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; 5419} 5420 5421static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 5422{ 5423 if (CHIP_IS_E1x(fp->bp)) 5424 return BP_L_ID(fp->bp) + fp->index; 5425 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 5426 return bnx2x_fp_igu_sb_id(fp); 5427} 5428 5429static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 5430{ 5431 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 5432 u8 cos; 5433 unsigned long q_type = 0; 5434 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 5435 fp->rx_queue = fp_idx; 5436 fp->cid = fp_idx; 5437 fp->cl_id = bnx2x_fp_cl_id(fp); 5438 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 5439 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 5440 /* qZone id equals to FW (per path) client id */ 5441 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 5442 5443 /* init shortcut */ 5444 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 5445 5446 /* Setup SB indicies */ 5447 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 5448 5449 /* Configure Queue State object */ 5450 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 5451 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 5452 5453 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 5454 5455 /* init tx data */ 5456 for_each_cos_in_tx_queue(fp, cos) { 5457 bnx2x_init_txdata(bp, &fp->txdata[cos], 5458 CID_COS_TO_TX_ONLY_CID(fp->cid, cos), 5459 FP_COS_TO_TXQ(fp, cos), 5460 BNX2X_TX_SB_INDEX_BASE + cos); 5461 cids[cos] = fp->txdata[cos].cid; 5462 } 5463 5464 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos, 5465 BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 5466 bnx2x_sp_mapping(bp, q_rdata), q_type); 5467 5468 /** 5469 * Configure classification DBs: Always enable Tx switching 5470 */ 5471 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 5472 5473 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) " 5474 "cl_id %d fw_sb %d igu_sb %d\n", 5475 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 5476 fp->igu_sb_id); 5477 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 5478 fp->fw_sb_id, fp->igu_sb_id); 5479 5480 bnx2x_update_fpsb_idx(fp); 5481} 5482 5483void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) 5484{ 5485 int i; 5486 5487 for_each_eth_queue(bp, i) 5488 bnx2x_init_eth_fp(bp, i); 5489#ifdef BCM_CNIC 5490 if (!NO_FCOE(bp)) 5491 bnx2x_init_fcoe_fp(bp); 5492 5493 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 5494 BNX2X_VF_ID_INVALID, false, 5495 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 5496 5497#endif 5498 5499 /* Initialize MOD_ABS interrupts */ 5500 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 5501 bp->common.shmem_base, bp->common.shmem2_base, 5502 BP_PORT(bp)); 5503 /* ensure status block indices were read */ 5504 rmb(); 5505 5506 bnx2x_init_def_sb(bp); 5507 bnx2x_update_dsb_idx(bp); 5508 bnx2x_init_rx_rings(bp); 5509 bnx2x_init_tx_rings(bp); 5510 bnx2x_init_sp_ring(bp); 5511 bnx2x_init_eq_ring(bp); 5512 bnx2x_init_internal(bp, load_code); 5513 bnx2x_pf_init(bp); 5514 bnx2x_stats_init(bp); 5515 5516 /* flush all before enabling interrupts */ 5517 mb(); 5518 mmiowb(); 5519 5520 bnx2x_int_enable(bp); 5521 5522 /* Check for SPIO5 */ 5523 bnx2x_attn_int_deasserted0(bp, 5524 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 5525 AEU_INPUTS_ATTN_BITS_SPIO5); 5526} 5527 5528/* end of nic init */ 5529 5530/* 5531 * gzip service functions 5532 */ 5533 5534static int bnx2x_gunzip_init(struct bnx2x *bp) 5535{ 5536 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 5537 &bp->gunzip_mapping, GFP_KERNEL); 5538 if (bp->gunzip_buf == NULL) 5539 goto gunzip_nomem1; 5540 5541 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 5542 if (bp->strm == NULL) 5543 goto gunzip_nomem2; 5544 5545 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 5546 if (bp->strm->workspace == NULL) 5547 goto gunzip_nomem3; 5548 5549 return 0; 5550 5551gunzip_nomem3: 5552 kfree(bp->strm); 5553 bp->strm = NULL; 5554 5555gunzip_nomem2: 5556 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5557 bp->gunzip_mapping); 5558 bp->gunzip_buf = NULL; 5559 5560gunzip_nomem1: 5561 netdev_err(bp->dev, "Cannot allocate firmware buffer for" 5562 " un-compression\n"); 5563 return -ENOMEM; 5564} 5565 5566static void bnx2x_gunzip_end(struct bnx2x *bp) 5567{ 5568 if (bp->strm) { 5569 vfree(bp->strm->workspace); 5570 kfree(bp->strm); 5571 bp->strm = NULL; 5572 } 5573 5574 if (bp->gunzip_buf) { 5575 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5576 bp->gunzip_mapping); 5577 bp->gunzip_buf = NULL; 5578 } 5579} 5580 5581static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 5582{ 5583 int n, rc; 5584 5585 /* check gzip header */ 5586 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 5587 BNX2X_ERR("Bad gzip header\n"); 5588 return -EINVAL; 5589 } 5590 5591 n = 10; 5592 5593#define FNAME 0x8 5594 5595 if (zbuf[3] & FNAME) 5596 while ((zbuf[n++] != 0) && (n < len)); 5597 5598 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 5599 bp->strm->avail_in = len - n; 5600 bp->strm->next_out = bp->gunzip_buf; 5601 bp->strm->avail_out = FW_BUF_SIZE; 5602 5603 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 5604 if (rc != Z_OK) 5605 return rc; 5606 5607 rc = zlib_inflate(bp->strm, Z_FINISH); 5608 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 5609 netdev_err(bp->dev, "Firmware decompression error: %s\n", 5610 bp->strm->msg); 5611 5612 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 5613 if (bp->gunzip_outlen & 0x3) 5614 netdev_err(bp->dev, "Firmware decompression error:" 5615 " gunzip_outlen (%d) not aligned\n", 5616 bp->gunzip_outlen); 5617 bp->gunzip_outlen >>= 2; 5618 5619 zlib_inflateEnd(bp->strm); 5620 5621 if (rc == Z_STREAM_END) 5622 return 0; 5623 5624 return rc; 5625} 5626 5627/* nic load/unload */ 5628 5629/* 5630 * General service functions 5631 */ 5632 5633/* send a NIG loopback debug packet */ 5634static void bnx2x_lb_pckt(struct bnx2x *bp) 5635{ 5636 u32 wb_write[3]; 5637 5638 /* Ethernet source and destination addresses */ 5639 wb_write[0] = 0x55555555; 5640 wb_write[1] = 0x55555555; 5641 wb_write[2] = 0x20; /* SOP */ 5642 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5643 5644 /* NON-IP protocol */ 5645 wb_write[0] = 0x09000000; 5646 wb_write[1] = 0x55555555; 5647 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 5648 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5649} 5650 5651/* some of the internal memories 5652 * are not directly readable from the driver 5653 * to test them we send debug packets 5654 */ 5655static int bnx2x_int_mem_test(struct bnx2x *bp) 5656{ 5657 int factor; 5658 int count, i; 5659 u32 val = 0; 5660 5661 if (CHIP_REV_IS_FPGA(bp)) 5662 factor = 120; 5663 else if (CHIP_REV_IS_EMUL(bp)) 5664 factor = 200; 5665 else 5666 factor = 1; 5667 5668 /* Disable inputs of parser neighbor blocks */ 5669 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5670 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5671 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5672 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5673 5674 /* Write 0 to parser credits for CFC search request */ 5675 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5676 5677 /* send Ethernet packet */ 5678 bnx2x_lb_pckt(bp); 5679 5680 /* TODO do i reset NIG statistic? */ 5681 /* Wait until NIG register shows 1 packet of size 0x10 */ 5682 count = 1000 * factor; 5683 while (count) { 5684 5685 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5686 val = *bnx2x_sp(bp, wb_data[0]); 5687 if (val == 0x10) 5688 break; 5689 5690 msleep(10); 5691 count--; 5692 } 5693 if (val != 0x10) { 5694 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5695 return -1; 5696 } 5697 5698 /* Wait until PRS register shows 1 packet */ 5699 count = 1000 * factor; 5700 while (count) { 5701 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5702 if (val == 1) 5703 break; 5704 5705 msleep(10); 5706 count--; 5707 } 5708 if (val != 0x1) { 5709 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5710 return -2; 5711 } 5712 5713 /* Reset and init BRB, PRS */ 5714 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5715 msleep(50); 5716 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5717 msleep(50); 5718 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5719 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5720 5721 DP(NETIF_MSG_HW, "part2\n"); 5722 5723 /* Disable inputs of parser neighbor blocks */ 5724 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5725 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5726 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5727 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5728 5729 /* Write 0 to parser credits for CFC search request */ 5730 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5731 5732 /* send 10 Ethernet packets */ 5733 for (i = 0; i < 10; i++) 5734 bnx2x_lb_pckt(bp); 5735 5736 /* Wait until NIG register shows 10 + 1 5737 packets of size 11*0x10 = 0xb0 */ 5738 count = 1000 * factor; 5739 while (count) { 5740 5741 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5742 val = *bnx2x_sp(bp, wb_data[0]); 5743 if (val == 0xb0) 5744 break; 5745 5746 msleep(10); 5747 count--; 5748 } 5749 if (val != 0xb0) { 5750 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5751 return -3; 5752 } 5753 5754 /* Wait until PRS register shows 2 packets */ 5755 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5756 if (val != 2) 5757 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5758 5759 /* Write 1 to parser credits for CFC search request */ 5760 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 5761 5762 /* Wait until PRS register shows 3 packets */ 5763 msleep(10 * factor); 5764 /* Wait until NIG register shows 1 packet of size 0x10 */ 5765 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5766 if (val != 3) 5767 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5768 5769 /* clear NIG EOP FIFO */ 5770 for (i = 0; i < 11; i++) 5771 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 5772 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 5773 if (val != 1) { 5774 BNX2X_ERR("clear of NIG failed\n"); 5775 return -4; 5776 } 5777 5778 /* Reset and init BRB, PRS, NIG */ 5779 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5780 msleep(50); 5781 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5782 msleep(50); 5783 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5784 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5785#ifndef BCM_CNIC 5786 /* set NIC mode */ 5787 REG_WR(bp, PRS_REG_NIC_MODE, 1); 5788#endif 5789 5790 /* Enable inputs of parser neighbor blocks */ 5791 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 5792 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 5793 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 5794 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 5795 5796 DP(NETIF_MSG_HW, "done\n"); 5797 5798 return 0; /* OK */ 5799} 5800 5801static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 5802{ 5803 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 5804 if (!CHIP_IS_E1x(bp)) 5805 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 5806 else 5807 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 5808 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 5809 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 5810 /* 5811 * mask read length error interrupts in brb for parser 5812 * (parsing unit and 'checksum and crc' unit) 5813 * these errors are legal (PU reads fixed length and CAC can cause 5814 * read length error on truncated packets) 5815 */ 5816 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 5817 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 5818 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 5819 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 5820 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 5821 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 5822/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 5823/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 5824 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 5825 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 5826 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 5827/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 5828/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 5829 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 5830 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 5831 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 5832 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 5833/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 5834/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 5835 5836 if (CHIP_REV_IS_FPGA(bp)) 5837 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); 5838 else if (!CHIP_IS_E1x(bp)) 5839 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 5840 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF 5841 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT 5842 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN 5843 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED 5844 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); 5845 else 5846 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); 5847 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 5848 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 5849 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 5850/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 5851 5852 if (!CHIP_IS_E1x(bp)) 5853 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 5854 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 5855 5856 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 5857 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 5858/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 5859 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 5860} 5861 5862static void bnx2x_reset_common(struct bnx2x *bp) 5863{ 5864 u32 val = 0x1400; 5865 5866 /* reset_common */ 5867 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 5868 0xd3ffff7f); 5869 5870 if (CHIP_IS_E3(bp)) { 5871 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 5872 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 5873 } 5874 5875 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); 5876} 5877 5878static void bnx2x_setup_dmae(struct bnx2x *bp) 5879{ 5880 bp->dmae_ready = 0; 5881 spin_lock_init(&bp->dmae_lock); 5882} 5883 5884static void bnx2x_init_pxp(struct bnx2x *bp) 5885{ 5886 u16 devctl; 5887 int r_order, w_order; 5888 5889 pci_read_config_word(bp->pdev, 5890 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); 5891 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); 5892 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 5893 if (bp->mrrs == -1) 5894 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); 5895 else { 5896 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); 5897 r_order = bp->mrrs; 5898 } 5899 5900 bnx2x_init_pxp_arb(bp, r_order, w_order); 5901} 5902 5903static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 5904{ 5905 int is_required; 5906 u32 val; 5907 int port; 5908 5909 if (BP_NOMCP(bp)) 5910 return; 5911 5912 is_required = 0; 5913 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 5914 SHARED_HW_CFG_FAN_FAILURE_MASK; 5915 5916 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) 5917 is_required = 1; 5918 5919 /* 5920 * The fan failure mechanism is usually related to the PHY type since 5921 * the power consumption of the board is affected by the PHY. Currently, 5922 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 5923 */ 5924 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 5925 for (port = PORT_0; port < PORT_MAX; port++) { 5926 is_required |= 5927 bnx2x_fan_failure_det_req( 5928 bp, 5929 bp->common.shmem_base, 5930 bp->common.shmem2_base, 5931 port); 5932 } 5933 5934 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 5935 5936 if (is_required == 0) 5937 return; 5938 5939 /* Fan failure is indicated by SPIO 5 */ 5940 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, 5941 MISC_REGISTERS_SPIO_INPUT_HI_Z); 5942 5943 /* set to active low mode */ 5944 val = REG_RD(bp, MISC_REG_SPIO_INT); 5945 val |= ((1 << MISC_REGISTERS_SPIO_5) << 5946 MISC_REGISTERS_SPIO_INT_OLD_SET_POS); 5947 REG_WR(bp, MISC_REG_SPIO_INT, val); 5948 5949 /* enable interrupt to signal the IGU */ 5950 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 5951 val |= (1 << MISC_REGISTERS_SPIO_5); 5952 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 5953} 5954 5955static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) 5956{ 5957 u32 offset = 0; 5958 5959 if (CHIP_IS_E1(bp)) 5960 return; 5961 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) 5962 return; 5963 5964 switch (BP_ABS_FUNC(bp)) { 5965 case 0: 5966 offset = PXP2_REG_PGL_PRETEND_FUNC_F0; 5967 break; 5968 case 1: 5969 offset = PXP2_REG_PGL_PRETEND_FUNC_F1; 5970 break; 5971 case 2: 5972 offset = PXP2_REG_PGL_PRETEND_FUNC_F2; 5973 break; 5974 case 3: 5975 offset = PXP2_REG_PGL_PRETEND_FUNC_F3; 5976 break; 5977 case 4: 5978 offset = PXP2_REG_PGL_PRETEND_FUNC_F4; 5979 break; 5980 case 5: 5981 offset = PXP2_REG_PGL_PRETEND_FUNC_F5; 5982 break; 5983 case 6: 5984 offset = PXP2_REG_PGL_PRETEND_FUNC_F6; 5985 break; 5986 case 7: 5987 offset = PXP2_REG_PGL_PRETEND_FUNC_F7; 5988 break; 5989 default: 5990 return; 5991 } 5992 5993 REG_WR(bp, offset, pretend_func_num); 5994 REG_RD(bp, offset); 5995 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); 5996} 5997 5998void bnx2x_pf_disable(struct bnx2x *bp) 5999{ 6000 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 6001 val &= ~IGU_PF_CONF_FUNC_EN; 6002 6003 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 6004 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6005 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); 6006} 6007 6008static inline void bnx2x__common_init_phy(struct bnx2x *bp) 6009{ 6010 u32 shmem_base[2], shmem2_base[2]; 6011 shmem_base[0] = bp->common.shmem_base; 6012 shmem2_base[0] = bp->common.shmem2_base; 6013 if (!CHIP_IS_E1x(bp)) { 6014 shmem_base[1] = 6015 SHMEM2_RD(bp, other_shmem_base_addr); 6016 shmem2_base[1] = 6017 SHMEM2_RD(bp, other_shmem2_base_addr); 6018 } 6019 bnx2x_acquire_phy_lock(bp); 6020 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, 6021 bp->common.chip_id); 6022 bnx2x_release_phy_lock(bp); 6023} 6024 6025/** 6026 * bnx2x_init_hw_common - initialize the HW at the COMMON phase. 6027 * 6028 * @bp: driver handle 6029 */ 6030static int bnx2x_init_hw_common(struct bnx2x *bp) 6031{ 6032 u32 val; 6033 6034 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp)); 6035 6036 /* 6037 * take the UNDI lock to protect undi_unload flow from accessing 6038 * registers while we're resetting the chip 6039 */ 6040 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6041 6042 bnx2x_reset_common(bp); 6043 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 6044 6045 val = 0xfffc; 6046 if (CHIP_IS_E3(bp)) { 6047 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 6048 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 6049 } 6050 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 6051 6052 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6053 6054 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 6055 6056 if (!CHIP_IS_E1x(bp)) { 6057 u8 abs_func_id; 6058 6059 /** 6060 * 4-port mode or 2-port mode we need to turn of master-enable 6061 * for everyone, after that, turn it back on for self. 6062 * so, we disregard multi-function or not, and always disable 6063 * for all functions on the given path, this means 0,2,4,6 for 6064 * path 0 and 1,3,5,7 for path 1 6065 */ 6066 for (abs_func_id = BP_PATH(bp); 6067 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { 6068 if (abs_func_id == BP_ABS_FUNC(bp)) { 6069 REG_WR(bp, 6070 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 6071 1); 6072 continue; 6073 } 6074 6075 bnx2x_pretend_func(bp, abs_func_id); 6076 /* clear pf enable */ 6077 bnx2x_pf_disable(bp); 6078 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6079 } 6080 } 6081 6082 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); 6083 if (CHIP_IS_E1(bp)) { 6084 /* enable HW interrupt from PXP on USDM overflow 6085 bit 16 on INT_MASK_0 */ 6086 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 6087 } 6088 6089 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); 6090 bnx2x_init_pxp(bp); 6091 6092#ifdef __BIG_ENDIAN 6093 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); 6094 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); 6095 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 6096 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 6097 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 6098 /* make sure this value is 0 */ 6099 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); 6100 6101/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ 6102 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); 6103 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); 6104 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); 6105 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 6106#endif 6107 6108 bnx2x_ilt_init_page_size(bp, INITOP_SET); 6109 6110 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 6111 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 6112 6113 /* let the HW do it's magic ... */ 6114 msleep(100); 6115 /* finish PXP init */ 6116 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); 6117 if (val != 1) { 6118 BNX2X_ERR("PXP2 CFG failed\n"); 6119 return -EBUSY; 6120 } 6121 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); 6122 if (val != 1) { 6123 BNX2X_ERR("PXP2 RD_INIT failed\n"); 6124 return -EBUSY; 6125 } 6126 6127 /* Timers bug workaround E2 only. We need to set the entire ILT to 6128 * have entries with value "0" and valid bit on. 6129 * This needs to be done by the first PF that is loaded in a path 6130 * (i.e. common phase) 6131 */ 6132 if (!CHIP_IS_E1x(bp)) { 6133/* In E2 there is a bug in the timers block that can cause function 6 / 7 6134 * (i.e. vnic3) to start even if it is marked as "scan-off". 6135 * This occurs when a different function (func2,3) is being marked 6136 * as "scan-off". Real-life scenario for example: if a driver is being 6137 * load-unloaded while func6,7 are down. This will cause the timer to access 6138 * the ilt, translate to a logical address and send a request to read/write. 6139 * Since the ilt for the function that is down is not valid, this will cause 6140 * a translation error which is unrecoverable. 6141 * The Workaround is intended to make sure that when this happens nothing fatal 6142 * will occur. The workaround: 6143 * 1. First PF driver which loads on a path will: 6144 * a. After taking the chip out of reset, by using pretend, 6145 * it will write "0" to the following registers of 6146 * the other vnics. 6147 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6148 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 6149 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 6150 * And for itself it will write '1' to 6151 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 6152 * dmae-operations (writing to pram for example.) 6153 * note: can be done for only function 6,7 but cleaner this 6154 * way. 6155 * b. Write zero+valid to the entire ILT. 6156 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 6157 * VNIC3 (of that port). The range allocated will be the 6158 * entire ILT. This is needed to prevent ILT range error. 6159 * 2. Any PF driver load flow: 6160 * a. ILT update with the physical addresses of the allocated 6161 * logical pages. 6162 * b. Wait 20msec. - note that this timeout is needed to make 6163 * sure there are no requests in one of the PXP internal 6164 * queues with "old" ILT addresses. 6165 * c. PF enable in the PGLC. 6166 * d. Clear the was_error of the PF in the PGLC. (could have 6167 * occured while driver was down) 6168 * e. PF enable in the CFC (WEAK + STRONG) 6169 * f. Timers scan enable 6170 * 3. PF driver unload flow: 6171 * a. Clear the Timers scan_en. 6172 * b. Polling for scan_on=0 for that PF. 6173 * c. Clear the PF enable bit in the PXP. 6174 * d. Clear the PF enable in the CFC (WEAK + STRONG) 6175 * e. Write zero+valid to all ILT entries (The valid bit must 6176 * stay set) 6177 * f. If this is VNIC 3 of a port then also init 6178 * first_timers_ilt_entry to zero and last_timers_ilt_entry 6179 * to the last enrty in the ILT. 6180 * 6181 * Notes: 6182 * Currently the PF error in the PGLC is non recoverable. 6183 * In the future the there will be a recovery routine for this error. 6184 * Currently attention is masked. 6185 * Having an MCP lock on the load/unload process does not guarantee that 6186 * there is no Timer disable during Func6/7 enable. This is because the 6187 * Timers scan is currently being cleared by the MCP on FLR. 6188 * Step 2.d can be done only for PF6/7 and the driver can also check if 6189 * there is error before clearing it. But the flow above is simpler and 6190 * more general. 6191 * All ILT entries are written by zero+valid and not just PF6/7 6192 * ILT entries since in the future the ILT entries allocation for 6193 * PF-s might be dynamic. 6194 */ 6195 struct ilt_client_info ilt_cli; 6196 struct bnx2x_ilt ilt; 6197 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 6198 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); 6199 6200 /* initialize dummy TM client */ 6201 ilt_cli.start = 0; 6202 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 6203 ilt_cli.client_num = ILT_CLIENT_TM; 6204 6205 /* Step 1: set zeroes to all ilt page entries with valid bit on 6206 * Step 2: set the timers first/last ilt entry to point 6207 * to the entire range to prevent ILT range error for 3rd/4th 6208 * vnic (this code assumes existance of the vnic) 6209 * 6210 * both steps performed by call to bnx2x_ilt_client_init_op() 6211 * with dummy TM client 6212 * 6213 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 6214 * and his brother are split registers 6215 */ 6216 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); 6217 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); 6218 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6219 6220 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); 6221 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); 6222 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 6223 } 6224 6225 6226 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 6227 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 6228 6229 if (!CHIP_IS_E1x(bp)) { 6230 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : 6231 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); 6232 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); 6233 6234 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); 6235 6236 /* let the HW do it's magic ... */ 6237 do { 6238 msleep(200); 6239 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); 6240 } while (factor-- && (val != 1)); 6241 6242 if (val != 1) { 6243 BNX2X_ERR("ATC_INIT failed\n"); 6244 return -EBUSY; 6245 } 6246 } 6247 6248 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); 6249 6250 /* clean the DMAE memory */ 6251 bp->dmae_ready = 1; 6252 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); 6253 6254 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); 6255 6256 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); 6257 6258 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); 6259 6260 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); 6261 6262 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); 6263 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); 6264 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); 6265 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); 6266 6267 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); 6268 6269 6270 /* QM queues pointers table */ 6271 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); 6272 6273 /* soft reset pulse */ 6274 REG_WR(bp, QM_REG_SOFT_RESET, 1); 6275 REG_WR(bp, QM_REG_SOFT_RESET, 0); 6276 6277#ifdef BCM_CNIC 6278 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); 6279#endif 6280 6281 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); 6282 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); 6283 if (!CHIP_REV_IS_SLOW(bp)) 6284 /* enable hw interrupt from doorbell Q */ 6285 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6286 6287 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6288 6289 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6290 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 6291 6292 if (!CHIP_IS_E1(bp)) 6293 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); 6294 6295 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) 6296 /* Bit-map indicating which L2 hdrs may appear 6297 * after the basic Ethernet header 6298 */ 6299 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 6300 bp->path_has_ovlan ? 7 : 6); 6301 6302 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); 6303 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); 6304 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); 6305 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); 6306 6307 if (!CHIP_IS_E1x(bp)) { 6308 /* reset VFC memories */ 6309 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6310 VFC_MEMORIES_RST_REG_CAM_RST | 6311 VFC_MEMORIES_RST_REG_RAM_RST); 6312 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6313 VFC_MEMORIES_RST_REG_CAM_RST | 6314 VFC_MEMORIES_RST_REG_RAM_RST); 6315 6316 msleep(20); 6317 } 6318 6319 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); 6320 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); 6321 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); 6322 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); 6323 6324 /* sync semi rtc */ 6325 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6326 0x80000000); 6327 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 6328 0x80000000); 6329 6330 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); 6331 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); 6332 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); 6333 6334 if (!CHIP_IS_E1x(bp)) 6335 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 6336 bp->path_has_ovlan ? 7 : 6); 6337 6338 REG_WR(bp, SRC_REG_SOFT_RST, 1); 6339 6340 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); 6341 6342#ifdef BCM_CNIC 6343 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 6344 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 6345 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); 6346 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); 6347 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); 6348 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 6349 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); 6350 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 6351 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); 6352 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); 6353#endif 6354 REG_WR(bp, SRC_REG_SOFT_RST, 0); 6355 6356 if (sizeof(union cdu_context) != 1024) 6357 /* we currently assume that a context is 1024 bytes */ 6358 dev_alert(&bp->pdev->dev, "please adjust the size " 6359 "of cdu_context(%ld)\n", 6360 (long)sizeof(union cdu_context)); 6361 6362 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 6363 val = (4 << 24) + (0 << 12) + 1024; 6364 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); 6365 6366 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); 6367 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); 6368 /* enable context validation interrupt from CFC */ 6369 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6370 6371 /* set the thresholds to prevent CFC/CDU race */ 6372 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 6373 6374 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); 6375 6376 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) 6377 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); 6378 6379 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); 6380 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); 6381 6382 /* Reset PCIE errors for debug */ 6383 REG_WR(bp, 0x2814, 0xffffffff); 6384 REG_WR(bp, 0x3820, 0xffffffff); 6385 6386 if (!CHIP_IS_E1x(bp)) { 6387 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 6388 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 6389 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 6390 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 6391 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 6392 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 6393 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 6394 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 6395 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 6396 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 6397 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 6398 } 6399 6400 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); 6401 if (!CHIP_IS_E1(bp)) { 6402 /* in E3 this done in per-port section */ 6403 if (!CHIP_IS_E3(bp)) 6404 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6405 } 6406 if (CHIP_IS_E1H(bp)) 6407 /* not applicable for E2 (and above ...) */ 6408 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); 6409 6410 if (CHIP_REV_IS_SLOW(bp)) 6411 msleep(200); 6412 6413 /* finish CFC init */ 6414 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); 6415 if (val != 1) { 6416 BNX2X_ERR("CFC LL_INIT failed\n"); 6417 return -EBUSY; 6418 } 6419 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); 6420 if (val != 1) { 6421 BNX2X_ERR("CFC AC_INIT failed\n"); 6422 return -EBUSY; 6423 } 6424 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 6425 if (val != 1) { 6426 BNX2X_ERR("CFC CAM_INIT failed\n"); 6427 return -EBUSY; 6428 } 6429 REG_WR(bp, CFC_REG_DEBUG0, 0); 6430 6431 if (CHIP_IS_E1(bp)) { 6432 /* read NIG statistic 6433 to see if this is our first up since powerup */ 6434 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6435 val = *bnx2x_sp(bp, wb_data[0]); 6436 6437 /* do internal memory self test */ 6438 if ((val == 0) && bnx2x_int_mem_test(bp)) { 6439 BNX2X_ERR("internal mem self test failed\n"); 6440 return -EBUSY; 6441 } 6442 } 6443 6444 bnx2x_setup_fan_failure_detection(bp); 6445 6446 /* clear PXP2 attentions */ 6447 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 6448 6449 bnx2x_enable_blocks_attention(bp); 6450 bnx2x_enable_blocks_parity(bp); 6451 6452 if (!BP_NOMCP(bp)) { 6453 if (CHIP_IS_E1x(bp)) 6454 bnx2x__common_init_phy(bp); 6455 } else 6456 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 6457 6458 return 0; 6459} 6460 6461/** 6462 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. 6463 * 6464 * @bp: driver handle 6465 */ 6466static int bnx2x_init_hw_common_chip(struct bnx2x *bp) 6467{ 6468 int rc = bnx2x_init_hw_common(bp); 6469 6470 if (rc) 6471 return rc; 6472 6473 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 6474 if (!BP_NOMCP(bp)) 6475 bnx2x__common_init_phy(bp); 6476 6477 return 0; 6478} 6479 6480static int bnx2x_init_hw_port(struct bnx2x *bp) 6481{ 6482 int port = BP_PORT(bp); 6483 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 6484 u32 low, high; 6485 u32 val; 6486 6487 bnx2x__link_reset(bp); 6488 6489 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port); 6490 6491 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 6492 6493 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6494 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6495 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6496 6497 /* Timers bug workaround: disables the pf_master bit in pglue at 6498 * common phase, we need to enable it here before any dmae access are 6499 * attempted. Therefore we manually added the enable-master to the 6500 * port phase (it also happens in the function phase) 6501 */ 6502 if (!CHIP_IS_E1x(bp)) 6503 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6504 6505 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6506 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6507 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6508 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6509 6510 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6511 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6512 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6513 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6514 6515 /* QM cid (connection) count */ 6516 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); 6517 6518#ifdef BCM_CNIC 6519 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6520 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 6521 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 6522#endif 6523 6524 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6525 6526 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { 6527 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6528 6529 if (IS_MF(bp)) 6530 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 6531 else if (bp->dev->mtu > 4096) { 6532 if (bp->flags & ONE_PORT_FLAG) 6533 low = 160; 6534 else { 6535 val = bp->dev->mtu; 6536 /* (24*1024 + val*4)/256 */ 6537 low = 96 + (val/64) + 6538 ((val % 64) ? 1 : 0); 6539 } 6540 } else 6541 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 6542 high = low + 56; /* 14*1024/256 */ 6543 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 6544 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 6545 } 6546 6547 if (CHIP_MODE_IS_4_PORT(bp)) 6548 REG_WR(bp, (BP_PORT(bp) ? 6549 BRB1_REG_MAC_GUARANTIED_1 : 6550 BRB1_REG_MAC_GUARANTIED_0), 40); 6551 6552 6553 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6554 if (CHIP_IS_E3B0(bp)) 6555 /* Ovlan exists only if we are in multi-function + 6556 * switch-dependent mode, in switch-independent there 6557 * is no ovlan headers 6558 */ 6559 REG_WR(bp, BP_PORT(bp) ? 6560 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 6561 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 6562 (bp->path_has_ovlan ? 7 : 6)); 6563 6564 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6565 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6566 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6567 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6568 6569 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6570 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6571 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6572 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6573 6574 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6575 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6576 6577 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6578 6579 if (CHIP_IS_E1x(bp)) { 6580 /* configure PBF to work without PAUSE mtu 9000 */ 6581 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 6582 6583 /* update threshold */ 6584 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 6585 /* update init credit */ 6586 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 6587 6588 /* probe changes */ 6589 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 6590 udelay(50); 6591 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 6592 } 6593 6594#ifdef BCM_CNIC 6595 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6596#endif 6597 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6598 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6599 6600 if (CHIP_IS_E1(bp)) { 6601 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6602 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6603 } 6604 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6605 6606 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6607 6608 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6609 /* init aeu_mask_attn_func_0/1: 6610 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 6611 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 6612 * bits 4-7 are used for "per vn group attention" */ 6613 val = IS_MF(bp) ? 0xF7 : 0x7; 6614 /* Enable DCBX attention for all but E1 */ 6615 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 6616 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 6617 6618 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6619 6620 if (!CHIP_IS_E1x(bp)) { 6621 /* Bit-map indicating which L2 hdrs may appear after the 6622 * basic Ethernet header 6623 */ 6624 REG_WR(bp, BP_PORT(bp) ? 6625 NIG_REG_P1_HDRS_AFTER_BASIC : 6626 NIG_REG_P0_HDRS_AFTER_BASIC, 6627 IS_MF_SD(bp) ? 7 : 6); 6628 6629 if (CHIP_IS_E3(bp)) 6630 REG_WR(bp, BP_PORT(bp) ? 6631 NIG_REG_LLH1_MF_MODE : 6632 NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6633 } 6634 if (!CHIP_IS_E3(bp)) 6635 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 6636 6637 if (!CHIP_IS_E1(bp)) { 6638 /* 0x2 disable mf_ov, 0x1 enable */ 6639 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 6640 (IS_MF_SD(bp) ? 0x1 : 0x2)); 6641 6642 if (!CHIP_IS_E1x(bp)) { 6643 val = 0; 6644 switch (bp->mf_mode) { 6645 case MULTI_FUNCTION_SD: 6646 val = 1; 6647 break; 6648 case MULTI_FUNCTION_SI: 6649 val = 2; 6650 break; 6651 } 6652 6653 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : 6654 NIG_REG_LLH0_CLS_TYPE), val); 6655 } 6656 { 6657 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 6658 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 6659 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 6660 } 6661 } 6662 6663 6664 /* If SPIO5 is set to generate interrupts, enable it for this port */ 6665 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6666 if (val & (1 << MISC_REGISTERS_SPIO_5)) { 6667 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 6668 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 6669 val = REG_RD(bp, reg_addr); 6670 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 6671 REG_WR(bp, reg_addr, val); 6672 } 6673 6674 return 0; 6675} 6676 6677static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 6678{ 6679 int reg; 6680 6681 if (CHIP_IS_E1(bp)) 6682 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 6683 else 6684 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 6685 6686 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr)); 6687} 6688 6689static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) 6690{ 6691 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); 6692} 6693 6694static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) 6695{ 6696 u32 i, base = FUNC_ILT_BASE(func); 6697 for (i = base; i < base + ILT_PER_FUNC; i++) 6698 bnx2x_ilt_wr(bp, i, 0); 6699} 6700 6701static int bnx2x_init_hw_func(struct bnx2x *bp) 6702{ 6703 int port = BP_PORT(bp); 6704 int func = BP_FUNC(bp); 6705 int init_phase = PHASE_PF0 + func; 6706 struct bnx2x_ilt *ilt = BP_ILT(bp); 6707 u16 cdu_ilt_start; 6708 u32 addr, val; 6709 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 6710 int i, main_mem_width, rc; 6711 6712 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func); 6713 6714 /* FLR cleanup - hmmm */ 6715 if (!CHIP_IS_E1x(bp)) { 6716 rc = bnx2x_pf_flr_clnup(bp); 6717 if (rc) 6718 return rc; 6719 } 6720 6721 /* set MSI reconfigure capability */ 6722 if (bp->common.int_block == INT_BLOCK_HC) { 6723 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 6724 val = REG_RD(bp, addr); 6725 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 6726 REG_WR(bp, addr, val); 6727 } 6728 6729 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6730 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6731 6732 ilt = BP_ILT(bp); 6733 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 6734 6735 for (i = 0; i < L2_ILT_LINES(bp); i++) { 6736 ilt->lines[cdu_ilt_start + i].page = 6737 bp->context.vcxt + (ILT_PAGE_CIDS * i); 6738 ilt->lines[cdu_ilt_start + i].page_mapping = 6739 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i); 6740 /* cdu ilt pages are allocated manually so there's no need to 6741 set the size */ 6742 } 6743 bnx2x_ilt_init_op(bp, INITOP_SET); 6744 6745#ifdef BCM_CNIC 6746 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); 6747 6748 /* T1 hash bits value determines the T1 number of entries */ 6749 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 6750#endif 6751 6752#ifndef BCM_CNIC 6753 /* set NIC mode */ 6754 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6755#endif /* BCM_CNIC */ 6756 6757 if (!CHIP_IS_E1x(bp)) { 6758 u32 pf_conf = IGU_PF_CONF_FUNC_EN; 6759 6760 /* Turn on a single ISR mode in IGU if driver is going to use 6761 * INT#x or MSI 6762 */ 6763 if (!(bp->flags & USING_MSIX_FLAG)) 6764 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 6765 /* 6766 * Timers workaround bug: function init part. 6767 * Need to wait 20msec after initializing ILT, 6768 * needed to make sure there are no requests in 6769 * one of the PXP internal queues with "old" ILT addresses 6770 */ 6771 msleep(20); 6772 /* 6773 * Master enable - Due to WB DMAE writes performed before this 6774 * register is re-initialized as part of the regular function 6775 * init 6776 */ 6777 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6778 /* Enable the function in IGU */ 6779 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); 6780 } 6781 6782 bp->dmae_ready = 1; 6783 6784 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6785 6786 if (!CHIP_IS_E1x(bp)) 6787 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); 6788 6789 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6790 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6791 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6792 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6793 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6794 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6795 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6796 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6797 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6798 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6799 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6800 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6801 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6802 6803 if (!CHIP_IS_E1x(bp)) 6804 REG_WR(bp, QM_REG_PF_EN, 1); 6805 6806 if (!CHIP_IS_E1x(bp)) { 6807 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6808 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6809 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6810 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6811 } 6812 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6813 6814 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6815 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6816 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6817 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6818 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6819 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6820 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6821 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6822 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6823 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6824 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6825 if (!CHIP_IS_E1x(bp)) 6826 REG_WR(bp, PBF_REG_DISABLE_PF, 0); 6827 6828 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6829 6830 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6831 6832 if (!CHIP_IS_E1x(bp)) 6833 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); 6834 6835 if (IS_MF(bp)) { 6836 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 6837 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); 6838 } 6839 6840 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6841 6842 /* HC init per function */ 6843 if (bp->common.int_block == INT_BLOCK_HC) { 6844 if (CHIP_IS_E1H(bp)) { 6845 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6846 6847 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6848 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6849 } 6850 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6851 6852 } else { 6853 int num_segs, sb_idx, prod_offset; 6854 6855 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6856 6857 if (!CHIP_IS_E1x(bp)) { 6858 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 6859 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 6860 } 6861 6862 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6863 6864 if (!CHIP_IS_E1x(bp)) { 6865 int dsb_idx = 0; 6866 /** 6867 * Producer memory: 6868 * E2 mode: address 0-135 match to the mapping memory; 6869 * 136 - PF0 default prod; 137 - PF1 default prod; 6870 * 138 - PF2 default prod; 139 - PF3 default prod; 6871 * 140 - PF0 attn prod; 141 - PF1 attn prod; 6872 * 142 - PF2 attn prod; 143 - PF3 attn prod; 6873 * 144-147 reserved. 6874 * 6875 * E1.5 mode - In backward compatible mode; 6876 * for non default SB; each even line in the memory 6877 * holds the U producer and each odd line hold 6878 * the C producer. The first 128 producers are for 6879 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 6880 * producers are for the DSB for each PF. 6881 * Each PF has five segments: (the order inside each 6882 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 6883 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 6884 * 144-147 attn prods; 6885 */ 6886 /* non-default-status-blocks */ 6887 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6888 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 6889 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { 6890 prod_offset = (bp->igu_base_sb + sb_idx) * 6891 num_segs; 6892 6893 for (i = 0; i < num_segs; i++) { 6894 addr = IGU_REG_PROD_CONS_MEMORY + 6895 (prod_offset + i) * 4; 6896 REG_WR(bp, addr, 0); 6897 } 6898 /* send consumer update with value 0 */ 6899 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, 6900 USTORM_ID, 0, IGU_INT_NOP, 1); 6901 bnx2x_igu_clear_sb(bp, 6902 bp->igu_base_sb + sb_idx); 6903 } 6904 6905 /* default-status-blocks */ 6906 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6907 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 6908 6909 if (CHIP_MODE_IS_4_PORT(bp)) 6910 dsb_idx = BP_FUNC(bp); 6911 else 6912 dsb_idx = BP_VN(bp); 6913 6914 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 6915 IGU_BC_BASE_DSB_PROD + dsb_idx : 6916 IGU_NORM_BASE_DSB_PROD + dsb_idx); 6917 6918 /* 6919 * igu prods come in chunks of E1HVN_MAX (4) - 6920 * does not matters what is the current chip mode 6921 */ 6922 for (i = 0; i < (num_segs * E1HVN_MAX); 6923 i += E1HVN_MAX) { 6924 addr = IGU_REG_PROD_CONS_MEMORY + 6925 (prod_offset + i)*4; 6926 REG_WR(bp, addr, 0); 6927 } 6928 /* send consumer update with 0 */ 6929 if (CHIP_INT_MODE_IS_BC(bp)) { 6930 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6931 USTORM_ID, 0, IGU_INT_NOP, 1); 6932 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6933 CSTORM_ID, 0, IGU_INT_NOP, 1); 6934 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6935 XSTORM_ID, 0, IGU_INT_NOP, 1); 6936 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6937 TSTORM_ID, 0, IGU_INT_NOP, 1); 6938 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6939 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6940 } else { 6941 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6942 USTORM_ID, 0, IGU_INT_NOP, 1); 6943 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6944 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6945 } 6946 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); 6947 6948 /* !!! these should become driver const once 6949 rf-tool supports split-68 const */ 6950 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 6951 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 6952 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 6953 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 6954 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 6955 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 6956 } 6957 } 6958 6959 /* Reset PCIE errors for debug */ 6960 REG_WR(bp, 0x2114, 0xffffffff); 6961 REG_WR(bp, 0x2120, 0xffffffff); 6962 6963 if (CHIP_IS_E1x(bp)) { 6964 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 6965 main_mem_base = HC_REG_MAIN_MEMORY + 6966 BP_PORT(bp) * (main_mem_size * 4); 6967 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 6968 main_mem_width = 8; 6969 6970 val = REG_RD(bp, main_mem_prty_clr); 6971 if (val) 6972 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC " 6973 "block during " 6974 "function init (0x%x)!\n", val); 6975 6976 /* Clear "false" parity errors in MSI-X table */ 6977 for (i = main_mem_base; 6978 i < main_mem_base + main_mem_size * 4; 6979 i += main_mem_width) { 6980 bnx2x_read_dmae(bp, i, main_mem_width / 4); 6981 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), 6982 i, main_mem_width / 4); 6983 } 6984 /* Clear HC parity attention */ 6985 REG_RD(bp, main_mem_prty_clr); 6986 } 6987 6988#ifdef BNX2X_STOP_ON_ERROR 6989 /* Enable STORMs SP logging */ 6990 REG_WR8(bp, BAR_USTRORM_INTMEM + 6991 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6992 REG_WR8(bp, BAR_TSTRORM_INTMEM + 6993 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6994 REG_WR8(bp, BAR_CSTRORM_INTMEM + 6995 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6996 REG_WR8(bp, BAR_XSTRORM_INTMEM + 6997 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6998#endif 6999 7000 bnx2x_phy_probe(&bp->link_params); 7001 7002 return 0; 7003} 7004 7005 7006void bnx2x_free_mem(struct bnx2x *bp) 7007{ 7008 /* fastpath */ 7009 bnx2x_free_fp_mem(bp); 7010 /* end of fastpath */ 7011 7012 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 7013 sizeof(struct host_sp_status_block)); 7014 7015 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 7016 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7017 7018 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 7019 sizeof(struct bnx2x_slowpath)); 7020 7021 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping, 7022 bp->context.size); 7023 7024 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); 7025 7026 BNX2X_FREE(bp->ilt->lines); 7027 7028#ifdef BCM_CNIC 7029 if (!CHIP_IS_E1x(bp)) 7030 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, 7031 sizeof(struct host_hc_status_block_e2)); 7032 else 7033 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, 7034 sizeof(struct host_hc_status_block_e1x)); 7035 7036 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 7037#endif 7038 7039 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 7040 7041 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, 7042 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7043} 7044 7045static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) 7046{ 7047 int num_groups; 7048 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1; 7049 7050 /* number of queues for statistics is number of eth queues + FCoE */ 7051 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats; 7052 7053 /* Total number of FW statistics requests = 7054 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats + 7055 * num of queues 7056 */ 7057 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats; 7058 7059 7060 /* Request is built from stats_query_header and an array of 7061 * stats_query_cmd_group each of which contains 7062 * STATS_QUERY_CMD_COUNT rules. The real number or requests is 7063 * configured in the stats_query_header. 7064 */ 7065 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) + 7066 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0); 7067 7068 bp->fw_stats_req_sz = sizeof(struct stats_query_header) + 7069 num_groups * sizeof(struct stats_query_cmd_group); 7070 7071 /* Data for statistics requests + stats_conter 7072 * 7073 * stats_counter holds per-STORM counters that are incremented 7074 * when STORM has finished with the current request. 7075 * 7076 * memory for FCoE offloaded statistics are counted anyway, 7077 * even if they will not be sent. 7078 */ 7079 bp->fw_stats_data_sz = sizeof(struct per_port_stats) + 7080 sizeof(struct per_pf_stats) + 7081 sizeof(struct fcoe_statistics_params) + 7082 sizeof(struct per_queue_stats) * num_queue_stats + 7083 sizeof(struct stats_counter); 7084 7085 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, 7086 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7087 7088 /* Set shortcuts */ 7089 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; 7090 bp->fw_stats_req_mapping = bp->fw_stats_mapping; 7091 7092 bp->fw_stats_data = (struct bnx2x_fw_stats_data *) 7093 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); 7094 7095 bp->fw_stats_data_mapping = bp->fw_stats_mapping + 7096 bp->fw_stats_req_sz; 7097 return 0; 7098 7099alloc_mem_err: 7100 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 7101 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7102 return -ENOMEM; 7103} 7104 7105 7106int bnx2x_alloc_mem(struct bnx2x *bp) 7107{ 7108#ifdef BCM_CNIC 7109 if (!CHIP_IS_E1x(bp)) 7110 /* size = the status block + ramrod buffers */ 7111 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, 7112 sizeof(struct host_hc_status_block_e2)); 7113 else 7114 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, 7115 sizeof(struct host_hc_status_block_e1x)); 7116 7117 /* allocate searcher T2 table */ 7118 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); 7119#endif 7120 7121 7122 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, 7123 sizeof(struct host_sp_status_block)); 7124 7125 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, 7126 sizeof(struct bnx2x_slowpath)); 7127 7128 /* Allocated memory for FW statistics */ 7129 if (bnx2x_alloc_fw_stats_mem(bp)) 7130 goto alloc_mem_err; 7131 7132 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); 7133 7134 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping, 7135 bp->context.size); 7136 7137 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); 7138 7139 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) 7140 goto alloc_mem_err; 7141 7142 /* Slow path ring */ 7143 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); 7144 7145 /* EQ */ 7146 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, 7147 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7148 7149 7150 /* fastpath */ 7151 /* need to be done at the end, since it's self adjusting to amount 7152 * of memory available for RSS queues 7153 */ 7154 if (bnx2x_alloc_fp_mem(bp)) 7155 goto alloc_mem_err; 7156 return 0; 7157 7158alloc_mem_err: 7159 bnx2x_free_mem(bp); 7160 return -ENOMEM; 7161} 7162 7163/* 7164 * Init service functions 7165 */ 7166 7167int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 7168 struct bnx2x_vlan_mac_obj *obj, bool set, 7169 int mac_type, unsigned long *ramrod_flags) 7170{ 7171 int rc; 7172 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 7173 7174 memset(&ramrod_param, 0, sizeof(ramrod_param)); 7175 7176 /* Fill general parameters */ 7177 ramrod_param.vlan_mac_obj = obj; 7178 ramrod_param.ramrod_flags = *ramrod_flags; 7179 7180 /* Fill a user request section if needed */ 7181 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 7182 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 7183 7184 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 7185 7186 /* Set the command: ADD or DEL */ 7187 if (set) 7188 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 7189 else 7190 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 7191 } 7192 7193 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 7194 if (rc < 0) 7195 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); 7196 return rc; 7197} 7198 7199int bnx2x_del_all_macs(struct bnx2x *bp, 7200 struct bnx2x_vlan_mac_obj *mac_obj, 7201 int mac_type, bool wait_for_comp) 7202{ 7203 int rc; 7204 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 7205 7206 /* Wait for completion of requested */ 7207 if (wait_for_comp) 7208 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7209 7210 /* Set the mac type of addresses we want to clear */ 7211 __set_bit(mac_type, &vlan_mac_flags); 7212 7213 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); 7214 if (rc < 0) 7215 BNX2X_ERR("Failed to delete MACs: %d\n", rc); 7216 7217 return rc; 7218} 7219 7220int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) 7221{ 7222 unsigned long ramrod_flags = 0; 7223 7224#ifdef BCM_CNIC 7225 if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_ISCSI_SD(bp)) { 7226 DP(NETIF_MSG_IFUP, "Ignoring Zero MAC for iSCSI SD mode\n"); 7227 return 0; 7228 } 7229#endif 7230 7231 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); 7232 7233 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7234 /* Eth MAC is set on RSS leading client (fp[0]) */ 7235 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set, 7236 BNX2X_ETH_MAC, &ramrod_flags); 7237} 7238 7239int bnx2x_setup_leading(struct bnx2x *bp) 7240{ 7241 return bnx2x_setup_queue(bp, &bp->fp[0], 1); 7242} 7243 7244/** 7245 * bnx2x_set_int_mode - configure interrupt mode 7246 * 7247 * @bp: driver handle 7248 * 7249 * In case of MSI-X it will also try to enable MSI-X. 7250 */ 7251static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) 7252{ 7253 switch (int_mode) { 7254 case INT_MODE_MSI: 7255 bnx2x_enable_msi(bp); 7256 /* falling through... */ 7257 case INT_MODE_INTx: 7258 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7259 DP(NETIF_MSG_IFUP, "set number of queues to 1\n"); 7260 break; 7261 default: 7262 /* Set number of queues according to bp->multi_mode value */ 7263 bnx2x_set_num_queues(bp); 7264 7265 DP(NETIF_MSG_IFUP, "set number of queues to %d\n", 7266 bp->num_queues); 7267 7268 /* if we can't use MSI-X we only need one fp, 7269 * so try to enable MSI-X with the requested number of fp's 7270 * and fallback to MSI or legacy INTx with one fp 7271 */ 7272 if (bnx2x_enable_msix(bp)) { 7273 /* failed to enable MSI-X */ 7274 if (bp->multi_mode) 7275 DP(NETIF_MSG_IFUP, 7276 "Multi requested but failed to " 7277 "enable MSI-X (%d), " 7278 "set number of queues to %d\n", 7279 bp->num_queues, 7280 1 + NON_ETH_CONTEXT_USE); 7281 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7282 7283 /* Try to enable MSI */ 7284 if (!(bp->flags & DISABLE_MSI_FLAG)) 7285 bnx2x_enable_msi(bp); 7286 } 7287 break; 7288 } 7289} 7290 7291/* must be called prioir to any HW initializations */ 7292static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) 7293{ 7294 return L2_ILT_LINES(bp); 7295} 7296 7297void bnx2x_ilt_set_info(struct bnx2x *bp) 7298{ 7299 struct ilt_client_info *ilt_client; 7300 struct bnx2x_ilt *ilt = BP_ILT(bp); 7301 u16 line = 0; 7302 7303 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); 7304 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); 7305 7306 /* CDU */ 7307 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 7308 ilt_client->client_num = ILT_CLIENT_CDU; 7309 ilt_client->page_size = CDU_ILT_PAGE_SZ; 7310 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 7311 ilt_client->start = line; 7312 line += bnx2x_cid_ilt_lines(bp); 7313#ifdef BCM_CNIC 7314 line += CNIC_ILT_LINES; 7315#endif 7316 ilt_client->end = line - 1; 7317 7318 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, " 7319 "flags 0x%x, hw psz %d\n", 7320 ilt_client->start, 7321 ilt_client->end, 7322 ilt_client->page_size, 7323 ilt_client->flags, 7324 ilog2(ilt_client->page_size >> 12)); 7325 7326 /* QM */ 7327 if (QM_INIT(bp->qm_cid_count)) { 7328 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 7329 ilt_client->client_num = ILT_CLIENT_QM; 7330 ilt_client->page_size = QM_ILT_PAGE_SZ; 7331 ilt_client->flags = 0; 7332 ilt_client->start = line; 7333 7334 /* 4 bytes for each cid */ 7335 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 7336 QM_ILT_PAGE_SZ); 7337 7338 ilt_client->end = line - 1; 7339 7340 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, " 7341 "flags 0x%x, hw psz %d\n", 7342 ilt_client->start, 7343 ilt_client->end, 7344 ilt_client->page_size, 7345 ilt_client->flags, 7346 ilog2(ilt_client->page_size >> 12)); 7347 7348 } 7349 /* SRC */ 7350 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 7351#ifdef BCM_CNIC 7352 ilt_client->client_num = ILT_CLIENT_SRC; 7353 ilt_client->page_size = SRC_ILT_PAGE_SZ; 7354 ilt_client->flags = 0; 7355 ilt_client->start = line; 7356 line += SRC_ILT_LINES; 7357 ilt_client->end = line - 1; 7358 7359 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, " 7360 "flags 0x%x, hw psz %d\n", 7361 ilt_client->start, 7362 ilt_client->end, 7363 ilt_client->page_size, 7364 ilt_client->flags, 7365 ilog2(ilt_client->page_size >> 12)); 7366 7367#else 7368 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7369#endif 7370 7371 /* TM */ 7372 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 7373#ifdef BCM_CNIC 7374 ilt_client->client_num = ILT_CLIENT_TM; 7375 ilt_client->page_size = TM_ILT_PAGE_SZ; 7376 ilt_client->flags = 0; 7377 ilt_client->start = line; 7378 line += TM_ILT_LINES; 7379 ilt_client->end = line - 1; 7380 7381 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, " 7382 "flags 0x%x, hw psz %d\n", 7383 ilt_client->start, 7384 ilt_client->end, 7385 ilt_client->page_size, 7386 ilt_client->flags, 7387 ilog2(ilt_client->page_size >> 12)); 7388 7389#else 7390 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7391#endif 7392 BUG_ON(line > ILT_MAX_LINES); 7393} 7394 7395/** 7396 * bnx2x_pf_q_prep_init - prepare INIT transition parameters 7397 * 7398 * @bp: driver handle 7399 * @fp: pointer to fastpath 7400 * @init_params: pointer to parameters structure 7401 * 7402 * parameters configured: 7403 * - HC configuration 7404 * - Queue's CDU context 7405 */ 7406static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp, 7407 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) 7408{ 7409 7410 u8 cos; 7411 /* FCoE Queue uses Default SB, thus has no HC capabilities */ 7412 if (!IS_FCOE_FP(fp)) { 7413 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); 7414 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); 7415 7416 /* If HC is supporterd, enable host coalescing in the transition 7417 * to INIT state. 7418 */ 7419 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); 7420 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); 7421 7422 /* HC rate */ 7423 init_params->rx.hc_rate = bp->rx_ticks ? 7424 (1000000 / bp->rx_ticks) : 0; 7425 init_params->tx.hc_rate = bp->tx_ticks ? 7426 (1000000 / bp->tx_ticks) : 0; 7427 7428 /* FW SB ID */ 7429 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = 7430 fp->fw_sb_id; 7431 7432 /* 7433 * CQ index among the SB indices: FCoE clients uses the default 7434 * SB, therefore it's different. 7435 */ 7436 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 7437 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 7438 } 7439 7440 /* set maximum number of COSs supported by this queue */ 7441 init_params->max_cos = fp->max_cos; 7442 7443 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n", 7444 fp->index, init_params->max_cos); 7445 7446 /* set the context pointers queue object */ 7447 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) 7448 init_params->cxts[cos] = 7449 &bp->context.vcxt[fp->txdata[cos].cid].eth; 7450} 7451 7452int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7453 struct bnx2x_queue_state_params *q_params, 7454 struct bnx2x_queue_setup_tx_only_params *tx_only_params, 7455 int tx_index, bool leading) 7456{ 7457 memset(tx_only_params, 0, sizeof(*tx_only_params)); 7458 7459 /* Set the command */ 7460 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 7461 7462 /* Set tx-only QUEUE flags: don't zero statistics */ 7463 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); 7464 7465 /* choose the index of the cid to send the slow path on */ 7466 tx_only_params->cid_index = tx_index; 7467 7468 /* Set general TX_ONLY_SETUP parameters */ 7469 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); 7470 7471 /* Set Tx TX_ONLY_SETUP parameters */ 7472 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 7473 7474 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:" 7475 "cos %d, primary cid %d, cid %d, " 7476 "client id %d, sp-client id %d, flags %lx\n", 7477 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 7478 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 7479 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 7480 7481 /* send the ramrod */ 7482 return bnx2x_queue_state_change(bp, q_params); 7483} 7484 7485 7486/** 7487 * bnx2x_setup_queue - setup queue 7488 * 7489 * @bp: driver handle 7490 * @fp: pointer to fastpath 7491 * @leading: is leading 7492 * 7493 * This function performs 2 steps in a Queue state machine 7494 * actually: 1) RESET->INIT 2) INIT->SETUP 7495 */ 7496 7497int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7498 bool leading) 7499{ 7500 struct bnx2x_queue_state_params q_params = {0}; 7501 struct bnx2x_queue_setup_params *setup_params = 7502 &q_params.params.setup; 7503 struct bnx2x_queue_setup_tx_only_params *tx_only_params = 7504 &q_params.params.tx_only; 7505 int rc; 7506 u8 tx_index; 7507 7508 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index); 7509 7510 /* reset IGU state skip FCoE L2 queue */ 7511 if (!IS_FCOE_FP(fp)) 7512 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, 7513 IGU_INT_ENABLE, 0); 7514 7515 q_params.q_obj = &fp->q_obj; 7516 /* We want to wait for completion in this context */ 7517 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7518 7519 /* Prepare the INIT parameters */ 7520 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); 7521 7522 /* Set the command */ 7523 q_params.cmd = BNX2X_Q_CMD_INIT; 7524 7525 /* Change the state to INIT */ 7526 rc = bnx2x_queue_state_change(bp, &q_params); 7527 if (rc) { 7528 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); 7529 return rc; 7530 } 7531 7532 DP(BNX2X_MSG_SP, "init complete\n"); 7533 7534 7535 /* Now move the Queue to the SETUP state... */ 7536 memset(setup_params, 0, sizeof(*setup_params)); 7537 7538 /* Set QUEUE flags */ 7539 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); 7540 7541 /* Set general SETUP parameters */ 7542 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, 7543 FIRST_TX_COS_INDEX); 7544 7545 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, 7546 &setup_params->rxq_params); 7547 7548 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, 7549 FIRST_TX_COS_INDEX); 7550 7551 /* Set the command */ 7552 q_params.cmd = BNX2X_Q_CMD_SETUP; 7553 7554 /* Change the state to SETUP */ 7555 rc = bnx2x_queue_state_change(bp, &q_params); 7556 if (rc) { 7557 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); 7558 return rc; 7559 } 7560 7561 /* loop through the relevant tx-only indices */ 7562 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7563 tx_index < fp->max_cos; 7564 tx_index++) { 7565 7566 /* prepare and send tx-only ramrod*/ 7567 rc = bnx2x_setup_tx_only(bp, fp, &q_params, 7568 tx_only_params, tx_index, leading); 7569 if (rc) { 7570 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", 7571 fp->index, tx_index); 7572 return rc; 7573 } 7574 } 7575 7576 return rc; 7577} 7578 7579static int bnx2x_stop_queue(struct bnx2x *bp, int index) 7580{ 7581 struct bnx2x_fastpath *fp = &bp->fp[index]; 7582 struct bnx2x_fp_txdata *txdata; 7583 struct bnx2x_queue_state_params q_params = {0}; 7584 int rc, tx_index; 7585 7586 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid); 7587 7588 q_params.q_obj = &fp->q_obj; 7589 /* We want to wait for completion in this context */ 7590 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7591 7592 7593 /* close tx-only connections */ 7594 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7595 tx_index < fp->max_cos; 7596 tx_index++){ 7597 7598 /* ascertain this is a normal queue*/ 7599 txdata = &fp->txdata[tx_index]; 7600 7601 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n", 7602 txdata->txq_index); 7603 7604 /* send halt terminate on tx-only connection */ 7605 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7606 memset(&q_params.params.terminate, 0, 7607 sizeof(q_params.params.terminate)); 7608 q_params.params.terminate.cid_index = tx_index; 7609 7610 rc = bnx2x_queue_state_change(bp, &q_params); 7611 if (rc) 7612 return rc; 7613 7614 /* send halt terminate on tx-only connection */ 7615 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7616 memset(&q_params.params.cfc_del, 0, 7617 sizeof(q_params.params.cfc_del)); 7618 q_params.params.cfc_del.cid_index = tx_index; 7619 rc = bnx2x_queue_state_change(bp, &q_params); 7620 if (rc) 7621 return rc; 7622 } 7623 /* Stop the primary connection: */ 7624 /* ...halt the connection */ 7625 q_params.cmd = BNX2X_Q_CMD_HALT; 7626 rc = bnx2x_queue_state_change(bp, &q_params); 7627 if (rc) 7628 return rc; 7629 7630 /* ...terminate the connection */ 7631 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7632 memset(&q_params.params.terminate, 0, 7633 sizeof(q_params.params.terminate)); 7634 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 7635 rc = bnx2x_queue_state_change(bp, &q_params); 7636 if (rc) 7637 return rc; 7638 /* ...delete cfc entry */ 7639 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7640 memset(&q_params.params.cfc_del, 0, 7641 sizeof(q_params.params.cfc_del)); 7642 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 7643 return bnx2x_queue_state_change(bp, &q_params); 7644} 7645 7646 7647static void bnx2x_reset_func(struct bnx2x *bp) 7648{ 7649 int port = BP_PORT(bp); 7650 int func = BP_FUNC(bp); 7651 int i; 7652 7653 /* Disable the function in the FW */ 7654 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 7655 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 7656 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 7657 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 7658 7659 /* FP SBs */ 7660 for_each_eth_queue(bp, i) { 7661 struct bnx2x_fastpath *fp = &bp->fp[i]; 7662 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7663 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 7664 SB_DISABLED); 7665 } 7666 7667#ifdef BCM_CNIC 7668 /* CNIC SB */ 7669 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7670 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), 7671 SB_DISABLED); 7672#endif 7673 /* SP SB */ 7674 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7675 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 7676 SB_DISABLED); 7677 7678 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) 7679 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 7680 0); 7681 7682 /* Configure IGU */ 7683 if (bp->common.int_block == INT_BLOCK_HC) { 7684 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7685 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7686 } else { 7687 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 7688 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 7689 } 7690 7691#ifdef BCM_CNIC 7692 /* Disable Timer scan */ 7693 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 7694 /* 7695 * Wait for at least 10ms and up to 2 second for the timers scan to 7696 * complete 7697 */ 7698 for (i = 0; i < 200; i++) { 7699 msleep(10); 7700 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) 7701 break; 7702 } 7703#endif 7704 /* Clear ILT */ 7705 bnx2x_clear_func_ilt(bp, func); 7706 7707 /* Timers workaround bug for E2: if this is vnic-3, 7708 * we need to set the entire ilt range for this timers. 7709 */ 7710 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { 7711 struct ilt_client_info ilt_cli; 7712 /* use dummy TM client */ 7713 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 7714 ilt_cli.start = 0; 7715 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 7716 ilt_cli.client_num = ILT_CLIENT_TM; 7717 7718 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); 7719 } 7720 7721 /* this assumes that reset_port() called before reset_func()*/ 7722 if (!CHIP_IS_E1x(bp)) 7723 bnx2x_pf_disable(bp); 7724 7725 bp->dmae_ready = 0; 7726} 7727 7728static void bnx2x_reset_port(struct bnx2x *bp) 7729{ 7730 int port = BP_PORT(bp); 7731 u32 val; 7732 7733 /* Reset physical Link */ 7734 bnx2x__link_reset(bp); 7735 7736 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 7737 7738 /* Do not rcv packets to BRB */ 7739 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 7740 /* Do not direct rcv packets that are not for MCP to the BRB */ 7741 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 7742 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 7743 7744 /* Configure AEU */ 7745 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 7746 7747 msleep(100); 7748 /* Check for BRB port occupancy */ 7749 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 7750 if (val) 7751 DP(NETIF_MSG_IFDOWN, 7752 "BRB1 is not empty %d blocks are occupied\n", val); 7753 7754 /* TODO: Close Doorbell port? */ 7755} 7756 7757static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) 7758{ 7759 struct bnx2x_func_state_params func_params = {0}; 7760 7761 /* Prepare parameters for function state transitions */ 7762 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7763 7764 func_params.f_obj = &bp->func_obj; 7765 func_params.cmd = BNX2X_F_CMD_HW_RESET; 7766 7767 func_params.params.hw_init.load_phase = load_code; 7768 7769 return bnx2x_func_state_change(bp, &func_params); 7770} 7771 7772static inline int bnx2x_func_stop(struct bnx2x *bp) 7773{ 7774 struct bnx2x_func_state_params func_params = {0}; 7775 int rc; 7776 7777 /* Prepare parameters for function state transitions */ 7778 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7779 func_params.f_obj = &bp->func_obj; 7780 func_params.cmd = BNX2X_F_CMD_STOP; 7781 7782 /* 7783 * Try to stop the function the 'good way'. If fails (in case 7784 * of a parity error during bnx2x_chip_cleanup()) and we are 7785 * not in a debug mode, perform a state transaction in order to 7786 * enable further HW_RESET transaction. 7787 */ 7788 rc = bnx2x_func_state_change(bp, &func_params); 7789 if (rc) { 7790#ifdef BNX2X_STOP_ON_ERROR 7791 return rc; 7792#else 7793 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry " 7794 "transaction\n"); 7795 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 7796 return bnx2x_func_state_change(bp, &func_params); 7797#endif 7798 } 7799 7800 return 0; 7801} 7802 7803/** 7804 * bnx2x_send_unload_req - request unload mode from the MCP. 7805 * 7806 * @bp: driver handle 7807 * @unload_mode: requested function's unload mode 7808 * 7809 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 7810 */ 7811u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 7812{ 7813 u32 reset_code = 0; 7814 int port = BP_PORT(bp); 7815 7816 /* Select the UNLOAD request mode */ 7817 if (unload_mode == UNLOAD_NORMAL) 7818 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7819 7820 else if (bp->flags & NO_WOL_FLAG) 7821 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 7822 7823 else if (bp->wol) { 7824 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 7825 u8 *mac_addr = bp->dev->dev_addr; 7826 u32 val; 7827 u16 pmc; 7828 7829 /* The mac address is written to entries 1-4 to 7830 * preserve entry 0 which is used by the PMF 7831 */ 7832 u8 entry = (BP_VN(bp) + 1)*8; 7833 7834 val = (mac_addr[0] << 8) | mac_addr[1]; 7835 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 7836 7837 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 7838 (mac_addr[4] << 8) | mac_addr[5]; 7839 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 7840 7841 /* Enable the PME and clear the status */ 7842 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); 7843 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; 7844 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); 7845 7846 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 7847 7848 } else 7849 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7850 7851 /* Send the request to the MCP */ 7852 if (!BP_NOMCP(bp)) 7853 reset_code = bnx2x_fw_command(bp, reset_code, 0); 7854 else { 7855 int path = BP_PATH(bp); 7856 7857 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] " 7858 "%d, %d, %d\n", 7859 path, load_count[path][0], load_count[path][1], 7860 load_count[path][2]); 7861 load_count[path][0]--; 7862 load_count[path][1 + port]--; 7863 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] " 7864 "%d, %d, %d\n", 7865 path, load_count[path][0], load_count[path][1], 7866 load_count[path][2]); 7867 if (load_count[path][0] == 0) 7868 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 7869 else if (load_count[path][1 + port] == 0) 7870 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 7871 else 7872 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 7873 } 7874 7875 return reset_code; 7876} 7877 7878/** 7879 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 7880 * 7881 * @bp: driver handle 7882 */ 7883void bnx2x_send_unload_done(struct bnx2x *bp) 7884{ 7885 /* Report UNLOAD_DONE to MCP */ 7886 if (!BP_NOMCP(bp)) 7887 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 7888} 7889 7890static inline int bnx2x_func_wait_started(struct bnx2x *bp) 7891{ 7892 int tout = 50; 7893 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 7894 7895 if (!bp->port.pmf) 7896 return 0; 7897 7898 /* 7899 * (assumption: No Attention from MCP at this stage) 7900 * PMF probably in the middle of TXdisable/enable transaction 7901 * 1. Sync IRS for default SB 7902 * 2. Sync SP queue - this guarantes us that attention handling started 7903 * 3. Wait, that TXdisable/enable transaction completes 7904 * 7905 * 1+2 guranty that if DCBx attention was scheduled it already changed 7906 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy 7907 * received complettion for the transaction the state is TX_STOPPED. 7908 * State will return to STARTED after completion of TX_STOPPED-->STARTED 7909 * transaction. 7910 */ 7911 7912 /* make sure default SB ISR is done */ 7913 if (msix) 7914 synchronize_irq(bp->msix_table[0].vector); 7915 else 7916 synchronize_irq(bp->pdev->irq); 7917 7918 flush_workqueue(bnx2x_wq); 7919 7920 while (bnx2x_func_get_state(bp, &bp->func_obj) != 7921 BNX2X_F_STATE_STARTED && tout--) 7922 msleep(20); 7923 7924 if (bnx2x_func_get_state(bp, &bp->func_obj) != 7925 BNX2X_F_STATE_STARTED) { 7926#ifdef BNX2X_STOP_ON_ERROR 7927 return -EBUSY; 7928#else 7929 /* 7930 * Failed to complete the transaction in a "good way" 7931 * Force both transactions with CLR bit 7932 */ 7933 struct bnx2x_func_state_params func_params = {0}; 7934 7935 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! " 7936 "Forcing STARTED-->TX_ST0PPED-->STARTED\n"); 7937 7938 func_params.f_obj = &bp->func_obj; 7939 __set_bit(RAMROD_DRV_CLR_ONLY, 7940 &func_params.ramrod_flags); 7941 7942 /* STARTED-->TX_ST0PPED */ 7943 func_params.cmd = BNX2X_F_CMD_TX_STOP; 7944 bnx2x_func_state_change(bp, &func_params); 7945 7946 /* TX_ST0PPED-->STARTED */ 7947 func_params.cmd = BNX2X_F_CMD_TX_START; 7948 return bnx2x_func_state_change(bp, &func_params); 7949#endif 7950 } 7951 7952 return 0; 7953} 7954 7955void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) 7956{ 7957 int port = BP_PORT(bp); 7958 int i, rc = 0; 7959 u8 cos; 7960 struct bnx2x_mcast_ramrod_params rparam = {0}; 7961 u32 reset_code; 7962 7963 /* Wait until tx fastpath tasks complete */ 7964 for_each_tx_queue(bp, i) { 7965 struct bnx2x_fastpath *fp = &bp->fp[i]; 7966 7967 for_each_cos_in_tx_queue(fp, cos) 7968 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]); 7969#ifdef BNX2X_STOP_ON_ERROR 7970 if (rc) 7971 return; 7972#endif 7973 } 7974 7975 /* Give HW time to discard old tx messages */ 7976 usleep_range(1000, 1000); 7977 7978 /* Clean all ETH MACs */ 7979 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false); 7980 if (rc < 0) 7981 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); 7982 7983 /* Clean up UC list */ 7984 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, 7985 true); 7986 if (rc < 0) 7987 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: " 7988 "%d\n", rc); 7989 7990 /* Disable LLH */ 7991 if (!CHIP_IS_E1(bp)) 7992 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 7993 7994 /* Set "drop all" (stop Rx). 7995 * We need to take a netif_addr_lock() here in order to prevent 7996 * a race between the completion code and this code. 7997 */ 7998 netif_addr_lock_bh(bp->dev); 7999 /* Schedule the rx_mode command */ 8000 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 8001 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 8002 else 8003 bnx2x_set_storm_rx_mode(bp); 8004 8005 /* Cleanup multicast configuration */ 8006 rparam.mcast_obj = &bp->mcast_obj; 8007 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 8008 if (rc < 0) 8009 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); 8010 8011 netif_addr_unlock_bh(bp->dev); 8012 8013 8014 8015 /* 8016 * Send the UNLOAD_REQUEST to the MCP. This will return if 8017 * this function should perform FUNC, PORT or COMMON HW 8018 * reset. 8019 */ 8020 reset_code = bnx2x_send_unload_req(bp, unload_mode); 8021 8022 /* 8023 * (assumption: No Attention from MCP at this stage) 8024 * PMF probably in the middle of TXdisable/enable transaction 8025 */ 8026 rc = bnx2x_func_wait_started(bp); 8027 if (rc) { 8028 BNX2X_ERR("bnx2x_func_wait_started failed\n"); 8029#ifdef BNX2X_STOP_ON_ERROR 8030 return; 8031#endif 8032 } 8033 8034 /* Close multi and leading connections 8035 * Completions for ramrods are collected in a synchronous way 8036 */ 8037 for_each_queue(bp, i) 8038 if (bnx2x_stop_queue(bp, i)) 8039#ifdef BNX2X_STOP_ON_ERROR 8040 return; 8041#else 8042 goto unload_error; 8043#endif 8044 /* If SP settings didn't get completed so far - something 8045 * very wrong has happen. 8046 */ 8047 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) 8048 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); 8049 8050#ifndef BNX2X_STOP_ON_ERROR 8051unload_error: 8052#endif 8053 rc = bnx2x_func_stop(bp); 8054 if (rc) { 8055 BNX2X_ERR("Function stop failed!\n"); 8056#ifdef BNX2X_STOP_ON_ERROR 8057 return; 8058#endif 8059 } 8060 8061 /* Disable HW interrupts, NAPI */ 8062 bnx2x_netif_stop(bp, 1); 8063 8064 /* Release IRQs */ 8065 bnx2x_free_irq(bp); 8066 8067 /* Reset the chip */ 8068 rc = bnx2x_reset_hw(bp, reset_code); 8069 if (rc) 8070 BNX2X_ERR("HW_RESET failed\n"); 8071 8072 8073 /* Report UNLOAD_DONE to MCP */ 8074 bnx2x_send_unload_done(bp); 8075} 8076 8077void bnx2x_disable_close_the_gate(struct bnx2x *bp) 8078{ 8079 u32 val; 8080 8081 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n"); 8082 8083 if (CHIP_IS_E1(bp)) { 8084 int port = BP_PORT(bp); 8085 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8086 MISC_REG_AEU_MASK_ATTN_FUNC_0; 8087 8088 val = REG_RD(bp, addr); 8089 val &= ~(0x300); 8090 REG_WR(bp, addr, val); 8091 } else { 8092 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); 8093 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 8094 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 8095 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); 8096 } 8097} 8098 8099/* Close gates #2, #3 and #4: */ 8100static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 8101{ 8102 u32 val; 8103 8104 /* Gates #2 and #4a are closed/opened for "not E1" only */ 8105 if (!CHIP_IS_E1(bp)) { 8106 /* #4 */ 8107 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 8108 /* #2 */ 8109 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 8110 } 8111 8112 /* #3 */ 8113 if (CHIP_IS_E1x(bp)) { 8114 /* Prevent interrupts from HC on both ports */ 8115 val = REG_RD(bp, HC_REG_CONFIG_1); 8116 REG_WR(bp, HC_REG_CONFIG_1, 8117 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 8118 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 8119 8120 val = REG_RD(bp, HC_REG_CONFIG_0); 8121 REG_WR(bp, HC_REG_CONFIG_0, 8122 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 8123 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 8124 } else { 8125 /* Prevent incomming interrupts in IGU */ 8126 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 8127 8128 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, 8129 (!close) ? 8130 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 8131 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 8132 } 8133 8134 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n", 8135 close ? "closing" : "opening"); 8136 mmiowb(); 8137} 8138 8139#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ 8140 8141static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) 8142{ 8143 /* Do some magic... */ 8144 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8145 *magic_val = val & SHARED_MF_CLP_MAGIC; 8146 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 8147} 8148 8149/** 8150 * bnx2x_clp_reset_done - restore the value of the `magic' bit. 8151 * 8152 * @bp: driver handle 8153 * @magic_val: old value of the `magic' bit. 8154 */ 8155static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 8156{ 8157 /* Restore the `magic' bit value... */ 8158 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8159 MF_CFG_WR(bp, shared_mf_config.clp_mb, 8160 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 8161} 8162 8163/** 8164 * bnx2x_reset_mcp_prep - prepare for MCP reset. 8165 * 8166 * @bp: driver handle 8167 * @magic_val: old value of 'magic' bit. 8168 * 8169 * Takes care of CLP configurations. 8170 */ 8171static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 8172{ 8173 u32 shmem; 8174 u32 validity_offset; 8175 8176 DP(NETIF_MSG_HW, "Starting\n"); 8177 8178 /* Set `magic' bit in order to save MF config */ 8179 if (!CHIP_IS_E1(bp)) 8180 bnx2x_clp_reset_prep(bp, magic_val); 8181 8182 /* Get shmem offset */ 8183 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8184 validity_offset = offsetof(struct shmem_region, validity_map[0]); 8185 8186 /* Clear validity map flags */ 8187 if (shmem > 0) 8188 REG_WR(bp, shmem + validity_offset, 0); 8189} 8190 8191#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 8192#define MCP_ONE_TIMEOUT 100 /* 100 ms */ 8193 8194/** 8195 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT 8196 * 8197 * @bp: driver handle 8198 */ 8199static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) 8200{ 8201 /* special handling for emulation and FPGA, 8202 wait 10 times longer */ 8203 if (CHIP_REV_IS_SLOW(bp)) 8204 msleep(MCP_ONE_TIMEOUT*10); 8205 else 8206 msleep(MCP_ONE_TIMEOUT); 8207} 8208 8209/* 8210 * initializes bp->common.shmem_base and waits for validity signature to appear 8211 */ 8212static int bnx2x_init_shmem(struct bnx2x *bp) 8213{ 8214 int cnt = 0; 8215 u32 val = 0; 8216 8217 do { 8218 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8219 if (bp->common.shmem_base) { 8220 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 8221 if (val & SHR_MEM_VALIDITY_MB) 8222 return 0; 8223 } 8224 8225 bnx2x_mcp_wait_one(bp); 8226 8227 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 8228 8229 BNX2X_ERR("BAD MCP validity signature\n"); 8230 8231 return -ENODEV; 8232} 8233 8234static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 8235{ 8236 int rc = bnx2x_init_shmem(bp); 8237 8238 /* Restore the `magic' bit value */ 8239 if (!CHIP_IS_E1(bp)) 8240 bnx2x_clp_reset_done(bp, magic_val); 8241 8242 return rc; 8243} 8244 8245static void bnx2x_pxp_prep(struct bnx2x *bp) 8246{ 8247 if (!CHIP_IS_E1(bp)) { 8248 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 8249 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 8250 mmiowb(); 8251 } 8252} 8253 8254/* 8255 * Reset the whole chip except for: 8256 * - PCIE core 8257 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by 8258 * one reset bit) 8259 * - IGU 8260 * - MISC (including AEU) 8261 * - GRC 8262 * - RBCN, RBCP 8263 */ 8264static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) 8265{ 8266 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 8267 u32 global_bits2, stay_reset2; 8268 8269 /* 8270 * Bits that have to be set in reset_mask2 if we want to reset 'global' 8271 * (per chip) blocks. 8272 */ 8273 global_bits2 = 8274 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 8275 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 8276 8277 /* Don't reset the following blocks */ 8278 not_reset_mask1 = 8279 MISC_REGISTERS_RESET_REG_1_RST_HC | 8280 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 8281 MISC_REGISTERS_RESET_REG_1_RST_PXP; 8282 8283 not_reset_mask2 = 8284 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 8285 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 8286 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 8287 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 8288 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 8289 MISC_REGISTERS_RESET_REG_2_RST_GRC | 8290 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 8291 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 8292 MISC_REGISTERS_RESET_REG_2_RST_ATC | 8293 MISC_REGISTERS_RESET_REG_2_PGLC; 8294 8295 /* 8296 * Keep the following blocks in reset: 8297 * - all xxMACs are handled by the bnx2x_link code. 8298 */ 8299 stay_reset2 = 8300 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 8301 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 8302 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 8303 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 8304 MISC_REGISTERS_RESET_REG_2_UMAC0 | 8305 MISC_REGISTERS_RESET_REG_2_UMAC1 | 8306 MISC_REGISTERS_RESET_REG_2_XMAC | 8307 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 8308 8309 /* Full reset masks according to the chip */ 8310 reset_mask1 = 0xffffffff; 8311 8312 if (CHIP_IS_E1(bp)) 8313 reset_mask2 = 0xffff; 8314 else if (CHIP_IS_E1H(bp)) 8315 reset_mask2 = 0x1ffff; 8316 else if (CHIP_IS_E2(bp)) 8317 reset_mask2 = 0xfffff; 8318 else /* CHIP_IS_E3 */ 8319 reset_mask2 = 0x3ffffff; 8320 8321 /* Don't reset global blocks unless we need to */ 8322 if (!global) 8323 reset_mask2 &= ~global_bits2; 8324 8325 /* 8326 * In case of attention in the QM, we need to reset PXP 8327 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 8328 * because otherwise QM reset would release 'close the gates' shortly 8329 * before resetting the PXP, then the PSWRQ would send a write 8330 * request to PGLUE. Then when PXP is reset, PGLUE would try to 8331 * read the payload data from PSWWR, but PSWWR would not 8332 * respond. The write queue in PGLUE would stuck, dmae commands 8333 * would not return. Therefore it's important to reset the second 8334 * reset register (containing the 8335 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 8336 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 8337 * bit). 8338 */ 8339 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8340 reset_mask2 & (~not_reset_mask2)); 8341 8342 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8343 reset_mask1 & (~not_reset_mask1)); 8344 8345 barrier(); 8346 mmiowb(); 8347 8348 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 8349 reset_mask2 & (~stay_reset2)); 8350 8351 barrier(); 8352 mmiowb(); 8353 8354 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 8355 mmiowb(); 8356} 8357 8358/** 8359 * bnx2x_er_poll_igu_vq - poll for pending writes bit. 8360 * It should get cleared in no more than 1s. 8361 * 8362 * @bp: driver handle 8363 * 8364 * It should get cleared in no more than 1s. Returns 0 if 8365 * pending writes bit gets cleared. 8366 */ 8367static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) 8368{ 8369 u32 cnt = 1000; 8370 u32 pend_bits = 0; 8371 8372 do { 8373 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); 8374 8375 if (pend_bits == 0) 8376 break; 8377 8378 usleep_range(1000, 1000); 8379 } while (cnt-- > 0); 8380 8381 if (cnt <= 0) { 8382 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", 8383 pend_bits); 8384 return -EBUSY; 8385 } 8386 8387 return 0; 8388} 8389 8390static int bnx2x_process_kill(struct bnx2x *bp, bool global) 8391{ 8392 int cnt = 1000; 8393 u32 val = 0; 8394 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 8395 8396 8397 /* Empty the Tetris buffer, wait for 1s */ 8398 do { 8399 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); 8400 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); 8401 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); 8402 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); 8403 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); 8404 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 8405 ((port_is_idle_0 & 0x1) == 0x1) && 8406 ((port_is_idle_1 & 0x1) == 0x1) && 8407 (pgl_exp_rom2 == 0xffffffff)) 8408 break; 8409 usleep_range(1000, 1000); 8410 } while (cnt-- > 0); 8411 8412 if (cnt <= 0) { 8413 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there" 8414 " are still" 8415 " outstanding read requests after 1s!\n"); 8416 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x," 8417 " port_is_idle_0=0x%08x," 8418 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 8419 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 8420 pgl_exp_rom2); 8421 return -EAGAIN; 8422 } 8423 8424 barrier(); 8425 8426 /* Close gates #2, #3 and #4 */ 8427 bnx2x_set_234_gates(bp, true); 8428 8429 /* Poll for IGU VQs for 57712 and newer chips */ 8430 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) 8431 return -EAGAIN; 8432 8433 8434 /* TBD: Indicate that "process kill" is in progress to MCP */ 8435 8436 /* Clear "unprepared" bit */ 8437 REG_WR(bp, MISC_REG_UNPREPARED, 0); 8438 barrier(); 8439 8440 /* Make sure all is written to the chip before the reset */ 8441 mmiowb(); 8442 8443 /* Wait for 1ms to empty GLUE and PCI-E core queues, 8444 * PSWHST, GRC and PSWRD Tetris buffer. 8445 */ 8446 usleep_range(1000, 1000); 8447 8448 /* Prepare to chip reset: */ 8449 /* MCP */ 8450 if (global) 8451 bnx2x_reset_mcp_prep(bp, &val); 8452 8453 /* PXP */ 8454 bnx2x_pxp_prep(bp); 8455 barrier(); 8456 8457 /* reset the chip */ 8458 bnx2x_process_kill_chip_reset(bp, global); 8459 barrier(); 8460 8461 /* Recover after reset: */ 8462 /* MCP */ 8463 if (global && bnx2x_reset_mcp_comp(bp, val)) 8464 return -EAGAIN; 8465 8466 /* TBD: Add resetting the NO_MCP mode DB here */ 8467 8468 /* PXP */ 8469 bnx2x_pxp_prep(bp); 8470 8471 /* Open the gates #2, #3 and #4 */ 8472 bnx2x_set_234_gates(bp, false); 8473 8474 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a 8475 * reset state, re-enable attentions. */ 8476 8477 return 0; 8478} 8479 8480int bnx2x_leader_reset(struct bnx2x *bp) 8481{ 8482 int rc = 0; 8483 bool global = bnx2x_reset_is_global(bp); 8484 u32 load_code; 8485 8486 /* if not going to reset MCP - load "fake" driver to reset HW while 8487 * driver is owner of the HW 8488 */ 8489 if (!global && !BP_NOMCP(bp)) { 8490 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 0); 8491 if (!load_code) { 8492 BNX2X_ERR("MCP response failure, aborting\n"); 8493 rc = -EAGAIN; 8494 goto exit_leader_reset; 8495 } 8496 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && 8497 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { 8498 BNX2X_ERR("MCP unexpected resp, aborting\n"); 8499 rc = -EAGAIN; 8500 goto exit_leader_reset2; 8501 } 8502 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); 8503 if (!load_code) { 8504 BNX2X_ERR("MCP response failure, aborting\n"); 8505 rc = -EAGAIN; 8506 goto exit_leader_reset2; 8507 } 8508 } 8509 8510 /* Try to recover after the failure */ 8511 if (bnx2x_process_kill(bp, global)) { 8512 netdev_err(bp->dev, "Something bad had happen on engine %d! " 8513 "Aii!\n", BP_PATH(bp)); 8514 rc = -EAGAIN; 8515 goto exit_leader_reset2; 8516 } 8517 8518 /* 8519 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver 8520 * state. 8521 */ 8522 bnx2x_set_reset_done(bp); 8523 if (global) 8524 bnx2x_clear_reset_global(bp); 8525 8526exit_leader_reset2: 8527 /* unload "fake driver" if it was loaded */ 8528 if (!global && !BP_NOMCP(bp)) { 8529 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); 8530 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 8531 } 8532exit_leader_reset: 8533 bp->is_leader = 0; 8534 bnx2x_release_leader_lock(bp); 8535 smp_mb(); 8536 return rc; 8537} 8538 8539static inline void bnx2x_recovery_failed(struct bnx2x *bp) 8540{ 8541 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); 8542 8543 /* Disconnect this device */ 8544 netif_device_detach(bp->dev); 8545 8546 /* 8547 * Block ifup for all function on this engine until "process kill" 8548 * or power cycle. 8549 */ 8550 bnx2x_set_reset_in_progress(bp); 8551 8552 /* Shut down the power */ 8553 bnx2x_set_power_state(bp, PCI_D3hot); 8554 8555 bp->recovery_state = BNX2X_RECOVERY_FAILED; 8556 8557 smp_mb(); 8558} 8559 8560/* 8561 * Assumption: runs under rtnl lock. This together with the fact 8562 * that it's called only from bnx2x_sp_rtnl() ensure that it 8563 * will never be called when netif_running(bp->dev) is false. 8564 */ 8565static void bnx2x_parity_recover(struct bnx2x *bp) 8566{ 8567 bool global = false; 8568 u32 error_recovered, error_unrecovered; 8569 bool is_parity; 8570 8571 DP(NETIF_MSG_HW, "Handling parity\n"); 8572 while (1) { 8573 switch (bp->recovery_state) { 8574 case BNX2X_RECOVERY_INIT: 8575 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 8576 is_parity = bnx2x_chk_parity_attn(bp, &global, false); 8577 WARN_ON(!is_parity); 8578 8579 /* Try to get a LEADER_LOCK HW lock */ 8580 if (bnx2x_trylock_leader_lock(bp)) { 8581 bnx2x_set_reset_in_progress(bp); 8582 /* 8583 * Check if there is a global attention and if 8584 * there was a global attention, set the global 8585 * reset bit. 8586 */ 8587 8588 if (global) 8589 bnx2x_set_reset_global(bp); 8590 8591 bp->is_leader = 1; 8592 } 8593 8594 /* Stop the driver */ 8595 /* If interface has been removed - break */ 8596 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) 8597 return; 8598 8599 bp->recovery_state = BNX2X_RECOVERY_WAIT; 8600 8601 /* Ensure "is_leader", MCP command sequence and 8602 * "recovery_state" update values are seen on other 8603 * CPUs. 8604 */ 8605 smp_mb(); 8606 break; 8607 8608 case BNX2X_RECOVERY_WAIT: 8609 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 8610 if (bp->is_leader) { 8611 int other_engine = BP_PATH(bp) ? 0 : 1; 8612 bool other_load_status = 8613 bnx2x_get_load_status(bp, other_engine); 8614 bool load_status = 8615 bnx2x_get_load_status(bp, BP_PATH(bp)); 8616 global = bnx2x_reset_is_global(bp); 8617 8618 /* 8619 * In case of a parity in a global block, let 8620 * the first leader that performs a 8621 * leader_reset() reset the global blocks in 8622 * order to clear global attentions. Otherwise 8623 * the the gates will remain closed for that 8624 * engine. 8625 */ 8626 if (load_status || 8627 (global && other_load_status)) { 8628 /* Wait until all other functions get 8629 * down. 8630 */ 8631 schedule_delayed_work(&bp->sp_rtnl_task, 8632 HZ/10); 8633 return; 8634 } else { 8635 /* If all other functions got down - 8636 * try to bring the chip back to 8637 * normal. In any case it's an exit 8638 * point for a leader. 8639 */ 8640 if (bnx2x_leader_reset(bp)) { 8641 bnx2x_recovery_failed(bp); 8642 return; 8643 } 8644 8645 /* If we are here, means that the 8646 * leader has succeeded and doesn't 8647 * want to be a leader any more. Try 8648 * to continue as a none-leader. 8649 */ 8650 break; 8651 } 8652 } else { /* non-leader */ 8653 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { 8654 /* Try to get a LEADER_LOCK HW lock as 8655 * long as a former leader may have 8656 * been unloaded by the user or 8657 * released a leadership by another 8658 * reason. 8659 */ 8660 if (bnx2x_trylock_leader_lock(bp)) { 8661 /* I'm a leader now! Restart a 8662 * switch case. 8663 */ 8664 bp->is_leader = 1; 8665 break; 8666 } 8667 8668 schedule_delayed_work(&bp->sp_rtnl_task, 8669 HZ/10); 8670 return; 8671 8672 } else { 8673 /* 8674 * If there was a global attention, wait 8675 * for it to be cleared. 8676 */ 8677 if (bnx2x_reset_is_global(bp)) { 8678 schedule_delayed_work( 8679 &bp->sp_rtnl_task, 8680 HZ/10); 8681 return; 8682 } 8683 8684 error_recovered = 8685 bp->eth_stats.recoverable_error; 8686 error_unrecovered = 8687 bp->eth_stats.unrecoverable_error; 8688 bp->recovery_state = 8689 BNX2X_RECOVERY_NIC_LOADING; 8690 if (bnx2x_nic_load(bp, LOAD_NORMAL)) { 8691 error_unrecovered++; 8692 netdev_err(bp->dev, 8693 "Recovery failed. " 8694 "Power cycle " 8695 "needed\n"); 8696 /* Disconnect this device */ 8697 netif_device_detach(bp->dev); 8698 /* Shut down the power */ 8699 bnx2x_set_power_state( 8700 bp, PCI_D3hot); 8701 smp_mb(); 8702 } else { 8703 bp->recovery_state = 8704 BNX2X_RECOVERY_DONE; 8705 error_recovered++; 8706 smp_mb(); 8707 } 8708 bp->eth_stats.recoverable_error = 8709 error_recovered; 8710 bp->eth_stats.unrecoverable_error = 8711 error_unrecovered; 8712 8713 return; 8714 } 8715 } 8716 default: 8717 return; 8718 } 8719 } 8720} 8721 8722/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is 8723 * scheduled on a general queue in order to prevent a dead lock. 8724 */ 8725static void bnx2x_sp_rtnl_task(struct work_struct *work) 8726{ 8727 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); 8728 8729 rtnl_lock(); 8730 8731 if (!netif_running(bp->dev)) 8732 goto sp_rtnl_exit; 8733 8734 /* if stop on error is defined no recovery flows should be executed */ 8735#ifdef BNX2X_STOP_ON_ERROR 8736 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined " 8737 "so reset not done to allow debug dump,\n" 8738 "you will need to reboot when done\n"); 8739 goto sp_rtnl_not_reset; 8740#endif 8741 8742 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { 8743 /* 8744 * Clear all pending SP commands as we are going to reset the 8745 * function anyway. 8746 */ 8747 bp->sp_rtnl_state = 0; 8748 smp_mb(); 8749 8750 bnx2x_parity_recover(bp); 8751 8752 goto sp_rtnl_exit; 8753 } 8754 8755 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { 8756 /* 8757 * Clear all pending SP commands as we are going to reset the 8758 * function anyway. 8759 */ 8760 bp->sp_rtnl_state = 0; 8761 smp_mb(); 8762 8763 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 8764 bnx2x_nic_load(bp, LOAD_NORMAL); 8765 8766 goto sp_rtnl_exit; 8767 } 8768#ifdef BNX2X_STOP_ON_ERROR 8769sp_rtnl_not_reset: 8770#endif 8771 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) 8772 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); 8773 8774 /* 8775 * in case of fan failure we need to reset id if the "stop on error" 8776 * debug flag is set, since we trying to prevent permanent overheating 8777 * damage 8778 */ 8779 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { 8780 DP(BNX2X_MSG_SP, "fan failure detected. Unloading driver\n"); 8781 netif_device_detach(bp->dev); 8782 bnx2x_close(bp->dev); 8783 } 8784 8785sp_rtnl_exit: 8786 rtnl_unlock(); 8787} 8788 8789/* end of nic load/unload */ 8790 8791static void bnx2x_period_task(struct work_struct *work) 8792{ 8793 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); 8794 8795 if (!netif_running(bp->dev)) 8796 goto period_task_exit; 8797 8798 if (CHIP_REV_IS_SLOW(bp)) { 8799 BNX2X_ERR("period task called on emulation, ignoring\n"); 8800 goto period_task_exit; 8801 } 8802 8803 bnx2x_acquire_phy_lock(bp); 8804 /* 8805 * The barrier is needed to ensure the ordering between the writing to 8806 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and 8807 * the reading here. 8808 */ 8809 smp_mb(); 8810 if (bp->port.pmf) { 8811 bnx2x_period_func(&bp->link_params, &bp->link_vars); 8812 8813 /* Re-queue task in 1 sec */ 8814 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); 8815 } 8816 8817 bnx2x_release_phy_lock(bp); 8818period_task_exit: 8819 return; 8820} 8821 8822/* 8823 * Init service functions 8824 */ 8825 8826static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) 8827{ 8828 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; 8829 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; 8830 return base + (BP_ABS_FUNC(bp)) * stride; 8831} 8832 8833static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) 8834{ 8835 u32 reg = bnx2x_get_pretend_reg(bp); 8836 8837 /* Flush all outstanding writes */ 8838 mmiowb(); 8839 8840 /* Pretend to be function 0 */ 8841 REG_WR(bp, reg, 0); 8842 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ 8843 8844 /* From now we are in the "like-E1" mode */ 8845 bnx2x_int_disable(bp); 8846 8847 /* Flush all outstanding writes */ 8848 mmiowb(); 8849 8850 /* Restore the original function */ 8851 REG_WR(bp, reg, BP_ABS_FUNC(bp)); 8852 REG_RD(bp, reg); 8853} 8854 8855static inline void bnx2x_undi_int_disable(struct bnx2x *bp) 8856{ 8857 if (CHIP_IS_E1(bp)) 8858 bnx2x_int_disable(bp); 8859 else 8860 bnx2x_undi_int_disable_e1h(bp); 8861} 8862 8863static void __devinit bnx2x_undi_unload(struct bnx2x *bp) 8864{ 8865 u32 val; 8866 8867 /* possibly another driver is trying to reset the chip */ 8868 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8869 8870 /* check if doorbell queue is reset */ 8871 if (REG_RD(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET) 8872 & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { 8873 8874 /* 8875 * Check if it is the UNDI driver 8876 * UNDI driver initializes CID offset for normal bell to 0x7 8877 */ 8878 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 8879 if (val == 0x7) { 8880 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8881 /* save our pf_num */ 8882 int orig_pf_num = bp->pf_num; 8883 int port; 8884 u32 swap_en, swap_val, value; 8885 8886 /* clear the UNDI indication */ 8887 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 8888 8889 BNX2X_DEV_INFO("UNDI is active! reset device\n"); 8890 8891 /* try unload UNDI on port 0 */ 8892 bp->pf_num = 0; 8893 bp->fw_seq = 8894 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8895 DRV_MSG_SEQ_NUMBER_MASK); 8896 reset_code = bnx2x_fw_command(bp, reset_code, 0); 8897 8898 /* if UNDI is loaded on the other port */ 8899 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { 8900 8901 /* send "DONE" for previous unload */ 8902 bnx2x_fw_command(bp, 8903 DRV_MSG_CODE_UNLOAD_DONE, 0); 8904 8905 /* unload UNDI on port 1 */ 8906 bp->pf_num = 1; 8907 bp->fw_seq = 8908 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8909 DRV_MSG_SEQ_NUMBER_MASK); 8910 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8911 8912 bnx2x_fw_command(bp, reset_code, 0); 8913 } 8914 8915 bnx2x_undi_int_disable(bp); 8916 port = BP_PORT(bp); 8917 8918 /* close input traffic and wait for it */ 8919 /* Do not rcv packets to BRB */ 8920 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK : 8921 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0); 8922 /* Do not direct rcv packets that are not for MCP to 8923 * the BRB */ 8924 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 8925 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 8926 /* clear AEU */ 8927 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8928 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0); 8929 msleep(10); 8930 8931 /* save NIG port swap info */ 8932 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 8933 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 8934 /* reset device */ 8935 REG_WR(bp, 8936 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8937 0xd3ffffff); 8938 8939 value = 0x1400; 8940 if (CHIP_IS_E3(bp)) { 8941 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 8942 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 8943 } 8944 8945 REG_WR(bp, 8946 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8947 value); 8948 8949 /* take the NIG out of reset and restore swap values */ 8950 REG_WR(bp, 8951 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 8952 MISC_REGISTERS_RESET_REG_1_RST_NIG); 8953 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val); 8954 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en); 8955 8956 /* send unload done to the MCP */ 8957 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 8958 8959 /* restore our func and fw_seq */ 8960 bp->pf_num = orig_pf_num; 8961 } 8962 } 8963 8964 /* now it's safe to release the lock */ 8965 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8966} 8967 8968static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) 8969{ 8970 u32 val, val2, val3, val4, id, boot_mode; 8971 u16 pmc; 8972 8973 /* Get the chip revision id and number. */ 8974 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 8975 val = REG_RD(bp, MISC_REG_CHIP_NUM); 8976 id = ((val & 0xffff) << 16); 8977 val = REG_RD(bp, MISC_REG_CHIP_REV); 8978 id |= ((val & 0xf) << 12); 8979 val = REG_RD(bp, MISC_REG_CHIP_METAL); 8980 id |= ((val & 0xff) << 4); 8981 val = REG_RD(bp, MISC_REG_BOND_ID); 8982 id |= (val & 0xf); 8983 bp->common.chip_id = id; 8984 8985 /* Set doorbell size */ 8986 bp->db_size = (1 << BNX2X_DB_SHIFT); 8987 8988 if (!CHIP_IS_E1x(bp)) { 8989 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 8990 if ((val & 1) == 0) 8991 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); 8992 else 8993 val = (val >> 1) & 1; 8994 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : 8995 "2_PORT_MODE"); 8996 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : 8997 CHIP_2_PORT_MODE; 8998 8999 if (CHIP_MODE_IS_4_PORT(bp)) 9000 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ 9001 else 9002 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ 9003 } else { 9004 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ 9005 bp->pfid = bp->pf_num; /* 0..7 */ 9006 } 9007 9008 bp->link_params.chip_id = bp->common.chip_id; 9009 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 9010 9011 val = (REG_RD(bp, 0x2874) & 0x55); 9012 if ((bp->common.chip_id & 0x1) || 9013 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { 9014 bp->flags |= ONE_PORT_FLAG; 9015 BNX2X_DEV_INFO("single port device\n"); 9016 } 9017 9018 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); 9019 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << 9020 (val & MCPR_NVM_CFG4_FLASH_SIZE)); 9021 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 9022 bp->common.flash_size, bp->common.flash_size); 9023 9024 bnx2x_init_shmem(bp); 9025 9026 9027 9028 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? 9029 MISC_REG_GENERIC_CR_1 : 9030 MISC_REG_GENERIC_CR_0)); 9031 9032 bp->link_params.shmem_base = bp->common.shmem_base; 9033 bp->link_params.shmem2_base = bp->common.shmem2_base; 9034 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 9035 bp->common.shmem_base, bp->common.shmem2_base); 9036 9037 if (!bp->common.shmem_base) { 9038 BNX2X_DEV_INFO("MCP not active\n"); 9039 bp->flags |= NO_MCP_FLAG; 9040 return; 9041 } 9042 9043 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 9044 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 9045 9046 bp->link_params.hw_led_mode = ((bp->common.hw_config & 9047 SHARED_HW_CFG_LED_MODE_MASK) >> 9048 SHARED_HW_CFG_LED_MODE_SHIFT); 9049 9050 bp->link_params.feature_config_flags = 0; 9051 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); 9052 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) 9053 bp->link_params.feature_config_flags |= 9054 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 9055 else 9056 bp->link_params.feature_config_flags &= 9057 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 9058 9059 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 9060 bp->common.bc_ver = val; 9061 BNX2X_DEV_INFO("bc_ver %X\n", val); 9062 if (val < BNX2X_BC_VER) { 9063 /* for now only warn 9064 * later we might need to enforce this */ 9065 BNX2X_ERR("This driver needs bc_ver %X but found %X, " 9066 "please upgrade BC\n", BNX2X_BC_VER, val); 9067 } 9068 bp->link_params.feature_config_flags |= 9069 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 9070 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 9071 9072 bp->link_params.feature_config_flags |= 9073 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? 9074 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; 9075 9076 bp->link_params.feature_config_flags |= 9077 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? 9078 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; 9079 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? 9080 BC_SUPPORTS_PFC_STATS : 0; 9081 9082 boot_mode = SHMEM_RD(bp, 9083 dev_info.port_feature_config[BP_PORT(bp)].mba_config) & 9084 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; 9085 switch (boot_mode) { 9086 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: 9087 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; 9088 break; 9089 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: 9090 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; 9091 break; 9092 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: 9093 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; 9094 break; 9095 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: 9096 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; 9097 break; 9098 } 9099 9100 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); 9101 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; 9102 9103 BNX2X_DEV_INFO("%sWoL capable\n", 9104 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 9105 9106 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 9107 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 9108 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); 9109 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); 9110 9111 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", 9112 val, val2, val3, val4); 9113} 9114 9115#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 9116#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 9117 9118static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) 9119{ 9120 int pfid = BP_FUNC(bp); 9121 int igu_sb_id; 9122 u32 val; 9123 u8 fid, igu_sb_cnt = 0; 9124 9125 bp->igu_base_sb = 0xff; 9126 if (CHIP_INT_MODE_IS_BC(bp)) { 9127 int vn = BP_VN(bp); 9128 igu_sb_cnt = bp->igu_sb_cnt; 9129 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 9130 FP_SB_MAX_E1x; 9131 9132 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + 9133 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); 9134 9135 return; 9136 } 9137 9138 /* IGU in normal mode - read CAM */ 9139 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 9140 igu_sb_id++) { 9141 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 9142 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 9143 continue; 9144 fid = IGU_FID(val); 9145 if ((fid & IGU_FID_ENCODE_IS_PF)) { 9146 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) 9147 continue; 9148 if (IGU_VEC(val) == 0) 9149 /* default status block */ 9150 bp->igu_dsb_id = igu_sb_id; 9151 else { 9152 if (bp->igu_base_sb == 0xff) 9153 bp->igu_base_sb = igu_sb_id; 9154 igu_sb_cnt++; 9155 } 9156 } 9157 } 9158 9159#ifdef CONFIG_PCI_MSI 9160 /* 9161 * It's expected that number of CAM entries for this functions is equal 9162 * to the number evaluated based on the MSI-X table size. We want a 9163 * harsh warning if these values are different! 9164 */ 9165 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); 9166#endif 9167 9168 if (igu_sb_cnt == 0) 9169 BNX2X_ERR("CAM configuration error\n"); 9170} 9171 9172static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, 9173 u32 switch_cfg) 9174{ 9175 int cfg_size = 0, idx, port = BP_PORT(bp); 9176 9177 /* Aggregation of supported attributes of all external phys */ 9178 bp->port.supported[0] = 0; 9179 bp->port.supported[1] = 0; 9180 switch (bp->link_params.num_phys) { 9181 case 1: 9182 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; 9183 cfg_size = 1; 9184 break; 9185 case 2: 9186 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; 9187 cfg_size = 1; 9188 break; 9189 case 3: 9190 if (bp->link_params.multi_phy_config & 9191 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 9192 bp->port.supported[1] = 9193 bp->link_params.phy[EXT_PHY1].supported; 9194 bp->port.supported[0] = 9195 bp->link_params.phy[EXT_PHY2].supported; 9196 } else { 9197 bp->port.supported[0] = 9198 bp->link_params.phy[EXT_PHY1].supported; 9199 bp->port.supported[1] = 9200 bp->link_params.phy[EXT_PHY2].supported; 9201 } 9202 cfg_size = 2; 9203 break; 9204 } 9205 9206 if (!(bp->port.supported[0] || bp->port.supported[1])) { 9207 BNX2X_ERR("NVRAM config error. BAD phy config." 9208 "PHY1 config 0x%x, PHY2 config 0x%x\n", 9209 SHMEM_RD(bp, 9210 dev_info.port_hw_config[port].external_phy_config), 9211 SHMEM_RD(bp, 9212 dev_info.port_hw_config[port].external_phy_config2)); 9213 return; 9214 } 9215 9216 if (CHIP_IS_E3(bp)) 9217 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); 9218 else { 9219 switch (switch_cfg) { 9220 case SWITCH_CFG_1G: 9221 bp->port.phy_addr = REG_RD( 9222 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 9223 break; 9224 case SWITCH_CFG_10G: 9225 bp->port.phy_addr = REG_RD( 9226 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 9227 break; 9228 default: 9229 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 9230 bp->port.link_config[0]); 9231 return; 9232 } 9233 } 9234 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 9235 /* mask what we support according to speed_cap_mask per configuration */ 9236 for (idx = 0; idx < cfg_size; idx++) { 9237 if (!(bp->link_params.speed_cap_mask[idx] & 9238 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 9239 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; 9240 9241 if (!(bp->link_params.speed_cap_mask[idx] & 9242 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 9243 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; 9244 9245 if (!(bp->link_params.speed_cap_mask[idx] & 9246 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 9247 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; 9248 9249 if (!(bp->link_params.speed_cap_mask[idx] & 9250 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 9251 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; 9252 9253 if (!(bp->link_params.speed_cap_mask[idx] & 9254 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 9255 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | 9256 SUPPORTED_1000baseT_Full); 9257 9258 if (!(bp->link_params.speed_cap_mask[idx] & 9259 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 9260 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; 9261 9262 if (!(bp->link_params.speed_cap_mask[idx] & 9263 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 9264 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; 9265 9266 } 9267 9268 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], 9269 bp->port.supported[1]); 9270} 9271 9272static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) 9273{ 9274 u32 link_config, idx, cfg_size = 0; 9275 bp->port.advertising[0] = 0; 9276 bp->port.advertising[1] = 0; 9277 switch (bp->link_params.num_phys) { 9278 case 1: 9279 case 2: 9280 cfg_size = 1; 9281 break; 9282 case 3: 9283 cfg_size = 2; 9284 break; 9285 } 9286 for (idx = 0; idx < cfg_size; idx++) { 9287 bp->link_params.req_duplex[idx] = DUPLEX_FULL; 9288 link_config = bp->port.link_config[idx]; 9289 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 9290 case PORT_FEATURE_LINK_SPEED_AUTO: 9291 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { 9292 bp->link_params.req_line_speed[idx] = 9293 SPEED_AUTO_NEG; 9294 bp->port.advertising[idx] |= 9295 bp->port.supported[idx]; 9296 } else { 9297 /* force 10G, no AN */ 9298 bp->link_params.req_line_speed[idx] = 9299 SPEED_10000; 9300 bp->port.advertising[idx] |= 9301 (ADVERTISED_10000baseT_Full | 9302 ADVERTISED_FIBRE); 9303 continue; 9304 } 9305 break; 9306 9307 case PORT_FEATURE_LINK_SPEED_10M_FULL: 9308 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { 9309 bp->link_params.req_line_speed[idx] = 9310 SPEED_10; 9311 bp->port.advertising[idx] |= 9312 (ADVERTISED_10baseT_Full | 9313 ADVERTISED_TP); 9314 } else { 9315 BNX2X_ERR("NVRAM config error. " 9316 "Invalid link_config 0x%x" 9317 " speed_cap_mask 0x%x\n", 9318 link_config, 9319 bp->link_params.speed_cap_mask[idx]); 9320 return; 9321 } 9322 break; 9323 9324 case PORT_FEATURE_LINK_SPEED_10M_HALF: 9325 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { 9326 bp->link_params.req_line_speed[idx] = 9327 SPEED_10; 9328 bp->link_params.req_duplex[idx] = 9329 DUPLEX_HALF; 9330 bp->port.advertising[idx] |= 9331 (ADVERTISED_10baseT_Half | 9332 ADVERTISED_TP); 9333 } else { 9334 BNX2X_ERR("NVRAM config error. " 9335 "Invalid link_config 0x%x" 9336 " speed_cap_mask 0x%x\n", 9337 link_config, 9338 bp->link_params.speed_cap_mask[idx]); 9339 return; 9340 } 9341 break; 9342 9343 case PORT_FEATURE_LINK_SPEED_100M_FULL: 9344 if (bp->port.supported[idx] & 9345 SUPPORTED_100baseT_Full) { 9346 bp->link_params.req_line_speed[idx] = 9347 SPEED_100; 9348 bp->port.advertising[idx] |= 9349 (ADVERTISED_100baseT_Full | 9350 ADVERTISED_TP); 9351 } else { 9352 BNX2X_ERR("NVRAM config error. " 9353 "Invalid link_config 0x%x" 9354 " speed_cap_mask 0x%x\n", 9355 link_config, 9356 bp->link_params.speed_cap_mask[idx]); 9357 return; 9358 } 9359 break; 9360 9361 case PORT_FEATURE_LINK_SPEED_100M_HALF: 9362 if (bp->port.supported[idx] & 9363 SUPPORTED_100baseT_Half) { 9364 bp->link_params.req_line_speed[idx] = 9365 SPEED_100; 9366 bp->link_params.req_duplex[idx] = 9367 DUPLEX_HALF; 9368 bp->port.advertising[idx] |= 9369 (ADVERTISED_100baseT_Half | 9370 ADVERTISED_TP); 9371 } else { 9372 BNX2X_ERR("NVRAM config error. " 9373 "Invalid link_config 0x%x" 9374 " speed_cap_mask 0x%x\n", 9375 link_config, 9376 bp->link_params.speed_cap_mask[idx]); 9377 return; 9378 } 9379 break; 9380 9381 case PORT_FEATURE_LINK_SPEED_1G: 9382 if (bp->port.supported[idx] & 9383 SUPPORTED_1000baseT_Full) { 9384 bp->link_params.req_line_speed[idx] = 9385 SPEED_1000; 9386 bp->port.advertising[idx] |= 9387 (ADVERTISED_1000baseT_Full | 9388 ADVERTISED_TP); 9389 } else { 9390 BNX2X_ERR("NVRAM config error. " 9391 "Invalid link_config 0x%x" 9392 " speed_cap_mask 0x%x\n", 9393 link_config, 9394 bp->link_params.speed_cap_mask[idx]); 9395 return; 9396 } 9397 break; 9398 9399 case PORT_FEATURE_LINK_SPEED_2_5G: 9400 if (bp->port.supported[idx] & 9401 SUPPORTED_2500baseX_Full) { 9402 bp->link_params.req_line_speed[idx] = 9403 SPEED_2500; 9404 bp->port.advertising[idx] |= 9405 (ADVERTISED_2500baseX_Full | 9406 ADVERTISED_TP); 9407 } else { 9408 BNX2X_ERR("NVRAM config error. " 9409 "Invalid link_config 0x%x" 9410 " speed_cap_mask 0x%x\n", 9411 link_config, 9412 bp->link_params.speed_cap_mask[idx]); 9413 return; 9414 } 9415 break; 9416 9417 case PORT_FEATURE_LINK_SPEED_10G_CX4: 9418 if (bp->port.supported[idx] & 9419 SUPPORTED_10000baseT_Full) { 9420 bp->link_params.req_line_speed[idx] = 9421 SPEED_10000; 9422 bp->port.advertising[idx] |= 9423 (ADVERTISED_10000baseT_Full | 9424 ADVERTISED_FIBRE); 9425 } else { 9426 BNX2X_ERR("NVRAM config error. " 9427 "Invalid link_config 0x%x" 9428 " speed_cap_mask 0x%x\n", 9429 link_config, 9430 bp->link_params.speed_cap_mask[idx]); 9431 return; 9432 } 9433 break; 9434 case PORT_FEATURE_LINK_SPEED_20G: 9435 bp->link_params.req_line_speed[idx] = SPEED_20000; 9436 9437 break; 9438 default: 9439 BNX2X_ERR("NVRAM config error. " 9440 "BAD link speed link_config 0x%x\n", 9441 link_config); 9442 bp->link_params.req_line_speed[idx] = 9443 SPEED_AUTO_NEG; 9444 bp->port.advertising[idx] = 9445 bp->port.supported[idx]; 9446 break; 9447 } 9448 9449 bp->link_params.req_flow_ctrl[idx] = (link_config & 9450 PORT_FEATURE_FLOW_CONTROL_MASK); 9451 if ((bp->link_params.req_flow_ctrl[idx] == 9452 BNX2X_FLOW_CTRL_AUTO) && 9453 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { 9454 bp->link_params.req_flow_ctrl[idx] = 9455 BNX2X_FLOW_CTRL_NONE; 9456 } 9457 9458 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl" 9459 " 0x%x advertising 0x%x\n", 9460 bp->link_params.req_line_speed[idx], 9461 bp->link_params.req_duplex[idx], 9462 bp->link_params.req_flow_ctrl[idx], 9463 bp->port.advertising[idx]); 9464 } 9465} 9466 9467static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 9468{ 9469 mac_hi = cpu_to_be16(mac_hi); 9470 mac_lo = cpu_to_be32(mac_lo); 9471 memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); 9472 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); 9473} 9474 9475static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) 9476{ 9477 int port = BP_PORT(bp); 9478 u32 config; 9479 u32 ext_phy_type, ext_phy_config; 9480 9481 bp->link_params.bp = bp; 9482 bp->link_params.port = port; 9483 9484 bp->link_params.lane_config = 9485 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 9486 9487 bp->link_params.speed_cap_mask[0] = 9488 SHMEM_RD(bp, 9489 dev_info.port_hw_config[port].speed_capability_mask); 9490 bp->link_params.speed_cap_mask[1] = 9491 SHMEM_RD(bp, 9492 dev_info.port_hw_config[port].speed_capability_mask2); 9493 bp->port.link_config[0] = 9494 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 9495 9496 bp->port.link_config[1] = 9497 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); 9498 9499 bp->link_params.multi_phy_config = 9500 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); 9501 /* If the device is capable of WoL, set the default state according 9502 * to the HW 9503 */ 9504 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 9505 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 9506 (config & PORT_FEATURE_WOL_ENABLED)); 9507 9508 BNX2X_DEV_INFO("lane_config 0x%08x " 9509 "speed_cap_mask0 0x%08x link_config0 0x%08x\n", 9510 bp->link_params.lane_config, 9511 bp->link_params.speed_cap_mask[0], 9512 bp->port.link_config[0]); 9513 9514 bp->link_params.switch_cfg = (bp->port.link_config[0] & 9515 PORT_FEATURE_CONNECTED_SWITCH_MASK); 9516 bnx2x_phy_probe(&bp->link_params); 9517 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 9518 9519 bnx2x_link_settings_requested(bp); 9520 9521 /* 9522 * If connected directly, work with the internal PHY, otherwise, work 9523 * with the external PHY 9524 */ 9525 ext_phy_config = 9526 SHMEM_RD(bp, 9527 dev_info.port_hw_config[port].external_phy_config); 9528 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 9529 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 9530 bp->mdio.prtad = bp->port.phy_addr; 9531 9532 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 9533 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 9534 bp->mdio.prtad = 9535 XGXS_EXT_PHY_ADDR(ext_phy_config); 9536 9537 /* 9538 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) 9539 * In MF mode, it is set to cover self test cases 9540 */ 9541 if (IS_MF(bp)) 9542 bp->port.need_hw_lock = 1; 9543 else 9544 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, 9545 bp->common.shmem_base, 9546 bp->common.shmem2_base); 9547} 9548 9549void bnx2x_get_iscsi_info(struct bnx2x *bp) 9550{ 9551#ifdef BCM_CNIC 9552 int port = BP_PORT(bp); 9553 9554 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9555 drv_lic_key[port].max_iscsi_conn); 9556 9557 /* Get the number of maximum allowed iSCSI connections */ 9558 bp->cnic_eth_dev.max_iscsi_conn = 9559 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> 9560 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; 9561 9562 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", 9563 bp->cnic_eth_dev.max_iscsi_conn); 9564 9565 /* 9566 * If maximum allowed number of connections is zero - 9567 * disable the feature. 9568 */ 9569 if (!bp->cnic_eth_dev.max_iscsi_conn) 9570 bp->flags |= NO_ISCSI_FLAG; 9571#else 9572 bp->flags |= NO_ISCSI_FLAG; 9573#endif 9574} 9575 9576static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp) 9577{ 9578#ifdef BCM_CNIC 9579 int port = BP_PORT(bp); 9580 int func = BP_ABS_FUNC(bp); 9581 9582 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9583 drv_lic_key[port].max_fcoe_conn); 9584 9585 /* Get the number of maximum allowed FCoE connections */ 9586 bp->cnic_eth_dev.max_fcoe_conn = 9587 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> 9588 BNX2X_MAX_FCOE_INIT_CONN_SHIFT; 9589 9590 /* Read the WWN: */ 9591 if (!IS_MF(bp)) { 9592 /* Port info */ 9593 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9594 SHMEM_RD(bp, 9595 dev_info.port_hw_config[port]. 9596 fcoe_wwn_port_name_upper); 9597 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9598 SHMEM_RD(bp, 9599 dev_info.port_hw_config[port]. 9600 fcoe_wwn_port_name_lower); 9601 9602 /* Node info */ 9603 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9604 SHMEM_RD(bp, 9605 dev_info.port_hw_config[port]. 9606 fcoe_wwn_node_name_upper); 9607 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9608 SHMEM_RD(bp, 9609 dev_info.port_hw_config[port]. 9610 fcoe_wwn_node_name_lower); 9611 } else if (!IS_MF_SD(bp)) { 9612 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9613 9614 /* 9615 * Read the WWN info only if the FCoE feature is enabled for 9616 * this function. 9617 */ 9618 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9619 /* Port info */ 9620 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9621 MF_CFG_RD(bp, func_ext_config[func]. 9622 fcoe_wwn_port_name_upper); 9623 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9624 MF_CFG_RD(bp, func_ext_config[func]. 9625 fcoe_wwn_port_name_lower); 9626 9627 /* Node info */ 9628 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9629 MF_CFG_RD(bp, func_ext_config[func]. 9630 fcoe_wwn_node_name_upper); 9631 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9632 MF_CFG_RD(bp, func_ext_config[func]. 9633 fcoe_wwn_node_name_lower); 9634 } 9635 } 9636 9637 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); 9638 9639 /* 9640 * If maximum allowed number of connections is zero - 9641 * disable the feature. 9642 */ 9643 if (!bp->cnic_eth_dev.max_fcoe_conn) 9644 bp->flags |= NO_FCOE_FLAG; 9645#else 9646 bp->flags |= NO_FCOE_FLAG; 9647#endif 9648} 9649 9650static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) 9651{ 9652 /* 9653 * iSCSI may be dynamically disabled but reading 9654 * info here we will decrease memory usage by driver 9655 * if the feature is disabled for good 9656 */ 9657 bnx2x_get_iscsi_info(bp); 9658 bnx2x_get_fcoe_info(bp); 9659} 9660 9661static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) 9662{ 9663 u32 val, val2; 9664 int func = BP_ABS_FUNC(bp); 9665 int port = BP_PORT(bp); 9666#ifdef BCM_CNIC 9667 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; 9668 u8 *fip_mac = bp->fip_mac; 9669#endif 9670 9671 /* Zero primary MAC configuration */ 9672 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9673 9674 if (BP_NOMCP(bp)) { 9675 BNX2X_ERROR("warning: random MAC workaround active\n"); 9676 random_ether_addr(bp->dev->dev_addr); 9677 } else if (IS_MF(bp)) { 9678 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 9679 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); 9680 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && 9681 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) 9682 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9683 9684#ifdef BCM_CNIC 9685 /* 9686 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or 9687 * FCoE MAC then the appropriate feature should be disabled. 9688 */ 9689 if (IS_MF_SI(bp)) { 9690 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9691 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 9692 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9693 iscsi_mac_addr_upper); 9694 val = MF_CFG_RD(bp, func_ext_config[func]. 9695 iscsi_mac_addr_lower); 9696 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9697 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9698 iscsi_mac); 9699 } else 9700 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 9701 9702 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9703 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9704 fcoe_mac_addr_upper); 9705 val = MF_CFG_RD(bp, func_ext_config[func]. 9706 fcoe_mac_addr_lower); 9707 bnx2x_set_mac_buf(fip_mac, val, val2); 9708 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n", 9709 fip_mac); 9710 9711 } else 9712 bp->flags |= NO_FCOE_FLAG; 9713 } else { /* SD mode */ 9714 if (BNX2X_IS_MF_PROTOCOL_ISCSI(bp)) { 9715 /* use primary mac as iscsi mac */ 9716 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); 9717 /* Zero primary MAC configuration */ 9718 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9719 9720 BNX2X_DEV_INFO("SD ISCSI MODE\n"); 9721 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9722 iscsi_mac); 9723 } 9724 } 9725#endif 9726 } else { 9727 /* in SF read MACs from port configuration */ 9728 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 9729 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 9730 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9731 9732#ifdef BCM_CNIC 9733 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9734 iscsi_mac_upper); 9735 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9736 iscsi_mac_lower); 9737 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9738 9739 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9740 fcoe_fip_mac_upper); 9741 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9742 fcoe_fip_mac_lower); 9743 bnx2x_set_mac_buf(fip_mac, val, val2); 9744#endif 9745 } 9746 9747 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 9748 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); 9749 9750#ifdef BCM_CNIC 9751 /* Set the FCoE MAC in MF_SD mode */ 9752 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp)) 9753 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); 9754 9755 /* Disable iSCSI if MAC configuration is 9756 * invalid. 9757 */ 9758 if (!is_valid_ether_addr(iscsi_mac)) { 9759 bp->flags |= NO_ISCSI_FLAG; 9760 memset(iscsi_mac, 0, ETH_ALEN); 9761 } 9762 9763 /* Disable FCoE if MAC configuration is 9764 * invalid. 9765 */ 9766 if (!is_valid_ether_addr(fip_mac)) { 9767 bp->flags |= NO_FCOE_FLAG; 9768 memset(bp->fip_mac, 0, ETH_ALEN); 9769 } 9770#endif 9771 9772 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) 9773 dev_err(&bp->pdev->dev, 9774 "bad Ethernet MAC address configuration: " 9775 "%pM, change it manually before bringing up " 9776 "the appropriate network interface\n", 9777 bp->dev->dev_addr); 9778} 9779 9780static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) 9781{ 9782 int /*abs*/func = BP_ABS_FUNC(bp); 9783 int vn; 9784 u32 val = 0; 9785 int rc = 0; 9786 9787 bnx2x_get_common_hwinfo(bp); 9788 9789 /* 9790 * initialize IGU parameters 9791 */ 9792 if (CHIP_IS_E1x(bp)) { 9793 bp->common.int_block = INT_BLOCK_HC; 9794 9795 bp->igu_dsb_id = DEF_SB_IGU_ID; 9796 bp->igu_base_sb = 0; 9797 } else { 9798 bp->common.int_block = INT_BLOCK_IGU; 9799 9800 /* do not allow device reset during IGU info preocessing */ 9801 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9802 9803 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 9804 9805 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9806 int tout = 5000; 9807 9808 BNX2X_DEV_INFO("FORCING Normal Mode\n"); 9809 9810 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 9811 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); 9812 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); 9813 9814 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9815 tout--; 9816 usleep_range(1000, 1000); 9817 } 9818 9819 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9820 dev_err(&bp->pdev->dev, 9821 "FORCING Normal Mode failed!!!\n"); 9822 return -EPERM; 9823 } 9824 } 9825 9826 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9827 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); 9828 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; 9829 } else 9830 BNX2X_DEV_INFO("IGU Normal Mode\n"); 9831 9832 bnx2x_get_igu_cam_info(bp); 9833 9834 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9835 } 9836 9837 /* 9838 * set base FW non-default (fast path) status block id, this value is 9839 * used to initialize the fw_sb_id saved on the fp/queue structure to 9840 * determine the id used by the FW. 9841 */ 9842 if (CHIP_IS_E1x(bp)) 9843 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); 9844 else /* 9845 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of 9846 * the same queue are indicated on the same IGU SB). So we prefer 9847 * FW and IGU SBs to be the same value. 9848 */ 9849 bp->base_fw_ndsb = bp->igu_base_sb; 9850 9851 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" 9852 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, 9853 bp->igu_sb_cnt, bp->base_fw_ndsb); 9854 9855 /* 9856 * Initialize MF configuration 9857 */ 9858 9859 bp->mf_ov = 0; 9860 bp->mf_mode = 0; 9861 vn = BP_VN(bp); 9862 9863 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 9864 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 9865 bp->common.shmem2_base, SHMEM2_RD(bp, size), 9866 (u32)offsetof(struct shmem2_region, mf_cfg_addr)); 9867 9868 if (SHMEM2_HAS(bp, mf_cfg_addr)) 9869 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); 9870 else 9871 bp->common.mf_cfg_base = bp->common.shmem_base + 9872 offsetof(struct shmem_region, func_mb) + 9873 E1H_FUNC_MAX * sizeof(struct drv_func_mb); 9874 /* 9875 * get mf configuration: 9876 * 1. existence of MF configuration 9877 * 2. MAC address must be legal (check only upper bytes) 9878 * for Switch-Independent mode; 9879 * OVLAN must be legal for Switch-Dependent mode 9880 * 3. SF_MODE configures specific MF mode 9881 */ 9882 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9883 /* get mf configuration */ 9884 val = SHMEM_RD(bp, 9885 dev_info.shared_feature_config.config); 9886 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; 9887 9888 switch (val) { 9889 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 9890 val = MF_CFG_RD(bp, func_mf_config[func]. 9891 mac_upper); 9892 /* check for legal mac (upper bytes)*/ 9893 if (val != 0xffff) { 9894 bp->mf_mode = MULTI_FUNCTION_SI; 9895 bp->mf_config[vn] = MF_CFG_RD(bp, 9896 func_mf_config[func].config); 9897 } else 9898 BNX2X_DEV_INFO("illegal MAC address " 9899 "for SI\n"); 9900 break; 9901 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 9902 /* get OV configuration */ 9903 val = MF_CFG_RD(bp, 9904 func_mf_config[FUNC_0].e1hov_tag); 9905 val &= FUNC_MF_CFG_E1HOV_TAG_MASK; 9906 9907 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9908 bp->mf_mode = MULTI_FUNCTION_SD; 9909 bp->mf_config[vn] = MF_CFG_RD(bp, 9910 func_mf_config[func].config); 9911 } else 9912 BNX2X_DEV_INFO("illegal OV for SD\n"); 9913 break; 9914 default: 9915 /* Unknown configuration: reset mf_config */ 9916 bp->mf_config[vn] = 0; 9917 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val); 9918 } 9919 } 9920 9921 BNX2X_DEV_INFO("%s function mode\n", 9922 IS_MF(bp) ? "multi" : "single"); 9923 9924 switch (bp->mf_mode) { 9925 case MULTI_FUNCTION_SD: 9926 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 9927 FUNC_MF_CFG_E1HOV_TAG_MASK; 9928 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9929 bp->mf_ov = val; 9930 bp->path_has_ovlan = true; 9931 9932 BNX2X_DEV_INFO("MF OV for func %d is %d " 9933 "(0x%04x)\n", func, bp->mf_ov, 9934 bp->mf_ov); 9935 } else { 9936 dev_err(&bp->pdev->dev, 9937 "No valid MF OV for func %d, " 9938 "aborting\n", func); 9939 return -EPERM; 9940 } 9941 break; 9942 case MULTI_FUNCTION_SI: 9943 BNX2X_DEV_INFO("func %d is in MF " 9944 "switch-independent mode\n", func); 9945 break; 9946 default: 9947 if (vn) { 9948 dev_err(&bp->pdev->dev, 9949 "VN %d is in a single function mode, " 9950 "aborting\n", vn); 9951 return -EPERM; 9952 } 9953 break; 9954 } 9955 9956 /* check if other port on the path needs ovlan: 9957 * Since MF configuration is shared between ports 9958 * Possible mixed modes are only 9959 * {SF, SI} {SF, SD} {SD, SF} {SI, SF} 9960 */ 9961 if (CHIP_MODE_IS_4_PORT(bp) && 9962 !bp->path_has_ovlan && 9963 !IS_MF(bp) && 9964 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9965 u8 other_port = !BP_PORT(bp); 9966 u8 other_func = BP_PATH(bp) + 2*other_port; 9967 val = MF_CFG_RD(bp, 9968 func_mf_config[other_func].e1hov_tag); 9969 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) 9970 bp->path_has_ovlan = true; 9971 } 9972 } 9973 9974 /* adjust igu_sb_cnt to MF for E1x */ 9975 if (CHIP_IS_E1x(bp) && IS_MF(bp)) 9976 bp->igu_sb_cnt /= E1HVN_MAX; 9977 9978 /* port info */ 9979 bnx2x_get_port_hwinfo(bp); 9980 9981 /* Get MAC addresses */ 9982 bnx2x_get_mac_hwinfo(bp); 9983 9984 bnx2x_get_cnic_info(bp); 9985 9986 return rc; 9987} 9988 9989static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) 9990{ 9991 int cnt, i, block_end, rodi; 9992 char vpd_start[BNX2X_VPD_LEN+1]; 9993 char str_id_reg[VENDOR_ID_LEN+1]; 9994 char str_id_cap[VENDOR_ID_LEN+1]; 9995 char *vpd_data; 9996 char *vpd_extended_data = NULL; 9997 u8 len; 9998 9999 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); 10000 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); 10001 10002 if (cnt < BNX2X_VPD_LEN) 10003 goto out_not_found; 10004 10005 /* VPD RO tag should be first tag after identifier string, hence 10006 * we should be able to find it in first BNX2X_VPD_LEN chars 10007 */ 10008 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, 10009 PCI_VPD_LRDT_RO_DATA); 10010 if (i < 0) 10011 goto out_not_found; 10012 10013 block_end = i + PCI_VPD_LRDT_TAG_SIZE + 10014 pci_vpd_lrdt_size(&vpd_start[i]); 10015 10016 i += PCI_VPD_LRDT_TAG_SIZE; 10017 10018 if (block_end > BNX2X_VPD_LEN) { 10019 vpd_extended_data = kmalloc(block_end, GFP_KERNEL); 10020 if (vpd_extended_data == NULL) 10021 goto out_not_found; 10022 10023 /* read rest of vpd image into vpd_extended_data */ 10024 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); 10025 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, 10026 block_end - BNX2X_VPD_LEN, 10027 vpd_extended_data + BNX2X_VPD_LEN); 10028 if (cnt < (block_end - BNX2X_VPD_LEN)) 10029 goto out_not_found; 10030 vpd_data = vpd_extended_data; 10031 } else 10032 vpd_data = vpd_start; 10033 10034 /* now vpd_data holds full vpd content in both cases */ 10035 10036 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 10037 PCI_VPD_RO_KEYWORD_MFR_ID); 10038 if (rodi < 0) 10039 goto out_not_found; 10040 10041 len = pci_vpd_info_field_size(&vpd_data[rodi]); 10042 10043 if (len != VENDOR_ID_LEN) 10044 goto out_not_found; 10045 10046 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 10047 10048 /* vendor specific info */ 10049 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); 10050 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); 10051 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || 10052 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { 10053 10054 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 10055 PCI_VPD_RO_KEYWORD_VENDOR0); 10056 if (rodi >= 0) { 10057 len = pci_vpd_info_field_size(&vpd_data[rodi]); 10058 10059 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 10060 10061 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { 10062 memcpy(bp->fw_ver, &vpd_data[rodi], len); 10063 bp->fw_ver[len] = ' '; 10064 } 10065 } 10066 kfree(vpd_extended_data); 10067 return; 10068 } 10069out_not_found: 10070 kfree(vpd_extended_data); 10071 return; 10072} 10073 10074static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) 10075{ 10076 u32 flags = 0; 10077 10078 if (CHIP_REV_IS_FPGA(bp)) 10079 SET_FLAGS(flags, MODE_FPGA); 10080 else if (CHIP_REV_IS_EMUL(bp)) 10081 SET_FLAGS(flags, MODE_EMUL); 10082 else 10083 SET_FLAGS(flags, MODE_ASIC); 10084 10085 if (CHIP_MODE_IS_4_PORT(bp)) 10086 SET_FLAGS(flags, MODE_PORT4); 10087 else 10088 SET_FLAGS(flags, MODE_PORT2); 10089 10090 if (CHIP_IS_E2(bp)) 10091 SET_FLAGS(flags, MODE_E2); 10092 else if (CHIP_IS_E3(bp)) { 10093 SET_FLAGS(flags, MODE_E3); 10094 if (CHIP_REV(bp) == CHIP_REV_Ax) 10095 SET_FLAGS(flags, MODE_E3_A0); 10096 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ 10097 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 10098 } 10099 10100 if (IS_MF(bp)) { 10101 SET_FLAGS(flags, MODE_MF); 10102 switch (bp->mf_mode) { 10103 case MULTI_FUNCTION_SD: 10104 SET_FLAGS(flags, MODE_MF_SD); 10105 break; 10106 case MULTI_FUNCTION_SI: 10107 SET_FLAGS(flags, MODE_MF_SI); 10108 break; 10109 } 10110 } else 10111 SET_FLAGS(flags, MODE_SF); 10112 10113#if defined(__LITTLE_ENDIAN) 10114 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 10115#else /*(__BIG_ENDIAN)*/ 10116 SET_FLAGS(flags, MODE_BIG_ENDIAN); 10117#endif 10118 INIT_MODE_FLAGS(bp) = flags; 10119} 10120 10121static int __devinit bnx2x_init_bp(struct bnx2x *bp) 10122{ 10123 int func; 10124 int timer_interval; 10125 int rc; 10126 10127 mutex_init(&bp->port.phy_mutex); 10128 mutex_init(&bp->fw_mb_mutex); 10129 spin_lock_init(&bp->stats_lock); 10130#ifdef BCM_CNIC 10131 mutex_init(&bp->cnic_mutex); 10132#endif 10133 10134 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); 10135 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); 10136 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); 10137 rc = bnx2x_get_hwinfo(bp); 10138 if (rc) 10139 return rc; 10140 10141 bnx2x_set_modes_bitmap(bp); 10142 10143 rc = bnx2x_alloc_mem_bp(bp); 10144 if (rc) 10145 return rc; 10146 10147 bnx2x_read_fwinfo(bp); 10148 10149 func = BP_FUNC(bp); 10150 10151 /* need to reset chip if undi was active */ 10152 if (!BP_NOMCP(bp)) 10153 bnx2x_undi_unload(bp); 10154 10155 if (CHIP_REV_IS_FPGA(bp)) 10156 dev_err(&bp->pdev->dev, "FPGA detected\n"); 10157 10158 if (BP_NOMCP(bp) && (func == 0)) 10159 dev_err(&bp->pdev->dev, "MCP disabled, " 10160 "must load devices in order!\n"); 10161 10162 bp->multi_mode = multi_mode; 10163 10164 bp->disable_tpa = disable_tpa; 10165 10166#ifdef BCM_CNIC 10167 bp->disable_tpa |= IS_MF_ISCSI_SD(bp); 10168#endif 10169 10170 /* Set TPA flags */ 10171 if (bp->disable_tpa) { 10172 bp->flags &= ~TPA_ENABLE_FLAG; 10173 bp->dev->features &= ~NETIF_F_LRO; 10174 } else { 10175 bp->flags |= TPA_ENABLE_FLAG; 10176 bp->dev->features |= NETIF_F_LRO; 10177 } 10178 10179 if (CHIP_IS_E1(bp)) 10180 bp->dropless_fc = 0; 10181 else 10182 bp->dropless_fc = dropless_fc; 10183 10184 bp->mrrs = mrrs; 10185 10186 bp->tx_ring_size = MAX_TX_AVAIL; 10187 10188 /* make sure that the numbers are in the right granularity */ 10189 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; 10190 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; 10191 10192 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ); 10193 bp->current_interval = (poll ? poll : timer_interval); 10194 10195 init_timer(&bp->timer); 10196 bp->timer.expires = jiffies + bp->current_interval; 10197 bp->timer.data = (unsigned long) bp; 10198 bp->timer.function = bnx2x_timer; 10199 10200 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); 10201 bnx2x_dcbx_init_params(bp); 10202 10203#ifdef BCM_CNIC 10204 if (CHIP_IS_E1x(bp)) 10205 bp->cnic_base_cl_id = FP_SB_MAX_E1x; 10206 else 10207 bp->cnic_base_cl_id = FP_SB_MAX_E2; 10208#endif 10209 10210 /* multiple tx priority */ 10211 if (CHIP_IS_E1x(bp)) 10212 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; 10213 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) 10214 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; 10215 if (CHIP_IS_E3B0(bp)) 10216 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; 10217 10218 return rc; 10219} 10220 10221 10222/**************************************************************************** 10223* General service functions 10224****************************************************************************/ 10225 10226/* 10227 * net_device service functions 10228 */ 10229 10230/* called with rtnl_lock */ 10231static int bnx2x_open(struct net_device *dev) 10232{ 10233 struct bnx2x *bp = netdev_priv(dev); 10234 bool global = false; 10235 int other_engine = BP_PATH(bp) ? 0 : 1; 10236 bool other_load_status, load_status; 10237 10238 netif_carrier_off(dev); 10239 10240 bnx2x_set_power_state(bp, PCI_D0); 10241 10242 other_load_status = bnx2x_get_load_status(bp, other_engine); 10243 load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); 10244 10245 /* 10246 * If parity had happen during the unload, then attentions 10247 * and/or RECOVERY_IN_PROGRES may still be set. In this case we 10248 * want the first function loaded on the current engine to 10249 * complete the recovery. 10250 */ 10251 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 10252 bnx2x_chk_parity_attn(bp, &global, true)) 10253 do { 10254 /* 10255 * If there are attentions and they are in a global 10256 * blocks, set the GLOBAL_RESET bit regardless whether 10257 * it will be this function that will complete the 10258 * recovery or not. 10259 */ 10260 if (global) 10261 bnx2x_set_reset_global(bp); 10262 10263 /* 10264 * Only the first function on the current engine should 10265 * try to recover in open. In case of attentions in 10266 * global blocks only the first in the chip should try 10267 * to recover. 10268 */ 10269 if ((!load_status && 10270 (!global || !other_load_status)) && 10271 bnx2x_trylock_leader_lock(bp) && 10272 !bnx2x_leader_reset(bp)) { 10273 netdev_info(bp->dev, "Recovered in open\n"); 10274 break; 10275 } 10276 10277 /* recovery has failed... */ 10278 bnx2x_set_power_state(bp, PCI_D3hot); 10279 bp->recovery_state = BNX2X_RECOVERY_FAILED; 10280 10281 netdev_err(bp->dev, "Recovery flow hasn't been properly" 10282 " completed yet. Try again later. If u still see this" 10283 " message after a few retries then power cycle is" 10284 " required.\n"); 10285 10286 return -EAGAIN; 10287 } while (0); 10288 10289 bp->recovery_state = BNX2X_RECOVERY_DONE; 10290 return bnx2x_nic_load(bp, LOAD_OPEN); 10291} 10292 10293/* called with rtnl_lock */ 10294int bnx2x_close(struct net_device *dev) 10295{ 10296 struct bnx2x *bp = netdev_priv(dev); 10297 10298 /* Unload the driver, release IRQs */ 10299 bnx2x_nic_unload(bp, UNLOAD_CLOSE); 10300 10301 /* Power off */ 10302 bnx2x_set_power_state(bp, PCI_D3hot); 10303 10304 return 0; 10305} 10306 10307static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp, 10308 struct bnx2x_mcast_ramrod_params *p) 10309{ 10310 int mc_count = netdev_mc_count(bp->dev); 10311 struct bnx2x_mcast_list_elem *mc_mac = 10312 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); 10313 struct netdev_hw_addr *ha; 10314 10315 if (!mc_mac) 10316 return -ENOMEM; 10317 10318 INIT_LIST_HEAD(&p->mcast_list); 10319 10320 netdev_for_each_mc_addr(ha, bp->dev) { 10321 mc_mac->mac = bnx2x_mc_addr(ha); 10322 list_add_tail(&mc_mac->link, &p->mcast_list); 10323 mc_mac++; 10324 } 10325 10326 p->mcast_list_len = mc_count; 10327 10328 return 0; 10329} 10330 10331static inline void bnx2x_free_mcast_macs_list( 10332 struct bnx2x_mcast_ramrod_params *p) 10333{ 10334 struct bnx2x_mcast_list_elem *mc_mac = 10335 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, 10336 link); 10337 10338 WARN_ON(!mc_mac); 10339 kfree(mc_mac); 10340} 10341 10342/** 10343 * bnx2x_set_uc_list - configure a new unicast MACs list. 10344 * 10345 * @bp: driver handle 10346 * 10347 * We will use zero (0) as a MAC type for these MACs. 10348 */ 10349static inline int bnx2x_set_uc_list(struct bnx2x *bp) 10350{ 10351 int rc; 10352 struct net_device *dev = bp->dev; 10353 struct netdev_hw_addr *ha; 10354 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj; 10355 unsigned long ramrod_flags = 0; 10356 10357 /* First schedule a cleanup up of old configuration */ 10358 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); 10359 if (rc < 0) { 10360 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); 10361 return rc; 10362 } 10363 10364 netdev_for_each_uc_addr(ha, dev) { 10365 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, 10366 BNX2X_UC_LIST_MAC, &ramrod_flags); 10367 if (rc < 0) { 10368 BNX2X_ERR("Failed to schedule ADD operations: %d\n", 10369 rc); 10370 return rc; 10371 } 10372 } 10373 10374 /* Execute the pending commands */ 10375 __set_bit(RAMROD_CONT, &ramrod_flags); 10376 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, 10377 BNX2X_UC_LIST_MAC, &ramrod_flags); 10378} 10379 10380static inline int bnx2x_set_mc_list(struct bnx2x *bp) 10381{ 10382 struct net_device *dev = bp->dev; 10383 struct bnx2x_mcast_ramrod_params rparam = {0}; 10384 int rc = 0; 10385 10386 rparam.mcast_obj = &bp->mcast_obj; 10387 10388 /* first, clear all configured multicast MACs */ 10389 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 10390 if (rc < 0) { 10391 BNX2X_ERR("Failed to clear multicast " 10392 "configuration: %d\n", rc); 10393 return rc; 10394 } 10395 10396 /* then, configure a new MACs list */ 10397 if (netdev_mc_count(dev)) { 10398 rc = bnx2x_init_mcast_macs_list(bp, &rparam); 10399 if (rc) { 10400 BNX2X_ERR("Failed to create multicast MACs " 10401 "list: %d\n", rc); 10402 return rc; 10403 } 10404 10405 /* Now add the new MACs */ 10406 rc = bnx2x_config_mcast(bp, &rparam, 10407 BNX2X_MCAST_CMD_ADD); 10408 if (rc < 0) 10409 BNX2X_ERR("Failed to set a new multicast " 10410 "configuration: %d\n", rc); 10411 10412 bnx2x_free_mcast_macs_list(&rparam); 10413 } 10414 10415 return rc; 10416} 10417 10418 10419/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ 10420void bnx2x_set_rx_mode(struct net_device *dev) 10421{ 10422 struct bnx2x *bp = netdev_priv(dev); 10423 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 10424 10425 if (bp->state != BNX2X_STATE_OPEN) { 10426 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 10427 return; 10428 } 10429 10430 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); 10431 10432 if (dev->flags & IFF_PROMISC) 10433 rx_mode = BNX2X_RX_MODE_PROMISC; 10434 else if ((dev->flags & IFF_ALLMULTI) || 10435 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && 10436 CHIP_IS_E1(bp))) 10437 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10438 else { 10439 /* some multicasts */ 10440 if (bnx2x_set_mc_list(bp) < 0) 10441 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10442 10443 if (bnx2x_set_uc_list(bp) < 0) 10444 rx_mode = BNX2X_RX_MODE_PROMISC; 10445 } 10446 10447 bp->rx_mode = rx_mode; 10448#ifdef BCM_CNIC 10449 /* handle ISCSI SD mode */ 10450 if (IS_MF_ISCSI_SD(bp)) 10451 bp->rx_mode = BNX2X_RX_MODE_NONE; 10452#endif 10453 10454 /* Schedule the rx_mode command */ 10455 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { 10456 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 10457 return; 10458 } 10459 10460 bnx2x_set_storm_rx_mode(bp); 10461} 10462 10463/* called with rtnl_lock */ 10464static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 10465 int devad, u16 addr) 10466{ 10467 struct bnx2x *bp = netdev_priv(netdev); 10468 u16 value; 10469 int rc; 10470 10471 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 10472 prtad, devad, addr); 10473 10474 /* The HW expects different devad if CL22 is used */ 10475 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10476 10477 bnx2x_acquire_phy_lock(bp); 10478 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); 10479 bnx2x_release_phy_lock(bp); 10480 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 10481 10482 if (!rc) 10483 rc = value; 10484 return rc; 10485} 10486 10487/* called with rtnl_lock */ 10488static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, 10489 u16 addr, u16 value) 10490{ 10491 struct bnx2x *bp = netdev_priv(netdev); 10492 int rc; 10493 10494 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x," 10495 " value 0x%x\n", prtad, devad, addr, value); 10496 10497 /* The HW expects different devad if CL22 is used */ 10498 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10499 10500 bnx2x_acquire_phy_lock(bp); 10501 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); 10502 bnx2x_release_phy_lock(bp); 10503 return rc; 10504} 10505 10506/* called with rtnl_lock */ 10507static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 10508{ 10509 struct bnx2x *bp = netdev_priv(dev); 10510 struct mii_ioctl_data *mdio = if_mii(ifr); 10511 10512 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", 10513 mdio->phy_id, mdio->reg_num, mdio->val_in); 10514 10515 if (!netif_running(dev)) 10516 return -EAGAIN; 10517 10518 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); 10519} 10520 10521#ifdef CONFIG_NET_POLL_CONTROLLER 10522static void poll_bnx2x(struct net_device *dev) 10523{ 10524 struct bnx2x *bp = netdev_priv(dev); 10525 10526 disable_irq(bp->pdev->irq); 10527 bnx2x_interrupt(bp->pdev->irq, dev); 10528 enable_irq(bp->pdev->irq); 10529} 10530#endif 10531 10532static int bnx2x_validate_addr(struct net_device *dev) 10533{ 10534 struct bnx2x *bp = netdev_priv(dev); 10535 10536 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) 10537 return -EADDRNOTAVAIL; 10538 return 0; 10539} 10540 10541static const struct net_device_ops bnx2x_netdev_ops = { 10542 .ndo_open = bnx2x_open, 10543 .ndo_stop = bnx2x_close, 10544 .ndo_start_xmit = bnx2x_start_xmit, 10545 .ndo_select_queue = bnx2x_select_queue, 10546 .ndo_set_rx_mode = bnx2x_set_rx_mode, 10547 .ndo_set_mac_address = bnx2x_change_mac_addr, 10548 .ndo_validate_addr = bnx2x_validate_addr, 10549 .ndo_do_ioctl = bnx2x_ioctl, 10550 .ndo_change_mtu = bnx2x_change_mtu, 10551 .ndo_fix_features = bnx2x_fix_features, 10552 .ndo_set_features = bnx2x_set_features, 10553 .ndo_tx_timeout = bnx2x_tx_timeout, 10554#ifdef CONFIG_NET_POLL_CONTROLLER 10555 .ndo_poll_controller = poll_bnx2x, 10556#endif 10557 .ndo_setup_tc = bnx2x_setup_tc, 10558 10559#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) 10560 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, 10561#endif 10562}; 10563 10564static inline int bnx2x_set_coherency_mask(struct bnx2x *bp) 10565{ 10566 struct device *dev = &bp->pdev->dev; 10567 10568 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 10569 bp->flags |= USING_DAC_FLAG; 10570 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 10571 dev_err(dev, "dma_set_coherent_mask failed, " 10572 "aborting\n"); 10573 return -EIO; 10574 } 10575 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 10576 dev_err(dev, "System does not support DMA, aborting\n"); 10577 return -EIO; 10578 } 10579 10580 return 0; 10581} 10582 10583static int __devinit bnx2x_init_dev(struct pci_dev *pdev, 10584 struct net_device *dev, 10585 unsigned long board_type) 10586{ 10587 struct bnx2x *bp; 10588 int rc; 10589 u32 pci_cfg_dword; 10590 bool chip_is_e1x = (board_type == BCM57710 || 10591 board_type == BCM57711 || 10592 board_type == BCM57711E); 10593 10594 SET_NETDEV_DEV(dev, &pdev->dev); 10595 bp = netdev_priv(dev); 10596 10597 bp->dev = dev; 10598 bp->pdev = pdev; 10599 bp->flags = 0; 10600 10601 rc = pci_enable_device(pdev); 10602 if (rc) { 10603 dev_err(&bp->pdev->dev, 10604 "Cannot enable PCI device, aborting\n"); 10605 goto err_out; 10606 } 10607 10608 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 10609 dev_err(&bp->pdev->dev, 10610 "Cannot find PCI device base address, aborting\n"); 10611 rc = -ENODEV; 10612 goto err_out_disable; 10613 } 10614 10615 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 10616 dev_err(&bp->pdev->dev, "Cannot find second PCI device" 10617 " base address, aborting\n"); 10618 rc = -ENODEV; 10619 goto err_out_disable; 10620 } 10621 10622 if (atomic_read(&pdev->enable_cnt) == 1) { 10623 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 10624 if (rc) { 10625 dev_err(&bp->pdev->dev, 10626 "Cannot obtain PCI resources, aborting\n"); 10627 goto err_out_disable; 10628 } 10629 10630 pci_set_master(pdev); 10631 pci_save_state(pdev); 10632 } 10633 10634 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 10635 if (bp->pm_cap == 0) { 10636 dev_err(&bp->pdev->dev, 10637 "Cannot find power management capability, aborting\n"); 10638 rc = -EIO; 10639 goto err_out_release; 10640 } 10641 10642 if (!pci_is_pcie(pdev)) { 10643 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 10644 rc = -EIO; 10645 goto err_out_release; 10646 } 10647 10648 rc = bnx2x_set_coherency_mask(bp); 10649 if (rc) 10650 goto err_out_release; 10651 10652 dev->mem_start = pci_resource_start(pdev, 0); 10653 dev->base_addr = dev->mem_start; 10654 dev->mem_end = pci_resource_end(pdev, 0); 10655 10656 dev->irq = pdev->irq; 10657 10658 bp->regview = pci_ioremap_bar(pdev, 0); 10659 if (!bp->regview) { 10660 dev_err(&bp->pdev->dev, 10661 "Cannot map register space, aborting\n"); 10662 rc = -ENOMEM; 10663 goto err_out_release; 10664 } 10665 10666 /* In E1/E1H use pci device function given by kernel. 10667 * In E2/E3 read physical function from ME register since these chips 10668 * support Physical Device Assignment where kernel BDF maybe arbitrary 10669 * (depending on hypervisor). 10670 */ 10671 if (chip_is_e1x) 10672 bp->pf_num = PCI_FUNC(pdev->devfn); 10673 else {/* chip is E2/3*/ 10674 pci_read_config_dword(bp->pdev, 10675 PCICFG_ME_REGISTER, &pci_cfg_dword); 10676 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> 10677 ME_REG_ABS_PF_NUM_SHIFT); 10678 } 10679 DP(BNX2X_MSG_SP, "me reg PF num: %d\n", bp->pf_num); 10680 10681 bnx2x_set_power_state(bp, PCI_D0); 10682 10683 /* clean indirect addresses */ 10684 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 10685 PCICFG_VENDOR_ID_OFFSET); 10686 /* 10687 * Clean the following indirect addresses for all functions since it 10688 * is not used by the driver. 10689 */ 10690 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); 10691 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); 10692 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 10693 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 10694 10695 if (chip_is_e1x) { 10696 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 10697 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 10698 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 10699 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); 10700 } 10701 10702 /* 10703 * Enable internal target-read (in case we are probed after PF FLR). 10704 * Must be done prior to any BAR read access. Only for 57712 and up 10705 */ 10706 if (!chip_is_e1x) 10707 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 10708 10709 /* Reset the load counter */ 10710 bnx2x_clear_load_status(bp); 10711 10712 dev->watchdog_timeo = TX_TIMEOUT; 10713 10714 dev->netdev_ops = &bnx2x_netdev_ops; 10715 bnx2x_set_ethtool_ops(dev); 10716 10717 dev->priv_flags |= IFF_UNICAST_FLT; 10718 10719 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10720 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_LRO | 10721 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; 10722 10723 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10724 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 10725 10726 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; 10727 if (bp->flags & USING_DAC_FLAG) 10728 dev->features |= NETIF_F_HIGHDMA; 10729 10730 /* Add Loopback capability to the device */ 10731 dev->hw_features |= NETIF_F_LOOPBACK; 10732 10733#ifdef BCM_DCBNL 10734 dev->dcbnl_ops = &bnx2x_dcbnl_ops; 10735#endif 10736 10737 /* get_port_hwinfo() will set prtad and mmds properly */ 10738 bp->mdio.prtad = MDIO_PRTAD_NONE; 10739 bp->mdio.mmds = 0; 10740 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10741 bp->mdio.dev = dev; 10742 bp->mdio.mdio_read = bnx2x_mdio_read; 10743 bp->mdio.mdio_write = bnx2x_mdio_write; 10744 10745 return 0; 10746 10747err_out_release: 10748 if (atomic_read(&pdev->enable_cnt) == 1) 10749 pci_release_regions(pdev); 10750 10751err_out_disable: 10752 pci_disable_device(pdev); 10753 pci_set_drvdata(pdev, NULL); 10754 10755err_out: 10756 return rc; 10757} 10758 10759static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, 10760 int *width, int *speed) 10761{ 10762 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); 10763 10764 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; 10765 10766 /* return value of 1=2.5GHz 2=5GHz */ 10767 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; 10768} 10769 10770static int bnx2x_check_firmware(struct bnx2x *bp) 10771{ 10772 const struct firmware *firmware = bp->firmware; 10773 struct bnx2x_fw_file_hdr *fw_hdr; 10774 struct bnx2x_fw_file_section *sections; 10775 u32 offset, len, num_ops; 10776 u16 *ops_offsets; 10777 int i; 10778 const u8 *fw_ver; 10779 10780 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) 10781 return -EINVAL; 10782 10783 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 10784 sections = (struct bnx2x_fw_file_section *)fw_hdr; 10785 10786 /* Make sure none of the offsets and sizes make us read beyond 10787 * the end of the firmware data */ 10788 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { 10789 offset = be32_to_cpu(sections[i].offset); 10790 len = be32_to_cpu(sections[i].len); 10791 if (offset + len > firmware->size) { 10792 dev_err(&bp->pdev->dev, 10793 "Section %d length is out of bounds\n", i); 10794 return -EINVAL; 10795 } 10796 } 10797 10798 /* Likewise for the init_ops offsets */ 10799 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); 10800 ops_offsets = (u16 *)(firmware->data + offset); 10801 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); 10802 10803 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 10804 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 10805 dev_err(&bp->pdev->dev, 10806 "Section offset %d is out of bounds\n", i); 10807 return -EINVAL; 10808 } 10809 } 10810 10811 /* Check FW version */ 10812 offset = be32_to_cpu(fw_hdr->fw_version.offset); 10813 fw_ver = firmware->data + offset; 10814 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || 10815 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || 10816 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || 10817 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { 10818 dev_err(&bp->pdev->dev, 10819 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 10820 fw_ver[0], fw_ver[1], fw_ver[2], 10821 fw_ver[3], BCM_5710_FW_MAJOR_VERSION, 10822 BCM_5710_FW_MINOR_VERSION, 10823 BCM_5710_FW_REVISION_VERSION, 10824 BCM_5710_FW_ENGINEERING_VERSION); 10825 return -EINVAL; 10826 } 10827 10828 return 0; 10829} 10830 10831static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10832{ 10833 const __be32 *source = (const __be32 *)_source; 10834 u32 *target = (u32 *)_target; 10835 u32 i; 10836 10837 for (i = 0; i < n/4; i++) 10838 target[i] = be32_to_cpu(source[i]); 10839} 10840 10841/* 10842 Ops array is stored in the following format: 10843 {op(8bit), offset(24bit, big endian), data(32bit, big endian)} 10844 */ 10845static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) 10846{ 10847 const __be32 *source = (const __be32 *)_source; 10848 struct raw_op *target = (struct raw_op *)_target; 10849 u32 i, j, tmp; 10850 10851 for (i = 0, j = 0; i < n/8; i++, j += 2) { 10852 tmp = be32_to_cpu(source[j]); 10853 target[i].op = (tmp >> 24) & 0xff; 10854 target[i].offset = tmp & 0xffffff; 10855 target[i].raw_data = be32_to_cpu(source[j + 1]); 10856 } 10857} 10858 10859/** 10860 * IRO array is stored in the following format: 10861 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } 10862 */ 10863static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) 10864{ 10865 const __be32 *source = (const __be32 *)_source; 10866 struct iro *target = (struct iro *)_target; 10867 u32 i, j, tmp; 10868 10869 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { 10870 target[i].base = be32_to_cpu(source[j]); 10871 j++; 10872 tmp = be32_to_cpu(source[j]); 10873 target[i].m1 = (tmp >> 16) & 0xffff; 10874 target[i].m2 = tmp & 0xffff; 10875 j++; 10876 tmp = be32_to_cpu(source[j]); 10877 target[i].m3 = (tmp >> 16) & 0xffff; 10878 target[i].size = tmp & 0xffff; 10879 j++; 10880 } 10881} 10882 10883static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10884{ 10885 const __be16 *source = (const __be16 *)_source; 10886 u16 *target = (u16 *)_target; 10887 u32 i; 10888 10889 for (i = 0; i < n/2; i++) 10890 target[i] = be16_to_cpu(source[i]); 10891} 10892 10893#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ 10894do { \ 10895 u32 len = be32_to_cpu(fw_hdr->arr.len); \ 10896 bp->arr = kmalloc(len, GFP_KERNEL); \ 10897 if (!bp->arr) { \ 10898 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \ 10899 goto lbl; \ 10900 } \ 10901 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ 10902 (u8 *)bp->arr, len); \ 10903} while (0) 10904 10905int bnx2x_init_firmware(struct bnx2x *bp) 10906{ 10907 struct bnx2x_fw_file_hdr *fw_hdr; 10908 int rc; 10909 10910 10911 if (!bp->firmware) { 10912 const char *fw_file_name; 10913 10914 if (CHIP_IS_E1(bp)) 10915 fw_file_name = FW_FILE_NAME_E1; 10916 else if (CHIP_IS_E1H(bp)) 10917 fw_file_name = FW_FILE_NAME_E1H; 10918 else if (!CHIP_IS_E1x(bp)) 10919 fw_file_name = FW_FILE_NAME_E2; 10920 else { 10921 BNX2X_ERR("Unsupported chip revision\n"); 10922 return -EINVAL; 10923 } 10924 BNX2X_DEV_INFO("Loading %s\n", fw_file_name); 10925 10926 rc = request_firmware(&bp->firmware, fw_file_name, 10927 &bp->pdev->dev); 10928 if (rc) { 10929 BNX2X_ERR("Can't load firmware file %s\n", 10930 fw_file_name); 10931 goto request_firmware_exit; 10932 } 10933 10934 rc = bnx2x_check_firmware(bp); 10935 if (rc) { 10936 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); 10937 goto request_firmware_exit; 10938 } 10939 } 10940 10941 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; 10942 10943 /* Initialize the pointers to the init arrays */ 10944 /* Blob */ 10945 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); 10946 10947 /* Opcodes */ 10948 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); 10949 10950 /* Offsets */ 10951 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, 10952 be16_to_cpu_n); 10953 10954 /* STORMs firmware */ 10955 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10956 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); 10957 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + 10958 be32_to_cpu(fw_hdr->tsem_pram_data.offset); 10959 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10960 be32_to_cpu(fw_hdr->usem_int_table_data.offset); 10961 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + 10962 be32_to_cpu(fw_hdr->usem_pram_data.offset); 10963 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10964 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); 10965 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + 10966 be32_to_cpu(fw_hdr->xsem_pram_data.offset); 10967 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10968 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 10969 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 10970 be32_to_cpu(fw_hdr->csem_pram_data.offset); 10971 /* IRO */ 10972 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); 10973 10974 return 0; 10975 10976iro_alloc_err: 10977 kfree(bp->init_ops_offsets); 10978init_offsets_alloc_err: 10979 kfree(bp->init_ops); 10980init_ops_alloc_err: 10981 kfree(bp->init_data); 10982request_firmware_exit: 10983 release_firmware(bp->firmware); 10984 10985 return rc; 10986} 10987 10988static void bnx2x_release_firmware(struct bnx2x *bp) 10989{ 10990 kfree(bp->init_ops_offsets); 10991 kfree(bp->init_ops); 10992 kfree(bp->init_data); 10993 release_firmware(bp->firmware); 10994 bp->firmware = NULL; 10995} 10996 10997 10998static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { 10999 .init_hw_cmn_chip = bnx2x_init_hw_common_chip, 11000 .init_hw_cmn = bnx2x_init_hw_common, 11001 .init_hw_port = bnx2x_init_hw_port, 11002 .init_hw_func = bnx2x_init_hw_func, 11003 11004 .reset_hw_cmn = bnx2x_reset_common, 11005 .reset_hw_port = bnx2x_reset_port, 11006 .reset_hw_func = bnx2x_reset_func, 11007 11008 .gunzip_init = bnx2x_gunzip_init, 11009 .gunzip_end = bnx2x_gunzip_end, 11010 11011 .init_fw = bnx2x_init_firmware, 11012 .release_fw = bnx2x_release_firmware, 11013}; 11014 11015void bnx2x__init_func_obj(struct bnx2x *bp) 11016{ 11017 /* Prepare DMAE related driver resources */ 11018 bnx2x_setup_dmae(bp); 11019 11020 bnx2x_init_func_obj(bp, &bp->func_obj, 11021 bnx2x_sp(bp, func_rdata), 11022 bnx2x_sp_mapping(bp, func_rdata), 11023 &bnx2x_func_sp_drv); 11024} 11025 11026/* must be called after sriov-enable */ 11027static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp) 11028{ 11029 int cid_count = BNX2X_L2_CID_COUNT(bp); 11030 11031#ifdef BCM_CNIC 11032 cid_count += CNIC_CID_MAX; 11033#endif 11034 return roundup(cid_count, QM_CID_ROUND); 11035} 11036 11037/** 11038 * bnx2x_get_num_none_def_sbs - return the number of none default SBs 11039 * 11040 * @dev: pci device 11041 * 11042 */ 11043static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) 11044{ 11045 int pos; 11046 u16 control; 11047 11048 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 11049 11050 /* 11051 * If MSI-X is not supported - return number of SBs needed to support 11052 * one fast path queue: one FP queue + SB for CNIC 11053 */ 11054 if (!pos) 11055 return 1 + CNIC_PRESENT; 11056 11057 /* 11058 * The value in the PCI configuration space is the index of the last 11059 * entry, namely one less than the actual size of the table, which is 11060 * exactly what we want to return from this function: number of all SBs 11061 * without the default SB. 11062 */ 11063 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 11064 return control & PCI_MSIX_FLAGS_QSIZE; 11065} 11066 11067static int __devinit bnx2x_init_one(struct pci_dev *pdev, 11068 const struct pci_device_id *ent) 11069{ 11070 struct net_device *dev = NULL; 11071 struct bnx2x *bp; 11072 int pcie_width, pcie_speed; 11073 int rc, max_non_def_sbs; 11074 int rx_count, tx_count, rss_count; 11075 /* 11076 * An estimated maximum supported CoS number according to the chip 11077 * version. 11078 * We will try to roughly estimate the maximum number of CoSes this chip 11079 * may support in order to minimize the memory allocated for Tx 11080 * netdev_queue's. This number will be accurately calculated during the 11081 * initialization of bp->max_cos based on the chip versions AND chip 11082 * revision in the bnx2x_init_bp(). 11083 */ 11084 u8 max_cos_est = 0; 11085 11086 switch (ent->driver_data) { 11087 case BCM57710: 11088 case BCM57711: 11089 case BCM57711E: 11090 max_cos_est = BNX2X_MULTI_TX_COS_E1X; 11091 break; 11092 11093 case BCM57712: 11094 case BCM57712_MF: 11095 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; 11096 break; 11097 11098 case BCM57800: 11099 case BCM57800_MF: 11100 case BCM57810: 11101 case BCM57810_MF: 11102 case BCM57840: 11103 case BCM57840_MF: 11104 max_cos_est = BNX2X_MULTI_TX_COS_E3B0; 11105 break; 11106 11107 default: 11108 pr_err("Unknown board_type (%ld), aborting\n", 11109 ent->driver_data); 11110 return -ENODEV; 11111 } 11112 11113 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); 11114 11115 /* !!! FIXME !!! 11116 * Do not allow the maximum SB count to grow above 16 11117 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48. 11118 * We will use the FP_SB_MAX_E1x macro for this matter. 11119 */ 11120 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs); 11121 11122 WARN_ON(!max_non_def_sbs); 11123 11124 /* Maximum number of RSS queues: one IGU SB goes to CNIC */ 11125 rss_count = max_non_def_sbs - CNIC_PRESENT; 11126 11127 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ 11128 rx_count = rss_count + FCOE_PRESENT; 11129 11130 /* 11131 * Maximum number of netdev Tx queues: 11132 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 11133 */ 11134 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT; 11135 11136 /* dev zeroed in init_etherdev */ 11137 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); 11138 if (!dev) { 11139 dev_err(&pdev->dev, "Cannot allocate net device\n"); 11140 return -ENOMEM; 11141 } 11142 11143 bp = netdev_priv(dev); 11144 11145 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n", 11146 tx_count, rx_count); 11147 11148 bp->igu_sb_cnt = max_non_def_sbs; 11149 bp->msg_enable = debug; 11150 pci_set_drvdata(pdev, dev); 11151 11152 rc = bnx2x_init_dev(pdev, dev, ent->driver_data); 11153 if (rc < 0) { 11154 free_netdev(dev); 11155 return rc; 11156 } 11157 11158 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs); 11159 11160 rc = bnx2x_init_bp(bp); 11161 if (rc) 11162 goto init_one_exit; 11163 11164 /* 11165 * Map doorbels here as we need the real value of bp->max_cos which 11166 * is initialized in bnx2x_init_bp(). 11167 */ 11168 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), 11169 min_t(u64, BNX2X_DB_SIZE(bp), 11170 pci_resource_len(pdev, 2))); 11171 if (!bp->doorbells) { 11172 dev_err(&bp->pdev->dev, 11173 "Cannot map doorbell space, aborting\n"); 11174 rc = -ENOMEM; 11175 goto init_one_exit; 11176 } 11177 11178 /* calc qm_cid_count */ 11179 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); 11180 11181#ifdef BCM_CNIC 11182 /* disable FCOE L2 queue for E1x */ 11183 if (CHIP_IS_E1x(bp)) 11184 bp->flags |= NO_FCOE_FLAG; 11185 11186#endif 11187 11188 /* Configure interrupt mode: try to enable MSI-X/MSI if 11189 * needed, set bp->num_queues appropriately. 11190 */ 11191 bnx2x_set_int_mode(bp); 11192 11193 /* Add all NAPI objects */ 11194 bnx2x_add_all_napi(bp); 11195 11196 rc = register_netdev(dev); 11197 if (rc) { 11198 dev_err(&pdev->dev, "Cannot register net device\n"); 11199 goto init_one_exit; 11200 } 11201 11202#ifdef BCM_CNIC 11203 if (!NO_FCOE(bp)) { 11204 /* Add storage MAC address */ 11205 rtnl_lock(); 11206 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11207 rtnl_unlock(); 11208 } 11209#endif 11210 11211 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); 11212 11213 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", 11214 board_info[ent->driver_data].name, 11215 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 11216 pcie_width, 11217 ((!CHIP_IS_E2(bp) && pcie_speed == 2) || 11218 (CHIP_IS_E2(bp) && pcie_speed == 1)) ? 11219 "5GHz (Gen2)" : "2.5GHz", 11220 dev->base_addr, bp->pdev->irq, dev->dev_addr); 11221 11222 return 0; 11223 11224init_one_exit: 11225 if (bp->regview) 11226 iounmap(bp->regview); 11227 11228 if (bp->doorbells) 11229 iounmap(bp->doorbells); 11230 11231 free_netdev(dev); 11232 11233 if (atomic_read(&pdev->enable_cnt) == 1) 11234 pci_release_regions(pdev); 11235 11236 pci_disable_device(pdev); 11237 pci_set_drvdata(pdev, NULL); 11238 11239 return rc; 11240} 11241 11242static void __devexit bnx2x_remove_one(struct pci_dev *pdev) 11243{ 11244 struct net_device *dev = pci_get_drvdata(pdev); 11245 struct bnx2x *bp; 11246 11247 if (!dev) { 11248 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); 11249 return; 11250 } 11251 bp = netdev_priv(dev); 11252 11253#ifdef BCM_CNIC 11254 /* Delete storage MAC address */ 11255 if (!NO_FCOE(bp)) { 11256 rtnl_lock(); 11257 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11258 rtnl_unlock(); 11259 } 11260#endif 11261 11262#ifdef BCM_DCBNL 11263 /* Delete app tlvs from dcbnl */ 11264 bnx2x_dcbnl_update_applist(bp, true); 11265#endif 11266 11267 unregister_netdev(dev); 11268 11269 /* Delete all NAPI objects */ 11270 bnx2x_del_all_napi(bp); 11271 11272 /* Power on: we can't let PCI layer write to us while we are in D3 */ 11273 bnx2x_set_power_state(bp, PCI_D0); 11274 11275 /* Disable MSI/MSI-X */ 11276 bnx2x_disable_msi(bp); 11277 11278 /* Power off */ 11279 bnx2x_set_power_state(bp, PCI_D3hot); 11280 11281 /* Make sure RESET task is not scheduled before continuing */ 11282 cancel_delayed_work_sync(&bp->sp_rtnl_task); 11283 11284 if (bp->regview) 11285 iounmap(bp->regview); 11286 11287 if (bp->doorbells) 11288 iounmap(bp->doorbells); 11289 11290 bnx2x_release_firmware(bp); 11291 11292 bnx2x_free_mem_bp(bp); 11293 11294 free_netdev(dev); 11295 11296 if (atomic_read(&pdev->enable_cnt) == 1) 11297 pci_release_regions(pdev); 11298 11299 pci_disable_device(pdev); 11300 pci_set_drvdata(pdev, NULL); 11301} 11302 11303static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 11304{ 11305 int i; 11306 11307 bp->state = BNX2X_STATE_ERROR; 11308 11309 bp->rx_mode = BNX2X_RX_MODE_NONE; 11310 11311#ifdef BCM_CNIC 11312 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); 11313#endif 11314 /* Stop Tx */ 11315 bnx2x_tx_disable(bp); 11316 11317 bnx2x_netif_stop(bp, 0); 11318 11319 del_timer_sync(&bp->timer); 11320 11321 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 11322 11323 /* Release IRQs */ 11324 bnx2x_free_irq(bp); 11325 11326 /* Free SKBs, SGEs, TPA pool and driver internals */ 11327 bnx2x_free_skbs(bp); 11328 11329 for_each_rx_queue(bp, i) 11330 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 11331 11332 bnx2x_free_mem(bp); 11333 11334 bp->state = BNX2X_STATE_CLOSED; 11335 11336 netif_carrier_off(bp->dev); 11337 11338 return 0; 11339} 11340 11341static void bnx2x_eeh_recover(struct bnx2x *bp) 11342{ 11343 u32 val; 11344 11345 mutex_init(&bp->port.phy_mutex); 11346 11347 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 11348 bp->link_params.shmem_base = bp->common.shmem_base; 11349 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base); 11350 11351 if (!bp->common.shmem_base || 11352 (bp->common.shmem_base < 0xA0000) || 11353 (bp->common.shmem_base >= 0xC0000)) { 11354 BNX2X_DEV_INFO("MCP not active\n"); 11355 bp->flags |= NO_MCP_FLAG; 11356 return; 11357 } 11358 11359 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 11360 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11361 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11362 BNX2X_ERR("BAD MCP validity signature\n"); 11363} 11364 11365/** 11366 * bnx2x_io_error_detected - called when PCI error is detected 11367 * @pdev: Pointer to PCI device 11368 * @state: The current pci connection state 11369 * 11370 * This function is called after a PCI bus error affecting 11371 * this device has been detected. 11372 */ 11373static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, 11374 pci_channel_state_t state) 11375{ 11376 struct net_device *dev = pci_get_drvdata(pdev); 11377 struct bnx2x *bp = netdev_priv(dev); 11378 11379 rtnl_lock(); 11380 11381 netif_device_detach(dev); 11382 11383 if (state == pci_channel_io_perm_failure) { 11384 rtnl_unlock(); 11385 return PCI_ERS_RESULT_DISCONNECT; 11386 } 11387 11388 if (netif_running(dev)) 11389 bnx2x_eeh_nic_unload(bp); 11390 11391 pci_disable_device(pdev); 11392 11393 rtnl_unlock(); 11394 11395 /* Request a slot reset */ 11396 return PCI_ERS_RESULT_NEED_RESET; 11397} 11398 11399/** 11400 * bnx2x_io_slot_reset - called after the PCI bus has been reset 11401 * @pdev: Pointer to PCI device 11402 * 11403 * Restart the card from scratch, as if from a cold-boot. 11404 */ 11405static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) 11406{ 11407 struct net_device *dev = pci_get_drvdata(pdev); 11408 struct bnx2x *bp = netdev_priv(dev); 11409 11410 rtnl_lock(); 11411 11412 if (pci_enable_device(pdev)) { 11413 dev_err(&pdev->dev, 11414 "Cannot re-enable PCI device after reset\n"); 11415 rtnl_unlock(); 11416 return PCI_ERS_RESULT_DISCONNECT; 11417 } 11418 11419 pci_set_master(pdev); 11420 pci_restore_state(pdev); 11421 11422 if (netif_running(dev)) 11423 bnx2x_set_power_state(bp, PCI_D0); 11424 11425 rtnl_unlock(); 11426 11427 return PCI_ERS_RESULT_RECOVERED; 11428} 11429 11430/** 11431 * bnx2x_io_resume - called when traffic can start flowing again 11432 * @pdev: Pointer to PCI device 11433 * 11434 * This callback is called when the error recovery driver tells us that 11435 * its OK to resume normal operation. 11436 */ 11437static void bnx2x_io_resume(struct pci_dev *pdev) 11438{ 11439 struct net_device *dev = pci_get_drvdata(pdev); 11440 struct bnx2x *bp = netdev_priv(dev); 11441 11442 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 11443 netdev_err(bp->dev, "Handling parity error recovery. " 11444 "Try again later\n"); 11445 return; 11446 } 11447 11448 rtnl_lock(); 11449 11450 bnx2x_eeh_recover(bp); 11451 11452 if (netif_running(dev)) 11453 bnx2x_nic_load(bp, LOAD_NORMAL); 11454 11455 netif_device_attach(dev); 11456 11457 rtnl_unlock(); 11458} 11459 11460static struct pci_error_handlers bnx2x_err_handler = { 11461 .error_detected = bnx2x_io_error_detected, 11462 .slot_reset = bnx2x_io_slot_reset, 11463 .resume = bnx2x_io_resume, 11464}; 11465 11466static struct pci_driver bnx2x_pci_driver = { 11467 .name = DRV_MODULE_NAME, 11468 .id_table = bnx2x_pci_tbl, 11469 .probe = bnx2x_init_one, 11470 .remove = __devexit_p(bnx2x_remove_one), 11471 .suspend = bnx2x_suspend, 11472 .resume = bnx2x_resume, 11473 .err_handler = &bnx2x_err_handler, 11474}; 11475 11476static int __init bnx2x_init(void) 11477{ 11478 int ret; 11479 11480 pr_info("%s", version); 11481 11482 bnx2x_wq = create_singlethread_workqueue("bnx2x"); 11483 if (bnx2x_wq == NULL) { 11484 pr_err("Cannot create workqueue\n"); 11485 return -ENOMEM; 11486 } 11487 11488 ret = pci_register_driver(&bnx2x_pci_driver); 11489 if (ret) { 11490 pr_err("Cannot register driver\n"); 11491 destroy_workqueue(bnx2x_wq); 11492 } 11493 return ret; 11494} 11495 11496static void __exit bnx2x_cleanup(void) 11497{ 11498 pci_unregister_driver(&bnx2x_pci_driver); 11499 11500 destroy_workqueue(bnx2x_wq); 11501} 11502 11503void bnx2x_notify_link_changed(struct bnx2x *bp) 11504{ 11505 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); 11506} 11507 11508module_init(bnx2x_init); 11509module_exit(bnx2x_cleanup); 11510 11511#ifdef BCM_CNIC 11512/** 11513 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). 11514 * 11515 * @bp: driver handle 11516 * @set: set or clear the CAM entry 11517 * 11518 * This function will wait until the ramdord completion returns. 11519 * Return 0 if success, -ENODEV if ramrod doesn't return. 11520 */ 11521static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) 11522{ 11523 unsigned long ramrod_flags = 0; 11524 11525 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 11526 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, 11527 &bp->iscsi_l2_mac_obj, true, 11528 BNX2X_ISCSI_ETH_MAC, &ramrod_flags); 11529} 11530 11531/* count denotes the number of new completions we have seen */ 11532static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) 11533{ 11534 struct eth_spe *spe; 11535 11536#ifdef BNX2X_STOP_ON_ERROR 11537 if (unlikely(bp->panic)) 11538 return; 11539#endif 11540 11541 spin_lock_bh(&bp->spq_lock); 11542 BUG_ON(bp->cnic_spq_pending < count); 11543 bp->cnic_spq_pending -= count; 11544 11545 11546 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { 11547 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) 11548 & SPE_HDR_CONN_TYPE) >> 11549 SPE_HDR_CONN_TYPE_SHIFT; 11550 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) 11551 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; 11552 11553 /* Set validation for iSCSI L2 client before sending SETUP 11554 * ramrod 11555 */ 11556 if (type == ETH_CONNECTION_TYPE) { 11557 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) 11558 bnx2x_set_ctx_validation(bp, &bp->context. 11559 vcxt[BNX2X_ISCSI_ETH_CID].eth, 11560 BNX2X_ISCSI_ETH_CID); 11561 } 11562 11563 /* 11564 * There may be not more than 8 L2, not more than 8 L5 SPEs 11565 * and in the air. We also check that number of outstanding 11566 * COMMON ramrods is not more than the EQ and SPQ can 11567 * accommodate. 11568 */ 11569 if (type == ETH_CONNECTION_TYPE) { 11570 if (!atomic_read(&bp->cq_spq_left)) 11571 break; 11572 else 11573 atomic_dec(&bp->cq_spq_left); 11574 } else if (type == NONE_CONNECTION_TYPE) { 11575 if (!atomic_read(&bp->eq_spq_left)) 11576 break; 11577 else 11578 atomic_dec(&bp->eq_spq_left); 11579 } else if ((type == ISCSI_CONNECTION_TYPE) || 11580 (type == FCOE_CONNECTION_TYPE)) { 11581 if (bp->cnic_spq_pending >= 11582 bp->cnic_eth_dev.max_kwqe_pending) 11583 break; 11584 else 11585 bp->cnic_spq_pending++; 11586 } else { 11587 BNX2X_ERR("Unknown SPE type: %d\n", type); 11588 bnx2x_panic(); 11589 break; 11590 } 11591 11592 spe = bnx2x_sp_get_next(bp); 11593 *spe = *bp->cnic_kwq_cons; 11594 11595 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n", 11596 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 11597 11598 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 11599 bp->cnic_kwq_cons = bp->cnic_kwq; 11600 else 11601 bp->cnic_kwq_cons++; 11602 } 11603 bnx2x_sp_prod_update(bp); 11604 spin_unlock_bh(&bp->spq_lock); 11605} 11606 11607static int bnx2x_cnic_sp_queue(struct net_device *dev, 11608 struct kwqe_16 *kwqes[], u32 count) 11609{ 11610 struct bnx2x *bp = netdev_priv(dev); 11611 int i; 11612 11613#ifdef BNX2X_STOP_ON_ERROR 11614 if (unlikely(bp->panic)) 11615 return -EIO; 11616#endif 11617 11618 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && 11619 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 11620 netdev_err(dev, "Handling parity error recovery. Try again " 11621 "later\n"); 11622 return -EAGAIN; 11623 } 11624 11625 spin_lock_bh(&bp->spq_lock); 11626 11627 for (i = 0; i < count; i++) { 11628 struct eth_spe *spe = (struct eth_spe *)kwqes[i]; 11629 11630 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) 11631 break; 11632 11633 *bp->cnic_kwq_prod = *spe; 11634 11635 bp->cnic_kwq_pending++; 11636 11637 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n", 11638 spe->hdr.conn_and_cmd_data, spe->hdr.type, 11639 spe->data.update_data_addr.hi, 11640 spe->data.update_data_addr.lo, 11641 bp->cnic_kwq_pending); 11642 11643 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 11644 bp->cnic_kwq_prod = bp->cnic_kwq; 11645 else 11646 bp->cnic_kwq_prod++; 11647 } 11648 11649 spin_unlock_bh(&bp->spq_lock); 11650 11651 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) 11652 bnx2x_cnic_sp_post(bp, 0); 11653 11654 return i; 11655} 11656 11657static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11658{ 11659 struct cnic_ops *c_ops; 11660 int rc = 0; 11661 11662 mutex_lock(&bp->cnic_mutex); 11663 c_ops = rcu_dereference_protected(bp->cnic_ops, 11664 lockdep_is_held(&bp->cnic_mutex)); 11665 if (c_ops) 11666 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11667 mutex_unlock(&bp->cnic_mutex); 11668 11669 return rc; 11670} 11671 11672static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11673{ 11674 struct cnic_ops *c_ops; 11675 int rc = 0; 11676 11677 rcu_read_lock(); 11678 c_ops = rcu_dereference(bp->cnic_ops); 11679 if (c_ops) 11680 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11681 rcu_read_unlock(); 11682 11683 return rc; 11684} 11685 11686/* 11687 * for commands that have no data 11688 */ 11689int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) 11690{ 11691 struct cnic_ctl_info ctl = {0}; 11692 11693 ctl.cmd = cmd; 11694 11695 return bnx2x_cnic_ctl_send(bp, &ctl); 11696} 11697 11698static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) 11699{ 11700 struct cnic_ctl_info ctl = {0}; 11701 11702 /* first we tell CNIC and only then we count this as a completion */ 11703 ctl.cmd = CNIC_CTL_COMPLETION_CMD; 11704 ctl.data.comp.cid = cid; 11705 ctl.data.comp.error = err; 11706 11707 bnx2x_cnic_ctl_send_bh(bp, &ctl); 11708 bnx2x_cnic_sp_post(bp, 0); 11709} 11710 11711 11712/* Called with netif_addr_lock_bh() taken. 11713 * Sets an rx_mode config for an iSCSI ETH client. 11714 * Doesn't block. 11715 * Completion should be checked outside. 11716 */ 11717static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) 11718{ 11719 unsigned long accept_flags = 0, ramrod_flags = 0; 11720 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11721 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; 11722 11723 if (start) { 11724 /* Start accepting on iSCSI L2 ring. Accept all multicasts 11725 * because it's the only way for UIO Queue to accept 11726 * multicasts (in non-promiscuous mode only one Queue per 11727 * function will receive multicast packets (leading in our 11728 * case). 11729 */ 11730 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); 11731 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); 11732 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); 11733 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 11734 11735 /* Clear STOP_PENDING bit if START is requested */ 11736 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); 11737 11738 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; 11739 } else 11740 /* Clear START_PENDING bit if STOP is requested */ 11741 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); 11742 11743 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 11744 set_bit(sched_state, &bp->sp_state); 11745 else { 11746 __set_bit(RAMROD_RX, &ramrod_flags); 11747 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, 11748 ramrod_flags); 11749 } 11750} 11751 11752 11753static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 11754{ 11755 struct bnx2x *bp = netdev_priv(dev); 11756 int rc = 0; 11757 11758 switch (ctl->cmd) { 11759 case DRV_CTL_CTXTBL_WR_CMD: { 11760 u32 index = ctl->data.io.offset; 11761 dma_addr_t addr = ctl->data.io.dma_addr; 11762 11763 bnx2x_ilt_wr(bp, index, addr); 11764 break; 11765 } 11766 11767 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { 11768 int count = ctl->data.credit.credit_count; 11769 11770 bnx2x_cnic_sp_post(bp, count); 11771 break; 11772 } 11773 11774 /* rtnl_lock is held. */ 11775 case DRV_CTL_START_L2_CMD: { 11776 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11777 unsigned long sp_bits = 0; 11778 11779 /* Configure the iSCSI classification object */ 11780 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, 11781 cp->iscsi_l2_client_id, 11782 cp->iscsi_l2_cid, BP_FUNC(bp), 11783 bnx2x_sp(bp, mac_rdata), 11784 bnx2x_sp_mapping(bp, mac_rdata), 11785 BNX2X_FILTER_MAC_PENDING, 11786 &bp->sp_state, BNX2X_OBJ_TYPE_RX, 11787 &bp->macs_pool); 11788 11789 /* Set iSCSI MAC address */ 11790 rc = bnx2x_set_iscsi_eth_mac_addr(bp); 11791 if (rc) 11792 break; 11793 11794 mmiowb(); 11795 barrier(); 11796 11797 /* Start accepting on iSCSI L2 ring */ 11798 11799 netif_addr_lock_bh(dev); 11800 bnx2x_set_iscsi_eth_rx_mode(bp, true); 11801 netif_addr_unlock_bh(dev); 11802 11803 /* bits to wait on */ 11804 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11805 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); 11806 11807 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11808 BNX2X_ERR("rx_mode completion timed out!\n"); 11809 11810 break; 11811 } 11812 11813 /* rtnl_lock is held. */ 11814 case DRV_CTL_STOP_L2_CMD: { 11815 unsigned long sp_bits = 0; 11816 11817 /* Stop accepting on iSCSI L2 ring */ 11818 netif_addr_lock_bh(dev); 11819 bnx2x_set_iscsi_eth_rx_mode(bp, false); 11820 netif_addr_unlock_bh(dev); 11821 11822 /* bits to wait on */ 11823 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11824 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); 11825 11826 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11827 BNX2X_ERR("rx_mode completion timed out!\n"); 11828 11829 mmiowb(); 11830 barrier(); 11831 11832 /* Unset iSCSI L2 MAC */ 11833 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, 11834 BNX2X_ISCSI_ETH_MAC, true); 11835 break; 11836 } 11837 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { 11838 int count = ctl->data.credit.credit_count; 11839 11840 smp_mb__before_atomic_inc(); 11841 atomic_add(count, &bp->cq_spq_left); 11842 smp_mb__after_atomic_inc(); 11843 break; 11844 } 11845 case DRV_CTL_ULP_REGISTER_CMD: { 11846 int ulp_type = ctl->data.ulp_type; 11847 11848 if (CHIP_IS_E3(bp)) { 11849 int idx = BP_FW_MB_IDX(bp); 11850 u32 cap; 11851 11852 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 11853 if (ulp_type == CNIC_ULP_ISCSI) 11854 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 11855 else if (ulp_type == CNIC_ULP_FCOE) 11856 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 11857 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 11858 } 11859 break; 11860 } 11861 case DRV_CTL_ULP_UNREGISTER_CMD: { 11862 int ulp_type = ctl->data.ulp_type; 11863 11864 if (CHIP_IS_E3(bp)) { 11865 int idx = BP_FW_MB_IDX(bp); 11866 u32 cap; 11867 11868 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 11869 if (ulp_type == CNIC_ULP_ISCSI) 11870 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 11871 else if (ulp_type == CNIC_ULP_FCOE) 11872 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 11873 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 11874 } 11875 break; 11876 } 11877 11878 default: 11879 BNX2X_ERR("unknown command %x\n", ctl->cmd); 11880 rc = -EINVAL; 11881 } 11882 11883 return rc; 11884} 11885 11886void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) 11887{ 11888 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11889 11890 if (bp->flags & USING_MSIX_FLAG) { 11891 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 11892 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 11893 cp->irq_arr[0].vector = bp->msix_table[1].vector; 11894 } else { 11895 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 11896 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 11897 } 11898 if (!CHIP_IS_E1x(bp)) 11899 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; 11900 else 11901 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; 11902 11903 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); 11904 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); 11905 cp->irq_arr[1].status_blk = bp->def_status_blk; 11906 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 11907 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; 11908 11909 cp->num_irq = 2; 11910} 11911 11912static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, 11913 void *data) 11914{ 11915 struct bnx2x *bp = netdev_priv(dev); 11916 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11917 11918 if (ops == NULL) 11919 return -EINVAL; 11920 11921 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 11922 if (!bp->cnic_kwq) 11923 return -ENOMEM; 11924 11925 bp->cnic_kwq_cons = bp->cnic_kwq; 11926 bp->cnic_kwq_prod = bp->cnic_kwq; 11927 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; 11928 11929 bp->cnic_spq_pending = 0; 11930 bp->cnic_kwq_pending = 0; 11931 11932 bp->cnic_data = data; 11933 11934 cp->num_irq = 0; 11935 cp->drv_state |= CNIC_DRV_STATE_REGD; 11936 cp->iro_arr = bp->iro_arr; 11937 11938 bnx2x_setup_cnic_irq_info(bp); 11939 11940 rcu_assign_pointer(bp->cnic_ops, ops); 11941 11942 return 0; 11943} 11944 11945static int bnx2x_unregister_cnic(struct net_device *dev) 11946{ 11947 struct bnx2x *bp = netdev_priv(dev); 11948 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11949 11950 mutex_lock(&bp->cnic_mutex); 11951 cp->drv_state = 0; 11952 RCU_INIT_POINTER(bp->cnic_ops, NULL); 11953 mutex_unlock(&bp->cnic_mutex); 11954 synchronize_rcu(); 11955 kfree(bp->cnic_kwq); 11956 bp->cnic_kwq = NULL; 11957 11958 return 0; 11959} 11960 11961struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) 11962{ 11963 struct bnx2x *bp = netdev_priv(dev); 11964 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11965 11966 /* If both iSCSI and FCoE are disabled - return NULL in 11967 * order to indicate CNIC that it should not try to work 11968 * with this device. 11969 */ 11970 if (NO_ISCSI(bp) && NO_FCOE(bp)) 11971 return NULL; 11972 11973 cp->drv_owner = THIS_MODULE; 11974 cp->chip_id = CHIP_ID(bp); 11975 cp->pdev = bp->pdev; 11976 cp->io_base = bp->regview; 11977 cp->io_base2 = bp->doorbells; 11978 cp->max_kwqe_pending = 8; 11979 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; 11980 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 11981 bnx2x_cid_ilt_lines(bp); 11982 cp->ctx_tbl_len = CNIC_ILT_LINES; 11983 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 11984 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 11985 cp->drv_ctl = bnx2x_drv_ctl; 11986 cp->drv_register_cnic = bnx2x_register_cnic; 11987 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 11988 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID; 11989 cp->iscsi_l2_client_id = 11990 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11991 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID; 11992 11993 if (NO_ISCSI_OOO(bp)) 11994 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 11995 11996 if (NO_ISCSI(bp)) 11997 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; 11998 11999 if (NO_FCOE(bp)) 12000 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 12001 12002 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, " 12003 "starting cid %d\n", 12004 cp->ctx_blk_size, 12005 cp->ctx_tbl_offset, 12006 cp->ctx_tbl_len, 12007 cp->starting_cid); 12008 return cp; 12009} 12010EXPORT_SYMBOL(bnx2x_cnic_probe); 12011 12012#endif /* BCM_CNIC */ 12013 12014