bnx2x_main.c revision 889b9af34f986138eebebfe781567cb950b3a22b
1/* bnx2x_main.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2011 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20#include <linux/module.h> 21#include <linux/moduleparam.h> 22#include <linux/kernel.h> 23#include <linux/device.h> /* for dev_info() */ 24#include <linux/timer.h> 25#include <linux/errno.h> 26#include <linux/ioport.h> 27#include <linux/slab.h> 28#include <linux/interrupt.h> 29#include <linux/pci.h> 30#include <linux/init.h> 31#include <linux/netdevice.h> 32#include <linux/etherdevice.h> 33#include <linux/skbuff.h> 34#include <linux/dma-mapping.h> 35#include <linux/bitops.h> 36#include <linux/irq.h> 37#include <linux/delay.h> 38#include <asm/byteorder.h> 39#include <linux/time.h> 40#include <linux/ethtool.h> 41#include <linux/mii.h> 42#include <linux/if.h> 43#include <linux/if_vlan.h> 44#include <net/ip.h> 45#include <net/ipv6.h> 46#include <net/tcp.h> 47#include <net/checksum.h> 48#include <net/ip6_checksum.h> 49#include <linux/workqueue.h> 50#include <linux/crc32.h> 51#include <linux/crc32c.h> 52#include <linux/prefetch.h> 53#include <linux/zlib.h> 54#include <linux/io.h> 55#include <linux/stringify.h> 56#include <linux/vmalloc.h> 57 58#include "bnx2x.h" 59#include "bnx2x_init.h" 60#include "bnx2x_init_ops.h" 61#include "bnx2x_cmn.h" 62#include "bnx2x_dcb.h" 63#include "bnx2x_sp.h" 64 65#include <linux/firmware.h> 66#include "bnx2x_fw_file_hdr.h" 67/* FW files */ 68#define FW_FILE_VERSION \ 69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 72 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 73#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 74#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 75#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 76 77/* Time in jiffies before concluding the transmitter is hung */ 78#define TX_TIMEOUT (5*HZ) 79 80static char version[] __devinitdata = 81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " 82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 83 84MODULE_AUTHOR("Eliezer Tamir"); 85MODULE_DESCRIPTION("Broadcom NetXtreme II " 86 "BCM57710/57711/57711E/" 87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 88 "57840/57840_MF Driver"); 89MODULE_LICENSE("GPL"); 90MODULE_VERSION(DRV_MODULE_VERSION); 91MODULE_FIRMWARE(FW_FILE_NAME_E1); 92MODULE_FIRMWARE(FW_FILE_NAME_E1H); 93MODULE_FIRMWARE(FW_FILE_NAME_E2); 94 95static int multi_mode = 1; 96module_param(multi_mode, int, 0); 97MODULE_PARM_DESC(multi_mode, " Multi queue mode " 98 "(0 Disable; 1 Enable (default))"); 99 100int num_queues; 101module_param(num_queues, int, 0); 102MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1" 103 " (default is as a number of CPUs)"); 104 105static int disable_tpa; 106module_param(disable_tpa, int, 0); 107MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 108 109#define INT_MODE_INTx 1 110#define INT_MODE_MSI 2 111static int int_mode; 112module_param(int_mode, int, 0); 113MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 114 "(1 INT#x; 2 MSI)"); 115 116static int dropless_fc; 117module_param(dropless_fc, int, 0); 118MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 119 120static int poll; 121module_param(poll, int, 0); 122MODULE_PARM_DESC(poll, " Use polling (for debug)"); 123 124static int mrrs = -1; 125module_param(mrrs, int, 0); 126MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 127 128static int debug; 129module_param(debug, int, 0); 130MODULE_PARM_DESC(debug, " Default debug msglevel"); 131 132 133 134struct workqueue_struct *bnx2x_wq; 135 136enum bnx2x_board_type { 137 BCM57710 = 0, 138 BCM57711, 139 BCM57711E, 140 BCM57712, 141 BCM57712_MF, 142 BCM57800, 143 BCM57800_MF, 144 BCM57810, 145 BCM57810_MF, 146 BCM57840, 147 BCM57840_MF 148}; 149 150/* indexed by board_type, above */ 151static struct { 152 char *name; 153} board_info[] __devinitdata = { 154 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, 155 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, 156 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, 157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, 158 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, 159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, 160 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, 161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, 162 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, 163 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, 164 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit " 165 "Ethernet Multi Function"} 166}; 167 168#ifndef PCI_DEVICE_ID_NX2_57710 169#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 170#endif 171#ifndef PCI_DEVICE_ID_NX2_57711 172#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 173#endif 174#ifndef PCI_DEVICE_ID_NX2_57711E 175#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 176#endif 177#ifndef PCI_DEVICE_ID_NX2_57712 178#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 179#endif 180#ifndef PCI_DEVICE_ID_NX2_57712_MF 181#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 182#endif 183#ifndef PCI_DEVICE_ID_NX2_57800 184#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 185#endif 186#ifndef PCI_DEVICE_ID_NX2_57800_MF 187#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 188#endif 189#ifndef PCI_DEVICE_ID_NX2_57810 190#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 191#endif 192#ifndef PCI_DEVICE_ID_NX2_57810_MF 193#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 194#endif 195#ifndef PCI_DEVICE_ID_NX2_57840 196#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 197#endif 198#ifndef PCI_DEVICE_ID_NX2_57840_MF 199#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 200#endif 201static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 210 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 211 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, 212 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 213 { 0 } 214}; 215 216MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 217 218/**************************************************************************** 219* General service functions 220****************************************************************************/ 221 222static inline void __storm_memset_dma_mapping(struct bnx2x *bp, 223 u32 addr, dma_addr_t mapping) 224{ 225 REG_WR(bp, addr, U64_LO(mapping)); 226 REG_WR(bp, addr + 4, U64_HI(mapping)); 227} 228 229static inline void storm_memset_spq_addr(struct bnx2x *bp, 230 dma_addr_t mapping, u16 abs_fid) 231{ 232 u32 addr = XSEM_REG_FAST_MEMORY + 233 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 234 235 __storm_memset_dma_mapping(bp, addr, mapping); 236} 237 238static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 239 u16 pf_id) 240{ 241 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 242 pf_id); 243 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 244 pf_id); 245 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 246 pf_id); 247 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 248 pf_id); 249} 250 251static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 252 u8 enable) 253{ 254 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 255 enable); 256 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 257 enable); 258 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 259 enable); 260 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 261 enable); 262} 263 264static inline void storm_memset_eq_data(struct bnx2x *bp, 265 struct event_ring_data *eq_data, 266 u16 pfid) 267{ 268 size_t size = sizeof(struct event_ring_data); 269 270 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 271 272 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 273} 274 275static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 276 u16 pfid) 277{ 278 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 279 REG_WR16(bp, addr, eq_prod); 280} 281 282/* used only at init 283 * locking is done by mcp 284 */ 285static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 286{ 287 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 288 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 289 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 290 PCICFG_VENDOR_ID_OFFSET); 291} 292 293static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 294{ 295 u32 val; 296 297 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 298 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 299 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 300 PCICFG_VENDOR_ID_OFFSET); 301 302 return val; 303} 304 305#define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 306#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 307#define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 308#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 309#define DMAE_DP_DST_NONE "dst_addr [none]" 310 311static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, 312 int msglvl) 313{ 314 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 315 316 switch (dmae->opcode & DMAE_COMMAND_DST) { 317 case DMAE_CMD_DST_PCI: 318 if (src_type == DMAE_CMD_SRC_PCI) 319 DP(msglvl, "DMAE: opcode 0x%08x\n" 320 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 321 "comp_addr [%x:%08x], comp_val 0x%08x\n", 322 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 323 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 324 dmae->comp_addr_hi, dmae->comp_addr_lo, 325 dmae->comp_val); 326 else 327 DP(msglvl, "DMAE: opcode 0x%08x\n" 328 "src [%08x], len [%d*4], dst [%x:%08x]\n" 329 "comp_addr [%x:%08x], comp_val 0x%08x\n", 330 dmae->opcode, dmae->src_addr_lo >> 2, 331 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 332 dmae->comp_addr_hi, dmae->comp_addr_lo, 333 dmae->comp_val); 334 break; 335 case DMAE_CMD_DST_GRC: 336 if (src_type == DMAE_CMD_SRC_PCI) 337 DP(msglvl, "DMAE: opcode 0x%08x\n" 338 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 339 "comp_addr [%x:%08x], comp_val 0x%08x\n", 340 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 341 dmae->len, dmae->dst_addr_lo >> 2, 342 dmae->comp_addr_hi, dmae->comp_addr_lo, 343 dmae->comp_val); 344 else 345 DP(msglvl, "DMAE: opcode 0x%08x\n" 346 "src [%08x], len [%d*4], dst [%08x]\n" 347 "comp_addr [%x:%08x], comp_val 0x%08x\n", 348 dmae->opcode, dmae->src_addr_lo >> 2, 349 dmae->len, dmae->dst_addr_lo >> 2, 350 dmae->comp_addr_hi, dmae->comp_addr_lo, 351 dmae->comp_val); 352 break; 353 default: 354 if (src_type == DMAE_CMD_SRC_PCI) 355 DP(msglvl, "DMAE: opcode 0x%08x\n" 356 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 357 "comp_addr [%x:%08x] comp_val 0x%08x\n", 358 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 359 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 360 dmae->comp_val); 361 else 362 DP(msglvl, "DMAE: opcode 0x%08x\n" 363 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 364 "comp_addr [%x:%08x] comp_val 0x%08x\n", 365 dmae->opcode, dmae->src_addr_lo >> 2, 366 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 367 dmae->comp_val); 368 break; 369 } 370 371} 372 373/* copy command into DMAE command memory and set DMAE command go */ 374void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 375{ 376 u32 cmd_offset; 377 int i; 378 379 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 380 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 381 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 382 383 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n", 384 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); 385 } 386 REG_WR(bp, dmae_reg_go_c[idx], 1); 387} 388 389u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 390{ 391 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 392 DMAE_CMD_C_ENABLE); 393} 394 395u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 396{ 397 return opcode & ~DMAE_CMD_SRC_RESET; 398} 399 400u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 401 bool with_comp, u8 comp_type) 402{ 403 u32 opcode = 0; 404 405 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 406 (dst_type << DMAE_COMMAND_DST_SHIFT)); 407 408 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 409 410 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 411 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | 412 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 413 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 414 415#ifdef __BIG_ENDIAN 416 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 417#else 418 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 419#endif 420 if (with_comp) 421 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 422 return opcode; 423} 424 425static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 426 struct dmae_command *dmae, 427 u8 src_type, u8 dst_type) 428{ 429 memset(dmae, 0, sizeof(struct dmae_command)); 430 431 /* set the opcode */ 432 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 433 true, DMAE_COMP_PCI); 434 435 /* fill in the completion parameters */ 436 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 437 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 438 dmae->comp_val = DMAE_COMP_VAL; 439} 440 441/* issue a dmae command over the init-channel and wailt for completion */ 442static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, 443 struct dmae_command *dmae) 444{ 445 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 446 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 447 int rc = 0; 448 449 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n", 450 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 451 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 452 453 /* 454 * Lock the dmae channel. Disable BHs to prevent a dead-lock 455 * as long as this code is called both from syscall context and 456 * from ndo_set_rx_mode() flow that may be called from BH. 457 */ 458 spin_lock_bh(&bp->dmae_lock); 459 460 /* reset completion */ 461 *wb_comp = 0; 462 463 /* post the command on the channel used for initializations */ 464 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 465 466 /* wait for completion */ 467 udelay(5); 468 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 469 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); 470 471 if (!cnt) { 472 BNX2X_ERR("DMAE timeout!\n"); 473 rc = DMAE_TIMEOUT; 474 goto unlock; 475 } 476 cnt--; 477 udelay(50); 478 } 479 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 480 BNX2X_ERR("DMAE PCI error!\n"); 481 rc = DMAE_PCI_ERROR; 482 } 483 484 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n", 485 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 486 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 487 488unlock: 489 spin_unlock_bh(&bp->dmae_lock); 490 return rc; 491} 492 493void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 494 u32 len32) 495{ 496 struct dmae_command dmae; 497 498 if (!bp->dmae_ready) { 499 u32 *data = bnx2x_sp(bp, wb_data[0]); 500 501 DP(BNX2X_MSG_OFF, 502 "DMAE is not ready (dst_addr %08x len32 %d) using indirect\n", 503 dst_addr, len32); 504 if (CHIP_IS_E1(bp)) 505 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 506 else 507 bnx2x_init_str_wr(bp, dst_addr, data, len32); 508 return; 509 } 510 511 /* set opcode and fixed command fields */ 512 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 513 514 /* fill in addresses and len */ 515 dmae.src_addr_lo = U64_LO(dma_addr); 516 dmae.src_addr_hi = U64_HI(dma_addr); 517 dmae.dst_addr_lo = dst_addr >> 2; 518 dmae.dst_addr_hi = 0; 519 dmae.len = len32; 520 521 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 522 523 /* issue the command and wait for completion */ 524 bnx2x_issue_dmae_with_comp(bp, &dmae); 525} 526 527void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 528{ 529 struct dmae_command dmae; 530 531 if (!bp->dmae_ready) { 532 u32 *data = bnx2x_sp(bp, wb_data[0]); 533 int i; 534 535 if (CHIP_IS_E1(bp)) { 536 DP(BNX2X_MSG_OFF, 537 "DMAE is not ready (src_addr %08x len32 %d) using indirect\n", 538 src_addr, len32); 539 for (i = 0; i < len32; i++) 540 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 541 } else 542 for (i = 0; i < len32; i++) 543 data[i] = REG_RD(bp, src_addr + i*4); 544 545 return; 546 } 547 548 /* set opcode and fixed command fields */ 549 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 550 551 /* fill in addresses and len */ 552 dmae.src_addr_lo = src_addr >> 2; 553 dmae.src_addr_hi = 0; 554 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 555 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 556 dmae.len = len32; 557 558 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 559 560 /* issue the command and wait for completion */ 561 bnx2x_issue_dmae_with_comp(bp, &dmae); 562} 563 564static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 565 u32 addr, u32 len) 566{ 567 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 568 int offset = 0; 569 570 while (len > dmae_wr_max) { 571 bnx2x_write_dmae(bp, phys_addr + offset, 572 addr + offset, dmae_wr_max); 573 offset += dmae_wr_max * 4; 574 len -= dmae_wr_max; 575 } 576 577 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 578} 579 580/* used only for slowpath so not inlined */ 581static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo) 582{ 583 u32 wb_write[2]; 584 585 wb_write[0] = val_hi; 586 wb_write[1] = val_lo; 587 REG_WR_DMAE(bp, reg, wb_write, 2); 588} 589 590#ifdef USE_WB_RD 591static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg) 592{ 593 u32 wb_data[2]; 594 595 REG_RD_DMAE(bp, reg, wb_data, 2); 596 597 return HILO_U64(wb_data[0], wb_data[1]); 598} 599#endif 600 601static int bnx2x_mc_assert(struct bnx2x *bp) 602{ 603 char last_idx; 604 int i, rc = 0; 605 u32 row0, row1, row2, row3; 606 607 /* XSTORM */ 608 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + 609 XSTORM_ASSERT_LIST_INDEX_OFFSET); 610 if (last_idx) 611 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 612 613 /* print the asserts */ 614 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 615 616 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + 617 XSTORM_ASSERT_LIST_OFFSET(i)); 618 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + 619 XSTORM_ASSERT_LIST_OFFSET(i) + 4); 620 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + 621 XSTORM_ASSERT_LIST_OFFSET(i) + 8); 622 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + 623 XSTORM_ASSERT_LIST_OFFSET(i) + 12); 624 625 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 626 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x" 627 " 0x%08x 0x%08x 0x%08x\n", 628 i, row3, row2, row1, row0); 629 rc++; 630 } else { 631 break; 632 } 633 } 634 635 /* TSTORM */ 636 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + 637 TSTORM_ASSERT_LIST_INDEX_OFFSET); 638 if (last_idx) 639 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 640 641 /* print the asserts */ 642 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 643 644 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + 645 TSTORM_ASSERT_LIST_OFFSET(i)); 646 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + 647 TSTORM_ASSERT_LIST_OFFSET(i) + 4); 648 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + 649 TSTORM_ASSERT_LIST_OFFSET(i) + 8); 650 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + 651 TSTORM_ASSERT_LIST_OFFSET(i) + 12); 652 653 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 654 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x" 655 " 0x%08x 0x%08x 0x%08x\n", 656 i, row3, row2, row1, row0); 657 rc++; 658 } else { 659 break; 660 } 661 } 662 663 /* CSTORM */ 664 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + 665 CSTORM_ASSERT_LIST_INDEX_OFFSET); 666 if (last_idx) 667 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 668 669 /* print the asserts */ 670 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 671 672 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + 673 CSTORM_ASSERT_LIST_OFFSET(i)); 674 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + 675 CSTORM_ASSERT_LIST_OFFSET(i) + 4); 676 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + 677 CSTORM_ASSERT_LIST_OFFSET(i) + 8); 678 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + 679 CSTORM_ASSERT_LIST_OFFSET(i) + 12); 680 681 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 682 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x" 683 " 0x%08x 0x%08x 0x%08x\n", 684 i, row3, row2, row1, row0); 685 rc++; 686 } else { 687 break; 688 } 689 } 690 691 /* USTORM */ 692 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + 693 USTORM_ASSERT_LIST_INDEX_OFFSET); 694 if (last_idx) 695 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 696 697 /* print the asserts */ 698 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 699 700 row0 = REG_RD(bp, BAR_USTRORM_INTMEM + 701 USTORM_ASSERT_LIST_OFFSET(i)); 702 row1 = REG_RD(bp, BAR_USTRORM_INTMEM + 703 USTORM_ASSERT_LIST_OFFSET(i) + 4); 704 row2 = REG_RD(bp, BAR_USTRORM_INTMEM + 705 USTORM_ASSERT_LIST_OFFSET(i) + 8); 706 row3 = REG_RD(bp, BAR_USTRORM_INTMEM + 707 USTORM_ASSERT_LIST_OFFSET(i) + 12); 708 709 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 710 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x" 711 " 0x%08x 0x%08x 0x%08x\n", 712 i, row3, row2, row1, row0); 713 rc++; 714 } else { 715 break; 716 } 717 } 718 719 return rc; 720} 721 722void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 723{ 724 u32 addr, val; 725 u32 mark, offset; 726 __be32 data[9]; 727 int word; 728 u32 trace_shmem_base; 729 if (BP_NOMCP(bp)) { 730 BNX2X_ERR("NO MCP - can not dump\n"); 731 return; 732 } 733 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 734 (bp->common.bc_ver & 0xff0000) >> 16, 735 (bp->common.bc_ver & 0xff00) >> 8, 736 (bp->common.bc_ver & 0xff)); 737 738 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 739 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 740 printk("%s" "MCP PC at 0x%x\n", lvl, val); 741 742 if (BP_PATH(bp) == 0) 743 trace_shmem_base = bp->common.shmem_base; 744 else 745 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 746 addr = trace_shmem_base - 0x0800 + 4; 747 mark = REG_RD(bp, addr); 748 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 749 + ((mark + 0x3) & ~0x3) - 0x08000000; 750 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 751 752 printk("%s", lvl); 753 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { 754 for (word = 0; word < 8; word++) 755 data[word] = htonl(REG_RD(bp, offset + 4*word)); 756 data[8] = 0x0; 757 pr_cont("%s", (char *)data); 758 } 759 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 760 for (word = 0; word < 8; word++) 761 data[word] = htonl(REG_RD(bp, offset + 4*word)); 762 data[8] = 0x0; 763 pr_cont("%s", (char *)data); 764 } 765 printk("%s" "end of fw dump\n", lvl); 766} 767 768static inline void bnx2x_fw_dump(struct bnx2x *bp) 769{ 770 bnx2x_fw_dump_lvl(bp, KERN_ERR); 771} 772 773void bnx2x_panic_dump(struct bnx2x *bp) 774{ 775 int i; 776 u16 j; 777 struct hc_sp_status_block_data sp_sb_data; 778 int func = BP_FUNC(bp); 779#ifdef BNX2X_STOP_ON_ERROR 780 u16 start = 0, end = 0; 781 u8 cos; 782#endif 783 784 bp->stats_state = STATS_STATE_DISABLED; 785 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 786 787 BNX2X_ERR("begin crash dump -----------------\n"); 788 789 /* Indices */ 790 /* Common */ 791 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)" 792 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 793 bp->def_idx, bp->def_att_idx, bp->attn_state, 794 bp->spq_prod_idx, bp->stats_counter); 795 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 796 bp->def_status_blk->atten_status_block.attn_bits, 797 bp->def_status_blk->atten_status_block.attn_bits_ack, 798 bp->def_status_blk->atten_status_block.status_block_id, 799 bp->def_status_blk->atten_status_block.attn_bits_index); 800 BNX2X_ERR(" def ("); 801 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 802 pr_cont("0x%x%s", 803 bp->def_status_blk->sp_sb.index_values[i], 804 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 805 806 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 807 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + 808 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 809 i*sizeof(u32)); 810 811 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 812 sp_sb_data.igu_sb_id, 813 sp_sb_data.igu_seg_id, 814 sp_sb_data.p_func.pf_id, 815 sp_sb_data.p_func.vnic_id, 816 sp_sb_data.p_func.vf_id, 817 sp_sb_data.p_func.vf_valid, 818 sp_sb_data.state); 819 820 821 for_each_eth_queue(bp, i) { 822 struct bnx2x_fastpath *fp = &bp->fp[i]; 823 int loop; 824 struct hc_status_block_data_e2 sb_data_e2; 825 struct hc_status_block_data_e1x sb_data_e1x; 826 struct hc_status_block_sm *hc_sm_p = 827 CHIP_IS_E1x(bp) ? 828 sb_data_e1x.common.state_machine : 829 sb_data_e2.common.state_machine; 830 struct hc_index_data *hc_index_p = 831 CHIP_IS_E1x(bp) ? 832 sb_data_e1x.index_data : 833 sb_data_e2.index_data; 834 u8 data_size, cos; 835 u32 *sb_data_p; 836 struct bnx2x_fp_txdata txdata; 837 838 /* Rx */ 839 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)" 840 " rx_comp_prod(0x%x)" 841 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 842 i, fp->rx_bd_prod, fp->rx_bd_cons, 843 fp->rx_comp_prod, 844 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 845 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)" 846 " fp_hc_idx(0x%x)\n", 847 fp->rx_sge_prod, fp->last_max_sge, 848 le16_to_cpu(fp->fp_hc_idx)); 849 850 /* Tx */ 851 for_each_cos_in_tx_queue(fp, cos) 852 { 853 txdata = fp->txdata[cos]; 854 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)" 855 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)" 856 " *tx_cons_sb(0x%x)\n", 857 i, txdata.tx_pkt_prod, 858 txdata.tx_pkt_cons, txdata.tx_bd_prod, 859 txdata.tx_bd_cons, 860 le16_to_cpu(*txdata.tx_cons_sb)); 861 } 862 863 loop = CHIP_IS_E1x(bp) ? 864 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 865 866 /* host sb data */ 867 868#ifdef BCM_CNIC 869 if (IS_FCOE_FP(fp)) 870 continue; 871#endif 872 BNX2X_ERR(" run indexes ("); 873 for (j = 0; j < HC_SB_MAX_SM; j++) 874 pr_cont("0x%x%s", 875 fp->sb_running_index[j], 876 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 877 878 BNX2X_ERR(" indexes ("); 879 for (j = 0; j < loop; j++) 880 pr_cont("0x%x%s", 881 fp->sb_index_values[j], 882 (j == loop - 1) ? ")" : " "); 883 /* fw sb data */ 884 data_size = CHIP_IS_E1x(bp) ? 885 sizeof(struct hc_status_block_data_e1x) : 886 sizeof(struct hc_status_block_data_e2); 887 data_size /= sizeof(u32); 888 sb_data_p = CHIP_IS_E1x(bp) ? 889 (u32 *)&sb_data_e1x : 890 (u32 *)&sb_data_e2; 891 /* copy sb data in here */ 892 for (j = 0; j < data_size; j++) 893 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 894 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 895 j * sizeof(u32)); 896 897 if (!CHIP_IS_E1x(bp)) { 898 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 899 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 900 "state(0x%x)\n", 901 sb_data_e2.common.p_func.pf_id, 902 sb_data_e2.common.p_func.vf_id, 903 sb_data_e2.common.p_func.vf_valid, 904 sb_data_e2.common.p_func.vnic_id, 905 sb_data_e2.common.same_igu_sb_1b, 906 sb_data_e2.common.state); 907 } else { 908 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 909 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 910 "state(0x%x)\n", 911 sb_data_e1x.common.p_func.pf_id, 912 sb_data_e1x.common.p_func.vf_id, 913 sb_data_e1x.common.p_func.vf_valid, 914 sb_data_e1x.common.p_func.vnic_id, 915 sb_data_e1x.common.same_igu_sb_1b, 916 sb_data_e1x.common.state); 917 } 918 919 /* SB_SMs data */ 920 for (j = 0; j < HC_SB_MAX_SM; j++) { 921 pr_cont("SM[%d] __flags (0x%x) " 922 "igu_sb_id (0x%x) igu_seg_id(0x%x) " 923 "time_to_expire (0x%x) " 924 "timer_value(0x%x)\n", j, 925 hc_sm_p[j].__flags, 926 hc_sm_p[j].igu_sb_id, 927 hc_sm_p[j].igu_seg_id, 928 hc_sm_p[j].time_to_expire, 929 hc_sm_p[j].timer_value); 930 } 931 932 /* Indecies data */ 933 for (j = 0; j < loop; j++) { 934 pr_cont("INDEX[%d] flags (0x%x) " 935 "timeout (0x%x)\n", j, 936 hc_index_p[j].flags, 937 hc_index_p[j].timeout); 938 } 939 } 940 941#ifdef BNX2X_STOP_ON_ERROR 942 /* Rings */ 943 /* Rx */ 944 for_each_rx_queue(bp, i) { 945 struct bnx2x_fastpath *fp = &bp->fp[i]; 946 947 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 948 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 949 for (j = start; j != end; j = RX_BD(j + 1)) { 950 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 951 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 952 953 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 954 i, j, rx_bd[1], rx_bd[0], sw_bd->data); 955 } 956 957 start = RX_SGE(fp->rx_sge_prod); 958 end = RX_SGE(fp->last_max_sge); 959 for (j = start; j != end; j = RX_SGE(j + 1)) { 960 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 961 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 962 963 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 964 i, j, rx_sge[1], rx_sge[0], sw_page->page); 965 } 966 967 start = RCQ_BD(fp->rx_comp_cons - 10); 968 end = RCQ_BD(fp->rx_comp_cons + 503); 969 for (j = start; j != end; j = RCQ_BD(j + 1)) { 970 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 971 972 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 973 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 974 } 975 } 976 977 /* Tx */ 978 for_each_tx_queue(bp, i) { 979 struct bnx2x_fastpath *fp = &bp->fp[i]; 980 for_each_cos_in_tx_queue(fp, cos) { 981 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; 982 983 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 984 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 985 for (j = start; j != end; j = TX_BD(j + 1)) { 986 struct sw_tx_bd *sw_bd = 987 &txdata->tx_buf_ring[j]; 988 989 BNX2X_ERR("fp%d: txdata %d, " 990 "packet[%x]=[%p,%x]\n", 991 i, cos, j, sw_bd->skb, 992 sw_bd->first_bd); 993 } 994 995 start = TX_BD(txdata->tx_bd_cons - 10); 996 end = TX_BD(txdata->tx_bd_cons + 254); 997 for (j = start; j != end; j = TX_BD(j + 1)) { 998 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 999 1000 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=" 1001 "[%x:%x:%x:%x]\n", 1002 i, cos, j, tx_bd[0], tx_bd[1], 1003 tx_bd[2], tx_bd[3]); 1004 } 1005 } 1006 } 1007#endif 1008 bnx2x_fw_dump(bp); 1009 bnx2x_mc_assert(bp); 1010 BNX2X_ERR("end crash dump -----------------\n"); 1011} 1012 1013/* 1014 * FLR Support for E2 1015 * 1016 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 1017 * initialization. 1018 */ 1019#define FLR_WAIT_USEC 10000 /* 10 miliseconds */ 1020#define FLR_WAIT_INTERVAL 50 /* usec */ 1021#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ 1022 1023struct pbf_pN_buf_regs { 1024 int pN; 1025 u32 init_crd; 1026 u32 crd; 1027 u32 crd_freed; 1028}; 1029 1030struct pbf_pN_cmd_regs { 1031 int pN; 1032 u32 lines_occup; 1033 u32 lines_freed; 1034}; 1035 1036static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1037 struct pbf_pN_buf_regs *regs, 1038 u32 poll_count) 1039{ 1040 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1041 u32 cur_cnt = poll_count; 1042 1043 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1044 crd = crd_start = REG_RD(bp, regs->crd); 1045 init_crd = REG_RD(bp, regs->init_crd); 1046 1047 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1048 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1049 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1050 1051 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1052 (init_crd - crd_start))) { 1053 if (cur_cnt--) { 1054 udelay(FLR_WAIT_INTERVAL); 1055 crd = REG_RD(bp, regs->crd); 1056 crd_freed = REG_RD(bp, regs->crd_freed); 1057 } else { 1058 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1059 regs->pN); 1060 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1061 regs->pN, crd); 1062 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1063 regs->pN, crd_freed); 1064 break; 1065 } 1066 } 1067 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1068 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1069} 1070 1071static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1072 struct pbf_pN_cmd_regs *regs, 1073 u32 poll_count) 1074{ 1075 u32 occup, to_free, freed, freed_start; 1076 u32 cur_cnt = poll_count; 1077 1078 occup = to_free = REG_RD(bp, regs->lines_occup); 1079 freed = freed_start = REG_RD(bp, regs->lines_freed); 1080 1081 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1082 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1083 1084 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1085 if (cur_cnt--) { 1086 udelay(FLR_WAIT_INTERVAL); 1087 occup = REG_RD(bp, regs->lines_occup); 1088 freed = REG_RD(bp, regs->lines_freed); 1089 } else { 1090 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1091 regs->pN); 1092 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1093 regs->pN, occup); 1094 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1095 regs->pN, freed); 1096 break; 1097 } 1098 } 1099 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1100 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1101} 1102 1103static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1104 u32 expected, u32 poll_count) 1105{ 1106 u32 cur_cnt = poll_count; 1107 u32 val; 1108 1109 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1110 udelay(FLR_WAIT_INTERVAL); 1111 1112 return val; 1113} 1114 1115static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1116 char *msg, u32 poll_cnt) 1117{ 1118 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1119 if (val != 0) { 1120 BNX2X_ERR("%s usage count=%d\n", msg, val); 1121 return 1; 1122 } 1123 return 0; 1124} 1125 1126static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1127{ 1128 /* adjust polling timeout */ 1129 if (CHIP_REV_IS_EMUL(bp)) 1130 return FLR_POLL_CNT * 2000; 1131 1132 if (CHIP_REV_IS_FPGA(bp)) 1133 return FLR_POLL_CNT * 120; 1134 1135 return FLR_POLL_CNT; 1136} 1137 1138static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1139{ 1140 struct pbf_pN_cmd_regs cmd_regs[] = { 1141 {0, (CHIP_IS_E3B0(bp)) ? 1142 PBF_REG_TQ_OCCUPANCY_Q0 : 1143 PBF_REG_P0_TQ_OCCUPANCY, 1144 (CHIP_IS_E3B0(bp)) ? 1145 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1146 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1147 {1, (CHIP_IS_E3B0(bp)) ? 1148 PBF_REG_TQ_OCCUPANCY_Q1 : 1149 PBF_REG_P1_TQ_OCCUPANCY, 1150 (CHIP_IS_E3B0(bp)) ? 1151 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1152 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1153 {4, (CHIP_IS_E3B0(bp)) ? 1154 PBF_REG_TQ_OCCUPANCY_LB_Q : 1155 PBF_REG_P4_TQ_OCCUPANCY, 1156 (CHIP_IS_E3B0(bp)) ? 1157 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1158 PBF_REG_P4_TQ_LINES_FREED_CNT} 1159 }; 1160 1161 struct pbf_pN_buf_regs buf_regs[] = { 1162 {0, (CHIP_IS_E3B0(bp)) ? 1163 PBF_REG_INIT_CRD_Q0 : 1164 PBF_REG_P0_INIT_CRD , 1165 (CHIP_IS_E3B0(bp)) ? 1166 PBF_REG_CREDIT_Q0 : 1167 PBF_REG_P0_CREDIT, 1168 (CHIP_IS_E3B0(bp)) ? 1169 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1170 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1171 {1, (CHIP_IS_E3B0(bp)) ? 1172 PBF_REG_INIT_CRD_Q1 : 1173 PBF_REG_P1_INIT_CRD, 1174 (CHIP_IS_E3B0(bp)) ? 1175 PBF_REG_CREDIT_Q1 : 1176 PBF_REG_P1_CREDIT, 1177 (CHIP_IS_E3B0(bp)) ? 1178 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1179 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1180 {4, (CHIP_IS_E3B0(bp)) ? 1181 PBF_REG_INIT_CRD_LB_Q : 1182 PBF_REG_P4_INIT_CRD, 1183 (CHIP_IS_E3B0(bp)) ? 1184 PBF_REG_CREDIT_LB_Q : 1185 PBF_REG_P4_CREDIT, 1186 (CHIP_IS_E3B0(bp)) ? 1187 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1188 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1189 }; 1190 1191 int i; 1192 1193 /* Verify the command queues are flushed P0, P1, P4 */ 1194 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1195 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1196 1197 1198 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1199 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1200 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1201} 1202 1203#define OP_GEN_PARAM(param) \ 1204 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1205 1206#define OP_GEN_TYPE(type) \ 1207 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1208 1209#define OP_GEN_AGG_VECT(index) \ 1210 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1211 1212 1213static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, 1214 u32 poll_cnt) 1215{ 1216 struct sdm_op_gen op_gen = {0}; 1217 1218 u32 comp_addr = BAR_CSTRORM_INTMEM + 1219 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1220 int ret = 0; 1221 1222 if (REG_RD(bp, comp_addr)) { 1223 BNX2X_ERR("Cleanup complete was not 0 before sending\n"); 1224 return 1; 1225 } 1226 1227 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1228 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1229 op_gen.command |= OP_GEN_AGG_VECT(clnup_func); 1230 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1231 1232 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); 1233 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); 1234 1235 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1236 BNX2X_ERR("FW final cleanup did not succeed\n"); 1237 ret = 1; 1238 } 1239 /* Zero completion for nxt FLR */ 1240 REG_WR(bp, comp_addr, 0); 1241 1242 return ret; 1243} 1244 1245static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1246{ 1247 int pos; 1248 u16 status; 1249 1250 pos = pci_pcie_cap(dev); 1251 if (!pos) 1252 return false; 1253 1254 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 1255 return status & PCI_EXP_DEVSTA_TRPND; 1256} 1257 1258/* PF FLR specific routines 1259*/ 1260static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1261{ 1262 1263 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1264 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1265 CFC_REG_NUM_LCIDS_INSIDE_PF, 1266 "CFC PF usage counter timed out", 1267 poll_cnt)) 1268 return 1; 1269 1270 1271 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1272 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1273 DORQ_REG_PF_USAGE_CNT, 1274 "DQ PF usage counter timed out", 1275 poll_cnt)) 1276 return 1; 1277 1278 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1279 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1280 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1281 "QM PF usage counter timed out", 1282 poll_cnt)) 1283 return 1; 1284 1285 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1286 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1287 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1288 "Timers VNIC usage counter timed out", 1289 poll_cnt)) 1290 return 1; 1291 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1292 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1293 "Timers NUM_SCANS usage counter timed out", 1294 poll_cnt)) 1295 return 1; 1296 1297 /* Wait DMAE PF usage counter to zero */ 1298 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1299 dmae_reg_go_c[INIT_DMAE_C(bp)], 1300 "DMAE dommand register timed out", 1301 poll_cnt)) 1302 return 1; 1303 1304 return 0; 1305} 1306 1307static void bnx2x_hw_enable_status(struct bnx2x *bp) 1308{ 1309 u32 val; 1310 1311 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1312 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1313 1314 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1315 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1316 1317 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1318 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1319 1320 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1321 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1322 1323 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1324 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1325 1326 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1327 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1328 1329 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1330 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1331 1332 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1333 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1334 val); 1335} 1336 1337static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1338{ 1339 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1340 1341 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1342 1343 /* Re-enable PF target read access */ 1344 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1345 1346 /* Poll HW usage counters */ 1347 DP(BNX2X_MSG_SP, "Polling usage counters\n"); 1348 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1349 return -EBUSY; 1350 1351 /* Zero the igu 'trailing edge' and 'leading edge' */ 1352 1353 /* Send the FW cleanup command */ 1354 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1355 return -EBUSY; 1356 1357 /* ATC cleanup */ 1358 1359 /* Verify TX hw is flushed */ 1360 bnx2x_tx_hw_flushed(bp, poll_cnt); 1361 1362 /* Wait 100ms (not adjusted according to platform) */ 1363 msleep(100); 1364 1365 /* Verify no pending pci transactions */ 1366 if (bnx2x_is_pcie_pending(bp->pdev)) 1367 BNX2X_ERR("PCIE Transactions still pending\n"); 1368 1369 /* Debug */ 1370 bnx2x_hw_enable_status(bp); 1371 1372 /* 1373 * Master enable - Due to WB DMAE writes performed before this 1374 * register is re-initialized as part of the regular function init 1375 */ 1376 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1377 1378 return 0; 1379} 1380 1381static void bnx2x_hc_int_enable(struct bnx2x *bp) 1382{ 1383 int port = BP_PORT(bp); 1384 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1385 u32 val = REG_RD(bp, addr); 1386 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1387 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1388 1389 if (msix) { 1390 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1391 HC_CONFIG_0_REG_INT_LINE_EN_0); 1392 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1393 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1394 } else if (msi) { 1395 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1396 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1397 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1398 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1399 } else { 1400 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1401 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1402 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1403 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1404 1405 if (!CHIP_IS_E1(bp)) { 1406 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1407 val, port, addr); 1408 1409 REG_WR(bp, addr, val); 1410 1411 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1412 } 1413 } 1414 1415 if (CHIP_IS_E1(bp)) 1416 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1417 1418 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", 1419 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1420 1421 REG_WR(bp, addr, val); 1422 /* 1423 * Ensure that HC_CONFIG is written before leading/trailing edge config 1424 */ 1425 mmiowb(); 1426 barrier(); 1427 1428 if (!CHIP_IS_E1(bp)) { 1429 /* init leading/trailing edge */ 1430 if (IS_MF(bp)) { 1431 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1432 if (bp->port.pmf) 1433 /* enable nig and gpio3 attention */ 1434 val |= 0x1100; 1435 } else 1436 val = 0xffff; 1437 1438 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1439 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1440 } 1441 1442 /* Make sure that interrupts are indeed enabled from here on */ 1443 mmiowb(); 1444} 1445 1446static void bnx2x_igu_int_enable(struct bnx2x *bp) 1447{ 1448 u32 val; 1449 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1450 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1451 1452 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1453 1454 if (msix) { 1455 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1456 IGU_PF_CONF_SINGLE_ISR_EN); 1457 val |= (IGU_PF_CONF_FUNC_EN | 1458 IGU_PF_CONF_MSI_MSIX_EN | 1459 IGU_PF_CONF_ATTN_BIT_EN); 1460 } else if (msi) { 1461 val &= ~IGU_PF_CONF_INT_LINE_EN; 1462 val |= (IGU_PF_CONF_FUNC_EN | 1463 IGU_PF_CONF_MSI_MSIX_EN | 1464 IGU_PF_CONF_ATTN_BIT_EN | 1465 IGU_PF_CONF_SINGLE_ISR_EN); 1466 } else { 1467 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1468 val |= (IGU_PF_CONF_FUNC_EN | 1469 IGU_PF_CONF_INT_LINE_EN | 1470 IGU_PF_CONF_ATTN_BIT_EN | 1471 IGU_PF_CONF_SINGLE_ISR_EN); 1472 } 1473 1474 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n", 1475 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1476 1477 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1478 1479 barrier(); 1480 1481 /* init leading/trailing edge */ 1482 if (IS_MF(bp)) { 1483 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1484 if (bp->port.pmf) 1485 /* enable nig and gpio3 attention */ 1486 val |= 0x1100; 1487 } else 1488 val = 0xffff; 1489 1490 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1491 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1492 1493 /* Make sure that interrupts are indeed enabled from here on */ 1494 mmiowb(); 1495} 1496 1497void bnx2x_int_enable(struct bnx2x *bp) 1498{ 1499 if (bp->common.int_block == INT_BLOCK_HC) 1500 bnx2x_hc_int_enable(bp); 1501 else 1502 bnx2x_igu_int_enable(bp); 1503} 1504 1505static void bnx2x_hc_int_disable(struct bnx2x *bp) 1506{ 1507 int port = BP_PORT(bp); 1508 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1509 u32 val = REG_RD(bp, addr); 1510 1511 /* 1512 * in E1 we must use only PCI configuration space to disable 1513 * MSI/MSIX capablility 1514 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 1515 */ 1516 if (CHIP_IS_E1(bp)) { 1517 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 1518 * Use mask register to prevent from HC sending interrupts 1519 * after we exit the function 1520 */ 1521 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 1522 1523 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1524 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1525 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1526 } else 1527 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1528 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1529 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1530 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1531 1532 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1533 val, port, addr); 1534 1535 /* flush all outstanding writes */ 1536 mmiowb(); 1537 1538 REG_WR(bp, addr, val); 1539 if (REG_RD(bp, addr) != val) 1540 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1541} 1542 1543static void bnx2x_igu_int_disable(struct bnx2x *bp) 1544{ 1545 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1546 1547 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 1548 IGU_PF_CONF_INT_LINE_EN | 1549 IGU_PF_CONF_ATTN_BIT_EN); 1550 1551 DP(NETIF_MSG_INTR, "write %x to IGU\n", val); 1552 1553 /* flush all outstanding writes */ 1554 mmiowb(); 1555 1556 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1557 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 1558 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1559} 1560 1561void bnx2x_int_disable(struct bnx2x *bp) 1562{ 1563 if (bp->common.int_block == INT_BLOCK_HC) 1564 bnx2x_hc_int_disable(bp); 1565 else 1566 bnx2x_igu_int_disable(bp); 1567} 1568 1569void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1570{ 1571 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1572 int i, offset; 1573 1574 if (disable_hw) 1575 /* prevent the HW from sending interrupts */ 1576 bnx2x_int_disable(bp); 1577 1578 /* make sure all ISRs are done */ 1579 if (msix) { 1580 synchronize_irq(bp->msix_table[0].vector); 1581 offset = 1; 1582#ifdef BCM_CNIC 1583 offset++; 1584#endif 1585 for_each_eth_queue(bp, i) 1586 synchronize_irq(bp->msix_table[offset++].vector); 1587 } else 1588 synchronize_irq(bp->pdev->irq); 1589 1590 /* make sure sp_task is not running */ 1591 cancel_delayed_work(&bp->sp_task); 1592 cancel_delayed_work(&bp->period_task); 1593 flush_workqueue(bnx2x_wq); 1594} 1595 1596/* fast path */ 1597 1598/* 1599 * General service functions 1600 */ 1601 1602/* Return true if succeeded to acquire the lock */ 1603static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1604{ 1605 u32 lock_status; 1606 u32 resource_bit = (1 << resource); 1607 int func = BP_FUNC(bp); 1608 u32 hw_lock_control_reg; 1609 1610 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource); 1611 1612 /* Validating that the resource is within range */ 1613 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1614 DP(NETIF_MSG_HW, 1615 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1616 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1617 return false; 1618 } 1619 1620 if (func <= 5) 1621 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1622 else 1623 hw_lock_control_reg = 1624 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1625 1626 /* Try to acquire the lock */ 1627 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1628 lock_status = REG_RD(bp, hw_lock_control_reg); 1629 if (lock_status & resource_bit) 1630 return true; 1631 1632 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource); 1633 return false; 1634} 1635 1636/** 1637 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1638 * 1639 * @bp: driver handle 1640 * 1641 * Returns the recovery leader resource id according to the engine this function 1642 * belongs to. Currently only only 2 engines is supported. 1643 */ 1644static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1645{ 1646 if (BP_PATH(bp)) 1647 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1648 else 1649 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1650} 1651 1652/** 1653 * bnx2x_trylock_leader_lock- try to aquire a leader lock. 1654 * 1655 * @bp: driver handle 1656 * 1657 * Tries to aquire a leader lock for cuurent engine. 1658 */ 1659static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1660{ 1661 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1662} 1663 1664#ifdef BCM_CNIC 1665static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1666#endif 1667 1668void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1669{ 1670 struct bnx2x *bp = fp->bp; 1671 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1672 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1673 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1674 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj; 1675 1676 DP(BNX2X_MSG_SP, 1677 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1678 fp->index, cid, command, bp->state, 1679 rr_cqe->ramrod_cqe.ramrod_type); 1680 1681 switch (command) { 1682 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1683 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1684 drv_cmd = BNX2X_Q_CMD_UPDATE; 1685 break; 1686 1687 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1688 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1689 drv_cmd = BNX2X_Q_CMD_SETUP; 1690 break; 1691 1692 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1693 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1694 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1695 break; 1696 1697 case (RAMROD_CMD_ID_ETH_HALT): 1698 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1699 drv_cmd = BNX2X_Q_CMD_HALT; 1700 break; 1701 1702 case (RAMROD_CMD_ID_ETH_TERMINATE): 1703 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); 1704 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1705 break; 1706 1707 case (RAMROD_CMD_ID_ETH_EMPTY): 1708 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1709 drv_cmd = BNX2X_Q_CMD_EMPTY; 1710 break; 1711 1712 default: 1713 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1714 command, fp->index); 1715 return; 1716 } 1717 1718 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1719 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1720 /* q_obj->complete_cmd() failure means that this was 1721 * an unexpected completion. 1722 * 1723 * In this case we don't want to increase the bp->spq_left 1724 * because apparently we haven't sent this command the first 1725 * place. 1726 */ 1727#ifdef BNX2X_STOP_ON_ERROR 1728 bnx2x_panic(); 1729#else 1730 return; 1731#endif 1732 1733 smp_mb__before_atomic_inc(); 1734 atomic_inc(&bp->cq_spq_left); 1735 /* push the change in bp->spq_left and towards the memory */ 1736 smp_mb__after_atomic_inc(); 1737 1738 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1739 1740 return; 1741} 1742 1743void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 1744 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) 1745{ 1746 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; 1747 1748 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, 1749 start); 1750} 1751 1752irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1753{ 1754 struct bnx2x *bp = netdev_priv(dev_instance); 1755 u16 status = bnx2x_ack_int(bp); 1756 u16 mask; 1757 int i; 1758 u8 cos; 1759 1760 /* Return here if interrupt is shared and it's not for us */ 1761 if (unlikely(status == 0)) { 1762 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1763 return IRQ_NONE; 1764 } 1765 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1766 1767#ifdef BNX2X_STOP_ON_ERROR 1768 if (unlikely(bp->panic)) 1769 return IRQ_HANDLED; 1770#endif 1771 1772 for_each_eth_queue(bp, i) { 1773 struct bnx2x_fastpath *fp = &bp->fp[i]; 1774 1775 mask = 0x2 << (fp->index + CNIC_PRESENT); 1776 if (status & mask) { 1777 /* Handle Rx or Tx according to SB id */ 1778 prefetch(fp->rx_cons_sb); 1779 for_each_cos_in_tx_queue(fp, cos) 1780 prefetch(fp->txdata[cos].tx_cons_sb); 1781 prefetch(&fp->sb_running_index[SM_RX_ID]); 1782 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 1783 status &= ~mask; 1784 } 1785 } 1786 1787#ifdef BCM_CNIC 1788 mask = 0x2; 1789 if (status & (mask | 0x1)) { 1790 struct cnic_ops *c_ops = NULL; 1791 1792 if (likely(bp->state == BNX2X_STATE_OPEN)) { 1793 rcu_read_lock(); 1794 c_ops = rcu_dereference(bp->cnic_ops); 1795 if (c_ops) 1796 c_ops->cnic_handler(bp->cnic_data, NULL); 1797 rcu_read_unlock(); 1798 } 1799 1800 status &= ~mask; 1801 } 1802#endif 1803 1804 if (unlikely(status & 0x1)) { 1805 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1806 1807 status &= ~0x1; 1808 if (!status) 1809 return IRQ_HANDLED; 1810 } 1811 1812 if (unlikely(status)) 1813 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1814 status); 1815 1816 return IRQ_HANDLED; 1817} 1818 1819/* Link */ 1820 1821/* 1822 * General service functions 1823 */ 1824 1825int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 1826{ 1827 u32 lock_status; 1828 u32 resource_bit = (1 << resource); 1829 int func = BP_FUNC(bp); 1830 u32 hw_lock_control_reg; 1831 int cnt; 1832 1833 /* Validating that the resource is within range */ 1834 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1835 DP(NETIF_MSG_HW, 1836 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1837 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1838 return -EINVAL; 1839 } 1840 1841 if (func <= 5) { 1842 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1843 } else { 1844 hw_lock_control_reg = 1845 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1846 } 1847 1848 /* Validating that the resource is not already taken */ 1849 lock_status = REG_RD(bp, hw_lock_control_reg); 1850 if (lock_status & resource_bit) { 1851 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1852 lock_status, resource_bit); 1853 return -EEXIST; 1854 } 1855 1856 /* Try for 5 second every 5ms */ 1857 for (cnt = 0; cnt < 1000; cnt++) { 1858 /* Try to acquire the lock */ 1859 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1860 lock_status = REG_RD(bp, hw_lock_control_reg); 1861 if (lock_status & resource_bit) 1862 return 0; 1863 1864 msleep(5); 1865 } 1866 DP(NETIF_MSG_HW, "Timeout\n"); 1867 return -EAGAIN; 1868} 1869 1870int bnx2x_release_leader_lock(struct bnx2x *bp) 1871{ 1872 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1873} 1874 1875int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 1876{ 1877 u32 lock_status; 1878 u32 resource_bit = (1 << resource); 1879 int func = BP_FUNC(bp); 1880 u32 hw_lock_control_reg; 1881 1882 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource); 1883 1884 /* Validating that the resource is within range */ 1885 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1886 DP(NETIF_MSG_HW, 1887 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1888 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1889 return -EINVAL; 1890 } 1891 1892 if (func <= 5) { 1893 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1894 } else { 1895 hw_lock_control_reg = 1896 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1897 } 1898 1899 /* Validating that the resource is currently taken */ 1900 lock_status = REG_RD(bp, hw_lock_control_reg); 1901 if (!(lock_status & resource_bit)) { 1902 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1903 lock_status, resource_bit); 1904 return -EFAULT; 1905 } 1906 1907 REG_WR(bp, hw_lock_control_reg, resource_bit); 1908 return 0; 1909} 1910 1911 1912int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 1913{ 1914 /* The GPIO should be swapped if swap register is set and active */ 1915 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1916 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1917 int gpio_shift = gpio_num + 1918 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1919 u32 gpio_mask = (1 << gpio_shift); 1920 u32 gpio_reg; 1921 int value; 1922 1923 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1924 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1925 return -EINVAL; 1926 } 1927 1928 /* read GPIO value */ 1929 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1930 1931 /* get the requested pin value */ 1932 if ((gpio_reg & gpio_mask) == gpio_mask) 1933 value = 1; 1934 else 1935 value = 0; 1936 1937 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); 1938 1939 return value; 1940} 1941 1942int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 1943{ 1944 /* The GPIO should be swapped if swap register is set and active */ 1945 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1946 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1947 int gpio_shift = gpio_num + 1948 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1949 u32 gpio_mask = (1 << gpio_shift); 1950 u32 gpio_reg; 1951 1952 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1953 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1954 return -EINVAL; 1955 } 1956 1957 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1958 /* read GPIO and mask except the float bits */ 1959 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 1960 1961 switch (mode) { 1962 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1963 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n", 1964 gpio_num, gpio_shift); 1965 /* clear FLOAT and set CLR */ 1966 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1967 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 1968 break; 1969 1970 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 1971 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n", 1972 gpio_num, gpio_shift); 1973 /* clear FLOAT and set SET */ 1974 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1975 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 1976 break; 1977 1978 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 1979 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", 1980 gpio_num, gpio_shift); 1981 /* set FLOAT */ 1982 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1983 break; 1984 1985 default: 1986 break; 1987 } 1988 1989 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 1990 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1991 1992 return 0; 1993} 1994 1995int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 1996{ 1997 u32 gpio_reg = 0; 1998 int rc = 0; 1999 2000 /* Any port swapping should be handled by caller. */ 2001 2002 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2003 /* read GPIO and mask except the float bits */ 2004 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 2005 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2006 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 2007 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 2008 2009 switch (mode) { 2010 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2011 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 2012 /* set CLR */ 2013 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2014 break; 2015 2016 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2017 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 2018 /* set SET */ 2019 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2020 break; 2021 2022 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2023 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2024 /* set FLOAT */ 2025 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2026 break; 2027 2028 default: 2029 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2030 rc = -EINVAL; 2031 break; 2032 } 2033 2034 if (rc == 0) 2035 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2036 2037 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2038 2039 return rc; 2040} 2041 2042int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2043{ 2044 /* The GPIO should be swapped if swap register is set and active */ 2045 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2046 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2047 int gpio_shift = gpio_num + 2048 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2049 u32 gpio_mask = (1 << gpio_shift); 2050 u32 gpio_reg; 2051 2052 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2053 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2054 return -EINVAL; 2055 } 2056 2057 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2058 /* read GPIO int */ 2059 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2060 2061 switch (mode) { 2062 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2063 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> " 2064 "output low\n", gpio_num, gpio_shift); 2065 /* clear SET and set CLR */ 2066 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2067 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2068 break; 2069 2070 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2071 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> " 2072 "output high\n", gpio_num, gpio_shift); 2073 /* clear CLR and set SET */ 2074 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2075 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2076 break; 2077 2078 default: 2079 break; 2080 } 2081 2082 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2083 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2084 2085 return 0; 2086} 2087 2088static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) 2089{ 2090 u32 spio_mask = (1 << spio_num); 2091 u32 spio_reg; 2092 2093 if ((spio_num < MISC_REGISTERS_SPIO_4) || 2094 (spio_num > MISC_REGISTERS_SPIO_7)) { 2095 BNX2X_ERR("Invalid SPIO %d\n", spio_num); 2096 return -EINVAL; 2097 } 2098 2099 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2100 /* read SPIO and mask except the float bits */ 2101 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); 2102 2103 switch (mode) { 2104 case MISC_REGISTERS_SPIO_OUTPUT_LOW: 2105 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); 2106 /* clear FLOAT and set CLR */ 2107 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2108 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); 2109 break; 2110 2111 case MISC_REGISTERS_SPIO_OUTPUT_HIGH: 2112 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); 2113 /* clear FLOAT and set SET */ 2114 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2115 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); 2116 break; 2117 2118 case MISC_REGISTERS_SPIO_INPUT_HI_Z: 2119 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num); 2120 /* set FLOAT */ 2121 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2122 break; 2123 2124 default: 2125 break; 2126 } 2127 2128 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2129 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2130 2131 return 0; 2132} 2133 2134void bnx2x_calc_fc_adv(struct bnx2x *bp) 2135{ 2136 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2137 switch (bp->link_vars.ieee_fc & 2138 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2139 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 2140 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2141 ADVERTISED_Pause); 2142 break; 2143 2144 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2145 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2146 ADVERTISED_Pause); 2147 break; 2148 2149 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2150 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2151 break; 2152 2153 default: 2154 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2155 ADVERTISED_Pause); 2156 break; 2157 } 2158} 2159 2160u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2161{ 2162 if (!BP_NOMCP(bp)) { 2163 u8 rc; 2164 int cfx_idx = bnx2x_get_link_cfg_idx(bp); 2165 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2166 /* 2167 * Initialize link parameters structure variables 2168 * It is recommended to turn off RX FC for jumbo frames 2169 * for better performance 2170 */ 2171 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2172 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2173 else 2174 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2175 2176 bnx2x_acquire_phy_lock(bp); 2177 2178 if (load_mode == LOAD_DIAG) { 2179 struct link_params *lp = &bp->link_params; 2180 lp->loopback_mode = LOOPBACK_XGXS; 2181 /* do PHY loopback at 10G speed, if possible */ 2182 if (lp->req_line_speed[cfx_idx] < SPEED_10000) { 2183 if (lp->speed_cap_mask[cfx_idx] & 2184 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2185 lp->req_line_speed[cfx_idx] = 2186 SPEED_10000; 2187 else 2188 lp->req_line_speed[cfx_idx] = 2189 SPEED_1000; 2190 } 2191 } 2192 2193 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2194 2195 bnx2x_release_phy_lock(bp); 2196 2197 bnx2x_calc_fc_adv(bp); 2198 2199 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { 2200 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2201 bnx2x_link_report(bp); 2202 } else 2203 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2204 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2205 return rc; 2206 } 2207 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2208 return -EINVAL; 2209} 2210 2211void bnx2x_link_set(struct bnx2x *bp) 2212{ 2213 if (!BP_NOMCP(bp)) { 2214 bnx2x_acquire_phy_lock(bp); 2215 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2216 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2217 bnx2x_release_phy_lock(bp); 2218 2219 bnx2x_calc_fc_adv(bp); 2220 } else 2221 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2222} 2223 2224static void bnx2x__link_reset(struct bnx2x *bp) 2225{ 2226 if (!BP_NOMCP(bp)) { 2227 bnx2x_acquire_phy_lock(bp); 2228 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2229 bnx2x_release_phy_lock(bp); 2230 } else 2231 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2232} 2233 2234u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2235{ 2236 u8 rc = 0; 2237 2238 if (!BP_NOMCP(bp)) { 2239 bnx2x_acquire_phy_lock(bp); 2240 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2241 is_serdes); 2242 bnx2x_release_phy_lock(bp); 2243 } else 2244 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2245 2246 return rc; 2247} 2248 2249static void bnx2x_init_port_minmax(struct bnx2x *bp) 2250{ 2251 u32 r_param = bp->link_vars.line_speed / 8; 2252 u32 fair_periodic_timeout_usec; 2253 u32 t_fair; 2254 2255 memset(&(bp->cmng.rs_vars), 0, 2256 sizeof(struct rate_shaping_vars_per_port)); 2257 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port)); 2258 2259 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ 2260 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4; 2261 2262 /* this is the threshold below which no timer arming will occur 2263 1.25 coefficient is for the threshold to be a little bigger 2264 than the real time, to compensate for timer in-accuracy */ 2265 bp->cmng.rs_vars.rs_threshold = 2266 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; 2267 2268 /* resolution of fairness timer */ 2269 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; 2270 /* for 10G it is 1000usec. for 1G it is 10000usec. */ 2271 t_fair = T_FAIR_COEF / bp->link_vars.line_speed; 2272 2273 /* this is the threshold below which we won't arm the timer anymore */ 2274 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES; 2275 2276 /* we multiply by 1e3/8 to get bytes/msec. 2277 We don't want the credits to pass a credit 2278 of the t_fair*FAIR_MEM (algorithm resolution) */ 2279 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM; 2280 /* since each tick is 4 usec */ 2281 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4; 2282} 2283 2284/* Calculates the sum of vn_min_rates. 2285 It's needed for further normalizing of the min_rates. 2286 Returns: 2287 sum of vn_min_rates. 2288 or 2289 0 - if all the min_rates are 0. 2290 In the later case fainess algorithm should be deactivated. 2291 If not all min_rates are zero then those that are zeroes will be set to 1. 2292 */ 2293static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) 2294{ 2295 int all_zero = 1; 2296 int vn; 2297 2298 bp->vn_weight_sum = 0; 2299 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2300 u32 vn_cfg = bp->mf_config[vn]; 2301 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2302 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2303 2304 /* Skip hidden vns */ 2305 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2306 continue; 2307 2308 /* If min rate is zero - set it to 1 */ 2309 if (!vn_min_rate) 2310 vn_min_rate = DEF_MIN_RATE; 2311 else 2312 all_zero = 0; 2313 2314 bp->vn_weight_sum += vn_min_rate; 2315 } 2316 2317 /* if ETS or all min rates are zeros - disable fairness */ 2318 if (BNX2X_IS_ETS_ENABLED(bp)) { 2319 bp->cmng.flags.cmng_enables &= 2320 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2321 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2322 } else if (all_zero) { 2323 bp->cmng.flags.cmng_enables &= 2324 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2325 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2326 " fairness will be disabled\n"); 2327 } else 2328 bp->cmng.flags.cmng_enables |= 2329 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2330} 2331 2332static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) 2333{ 2334 struct rate_shaping_vars_per_vn m_rs_vn; 2335 struct fairness_vars_per_vn m_fair_vn; 2336 u32 vn_cfg = bp->mf_config[vn]; 2337 int func = func_by_vn(bp, vn); 2338 u16 vn_min_rate, vn_max_rate; 2339 int i; 2340 2341 /* If function is hidden - set min and max to zeroes */ 2342 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 2343 vn_min_rate = 0; 2344 vn_max_rate = 0; 2345 2346 } else { 2347 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2348 2349 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2350 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2351 /* If fairness is enabled (not all min rates are zeroes) and 2352 if current min rate is zero - set it to 1. 2353 This is a requirement of the algorithm. */ 2354 if (bp->vn_weight_sum && (vn_min_rate == 0)) 2355 vn_min_rate = DEF_MIN_RATE; 2356 2357 if (IS_MF_SI(bp)) 2358 /* maxCfg in percents of linkspeed */ 2359 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2360 else 2361 /* maxCfg is absolute in 100Mb units */ 2362 vn_max_rate = maxCfg * 100; 2363 } 2364 2365 DP(NETIF_MSG_IFUP, 2366 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n", 2367 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); 2368 2369 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn)); 2370 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); 2371 2372 /* global vn counter - maximal Mbps for this vn */ 2373 m_rs_vn.vn_counter.rate = vn_max_rate; 2374 2375 /* quota - number of bytes transmitted in this period */ 2376 m_rs_vn.vn_counter.quota = 2377 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8; 2378 2379 if (bp->vn_weight_sum) { 2380 /* credit for each period of the fairness algorithm: 2381 number of bytes in T_FAIR (the vn share the port rate). 2382 vn_weight_sum should not be larger than 10000, thus 2383 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater 2384 than zero */ 2385 m_fair_vn.vn_credit_delta = 2386 max_t(u32, (vn_min_rate * (T_FAIR_COEF / 2387 (8 * bp->vn_weight_sum))), 2388 (bp->cmng.fair_vars.fair_threshold + 2389 MIN_ABOVE_THRESH)); 2390 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n", 2391 m_fair_vn.vn_credit_delta); 2392 } 2393 2394 /* Store it to internal memory */ 2395 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++) 2396 REG_WR(bp, BAR_XSTRORM_INTMEM + 2397 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4, 2398 ((u32 *)(&m_rs_vn))[i]); 2399 2400 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++) 2401 REG_WR(bp, BAR_XSTRORM_INTMEM + 2402 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4, 2403 ((u32 *)(&m_fair_vn))[i]); 2404} 2405 2406static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2407{ 2408 if (CHIP_REV_IS_SLOW(bp)) 2409 return CMNG_FNS_NONE; 2410 if (IS_MF(bp)) 2411 return CMNG_FNS_MINMAX; 2412 2413 return CMNG_FNS_NONE; 2414} 2415 2416void bnx2x_read_mf_cfg(struct bnx2x *bp) 2417{ 2418 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2419 2420 if (BP_NOMCP(bp)) 2421 return; /* what should be the default bvalue in this case */ 2422 2423 /* For 2 port configuration the absolute function number formula 2424 * is: 2425 * abs_func = 2 * vn + BP_PORT + BP_PATH 2426 * 2427 * and there are 4 functions per port 2428 * 2429 * For 4 port configuration it is 2430 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2431 * 2432 * and there are 2 functions per port 2433 */ 2434 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2435 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2436 2437 if (func >= E1H_FUNC_MAX) 2438 break; 2439 2440 bp->mf_config[vn] = 2441 MF_CFG_RD(bp, func_mf_config[func].config); 2442 } 2443} 2444 2445static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2446{ 2447 2448 if (cmng_type == CMNG_FNS_MINMAX) { 2449 int vn; 2450 2451 /* clear cmng_enables */ 2452 bp->cmng.flags.cmng_enables = 0; 2453 2454 /* read mf conf from shmem */ 2455 if (read_cfg) 2456 bnx2x_read_mf_cfg(bp); 2457 2458 /* Init rate shaping and fairness contexts */ 2459 bnx2x_init_port_minmax(bp); 2460 2461 /* vn_weight_sum and enable fairness if not 0 */ 2462 bnx2x_calc_vn_weight_sum(bp); 2463 2464 /* calculate and set min-max rate for each vn */ 2465 if (bp->port.pmf) 2466 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) 2467 bnx2x_init_vn_minmax(bp, vn); 2468 2469 /* always enable rate shaping and fairness */ 2470 bp->cmng.flags.cmng_enables |= 2471 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2472 if (!bp->vn_weight_sum) 2473 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2474 " fairness will be disabled\n"); 2475 return; 2476 } 2477 2478 /* rate shaping and fairness are disabled */ 2479 DP(NETIF_MSG_IFUP, 2480 "rate shaping and fairness are disabled\n"); 2481} 2482 2483/* This function is called upon link interrupt */ 2484static void bnx2x_link_attn(struct bnx2x *bp) 2485{ 2486 /* Make sure that we are synced with the current statistics */ 2487 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2488 2489 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2490 2491 if (bp->link_vars.link_up) { 2492 2493 /* dropless flow control */ 2494 if (!CHIP_IS_E1(bp) && bp->dropless_fc) { 2495 int port = BP_PORT(bp); 2496 u32 pause_enabled = 0; 2497 2498 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2499 pause_enabled = 1; 2500 2501 REG_WR(bp, BAR_USTRORM_INTMEM + 2502 USTORM_ETH_PAUSE_ENABLED_OFFSET(port), 2503 pause_enabled); 2504 } 2505 2506 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2507 struct host_port_stats *pstats; 2508 2509 pstats = bnx2x_sp(bp, port_stats); 2510 /* reset old mac stats */ 2511 memset(&(pstats->mac_stx[0]), 0, 2512 sizeof(struct mac_stx)); 2513 } 2514 if (bp->state == BNX2X_STATE_OPEN) 2515 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2516 } 2517 2518 if (bp->link_vars.link_up && bp->link_vars.line_speed) { 2519 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2520 2521 if (cmng_fns != CMNG_FNS_NONE) { 2522 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2523 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2524 } else 2525 /* rate shaping and fairness are disabled */ 2526 DP(NETIF_MSG_IFUP, 2527 "single function mode without fairness\n"); 2528 } 2529 2530 __bnx2x_link_report(bp); 2531 2532 if (IS_MF(bp)) 2533 bnx2x_link_sync_notify(bp); 2534} 2535 2536void bnx2x__link_status_update(struct bnx2x *bp) 2537{ 2538 if (bp->state != BNX2X_STATE_OPEN) 2539 return; 2540 2541 /* read updated dcb configuration */ 2542 bnx2x_dcbx_pmf_update(bp); 2543 2544 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2545 2546 if (bp->link_vars.link_up) 2547 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2548 else 2549 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2550 2551 /* indicate link status */ 2552 bnx2x_link_report(bp); 2553} 2554 2555static void bnx2x_pmf_update(struct bnx2x *bp) 2556{ 2557 int port = BP_PORT(bp); 2558 u32 val; 2559 2560 bp->port.pmf = 1; 2561 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf); 2562 2563 /* 2564 * We need the mb() to ensure the ordering between the writing to 2565 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2566 */ 2567 smp_mb(); 2568 2569 /* queue a periodic task */ 2570 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2571 2572 bnx2x_dcbx_pmf_update(bp); 2573 2574 /* enable nig attention */ 2575 val = (0xff0f | (1 << (BP_VN(bp) + 4))); 2576 if (bp->common.int_block == INT_BLOCK_HC) { 2577 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 2578 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 2579 } else if (!CHIP_IS_E1x(bp)) { 2580 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 2581 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 2582 } 2583 2584 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 2585} 2586 2587/* end of Link */ 2588 2589/* slow path */ 2590 2591/* 2592 * General service functions 2593 */ 2594 2595/* send the MCP a request, block until there is a reply */ 2596u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 2597{ 2598 int mb_idx = BP_FW_MB_IDX(bp); 2599 u32 seq; 2600 u32 rc = 0; 2601 u32 cnt = 1; 2602 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 2603 2604 mutex_lock(&bp->fw_mb_mutex); 2605 seq = ++bp->fw_seq; 2606 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 2607 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 2608 2609 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 2610 (command | seq), param); 2611 2612 do { 2613 /* let the FW do it's magic ... */ 2614 msleep(delay); 2615 2616 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 2617 2618 /* Give the FW up to 5 second (500*10ms) */ 2619 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2620 2621 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 2622 cnt*delay, rc, seq); 2623 2624 /* is this a reply to our command? */ 2625 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 2626 rc &= FW_MSG_CODE_MASK; 2627 else { 2628 /* FW BUG! */ 2629 BNX2X_ERR("FW failed to respond!\n"); 2630 bnx2x_fw_dump(bp); 2631 rc = 0; 2632 } 2633 mutex_unlock(&bp->fw_mb_mutex); 2634 2635 return rc; 2636} 2637 2638 2639void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 2640{ 2641 if (CHIP_IS_E1x(bp)) { 2642 struct tstorm_eth_function_common_config tcfg = {0}; 2643 2644 storm_memset_func_cfg(bp, &tcfg, p->func_id); 2645 } 2646 2647 /* Enable the function in the FW */ 2648 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 2649 storm_memset_func_en(bp, p->func_id, 1); 2650 2651 /* spq */ 2652 if (p->func_flgs & FUNC_FLG_SPQ) { 2653 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 2654 REG_WR(bp, XSEM_REG_FAST_MEMORY + 2655 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 2656 } 2657} 2658 2659/** 2660 * bnx2x_get_tx_only_flags - Return common flags 2661 * 2662 * @bp device handle 2663 * @fp queue handle 2664 * @zero_stats TRUE if statistics zeroing is needed 2665 * 2666 * Return the flags that are common for the Tx-only and not normal connections. 2667 */ 2668static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 2669 struct bnx2x_fastpath *fp, 2670 bool zero_stats) 2671{ 2672 unsigned long flags = 0; 2673 2674 /* PF driver will always initialize the Queue to an ACTIVE state */ 2675 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 2676 2677 /* tx only connections collect statistics (on the same index as the 2678 * parent connection). The statistics are zeroed when the parent 2679 * connection is initialized. 2680 */ 2681 2682 __set_bit(BNX2X_Q_FLG_STATS, &flags); 2683 if (zero_stats) 2684 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 2685 2686 2687 return flags; 2688} 2689 2690static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 2691 struct bnx2x_fastpath *fp, 2692 bool leading) 2693{ 2694 unsigned long flags = 0; 2695 2696 /* calculate other queue flags */ 2697 if (IS_MF_SD(bp)) 2698 __set_bit(BNX2X_Q_FLG_OV, &flags); 2699 2700 if (IS_FCOE_FP(fp)) 2701 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 2702 2703 if (!fp->disable_tpa) { 2704 __set_bit(BNX2X_Q_FLG_TPA, &flags); 2705 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 2706 } 2707 2708 if (leading) { 2709 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 2710 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 2711 } 2712 2713 /* Always set HW VLAN stripping */ 2714 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 2715 2716 2717 return flags | bnx2x_get_common_flags(bp, fp, true); 2718} 2719 2720static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 2721 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 2722 u8 cos) 2723{ 2724 gen_init->stat_id = bnx2x_stats_id(fp); 2725 gen_init->spcl_id = fp->cl_id; 2726 2727 /* Always use mini-jumbo MTU for FCoE L2 ring */ 2728 if (IS_FCOE_FP(fp)) 2729 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 2730 else 2731 gen_init->mtu = bp->dev->mtu; 2732 2733 gen_init->cos = cos; 2734} 2735 2736static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 2737 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 2738 struct bnx2x_rxq_setup_params *rxq_init) 2739{ 2740 u8 max_sge = 0; 2741 u16 sge_sz = 0; 2742 u16 tpa_agg_size = 0; 2743 2744 if (!fp->disable_tpa) { 2745 pause->sge_th_lo = SGE_TH_LO(bp); 2746 pause->sge_th_hi = SGE_TH_HI(bp); 2747 2748 /* validate SGE ring has enough to cross high threshold */ 2749 WARN_ON(bp->dropless_fc && 2750 pause->sge_th_hi + FW_PREFETCH_CNT > 2751 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); 2752 2753 tpa_agg_size = min_t(u32, 2754 (min_t(u32, 8, MAX_SKB_FRAGS) * 2755 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); 2756 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 2757 SGE_PAGE_SHIFT; 2758 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 2759 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 2760 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, 2761 0xffff); 2762 } 2763 2764 /* pause - not for e1 */ 2765 if (!CHIP_IS_E1(bp)) { 2766 pause->bd_th_lo = BD_TH_LO(bp); 2767 pause->bd_th_hi = BD_TH_HI(bp); 2768 2769 pause->rcq_th_lo = RCQ_TH_LO(bp); 2770 pause->rcq_th_hi = RCQ_TH_HI(bp); 2771 /* 2772 * validate that rings have enough entries to cross 2773 * high thresholds 2774 */ 2775 WARN_ON(bp->dropless_fc && 2776 pause->bd_th_hi + FW_PREFETCH_CNT > 2777 bp->rx_ring_size); 2778 WARN_ON(bp->dropless_fc && 2779 pause->rcq_th_hi + FW_PREFETCH_CNT > 2780 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); 2781 2782 pause->pri_map = 1; 2783 } 2784 2785 /* rxq setup */ 2786 rxq_init->dscr_map = fp->rx_desc_mapping; 2787 rxq_init->sge_map = fp->rx_sge_mapping; 2788 rxq_init->rcq_map = fp->rx_comp_mapping; 2789 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 2790 2791 /* This should be a maximum number of data bytes that may be 2792 * placed on the BD (not including paddings). 2793 */ 2794 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - 2795 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; 2796 2797 rxq_init->cl_qzone_id = fp->cl_qzone_id; 2798 rxq_init->tpa_agg_sz = tpa_agg_size; 2799 rxq_init->sge_buf_sz = sge_sz; 2800 rxq_init->max_sges_pkt = max_sge; 2801 rxq_init->rss_engine_id = BP_FUNC(bp); 2802 2803 /* Maximum number or simultaneous TPA aggregation for this Queue. 2804 * 2805 * For PF Clients it should be the maximum avaliable number. 2806 * VF driver(s) may want to define it to a smaller value. 2807 */ 2808 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); 2809 2810 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 2811 rxq_init->fw_sb_id = fp->fw_sb_id; 2812 2813 if (IS_FCOE_FP(fp)) 2814 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 2815 else 2816 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 2817} 2818 2819static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 2820 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 2821 u8 cos) 2822{ 2823 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping; 2824 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 2825 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 2826 txq_init->fw_sb_id = fp->fw_sb_id; 2827 2828 /* 2829 * set the tss leading client id for TX classfication == 2830 * leading RSS client id 2831 */ 2832 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 2833 2834 if (IS_FCOE_FP(fp)) { 2835 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 2836 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 2837 } 2838} 2839 2840static void bnx2x_pf_init(struct bnx2x *bp) 2841{ 2842 struct bnx2x_func_init_params func_init = {0}; 2843 struct event_ring_data eq_data = { {0} }; 2844 u16 flags; 2845 2846 if (!CHIP_IS_E1x(bp)) { 2847 /* reset IGU PF statistics: MSIX + ATTN */ 2848 /* PF */ 2849 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2850 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2851 (CHIP_MODE_IS_4_PORT(bp) ? 2852 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2853 /* ATTN */ 2854 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2855 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2856 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 2857 (CHIP_MODE_IS_4_PORT(bp) ? 2858 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2859 } 2860 2861 /* function setup flags */ 2862 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 2863 2864 /* This flag is relevant for E1x only. 2865 * E2 doesn't have a TPA configuration in a function level. 2866 */ 2867 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; 2868 2869 func_init.func_flgs = flags; 2870 func_init.pf_id = BP_FUNC(bp); 2871 func_init.func_id = BP_FUNC(bp); 2872 func_init.spq_map = bp->spq_mapping; 2873 func_init.spq_prod = bp->spq_prod_idx; 2874 2875 bnx2x_func_init(bp, &func_init); 2876 2877 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 2878 2879 /* 2880 * Congestion management values depend on the link rate 2881 * There is no active link so initial link rate is set to 10 Gbps. 2882 * When the link comes up The congestion management values are 2883 * re-calculated according to the actual link rate. 2884 */ 2885 bp->link_vars.line_speed = SPEED_10000; 2886 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 2887 2888 /* Only the PMF sets the HW */ 2889 if (bp->port.pmf) 2890 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2891 2892 /* init Event Queue */ 2893 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 2894 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 2895 eq_data.producer = bp->eq_prod; 2896 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 2897 eq_data.sb_id = DEF_SB_ID; 2898 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 2899} 2900 2901 2902static void bnx2x_e1h_disable(struct bnx2x *bp) 2903{ 2904 int port = BP_PORT(bp); 2905 2906 bnx2x_tx_disable(bp); 2907 2908 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 2909} 2910 2911static void bnx2x_e1h_enable(struct bnx2x *bp) 2912{ 2913 int port = BP_PORT(bp); 2914 2915 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 2916 2917 /* Tx queue should be only reenabled */ 2918 netif_tx_wake_all_queues(bp->dev); 2919 2920 /* 2921 * Should not call netif_carrier_on since it will be called if the link 2922 * is up when checking for link state 2923 */ 2924} 2925 2926#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 2927 2928static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) 2929{ 2930 struct eth_stats_info *ether_stat = 2931 &bp->slowpath->drv_info_to_mcp.ether_stat; 2932 2933 /* leave last char as NULL */ 2934 memcpy(ether_stat->version, DRV_MODULE_VERSION, 2935 ETH_STAT_INFO_VERSION_LEN - 1); 2936 2937 bp->fp[0].mac_obj.get_n_elements(bp, &bp->fp[0].mac_obj, 2938 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 2939 ether_stat->mac_local); 2940 2941 ether_stat->mtu_size = bp->dev->mtu; 2942 2943 if (bp->dev->features & NETIF_F_RXCSUM) 2944 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 2945 if (bp->dev->features & NETIF_F_TSO) 2946 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 2947 ether_stat->feature_flags |= bp->common.boot_mode; 2948 2949 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; 2950 2951 ether_stat->txq_size = bp->tx_ring_size; 2952 ether_stat->rxq_size = bp->rx_ring_size; 2953} 2954 2955static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) 2956{ 2957#ifdef BCM_CNIC 2958 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 2959 struct fcoe_stats_info *fcoe_stat = 2960 &bp->slowpath->drv_info_to_mcp.fcoe_stat; 2961 2962 memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN); 2963 2964 fcoe_stat->qos_priority = 2965 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; 2966 2967 /* insert FCoE stats from ramrod response */ 2968 if (!NO_FCOE(bp)) { 2969 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = 2970 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2971 tstorm_queue_statistics; 2972 2973 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = 2974 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2975 xstorm_queue_statistics; 2976 2977 struct fcoe_statistics_params *fw_fcoe_stat = 2978 &bp->fw_stats_data->fcoe; 2979 2980 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo, 2981 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); 2982 2983 ADD_64(fcoe_stat->rx_bytes_hi, 2984 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, 2985 fcoe_stat->rx_bytes_lo, 2986 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); 2987 2988 ADD_64(fcoe_stat->rx_bytes_hi, 2989 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, 2990 fcoe_stat->rx_bytes_lo, 2991 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); 2992 2993 ADD_64(fcoe_stat->rx_bytes_hi, 2994 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, 2995 fcoe_stat->rx_bytes_lo, 2996 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); 2997 2998 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2999 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); 3000 3001 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3002 fcoe_q_tstorm_stats->rcv_ucast_pkts); 3003 3004 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3005 fcoe_q_tstorm_stats->rcv_bcast_pkts); 3006 3007 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3008 fcoe_q_tstorm_stats->rcv_mcast_pkts); 3009 3010 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo, 3011 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); 3012 3013 ADD_64(fcoe_stat->tx_bytes_hi, 3014 fcoe_q_xstorm_stats->ucast_bytes_sent.hi, 3015 fcoe_stat->tx_bytes_lo, 3016 fcoe_q_xstorm_stats->ucast_bytes_sent.lo); 3017 3018 ADD_64(fcoe_stat->tx_bytes_hi, 3019 fcoe_q_xstorm_stats->bcast_bytes_sent.hi, 3020 fcoe_stat->tx_bytes_lo, 3021 fcoe_q_xstorm_stats->bcast_bytes_sent.lo); 3022 3023 ADD_64(fcoe_stat->tx_bytes_hi, 3024 fcoe_q_xstorm_stats->mcast_bytes_sent.hi, 3025 fcoe_stat->tx_bytes_lo, 3026 fcoe_q_xstorm_stats->mcast_bytes_sent.lo); 3027 3028 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3029 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); 3030 3031 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3032 fcoe_q_xstorm_stats->ucast_pkts_sent); 3033 3034 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3035 fcoe_q_xstorm_stats->bcast_pkts_sent); 3036 3037 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3038 fcoe_q_xstorm_stats->mcast_pkts_sent); 3039 } 3040 3041 /* ask L5 driver to add data to the struct */ 3042 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); 3043#endif 3044} 3045 3046static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) 3047{ 3048#ifdef BCM_CNIC 3049 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3050 struct iscsi_stats_info *iscsi_stat = 3051 &bp->slowpath->drv_info_to_mcp.iscsi_stat; 3052 3053 memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); 3054 3055 iscsi_stat->qos_priority = 3056 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; 3057 3058 /* ask L5 driver to add data to the struct */ 3059 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); 3060#endif 3061} 3062 3063/* called due to MCP event (on pmf): 3064 * reread new bandwidth configuration 3065 * configure FW 3066 * notify others function about the change 3067 */ 3068static inline void bnx2x_config_mf_bw(struct bnx2x *bp) 3069{ 3070 if (bp->link_vars.link_up) { 3071 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 3072 bnx2x_link_sync_notify(bp); 3073 } 3074 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3075} 3076 3077static inline void bnx2x_set_mf_bw(struct bnx2x *bp) 3078{ 3079 bnx2x_config_mf_bw(bp); 3080 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 3081} 3082 3083static void bnx2x_handle_drv_info_req(struct bnx2x *bp) 3084{ 3085 enum drv_info_opcode op_code; 3086 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); 3087 3088 /* if drv_info version supported by MFW doesn't match - send NACK */ 3089 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 3090 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3091 return; 3092 } 3093 3094 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 3095 DRV_INFO_CONTROL_OP_CODE_SHIFT; 3096 3097 memset(&bp->slowpath->drv_info_to_mcp, 0, 3098 sizeof(union drv_info_to_mcp)); 3099 3100 switch (op_code) { 3101 case ETH_STATS_OPCODE: 3102 bnx2x_drv_info_ether_stat(bp); 3103 break; 3104 case FCOE_STATS_OPCODE: 3105 bnx2x_drv_info_fcoe_stat(bp); 3106 break; 3107 case ISCSI_STATS_OPCODE: 3108 bnx2x_drv_info_iscsi_stat(bp); 3109 break; 3110 default: 3111 /* if op code isn't supported - send NACK */ 3112 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3113 return; 3114 } 3115 3116 /* if we got drv_info attn from MFW then these fields are defined in 3117 * shmem2 for sure 3118 */ 3119 SHMEM2_WR(bp, drv_info_host_addr_lo, 3120 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3121 SHMEM2_WR(bp, drv_info_host_addr_hi, 3122 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3123 3124 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); 3125} 3126 3127static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) 3128{ 3129 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); 3130 3131 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 3132 3133 /* 3134 * This is the only place besides the function initialization 3135 * where the bp->flags can change so it is done without any 3136 * locks 3137 */ 3138 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 3139 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n"); 3140 bp->flags |= MF_FUNC_DIS; 3141 3142 bnx2x_e1h_disable(bp); 3143 } else { 3144 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); 3145 bp->flags &= ~MF_FUNC_DIS; 3146 3147 bnx2x_e1h_enable(bp); 3148 } 3149 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 3150 } 3151 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 3152 bnx2x_config_mf_bw(bp); 3153 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 3154 } 3155 3156 /* Report results to MCP */ 3157 if (dcc_event) 3158 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); 3159 else 3160 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); 3161} 3162 3163/* must be called under the spq lock */ 3164static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 3165{ 3166 struct eth_spe *next_spe = bp->spq_prod_bd; 3167 3168 if (bp->spq_prod_bd == bp->spq_last_bd) { 3169 bp->spq_prod_bd = bp->spq; 3170 bp->spq_prod_idx = 0; 3171 DP(NETIF_MSG_TIMER, "end of spq\n"); 3172 } else { 3173 bp->spq_prod_bd++; 3174 bp->spq_prod_idx++; 3175 } 3176 return next_spe; 3177} 3178 3179/* must be called under the spq lock */ 3180static inline void bnx2x_sp_prod_update(struct bnx2x *bp) 3181{ 3182 int func = BP_FUNC(bp); 3183 3184 /* 3185 * Make sure that BD data is updated before writing the producer: 3186 * BD data is written to the memory, the producer is read from the 3187 * memory, thus we need a full memory barrier to ensure the ordering. 3188 */ 3189 mb(); 3190 3191 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3192 bp->spq_prod_idx); 3193 mmiowb(); 3194} 3195 3196/** 3197 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3198 * 3199 * @cmd: command to check 3200 * @cmd_type: command type 3201 */ 3202static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3203{ 3204 if ((cmd_type == NONE_CONNECTION_TYPE) || 3205 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3206 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3207 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3208 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3209 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3210 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3211 return true; 3212 else 3213 return false; 3214 3215} 3216 3217 3218/** 3219 * bnx2x_sp_post - place a single command on an SP ring 3220 * 3221 * @bp: driver handle 3222 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3223 * @cid: SW CID the command is related to 3224 * @data_hi: command private data address (high 32 bits) 3225 * @data_lo: command private data address (low 32 bits) 3226 * @cmd_type: command type (e.g. NONE, ETH) 3227 * 3228 * SP data is handled as if it's always an address pair, thus data fields are 3229 * not swapped to little endian in upper functions. Instead this function swaps 3230 * data as if it's two u32 fields. 3231 */ 3232int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3233 u32 data_hi, u32 data_lo, int cmd_type) 3234{ 3235 struct eth_spe *spe; 3236 u16 type; 3237 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3238 3239#ifdef BNX2X_STOP_ON_ERROR 3240 if (unlikely(bp->panic)) 3241 return -EIO; 3242#endif 3243 3244 spin_lock_bh(&bp->spq_lock); 3245 3246 if (common) { 3247 if (!atomic_read(&bp->eq_spq_left)) { 3248 BNX2X_ERR("BUG! EQ ring full!\n"); 3249 spin_unlock_bh(&bp->spq_lock); 3250 bnx2x_panic(); 3251 return -EBUSY; 3252 } 3253 } else if (!atomic_read(&bp->cq_spq_left)) { 3254 BNX2X_ERR("BUG! SPQ ring full!\n"); 3255 spin_unlock_bh(&bp->spq_lock); 3256 bnx2x_panic(); 3257 return -EBUSY; 3258 } 3259 3260 spe = bnx2x_sp_get_next(bp); 3261 3262 /* CID needs port number to be encoded int it */ 3263 spe->hdr.conn_and_cmd_data = 3264 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3265 HW_CID(bp, cid)); 3266 3267 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; 3268 3269 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3270 SPE_HDR_FUNCTION_ID); 3271 3272 spe->hdr.type = cpu_to_le16(type); 3273 3274 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3275 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3276 3277 /* 3278 * It's ok if the actual decrement is issued towards the memory 3279 * somewhere between the spin_lock and spin_unlock. Thus no 3280 * more explict memory barrier is needed. 3281 */ 3282 if (common) 3283 atomic_dec(&bp->eq_spq_left); 3284 else 3285 atomic_dec(&bp->cq_spq_left); 3286 3287 3288 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/, 3289 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) " 3290 "type(0x%x) left (CQ, EQ) (%x,%x)\n", 3291 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3292 (u32)(U64_LO(bp->spq_mapping) + 3293 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3294 HW_CID(bp, cid), data_hi, data_lo, type, 3295 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3296 3297 bnx2x_sp_prod_update(bp); 3298 spin_unlock_bh(&bp->spq_lock); 3299 return 0; 3300} 3301 3302/* acquire split MCP access lock register */ 3303static int bnx2x_acquire_alr(struct bnx2x *bp) 3304{ 3305 u32 j, val; 3306 int rc = 0; 3307 3308 might_sleep(); 3309 for (j = 0; j < 1000; j++) { 3310 val = (1UL << 31); 3311 REG_WR(bp, GRCBASE_MCP + 0x9c, val); 3312 val = REG_RD(bp, GRCBASE_MCP + 0x9c); 3313 if (val & (1L << 31)) 3314 break; 3315 3316 msleep(5); 3317 } 3318 if (!(val & (1L << 31))) { 3319 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3320 rc = -EBUSY; 3321 } 3322 3323 return rc; 3324} 3325 3326/* release split MCP access lock register */ 3327static void bnx2x_release_alr(struct bnx2x *bp) 3328{ 3329 REG_WR(bp, GRCBASE_MCP + 0x9c, 0); 3330} 3331 3332#define BNX2X_DEF_SB_ATT_IDX 0x0001 3333#define BNX2X_DEF_SB_IDX 0x0002 3334 3335static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3336{ 3337 struct host_sp_status_block *def_sb = bp->def_status_blk; 3338 u16 rc = 0; 3339 3340 barrier(); /* status block is written to by the chip */ 3341 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3342 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 3343 rc |= BNX2X_DEF_SB_ATT_IDX; 3344 } 3345 3346 if (bp->def_idx != def_sb->sp_sb.running_index) { 3347 bp->def_idx = def_sb->sp_sb.running_index; 3348 rc |= BNX2X_DEF_SB_IDX; 3349 } 3350 3351 /* Do not reorder: indecies reading should complete before handling */ 3352 barrier(); 3353 return rc; 3354} 3355 3356/* 3357 * slow path service functions 3358 */ 3359 3360static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 3361{ 3362 int port = BP_PORT(bp); 3363 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 3364 MISC_REG_AEU_MASK_ATTN_FUNC_0; 3365 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 3366 NIG_REG_MASK_INTERRUPT_PORT0; 3367 u32 aeu_mask; 3368 u32 nig_mask = 0; 3369 u32 reg_addr; 3370 3371 if (bp->attn_state & asserted) 3372 BNX2X_ERR("IGU ERROR\n"); 3373 3374 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3375 aeu_mask = REG_RD(bp, aeu_addr); 3376 3377 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 3378 aeu_mask, asserted); 3379 aeu_mask &= ~(asserted & 0x3ff); 3380 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 3381 3382 REG_WR(bp, aeu_addr, aeu_mask); 3383 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3384 3385 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 3386 bp->attn_state |= asserted; 3387 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 3388 3389 if (asserted & ATTN_HARD_WIRED_MASK) { 3390 if (asserted & ATTN_NIG_FOR_FUNC) { 3391 3392 bnx2x_acquire_phy_lock(bp); 3393 3394 /* save nig interrupt mask */ 3395 nig_mask = REG_RD(bp, nig_int_mask_addr); 3396 3397 /* If nig_mask is not set, no need to call the update 3398 * function. 3399 */ 3400 if (nig_mask) { 3401 REG_WR(bp, nig_int_mask_addr, 0); 3402 3403 bnx2x_link_attn(bp); 3404 } 3405 3406 /* handle unicore attn? */ 3407 } 3408 if (asserted & ATTN_SW_TIMER_4_FUNC) 3409 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 3410 3411 if (asserted & GPIO_2_FUNC) 3412 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 3413 3414 if (asserted & GPIO_3_FUNC) 3415 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 3416 3417 if (asserted & GPIO_4_FUNC) 3418 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 3419 3420 if (port == 0) { 3421 if (asserted & ATTN_GENERAL_ATTN_1) { 3422 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 3423 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 3424 } 3425 if (asserted & ATTN_GENERAL_ATTN_2) { 3426 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 3427 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 3428 } 3429 if (asserted & ATTN_GENERAL_ATTN_3) { 3430 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 3431 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 3432 } 3433 } else { 3434 if (asserted & ATTN_GENERAL_ATTN_4) { 3435 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 3436 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 3437 } 3438 if (asserted & ATTN_GENERAL_ATTN_5) { 3439 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 3440 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 3441 } 3442 if (asserted & ATTN_GENERAL_ATTN_6) { 3443 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 3444 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 3445 } 3446 } 3447 3448 } /* if hardwired */ 3449 3450 if (bp->common.int_block == INT_BLOCK_HC) 3451 reg_addr = (HC_REG_COMMAND_REG + port*32 + 3452 COMMAND_REG_ATTN_BITS_SET); 3453 else 3454 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 3455 3456 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 3457 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 3458 REG_WR(bp, reg_addr, asserted); 3459 3460 /* now set back the mask */ 3461 if (asserted & ATTN_NIG_FOR_FUNC) { 3462 REG_WR(bp, nig_int_mask_addr, nig_mask); 3463 bnx2x_release_phy_lock(bp); 3464 } 3465} 3466 3467static inline void bnx2x_fan_failure(struct bnx2x *bp) 3468{ 3469 int port = BP_PORT(bp); 3470 u32 ext_phy_config; 3471 /* mark the failure */ 3472 ext_phy_config = 3473 SHMEM_RD(bp, 3474 dev_info.port_hw_config[port].external_phy_config); 3475 3476 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 3477 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 3478 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 3479 ext_phy_config); 3480 3481 /* log the failure */ 3482 netdev_err(bp->dev, "Fan Failure on Network Controller has caused" 3483 " the driver to shutdown the card to prevent permanent" 3484 " damage. Please contact OEM Support for assistance\n"); 3485 3486 /* 3487 * Scheudle device reset (unload) 3488 * This is due to some boards consuming sufficient power when driver is 3489 * up to overheat if fan fails. 3490 */ 3491 smp_mb__before_clear_bit(); 3492 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); 3493 smp_mb__after_clear_bit(); 3494 schedule_delayed_work(&bp->sp_rtnl_task, 0); 3495 3496} 3497 3498static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 3499{ 3500 int port = BP_PORT(bp); 3501 int reg_offset; 3502 u32 val; 3503 3504 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 3505 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 3506 3507 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 3508 3509 val = REG_RD(bp, reg_offset); 3510 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 3511 REG_WR(bp, reg_offset, val); 3512 3513 BNX2X_ERR("SPIO5 hw attention\n"); 3514 3515 /* Fan failure attention */ 3516 bnx2x_hw_reset_phy(&bp->link_params); 3517 bnx2x_fan_failure(bp); 3518 } 3519 3520 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 3521 bnx2x_acquire_phy_lock(bp); 3522 bnx2x_handle_module_detect_int(&bp->link_params); 3523 bnx2x_release_phy_lock(bp); 3524 } 3525 3526 if (attn & HW_INTERRUT_ASSERT_SET_0) { 3527 3528 val = REG_RD(bp, reg_offset); 3529 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 3530 REG_WR(bp, reg_offset, val); 3531 3532 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 3533 (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); 3534 bnx2x_panic(); 3535 } 3536} 3537 3538static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 3539{ 3540 u32 val; 3541 3542 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 3543 3544 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 3545 BNX2X_ERR("DB hw attention 0x%x\n", val); 3546 /* DORQ discard attention */ 3547 if (val & 0x2) 3548 BNX2X_ERR("FATAL error from DORQ\n"); 3549 } 3550 3551 if (attn & HW_INTERRUT_ASSERT_SET_1) { 3552 3553 int port = BP_PORT(bp); 3554 int reg_offset; 3555 3556 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 3557 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 3558 3559 val = REG_RD(bp, reg_offset); 3560 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 3561 REG_WR(bp, reg_offset, val); 3562 3563 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 3564 (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); 3565 bnx2x_panic(); 3566 } 3567} 3568 3569static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 3570{ 3571 u32 val; 3572 3573 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 3574 3575 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 3576 BNX2X_ERR("CFC hw attention 0x%x\n", val); 3577 /* CFC error attention */ 3578 if (val & 0x2) 3579 BNX2X_ERR("FATAL error from CFC\n"); 3580 } 3581 3582 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 3583 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 3584 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 3585 /* RQ_USDMDP_FIFO_OVERFLOW */ 3586 if (val & 0x18000) 3587 BNX2X_ERR("FATAL error from PXP\n"); 3588 3589 if (!CHIP_IS_E1x(bp)) { 3590 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 3591 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 3592 } 3593 } 3594 3595 if (attn & HW_INTERRUT_ASSERT_SET_2) { 3596 3597 int port = BP_PORT(bp); 3598 int reg_offset; 3599 3600 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 3601 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 3602 3603 val = REG_RD(bp, reg_offset); 3604 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 3605 REG_WR(bp, reg_offset, val); 3606 3607 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 3608 (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); 3609 bnx2x_panic(); 3610 } 3611} 3612 3613static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 3614{ 3615 u32 val; 3616 3617 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 3618 3619 if (attn & BNX2X_PMF_LINK_ASSERT) { 3620 int func = BP_FUNC(bp); 3621 3622 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 3623 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 3624 func_mf_config[BP_ABS_FUNC(bp)].config); 3625 val = SHMEM_RD(bp, 3626 func_mb[BP_FW_MB_IDX(bp)].drv_status); 3627 if (val & DRV_STATUS_DCC_EVENT_MASK) 3628 bnx2x_dcc_event(bp, 3629 (val & DRV_STATUS_DCC_EVENT_MASK)); 3630 3631 if (val & DRV_STATUS_SET_MF_BW) 3632 bnx2x_set_mf_bw(bp); 3633 3634 if (val & DRV_STATUS_DRV_INFO_REQ) 3635 bnx2x_handle_drv_info_req(bp); 3636 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 3637 bnx2x_pmf_update(bp); 3638 3639 if (bp->port.pmf && 3640 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 3641 bp->dcbx_enabled > 0) 3642 /* start dcbx state machine */ 3643 bnx2x_dcbx_set_params(bp, 3644 BNX2X_DCBX_STATE_NEG_RECEIVED); 3645 if (bp->link_vars.periodic_flags & 3646 PERIODIC_FLAGS_LINK_EVENT) { 3647 /* sync with link */ 3648 bnx2x_acquire_phy_lock(bp); 3649 bp->link_vars.periodic_flags &= 3650 ~PERIODIC_FLAGS_LINK_EVENT; 3651 bnx2x_release_phy_lock(bp); 3652 if (IS_MF(bp)) 3653 bnx2x_link_sync_notify(bp); 3654 bnx2x_link_report(bp); 3655 } 3656 /* Always call it here: bnx2x_link_report() will 3657 * prevent the link indication duplication. 3658 */ 3659 bnx2x__link_status_update(bp); 3660 } else if (attn & BNX2X_MC_ASSERT_BITS) { 3661 3662 BNX2X_ERR("MC assert!\n"); 3663 bnx2x_mc_assert(bp); 3664 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 3665 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 3666 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 3667 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 3668 bnx2x_panic(); 3669 3670 } else if (attn & BNX2X_MCP_ASSERT) { 3671 3672 BNX2X_ERR("MCP assert!\n"); 3673 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 3674 bnx2x_fw_dump(bp); 3675 3676 } else 3677 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 3678 } 3679 3680 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 3681 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 3682 if (attn & BNX2X_GRC_TIMEOUT) { 3683 val = CHIP_IS_E1(bp) ? 0 : 3684 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 3685 BNX2X_ERR("GRC time-out 0x%08x\n", val); 3686 } 3687 if (attn & BNX2X_GRC_RSV) { 3688 val = CHIP_IS_E1(bp) ? 0 : 3689 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 3690 BNX2X_ERR("GRC reserved 0x%08x\n", val); 3691 } 3692 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 3693 } 3694} 3695 3696/* 3697 * Bits map: 3698 * 0-7 - Engine0 load counter. 3699 * 8-15 - Engine1 load counter. 3700 * 16 - Engine0 RESET_IN_PROGRESS bit. 3701 * 17 - Engine1 RESET_IN_PROGRESS bit. 3702 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 3703 * on the engine 3704 * 19 - Engine1 ONE_IS_LOADED. 3705 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 3706 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 3707 * just the one belonging to its engine). 3708 * 3709 */ 3710#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 3711 3712#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 3713#define BNX2X_PATH0_LOAD_CNT_SHIFT 0 3714#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 3715#define BNX2X_PATH1_LOAD_CNT_SHIFT 8 3716#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 3717#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 3718#define BNX2X_GLOBAL_RESET_BIT 0x00040000 3719 3720/* 3721 * Set the GLOBAL_RESET bit. 3722 * 3723 * Should be run under rtnl lock 3724 */ 3725void bnx2x_set_reset_global(struct bnx2x *bp) 3726{ 3727 u32 val; 3728 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3729 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3730 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 3731 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3732} 3733 3734/* 3735 * Clear the GLOBAL_RESET bit. 3736 * 3737 * Should be run under rtnl lock 3738 */ 3739static inline void bnx2x_clear_reset_global(struct bnx2x *bp) 3740{ 3741 u32 val; 3742 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3743 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3744 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 3745 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3746} 3747 3748/* 3749 * Checks the GLOBAL_RESET bit. 3750 * 3751 * should be run under rtnl lock 3752 */ 3753static inline bool bnx2x_reset_is_global(struct bnx2x *bp) 3754{ 3755 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3756 3757 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 3758 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 3759} 3760 3761/* 3762 * Clear RESET_IN_PROGRESS bit for the current engine. 3763 * 3764 * Should be run under rtnl lock 3765 */ 3766static inline void bnx2x_set_reset_done(struct bnx2x *bp) 3767{ 3768 u32 val; 3769 u32 bit = BP_PATH(bp) ? 3770 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3771 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3772 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3773 3774 /* Clear the bit */ 3775 val &= ~bit; 3776 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3777 3778 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3779} 3780 3781/* 3782 * Set RESET_IN_PROGRESS for the current engine. 3783 * 3784 * should be run under rtnl lock 3785 */ 3786void bnx2x_set_reset_in_progress(struct bnx2x *bp) 3787{ 3788 u32 val; 3789 u32 bit = BP_PATH(bp) ? 3790 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3791 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3792 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3793 3794 /* Set the bit */ 3795 val |= bit; 3796 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3797 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3798} 3799 3800/* 3801 * Checks the RESET_IN_PROGRESS bit for the given engine. 3802 * should be run under rtnl lock 3803 */ 3804bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 3805{ 3806 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3807 u32 bit = engine ? 3808 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3809 3810 /* return false if bit is set */ 3811 return (val & bit) ? false : true; 3812} 3813 3814/* 3815 * set pf load for the current pf. 3816 * 3817 * should be run under rtnl lock 3818 */ 3819void bnx2x_set_pf_load(struct bnx2x *bp) 3820{ 3821 u32 val1, val; 3822 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3823 BNX2X_PATH0_LOAD_CNT_MASK; 3824 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3825 BNX2X_PATH0_LOAD_CNT_SHIFT; 3826 3827 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3828 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3829 3830 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3831 3832 /* get the current counter value */ 3833 val1 = (val & mask) >> shift; 3834 3835 /* set bit of that PF */ 3836 val1 |= (1 << bp->pf_num); 3837 3838 /* clear the old value */ 3839 val &= ~mask; 3840 3841 /* set the new one */ 3842 val |= ((val1 << shift) & mask); 3843 3844 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3845 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3846} 3847 3848/** 3849 * bnx2x_clear_pf_load - clear pf load mark 3850 * 3851 * @bp: driver handle 3852 * 3853 * Should be run under rtnl lock. 3854 * Decrements the load counter for the current engine. Returns 3855 * whether other functions are still loaded 3856 */ 3857bool bnx2x_clear_pf_load(struct bnx2x *bp) 3858{ 3859 u32 val1, val; 3860 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3861 BNX2X_PATH0_LOAD_CNT_MASK; 3862 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3863 BNX2X_PATH0_LOAD_CNT_SHIFT; 3864 3865 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3866 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3867 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3868 3869 /* get the current counter value */ 3870 val1 = (val & mask) >> shift; 3871 3872 /* clear bit of that PF */ 3873 val1 &= ~(1 << bp->pf_num); 3874 3875 /* clear the old value */ 3876 val &= ~mask; 3877 3878 /* set the new one */ 3879 val |= ((val1 << shift) & mask); 3880 3881 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3882 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3883 return val1 != 0; 3884} 3885 3886/* 3887 * Read the load status for the current engine. 3888 * 3889 * should be run under rtnl lock 3890 */ 3891static inline bool bnx2x_get_load_status(struct bnx2x *bp, int engine) 3892{ 3893 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 3894 BNX2X_PATH0_LOAD_CNT_MASK); 3895 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3896 BNX2X_PATH0_LOAD_CNT_SHIFT); 3897 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3898 3899 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val); 3900 3901 val = (val & mask) >> shift; 3902 3903 DP(NETIF_MSG_HW, "load mask for engine %d = 0x%x\n", engine, val); 3904 3905 return val != 0; 3906} 3907 3908/* 3909 * Reset the load status for the current engine. 3910 */ 3911static inline void bnx2x_clear_load_status(struct bnx2x *bp) 3912{ 3913 u32 val; 3914 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3915 BNX2X_PATH0_LOAD_CNT_MASK); 3916 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3917 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3918 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); 3919 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3920} 3921 3922static inline void _print_next_block(int idx, const char *blk) 3923{ 3924 pr_cont("%s%s", idx ? ", " : "", blk); 3925} 3926 3927static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, 3928 bool print) 3929{ 3930 int i = 0; 3931 u32 cur_bit = 0; 3932 for (i = 0; sig; i++) { 3933 cur_bit = ((u32)0x1 << i); 3934 if (sig & cur_bit) { 3935 switch (cur_bit) { 3936 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 3937 if (print) 3938 _print_next_block(par_num++, "BRB"); 3939 break; 3940 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 3941 if (print) 3942 _print_next_block(par_num++, "PARSER"); 3943 break; 3944 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 3945 if (print) 3946 _print_next_block(par_num++, "TSDM"); 3947 break; 3948 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 3949 if (print) 3950 _print_next_block(par_num++, 3951 "SEARCHER"); 3952 break; 3953 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 3954 if (print) 3955 _print_next_block(par_num++, "TCM"); 3956 break; 3957 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 3958 if (print) 3959 _print_next_block(par_num++, "TSEMI"); 3960 break; 3961 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 3962 if (print) 3963 _print_next_block(par_num++, "XPB"); 3964 break; 3965 } 3966 3967 /* Clear the bit */ 3968 sig &= ~cur_bit; 3969 } 3970 } 3971 3972 return par_num; 3973} 3974 3975static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, 3976 bool *global, bool print) 3977{ 3978 int i = 0; 3979 u32 cur_bit = 0; 3980 for (i = 0; sig; i++) { 3981 cur_bit = ((u32)0x1 << i); 3982 if (sig & cur_bit) { 3983 switch (cur_bit) { 3984 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 3985 if (print) 3986 _print_next_block(par_num++, "PBF"); 3987 break; 3988 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 3989 if (print) 3990 _print_next_block(par_num++, "QM"); 3991 break; 3992 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 3993 if (print) 3994 _print_next_block(par_num++, "TM"); 3995 break; 3996 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 3997 if (print) 3998 _print_next_block(par_num++, "XSDM"); 3999 break; 4000 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 4001 if (print) 4002 _print_next_block(par_num++, "XCM"); 4003 break; 4004 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 4005 if (print) 4006 _print_next_block(par_num++, "XSEMI"); 4007 break; 4008 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 4009 if (print) 4010 _print_next_block(par_num++, 4011 "DOORBELLQ"); 4012 break; 4013 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 4014 if (print) 4015 _print_next_block(par_num++, "NIG"); 4016 break; 4017 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 4018 if (print) 4019 _print_next_block(par_num++, 4020 "VAUX PCI CORE"); 4021 *global = true; 4022 break; 4023 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 4024 if (print) 4025 _print_next_block(par_num++, "DEBUG"); 4026 break; 4027 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 4028 if (print) 4029 _print_next_block(par_num++, "USDM"); 4030 break; 4031 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 4032 if (print) 4033 _print_next_block(par_num++, "UCM"); 4034 break; 4035 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 4036 if (print) 4037 _print_next_block(par_num++, "USEMI"); 4038 break; 4039 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 4040 if (print) 4041 _print_next_block(par_num++, "UPB"); 4042 break; 4043 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 4044 if (print) 4045 _print_next_block(par_num++, "CSDM"); 4046 break; 4047 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 4048 if (print) 4049 _print_next_block(par_num++, "CCM"); 4050 break; 4051 } 4052 4053 /* Clear the bit */ 4054 sig &= ~cur_bit; 4055 } 4056 } 4057 4058 return par_num; 4059} 4060 4061static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, 4062 bool print) 4063{ 4064 int i = 0; 4065 u32 cur_bit = 0; 4066 for (i = 0; sig; i++) { 4067 cur_bit = ((u32)0x1 << i); 4068 if (sig & cur_bit) { 4069 switch (cur_bit) { 4070 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 4071 if (print) 4072 _print_next_block(par_num++, "CSEMI"); 4073 break; 4074 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 4075 if (print) 4076 _print_next_block(par_num++, "PXP"); 4077 break; 4078 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 4079 if (print) 4080 _print_next_block(par_num++, 4081 "PXPPCICLOCKCLIENT"); 4082 break; 4083 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 4084 if (print) 4085 _print_next_block(par_num++, "CFC"); 4086 break; 4087 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 4088 if (print) 4089 _print_next_block(par_num++, "CDU"); 4090 break; 4091 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 4092 if (print) 4093 _print_next_block(par_num++, "DMAE"); 4094 break; 4095 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 4096 if (print) 4097 _print_next_block(par_num++, "IGU"); 4098 break; 4099 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 4100 if (print) 4101 _print_next_block(par_num++, "MISC"); 4102 break; 4103 } 4104 4105 /* Clear the bit */ 4106 sig &= ~cur_bit; 4107 } 4108 } 4109 4110 return par_num; 4111} 4112 4113static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, 4114 bool *global, bool print) 4115{ 4116 int i = 0; 4117 u32 cur_bit = 0; 4118 for (i = 0; sig; i++) { 4119 cur_bit = ((u32)0x1 << i); 4120 if (sig & cur_bit) { 4121 switch (cur_bit) { 4122 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 4123 if (print) 4124 _print_next_block(par_num++, "MCP ROM"); 4125 *global = true; 4126 break; 4127 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 4128 if (print) 4129 _print_next_block(par_num++, 4130 "MCP UMP RX"); 4131 *global = true; 4132 break; 4133 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 4134 if (print) 4135 _print_next_block(par_num++, 4136 "MCP UMP TX"); 4137 *global = true; 4138 break; 4139 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 4140 if (print) 4141 _print_next_block(par_num++, 4142 "MCP SCPAD"); 4143 *global = true; 4144 break; 4145 } 4146 4147 /* Clear the bit */ 4148 sig &= ~cur_bit; 4149 } 4150 } 4151 4152 return par_num; 4153} 4154 4155static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, 4156 bool print) 4157{ 4158 int i = 0; 4159 u32 cur_bit = 0; 4160 for (i = 0; sig; i++) { 4161 cur_bit = ((u32)0x1 << i); 4162 if (sig & cur_bit) { 4163 switch (cur_bit) { 4164 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 4165 if (print) 4166 _print_next_block(par_num++, "PGLUE_B"); 4167 break; 4168 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 4169 if (print) 4170 _print_next_block(par_num++, "ATC"); 4171 break; 4172 } 4173 4174 /* Clear the bit */ 4175 sig &= ~cur_bit; 4176 } 4177 } 4178 4179 return par_num; 4180} 4181 4182static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4183 u32 *sig) 4184{ 4185 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4186 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4187 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4188 (sig[3] & HW_PRTY_ASSERT_SET_3) || 4189 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4190 int par_num = 0; 4191 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: " 4192 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x " 4193 "[4]:0x%08x\n", 4194 sig[0] & HW_PRTY_ASSERT_SET_0, 4195 sig[1] & HW_PRTY_ASSERT_SET_1, 4196 sig[2] & HW_PRTY_ASSERT_SET_2, 4197 sig[3] & HW_PRTY_ASSERT_SET_3, 4198 sig[4] & HW_PRTY_ASSERT_SET_4); 4199 if (print) 4200 netdev_err(bp->dev, 4201 "Parity errors detected in blocks: "); 4202 par_num = bnx2x_check_blocks_with_parity0( 4203 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); 4204 par_num = bnx2x_check_blocks_with_parity1( 4205 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); 4206 par_num = bnx2x_check_blocks_with_parity2( 4207 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); 4208 par_num = bnx2x_check_blocks_with_parity3( 4209 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); 4210 par_num = bnx2x_check_blocks_with_parity4( 4211 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); 4212 4213 if (print) 4214 pr_cont("\n"); 4215 4216 return true; 4217 } else 4218 return false; 4219} 4220 4221/** 4222 * bnx2x_chk_parity_attn - checks for parity attentions. 4223 * 4224 * @bp: driver handle 4225 * @global: true if there was a global attention 4226 * @print: show parity attention in syslog 4227 */ 4228bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 4229{ 4230 struct attn_route attn = { {0} }; 4231 int port = BP_PORT(bp); 4232 4233 attn.sig[0] = REG_RD(bp, 4234 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 4235 port*4); 4236 attn.sig[1] = REG_RD(bp, 4237 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 4238 port*4); 4239 attn.sig[2] = REG_RD(bp, 4240 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 4241 port*4); 4242 attn.sig[3] = REG_RD(bp, 4243 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 4244 port*4); 4245 4246 if (!CHIP_IS_E1x(bp)) 4247 attn.sig[4] = REG_RD(bp, 4248 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 4249 port*4); 4250 4251 return bnx2x_parity_attn(bp, global, print, attn.sig); 4252} 4253 4254 4255static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 4256{ 4257 u32 val; 4258 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 4259 4260 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 4261 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 4262 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 4263 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4264 "ADDRESS_ERROR\n"); 4265 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 4266 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4267 "INCORRECT_RCV_BEHAVIOR\n"); 4268 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 4269 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4270 "WAS_ERROR_ATTN\n"); 4271 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 4272 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4273 "VF_LENGTH_VIOLATION_ATTN\n"); 4274 if (val & 4275 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 4276 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4277 "VF_GRC_SPACE_VIOLATION_ATTN\n"); 4278 if (val & 4279 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 4280 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4281 "VF_MSIX_BAR_VIOLATION_ATTN\n"); 4282 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 4283 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4284 "TCPL_ERROR_ATTN\n"); 4285 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 4286 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4287 "TCPL_IN_TWO_RCBS_ATTN\n"); 4288 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 4289 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4290 "CSSNOOP_FIFO_OVERFLOW\n"); 4291 } 4292 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 4293 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 4294 BNX2X_ERR("ATC hw attention 0x%x\n", val); 4295 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 4296 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 4297 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 4298 BNX2X_ERR("ATC_ATC_INT_STS_REG" 4299 "_ATC_TCPL_TO_NOT_PEND\n"); 4300 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 4301 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4302 "ATC_GPA_MULTIPLE_HITS\n"); 4303 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 4304 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4305 "ATC_RCPL_TO_EMPTY_CNT\n"); 4306 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 4307 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 4308 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 4309 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4310 "ATC_IREQ_LESS_THAN_STU\n"); 4311 } 4312 4313 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4314 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 4315 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 4316 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4317 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 4318 } 4319 4320} 4321 4322static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 4323{ 4324 struct attn_route attn, *group_mask; 4325 int port = BP_PORT(bp); 4326 int index; 4327 u32 reg_addr; 4328 u32 val; 4329 u32 aeu_mask; 4330 bool global = false; 4331 4332 /* need to take HW lock because MCP or other port might also 4333 try to handle this event */ 4334 bnx2x_acquire_alr(bp); 4335 4336 if (bnx2x_chk_parity_attn(bp, &global, true)) { 4337#ifndef BNX2X_STOP_ON_ERROR 4338 bp->recovery_state = BNX2X_RECOVERY_INIT; 4339 schedule_delayed_work(&bp->sp_rtnl_task, 0); 4340 /* Disable HW interrupts */ 4341 bnx2x_int_disable(bp); 4342 /* In case of parity errors don't handle attentions so that 4343 * other function would "see" parity errors. 4344 */ 4345#else 4346 bnx2x_panic(); 4347#endif 4348 bnx2x_release_alr(bp); 4349 return; 4350 } 4351 4352 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 4353 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 4354 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 4355 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 4356 if (!CHIP_IS_E1x(bp)) 4357 attn.sig[4] = 4358 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 4359 else 4360 attn.sig[4] = 0; 4361 4362 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 4363 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 4364 4365 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4366 if (deasserted & (1 << index)) { 4367 group_mask = &bp->attn_group[index]; 4368 4369 DP(NETIF_MSG_HW, "group[%d]: %08x %08x " 4370 "%08x %08x %08x\n", 4371 index, 4372 group_mask->sig[0], group_mask->sig[1], 4373 group_mask->sig[2], group_mask->sig[3], 4374 group_mask->sig[4]); 4375 4376 bnx2x_attn_int_deasserted4(bp, 4377 attn.sig[4] & group_mask->sig[4]); 4378 bnx2x_attn_int_deasserted3(bp, 4379 attn.sig[3] & group_mask->sig[3]); 4380 bnx2x_attn_int_deasserted1(bp, 4381 attn.sig[1] & group_mask->sig[1]); 4382 bnx2x_attn_int_deasserted2(bp, 4383 attn.sig[2] & group_mask->sig[2]); 4384 bnx2x_attn_int_deasserted0(bp, 4385 attn.sig[0] & group_mask->sig[0]); 4386 } 4387 } 4388 4389 bnx2x_release_alr(bp); 4390 4391 if (bp->common.int_block == INT_BLOCK_HC) 4392 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4393 COMMAND_REG_ATTN_BITS_CLR); 4394 else 4395 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 4396 4397 val = ~deasserted; 4398 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 4399 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4400 REG_WR(bp, reg_addr, val); 4401 4402 if (~bp->attn_state & deasserted) 4403 BNX2X_ERR("IGU ERROR\n"); 4404 4405 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4406 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4407 4408 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4409 aeu_mask = REG_RD(bp, reg_addr); 4410 4411 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 4412 aeu_mask, deasserted); 4413 aeu_mask |= (deasserted & 0x3ff); 4414 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4415 4416 REG_WR(bp, reg_addr, aeu_mask); 4417 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4418 4419 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4420 bp->attn_state &= ~deasserted; 4421 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4422} 4423 4424static void bnx2x_attn_int(struct bnx2x *bp) 4425{ 4426 /* read local copy of bits */ 4427 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 4428 attn_bits); 4429 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 4430 attn_bits_ack); 4431 u32 attn_state = bp->attn_state; 4432 4433 /* look for changed bits */ 4434 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 4435 u32 deasserted = ~attn_bits & attn_ack & attn_state; 4436 4437 DP(NETIF_MSG_HW, 4438 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 4439 attn_bits, attn_ack, asserted, deasserted); 4440 4441 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 4442 BNX2X_ERR("BAD attention state\n"); 4443 4444 /* handle bits that were raised */ 4445 if (asserted) 4446 bnx2x_attn_int_asserted(bp, asserted); 4447 4448 if (deasserted) 4449 bnx2x_attn_int_deasserted(bp, deasserted); 4450} 4451 4452void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 4453 u16 index, u8 op, u8 update) 4454{ 4455 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 4456 4457 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 4458 igu_addr); 4459} 4460 4461static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 4462{ 4463 /* No memory barriers */ 4464 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 4465 mmiowb(); /* keep prod updates ordered */ 4466} 4467 4468#ifdef BCM_CNIC 4469static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 4470 union event_ring_elem *elem) 4471{ 4472 u8 err = elem->message.error; 4473 4474 if (!bp->cnic_eth_dev.starting_cid || 4475 (cid < bp->cnic_eth_dev.starting_cid && 4476 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 4477 return 1; 4478 4479 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 4480 4481 if (unlikely(err)) { 4482 4483 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 4484 cid); 4485 bnx2x_panic_dump(bp); 4486 } 4487 bnx2x_cnic_cfc_comp(bp, cid, err); 4488 return 0; 4489} 4490#endif 4491 4492static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 4493{ 4494 struct bnx2x_mcast_ramrod_params rparam; 4495 int rc; 4496 4497 memset(&rparam, 0, sizeof(rparam)); 4498 4499 rparam.mcast_obj = &bp->mcast_obj; 4500 4501 netif_addr_lock_bh(bp->dev); 4502 4503 /* Clear pending state for the last command */ 4504 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 4505 4506 /* If there are pending mcast commands - send them */ 4507 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 4508 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 4509 if (rc < 0) 4510 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 4511 rc); 4512 } 4513 4514 netif_addr_unlock_bh(bp->dev); 4515} 4516 4517static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp, 4518 union event_ring_elem *elem) 4519{ 4520 unsigned long ramrod_flags = 0; 4521 int rc = 0; 4522 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; 4523 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 4524 4525 /* Always push next commands out, don't wait here */ 4526 __set_bit(RAMROD_CONT, &ramrod_flags); 4527 4528 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 4529 case BNX2X_FILTER_MAC_PENDING: 4530#ifdef BCM_CNIC 4531 if (cid == BNX2X_ISCSI_ETH_CID) 4532 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 4533 else 4534#endif 4535 vlan_mac_obj = &bp->fp[cid].mac_obj; 4536 4537 break; 4538 case BNX2X_FILTER_MCAST_PENDING: 4539 /* This is only relevant for 57710 where multicast MACs are 4540 * configured as unicast MACs using the same ramrod. 4541 */ 4542 bnx2x_handle_mcast_eqe(bp); 4543 return; 4544 default: 4545 BNX2X_ERR("Unsupported classification command: %d\n", 4546 elem->message.data.eth_event.echo); 4547 return; 4548 } 4549 4550 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 4551 4552 if (rc < 0) 4553 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 4554 else if (rc > 0) 4555 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 4556 4557} 4558 4559#ifdef BCM_CNIC 4560static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 4561#endif 4562 4563static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 4564{ 4565 netif_addr_lock_bh(bp->dev); 4566 4567 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 4568 4569 /* Send rx_mode command again if was requested */ 4570 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 4571 bnx2x_set_storm_rx_mode(bp); 4572#ifdef BCM_CNIC 4573 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 4574 &bp->sp_state)) 4575 bnx2x_set_iscsi_eth_rx_mode(bp, true); 4576 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 4577 &bp->sp_state)) 4578 bnx2x_set_iscsi_eth_rx_mode(bp, false); 4579#endif 4580 4581 netif_addr_unlock_bh(bp->dev); 4582} 4583 4584static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 4585 struct bnx2x *bp, u32 cid) 4586{ 4587 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 4588#ifdef BCM_CNIC 4589 if (cid == BNX2X_FCOE_ETH_CID) 4590 return &bnx2x_fcoe(bp, q_obj); 4591 else 4592#endif 4593 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj); 4594} 4595 4596static void bnx2x_eq_int(struct bnx2x *bp) 4597{ 4598 u16 hw_cons, sw_cons, sw_prod; 4599 union event_ring_elem *elem; 4600 u32 cid; 4601 u8 opcode; 4602 int spqe_cnt = 0; 4603 struct bnx2x_queue_sp_obj *q_obj; 4604 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 4605 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 4606 4607 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 4608 4609 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 4610 * when we get the the next-page we nned to adjust so the loop 4611 * condition below will be met. The next element is the size of a 4612 * regular element and hence incrementing by 1 4613 */ 4614 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 4615 hw_cons++; 4616 4617 /* This function may never run in parallel with itself for a 4618 * specific bp, thus there is no need in "paired" read memory 4619 * barrier here. 4620 */ 4621 sw_cons = bp->eq_cons; 4622 sw_prod = bp->eq_prod; 4623 4624 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 4625 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 4626 4627 for (; sw_cons != hw_cons; 4628 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 4629 4630 4631 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 4632 4633 cid = SW_CID(elem->message.data.cfc_del_event.cid); 4634 opcode = elem->message.opcode; 4635 4636 4637 /* handle eq element */ 4638 switch (opcode) { 4639 case EVENT_RING_OPCODE_STAT_QUERY: 4640 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n", 4641 bp->stats_comp++); 4642 /* nothing to do with stats comp */ 4643 goto next_spqe; 4644 4645 case EVENT_RING_OPCODE_CFC_DEL: 4646 /* handle according to cid range */ 4647 /* 4648 * we may want to verify here that the bp state is 4649 * HALTING 4650 */ 4651 DP(BNX2X_MSG_SP, 4652 "got delete ramrod for MULTI[%d]\n", cid); 4653#ifdef BCM_CNIC 4654 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 4655 goto next_spqe; 4656#endif 4657 q_obj = bnx2x_cid_to_q_obj(bp, cid); 4658 4659 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 4660 break; 4661 4662 4663 4664 goto next_spqe; 4665 4666 case EVENT_RING_OPCODE_STOP_TRAFFIC: 4667 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n"); 4668 if (f_obj->complete_cmd(bp, f_obj, 4669 BNX2X_F_CMD_TX_STOP)) 4670 break; 4671 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 4672 goto next_spqe; 4673 4674 case EVENT_RING_OPCODE_START_TRAFFIC: 4675 DP(BNX2X_MSG_SP, "got START TRAFFIC\n"); 4676 if (f_obj->complete_cmd(bp, f_obj, 4677 BNX2X_F_CMD_TX_START)) 4678 break; 4679 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 4680 goto next_spqe; 4681 case EVENT_RING_OPCODE_FUNCTION_START: 4682 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n"); 4683 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 4684 break; 4685 4686 goto next_spqe; 4687 4688 case EVENT_RING_OPCODE_FUNCTION_STOP: 4689 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n"); 4690 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 4691 break; 4692 4693 goto next_spqe; 4694 } 4695 4696 switch (opcode | bp->state) { 4697 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4698 BNX2X_STATE_OPEN): 4699 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4700 BNX2X_STATE_OPENING_WAIT4_PORT): 4701 cid = elem->message.data.eth_event.echo & 4702 BNX2X_SWCID_MASK; 4703 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 4704 cid); 4705 rss_raw->clear_pending(rss_raw); 4706 break; 4707 4708 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 4709 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 4710 case (EVENT_RING_OPCODE_SET_MAC | 4711 BNX2X_STATE_CLOSING_WAIT4_HALT): 4712 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4713 BNX2X_STATE_OPEN): 4714 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4715 BNX2X_STATE_DIAG): 4716 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4717 BNX2X_STATE_CLOSING_WAIT4_HALT): 4718 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); 4719 bnx2x_handle_classification_eqe(bp, elem); 4720 break; 4721 4722 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4723 BNX2X_STATE_OPEN): 4724 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4725 BNX2X_STATE_DIAG): 4726 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4727 BNX2X_STATE_CLOSING_WAIT4_HALT): 4728 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 4729 bnx2x_handle_mcast_eqe(bp); 4730 break; 4731 4732 case (EVENT_RING_OPCODE_FILTERS_RULES | 4733 BNX2X_STATE_OPEN): 4734 case (EVENT_RING_OPCODE_FILTERS_RULES | 4735 BNX2X_STATE_DIAG): 4736 case (EVENT_RING_OPCODE_FILTERS_RULES | 4737 BNX2X_STATE_CLOSING_WAIT4_HALT): 4738 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 4739 bnx2x_handle_rx_mode_eqe(bp); 4740 break; 4741 default: 4742 /* unknown event log error and continue */ 4743 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 4744 elem->message.opcode, bp->state); 4745 } 4746next_spqe: 4747 spqe_cnt++; 4748 } /* for */ 4749 4750 smp_mb__before_atomic_inc(); 4751 atomic_add(spqe_cnt, &bp->eq_spq_left); 4752 4753 bp->eq_cons = sw_cons; 4754 bp->eq_prod = sw_prod; 4755 /* Make sure that above mem writes were issued towards the memory */ 4756 smp_wmb(); 4757 4758 /* update producer */ 4759 bnx2x_update_eq_prod(bp, bp->eq_prod); 4760} 4761 4762static void bnx2x_sp_task(struct work_struct *work) 4763{ 4764 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 4765 u16 status; 4766 4767 status = bnx2x_update_dsb_idx(bp); 4768/* if (status == 0) */ 4769/* BNX2X_ERR("spurious slowpath interrupt!\n"); */ 4770 4771 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status); 4772 4773 /* HW attentions */ 4774 if (status & BNX2X_DEF_SB_ATT_IDX) { 4775 bnx2x_attn_int(bp); 4776 status &= ~BNX2X_DEF_SB_ATT_IDX; 4777 } 4778 4779 /* SP events: STAT_QUERY and others */ 4780 if (status & BNX2X_DEF_SB_IDX) { 4781#ifdef BCM_CNIC 4782 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 4783 4784 if ((!NO_FCOE(bp)) && 4785 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 4786 /* 4787 * Prevent local bottom-halves from running as 4788 * we are going to change the local NAPI list. 4789 */ 4790 local_bh_disable(); 4791 napi_schedule(&bnx2x_fcoe(bp, napi)); 4792 local_bh_enable(); 4793 } 4794#endif 4795 /* Handle EQ completions */ 4796 bnx2x_eq_int(bp); 4797 4798 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 4799 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 4800 4801 status &= ~BNX2X_DEF_SB_IDX; 4802 } 4803 4804 if (unlikely(status)) 4805 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 4806 status); 4807 4808 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 4809 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 4810} 4811 4812irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 4813{ 4814 struct net_device *dev = dev_instance; 4815 struct bnx2x *bp = netdev_priv(dev); 4816 4817 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 4818 IGU_INT_DISABLE, 0); 4819 4820#ifdef BNX2X_STOP_ON_ERROR 4821 if (unlikely(bp->panic)) 4822 return IRQ_HANDLED; 4823#endif 4824 4825#ifdef BCM_CNIC 4826 { 4827 struct cnic_ops *c_ops; 4828 4829 rcu_read_lock(); 4830 c_ops = rcu_dereference(bp->cnic_ops); 4831 if (c_ops) 4832 c_ops->cnic_handler(bp->cnic_data, NULL); 4833 rcu_read_unlock(); 4834 } 4835#endif 4836 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 4837 4838 return IRQ_HANDLED; 4839} 4840 4841/* end of slow path */ 4842 4843 4844void bnx2x_drv_pulse(struct bnx2x *bp) 4845{ 4846 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 4847 bp->fw_drv_pulse_wr_seq); 4848} 4849 4850 4851static void bnx2x_timer(unsigned long data) 4852{ 4853 u8 cos; 4854 struct bnx2x *bp = (struct bnx2x *) data; 4855 4856 if (!netif_running(bp->dev)) 4857 return; 4858 4859 if (poll) { 4860 struct bnx2x_fastpath *fp = &bp->fp[0]; 4861 4862 for_each_cos_in_tx_queue(fp, cos) 4863 bnx2x_tx_int(bp, &fp->txdata[cos]); 4864 bnx2x_rx_int(fp, 1000); 4865 } 4866 4867 if (!BP_NOMCP(bp)) { 4868 int mb_idx = BP_FW_MB_IDX(bp); 4869 u32 drv_pulse; 4870 u32 mcp_pulse; 4871 4872 ++bp->fw_drv_pulse_wr_seq; 4873 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 4874 /* TBD - add SYSTEM_TIME */ 4875 drv_pulse = bp->fw_drv_pulse_wr_seq; 4876 bnx2x_drv_pulse(bp); 4877 4878 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 4879 MCP_PULSE_SEQ_MASK); 4880 /* The delta between driver pulse and mcp response 4881 * should be 1 (before mcp response) or 0 (after mcp response) 4882 */ 4883 if ((drv_pulse != mcp_pulse) && 4884 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 4885 /* someone lost a heartbeat... */ 4886 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 4887 drv_pulse, mcp_pulse); 4888 } 4889 } 4890 4891 if (bp->state == BNX2X_STATE_OPEN) 4892 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 4893 4894 mod_timer(&bp->timer, jiffies + bp->current_interval); 4895} 4896 4897/* end of Statistics */ 4898 4899/* nic init */ 4900 4901/* 4902 * nic init service functions 4903 */ 4904 4905static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 4906{ 4907 u32 i; 4908 if (!(len%4) && !(addr%4)) 4909 for (i = 0; i < len; i += 4) 4910 REG_WR(bp, addr + i, fill); 4911 else 4912 for (i = 0; i < len; i++) 4913 REG_WR8(bp, addr + i, fill); 4914 4915} 4916 4917/* helper: writes FP SP data to FW - data_size in dwords */ 4918static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 4919 int fw_sb_id, 4920 u32 *sb_data_p, 4921 u32 data_size) 4922{ 4923 int index; 4924 for (index = 0; index < data_size; index++) 4925 REG_WR(bp, BAR_CSTRORM_INTMEM + 4926 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 4927 sizeof(u32)*index, 4928 *(sb_data_p + index)); 4929} 4930 4931static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 4932{ 4933 u32 *sb_data_p; 4934 u32 data_size = 0; 4935 struct hc_status_block_data_e2 sb_data_e2; 4936 struct hc_status_block_data_e1x sb_data_e1x; 4937 4938 /* disable the function first */ 4939 if (!CHIP_IS_E1x(bp)) { 4940 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 4941 sb_data_e2.common.state = SB_DISABLED; 4942 sb_data_e2.common.p_func.vf_valid = false; 4943 sb_data_p = (u32 *)&sb_data_e2; 4944 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 4945 } else { 4946 memset(&sb_data_e1x, 0, 4947 sizeof(struct hc_status_block_data_e1x)); 4948 sb_data_e1x.common.state = SB_DISABLED; 4949 sb_data_e1x.common.p_func.vf_valid = false; 4950 sb_data_p = (u32 *)&sb_data_e1x; 4951 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 4952 } 4953 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 4954 4955 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4956 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 4957 CSTORM_STATUS_BLOCK_SIZE); 4958 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4959 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 4960 CSTORM_SYNC_BLOCK_SIZE); 4961} 4962 4963/* helper: writes SP SB data to FW */ 4964static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 4965 struct hc_sp_status_block_data *sp_sb_data) 4966{ 4967 int func = BP_FUNC(bp); 4968 int i; 4969 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 4970 REG_WR(bp, BAR_CSTRORM_INTMEM + 4971 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 4972 i*sizeof(u32), 4973 *((u32 *)sp_sb_data + i)); 4974} 4975 4976static inline void bnx2x_zero_sp_sb(struct bnx2x *bp) 4977{ 4978 int func = BP_FUNC(bp); 4979 struct hc_sp_status_block_data sp_sb_data; 4980 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 4981 4982 sp_sb_data.state = SB_DISABLED; 4983 sp_sb_data.p_func.vf_valid = false; 4984 4985 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 4986 4987 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4988 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 4989 CSTORM_SP_STATUS_BLOCK_SIZE); 4990 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4991 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 4992 CSTORM_SP_SYNC_BLOCK_SIZE); 4993 4994} 4995 4996 4997static inline 4998void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 4999 int igu_sb_id, int igu_seg_id) 5000{ 5001 hc_sm->igu_sb_id = igu_sb_id; 5002 hc_sm->igu_seg_id = igu_seg_id; 5003 hc_sm->timer_value = 0xFF; 5004 hc_sm->time_to_expire = 0xFFFFFFFF; 5005} 5006 5007 5008/* allocates state machine ids. */ 5009static inline 5010void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) 5011{ 5012 /* zero out state machine indices */ 5013 /* rx indices */ 5014 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5015 5016 /* tx indices */ 5017 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5018 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 5019 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 5020 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 5021 5022 /* map indices */ 5023 /* rx indices */ 5024 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 5025 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5026 5027 /* tx indices */ 5028 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 5029 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5030 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 5031 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5032 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 5033 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5034 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 5035 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5036} 5037 5038static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 5039 u8 vf_valid, int fw_sb_id, int igu_sb_id) 5040{ 5041 int igu_seg_id; 5042 5043 struct hc_status_block_data_e2 sb_data_e2; 5044 struct hc_status_block_data_e1x sb_data_e1x; 5045 struct hc_status_block_sm *hc_sm_p; 5046 int data_size; 5047 u32 *sb_data_p; 5048 5049 if (CHIP_INT_MODE_IS_BC(bp)) 5050 igu_seg_id = HC_SEG_ACCESS_NORM; 5051 else 5052 igu_seg_id = IGU_SEG_ACCESS_NORM; 5053 5054 bnx2x_zero_fp_sb(bp, fw_sb_id); 5055 5056 if (!CHIP_IS_E1x(bp)) { 5057 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5058 sb_data_e2.common.state = SB_ENABLED; 5059 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 5060 sb_data_e2.common.p_func.vf_id = vfid; 5061 sb_data_e2.common.p_func.vf_valid = vf_valid; 5062 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 5063 sb_data_e2.common.same_igu_sb_1b = true; 5064 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 5065 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 5066 hc_sm_p = sb_data_e2.common.state_machine; 5067 sb_data_p = (u32 *)&sb_data_e2; 5068 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5069 bnx2x_map_sb_state_machines(sb_data_e2.index_data); 5070 } else { 5071 memset(&sb_data_e1x, 0, 5072 sizeof(struct hc_status_block_data_e1x)); 5073 sb_data_e1x.common.state = SB_ENABLED; 5074 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 5075 sb_data_e1x.common.p_func.vf_id = 0xff; 5076 sb_data_e1x.common.p_func.vf_valid = false; 5077 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 5078 sb_data_e1x.common.same_igu_sb_1b = true; 5079 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 5080 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 5081 hc_sm_p = sb_data_e1x.common.state_machine; 5082 sb_data_p = (u32 *)&sb_data_e1x; 5083 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5084 bnx2x_map_sb_state_machines(sb_data_e1x.index_data); 5085 } 5086 5087 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 5088 igu_sb_id, igu_seg_id); 5089 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 5090 igu_sb_id, igu_seg_id); 5091 5092 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id); 5093 5094 /* write indecies to HW */ 5095 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5096} 5097 5098static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 5099 u16 tx_usec, u16 rx_usec) 5100{ 5101 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 5102 false, rx_usec); 5103 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5104 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 5105 tx_usec); 5106 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5107 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 5108 tx_usec); 5109 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5110 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 5111 tx_usec); 5112} 5113 5114static void bnx2x_init_def_sb(struct bnx2x *bp) 5115{ 5116 struct host_sp_status_block *def_sb = bp->def_status_blk; 5117 dma_addr_t mapping = bp->def_status_blk_mapping; 5118 int igu_sp_sb_index; 5119 int igu_seg_id; 5120 int port = BP_PORT(bp); 5121 int func = BP_FUNC(bp); 5122 int reg_offset, reg_offset_en5; 5123 u64 section; 5124 int index; 5125 struct hc_sp_status_block_data sp_sb_data; 5126 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5127 5128 if (CHIP_INT_MODE_IS_BC(bp)) { 5129 igu_sp_sb_index = DEF_SB_IGU_ID; 5130 igu_seg_id = HC_SEG_ACCESS_DEF; 5131 } else { 5132 igu_sp_sb_index = bp->igu_dsb_id; 5133 igu_seg_id = IGU_SEG_ACCESS_DEF; 5134 } 5135 5136 /* ATTN */ 5137 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5138 atten_status_block); 5139 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 5140 5141 bp->attn_state = 0; 5142 5143 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 5144 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 5145 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 5146 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); 5147 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 5148 int sindex; 5149 /* take care of sig[0]..sig[4] */ 5150 for (sindex = 0; sindex < 4; sindex++) 5151 bp->attn_group[index].sig[sindex] = 5152 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 5153 5154 if (!CHIP_IS_E1x(bp)) 5155 /* 5156 * enable5 is separate from the rest of the registers, 5157 * and therefore the address skip is 4 5158 * and not 16 between the different groups 5159 */ 5160 bp->attn_group[index].sig[4] = REG_RD(bp, 5161 reg_offset_en5 + 0x4*index); 5162 else 5163 bp->attn_group[index].sig[4] = 0; 5164 } 5165 5166 if (bp->common.int_block == INT_BLOCK_HC) { 5167 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 5168 HC_REG_ATTN_MSG0_ADDR_L); 5169 5170 REG_WR(bp, reg_offset, U64_LO(section)); 5171 REG_WR(bp, reg_offset + 4, U64_HI(section)); 5172 } else if (!CHIP_IS_E1x(bp)) { 5173 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 5174 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 5175 } 5176 5177 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5178 sp_sb); 5179 5180 bnx2x_zero_sp_sb(bp); 5181 5182 sp_sb_data.state = SB_ENABLED; 5183 sp_sb_data.host_sb_addr.lo = U64_LO(section); 5184 sp_sb_data.host_sb_addr.hi = U64_HI(section); 5185 sp_sb_data.igu_sb_id = igu_sp_sb_index; 5186 sp_sb_data.igu_seg_id = igu_seg_id; 5187 sp_sb_data.p_func.pf_id = func; 5188 sp_sb_data.p_func.vnic_id = BP_VN(bp); 5189 sp_sb_data.p_func.vf_id = 0xff; 5190 5191 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5192 5193 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 5194} 5195 5196void bnx2x_update_coalesce(struct bnx2x *bp) 5197{ 5198 int i; 5199 5200 for_each_eth_queue(bp, i) 5201 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 5202 bp->tx_ticks, bp->rx_ticks); 5203} 5204 5205static void bnx2x_init_sp_ring(struct bnx2x *bp) 5206{ 5207 spin_lock_init(&bp->spq_lock); 5208 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 5209 5210 bp->spq_prod_idx = 0; 5211 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 5212 bp->spq_prod_bd = bp->spq; 5213 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 5214} 5215 5216static void bnx2x_init_eq_ring(struct bnx2x *bp) 5217{ 5218 int i; 5219 for (i = 1; i <= NUM_EQ_PAGES; i++) { 5220 union event_ring_elem *elem = 5221 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 5222 5223 elem->next_page.addr.hi = 5224 cpu_to_le32(U64_HI(bp->eq_mapping + 5225 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 5226 elem->next_page.addr.lo = 5227 cpu_to_le32(U64_LO(bp->eq_mapping + 5228 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 5229 } 5230 bp->eq_cons = 0; 5231 bp->eq_prod = NUM_EQ_DESC; 5232 bp->eq_cons_sb = BNX2X_EQ_INDEX; 5233 /* we want a warning message before it gets rought... */ 5234 atomic_set(&bp->eq_spq_left, 5235 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 5236} 5237 5238 5239/* called with netif_addr_lock_bh() */ 5240void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 5241 unsigned long rx_mode_flags, 5242 unsigned long rx_accept_flags, 5243 unsigned long tx_accept_flags, 5244 unsigned long ramrod_flags) 5245{ 5246 struct bnx2x_rx_mode_ramrod_params ramrod_param; 5247 int rc; 5248 5249 memset(&ramrod_param, 0, sizeof(ramrod_param)); 5250 5251 /* Prepare ramrod parameters */ 5252 ramrod_param.cid = 0; 5253 ramrod_param.cl_id = cl_id; 5254 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 5255 ramrod_param.func_id = BP_FUNC(bp); 5256 5257 ramrod_param.pstate = &bp->sp_state; 5258 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 5259 5260 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 5261 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 5262 5263 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5264 5265 ramrod_param.ramrod_flags = ramrod_flags; 5266 ramrod_param.rx_mode_flags = rx_mode_flags; 5267 5268 ramrod_param.rx_accept_flags = rx_accept_flags; 5269 ramrod_param.tx_accept_flags = tx_accept_flags; 5270 5271 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 5272 if (rc < 0) { 5273 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 5274 return; 5275 } 5276} 5277 5278/* called with netif_addr_lock_bh() */ 5279void bnx2x_set_storm_rx_mode(struct bnx2x *bp) 5280{ 5281 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 5282 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 5283 5284#ifdef BCM_CNIC 5285 if (!NO_FCOE(bp)) 5286 5287 /* Configure rx_mode of FCoE Queue */ 5288 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 5289#endif 5290 5291 switch (bp->rx_mode) { 5292 case BNX2X_RX_MODE_NONE: 5293 /* 5294 * 'drop all' supersedes any accept flags that may have been 5295 * passed to the function. 5296 */ 5297 break; 5298 case BNX2X_RX_MODE_NORMAL: 5299 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5300 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); 5301 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5302 5303 /* internal switching mode */ 5304 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5305 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); 5306 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5307 5308 break; 5309 case BNX2X_RX_MODE_ALLMULTI: 5310 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5311 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5312 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5313 5314 /* internal switching mode */ 5315 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5316 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5317 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5318 5319 break; 5320 case BNX2X_RX_MODE_PROMISC: 5321 /* According to deffinition of SI mode, iface in promisc mode 5322 * should receive matched and unmatched (in resolution of port) 5323 * unicast packets. 5324 */ 5325 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); 5326 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5327 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5328 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5329 5330 /* internal switching mode */ 5331 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5332 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5333 5334 if (IS_MF_SI(bp)) 5335 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); 5336 else 5337 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5338 5339 break; 5340 default: 5341 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); 5342 return; 5343 } 5344 5345 if (bp->rx_mode != BNX2X_RX_MODE_NONE) { 5346 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); 5347 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); 5348 } 5349 5350 __set_bit(RAMROD_RX, &ramrod_flags); 5351 __set_bit(RAMROD_TX, &ramrod_flags); 5352 5353 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, 5354 tx_accept_flags, ramrod_flags); 5355} 5356 5357static void bnx2x_init_internal_common(struct bnx2x *bp) 5358{ 5359 int i; 5360 5361 if (IS_MF_SI(bp)) 5362 /* 5363 * In switch independent mode, the TSTORM needs to accept 5364 * packets that failed classification, since approximate match 5365 * mac addresses aren't written to NIG LLH 5366 */ 5367 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5368 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); 5369 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ 5370 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5371 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); 5372 5373 /* Zero this manually as its initialization is 5374 currently missing in the initTool */ 5375 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 5376 REG_WR(bp, BAR_USTRORM_INTMEM + 5377 USTORM_AGG_DATA_OFFSET + i * 4, 0); 5378 if (!CHIP_IS_E1x(bp)) { 5379 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 5380 CHIP_INT_MODE_IS_BC(bp) ? 5381 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 5382 } 5383} 5384 5385static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 5386{ 5387 switch (load_code) { 5388 case FW_MSG_CODE_DRV_LOAD_COMMON: 5389 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5390 bnx2x_init_internal_common(bp); 5391 /* no break */ 5392 5393 case FW_MSG_CODE_DRV_LOAD_PORT: 5394 /* nothing to do */ 5395 /* no break */ 5396 5397 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5398 /* internal memory per function is 5399 initialized inside bnx2x_pf_init */ 5400 break; 5401 5402 default: 5403 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5404 break; 5405 } 5406} 5407 5408static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 5409{ 5410 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; 5411} 5412 5413static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 5414{ 5415 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; 5416} 5417 5418static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 5419{ 5420 if (CHIP_IS_E1x(fp->bp)) 5421 return BP_L_ID(fp->bp) + fp->index; 5422 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 5423 return bnx2x_fp_igu_sb_id(fp); 5424} 5425 5426static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 5427{ 5428 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 5429 u8 cos; 5430 unsigned long q_type = 0; 5431 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 5432 fp->rx_queue = fp_idx; 5433 fp->cid = fp_idx; 5434 fp->cl_id = bnx2x_fp_cl_id(fp); 5435 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 5436 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 5437 /* qZone id equals to FW (per path) client id */ 5438 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 5439 5440 /* init shortcut */ 5441 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 5442 /* Setup SB indicies */ 5443 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 5444 5445 /* Configure Queue State object */ 5446 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 5447 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 5448 5449 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 5450 5451 /* init tx data */ 5452 for_each_cos_in_tx_queue(fp, cos) { 5453 bnx2x_init_txdata(bp, &fp->txdata[cos], 5454 CID_COS_TO_TX_ONLY_CID(fp->cid, cos), 5455 FP_COS_TO_TXQ(fp, cos), 5456 BNX2X_TX_SB_INDEX_BASE + cos); 5457 cids[cos] = fp->txdata[cos].cid; 5458 } 5459 5460 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos, 5461 BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 5462 bnx2x_sp_mapping(bp, q_rdata), q_type); 5463 5464 /** 5465 * Configure classification DBs: Always enable Tx switching 5466 */ 5467 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 5468 5469 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) " 5470 "cl_id %d fw_sb %d igu_sb %d\n", 5471 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 5472 fp->igu_sb_id); 5473 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 5474 fp->fw_sb_id, fp->igu_sb_id); 5475 5476 bnx2x_update_fpsb_idx(fp); 5477} 5478 5479void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) 5480{ 5481 int i; 5482 5483 for_each_eth_queue(bp, i) 5484 bnx2x_init_eth_fp(bp, i); 5485#ifdef BCM_CNIC 5486 if (!NO_FCOE(bp)) 5487 bnx2x_init_fcoe_fp(bp); 5488 5489 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 5490 BNX2X_VF_ID_INVALID, false, 5491 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 5492 5493#endif 5494 5495 /* Initialize MOD_ABS interrupts */ 5496 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 5497 bp->common.shmem_base, bp->common.shmem2_base, 5498 BP_PORT(bp)); 5499 /* ensure status block indices were read */ 5500 rmb(); 5501 5502 bnx2x_init_def_sb(bp); 5503 bnx2x_update_dsb_idx(bp); 5504 bnx2x_init_rx_rings(bp); 5505 bnx2x_init_tx_rings(bp); 5506 bnx2x_init_sp_ring(bp); 5507 bnx2x_init_eq_ring(bp); 5508 bnx2x_init_internal(bp, load_code); 5509 bnx2x_pf_init(bp); 5510 bnx2x_stats_init(bp); 5511 5512 /* flush all before enabling interrupts */ 5513 mb(); 5514 mmiowb(); 5515 5516 bnx2x_int_enable(bp); 5517 5518 /* Check for SPIO5 */ 5519 bnx2x_attn_int_deasserted0(bp, 5520 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 5521 AEU_INPUTS_ATTN_BITS_SPIO5); 5522} 5523 5524/* end of nic init */ 5525 5526/* 5527 * gzip service functions 5528 */ 5529 5530static int bnx2x_gunzip_init(struct bnx2x *bp) 5531{ 5532 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 5533 &bp->gunzip_mapping, GFP_KERNEL); 5534 if (bp->gunzip_buf == NULL) 5535 goto gunzip_nomem1; 5536 5537 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 5538 if (bp->strm == NULL) 5539 goto gunzip_nomem2; 5540 5541 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 5542 if (bp->strm->workspace == NULL) 5543 goto gunzip_nomem3; 5544 5545 return 0; 5546 5547gunzip_nomem3: 5548 kfree(bp->strm); 5549 bp->strm = NULL; 5550 5551gunzip_nomem2: 5552 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5553 bp->gunzip_mapping); 5554 bp->gunzip_buf = NULL; 5555 5556gunzip_nomem1: 5557 netdev_err(bp->dev, "Cannot allocate firmware buffer for" 5558 " un-compression\n"); 5559 return -ENOMEM; 5560} 5561 5562static void bnx2x_gunzip_end(struct bnx2x *bp) 5563{ 5564 if (bp->strm) { 5565 vfree(bp->strm->workspace); 5566 kfree(bp->strm); 5567 bp->strm = NULL; 5568 } 5569 5570 if (bp->gunzip_buf) { 5571 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5572 bp->gunzip_mapping); 5573 bp->gunzip_buf = NULL; 5574 } 5575} 5576 5577static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 5578{ 5579 int n, rc; 5580 5581 /* check gzip header */ 5582 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 5583 BNX2X_ERR("Bad gzip header\n"); 5584 return -EINVAL; 5585 } 5586 5587 n = 10; 5588 5589#define FNAME 0x8 5590 5591 if (zbuf[3] & FNAME) 5592 while ((zbuf[n++] != 0) && (n < len)); 5593 5594 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 5595 bp->strm->avail_in = len - n; 5596 bp->strm->next_out = bp->gunzip_buf; 5597 bp->strm->avail_out = FW_BUF_SIZE; 5598 5599 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 5600 if (rc != Z_OK) 5601 return rc; 5602 5603 rc = zlib_inflate(bp->strm, Z_FINISH); 5604 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 5605 netdev_err(bp->dev, "Firmware decompression error: %s\n", 5606 bp->strm->msg); 5607 5608 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 5609 if (bp->gunzip_outlen & 0x3) 5610 netdev_err(bp->dev, "Firmware decompression error:" 5611 " gunzip_outlen (%d) not aligned\n", 5612 bp->gunzip_outlen); 5613 bp->gunzip_outlen >>= 2; 5614 5615 zlib_inflateEnd(bp->strm); 5616 5617 if (rc == Z_STREAM_END) 5618 return 0; 5619 5620 return rc; 5621} 5622 5623/* nic load/unload */ 5624 5625/* 5626 * General service functions 5627 */ 5628 5629/* send a NIG loopback debug packet */ 5630static void bnx2x_lb_pckt(struct bnx2x *bp) 5631{ 5632 u32 wb_write[3]; 5633 5634 /* Ethernet source and destination addresses */ 5635 wb_write[0] = 0x55555555; 5636 wb_write[1] = 0x55555555; 5637 wb_write[2] = 0x20; /* SOP */ 5638 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5639 5640 /* NON-IP protocol */ 5641 wb_write[0] = 0x09000000; 5642 wb_write[1] = 0x55555555; 5643 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 5644 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5645} 5646 5647/* some of the internal memories 5648 * are not directly readable from the driver 5649 * to test them we send debug packets 5650 */ 5651static int bnx2x_int_mem_test(struct bnx2x *bp) 5652{ 5653 int factor; 5654 int count, i; 5655 u32 val = 0; 5656 5657 if (CHIP_REV_IS_FPGA(bp)) 5658 factor = 120; 5659 else if (CHIP_REV_IS_EMUL(bp)) 5660 factor = 200; 5661 else 5662 factor = 1; 5663 5664 /* Disable inputs of parser neighbor blocks */ 5665 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5666 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5667 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5668 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5669 5670 /* Write 0 to parser credits for CFC search request */ 5671 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5672 5673 /* send Ethernet packet */ 5674 bnx2x_lb_pckt(bp); 5675 5676 /* TODO do i reset NIG statistic? */ 5677 /* Wait until NIG register shows 1 packet of size 0x10 */ 5678 count = 1000 * factor; 5679 while (count) { 5680 5681 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5682 val = *bnx2x_sp(bp, wb_data[0]); 5683 if (val == 0x10) 5684 break; 5685 5686 msleep(10); 5687 count--; 5688 } 5689 if (val != 0x10) { 5690 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5691 return -1; 5692 } 5693 5694 /* Wait until PRS register shows 1 packet */ 5695 count = 1000 * factor; 5696 while (count) { 5697 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5698 if (val == 1) 5699 break; 5700 5701 msleep(10); 5702 count--; 5703 } 5704 if (val != 0x1) { 5705 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5706 return -2; 5707 } 5708 5709 /* Reset and init BRB, PRS */ 5710 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5711 msleep(50); 5712 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5713 msleep(50); 5714 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5715 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5716 5717 DP(NETIF_MSG_HW, "part2\n"); 5718 5719 /* Disable inputs of parser neighbor blocks */ 5720 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5721 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5722 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5723 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5724 5725 /* Write 0 to parser credits for CFC search request */ 5726 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5727 5728 /* send 10 Ethernet packets */ 5729 for (i = 0; i < 10; i++) 5730 bnx2x_lb_pckt(bp); 5731 5732 /* Wait until NIG register shows 10 + 1 5733 packets of size 11*0x10 = 0xb0 */ 5734 count = 1000 * factor; 5735 while (count) { 5736 5737 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5738 val = *bnx2x_sp(bp, wb_data[0]); 5739 if (val == 0xb0) 5740 break; 5741 5742 msleep(10); 5743 count--; 5744 } 5745 if (val != 0xb0) { 5746 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5747 return -3; 5748 } 5749 5750 /* Wait until PRS register shows 2 packets */ 5751 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5752 if (val != 2) 5753 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5754 5755 /* Write 1 to parser credits for CFC search request */ 5756 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 5757 5758 /* Wait until PRS register shows 3 packets */ 5759 msleep(10 * factor); 5760 /* Wait until NIG register shows 1 packet of size 0x10 */ 5761 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5762 if (val != 3) 5763 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5764 5765 /* clear NIG EOP FIFO */ 5766 for (i = 0; i < 11; i++) 5767 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 5768 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 5769 if (val != 1) { 5770 BNX2X_ERR("clear of NIG failed\n"); 5771 return -4; 5772 } 5773 5774 /* Reset and init BRB, PRS, NIG */ 5775 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5776 msleep(50); 5777 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5778 msleep(50); 5779 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5780 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5781#ifndef BCM_CNIC 5782 /* set NIC mode */ 5783 REG_WR(bp, PRS_REG_NIC_MODE, 1); 5784#endif 5785 5786 /* Enable inputs of parser neighbor blocks */ 5787 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 5788 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 5789 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 5790 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 5791 5792 DP(NETIF_MSG_HW, "done\n"); 5793 5794 return 0; /* OK */ 5795} 5796 5797static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 5798{ 5799 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 5800 if (!CHIP_IS_E1x(bp)) 5801 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 5802 else 5803 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 5804 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 5805 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 5806 /* 5807 * mask read length error interrupts in brb for parser 5808 * (parsing unit and 'checksum and crc' unit) 5809 * these errors are legal (PU reads fixed length and CAC can cause 5810 * read length error on truncated packets) 5811 */ 5812 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 5813 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 5814 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 5815 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 5816 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 5817 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 5818/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 5819/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 5820 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 5821 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 5822 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 5823/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 5824/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 5825 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 5826 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 5827 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 5828 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 5829/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 5830/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 5831 5832 if (CHIP_REV_IS_FPGA(bp)) 5833 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); 5834 else if (!CHIP_IS_E1x(bp)) 5835 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 5836 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF 5837 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT 5838 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN 5839 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED 5840 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); 5841 else 5842 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); 5843 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 5844 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 5845 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 5846/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 5847 5848 if (!CHIP_IS_E1x(bp)) 5849 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 5850 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 5851 5852 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 5853 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 5854/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 5855 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 5856} 5857 5858static void bnx2x_reset_common(struct bnx2x *bp) 5859{ 5860 u32 val = 0x1400; 5861 5862 /* reset_common */ 5863 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 5864 0xd3ffff7f); 5865 5866 if (CHIP_IS_E3(bp)) { 5867 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 5868 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 5869 } 5870 5871 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); 5872} 5873 5874static void bnx2x_setup_dmae(struct bnx2x *bp) 5875{ 5876 bp->dmae_ready = 0; 5877 spin_lock_init(&bp->dmae_lock); 5878} 5879 5880static void bnx2x_init_pxp(struct bnx2x *bp) 5881{ 5882 u16 devctl; 5883 int r_order, w_order; 5884 5885 pci_read_config_word(bp->pdev, 5886 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); 5887 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); 5888 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 5889 if (bp->mrrs == -1) 5890 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); 5891 else { 5892 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); 5893 r_order = bp->mrrs; 5894 } 5895 5896 bnx2x_init_pxp_arb(bp, r_order, w_order); 5897} 5898 5899static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 5900{ 5901 int is_required; 5902 u32 val; 5903 int port; 5904 5905 if (BP_NOMCP(bp)) 5906 return; 5907 5908 is_required = 0; 5909 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 5910 SHARED_HW_CFG_FAN_FAILURE_MASK; 5911 5912 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) 5913 is_required = 1; 5914 5915 /* 5916 * The fan failure mechanism is usually related to the PHY type since 5917 * the power consumption of the board is affected by the PHY. Currently, 5918 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 5919 */ 5920 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 5921 for (port = PORT_0; port < PORT_MAX; port++) { 5922 is_required |= 5923 bnx2x_fan_failure_det_req( 5924 bp, 5925 bp->common.shmem_base, 5926 bp->common.shmem2_base, 5927 port); 5928 } 5929 5930 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 5931 5932 if (is_required == 0) 5933 return; 5934 5935 /* Fan failure is indicated by SPIO 5 */ 5936 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, 5937 MISC_REGISTERS_SPIO_INPUT_HI_Z); 5938 5939 /* set to active low mode */ 5940 val = REG_RD(bp, MISC_REG_SPIO_INT); 5941 val |= ((1 << MISC_REGISTERS_SPIO_5) << 5942 MISC_REGISTERS_SPIO_INT_OLD_SET_POS); 5943 REG_WR(bp, MISC_REG_SPIO_INT, val); 5944 5945 /* enable interrupt to signal the IGU */ 5946 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 5947 val |= (1 << MISC_REGISTERS_SPIO_5); 5948 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 5949} 5950 5951static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) 5952{ 5953 u32 offset = 0; 5954 5955 if (CHIP_IS_E1(bp)) 5956 return; 5957 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) 5958 return; 5959 5960 switch (BP_ABS_FUNC(bp)) { 5961 case 0: 5962 offset = PXP2_REG_PGL_PRETEND_FUNC_F0; 5963 break; 5964 case 1: 5965 offset = PXP2_REG_PGL_PRETEND_FUNC_F1; 5966 break; 5967 case 2: 5968 offset = PXP2_REG_PGL_PRETEND_FUNC_F2; 5969 break; 5970 case 3: 5971 offset = PXP2_REG_PGL_PRETEND_FUNC_F3; 5972 break; 5973 case 4: 5974 offset = PXP2_REG_PGL_PRETEND_FUNC_F4; 5975 break; 5976 case 5: 5977 offset = PXP2_REG_PGL_PRETEND_FUNC_F5; 5978 break; 5979 case 6: 5980 offset = PXP2_REG_PGL_PRETEND_FUNC_F6; 5981 break; 5982 case 7: 5983 offset = PXP2_REG_PGL_PRETEND_FUNC_F7; 5984 break; 5985 default: 5986 return; 5987 } 5988 5989 REG_WR(bp, offset, pretend_func_num); 5990 REG_RD(bp, offset); 5991 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); 5992} 5993 5994void bnx2x_pf_disable(struct bnx2x *bp) 5995{ 5996 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 5997 val &= ~IGU_PF_CONF_FUNC_EN; 5998 5999 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 6000 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6001 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); 6002} 6003 6004static inline void bnx2x__common_init_phy(struct bnx2x *bp) 6005{ 6006 u32 shmem_base[2], shmem2_base[2]; 6007 shmem_base[0] = bp->common.shmem_base; 6008 shmem2_base[0] = bp->common.shmem2_base; 6009 if (!CHIP_IS_E1x(bp)) { 6010 shmem_base[1] = 6011 SHMEM2_RD(bp, other_shmem_base_addr); 6012 shmem2_base[1] = 6013 SHMEM2_RD(bp, other_shmem2_base_addr); 6014 } 6015 bnx2x_acquire_phy_lock(bp); 6016 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, 6017 bp->common.chip_id); 6018 bnx2x_release_phy_lock(bp); 6019} 6020 6021/** 6022 * bnx2x_init_hw_common - initialize the HW at the COMMON phase. 6023 * 6024 * @bp: driver handle 6025 */ 6026static int bnx2x_init_hw_common(struct bnx2x *bp) 6027{ 6028 u32 val; 6029 6030 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp)); 6031 6032 /* 6033 * take the UNDI lock to protect undi_unload flow from accessing 6034 * registers while we're resetting the chip 6035 */ 6036 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6037 6038 bnx2x_reset_common(bp); 6039 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 6040 6041 val = 0xfffc; 6042 if (CHIP_IS_E3(bp)) { 6043 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 6044 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 6045 } 6046 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 6047 6048 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6049 6050 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 6051 6052 if (!CHIP_IS_E1x(bp)) { 6053 u8 abs_func_id; 6054 6055 /** 6056 * 4-port mode or 2-port mode we need to turn of master-enable 6057 * for everyone, after that, turn it back on for self. 6058 * so, we disregard multi-function or not, and always disable 6059 * for all functions on the given path, this means 0,2,4,6 for 6060 * path 0 and 1,3,5,7 for path 1 6061 */ 6062 for (abs_func_id = BP_PATH(bp); 6063 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { 6064 if (abs_func_id == BP_ABS_FUNC(bp)) { 6065 REG_WR(bp, 6066 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 6067 1); 6068 continue; 6069 } 6070 6071 bnx2x_pretend_func(bp, abs_func_id); 6072 /* clear pf enable */ 6073 bnx2x_pf_disable(bp); 6074 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6075 } 6076 } 6077 6078 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); 6079 if (CHIP_IS_E1(bp)) { 6080 /* enable HW interrupt from PXP on USDM overflow 6081 bit 16 on INT_MASK_0 */ 6082 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 6083 } 6084 6085 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); 6086 bnx2x_init_pxp(bp); 6087 6088#ifdef __BIG_ENDIAN 6089 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); 6090 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); 6091 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 6092 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 6093 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 6094 /* make sure this value is 0 */ 6095 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); 6096 6097/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ 6098 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); 6099 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); 6100 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); 6101 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 6102#endif 6103 6104 bnx2x_ilt_init_page_size(bp, INITOP_SET); 6105 6106 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 6107 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 6108 6109 /* let the HW do it's magic ... */ 6110 msleep(100); 6111 /* finish PXP init */ 6112 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); 6113 if (val != 1) { 6114 BNX2X_ERR("PXP2 CFG failed\n"); 6115 return -EBUSY; 6116 } 6117 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); 6118 if (val != 1) { 6119 BNX2X_ERR("PXP2 RD_INIT failed\n"); 6120 return -EBUSY; 6121 } 6122 6123 /* Timers bug workaround E2 only. We need to set the entire ILT to 6124 * have entries with value "0" and valid bit on. 6125 * This needs to be done by the first PF that is loaded in a path 6126 * (i.e. common phase) 6127 */ 6128 if (!CHIP_IS_E1x(bp)) { 6129/* In E2 there is a bug in the timers block that can cause function 6 / 7 6130 * (i.e. vnic3) to start even if it is marked as "scan-off". 6131 * This occurs when a different function (func2,3) is being marked 6132 * as "scan-off". Real-life scenario for example: if a driver is being 6133 * load-unloaded while func6,7 are down. This will cause the timer to access 6134 * the ilt, translate to a logical address and send a request to read/write. 6135 * Since the ilt for the function that is down is not valid, this will cause 6136 * a translation error which is unrecoverable. 6137 * The Workaround is intended to make sure that when this happens nothing fatal 6138 * will occur. The workaround: 6139 * 1. First PF driver which loads on a path will: 6140 * a. After taking the chip out of reset, by using pretend, 6141 * it will write "0" to the following registers of 6142 * the other vnics. 6143 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6144 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 6145 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 6146 * And for itself it will write '1' to 6147 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 6148 * dmae-operations (writing to pram for example.) 6149 * note: can be done for only function 6,7 but cleaner this 6150 * way. 6151 * b. Write zero+valid to the entire ILT. 6152 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 6153 * VNIC3 (of that port). The range allocated will be the 6154 * entire ILT. This is needed to prevent ILT range error. 6155 * 2. Any PF driver load flow: 6156 * a. ILT update with the physical addresses of the allocated 6157 * logical pages. 6158 * b. Wait 20msec. - note that this timeout is needed to make 6159 * sure there are no requests in one of the PXP internal 6160 * queues with "old" ILT addresses. 6161 * c. PF enable in the PGLC. 6162 * d. Clear the was_error of the PF in the PGLC. (could have 6163 * occured while driver was down) 6164 * e. PF enable in the CFC (WEAK + STRONG) 6165 * f. Timers scan enable 6166 * 3. PF driver unload flow: 6167 * a. Clear the Timers scan_en. 6168 * b. Polling for scan_on=0 for that PF. 6169 * c. Clear the PF enable bit in the PXP. 6170 * d. Clear the PF enable in the CFC (WEAK + STRONG) 6171 * e. Write zero+valid to all ILT entries (The valid bit must 6172 * stay set) 6173 * f. If this is VNIC 3 of a port then also init 6174 * first_timers_ilt_entry to zero and last_timers_ilt_entry 6175 * to the last enrty in the ILT. 6176 * 6177 * Notes: 6178 * Currently the PF error in the PGLC is non recoverable. 6179 * In the future the there will be a recovery routine for this error. 6180 * Currently attention is masked. 6181 * Having an MCP lock on the load/unload process does not guarantee that 6182 * there is no Timer disable during Func6/7 enable. This is because the 6183 * Timers scan is currently being cleared by the MCP on FLR. 6184 * Step 2.d can be done only for PF6/7 and the driver can also check if 6185 * there is error before clearing it. But the flow above is simpler and 6186 * more general. 6187 * All ILT entries are written by zero+valid and not just PF6/7 6188 * ILT entries since in the future the ILT entries allocation for 6189 * PF-s might be dynamic. 6190 */ 6191 struct ilt_client_info ilt_cli; 6192 struct bnx2x_ilt ilt; 6193 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 6194 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); 6195 6196 /* initialize dummy TM client */ 6197 ilt_cli.start = 0; 6198 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 6199 ilt_cli.client_num = ILT_CLIENT_TM; 6200 6201 /* Step 1: set zeroes to all ilt page entries with valid bit on 6202 * Step 2: set the timers first/last ilt entry to point 6203 * to the entire range to prevent ILT range error for 3rd/4th 6204 * vnic (this code assumes existance of the vnic) 6205 * 6206 * both steps performed by call to bnx2x_ilt_client_init_op() 6207 * with dummy TM client 6208 * 6209 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 6210 * and his brother are split registers 6211 */ 6212 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); 6213 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); 6214 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6215 6216 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); 6217 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); 6218 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 6219 } 6220 6221 6222 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 6223 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 6224 6225 if (!CHIP_IS_E1x(bp)) { 6226 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : 6227 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); 6228 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); 6229 6230 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); 6231 6232 /* let the HW do it's magic ... */ 6233 do { 6234 msleep(200); 6235 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); 6236 } while (factor-- && (val != 1)); 6237 6238 if (val != 1) { 6239 BNX2X_ERR("ATC_INIT failed\n"); 6240 return -EBUSY; 6241 } 6242 } 6243 6244 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); 6245 6246 /* clean the DMAE memory */ 6247 bp->dmae_ready = 1; 6248 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); 6249 6250 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); 6251 6252 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); 6253 6254 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); 6255 6256 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); 6257 6258 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); 6259 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); 6260 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); 6261 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); 6262 6263 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); 6264 6265 6266 /* QM queues pointers table */ 6267 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); 6268 6269 /* soft reset pulse */ 6270 REG_WR(bp, QM_REG_SOFT_RESET, 1); 6271 REG_WR(bp, QM_REG_SOFT_RESET, 0); 6272 6273#ifdef BCM_CNIC 6274 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); 6275#endif 6276 6277 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); 6278 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); 6279 if (!CHIP_REV_IS_SLOW(bp)) 6280 /* enable hw interrupt from doorbell Q */ 6281 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6282 6283 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6284 6285 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6286 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 6287 6288 if (!CHIP_IS_E1(bp)) 6289 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); 6290 6291 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) 6292 /* Bit-map indicating which L2 hdrs may appear 6293 * after the basic Ethernet header 6294 */ 6295 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 6296 bp->path_has_ovlan ? 7 : 6); 6297 6298 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); 6299 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); 6300 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); 6301 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); 6302 6303 if (!CHIP_IS_E1x(bp)) { 6304 /* reset VFC memories */ 6305 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6306 VFC_MEMORIES_RST_REG_CAM_RST | 6307 VFC_MEMORIES_RST_REG_RAM_RST); 6308 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6309 VFC_MEMORIES_RST_REG_CAM_RST | 6310 VFC_MEMORIES_RST_REG_RAM_RST); 6311 6312 msleep(20); 6313 } 6314 6315 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); 6316 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); 6317 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); 6318 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); 6319 6320 /* sync semi rtc */ 6321 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6322 0x80000000); 6323 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 6324 0x80000000); 6325 6326 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); 6327 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); 6328 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); 6329 6330 if (!CHIP_IS_E1x(bp)) 6331 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 6332 bp->path_has_ovlan ? 7 : 6); 6333 6334 REG_WR(bp, SRC_REG_SOFT_RST, 1); 6335 6336 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); 6337 6338#ifdef BCM_CNIC 6339 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 6340 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 6341 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); 6342 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); 6343 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); 6344 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 6345 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); 6346 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 6347 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); 6348 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); 6349#endif 6350 REG_WR(bp, SRC_REG_SOFT_RST, 0); 6351 6352 if (sizeof(union cdu_context) != 1024) 6353 /* we currently assume that a context is 1024 bytes */ 6354 dev_alert(&bp->pdev->dev, "please adjust the size " 6355 "of cdu_context(%ld)\n", 6356 (long)sizeof(union cdu_context)); 6357 6358 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 6359 val = (4 << 24) + (0 << 12) + 1024; 6360 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); 6361 6362 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); 6363 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); 6364 /* enable context validation interrupt from CFC */ 6365 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6366 6367 /* set the thresholds to prevent CFC/CDU race */ 6368 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 6369 6370 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); 6371 6372 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) 6373 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); 6374 6375 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); 6376 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); 6377 6378 /* Reset PCIE errors for debug */ 6379 REG_WR(bp, 0x2814, 0xffffffff); 6380 REG_WR(bp, 0x3820, 0xffffffff); 6381 6382 if (!CHIP_IS_E1x(bp)) { 6383 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 6384 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 6385 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 6386 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 6387 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 6388 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 6389 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 6390 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 6391 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 6392 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 6393 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 6394 } 6395 6396 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); 6397 if (!CHIP_IS_E1(bp)) { 6398 /* in E3 this done in per-port section */ 6399 if (!CHIP_IS_E3(bp)) 6400 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6401 } 6402 if (CHIP_IS_E1H(bp)) 6403 /* not applicable for E2 (and above ...) */ 6404 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); 6405 6406 if (CHIP_REV_IS_SLOW(bp)) 6407 msleep(200); 6408 6409 /* finish CFC init */ 6410 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); 6411 if (val != 1) { 6412 BNX2X_ERR("CFC LL_INIT failed\n"); 6413 return -EBUSY; 6414 } 6415 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); 6416 if (val != 1) { 6417 BNX2X_ERR("CFC AC_INIT failed\n"); 6418 return -EBUSY; 6419 } 6420 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 6421 if (val != 1) { 6422 BNX2X_ERR("CFC CAM_INIT failed\n"); 6423 return -EBUSY; 6424 } 6425 REG_WR(bp, CFC_REG_DEBUG0, 0); 6426 6427 if (CHIP_IS_E1(bp)) { 6428 /* read NIG statistic 6429 to see if this is our first up since powerup */ 6430 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6431 val = *bnx2x_sp(bp, wb_data[0]); 6432 6433 /* do internal memory self test */ 6434 if ((val == 0) && bnx2x_int_mem_test(bp)) { 6435 BNX2X_ERR("internal mem self test failed\n"); 6436 return -EBUSY; 6437 } 6438 } 6439 6440 bnx2x_setup_fan_failure_detection(bp); 6441 6442 /* clear PXP2 attentions */ 6443 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 6444 6445 bnx2x_enable_blocks_attention(bp); 6446 bnx2x_enable_blocks_parity(bp); 6447 6448 if (!BP_NOMCP(bp)) { 6449 if (CHIP_IS_E1x(bp)) 6450 bnx2x__common_init_phy(bp); 6451 } else 6452 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 6453 6454 return 0; 6455} 6456 6457/** 6458 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. 6459 * 6460 * @bp: driver handle 6461 */ 6462static int bnx2x_init_hw_common_chip(struct bnx2x *bp) 6463{ 6464 int rc = bnx2x_init_hw_common(bp); 6465 6466 if (rc) 6467 return rc; 6468 6469 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 6470 if (!BP_NOMCP(bp)) 6471 bnx2x__common_init_phy(bp); 6472 6473 return 0; 6474} 6475 6476static int bnx2x_init_hw_port(struct bnx2x *bp) 6477{ 6478 int port = BP_PORT(bp); 6479 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 6480 u32 low, high; 6481 u32 val; 6482 6483 bnx2x__link_reset(bp); 6484 6485 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port); 6486 6487 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 6488 6489 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6490 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6491 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6492 6493 /* Timers bug workaround: disables the pf_master bit in pglue at 6494 * common phase, we need to enable it here before any dmae access are 6495 * attempted. Therefore we manually added the enable-master to the 6496 * port phase (it also happens in the function phase) 6497 */ 6498 if (!CHIP_IS_E1x(bp)) 6499 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6500 6501 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6502 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6503 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6504 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6505 6506 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6507 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6508 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6509 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6510 6511 /* QM cid (connection) count */ 6512 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); 6513 6514#ifdef BCM_CNIC 6515 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6516 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 6517 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 6518#endif 6519 6520 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6521 6522 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { 6523 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6524 6525 if (IS_MF(bp)) 6526 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 6527 else if (bp->dev->mtu > 4096) { 6528 if (bp->flags & ONE_PORT_FLAG) 6529 low = 160; 6530 else { 6531 val = bp->dev->mtu; 6532 /* (24*1024 + val*4)/256 */ 6533 low = 96 + (val/64) + 6534 ((val % 64) ? 1 : 0); 6535 } 6536 } else 6537 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 6538 high = low + 56; /* 14*1024/256 */ 6539 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 6540 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 6541 } 6542 6543 if (CHIP_MODE_IS_4_PORT(bp)) 6544 REG_WR(bp, (BP_PORT(bp) ? 6545 BRB1_REG_MAC_GUARANTIED_1 : 6546 BRB1_REG_MAC_GUARANTIED_0), 40); 6547 6548 6549 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6550 if (CHIP_IS_E3B0(bp)) 6551 /* Ovlan exists only if we are in multi-function + 6552 * switch-dependent mode, in switch-independent there 6553 * is no ovlan headers 6554 */ 6555 REG_WR(bp, BP_PORT(bp) ? 6556 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 6557 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 6558 (bp->path_has_ovlan ? 7 : 6)); 6559 6560 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6561 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6562 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6563 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6564 6565 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6566 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6567 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6568 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6569 6570 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6571 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6572 6573 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6574 6575 if (CHIP_IS_E1x(bp)) { 6576 /* configure PBF to work without PAUSE mtu 9000 */ 6577 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 6578 6579 /* update threshold */ 6580 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 6581 /* update init credit */ 6582 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 6583 6584 /* probe changes */ 6585 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 6586 udelay(50); 6587 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 6588 } 6589 6590#ifdef BCM_CNIC 6591 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6592#endif 6593 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6594 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6595 6596 if (CHIP_IS_E1(bp)) { 6597 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6598 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6599 } 6600 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6601 6602 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6603 6604 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6605 /* init aeu_mask_attn_func_0/1: 6606 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 6607 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 6608 * bits 4-7 are used for "per vn group attention" */ 6609 val = IS_MF(bp) ? 0xF7 : 0x7; 6610 /* Enable DCBX attention for all but E1 */ 6611 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 6612 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 6613 6614 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6615 6616 if (!CHIP_IS_E1x(bp)) { 6617 /* Bit-map indicating which L2 hdrs may appear after the 6618 * basic Ethernet header 6619 */ 6620 REG_WR(bp, BP_PORT(bp) ? 6621 NIG_REG_P1_HDRS_AFTER_BASIC : 6622 NIG_REG_P0_HDRS_AFTER_BASIC, 6623 IS_MF_SD(bp) ? 7 : 6); 6624 6625 if (CHIP_IS_E3(bp)) 6626 REG_WR(bp, BP_PORT(bp) ? 6627 NIG_REG_LLH1_MF_MODE : 6628 NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6629 } 6630 if (!CHIP_IS_E3(bp)) 6631 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 6632 6633 if (!CHIP_IS_E1(bp)) { 6634 /* 0x2 disable mf_ov, 0x1 enable */ 6635 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 6636 (IS_MF_SD(bp) ? 0x1 : 0x2)); 6637 6638 if (!CHIP_IS_E1x(bp)) { 6639 val = 0; 6640 switch (bp->mf_mode) { 6641 case MULTI_FUNCTION_SD: 6642 val = 1; 6643 break; 6644 case MULTI_FUNCTION_SI: 6645 val = 2; 6646 break; 6647 } 6648 6649 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : 6650 NIG_REG_LLH0_CLS_TYPE), val); 6651 } 6652 { 6653 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 6654 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 6655 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 6656 } 6657 } 6658 6659 6660 /* If SPIO5 is set to generate interrupts, enable it for this port */ 6661 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6662 if (val & (1 << MISC_REGISTERS_SPIO_5)) { 6663 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 6664 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 6665 val = REG_RD(bp, reg_addr); 6666 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 6667 REG_WR(bp, reg_addr, val); 6668 } 6669 6670 return 0; 6671} 6672 6673static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 6674{ 6675 int reg; 6676 6677 if (CHIP_IS_E1(bp)) 6678 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 6679 else 6680 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 6681 6682 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr)); 6683} 6684 6685static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) 6686{ 6687 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); 6688} 6689 6690static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) 6691{ 6692 u32 i, base = FUNC_ILT_BASE(func); 6693 for (i = base; i < base + ILT_PER_FUNC; i++) 6694 bnx2x_ilt_wr(bp, i, 0); 6695} 6696 6697static int bnx2x_init_hw_func(struct bnx2x *bp) 6698{ 6699 int port = BP_PORT(bp); 6700 int func = BP_FUNC(bp); 6701 int init_phase = PHASE_PF0 + func; 6702 struct bnx2x_ilt *ilt = BP_ILT(bp); 6703 u16 cdu_ilt_start; 6704 u32 addr, val; 6705 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 6706 int i, main_mem_width, rc; 6707 6708 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func); 6709 6710 /* FLR cleanup - hmmm */ 6711 if (!CHIP_IS_E1x(bp)) { 6712 rc = bnx2x_pf_flr_clnup(bp); 6713 if (rc) 6714 return rc; 6715 } 6716 6717 /* set MSI reconfigure capability */ 6718 if (bp->common.int_block == INT_BLOCK_HC) { 6719 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 6720 val = REG_RD(bp, addr); 6721 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 6722 REG_WR(bp, addr, val); 6723 } 6724 6725 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6726 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6727 6728 ilt = BP_ILT(bp); 6729 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 6730 6731 for (i = 0; i < L2_ILT_LINES(bp); i++) { 6732 ilt->lines[cdu_ilt_start + i].page = 6733 bp->context.vcxt + (ILT_PAGE_CIDS * i); 6734 ilt->lines[cdu_ilt_start + i].page_mapping = 6735 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i); 6736 /* cdu ilt pages are allocated manually so there's no need to 6737 set the size */ 6738 } 6739 bnx2x_ilt_init_op(bp, INITOP_SET); 6740 6741#ifdef BCM_CNIC 6742 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); 6743 6744 /* T1 hash bits value determines the T1 number of entries */ 6745 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 6746#endif 6747 6748#ifndef BCM_CNIC 6749 /* set NIC mode */ 6750 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6751#endif /* BCM_CNIC */ 6752 6753 if (!CHIP_IS_E1x(bp)) { 6754 u32 pf_conf = IGU_PF_CONF_FUNC_EN; 6755 6756 /* Turn on a single ISR mode in IGU if driver is going to use 6757 * INT#x or MSI 6758 */ 6759 if (!(bp->flags & USING_MSIX_FLAG)) 6760 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 6761 /* 6762 * Timers workaround bug: function init part. 6763 * Need to wait 20msec after initializing ILT, 6764 * needed to make sure there are no requests in 6765 * one of the PXP internal queues with "old" ILT addresses 6766 */ 6767 msleep(20); 6768 /* 6769 * Master enable - Due to WB DMAE writes performed before this 6770 * register is re-initialized as part of the regular function 6771 * init 6772 */ 6773 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6774 /* Enable the function in IGU */ 6775 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); 6776 } 6777 6778 bp->dmae_ready = 1; 6779 6780 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6781 6782 if (!CHIP_IS_E1x(bp)) 6783 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); 6784 6785 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6786 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6787 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6788 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6789 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6790 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6791 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6792 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6793 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6794 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6795 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6796 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6797 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6798 6799 if (!CHIP_IS_E1x(bp)) 6800 REG_WR(bp, QM_REG_PF_EN, 1); 6801 6802 if (!CHIP_IS_E1x(bp)) { 6803 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6804 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6805 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6806 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6807 } 6808 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6809 6810 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6811 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6812 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6813 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6814 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6815 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6816 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6817 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6818 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6819 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6820 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6821 if (!CHIP_IS_E1x(bp)) 6822 REG_WR(bp, PBF_REG_DISABLE_PF, 0); 6823 6824 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6825 6826 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6827 6828 if (!CHIP_IS_E1x(bp)) 6829 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); 6830 6831 if (IS_MF(bp)) { 6832 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 6833 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); 6834 } 6835 6836 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6837 6838 /* HC init per function */ 6839 if (bp->common.int_block == INT_BLOCK_HC) { 6840 if (CHIP_IS_E1H(bp)) { 6841 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6842 6843 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6844 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6845 } 6846 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6847 6848 } else { 6849 int num_segs, sb_idx, prod_offset; 6850 6851 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6852 6853 if (!CHIP_IS_E1x(bp)) { 6854 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 6855 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 6856 } 6857 6858 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6859 6860 if (!CHIP_IS_E1x(bp)) { 6861 int dsb_idx = 0; 6862 /** 6863 * Producer memory: 6864 * E2 mode: address 0-135 match to the mapping memory; 6865 * 136 - PF0 default prod; 137 - PF1 default prod; 6866 * 138 - PF2 default prod; 139 - PF3 default prod; 6867 * 140 - PF0 attn prod; 141 - PF1 attn prod; 6868 * 142 - PF2 attn prod; 143 - PF3 attn prod; 6869 * 144-147 reserved. 6870 * 6871 * E1.5 mode - In backward compatible mode; 6872 * for non default SB; each even line in the memory 6873 * holds the U producer and each odd line hold 6874 * the C producer. The first 128 producers are for 6875 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 6876 * producers are for the DSB for each PF. 6877 * Each PF has five segments: (the order inside each 6878 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 6879 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 6880 * 144-147 attn prods; 6881 */ 6882 /* non-default-status-blocks */ 6883 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6884 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 6885 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { 6886 prod_offset = (bp->igu_base_sb + sb_idx) * 6887 num_segs; 6888 6889 for (i = 0; i < num_segs; i++) { 6890 addr = IGU_REG_PROD_CONS_MEMORY + 6891 (prod_offset + i) * 4; 6892 REG_WR(bp, addr, 0); 6893 } 6894 /* send consumer update with value 0 */ 6895 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, 6896 USTORM_ID, 0, IGU_INT_NOP, 1); 6897 bnx2x_igu_clear_sb(bp, 6898 bp->igu_base_sb + sb_idx); 6899 } 6900 6901 /* default-status-blocks */ 6902 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6903 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 6904 6905 if (CHIP_MODE_IS_4_PORT(bp)) 6906 dsb_idx = BP_FUNC(bp); 6907 else 6908 dsb_idx = BP_VN(bp); 6909 6910 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 6911 IGU_BC_BASE_DSB_PROD + dsb_idx : 6912 IGU_NORM_BASE_DSB_PROD + dsb_idx); 6913 6914 /* 6915 * igu prods come in chunks of E1HVN_MAX (4) - 6916 * does not matters what is the current chip mode 6917 */ 6918 for (i = 0; i < (num_segs * E1HVN_MAX); 6919 i += E1HVN_MAX) { 6920 addr = IGU_REG_PROD_CONS_MEMORY + 6921 (prod_offset + i)*4; 6922 REG_WR(bp, addr, 0); 6923 } 6924 /* send consumer update with 0 */ 6925 if (CHIP_INT_MODE_IS_BC(bp)) { 6926 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6927 USTORM_ID, 0, IGU_INT_NOP, 1); 6928 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6929 CSTORM_ID, 0, IGU_INT_NOP, 1); 6930 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6931 XSTORM_ID, 0, IGU_INT_NOP, 1); 6932 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6933 TSTORM_ID, 0, IGU_INT_NOP, 1); 6934 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6935 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6936 } else { 6937 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6938 USTORM_ID, 0, IGU_INT_NOP, 1); 6939 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6940 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6941 } 6942 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); 6943 6944 /* !!! these should become driver const once 6945 rf-tool supports split-68 const */ 6946 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 6947 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 6948 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 6949 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 6950 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 6951 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 6952 } 6953 } 6954 6955 /* Reset PCIE errors for debug */ 6956 REG_WR(bp, 0x2114, 0xffffffff); 6957 REG_WR(bp, 0x2120, 0xffffffff); 6958 6959 if (CHIP_IS_E1x(bp)) { 6960 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 6961 main_mem_base = HC_REG_MAIN_MEMORY + 6962 BP_PORT(bp) * (main_mem_size * 4); 6963 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 6964 main_mem_width = 8; 6965 6966 val = REG_RD(bp, main_mem_prty_clr); 6967 if (val) 6968 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC " 6969 "block during " 6970 "function init (0x%x)!\n", val); 6971 6972 /* Clear "false" parity errors in MSI-X table */ 6973 for (i = main_mem_base; 6974 i < main_mem_base + main_mem_size * 4; 6975 i += main_mem_width) { 6976 bnx2x_read_dmae(bp, i, main_mem_width / 4); 6977 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), 6978 i, main_mem_width / 4); 6979 } 6980 /* Clear HC parity attention */ 6981 REG_RD(bp, main_mem_prty_clr); 6982 } 6983 6984#ifdef BNX2X_STOP_ON_ERROR 6985 /* Enable STORMs SP logging */ 6986 REG_WR8(bp, BAR_USTRORM_INTMEM + 6987 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6988 REG_WR8(bp, BAR_TSTRORM_INTMEM + 6989 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6990 REG_WR8(bp, BAR_CSTRORM_INTMEM + 6991 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6992 REG_WR8(bp, BAR_XSTRORM_INTMEM + 6993 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6994#endif 6995 6996 bnx2x_phy_probe(&bp->link_params); 6997 6998 return 0; 6999} 7000 7001 7002void bnx2x_free_mem(struct bnx2x *bp) 7003{ 7004 /* fastpath */ 7005 bnx2x_free_fp_mem(bp); 7006 /* end of fastpath */ 7007 7008 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 7009 sizeof(struct host_sp_status_block)); 7010 7011 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 7012 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7013 7014 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 7015 sizeof(struct bnx2x_slowpath)); 7016 7017 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping, 7018 bp->context.size); 7019 7020 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); 7021 7022 BNX2X_FREE(bp->ilt->lines); 7023 7024#ifdef BCM_CNIC 7025 if (!CHIP_IS_E1x(bp)) 7026 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, 7027 sizeof(struct host_hc_status_block_e2)); 7028 else 7029 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, 7030 sizeof(struct host_hc_status_block_e1x)); 7031 7032 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 7033#endif 7034 7035 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 7036 7037 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, 7038 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7039} 7040 7041static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) 7042{ 7043 int num_groups; 7044 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1; 7045 7046 /* number of queues for statistics is number of eth queues + FCoE */ 7047 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats; 7048 7049 /* Total number of FW statistics requests = 7050 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats + 7051 * num of queues 7052 */ 7053 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats; 7054 7055 7056 /* Request is built from stats_query_header and an array of 7057 * stats_query_cmd_group each of which contains 7058 * STATS_QUERY_CMD_COUNT rules. The real number or requests is 7059 * configured in the stats_query_header. 7060 */ 7061 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) + 7062 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0); 7063 7064 bp->fw_stats_req_sz = sizeof(struct stats_query_header) + 7065 num_groups * sizeof(struct stats_query_cmd_group); 7066 7067 /* Data for statistics requests + stats_conter 7068 * 7069 * stats_counter holds per-STORM counters that are incremented 7070 * when STORM has finished with the current request. 7071 * 7072 * memory for FCoE offloaded statistics are counted anyway, 7073 * even if they will not be sent. 7074 */ 7075 bp->fw_stats_data_sz = sizeof(struct per_port_stats) + 7076 sizeof(struct per_pf_stats) + 7077 sizeof(struct fcoe_statistics_params) + 7078 sizeof(struct per_queue_stats) * num_queue_stats + 7079 sizeof(struct stats_counter); 7080 7081 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, 7082 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7083 7084 /* Set shortcuts */ 7085 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; 7086 bp->fw_stats_req_mapping = bp->fw_stats_mapping; 7087 7088 bp->fw_stats_data = (struct bnx2x_fw_stats_data *) 7089 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); 7090 7091 bp->fw_stats_data_mapping = bp->fw_stats_mapping + 7092 bp->fw_stats_req_sz; 7093 return 0; 7094 7095alloc_mem_err: 7096 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 7097 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7098 return -ENOMEM; 7099} 7100 7101 7102int bnx2x_alloc_mem(struct bnx2x *bp) 7103{ 7104#ifdef BCM_CNIC 7105 if (!CHIP_IS_E1x(bp)) 7106 /* size = the status block + ramrod buffers */ 7107 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, 7108 sizeof(struct host_hc_status_block_e2)); 7109 else 7110 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, 7111 sizeof(struct host_hc_status_block_e1x)); 7112 7113 /* allocate searcher T2 table */ 7114 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); 7115#endif 7116 7117 7118 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, 7119 sizeof(struct host_sp_status_block)); 7120 7121 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, 7122 sizeof(struct bnx2x_slowpath)); 7123 7124 /* Allocated memory for FW statistics */ 7125 if (bnx2x_alloc_fw_stats_mem(bp)) 7126 goto alloc_mem_err; 7127 7128 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); 7129 7130 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping, 7131 bp->context.size); 7132 7133 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); 7134 7135 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) 7136 goto alloc_mem_err; 7137 7138 /* Slow path ring */ 7139 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); 7140 7141 /* EQ */ 7142 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, 7143 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7144 7145 7146 /* fastpath */ 7147 /* need to be done at the end, since it's self adjusting to amount 7148 * of memory available for RSS queues 7149 */ 7150 if (bnx2x_alloc_fp_mem(bp)) 7151 goto alloc_mem_err; 7152 return 0; 7153 7154alloc_mem_err: 7155 bnx2x_free_mem(bp); 7156 return -ENOMEM; 7157} 7158 7159/* 7160 * Init service functions 7161 */ 7162 7163int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 7164 struct bnx2x_vlan_mac_obj *obj, bool set, 7165 int mac_type, unsigned long *ramrod_flags) 7166{ 7167 int rc; 7168 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 7169 7170 memset(&ramrod_param, 0, sizeof(ramrod_param)); 7171 7172 /* Fill general parameters */ 7173 ramrod_param.vlan_mac_obj = obj; 7174 ramrod_param.ramrod_flags = *ramrod_flags; 7175 7176 /* Fill a user request section if needed */ 7177 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 7178 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 7179 7180 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 7181 7182 /* Set the command: ADD or DEL */ 7183 if (set) 7184 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 7185 else 7186 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 7187 } 7188 7189 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 7190 if (rc < 0) 7191 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); 7192 return rc; 7193} 7194 7195int bnx2x_del_all_macs(struct bnx2x *bp, 7196 struct bnx2x_vlan_mac_obj *mac_obj, 7197 int mac_type, bool wait_for_comp) 7198{ 7199 int rc; 7200 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 7201 7202 /* Wait for completion of requested */ 7203 if (wait_for_comp) 7204 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7205 7206 /* Set the mac type of addresses we want to clear */ 7207 __set_bit(mac_type, &vlan_mac_flags); 7208 7209 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); 7210 if (rc < 0) 7211 BNX2X_ERR("Failed to delete MACs: %d\n", rc); 7212 7213 return rc; 7214} 7215 7216int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) 7217{ 7218 unsigned long ramrod_flags = 0; 7219 7220#ifdef BCM_CNIC 7221 if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_ISCSI_SD(bp)) { 7222 DP(NETIF_MSG_IFUP, "Ignoring Zero MAC for iSCSI SD mode\n"); 7223 return 0; 7224 } 7225#endif 7226 7227 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); 7228 7229 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7230 /* Eth MAC is set on RSS leading client (fp[0]) */ 7231 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set, 7232 BNX2X_ETH_MAC, &ramrod_flags); 7233} 7234 7235int bnx2x_setup_leading(struct bnx2x *bp) 7236{ 7237 return bnx2x_setup_queue(bp, &bp->fp[0], 1); 7238} 7239 7240/** 7241 * bnx2x_set_int_mode - configure interrupt mode 7242 * 7243 * @bp: driver handle 7244 * 7245 * In case of MSI-X it will also try to enable MSI-X. 7246 */ 7247static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) 7248{ 7249 switch (int_mode) { 7250 case INT_MODE_MSI: 7251 bnx2x_enable_msi(bp); 7252 /* falling through... */ 7253 case INT_MODE_INTx: 7254 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7255 DP(NETIF_MSG_IFUP, "set number of queues to 1\n"); 7256 break; 7257 default: 7258 /* Set number of queues according to bp->multi_mode value */ 7259 bnx2x_set_num_queues(bp); 7260 7261 DP(NETIF_MSG_IFUP, "set number of queues to %d\n", 7262 bp->num_queues); 7263 7264 /* if we can't use MSI-X we only need one fp, 7265 * so try to enable MSI-X with the requested number of fp's 7266 * and fallback to MSI or legacy INTx with one fp 7267 */ 7268 if (bnx2x_enable_msix(bp)) { 7269 /* failed to enable MSI-X */ 7270 if (bp->multi_mode) 7271 DP(NETIF_MSG_IFUP, 7272 "Multi requested but failed to " 7273 "enable MSI-X (%d), " 7274 "set number of queues to %d\n", 7275 bp->num_queues, 7276 1 + NON_ETH_CONTEXT_USE); 7277 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7278 7279 /* Try to enable MSI */ 7280 if (!(bp->flags & DISABLE_MSI_FLAG)) 7281 bnx2x_enable_msi(bp); 7282 } 7283 break; 7284 } 7285} 7286 7287/* must be called prioir to any HW initializations */ 7288static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) 7289{ 7290 return L2_ILT_LINES(bp); 7291} 7292 7293void bnx2x_ilt_set_info(struct bnx2x *bp) 7294{ 7295 struct ilt_client_info *ilt_client; 7296 struct bnx2x_ilt *ilt = BP_ILT(bp); 7297 u16 line = 0; 7298 7299 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); 7300 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); 7301 7302 /* CDU */ 7303 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 7304 ilt_client->client_num = ILT_CLIENT_CDU; 7305 ilt_client->page_size = CDU_ILT_PAGE_SZ; 7306 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 7307 ilt_client->start = line; 7308 line += bnx2x_cid_ilt_lines(bp); 7309#ifdef BCM_CNIC 7310 line += CNIC_ILT_LINES; 7311#endif 7312 ilt_client->end = line - 1; 7313 7314 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, " 7315 "flags 0x%x, hw psz %d\n", 7316 ilt_client->start, 7317 ilt_client->end, 7318 ilt_client->page_size, 7319 ilt_client->flags, 7320 ilog2(ilt_client->page_size >> 12)); 7321 7322 /* QM */ 7323 if (QM_INIT(bp->qm_cid_count)) { 7324 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 7325 ilt_client->client_num = ILT_CLIENT_QM; 7326 ilt_client->page_size = QM_ILT_PAGE_SZ; 7327 ilt_client->flags = 0; 7328 ilt_client->start = line; 7329 7330 /* 4 bytes for each cid */ 7331 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 7332 QM_ILT_PAGE_SZ); 7333 7334 ilt_client->end = line - 1; 7335 7336 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, " 7337 "flags 0x%x, hw psz %d\n", 7338 ilt_client->start, 7339 ilt_client->end, 7340 ilt_client->page_size, 7341 ilt_client->flags, 7342 ilog2(ilt_client->page_size >> 12)); 7343 7344 } 7345 /* SRC */ 7346 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 7347#ifdef BCM_CNIC 7348 ilt_client->client_num = ILT_CLIENT_SRC; 7349 ilt_client->page_size = SRC_ILT_PAGE_SZ; 7350 ilt_client->flags = 0; 7351 ilt_client->start = line; 7352 line += SRC_ILT_LINES; 7353 ilt_client->end = line - 1; 7354 7355 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, " 7356 "flags 0x%x, hw psz %d\n", 7357 ilt_client->start, 7358 ilt_client->end, 7359 ilt_client->page_size, 7360 ilt_client->flags, 7361 ilog2(ilt_client->page_size >> 12)); 7362 7363#else 7364 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7365#endif 7366 7367 /* TM */ 7368 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 7369#ifdef BCM_CNIC 7370 ilt_client->client_num = ILT_CLIENT_TM; 7371 ilt_client->page_size = TM_ILT_PAGE_SZ; 7372 ilt_client->flags = 0; 7373 ilt_client->start = line; 7374 line += TM_ILT_LINES; 7375 ilt_client->end = line - 1; 7376 7377 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, " 7378 "flags 0x%x, hw psz %d\n", 7379 ilt_client->start, 7380 ilt_client->end, 7381 ilt_client->page_size, 7382 ilt_client->flags, 7383 ilog2(ilt_client->page_size >> 12)); 7384 7385#else 7386 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7387#endif 7388 BUG_ON(line > ILT_MAX_LINES); 7389} 7390 7391/** 7392 * bnx2x_pf_q_prep_init - prepare INIT transition parameters 7393 * 7394 * @bp: driver handle 7395 * @fp: pointer to fastpath 7396 * @init_params: pointer to parameters structure 7397 * 7398 * parameters configured: 7399 * - HC configuration 7400 * - Queue's CDU context 7401 */ 7402static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp, 7403 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) 7404{ 7405 7406 u8 cos; 7407 /* FCoE Queue uses Default SB, thus has no HC capabilities */ 7408 if (!IS_FCOE_FP(fp)) { 7409 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); 7410 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); 7411 7412 /* If HC is supporterd, enable host coalescing in the transition 7413 * to INIT state. 7414 */ 7415 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); 7416 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); 7417 7418 /* HC rate */ 7419 init_params->rx.hc_rate = bp->rx_ticks ? 7420 (1000000 / bp->rx_ticks) : 0; 7421 init_params->tx.hc_rate = bp->tx_ticks ? 7422 (1000000 / bp->tx_ticks) : 0; 7423 7424 /* FW SB ID */ 7425 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = 7426 fp->fw_sb_id; 7427 7428 /* 7429 * CQ index among the SB indices: FCoE clients uses the default 7430 * SB, therefore it's different. 7431 */ 7432 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 7433 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 7434 } 7435 7436 /* set maximum number of COSs supported by this queue */ 7437 init_params->max_cos = fp->max_cos; 7438 7439 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n", 7440 fp->index, init_params->max_cos); 7441 7442 /* set the context pointers queue object */ 7443 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) 7444 init_params->cxts[cos] = 7445 &bp->context.vcxt[fp->txdata[cos].cid].eth; 7446} 7447 7448int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7449 struct bnx2x_queue_state_params *q_params, 7450 struct bnx2x_queue_setup_tx_only_params *tx_only_params, 7451 int tx_index, bool leading) 7452{ 7453 memset(tx_only_params, 0, sizeof(*tx_only_params)); 7454 7455 /* Set the command */ 7456 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 7457 7458 /* Set tx-only QUEUE flags: don't zero statistics */ 7459 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); 7460 7461 /* choose the index of the cid to send the slow path on */ 7462 tx_only_params->cid_index = tx_index; 7463 7464 /* Set general TX_ONLY_SETUP parameters */ 7465 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); 7466 7467 /* Set Tx TX_ONLY_SETUP parameters */ 7468 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 7469 7470 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:" 7471 "cos %d, primary cid %d, cid %d, " 7472 "client id %d, sp-client id %d, flags %lx\n", 7473 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 7474 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 7475 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 7476 7477 /* send the ramrod */ 7478 return bnx2x_queue_state_change(bp, q_params); 7479} 7480 7481 7482/** 7483 * bnx2x_setup_queue - setup queue 7484 * 7485 * @bp: driver handle 7486 * @fp: pointer to fastpath 7487 * @leading: is leading 7488 * 7489 * This function performs 2 steps in a Queue state machine 7490 * actually: 1) RESET->INIT 2) INIT->SETUP 7491 */ 7492 7493int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7494 bool leading) 7495{ 7496 struct bnx2x_queue_state_params q_params = {0}; 7497 struct bnx2x_queue_setup_params *setup_params = 7498 &q_params.params.setup; 7499 struct bnx2x_queue_setup_tx_only_params *tx_only_params = 7500 &q_params.params.tx_only; 7501 int rc; 7502 u8 tx_index; 7503 7504 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index); 7505 7506 /* reset IGU state skip FCoE L2 queue */ 7507 if (!IS_FCOE_FP(fp)) 7508 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, 7509 IGU_INT_ENABLE, 0); 7510 7511 q_params.q_obj = &fp->q_obj; 7512 /* We want to wait for completion in this context */ 7513 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7514 7515 /* Prepare the INIT parameters */ 7516 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); 7517 7518 /* Set the command */ 7519 q_params.cmd = BNX2X_Q_CMD_INIT; 7520 7521 /* Change the state to INIT */ 7522 rc = bnx2x_queue_state_change(bp, &q_params); 7523 if (rc) { 7524 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); 7525 return rc; 7526 } 7527 7528 DP(BNX2X_MSG_SP, "init complete\n"); 7529 7530 7531 /* Now move the Queue to the SETUP state... */ 7532 memset(setup_params, 0, sizeof(*setup_params)); 7533 7534 /* Set QUEUE flags */ 7535 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); 7536 7537 /* Set general SETUP parameters */ 7538 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, 7539 FIRST_TX_COS_INDEX); 7540 7541 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, 7542 &setup_params->rxq_params); 7543 7544 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, 7545 FIRST_TX_COS_INDEX); 7546 7547 /* Set the command */ 7548 q_params.cmd = BNX2X_Q_CMD_SETUP; 7549 7550 /* Change the state to SETUP */ 7551 rc = bnx2x_queue_state_change(bp, &q_params); 7552 if (rc) { 7553 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); 7554 return rc; 7555 } 7556 7557 /* loop through the relevant tx-only indices */ 7558 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7559 tx_index < fp->max_cos; 7560 tx_index++) { 7561 7562 /* prepare and send tx-only ramrod*/ 7563 rc = bnx2x_setup_tx_only(bp, fp, &q_params, 7564 tx_only_params, tx_index, leading); 7565 if (rc) { 7566 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", 7567 fp->index, tx_index); 7568 return rc; 7569 } 7570 } 7571 7572 return rc; 7573} 7574 7575static int bnx2x_stop_queue(struct bnx2x *bp, int index) 7576{ 7577 struct bnx2x_fastpath *fp = &bp->fp[index]; 7578 struct bnx2x_fp_txdata *txdata; 7579 struct bnx2x_queue_state_params q_params = {0}; 7580 int rc, tx_index; 7581 7582 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid); 7583 7584 q_params.q_obj = &fp->q_obj; 7585 /* We want to wait for completion in this context */ 7586 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7587 7588 7589 /* close tx-only connections */ 7590 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7591 tx_index < fp->max_cos; 7592 tx_index++){ 7593 7594 /* ascertain this is a normal queue*/ 7595 txdata = &fp->txdata[tx_index]; 7596 7597 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n", 7598 txdata->txq_index); 7599 7600 /* send halt terminate on tx-only connection */ 7601 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7602 memset(&q_params.params.terminate, 0, 7603 sizeof(q_params.params.terminate)); 7604 q_params.params.terminate.cid_index = tx_index; 7605 7606 rc = bnx2x_queue_state_change(bp, &q_params); 7607 if (rc) 7608 return rc; 7609 7610 /* send halt terminate on tx-only connection */ 7611 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7612 memset(&q_params.params.cfc_del, 0, 7613 sizeof(q_params.params.cfc_del)); 7614 q_params.params.cfc_del.cid_index = tx_index; 7615 rc = bnx2x_queue_state_change(bp, &q_params); 7616 if (rc) 7617 return rc; 7618 } 7619 /* Stop the primary connection: */ 7620 /* ...halt the connection */ 7621 q_params.cmd = BNX2X_Q_CMD_HALT; 7622 rc = bnx2x_queue_state_change(bp, &q_params); 7623 if (rc) 7624 return rc; 7625 7626 /* ...terminate the connection */ 7627 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7628 memset(&q_params.params.terminate, 0, 7629 sizeof(q_params.params.terminate)); 7630 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 7631 rc = bnx2x_queue_state_change(bp, &q_params); 7632 if (rc) 7633 return rc; 7634 /* ...delete cfc entry */ 7635 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7636 memset(&q_params.params.cfc_del, 0, 7637 sizeof(q_params.params.cfc_del)); 7638 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 7639 return bnx2x_queue_state_change(bp, &q_params); 7640} 7641 7642 7643static void bnx2x_reset_func(struct bnx2x *bp) 7644{ 7645 int port = BP_PORT(bp); 7646 int func = BP_FUNC(bp); 7647 int i; 7648 7649 /* Disable the function in the FW */ 7650 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 7651 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 7652 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 7653 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 7654 7655 /* FP SBs */ 7656 for_each_eth_queue(bp, i) { 7657 struct bnx2x_fastpath *fp = &bp->fp[i]; 7658 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7659 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 7660 SB_DISABLED); 7661 } 7662 7663#ifdef BCM_CNIC 7664 /* CNIC SB */ 7665 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7666 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), 7667 SB_DISABLED); 7668#endif 7669 /* SP SB */ 7670 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7671 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 7672 SB_DISABLED); 7673 7674 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) 7675 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 7676 0); 7677 7678 /* Configure IGU */ 7679 if (bp->common.int_block == INT_BLOCK_HC) { 7680 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7681 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7682 } else { 7683 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 7684 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 7685 } 7686 7687#ifdef BCM_CNIC 7688 /* Disable Timer scan */ 7689 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 7690 /* 7691 * Wait for at least 10ms and up to 2 second for the timers scan to 7692 * complete 7693 */ 7694 for (i = 0; i < 200; i++) { 7695 msleep(10); 7696 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) 7697 break; 7698 } 7699#endif 7700 /* Clear ILT */ 7701 bnx2x_clear_func_ilt(bp, func); 7702 7703 /* Timers workaround bug for E2: if this is vnic-3, 7704 * we need to set the entire ilt range for this timers. 7705 */ 7706 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { 7707 struct ilt_client_info ilt_cli; 7708 /* use dummy TM client */ 7709 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 7710 ilt_cli.start = 0; 7711 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 7712 ilt_cli.client_num = ILT_CLIENT_TM; 7713 7714 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); 7715 } 7716 7717 /* this assumes that reset_port() called before reset_func()*/ 7718 if (!CHIP_IS_E1x(bp)) 7719 bnx2x_pf_disable(bp); 7720 7721 bp->dmae_ready = 0; 7722} 7723 7724static void bnx2x_reset_port(struct bnx2x *bp) 7725{ 7726 int port = BP_PORT(bp); 7727 u32 val; 7728 7729 /* Reset physical Link */ 7730 bnx2x__link_reset(bp); 7731 7732 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 7733 7734 /* Do not rcv packets to BRB */ 7735 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 7736 /* Do not direct rcv packets that are not for MCP to the BRB */ 7737 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 7738 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 7739 7740 /* Configure AEU */ 7741 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 7742 7743 msleep(100); 7744 /* Check for BRB port occupancy */ 7745 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 7746 if (val) 7747 DP(NETIF_MSG_IFDOWN, 7748 "BRB1 is not empty %d blocks are occupied\n", val); 7749 7750 /* TODO: Close Doorbell port? */ 7751} 7752 7753static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) 7754{ 7755 struct bnx2x_func_state_params func_params = {0}; 7756 7757 /* Prepare parameters for function state transitions */ 7758 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7759 7760 func_params.f_obj = &bp->func_obj; 7761 func_params.cmd = BNX2X_F_CMD_HW_RESET; 7762 7763 func_params.params.hw_init.load_phase = load_code; 7764 7765 return bnx2x_func_state_change(bp, &func_params); 7766} 7767 7768static inline int bnx2x_func_stop(struct bnx2x *bp) 7769{ 7770 struct bnx2x_func_state_params func_params = {0}; 7771 int rc; 7772 7773 /* Prepare parameters for function state transitions */ 7774 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7775 func_params.f_obj = &bp->func_obj; 7776 func_params.cmd = BNX2X_F_CMD_STOP; 7777 7778 /* 7779 * Try to stop the function the 'good way'. If fails (in case 7780 * of a parity error during bnx2x_chip_cleanup()) and we are 7781 * not in a debug mode, perform a state transaction in order to 7782 * enable further HW_RESET transaction. 7783 */ 7784 rc = bnx2x_func_state_change(bp, &func_params); 7785 if (rc) { 7786#ifdef BNX2X_STOP_ON_ERROR 7787 return rc; 7788#else 7789 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry " 7790 "transaction\n"); 7791 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 7792 return bnx2x_func_state_change(bp, &func_params); 7793#endif 7794 } 7795 7796 return 0; 7797} 7798 7799/** 7800 * bnx2x_send_unload_req - request unload mode from the MCP. 7801 * 7802 * @bp: driver handle 7803 * @unload_mode: requested function's unload mode 7804 * 7805 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 7806 */ 7807u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 7808{ 7809 u32 reset_code = 0; 7810 int port = BP_PORT(bp); 7811 7812 /* Select the UNLOAD request mode */ 7813 if (unload_mode == UNLOAD_NORMAL) 7814 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7815 7816 else if (bp->flags & NO_WOL_FLAG) 7817 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 7818 7819 else if (bp->wol) { 7820 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 7821 u8 *mac_addr = bp->dev->dev_addr; 7822 u32 val; 7823 u16 pmc; 7824 7825 /* The mac address is written to entries 1-4 to 7826 * preserve entry 0 which is used by the PMF 7827 */ 7828 u8 entry = (BP_VN(bp) + 1)*8; 7829 7830 val = (mac_addr[0] << 8) | mac_addr[1]; 7831 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 7832 7833 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 7834 (mac_addr[4] << 8) | mac_addr[5]; 7835 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 7836 7837 /* Enable the PME and clear the status */ 7838 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); 7839 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; 7840 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); 7841 7842 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 7843 7844 } else 7845 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7846 7847 /* Send the request to the MCP */ 7848 if (!BP_NOMCP(bp)) 7849 reset_code = bnx2x_fw_command(bp, reset_code, 0); 7850 else { 7851 int path = BP_PATH(bp); 7852 7853 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] " 7854 "%d, %d, %d\n", 7855 path, load_count[path][0], load_count[path][1], 7856 load_count[path][2]); 7857 load_count[path][0]--; 7858 load_count[path][1 + port]--; 7859 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] " 7860 "%d, %d, %d\n", 7861 path, load_count[path][0], load_count[path][1], 7862 load_count[path][2]); 7863 if (load_count[path][0] == 0) 7864 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 7865 else if (load_count[path][1 + port] == 0) 7866 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 7867 else 7868 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 7869 } 7870 7871 return reset_code; 7872} 7873 7874/** 7875 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 7876 * 7877 * @bp: driver handle 7878 */ 7879void bnx2x_send_unload_done(struct bnx2x *bp) 7880{ 7881 /* Report UNLOAD_DONE to MCP */ 7882 if (!BP_NOMCP(bp)) 7883 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 7884} 7885 7886static inline int bnx2x_func_wait_started(struct bnx2x *bp) 7887{ 7888 int tout = 50; 7889 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 7890 7891 if (!bp->port.pmf) 7892 return 0; 7893 7894 /* 7895 * (assumption: No Attention from MCP at this stage) 7896 * PMF probably in the middle of TXdisable/enable transaction 7897 * 1. Sync IRS for default SB 7898 * 2. Sync SP queue - this guarantes us that attention handling started 7899 * 3. Wait, that TXdisable/enable transaction completes 7900 * 7901 * 1+2 guranty that if DCBx attention was scheduled it already changed 7902 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy 7903 * received complettion for the transaction the state is TX_STOPPED. 7904 * State will return to STARTED after completion of TX_STOPPED-->STARTED 7905 * transaction. 7906 */ 7907 7908 /* make sure default SB ISR is done */ 7909 if (msix) 7910 synchronize_irq(bp->msix_table[0].vector); 7911 else 7912 synchronize_irq(bp->pdev->irq); 7913 7914 flush_workqueue(bnx2x_wq); 7915 7916 while (bnx2x_func_get_state(bp, &bp->func_obj) != 7917 BNX2X_F_STATE_STARTED && tout--) 7918 msleep(20); 7919 7920 if (bnx2x_func_get_state(bp, &bp->func_obj) != 7921 BNX2X_F_STATE_STARTED) { 7922#ifdef BNX2X_STOP_ON_ERROR 7923 return -EBUSY; 7924#else 7925 /* 7926 * Failed to complete the transaction in a "good way" 7927 * Force both transactions with CLR bit 7928 */ 7929 struct bnx2x_func_state_params func_params = {0}; 7930 7931 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! " 7932 "Forcing STARTED-->TX_ST0PPED-->STARTED\n"); 7933 7934 func_params.f_obj = &bp->func_obj; 7935 __set_bit(RAMROD_DRV_CLR_ONLY, 7936 &func_params.ramrod_flags); 7937 7938 /* STARTED-->TX_ST0PPED */ 7939 func_params.cmd = BNX2X_F_CMD_TX_STOP; 7940 bnx2x_func_state_change(bp, &func_params); 7941 7942 /* TX_ST0PPED-->STARTED */ 7943 func_params.cmd = BNX2X_F_CMD_TX_START; 7944 return bnx2x_func_state_change(bp, &func_params); 7945#endif 7946 } 7947 7948 return 0; 7949} 7950 7951void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) 7952{ 7953 int port = BP_PORT(bp); 7954 int i, rc = 0; 7955 u8 cos; 7956 struct bnx2x_mcast_ramrod_params rparam = {0}; 7957 u32 reset_code; 7958 7959 /* Wait until tx fastpath tasks complete */ 7960 for_each_tx_queue(bp, i) { 7961 struct bnx2x_fastpath *fp = &bp->fp[i]; 7962 7963 for_each_cos_in_tx_queue(fp, cos) 7964 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]); 7965#ifdef BNX2X_STOP_ON_ERROR 7966 if (rc) 7967 return; 7968#endif 7969 } 7970 7971 /* Give HW time to discard old tx messages */ 7972 usleep_range(1000, 1000); 7973 7974 /* Clean all ETH MACs */ 7975 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false); 7976 if (rc < 0) 7977 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); 7978 7979 /* Clean up UC list */ 7980 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, 7981 true); 7982 if (rc < 0) 7983 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: " 7984 "%d\n", rc); 7985 7986 /* Disable LLH */ 7987 if (!CHIP_IS_E1(bp)) 7988 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 7989 7990 /* Set "drop all" (stop Rx). 7991 * We need to take a netif_addr_lock() here in order to prevent 7992 * a race between the completion code and this code. 7993 */ 7994 netif_addr_lock_bh(bp->dev); 7995 /* Schedule the rx_mode command */ 7996 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 7997 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 7998 else 7999 bnx2x_set_storm_rx_mode(bp); 8000 8001 /* Cleanup multicast configuration */ 8002 rparam.mcast_obj = &bp->mcast_obj; 8003 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 8004 if (rc < 0) 8005 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); 8006 8007 netif_addr_unlock_bh(bp->dev); 8008 8009 8010 8011 /* 8012 * Send the UNLOAD_REQUEST to the MCP. This will return if 8013 * this function should perform FUNC, PORT or COMMON HW 8014 * reset. 8015 */ 8016 reset_code = bnx2x_send_unload_req(bp, unload_mode); 8017 8018 /* 8019 * (assumption: No Attention from MCP at this stage) 8020 * PMF probably in the middle of TXdisable/enable transaction 8021 */ 8022 rc = bnx2x_func_wait_started(bp); 8023 if (rc) { 8024 BNX2X_ERR("bnx2x_func_wait_started failed\n"); 8025#ifdef BNX2X_STOP_ON_ERROR 8026 return; 8027#endif 8028 } 8029 8030 /* Close multi and leading connections 8031 * Completions for ramrods are collected in a synchronous way 8032 */ 8033 for_each_queue(bp, i) 8034 if (bnx2x_stop_queue(bp, i)) 8035#ifdef BNX2X_STOP_ON_ERROR 8036 return; 8037#else 8038 goto unload_error; 8039#endif 8040 /* If SP settings didn't get completed so far - something 8041 * very wrong has happen. 8042 */ 8043 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) 8044 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); 8045 8046#ifndef BNX2X_STOP_ON_ERROR 8047unload_error: 8048#endif 8049 rc = bnx2x_func_stop(bp); 8050 if (rc) { 8051 BNX2X_ERR("Function stop failed!\n"); 8052#ifdef BNX2X_STOP_ON_ERROR 8053 return; 8054#endif 8055 } 8056 8057 /* Disable HW interrupts, NAPI */ 8058 bnx2x_netif_stop(bp, 1); 8059 8060 /* Release IRQs */ 8061 bnx2x_free_irq(bp); 8062 8063 /* Reset the chip */ 8064 rc = bnx2x_reset_hw(bp, reset_code); 8065 if (rc) 8066 BNX2X_ERR("HW_RESET failed\n"); 8067 8068 8069 /* Report UNLOAD_DONE to MCP */ 8070 bnx2x_send_unload_done(bp); 8071} 8072 8073void bnx2x_disable_close_the_gate(struct bnx2x *bp) 8074{ 8075 u32 val; 8076 8077 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n"); 8078 8079 if (CHIP_IS_E1(bp)) { 8080 int port = BP_PORT(bp); 8081 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8082 MISC_REG_AEU_MASK_ATTN_FUNC_0; 8083 8084 val = REG_RD(bp, addr); 8085 val &= ~(0x300); 8086 REG_WR(bp, addr, val); 8087 } else { 8088 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); 8089 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 8090 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 8091 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); 8092 } 8093} 8094 8095/* Close gates #2, #3 and #4: */ 8096static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 8097{ 8098 u32 val; 8099 8100 /* Gates #2 and #4a are closed/opened for "not E1" only */ 8101 if (!CHIP_IS_E1(bp)) { 8102 /* #4 */ 8103 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 8104 /* #2 */ 8105 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 8106 } 8107 8108 /* #3 */ 8109 if (CHIP_IS_E1x(bp)) { 8110 /* Prevent interrupts from HC on both ports */ 8111 val = REG_RD(bp, HC_REG_CONFIG_1); 8112 REG_WR(bp, HC_REG_CONFIG_1, 8113 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 8114 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 8115 8116 val = REG_RD(bp, HC_REG_CONFIG_0); 8117 REG_WR(bp, HC_REG_CONFIG_0, 8118 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 8119 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 8120 } else { 8121 /* Prevent incomming interrupts in IGU */ 8122 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 8123 8124 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, 8125 (!close) ? 8126 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 8127 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 8128 } 8129 8130 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n", 8131 close ? "closing" : "opening"); 8132 mmiowb(); 8133} 8134 8135#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ 8136 8137static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) 8138{ 8139 /* Do some magic... */ 8140 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8141 *magic_val = val & SHARED_MF_CLP_MAGIC; 8142 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 8143} 8144 8145/** 8146 * bnx2x_clp_reset_done - restore the value of the `magic' bit. 8147 * 8148 * @bp: driver handle 8149 * @magic_val: old value of the `magic' bit. 8150 */ 8151static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 8152{ 8153 /* Restore the `magic' bit value... */ 8154 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8155 MF_CFG_WR(bp, shared_mf_config.clp_mb, 8156 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 8157} 8158 8159/** 8160 * bnx2x_reset_mcp_prep - prepare for MCP reset. 8161 * 8162 * @bp: driver handle 8163 * @magic_val: old value of 'magic' bit. 8164 * 8165 * Takes care of CLP configurations. 8166 */ 8167static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 8168{ 8169 u32 shmem; 8170 u32 validity_offset; 8171 8172 DP(NETIF_MSG_HW, "Starting\n"); 8173 8174 /* Set `magic' bit in order to save MF config */ 8175 if (!CHIP_IS_E1(bp)) 8176 bnx2x_clp_reset_prep(bp, magic_val); 8177 8178 /* Get shmem offset */ 8179 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8180 validity_offset = offsetof(struct shmem_region, validity_map[0]); 8181 8182 /* Clear validity map flags */ 8183 if (shmem > 0) 8184 REG_WR(bp, shmem + validity_offset, 0); 8185} 8186 8187#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 8188#define MCP_ONE_TIMEOUT 100 /* 100 ms */ 8189 8190/** 8191 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT 8192 * 8193 * @bp: driver handle 8194 */ 8195static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) 8196{ 8197 /* special handling for emulation and FPGA, 8198 wait 10 times longer */ 8199 if (CHIP_REV_IS_SLOW(bp)) 8200 msleep(MCP_ONE_TIMEOUT*10); 8201 else 8202 msleep(MCP_ONE_TIMEOUT); 8203} 8204 8205/* 8206 * initializes bp->common.shmem_base and waits for validity signature to appear 8207 */ 8208static int bnx2x_init_shmem(struct bnx2x *bp) 8209{ 8210 int cnt = 0; 8211 u32 val = 0; 8212 8213 do { 8214 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8215 if (bp->common.shmem_base) { 8216 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 8217 if (val & SHR_MEM_VALIDITY_MB) 8218 return 0; 8219 } 8220 8221 bnx2x_mcp_wait_one(bp); 8222 8223 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 8224 8225 BNX2X_ERR("BAD MCP validity signature\n"); 8226 8227 return -ENODEV; 8228} 8229 8230static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 8231{ 8232 int rc = bnx2x_init_shmem(bp); 8233 8234 /* Restore the `magic' bit value */ 8235 if (!CHIP_IS_E1(bp)) 8236 bnx2x_clp_reset_done(bp, magic_val); 8237 8238 return rc; 8239} 8240 8241static void bnx2x_pxp_prep(struct bnx2x *bp) 8242{ 8243 if (!CHIP_IS_E1(bp)) { 8244 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 8245 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 8246 mmiowb(); 8247 } 8248} 8249 8250/* 8251 * Reset the whole chip except for: 8252 * - PCIE core 8253 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by 8254 * one reset bit) 8255 * - IGU 8256 * - MISC (including AEU) 8257 * - GRC 8258 * - RBCN, RBCP 8259 */ 8260static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) 8261{ 8262 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 8263 u32 global_bits2, stay_reset2; 8264 8265 /* 8266 * Bits that have to be set in reset_mask2 if we want to reset 'global' 8267 * (per chip) blocks. 8268 */ 8269 global_bits2 = 8270 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 8271 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 8272 8273 /* Don't reset the following blocks */ 8274 not_reset_mask1 = 8275 MISC_REGISTERS_RESET_REG_1_RST_HC | 8276 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 8277 MISC_REGISTERS_RESET_REG_1_RST_PXP; 8278 8279 not_reset_mask2 = 8280 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 8281 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 8282 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 8283 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 8284 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 8285 MISC_REGISTERS_RESET_REG_2_RST_GRC | 8286 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 8287 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 8288 MISC_REGISTERS_RESET_REG_2_RST_ATC | 8289 MISC_REGISTERS_RESET_REG_2_PGLC; 8290 8291 /* 8292 * Keep the following blocks in reset: 8293 * - all xxMACs are handled by the bnx2x_link code. 8294 */ 8295 stay_reset2 = 8296 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 8297 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 8298 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 8299 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 8300 MISC_REGISTERS_RESET_REG_2_UMAC0 | 8301 MISC_REGISTERS_RESET_REG_2_UMAC1 | 8302 MISC_REGISTERS_RESET_REG_2_XMAC | 8303 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 8304 8305 /* Full reset masks according to the chip */ 8306 reset_mask1 = 0xffffffff; 8307 8308 if (CHIP_IS_E1(bp)) 8309 reset_mask2 = 0xffff; 8310 else if (CHIP_IS_E1H(bp)) 8311 reset_mask2 = 0x1ffff; 8312 else if (CHIP_IS_E2(bp)) 8313 reset_mask2 = 0xfffff; 8314 else /* CHIP_IS_E3 */ 8315 reset_mask2 = 0x3ffffff; 8316 8317 /* Don't reset global blocks unless we need to */ 8318 if (!global) 8319 reset_mask2 &= ~global_bits2; 8320 8321 /* 8322 * In case of attention in the QM, we need to reset PXP 8323 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 8324 * because otherwise QM reset would release 'close the gates' shortly 8325 * before resetting the PXP, then the PSWRQ would send a write 8326 * request to PGLUE. Then when PXP is reset, PGLUE would try to 8327 * read the payload data from PSWWR, but PSWWR would not 8328 * respond. The write queue in PGLUE would stuck, dmae commands 8329 * would not return. Therefore it's important to reset the second 8330 * reset register (containing the 8331 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 8332 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 8333 * bit). 8334 */ 8335 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8336 reset_mask2 & (~not_reset_mask2)); 8337 8338 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8339 reset_mask1 & (~not_reset_mask1)); 8340 8341 barrier(); 8342 mmiowb(); 8343 8344 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 8345 reset_mask2 & (~stay_reset2)); 8346 8347 barrier(); 8348 mmiowb(); 8349 8350 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 8351 mmiowb(); 8352} 8353 8354/** 8355 * bnx2x_er_poll_igu_vq - poll for pending writes bit. 8356 * It should get cleared in no more than 1s. 8357 * 8358 * @bp: driver handle 8359 * 8360 * It should get cleared in no more than 1s. Returns 0 if 8361 * pending writes bit gets cleared. 8362 */ 8363static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) 8364{ 8365 u32 cnt = 1000; 8366 u32 pend_bits = 0; 8367 8368 do { 8369 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); 8370 8371 if (pend_bits == 0) 8372 break; 8373 8374 usleep_range(1000, 1000); 8375 } while (cnt-- > 0); 8376 8377 if (cnt <= 0) { 8378 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", 8379 pend_bits); 8380 return -EBUSY; 8381 } 8382 8383 return 0; 8384} 8385 8386static int bnx2x_process_kill(struct bnx2x *bp, bool global) 8387{ 8388 int cnt = 1000; 8389 u32 val = 0; 8390 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 8391 8392 8393 /* Empty the Tetris buffer, wait for 1s */ 8394 do { 8395 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); 8396 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); 8397 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); 8398 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); 8399 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); 8400 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 8401 ((port_is_idle_0 & 0x1) == 0x1) && 8402 ((port_is_idle_1 & 0x1) == 0x1) && 8403 (pgl_exp_rom2 == 0xffffffff)) 8404 break; 8405 usleep_range(1000, 1000); 8406 } while (cnt-- > 0); 8407 8408 if (cnt <= 0) { 8409 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there" 8410 " are still" 8411 " outstanding read requests after 1s!\n"); 8412 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x," 8413 " port_is_idle_0=0x%08x," 8414 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 8415 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 8416 pgl_exp_rom2); 8417 return -EAGAIN; 8418 } 8419 8420 barrier(); 8421 8422 /* Close gates #2, #3 and #4 */ 8423 bnx2x_set_234_gates(bp, true); 8424 8425 /* Poll for IGU VQs for 57712 and newer chips */ 8426 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) 8427 return -EAGAIN; 8428 8429 8430 /* TBD: Indicate that "process kill" is in progress to MCP */ 8431 8432 /* Clear "unprepared" bit */ 8433 REG_WR(bp, MISC_REG_UNPREPARED, 0); 8434 barrier(); 8435 8436 /* Make sure all is written to the chip before the reset */ 8437 mmiowb(); 8438 8439 /* Wait for 1ms to empty GLUE and PCI-E core queues, 8440 * PSWHST, GRC and PSWRD Tetris buffer. 8441 */ 8442 usleep_range(1000, 1000); 8443 8444 /* Prepare to chip reset: */ 8445 /* MCP */ 8446 if (global) 8447 bnx2x_reset_mcp_prep(bp, &val); 8448 8449 /* PXP */ 8450 bnx2x_pxp_prep(bp); 8451 barrier(); 8452 8453 /* reset the chip */ 8454 bnx2x_process_kill_chip_reset(bp, global); 8455 barrier(); 8456 8457 /* Recover after reset: */ 8458 /* MCP */ 8459 if (global && bnx2x_reset_mcp_comp(bp, val)) 8460 return -EAGAIN; 8461 8462 /* TBD: Add resetting the NO_MCP mode DB here */ 8463 8464 /* PXP */ 8465 bnx2x_pxp_prep(bp); 8466 8467 /* Open the gates #2, #3 and #4 */ 8468 bnx2x_set_234_gates(bp, false); 8469 8470 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a 8471 * reset state, re-enable attentions. */ 8472 8473 return 0; 8474} 8475 8476int bnx2x_leader_reset(struct bnx2x *bp) 8477{ 8478 int rc = 0; 8479 bool global = bnx2x_reset_is_global(bp); 8480 8481 /* Try to recover after the failure */ 8482 if (bnx2x_process_kill(bp, global)) { 8483 netdev_err(bp->dev, "Something bad had happen on engine %d! " 8484 "Aii!\n", BP_PATH(bp)); 8485 rc = -EAGAIN; 8486 goto exit_leader_reset; 8487 } 8488 8489 /* 8490 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver 8491 * state. 8492 */ 8493 bnx2x_set_reset_done(bp); 8494 if (global) 8495 bnx2x_clear_reset_global(bp); 8496 8497exit_leader_reset: 8498 bp->is_leader = 0; 8499 bnx2x_release_leader_lock(bp); 8500 smp_mb(); 8501 return rc; 8502} 8503 8504static inline void bnx2x_recovery_failed(struct bnx2x *bp) 8505{ 8506 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); 8507 8508 /* Disconnect this device */ 8509 netif_device_detach(bp->dev); 8510 8511 /* 8512 * Block ifup for all function on this engine until "process kill" 8513 * or power cycle. 8514 */ 8515 bnx2x_set_reset_in_progress(bp); 8516 8517 /* Shut down the power */ 8518 bnx2x_set_power_state(bp, PCI_D3hot); 8519 8520 bp->recovery_state = BNX2X_RECOVERY_FAILED; 8521 8522 smp_mb(); 8523} 8524 8525/* 8526 * Assumption: runs under rtnl lock. This together with the fact 8527 * that it's called only from bnx2x_sp_rtnl() ensure that it 8528 * will never be called when netif_running(bp->dev) is false. 8529 */ 8530static void bnx2x_parity_recover(struct bnx2x *bp) 8531{ 8532 bool global = false; 8533 8534 DP(NETIF_MSG_HW, "Handling parity\n"); 8535 while (1) { 8536 switch (bp->recovery_state) { 8537 case BNX2X_RECOVERY_INIT: 8538 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 8539 bnx2x_chk_parity_attn(bp, &global, false); 8540 8541 /* Try to get a LEADER_LOCK HW lock */ 8542 if (bnx2x_trylock_leader_lock(bp)) { 8543 bnx2x_set_reset_in_progress(bp); 8544 /* 8545 * Check if there is a global attention and if 8546 * there was a global attention, set the global 8547 * reset bit. 8548 */ 8549 8550 if (global) 8551 bnx2x_set_reset_global(bp); 8552 8553 bp->is_leader = 1; 8554 } 8555 8556 /* Stop the driver */ 8557 /* If interface has been removed - break */ 8558 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) 8559 return; 8560 8561 bp->recovery_state = BNX2X_RECOVERY_WAIT; 8562 8563 /* 8564 * Reset MCP command sequence number and MCP mail box 8565 * sequence as we are going to reset the MCP. 8566 */ 8567 if (global) { 8568 bp->fw_seq = 0; 8569 bp->fw_drv_pulse_wr_seq = 0; 8570 } 8571 8572 /* Ensure "is_leader", MCP command sequence and 8573 * "recovery_state" update values are seen on other 8574 * CPUs. 8575 */ 8576 smp_mb(); 8577 break; 8578 8579 case BNX2X_RECOVERY_WAIT: 8580 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 8581 if (bp->is_leader) { 8582 int other_engine = BP_PATH(bp) ? 0 : 1; 8583 bool other_load_status = 8584 bnx2x_get_load_status(bp, other_engine); 8585 bool load_status = 8586 bnx2x_get_load_status(bp, BP_PATH(bp)); 8587 global = bnx2x_reset_is_global(bp); 8588 8589 /* 8590 * In case of a parity in a global block, let 8591 * the first leader that performs a 8592 * leader_reset() reset the global blocks in 8593 * order to clear global attentions. Otherwise 8594 * the the gates will remain closed for that 8595 * engine. 8596 */ 8597 if (load_status || 8598 (global && other_load_status)) { 8599 /* Wait until all other functions get 8600 * down. 8601 */ 8602 schedule_delayed_work(&bp->sp_rtnl_task, 8603 HZ/10); 8604 return; 8605 } else { 8606 /* If all other functions got down - 8607 * try to bring the chip back to 8608 * normal. In any case it's an exit 8609 * point for a leader. 8610 */ 8611 if (bnx2x_leader_reset(bp)) { 8612 bnx2x_recovery_failed(bp); 8613 return; 8614 } 8615 8616 /* If we are here, means that the 8617 * leader has succeeded and doesn't 8618 * want to be a leader any more. Try 8619 * to continue as a none-leader. 8620 */ 8621 break; 8622 } 8623 } else { /* non-leader */ 8624 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { 8625 /* Try to get a LEADER_LOCK HW lock as 8626 * long as a former leader may have 8627 * been unloaded by the user or 8628 * released a leadership by another 8629 * reason. 8630 */ 8631 if (bnx2x_trylock_leader_lock(bp)) { 8632 /* I'm a leader now! Restart a 8633 * switch case. 8634 */ 8635 bp->is_leader = 1; 8636 break; 8637 } 8638 8639 schedule_delayed_work(&bp->sp_rtnl_task, 8640 HZ/10); 8641 return; 8642 8643 } else { 8644 /* 8645 * If there was a global attention, wait 8646 * for it to be cleared. 8647 */ 8648 if (bnx2x_reset_is_global(bp)) { 8649 schedule_delayed_work( 8650 &bp->sp_rtnl_task, 8651 HZ/10); 8652 return; 8653 } 8654 8655 if (bnx2x_nic_load(bp, LOAD_NORMAL)) 8656 bnx2x_recovery_failed(bp); 8657 else { 8658 bp->recovery_state = 8659 BNX2X_RECOVERY_DONE; 8660 smp_mb(); 8661 } 8662 8663 return; 8664 } 8665 } 8666 default: 8667 return; 8668 } 8669 } 8670} 8671 8672/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is 8673 * scheduled on a general queue in order to prevent a dead lock. 8674 */ 8675static void bnx2x_sp_rtnl_task(struct work_struct *work) 8676{ 8677 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); 8678 8679 rtnl_lock(); 8680 8681 if (!netif_running(bp->dev)) 8682 goto sp_rtnl_exit; 8683 8684 /* if stop on error is defined no recovery flows should be executed */ 8685#ifdef BNX2X_STOP_ON_ERROR 8686 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined " 8687 "so reset not done to allow debug dump,\n" 8688 "you will need to reboot when done\n"); 8689 goto sp_rtnl_not_reset; 8690#endif 8691 8692 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { 8693 /* 8694 * Clear all pending SP commands as we are going to reset the 8695 * function anyway. 8696 */ 8697 bp->sp_rtnl_state = 0; 8698 smp_mb(); 8699 8700 bnx2x_parity_recover(bp); 8701 8702 goto sp_rtnl_exit; 8703 } 8704 8705 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { 8706 /* 8707 * Clear all pending SP commands as we are going to reset the 8708 * function anyway. 8709 */ 8710 bp->sp_rtnl_state = 0; 8711 smp_mb(); 8712 8713 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 8714 bnx2x_nic_load(bp, LOAD_NORMAL); 8715 8716 goto sp_rtnl_exit; 8717 } 8718#ifdef BNX2X_STOP_ON_ERROR 8719sp_rtnl_not_reset: 8720#endif 8721 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) 8722 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); 8723 8724 /* 8725 * in case of fan failure we need to reset id if the "stop on error" 8726 * debug flag is set, since we trying to prevent permanent overheating 8727 * damage 8728 */ 8729 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { 8730 DP(BNX2X_MSG_SP, "fan failure detected. Unloading driver\n"); 8731 netif_device_detach(bp->dev); 8732 bnx2x_close(bp->dev); 8733 } 8734 8735sp_rtnl_exit: 8736 rtnl_unlock(); 8737} 8738 8739/* end of nic load/unload */ 8740 8741static void bnx2x_period_task(struct work_struct *work) 8742{ 8743 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); 8744 8745 if (!netif_running(bp->dev)) 8746 goto period_task_exit; 8747 8748 if (CHIP_REV_IS_SLOW(bp)) { 8749 BNX2X_ERR("period task called on emulation, ignoring\n"); 8750 goto period_task_exit; 8751 } 8752 8753 bnx2x_acquire_phy_lock(bp); 8754 /* 8755 * The barrier is needed to ensure the ordering between the writing to 8756 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and 8757 * the reading here. 8758 */ 8759 smp_mb(); 8760 if (bp->port.pmf) { 8761 bnx2x_period_func(&bp->link_params, &bp->link_vars); 8762 8763 /* Re-queue task in 1 sec */ 8764 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); 8765 } 8766 8767 bnx2x_release_phy_lock(bp); 8768period_task_exit: 8769 return; 8770} 8771 8772/* 8773 * Init service functions 8774 */ 8775 8776static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) 8777{ 8778 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; 8779 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; 8780 return base + (BP_ABS_FUNC(bp)) * stride; 8781} 8782 8783static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) 8784{ 8785 u32 reg = bnx2x_get_pretend_reg(bp); 8786 8787 /* Flush all outstanding writes */ 8788 mmiowb(); 8789 8790 /* Pretend to be function 0 */ 8791 REG_WR(bp, reg, 0); 8792 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ 8793 8794 /* From now we are in the "like-E1" mode */ 8795 bnx2x_int_disable(bp); 8796 8797 /* Flush all outstanding writes */ 8798 mmiowb(); 8799 8800 /* Restore the original function */ 8801 REG_WR(bp, reg, BP_ABS_FUNC(bp)); 8802 REG_RD(bp, reg); 8803} 8804 8805static inline void bnx2x_undi_int_disable(struct bnx2x *bp) 8806{ 8807 if (CHIP_IS_E1(bp)) 8808 bnx2x_int_disable(bp); 8809 else 8810 bnx2x_undi_int_disable_e1h(bp); 8811} 8812 8813static void __devinit bnx2x_undi_unload(struct bnx2x *bp) 8814{ 8815 u32 val; 8816 8817 /* possibly another driver is trying to reset the chip */ 8818 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8819 8820 /* check if doorbell queue is reset */ 8821 if (REG_RD(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET) 8822 & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { 8823 8824 /* 8825 * Check if it is the UNDI driver 8826 * UNDI driver initializes CID offset for normal bell to 0x7 8827 */ 8828 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 8829 if (val == 0x7) { 8830 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8831 /* save our pf_num */ 8832 int orig_pf_num = bp->pf_num; 8833 int port; 8834 u32 swap_en, swap_val, value; 8835 8836 /* clear the UNDI indication */ 8837 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 8838 8839 BNX2X_DEV_INFO("UNDI is active! reset device\n"); 8840 8841 /* try unload UNDI on port 0 */ 8842 bp->pf_num = 0; 8843 bp->fw_seq = 8844 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8845 DRV_MSG_SEQ_NUMBER_MASK); 8846 reset_code = bnx2x_fw_command(bp, reset_code, 0); 8847 8848 /* if UNDI is loaded on the other port */ 8849 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { 8850 8851 /* send "DONE" for previous unload */ 8852 bnx2x_fw_command(bp, 8853 DRV_MSG_CODE_UNLOAD_DONE, 0); 8854 8855 /* unload UNDI on port 1 */ 8856 bp->pf_num = 1; 8857 bp->fw_seq = 8858 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8859 DRV_MSG_SEQ_NUMBER_MASK); 8860 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8861 8862 bnx2x_fw_command(bp, reset_code, 0); 8863 } 8864 8865 bnx2x_undi_int_disable(bp); 8866 port = BP_PORT(bp); 8867 8868 /* close input traffic and wait for it */ 8869 /* Do not rcv packets to BRB */ 8870 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK : 8871 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0); 8872 /* Do not direct rcv packets that are not for MCP to 8873 * the BRB */ 8874 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 8875 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 8876 /* clear AEU */ 8877 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8878 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0); 8879 msleep(10); 8880 8881 /* save NIG port swap info */ 8882 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 8883 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 8884 /* reset device */ 8885 REG_WR(bp, 8886 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8887 0xd3ffffff); 8888 8889 value = 0x1400; 8890 if (CHIP_IS_E3(bp)) { 8891 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 8892 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 8893 } 8894 8895 REG_WR(bp, 8896 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8897 value); 8898 8899 /* take the NIG out of reset and restore swap values */ 8900 REG_WR(bp, 8901 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 8902 MISC_REGISTERS_RESET_REG_1_RST_NIG); 8903 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val); 8904 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en); 8905 8906 /* send unload done to the MCP */ 8907 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 8908 8909 /* restore our func and fw_seq */ 8910 bp->pf_num = orig_pf_num; 8911 bp->fw_seq = 8912 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8913 DRV_MSG_SEQ_NUMBER_MASK); 8914 } 8915 } 8916 8917 /* now it's safe to release the lock */ 8918 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8919} 8920 8921static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) 8922{ 8923 u32 val, val2, val3, val4, id, boot_mode; 8924 u16 pmc; 8925 8926 /* Get the chip revision id and number. */ 8927 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 8928 val = REG_RD(bp, MISC_REG_CHIP_NUM); 8929 id = ((val & 0xffff) << 16); 8930 val = REG_RD(bp, MISC_REG_CHIP_REV); 8931 id |= ((val & 0xf) << 12); 8932 val = REG_RD(bp, MISC_REG_CHIP_METAL); 8933 id |= ((val & 0xff) << 4); 8934 val = REG_RD(bp, MISC_REG_BOND_ID); 8935 id |= (val & 0xf); 8936 bp->common.chip_id = id; 8937 8938 /* Set doorbell size */ 8939 bp->db_size = (1 << BNX2X_DB_SHIFT); 8940 8941 if (!CHIP_IS_E1x(bp)) { 8942 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 8943 if ((val & 1) == 0) 8944 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); 8945 else 8946 val = (val >> 1) & 1; 8947 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : 8948 "2_PORT_MODE"); 8949 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : 8950 CHIP_2_PORT_MODE; 8951 8952 if (CHIP_MODE_IS_4_PORT(bp)) 8953 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ 8954 else 8955 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ 8956 } else { 8957 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ 8958 bp->pfid = bp->pf_num; /* 0..7 */ 8959 } 8960 8961 bp->link_params.chip_id = bp->common.chip_id; 8962 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 8963 8964 val = (REG_RD(bp, 0x2874) & 0x55); 8965 if ((bp->common.chip_id & 0x1) || 8966 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { 8967 bp->flags |= ONE_PORT_FLAG; 8968 BNX2X_DEV_INFO("single port device\n"); 8969 } 8970 8971 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); 8972 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << 8973 (val & MCPR_NVM_CFG4_FLASH_SIZE)); 8974 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 8975 bp->common.flash_size, bp->common.flash_size); 8976 8977 bnx2x_init_shmem(bp); 8978 8979 8980 8981 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? 8982 MISC_REG_GENERIC_CR_1 : 8983 MISC_REG_GENERIC_CR_0)); 8984 8985 bp->link_params.shmem_base = bp->common.shmem_base; 8986 bp->link_params.shmem2_base = bp->common.shmem2_base; 8987 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 8988 bp->common.shmem_base, bp->common.shmem2_base); 8989 8990 if (!bp->common.shmem_base) { 8991 BNX2X_DEV_INFO("MCP not active\n"); 8992 bp->flags |= NO_MCP_FLAG; 8993 return; 8994 } 8995 8996 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 8997 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 8998 8999 bp->link_params.hw_led_mode = ((bp->common.hw_config & 9000 SHARED_HW_CFG_LED_MODE_MASK) >> 9001 SHARED_HW_CFG_LED_MODE_SHIFT); 9002 9003 bp->link_params.feature_config_flags = 0; 9004 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); 9005 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) 9006 bp->link_params.feature_config_flags |= 9007 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 9008 else 9009 bp->link_params.feature_config_flags &= 9010 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 9011 9012 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 9013 bp->common.bc_ver = val; 9014 BNX2X_DEV_INFO("bc_ver %X\n", val); 9015 if (val < BNX2X_BC_VER) { 9016 /* for now only warn 9017 * later we might need to enforce this */ 9018 BNX2X_ERR("This driver needs bc_ver %X but found %X, " 9019 "please upgrade BC\n", BNX2X_BC_VER, val); 9020 } 9021 bp->link_params.feature_config_flags |= 9022 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 9023 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 9024 9025 bp->link_params.feature_config_flags |= 9026 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? 9027 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; 9028 9029 bp->link_params.feature_config_flags |= 9030 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? 9031 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; 9032 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? 9033 BC_SUPPORTS_PFC_STATS : 0; 9034 9035 boot_mode = SHMEM_RD(bp, 9036 dev_info.port_feature_config[BP_PORT(bp)].mba_config) & 9037 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; 9038 switch (boot_mode) { 9039 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: 9040 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; 9041 break; 9042 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: 9043 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; 9044 break; 9045 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: 9046 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; 9047 break; 9048 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: 9049 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; 9050 break; 9051 } 9052 9053 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); 9054 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; 9055 9056 BNX2X_DEV_INFO("%sWoL capable\n", 9057 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 9058 9059 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 9060 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 9061 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); 9062 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); 9063 9064 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", 9065 val, val2, val3, val4); 9066} 9067 9068#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 9069#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 9070 9071static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) 9072{ 9073 int pfid = BP_FUNC(bp); 9074 int igu_sb_id; 9075 u32 val; 9076 u8 fid, igu_sb_cnt = 0; 9077 9078 bp->igu_base_sb = 0xff; 9079 if (CHIP_INT_MODE_IS_BC(bp)) { 9080 int vn = BP_VN(bp); 9081 igu_sb_cnt = bp->igu_sb_cnt; 9082 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 9083 FP_SB_MAX_E1x; 9084 9085 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + 9086 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); 9087 9088 return; 9089 } 9090 9091 /* IGU in normal mode - read CAM */ 9092 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 9093 igu_sb_id++) { 9094 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 9095 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 9096 continue; 9097 fid = IGU_FID(val); 9098 if ((fid & IGU_FID_ENCODE_IS_PF)) { 9099 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) 9100 continue; 9101 if (IGU_VEC(val) == 0) 9102 /* default status block */ 9103 bp->igu_dsb_id = igu_sb_id; 9104 else { 9105 if (bp->igu_base_sb == 0xff) 9106 bp->igu_base_sb = igu_sb_id; 9107 igu_sb_cnt++; 9108 } 9109 } 9110 } 9111 9112#ifdef CONFIG_PCI_MSI 9113 /* 9114 * It's expected that number of CAM entries for this functions is equal 9115 * to the number evaluated based on the MSI-X table size. We want a 9116 * harsh warning if these values are different! 9117 */ 9118 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); 9119#endif 9120 9121 if (igu_sb_cnt == 0) 9122 BNX2X_ERR("CAM configuration error\n"); 9123} 9124 9125static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, 9126 u32 switch_cfg) 9127{ 9128 int cfg_size = 0, idx, port = BP_PORT(bp); 9129 9130 /* Aggregation of supported attributes of all external phys */ 9131 bp->port.supported[0] = 0; 9132 bp->port.supported[1] = 0; 9133 switch (bp->link_params.num_phys) { 9134 case 1: 9135 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; 9136 cfg_size = 1; 9137 break; 9138 case 2: 9139 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; 9140 cfg_size = 1; 9141 break; 9142 case 3: 9143 if (bp->link_params.multi_phy_config & 9144 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 9145 bp->port.supported[1] = 9146 bp->link_params.phy[EXT_PHY1].supported; 9147 bp->port.supported[0] = 9148 bp->link_params.phy[EXT_PHY2].supported; 9149 } else { 9150 bp->port.supported[0] = 9151 bp->link_params.phy[EXT_PHY1].supported; 9152 bp->port.supported[1] = 9153 bp->link_params.phy[EXT_PHY2].supported; 9154 } 9155 cfg_size = 2; 9156 break; 9157 } 9158 9159 if (!(bp->port.supported[0] || bp->port.supported[1])) { 9160 BNX2X_ERR("NVRAM config error. BAD phy config." 9161 "PHY1 config 0x%x, PHY2 config 0x%x\n", 9162 SHMEM_RD(bp, 9163 dev_info.port_hw_config[port].external_phy_config), 9164 SHMEM_RD(bp, 9165 dev_info.port_hw_config[port].external_phy_config2)); 9166 return; 9167 } 9168 9169 if (CHIP_IS_E3(bp)) 9170 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); 9171 else { 9172 switch (switch_cfg) { 9173 case SWITCH_CFG_1G: 9174 bp->port.phy_addr = REG_RD( 9175 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 9176 break; 9177 case SWITCH_CFG_10G: 9178 bp->port.phy_addr = REG_RD( 9179 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 9180 break; 9181 default: 9182 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 9183 bp->port.link_config[0]); 9184 return; 9185 } 9186 } 9187 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 9188 /* mask what we support according to speed_cap_mask per configuration */ 9189 for (idx = 0; idx < cfg_size; idx++) { 9190 if (!(bp->link_params.speed_cap_mask[idx] & 9191 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 9192 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; 9193 9194 if (!(bp->link_params.speed_cap_mask[idx] & 9195 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 9196 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; 9197 9198 if (!(bp->link_params.speed_cap_mask[idx] & 9199 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 9200 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; 9201 9202 if (!(bp->link_params.speed_cap_mask[idx] & 9203 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 9204 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; 9205 9206 if (!(bp->link_params.speed_cap_mask[idx] & 9207 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 9208 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | 9209 SUPPORTED_1000baseT_Full); 9210 9211 if (!(bp->link_params.speed_cap_mask[idx] & 9212 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 9213 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; 9214 9215 if (!(bp->link_params.speed_cap_mask[idx] & 9216 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 9217 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; 9218 9219 } 9220 9221 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], 9222 bp->port.supported[1]); 9223} 9224 9225static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) 9226{ 9227 u32 link_config, idx, cfg_size = 0; 9228 bp->port.advertising[0] = 0; 9229 bp->port.advertising[1] = 0; 9230 switch (bp->link_params.num_phys) { 9231 case 1: 9232 case 2: 9233 cfg_size = 1; 9234 break; 9235 case 3: 9236 cfg_size = 2; 9237 break; 9238 } 9239 for (idx = 0; idx < cfg_size; idx++) { 9240 bp->link_params.req_duplex[idx] = DUPLEX_FULL; 9241 link_config = bp->port.link_config[idx]; 9242 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 9243 case PORT_FEATURE_LINK_SPEED_AUTO: 9244 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { 9245 bp->link_params.req_line_speed[idx] = 9246 SPEED_AUTO_NEG; 9247 bp->port.advertising[idx] |= 9248 bp->port.supported[idx]; 9249 } else { 9250 /* force 10G, no AN */ 9251 bp->link_params.req_line_speed[idx] = 9252 SPEED_10000; 9253 bp->port.advertising[idx] |= 9254 (ADVERTISED_10000baseT_Full | 9255 ADVERTISED_FIBRE); 9256 continue; 9257 } 9258 break; 9259 9260 case PORT_FEATURE_LINK_SPEED_10M_FULL: 9261 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { 9262 bp->link_params.req_line_speed[idx] = 9263 SPEED_10; 9264 bp->port.advertising[idx] |= 9265 (ADVERTISED_10baseT_Full | 9266 ADVERTISED_TP); 9267 } else { 9268 BNX2X_ERR("NVRAM config error. " 9269 "Invalid link_config 0x%x" 9270 " speed_cap_mask 0x%x\n", 9271 link_config, 9272 bp->link_params.speed_cap_mask[idx]); 9273 return; 9274 } 9275 break; 9276 9277 case PORT_FEATURE_LINK_SPEED_10M_HALF: 9278 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { 9279 bp->link_params.req_line_speed[idx] = 9280 SPEED_10; 9281 bp->link_params.req_duplex[idx] = 9282 DUPLEX_HALF; 9283 bp->port.advertising[idx] |= 9284 (ADVERTISED_10baseT_Half | 9285 ADVERTISED_TP); 9286 } else { 9287 BNX2X_ERR("NVRAM config error. " 9288 "Invalid link_config 0x%x" 9289 " speed_cap_mask 0x%x\n", 9290 link_config, 9291 bp->link_params.speed_cap_mask[idx]); 9292 return; 9293 } 9294 break; 9295 9296 case PORT_FEATURE_LINK_SPEED_100M_FULL: 9297 if (bp->port.supported[idx] & 9298 SUPPORTED_100baseT_Full) { 9299 bp->link_params.req_line_speed[idx] = 9300 SPEED_100; 9301 bp->port.advertising[idx] |= 9302 (ADVERTISED_100baseT_Full | 9303 ADVERTISED_TP); 9304 } else { 9305 BNX2X_ERR("NVRAM config error. " 9306 "Invalid link_config 0x%x" 9307 " speed_cap_mask 0x%x\n", 9308 link_config, 9309 bp->link_params.speed_cap_mask[idx]); 9310 return; 9311 } 9312 break; 9313 9314 case PORT_FEATURE_LINK_SPEED_100M_HALF: 9315 if (bp->port.supported[idx] & 9316 SUPPORTED_100baseT_Half) { 9317 bp->link_params.req_line_speed[idx] = 9318 SPEED_100; 9319 bp->link_params.req_duplex[idx] = 9320 DUPLEX_HALF; 9321 bp->port.advertising[idx] |= 9322 (ADVERTISED_100baseT_Half | 9323 ADVERTISED_TP); 9324 } else { 9325 BNX2X_ERR("NVRAM config error. " 9326 "Invalid link_config 0x%x" 9327 " speed_cap_mask 0x%x\n", 9328 link_config, 9329 bp->link_params.speed_cap_mask[idx]); 9330 return; 9331 } 9332 break; 9333 9334 case PORT_FEATURE_LINK_SPEED_1G: 9335 if (bp->port.supported[idx] & 9336 SUPPORTED_1000baseT_Full) { 9337 bp->link_params.req_line_speed[idx] = 9338 SPEED_1000; 9339 bp->port.advertising[idx] |= 9340 (ADVERTISED_1000baseT_Full | 9341 ADVERTISED_TP); 9342 } else { 9343 BNX2X_ERR("NVRAM config error. " 9344 "Invalid link_config 0x%x" 9345 " speed_cap_mask 0x%x\n", 9346 link_config, 9347 bp->link_params.speed_cap_mask[idx]); 9348 return; 9349 } 9350 break; 9351 9352 case PORT_FEATURE_LINK_SPEED_2_5G: 9353 if (bp->port.supported[idx] & 9354 SUPPORTED_2500baseX_Full) { 9355 bp->link_params.req_line_speed[idx] = 9356 SPEED_2500; 9357 bp->port.advertising[idx] |= 9358 (ADVERTISED_2500baseX_Full | 9359 ADVERTISED_TP); 9360 } else { 9361 BNX2X_ERR("NVRAM config error. " 9362 "Invalid link_config 0x%x" 9363 " speed_cap_mask 0x%x\n", 9364 link_config, 9365 bp->link_params.speed_cap_mask[idx]); 9366 return; 9367 } 9368 break; 9369 9370 case PORT_FEATURE_LINK_SPEED_10G_CX4: 9371 if (bp->port.supported[idx] & 9372 SUPPORTED_10000baseT_Full) { 9373 bp->link_params.req_line_speed[idx] = 9374 SPEED_10000; 9375 bp->port.advertising[idx] |= 9376 (ADVERTISED_10000baseT_Full | 9377 ADVERTISED_FIBRE); 9378 } else { 9379 BNX2X_ERR("NVRAM config error. " 9380 "Invalid link_config 0x%x" 9381 " speed_cap_mask 0x%x\n", 9382 link_config, 9383 bp->link_params.speed_cap_mask[idx]); 9384 return; 9385 } 9386 break; 9387 case PORT_FEATURE_LINK_SPEED_20G: 9388 bp->link_params.req_line_speed[idx] = SPEED_20000; 9389 9390 break; 9391 default: 9392 BNX2X_ERR("NVRAM config error. " 9393 "BAD link speed link_config 0x%x\n", 9394 link_config); 9395 bp->link_params.req_line_speed[idx] = 9396 SPEED_AUTO_NEG; 9397 bp->port.advertising[idx] = 9398 bp->port.supported[idx]; 9399 break; 9400 } 9401 9402 bp->link_params.req_flow_ctrl[idx] = (link_config & 9403 PORT_FEATURE_FLOW_CONTROL_MASK); 9404 if ((bp->link_params.req_flow_ctrl[idx] == 9405 BNX2X_FLOW_CTRL_AUTO) && 9406 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { 9407 bp->link_params.req_flow_ctrl[idx] = 9408 BNX2X_FLOW_CTRL_NONE; 9409 } 9410 9411 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl" 9412 " 0x%x advertising 0x%x\n", 9413 bp->link_params.req_line_speed[idx], 9414 bp->link_params.req_duplex[idx], 9415 bp->link_params.req_flow_ctrl[idx], 9416 bp->port.advertising[idx]); 9417 } 9418} 9419 9420static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 9421{ 9422 mac_hi = cpu_to_be16(mac_hi); 9423 mac_lo = cpu_to_be32(mac_lo); 9424 memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); 9425 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); 9426} 9427 9428static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) 9429{ 9430 int port = BP_PORT(bp); 9431 u32 config; 9432 u32 ext_phy_type, ext_phy_config; 9433 9434 bp->link_params.bp = bp; 9435 bp->link_params.port = port; 9436 9437 bp->link_params.lane_config = 9438 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 9439 9440 bp->link_params.speed_cap_mask[0] = 9441 SHMEM_RD(bp, 9442 dev_info.port_hw_config[port].speed_capability_mask); 9443 bp->link_params.speed_cap_mask[1] = 9444 SHMEM_RD(bp, 9445 dev_info.port_hw_config[port].speed_capability_mask2); 9446 bp->port.link_config[0] = 9447 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 9448 9449 bp->port.link_config[1] = 9450 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); 9451 9452 bp->link_params.multi_phy_config = 9453 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); 9454 /* If the device is capable of WoL, set the default state according 9455 * to the HW 9456 */ 9457 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 9458 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 9459 (config & PORT_FEATURE_WOL_ENABLED)); 9460 9461 BNX2X_DEV_INFO("lane_config 0x%08x " 9462 "speed_cap_mask0 0x%08x link_config0 0x%08x\n", 9463 bp->link_params.lane_config, 9464 bp->link_params.speed_cap_mask[0], 9465 bp->port.link_config[0]); 9466 9467 bp->link_params.switch_cfg = (bp->port.link_config[0] & 9468 PORT_FEATURE_CONNECTED_SWITCH_MASK); 9469 bnx2x_phy_probe(&bp->link_params); 9470 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 9471 9472 bnx2x_link_settings_requested(bp); 9473 9474 /* 9475 * If connected directly, work with the internal PHY, otherwise, work 9476 * with the external PHY 9477 */ 9478 ext_phy_config = 9479 SHMEM_RD(bp, 9480 dev_info.port_hw_config[port].external_phy_config); 9481 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 9482 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 9483 bp->mdio.prtad = bp->port.phy_addr; 9484 9485 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 9486 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 9487 bp->mdio.prtad = 9488 XGXS_EXT_PHY_ADDR(ext_phy_config); 9489 9490 /* 9491 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) 9492 * In MF mode, it is set to cover self test cases 9493 */ 9494 if (IS_MF(bp)) 9495 bp->port.need_hw_lock = 1; 9496 else 9497 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, 9498 bp->common.shmem_base, 9499 bp->common.shmem2_base); 9500} 9501 9502void bnx2x_get_iscsi_info(struct bnx2x *bp) 9503{ 9504#ifdef BCM_CNIC 9505 int port = BP_PORT(bp); 9506 9507 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9508 drv_lic_key[port].max_iscsi_conn); 9509 9510 /* Get the number of maximum allowed iSCSI connections */ 9511 bp->cnic_eth_dev.max_iscsi_conn = 9512 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> 9513 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; 9514 9515 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", 9516 bp->cnic_eth_dev.max_iscsi_conn); 9517 9518 /* 9519 * If maximum allowed number of connections is zero - 9520 * disable the feature. 9521 */ 9522 if (!bp->cnic_eth_dev.max_iscsi_conn) 9523 bp->flags |= NO_ISCSI_FLAG; 9524#else 9525 bp->flags |= NO_ISCSI_FLAG; 9526#endif 9527} 9528 9529static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp) 9530{ 9531#ifdef BCM_CNIC 9532 int port = BP_PORT(bp); 9533 int func = BP_ABS_FUNC(bp); 9534 9535 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9536 drv_lic_key[port].max_fcoe_conn); 9537 9538 /* Get the number of maximum allowed FCoE connections */ 9539 bp->cnic_eth_dev.max_fcoe_conn = 9540 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> 9541 BNX2X_MAX_FCOE_INIT_CONN_SHIFT; 9542 9543 /* Read the WWN: */ 9544 if (!IS_MF(bp)) { 9545 /* Port info */ 9546 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9547 SHMEM_RD(bp, 9548 dev_info.port_hw_config[port]. 9549 fcoe_wwn_port_name_upper); 9550 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9551 SHMEM_RD(bp, 9552 dev_info.port_hw_config[port]. 9553 fcoe_wwn_port_name_lower); 9554 9555 /* Node info */ 9556 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9557 SHMEM_RD(bp, 9558 dev_info.port_hw_config[port]. 9559 fcoe_wwn_node_name_upper); 9560 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9561 SHMEM_RD(bp, 9562 dev_info.port_hw_config[port]. 9563 fcoe_wwn_node_name_lower); 9564 } else if (!IS_MF_SD(bp)) { 9565 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9566 9567 /* 9568 * Read the WWN info only if the FCoE feature is enabled for 9569 * this function. 9570 */ 9571 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9572 /* Port info */ 9573 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9574 MF_CFG_RD(bp, func_ext_config[func]. 9575 fcoe_wwn_port_name_upper); 9576 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9577 MF_CFG_RD(bp, func_ext_config[func]. 9578 fcoe_wwn_port_name_lower); 9579 9580 /* Node info */ 9581 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9582 MF_CFG_RD(bp, func_ext_config[func]. 9583 fcoe_wwn_node_name_upper); 9584 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9585 MF_CFG_RD(bp, func_ext_config[func]. 9586 fcoe_wwn_node_name_lower); 9587 } 9588 } 9589 9590 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); 9591 9592 /* 9593 * If maximum allowed number of connections is zero - 9594 * disable the feature. 9595 */ 9596 if (!bp->cnic_eth_dev.max_fcoe_conn) 9597 bp->flags |= NO_FCOE_FLAG; 9598#else 9599 bp->flags |= NO_FCOE_FLAG; 9600#endif 9601} 9602 9603static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) 9604{ 9605 /* 9606 * iSCSI may be dynamically disabled but reading 9607 * info here we will decrease memory usage by driver 9608 * if the feature is disabled for good 9609 */ 9610 bnx2x_get_iscsi_info(bp); 9611 bnx2x_get_fcoe_info(bp); 9612} 9613 9614static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) 9615{ 9616 u32 val, val2; 9617 int func = BP_ABS_FUNC(bp); 9618 int port = BP_PORT(bp); 9619#ifdef BCM_CNIC 9620 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; 9621 u8 *fip_mac = bp->fip_mac; 9622#endif 9623 9624 /* Zero primary MAC configuration */ 9625 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9626 9627 if (BP_NOMCP(bp)) { 9628 BNX2X_ERROR("warning: random MAC workaround active\n"); 9629 random_ether_addr(bp->dev->dev_addr); 9630 } else if (IS_MF(bp)) { 9631 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 9632 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); 9633 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && 9634 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) 9635 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9636 9637#ifdef BCM_CNIC 9638 /* 9639 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or 9640 * FCoE MAC then the appropriate feature should be disabled. 9641 */ 9642 if (IS_MF_SI(bp)) { 9643 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9644 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 9645 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9646 iscsi_mac_addr_upper); 9647 val = MF_CFG_RD(bp, func_ext_config[func]. 9648 iscsi_mac_addr_lower); 9649 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9650 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9651 iscsi_mac); 9652 } else 9653 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 9654 9655 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9656 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9657 fcoe_mac_addr_upper); 9658 val = MF_CFG_RD(bp, func_ext_config[func]. 9659 fcoe_mac_addr_lower); 9660 bnx2x_set_mac_buf(fip_mac, val, val2); 9661 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n", 9662 fip_mac); 9663 9664 } else 9665 bp->flags |= NO_FCOE_FLAG; 9666 } else { /* SD mode */ 9667 if (BNX2X_IS_MF_PROTOCOL_ISCSI(bp)) { 9668 /* use primary mac as iscsi mac */ 9669 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); 9670 /* Zero primary MAC configuration */ 9671 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9672 9673 BNX2X_DEV_INFO("SD ISCSI MODE\n"); 9674 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9675 iscsi_mac); 9676 } 9677 } 9678#endif 9679 } else { 9680 /* in SF read MACs from port configuration */ 9681 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 9682 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 9683 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9684 9685#ifdef BCM_CNIC 9686 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9687 iscsi_mac_upper); 9688 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9689 iscsi_mac_lower); 9690 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9691 9692 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9693 fcoe_fip_mac_upper); 9694 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9695 fcoe_fip_mac_lower); 9696 bnx2x_set_mac_buf(fip_mac, val, val2); 9697#endif 9698 } 9699 9700 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 9701 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); 9702 9703#ifdef BCM_CNIC 9704 /* Set the FCoE MAC in MF_SD mode */ 9705 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp)) 9706 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); 9707 9708 /* Disable iSCSI if MAC configuration is 9709 * invalid. 9710 */ 9711 if (!is_valid_ether_addr(iscsi_mac)) { 9712 bp->flags |= NO_ISCSI_FLAG; 9713 memset(iscsi_mac, 0, ETH_ALEN); 9714 } 9715 9716 /* Disable FCoE if MAC configuration is 9717 * invalid. 9718 */ 9719 if (!is_valid_ether_addr(fip_mac)) { 9720 bp->flags |= NO_FCOE_FLAG; 9721 memset(bp->fip_mac, 0, ETH_ALEN); 9722 } 9723#endif 9724 9725 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) 9726 dev_err(&bp->pdev->dev, 9727 "bad Ethernet MAC address configuration: " 9728 "%pM, change it manually before bringing up " 9729 "the appropriate network interface\n", 9730 bp->dev->dev_addr); 9731} 9732 9733static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) 9734{ 9735 int /*abs*/func = BP_ABS_FUNC(bp); 9736 int vn; 9737 u32 val = 0; 9738 int rc = 0; 9739 9740 bnx2x_get_common_hwinfo(bp); 9741 9742 /* 9743 * initialize IGU parameters 9744 */ 9745 if (CHIP_IS_E1x(bp)) { 9746 bp->common.int_block = INT_BLOCK_HC; 9747 9748 bp->igu_dsb_id = DEF_SB_IGU_ID; 9749 bp->igu_base_sb = 0; 9750 } else { 9751 bp->common.int_block = INT_BLOCK_IGU; 9752 9753 /* do not allow device reset during IGU info preocessing */ 9754 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9755 9756 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 9757 9758 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9759 int tout = 5000; 9760 9761 BNX2X_DEV_INFO("FORCING Normal Mode\n"); 9762 9763 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 9764 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); 9765 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); 9766 9767 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9768 tout--; 9769 usleep_range(1000, 1000); 9770 } 9771 9772 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9773 dev_err(&bp->pdev->dev, 9774 "FORCING Normal Mode failed!!!\n"); 9775 return -EPERM; 9776 } 9777 } 9778 9779 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9780 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); 9781 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; 9782 } else 9783 BNX2X_DEV_INFO("IGU Normal Mode\n"); 9784 9785 bnx2x_get_igu_cam_info(bp); 9786 9787 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9788 } 9789 9790 /* 9791 * set base FW non-default (fast path) status block id, this value is 9792 * used to initialize the fw_sb_id saved on the fp/queue structure to 9793 * determine the id used by the FW. 9794 */ 9795 if (CHIP_IS_E1x(bp)) 9796 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); 9797 else /* 9798 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of 9799 * the same queue are indicated on the same IGU SB). So we prefer 9800 * FW and IGU SBs to be the same value. 9801 */ 9802 bp->base_fw_ndsb = bp->igu_base_sb; 9803 9804 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" 9805 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, 9806 bp->igu_sb_cnt, bp->base_fw_ndsb); 9807 9808 /* 9809 * Initialize MF configuration 9810 */ 9811 9812 bp->mf_ov = 0; 9813 bp->mf_mode = 0; 9814 vn = BP_VN(bp); 9815 9816 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 9817 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 9818 bp->common.shmem2_base, SHMEM2_RD(bp, size), 9819 (u32)offsetof(struct shmem2_region, mf_cfg_addr)); 9820 9821 if (SHMEM2_HAS(bp, mf_cfg_addr)) 9822 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); 9823 else 9824 bp->common.mf_cfg_base = bp->common.shmem_base + 9825 offsetof(struct shmem_region, func_mb) + 9826 E1H_FUNC_MAX * sizeof(struct drv_func_mb); 9827 /* 9828 * get mf configuration: 9829 * 1. existence of MF configuration 9830 * 2. MAC address must be legal (check only upper bytes) 9831 * for Switch-Independent mode; 9832 * OVLAN must be legal for Switch-Dependent mode 9833 * 3. SF_MODE configures specific MF mode 9834 */ 9835 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9836 /* get mf configuration */ 9837 val = SHMEM_RD(bp, 9838 dev_info.shared_feature_config.config); 9839 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; 9840 9841 switch (val) { 9842 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 9843 val = MF_CFG_RD(bp, func_mf_config[func]. 9844 mac_upper); 9845 /* check for legal mac (upper bytes)*/ 9846 if (val != 0xffff) { 9847 bp->mf_mode = MULTI_FUNCTION_SI; 9848 bp->mf_config[vn] = MF_CFG_RD(bp, 9849 func_mf_config[func].config); 9850 } else 9851 BNX2X_DEV_INFO("illegal MAC address " 9852 "for SI\n"); 9853 break; 9854 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 9855 /* get OV configuration */ 9856 val = MF_CFG_RD(bp, 9857 func_mf_config[FUNC_0].e1hov_tag); 9858 val &= FUNC_MF_CFG_E1HOV_TAG_MASK; 9859 9860 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9861 bp->mf_mode = MULTI_FUNCTION_SD; 9862 bp->mf_config[vn] = MF_CFG_RD(bp, 9863 func_mf_config[func].config); 9864 } else 9865 BNX2X_DEV_INFO("illegal OV for SD\n"); 9866 break; 9867 default: 9868 /* Unknown configuration: reset mf_config */ 9869 bp->mf_config[vn] = 0; 9870 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val); 9871 } 9872 } 9873 9874 BNX2X_DEV_INFO("%s function mode\n", 9875 IS_MF(bp) ? "multi" : "single"); 9876 9877 switch (bp->mf_mode) { 9878 case MULTI_FUNCTION_SD: 9879 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 9880 FUNC_MF_CFG_E1HOV_TAG_MASK; 9881 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9882 bp->mf_ov = val; 9883 bp->path_has_ovlan = true; 9884 9885 BNX2X_DEV_INFO("MF OV for func %d is %d " 9886 "(0x%04x)\n", func, bp->mf_ov, 9887 bp->mf_ov); 9888 } else { 9889 dev_err(&bp->pdev->dev, 9890 "No valid MF OV for func %d, " 9891 "aborting\n", func); 9892 return -EPERM; 9893 } 9894 break; 9895 case MULTI_FUNCTION_SI: 9896 BNX2X_DEV_INFO("func %d is in MF " 9897 "switch-independent mode\n", func); 9898 break; 9899 default: 9900 if (vn) { 9901 dev_err(&bp->pdev->dev, 9902 "VN %d is in a single function mode, " 9903 "aborting\n", vn); 9904 return -EPERM; 9905 } 9906 break; 9907 } 9908 9909 /* check if other port on the path needs ovlan: 9910 * Since MF configuration is shared between ports 9911 * Possible mixed modes are only 9912 * {SF, SI} {SF, SD} {SD, SF} {SI, SF} 9913 */ 9914 if (CHIP_MODE_IS_4_PORT(bp) && 9915 !bp->path_has_ovlan && 9916 !IS_MF(bp) && 9917 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9918 u8 other_port = !BP_PORT(bp); 9919 u8 other_func = BP_PATH(bp) + 2*other_port; 9920 val = MF_CFG_RD(bp, 9921 func_mf_config[other_func].e1hov_tag); 9922 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) 9923 bp->path_has_ovlan = true; 9924 } 9925 } 9926 9927 /* adjust igu_sb_cnt to MF for E1x */ 9928 if (CHIP_IS_E1x(bp) && IS_MF(bp)) 9929 bp->igu_sb_cnt /= E1HVN_MAX; 9930 9931 /* port info */ 9932 bnx2x_get_port_hwinfo(bp); 9933 9934 /* Get MAC addresses */ 9935 bnx2x_get_mac_hwinfo(bp); 9936 9937 bnx2x_get_cnic_info(bp); 9938 9939 /* Get current FW pulse sequence */ 9940 if (!BP_NOMCP(bp)) { 9941 int mb_idx = BP_FW_MB_IDX(bp); 9942 9943 bp->fw_drv_pulse_wr_seq = 9944 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) & 9945 DRV_PULSE_SEQ_MASK); 9946 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq); 9947 } 9948 9949 return rc; 9950} 9951 9952static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) 9953{ 9954 int cnt, i, block_end, rodi; 9955 char vpd_start[BNX2X_VPD_LEN+1]; 9956 char str_id_reg[VENDOR_ID_LEN+1]; 9957 char str_id_cap[VENDOR_ID_LEN+1]; 9958 char *vpd_data; 9959 char *vpd_extended_data = NULL; 9960 u8 len; 9961 9962 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); 9963 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); 9964 9965 if (cnt < BNX2X_VPD_LEN) 9966 goto out_not_found; 9967 9968 /* VPD RO tag should be first tag after identifier string, hence 9969 * we should be able to find it in first BNX2X_VPD_LEN chars 9970 */ 9971 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, 9972 PCI_VPD_LRDT_RO_DATA); 9973 if (i < 0) 9974 goto out_not_found; 9975 9976 block_end = i + PCI_VPD_LRDT_TAG_SIZE + 9977 pci_vpd_lrdt_size(&vpd_start[i]); 9978 9979 i += PCI_VPD_LRDT_TAG_SIZE; 9980 9981 if (block_end > BNX2X_VPD_LEN) { 9982 vpd_extended_data = kmalloc(block_end, GFP_KERNEL); 9983 if (vpd_extended_data == NULL) 9984 goto out_not_found; 9985 9986 /* read rest of vpd image into vpd_extended_data */ 9987 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); 9988 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, 9989 block_end - BNX2X_VPD_LEN, 9990 vpd_extended_data + BNX2X_VPD_LEN); 9991 if (cnt < (block_end - BNX2X_VPD_LEN)) 9992 goto out_not_found; 9993 vpd_data = vpd_extended_data; 9994 } else 9995 vpd_data = vpd_start; 9996 9997 /* now vpd_data holds full vpd content in both cases */ 9998 9999 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 10000 PCI_VPD_RO_KEYWORD_MFR_ID); 10001 if (rodi < 0) 10002 goto out_not_found; 10003 10004 len = pci_vpd_info_field_size(&vpd_data[rodi]); 10005 10006 if (len != VENDOR_ID_LEN) 10007 goto out_not_found; 10008 10009 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 10010 10011 /* vendor specific info */ 10012 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); 10013 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); 10014 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || 10015 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { 10016 10017 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 10018 PCI_VPD_RO_KEYWORD_VENDOR0); 10019 if (rodi >= 0) { 10020 len = pci_vpd_info_field_size(&vpd_data[rodi]); 10021 10022 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 10023 10024 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { 10025 memcpy(bp->fw_ver, &vpd_data[rodi], len); 10026 bp->fw_ver[len] = ' '; 10027 } 10028 } 10029 kfree(vpd_extended_data); 10030 return; 10031 } 10032out_not_found: 10033 kfree(vpd_extended_data); 10034 return; 10035} 10036 10037static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) 10038{ 10039 u32 flags = 0; 10040 10041 if (CHIP_REV_IS_FPGA(bp)) 10042 SET_FLAGS(flags, MODE_FPGA); 10043 else if (CHIP_REV_IS_EMUL(bp)) 10044 SET_FLAGS(flags, MODE_EMUL); 10045 else 10046 SET_FLAGS(flags, MODE_ASIC); 10047 10048 if (CHIP_MODE_IS_4_PORT(bp)) 10049 SET_FLAGS(flags, MODE_PORT4); 10050 else 10051 SET_FLAGS(flags, MODE_PORT2); 10052 10053 if (CHIP_IS_E2(bp)) 10054 SET_FLAGS(flags, MODE_E2); 10055 else if (CHIP_IS_E3(bp)) { 10056 SET_FLAGS(flags, MODE_E3); 10057 if (CHIP_REV(bp) == CHIP_REV_Ax) 10058 SET_FLAGS(flags, MODE_E3_A0); 10059 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ 10060 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 10061 } 10062 10063 if (IS_MF(bp)) { 10064 SET_FLAGS(flags, MODE_MF); 10065 switch (bp->mf_mode) { 10066 case MULTI_FUNCTION_SD: 10067 SET_FLAGS(flags, MODE_MF_SD); 10068 break; 10069 case MULTI_FUNCTION_SI: 10070 SET_FLAGS(flags, MODE_MF_SI); 10071 break; 10072 } 10073 } else 10074 SET_FLAGS(flags, MODE_SF); 10075 10076#if defined(__LITTLE_ENDIAN) 10077 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 10078#else /*(__BIG_ENDIAN)*/ 10079 SET_FLAGS(flags, MODE_BIG_ENDIAN); 10080#endif 10081 INIT_MODE_FLAGS(bp) = flags; 10082} 10083 10084static int __devinit bnx2x_init_bp(struct bnx2x *bp) 10085{ 10086 int func; 10087 int timer_interval; 10088 int rc; 10089 10090 mutex_init(&bp->port.phy_mutex); 10091 mutex_init(&bp->fw_mb_mutex); 10092 spin_lock_init(&bp->stats_lock); 10093#ifdef BCM_CNIC 10094 mutex_init(&bp->cnic_mutex); 10095#endif 10096 10097 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); 10098 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); 10099 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); 10100 rc = bnx2x_get_hwinfo(bp); 10101 if (rc) 10102 return rc; 10103 10104 bnx2x_set_modes_bitmap(bp); 10105 10106 rc = bnx2x_alloc_mem_bp(bp); 10107 if (rc) 10108 return rc; 10109 10110 bnx2x_read_fwinfo(bp); 10111 10112 func = BP_FUNC(bp); 10113 10114 /* need to reset chip if undi was active */ 10115 if (!BP_NOMCP(bp)) 10116 bnx2x_undi_unload(bp); 10117 10118 /* init fw_seq after undi_unload! */ 10119 if (!BP_NOMCP(bp)) { 10120 bp->fw_seq = 10121 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 10122 DRV_MSG_SEQ_NUMBER_MASK); 10123 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 10124 } 10125 10126 if (CHIP_REV_IS_FPGA(bp)) 10127 dev_err(&bp->pdev->dev, "FPGA detected\n"); 10128 10129 if (BP_NOMCP(bp) && (func == 0)) 10130 dev_err(&bp->pdev->dev, "MCP disabled, " 10131 "must load devices in order!\n"); 10132 10133 bp->multi_mode = multi_mode; 10134 10135 bp->disable_tpa = disable_tpa; 10136 10137#ifdef BCM_CNIC 10138 bp->disable_tpa |= IS_MF_ISCSI_SD(bp); 10139#endif 10140 10141 /* Set TPA flags */ 10142 if (bp->disable_tpa) { 10143 bp->flags &= ~TPA_ENABLE_FLAG; 10144 bp->dev->features &= ~NETIF_F_LRO; 10145 } else { 10146 bp->flags |= TPA_ENABLE_FLAG; 10147 bp->dev->features |= NETIF_F_LRO; 10148 } 10149 10150 if (CHIP_IS_E1(bp)) 10151 bp->dropless_fc = 0; 10152 else 10153 bp->dropless_fc = dropless_fc; 10154 10155 bp->mrrs = mrrs; 10156 10157 bp->tx_ring_size = MAX_TX_AVAIL; 10158 10159 /* make sure that the numbers are in the right granularity */ 10160 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; 10161 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; 10162 10163 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ); 10164 bp->current_interval = (poll ? poll : timer_interval); 10165 10166 init_timer(&bp->timer); 10167 bp->timer.expires = jiffies + bp->current_interval; 10168 bp->timer.data = (unsigned long) bp; 10169 bp->timer.function = bnx2x_timer; 10170 10171 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); 10172 bnx2x_dcbx_init_params(bp); 10173 10174#ifdef BCM_CNIC 10175 if (CHIP_IS_E1x(bp)) 10176 bp->cnic_base_cl_id = FP_SB_MAX_E1x; 10177 else 10178 bp->cnic_base_cl_id = FP_SB_MAX_E2; 10179#endif 10180 10181 /* multiple tx priority */ 10182 if (CHIP_IS_E1x(bp)) 10183 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; 10184 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) 10185 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; 10186 if (CHIP_IS_E3B0(bp)) 10187 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; 10188 10189 return rc; 10190} 10191 10192 10193/**************************************************************************** 10194* General service functions 10195****************************************************************************/ 10196 10197/* 10198 * net_device service functions 10199 */ 10200 10201/* called with rtnl_lock */ 10202static int bnx2x_open(struct net_device *dev) 10203{ 10204 struct bnx2x *bp = netdev_priv(dev); 10205 bool global = false; 10206 int other_engine = BP_PATH(bp) ? 0 : 1; 10207 bool other_load_status, load_status; 10208 10209 netif_carrier_off(dev); 10210 10211 bnx2x_set_power_state(bp, PCI_D0); 10212 10213 other_load_status = bnx2x_get_load_status(bp, other_engine); 10214 load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); 10215 10216 /* 10217 * If parity had happen during the unload, then attentions 10218 * and/or RECOVERY_IN_PROGRES may still be set. In this case we 10219 * want the first function loaded on the current engine to 10220 * complete the recovery. 10221 */ 10222 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 10223 bnx2x_chk_parity_attn(bp, &global, true)) 10224 do { 10225 /* 10226 * If there are attentions and they are in a global 10227 * blocks, set the GLOBAL_RESET bit regardless whether 10228 * it will be this function that will complete the 10229 * recovery or not. 10230 */ 10231 if (global) 10232 bnx2x_set_reset_global(bp); 10233 10234 /* 10235 * Only the first function on the current engine should 10236 * try to recover in open. In case of attentions in 10237 * global blocks only the first in the chip should try 10238 * to recover. 10239 */ 10240 if ((!load_status && 10241 (!global || !other_load_status)) && 10242 bnx2x_trylock_leader_lock(bp) && 10243 !bnx2x_leader_reset(bp)) { 10244 netdev_info(bp->dev, "Recovered in open\n"); 10245 break; 10246 } 10247 10248 /* recovery has failed... */ 10249 bnx2x_set_power_state(bp, PCI_D3hot); 10250 bp->recovery_state = BNX2X_RECOVERY_FAILED; 10251 10252 netdev_err(bp->dev, "Recovery flow hasn't been properly" 10253 " completed yet. Try again later. If u still see this" 10254 " message after a few retries then power cycle is" 10255 " required.\n"); 10256 10257 return -EAGAIN; 10258 } while (0); 10259 10260 bp->recovery_state = BNX2X_RECOVERY_DONE; 10261 return bnx2x_nic_load(bp, LOAD_OPEN); 10262} 10263 10264/* called with rtnl_lock */ 10265int bnx2x_close(struct net_device *dev) 10266{ 10267 struct bnx2x *bp = netdev_priv(dev); 10268 10269 /* Unload the driver, release IRQs */ 10270 bnx2x_nic_unload(bp, UNLOAD_CLOSE); 10271 10272 /* Power off */ 10273 bnx2x_set_power_state(bp, PCI_D3hot); 10274 10275 return 0; 10276} 10277 10278static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp, 10279 struct bnx2x_mcast_ramrod_params *p) 10280{ 10281 int mc_count = netdev_mc_count(bp->dev); 10282 struct bnx2x_mcast_list_elem *mc_mac = 10283 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); 10284 struct netdev_hw_addr *ha; 10285 10286 if (!mc_mac) 10287 return -ENOMEM; 10288 10289 INIT_LIST_HEAD(&p->mcast_list); 10290 10291 netdev_for_each_mc_addr(ha, bp->dev) { 10292 mc_mac->mac = bnx2x_mc_addr(ha); 10293 list_add_tail(&mc_mac->link, &p->mcast_list); 10294 mc_mac++; 10295 } 10296 10297 p->mcast_list_len = mc_count; 10298 10299 return 0; 10300} 10301 10302static inline void bnx2x_free_mcast_macs_list( 10303 struct bnx2x_mcast_ramrod_params *p) 10304{ 10305 struct bnx2x_mcast_list_elem *mc_mac = 10306 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, 10307 link); 10308 10309 WARN_ON(!mc_mac); 10310 kfree(mc_mac); 10311} 10312 10313/** 10314 * bnx2x_set_uc_list - configure a new unicast MACs list. 10315 * 10316 * @bp: driver handle 10317 * 10318 * We will use zero (0) as a MAC type for these MACs. 10319 */ 10320static inline int bnx2x_set_uc_list(struct bnx2x *bp) 10321{ 10322 int rc; 10323 struct net_device *dev = bp->dev; 10324 struct netdev_hw_addr *ha; 10325 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj; 10326 unsigned long ramrod_flags = 0; 10327 10328 /* First schedule a cleanup up of old configuration */ 10329 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); 10330 if (rc < 0) { 10331 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); 10332 return rc; 10333 } 10334 10335 netdev_for_each_uc_addr(ha, dev) { 10336 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, 10337 BNX2X_UC_LIST_MAC, &ramrod_flags); 10338 if (rc < 0) { 10339 BNX2X_ERR("Failed to schedule ADD operations: %d\n", 10340 rc); 10341 return rc; 10342 } 10343 } 10344 10345 /* Execute the pending commands */ 10346 __set_bit(RAMROD_CONT, &ramrod_flags); 10347 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, 10348 BNX2X_UC_LIST_MAC, &ramrod_flags); 10349} 10350 10351static inline int bnx2x_set_mc_list(struct bnx2x *bp) 10352{ 10353 struct net_device *dev = bp->dev; 10354 struct bnx2x_mcast_ramrod_params rparam = {0}; 10355 int rc = 0; 10356 10357 rparam.mcast_obj = &bp->mcast_obj; 10358 10359 /* first, clear all configured multicast MACs */ 10360 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 10361 if (rc < 0) { 10362 BNX2X_ERR("Failed to clear multicast " 10363 "configuration: %d\n", rc); 10364 return rc; 10365 } 10366 10367 /* then, configure a new MACs list */ 10368 if (netdev_mc_count(dev)) { 10369 rc = bnx2x_init_mcast_macs_list(bp, &rparam); 10370 if (rc) { 10371 BNX2X_ERR("Failed to create multicast MACs " 10372 "list: %d\n", rc); 10373 return rc; 10374 } 10375 10376 /* Now add the new MACs */ 10377 rc = bnx2x_config_mcast(bp, &rparam, 10378 BNX2X_MCAST_CMD_ADD); 10379 if (rc < 0) 10380 BNX2X_ERR("Failed to set a new multicast " 10381 "configuration: %d\n", rc); 10382 10383 bnx2x_free_mcast_macs_list(&rparam); 10384 } 10385 10386 return rc; 10387} 10388 10389 10390/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ 10391void bnx2x_set_rx_mode(struct net_device *dev) 10392{ 10393 struct bnx2x *bp = netdev_priv(dev); 10394 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 10395 10396 if (bp->state != BNX2X_STATE_OPEN) { 10397 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 10398 return; 10399 } 10400 10401 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); 10402 10403 if (dev->flags & IFF_PROMISC) 10404 rx_mode = BNX2X_RX_MODE_PROMISC; 10405 else if ((dev->flags & IFF_ALLMULTI) || 10406 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && 10407 CHIP_IS_E1(bp))) 10408 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10409 else { 10410 /* some multicasts */ 10411 if (bnx2x_set_mc_list(bp) < 0) 10412 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10413 10414 if (bnx2x_set_uc_list(bp) < 0) 10415 rx_mode = BNX2X_RX_MODE_PROMISC; 10416 } 10417 10418 bp->rx_mode = rx_mode; 10419#ifdef BCM_CNIC 10420 /* handle ISCSI SD mode */ 10421 if (IS_MF_ISCSI_SD(bp)) 10422 bp->rx_mode = BNX2X_RX_MODE_NONE; 10423#endif 10424 10425 /* Schedule the rx_mode command */ 10426 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { 10427 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 10428 return; 10429 } 10430 10431 bnx2x_set_storm_rx_mode(bp); 10432} 10433 10434/* called with rtnl_lock */ 10435static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 10436 int devad, u16 addr) 10437{ 10438 struct bnx2x *bp = netdev_priv(netdev); 10439 u16 value; 10440 int rc; 10441 10442 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 10443 prtad, devad, addr); 10444 10445 /* The HW expects different devad if CL22 is used */ 10446 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10447 10448 bnx2x_acquire_phy_lock(bp); 10449 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); 10450 bnx2x_release_phy_lock(bp); 10451 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 10452 10453 if (!rc) 10454 rc = value; 10455 return rc; 10456} 10457 10458/* called with rtnl_lock */ 10459static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, 10460 u16 addr, u16 value) 10461{ 10462 struct bnx2x *bp = netdev_priv(netdev); 10463 int rc; 10464 10465 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x," 10466 " value 0x%x\n", prtad, devad, addr, value); 10467 10468 /* The HW expects different devad if CL22 is used */ 10469 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10470 10471 bnx2x_acquire_phy_lock(bp); 10472 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); 10473 bnx2x_release_phy_lock(bp); 10474 return rc; 10475} 10476 10477/* called with rtnl_lock */ 10478static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 10479{ 10480 struct bnx2x *bp = netdev_priv(dev); 10481 struct mii_ioctl_data *mdio = if_mii(ifr); 10482 10483 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", 10484 mdio->phy_id, mdio->reg_num, mdio->val_in); 10485 10486 if (!netif_running(dev)) 10487 return -EAGAIN; 10488 10489 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); 10490} 10491 10492#ifdef CONFIG_NET_POLL_CONTROLLER 10493static void poll_bnx2x(struct net_device *dev) 10494{ 10495 struct bnx2x *bp = netdev_priv(dev); 10496 10497 disable_irq(bp->pdev->irq); 10498 bnx2x_interrupt(bp->pdev->irq, dev); 10499 enable_irq(bp->pdev->irq); 10500} 10501#endif 10502 10503static int bnx2x_validate_addr(struct net_device *dev) 10504{ 10505 struct bnx2x *bp = netdev_priv(dev); 10506 10507 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) 10508 return -EADDRNOTAVAIL; 10509 return 0; 10510} 10511 10512static const struct net_device_ops bnx2x_netdev_ops = { 10513 .ndo_open = bnx2x_open, 10514 .ndo_stop = bnx2x_close, 10515 .ndo_start_xmit = bnx2x_start_xmit, 10516 .ndo_select_queue = bnx2x_select_queue, 10517 .ndo_set_rx_mode = bnx2x_set_rx_mode, 10518 .ndo_set_mac_address = bnx2x_change_mac_addr, 10519 .ndo_validate_addr = bnx2x_validate_addr, 10520 .ndo_do_ioctl = bnx2x_ioctl, 10521 .ndo_change_mtu = bnx2x_change_mtu, 10522 .ndo_fix_features = bnx2x_fix_features, 10523 .ndo_set_features = bnx2x_set_features, 10524 .ndo_tx_timeout = bnx2x_tx_timeout, 10525#ifdef CONFIG_NET_POLL_CONTROLLER 10526 .ndo_poll_controller = poll_bnx2x, 10527#endif 10528 .ndo_setup_tc = bnx2x_setup_tc, 10529 10530#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) 10531 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, 10532#endif 10533}; 10534 10535static inline int bnx2x_set_coherency_mask(struct bnx2x *bp) 10536{ 10537 struct device *dev = &bp->pdev->dev; 10538 10539 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 10540 bp->flags |= USING_DAC_FLAG; 10541 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 10542 dev_err(dev, "dma_set_coherent_mask failed, " 10543 "aborting\n"); 10544 return -EIO; 10545 } 10546 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 10547 dev_err(dev, "System does not support DMA, aborting\n"); 10548 return -EIO; 10549 } 10550 10551 return 0; 10552} 10553 10554static int __devinit bnx2x_init_dev(struct pci_dev *pdev, 10555 struct net_device *dev, 10556 unsigned long board_type) 10557{ 10558 struct bnx2x *bp; 10559 int rc; 10560 u32 pci_cfg_dword; 10561 bool chip_is_e1x = (board_type == BCM57710 || 10562 board_type == BCM57711 || 10563 board_type == BCM57711E); 10564 10565 SET_NETDEV_DEV(dev, &pdev->dev); 10566 bp = netdev_priv(dev); 10567 10568 bp->dev = dev; 10569 bp->pdev = pdev; 10570 bp->flags = 0; 10571 10572 rc = pci_enable_device(pdev); 10573 if (rc) { 10574 dev_err(&bp->pdev->dev, 10575 "Cannot enable PCI device, aborting\n"); 10576 goto err_out; 10577 } 10578 10579 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 10580 dev_err(&bp->pdev->dev, 10581 "Cannot find PCI device base address, aborting\n"); 10582 rc = -ENODEV; 10583 goto err_out_disable; 10584 } 10585 10586 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 10587 dev_err(&bp->pdev->dev, "Cannot find second PCI device" 10588 " base address, aborting\n"); 10589 rc = -ENODEV; 10590 goto err_out_disable; 10591 } 10592 10593 if (atomic_read(&pdev->enable_cnt) == 1) { 10594 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 10595 if (rc) { 10596 dev_err(&bp->pdev->dev, 10597 "Cannot obtain PCI resources, aborting\n"); 10598 goto err_out_disable; 10599 } 10600 10601 pci_set_master(pdev); 10602 pci_save_state(pdev); 10603 } 10604 10605 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 10606 if (bp->pm_cap == 0) { 10607 dev_err(&bp->pdev->dev, 10608 "Cannot find power management capability, aborting\n"); 10609 rc = -EIO; 10610 goto err_out_release; 10611 } 10612 10613 if (!pci_is_pcie(pdev)) { 10614 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 10615 rc = -EIO; 10616 goto err_out_release; 10617 } 10618 10619 rc = bnx2x_set_coherency_mask(bp); 10620 if (rc) 10621 goto err_out_release; 10622 10623 dev->mem_start = pci_resource_start(pdev, 0); 10624 dev->base_addr = dev->mem_start; 10625 dev->mem_end = pci_resource_end(pdev, 0); 10626 10627 dev->irq = pdev->irq; 10628 10629 bp->regview = pci_ioremap_bar(pdev, 0); 10630 if (!bp->regview) { 10631 dev_err(&bp->pdev->dev, 10632 "Cannot map register space, aborting\n"); 10633 rc = -ENOMEM; 10634 goto err_out_release; 10635 } 10636 10637 /* In E1/E1H use pci device function given by kernel. 10638 * In E2/E3 read physical function from ME register since these chips 10639 * support Physical Device Assignment where kernel BDF maybe arbitrary 10640 * (depending on hypervisor). 10641 */ 10642 if (chip_is_e1x) 10643 bp->pf_num = PCI_FUNC(pdev->devfn); 10644 else {/* chip is E2/3*/ 10645 pci_read_config_dword(bp->pdev, 10646 PCICFG_ME_REGISTER, &pci_cfg_dword); 10647 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> 10648 ME_REG_ABS_PF_NUM_SHIFT); 10649 } 10650 DP(BNX2X_MSG_SP, "me reg PF num: %d\n", bp->pf_num); 10651 10652 bnx2x_set_power_state(bp, PCI_D0); 10653 10654 /* clean indirect addresses */ 10655 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 10656 PCICFG_VENDOR_ID_OFFSET); 10657 /* 10658 * Clean the following indirect addresses for all functions since it 10659 * is not used by the driver. 10660 */ 10661 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); 10662 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); 10663 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 10664 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 10665 10666 if (chip_is_e1x) { 10667 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 10668 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 10669 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 10670 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); 10671 } 10672 10673 /* 10674 * Enable internal target-read (in case we are probed after PF FLR). 10675 * Must be done prior to any BAR read access. Only for 57712 and up 10676 */ 10677 if (!chip_is_e1x) 10678 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 10679 10680 /* Reset the load counter */ 10681 bnx2x_clear_load_status(bp); 10682 10683 dev->watchdog_timeo = TX_TIMEOUT; 10684 10685 dev->netdev_ops = &bnx2x_netdev_ops; 10686 bnx2x_set_ethtool_ops(dev); 10687 10688 dev->priv_flags |= IFF_UNICAST_FLT; 10689 10690 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10691 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_LRO | 10692 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; 10693 10694 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10695 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 10696 10697 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; 10698 if (bp->flags & USING_DAC_FLAG) 10699 dev->features |= NETIF_F_HIGHDMA; 10700 10701 /* Add Loopback capability to the device */ 10702 dev->hw_features |= NETIF_F_LOOPBACK; 10703 10704#ifdef BCM_DCBNL 10705 dev->dcbnl_ops = &bnx2x_dcbnl_ops; 10706#endif 10707 10708 /* get_port_hwinfo() will set prtad and mmds properly */ 10709 bp->mdio.prtad = MDIO_PRTAD_NONE; 10710 bp->mdio.mmds = 0; 10711 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10712 bp->mdio.dev = dev; 10713 bp->mdio.mdio_read = bnx2x_mdio_read; 10714 bp->mdio.mdio_write = bnx2x_mdio_write; 10715 10716 return 0; 10717 10718err_out_release: 10719 if (atomic_read(&pdev->enable_cnt) == 1) 10720 pci_release_regions(pdev); 10721 10722err_out_disable: 10723 pci_disable_device(pdev); 10724 pci_set_drvdata(pdev, NULL); 10725 10726err_out: 10727 return rc; 10728} 10729 10730static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, 10731 int *width, int *speed) 10732{ 10733 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); 10734 10735 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; 10736 10737 /* return value of 1=2.5GHz 2=5GHz */ 10738 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; 10739} 10740 10741static int bnx2x_check_firmware(struct bnx2x *bp) 10742{ 10743 const struct firmware *firmware = bp->firmware; 10744 struct bnx2x_fw_file_hdr *fw_hdr; 10745 struct bnx2x_fw_file_section *sections; 10746 u32 offset, len, num_ops; 10747 u16 *ops_offsets; 10748 int i; 10749 const u8 *fw_ver; 10750 10751 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) 10752 return -EINVAL; 10753 10754 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 10755 sections = (struct bnx2x_fw_file_section *)fw_hdr; 10756 10757 /* Make sure none of the offsets and sizes make us read beyond 10758 * the end of the firmware data */ 10759 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { 10760 offset = be32_to_cpu(sections[i].offset); 10761 len = be32_to_cpu(sections[i].len); 10762 if (offset + len > firmware->size) { 10763 dev_err(&bp->pdev->dev, 10764 "Section %d length is out of bounds\n", i); 10765 return -EINVAL; 10766 } 10767 } 10768 10769 /* Likewise for the init_ops offsets */ 10770 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); 10771 ops_offsets = (u16 *)(firmware->data + offset); 10772 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); 10773 10774 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 10775 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 10776 dev_err(&bp->pdev->dev, 10777 "Section offset %d is out of bounds\n", i); 10778 return -EINVAL; 10779 } 10780 } 10781 10782 /* Check FW version */ 10783 offset = be32_to_cpu(fw_hdr->fw_version.offset); 10784 fw_ver = firmware->data + offset; 10785 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || 10786 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || 10787 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || 10788 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { 10789 dev_err(&bp->pdev->dev, 10790 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 10791 fw_ver[0], fw_ver[1], fw_ver[2], 10792 fw_ver[3], BCM_5710_FW_MAJOR_VERSION, 10793 BCM_5710_FW_MINOR_VERSION, 10794 BCM_5710_FW_REVISION_VERSION, 10795 BCM_5710_FW_ENGINEERING_VERSION); 10796 return -EINVAL; 10797 } 10798 10799 return 0; 10800} 10801 10802static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10803{ 10804 const __be32 *source = (const __be32 *)_source; 10805 u32 *target = (u32 *)_target; 10806 u32 i; 10807 10808 for (i = 0; i < n/4; i++) 10809 target[i] = be32_to_cpu(source[i]); 10810} 10811 10812/* 10813 Ops array is stored in the following format: 10814 {op(8bit), offset(24bit, big endian), data(32bit, big endian)} 10815 */ 10816static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) 10817{ 10818 const __be32 *source = (const __be32 *)_source; 10819 struct raw_op *target = (struct raw_op *)_target; 10820 u32 i, j, tmp; 10821 10822 for (i = 0, j = 0; i < n/8; i++, j += 2) { 10823 tmp = be32_to_cpu(source[j]); 10824 target[i].op = (tmp >> 24) & 0xff; 10825 target[i].offset = tmp & 0xffffff; 10826 target[i].raw_data = be32_to_cpu(source[j + 1]); 10827 } 10828} 10829 10830/** 10831 * IRO array is stored in the following format: 10832 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } 10833 */ 10834static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) 10835{ 10836 const __be32 *source = (const __be32 *)_source; 10837 struct iro *target = (struct iro *)_target; 10838 u32 i, j, tmp; 10839 10840 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { 10841 target[i].base = be32_to_cpu(source[j]); 10842 j++; 10843 tmp = be32_to_cpu(source[j]); 10844 target[i].m1 = (tmp >> 16) & 0xffff; 10845 target[i].m2 = tmp & 0xffff; 10846 j++; 10847 tmp = be32_to_cpu(source[j]); 10848 target[i].m3 = (tmp >> 16) & 0xffff; 10849 target[i].size = tmp & 0xffff; 10850 j++; 10851 } 10852} 10853 10854static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10855{ 10856 const __be16 *source = (const __be16 *)_source; 10857 u16 *target = (u16 *)_target; 10858 u32 i; 10859 10860 for (i = 0; i < n/2; i++) 10861 target[i] = be16_to_cpu(source[i]); 10862} 10863 10864#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ 10865do { \ 10866 u32 len = be32_to_cpu(fw_hdr->arr.len); \ 10867 bp->arr = kmalloc(len, GFP_KERNEL); \ 10868 if (!bp->arr) { \ 10869 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \ 10870 goto lbl; \ 10871 } \ 10872 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ 10873 (u8 *)bp->arr, len); \ 10874} while (0) 10875 10876int bnx2x_init_firmware(struct bnx2x *bp) 10877{ 10878 struct bnx2x_fw_file_hdr *fw_hdr; 10879 int rc; 10880 10881 10882 if (!bp->firmware) { 10883 const char *fw_file_name; 10884 10885 if (CHIP_IS_E1(bp)) 10886 fw_file_name = FW_FILE_NAME_E1; 10887 else if (CHIP_IS_E1H(bp)) 10888 fw_file_name = FW_FILE_NAME_E1H; 10889 else if (!CHIP_IS_E1x(bp)) 10890 fw_file_name = FW_FILE_NAME_E2; 10891 else { 10892 BNX2X_ERR("Unsupported chip revision\n"); 10893 return -EINVAL; 10894 } 10895 BNX2X_DEV_INFO("Loading %s\n", fw_file_name); 10896 10897 rc = request_firmware(&bp->firmware, fw_file_name, 10898 &bp->pdev->dev); 10899 if (rc) { 10900 BNX2X_ERR("Can't load firmware file %s\n", 10901 fw_file_name); 10902 goto request_firmware_exit; 10903 } 10904 10905 rc = bnx2x_check_firmware(bp); 10906 if (rc) { 10907 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); 10908 goto request_firmware_exit; 10909 } 10910 } 10911 10912 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; 10913 10914 /* Initialize the pointers to the init arrays */ 10915 /* Blob */ 10916 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); 10917 10918 /* Opcodes */ 10919 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); 10920 10921 /* Offsets */ 10922 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, 10923 be16_to_cpu_n); 10924 10925 /* STORMs firmware */ 10926 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10927 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); 10928 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + 10929 be32_to_cpu(fw_hdr->tsem_pram_data.offset); 10930 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10931 be32_to_cpu(fw_hdr->usem_int_table_data.offset); 10932 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + 10933 be32_to_cpu(fw_hdr->usem_pram_data.offset); 10934 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10935 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); 10936 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + 10937 be32_to_cpu(fw_hdr->xsem_pram_data.offset); 10938 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10939 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 10940 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 10941 be32_to_cpu(fw_hdr->csem_pram_data.offset); 10942 /* IRO */ 10943 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); 10944 10945 return 0; 10946 10947iro_alloc_err: 10948 kfree(bp->init_ops_offsets); 10949init_offsets_alloc_err: 10950 kfree(bp->init_ops); 10951init_ops_alloc_err: 10952 kfree(bp->init_data); 10953request_firmware_exit: 10954 release_firmware(bp->firmware); 10955 10956 return rc; 10957} 10958 10959static void bnx2x_release_firmware(struct bnx2x *bp) 10960{ 10961 kfree(bp->init_ops_offsets); 10962 kfree(bp->init_ops); 10963 kfree(bp->init_data); 10964 release_firmware(bp->firmware); 10965 bp->firmware = NULL; 10966} 10967 10968 10969static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { 10970 .init_hw_cmn_chip = bnx2x_init_hw_common_chip, 10971 .init_hw_cmn = bnx2x_init_hw_common, 10972 .init_hw_port = bnx2x_init_hw_port, 10973 .init_hw_func = bnx2x_init_hw_func, 10974 10975 .reset_hw_cmn = bnx2x_reset_common, 10976 .reset_hw_port = bnx2x_reset_port, 10977 .reset_hw_func = bnx2x_reset_func, 10978 10979 .gunzip_init = bnx2x_gunzip_init, 10980 .gunzip_end = bnx2x_gunzip_end, 10981 10982 .init_fw = bnx2x_init_firmware, 10983 .release_fw = bnx2x_release_firmware, 10984}; 10985 10986void bnx2x__init_func_obj(struct bnx2x *bp) 10987{ 10988 /* Prepare DMAE related driver resources */ 10989 bnx2x_setup_dmae(bp); 10990 10991 bnx2x_init_func_obj(bp, &bp->func_obj, 10992 bnx2x_sp(bp, func_rdata), 10993 bnx2x_sp_mapping(bp, func_rdata), 10994 &bnx2x_func_sp_drv); 10995} 10996 10997/* must be called after sriov-enable */ 10998static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp) 10999{ 11000 int cid_count = BNX2X_L2_CID_COUNT(bp); 11001 11002#ifdef BCM_CNIC 11003 cid_count += CNIC_CID_MAX; 11004#endif 11005 return roundup(cid_count, QM_CID_ROUND); 11006} 11007 11008/** 11009 * bnx2x_get_num_none_def_sbs - return the number of none default SBs 11010 * 11011 * @dev: pci device 11012 * 11013 */ 11014static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) 11015{ 11016 int pos; 11017 u16 control; 11018 11019 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 11020 11021 /* 11022 * If MSI-X is not supported - return number of SBs needed to support 11023 * one fast path queue: one FP queue + SB for CNIC 11024 */ 11025 if (!pos) 11026 return 1 + CNIC_PRESENT; 11027 11028 /* 11029 * The value in the PCI configuration space is the index of the last 11030 * entry, namely one less than the actual size of the table, which is 11031 * exactly what we want to return from this function: number of all SBs 11032 * without the default SB. 11033 */ 11034 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 11035 return control & PCI_MSIX_FLAGS_QSIZE; 11036} 11037 11038static int __devinit bnx2x_init_one(struct pci_dev *pdev, 11039 const struct pci_device_id *ent) 11040{ 11041 struct net_device *dev = NULL; 11042 struct bnx2x *bp; 11043 int pcie_width, pcie_speed; 11044 int rc, max_non_def_sbs; 11045 int rx_count, tx_count, rss_count; 11046 /* 11047 * An estimated maximum supported CoS number according to the chip 11048 * version. 11049 * We will try to roughly estimate the maximum number of CoSes this chip 11050 * may support in order to minimize the memory allocated for Tx 11051 * netdev_queue's. This number will be accurately calculated during the 11052 * initialization of bp->max_cos based on the chip versions AND chip 11053 * revision in the bnx2x_init_bp(). 11054 */ 11055 u8 max_cos_est = 0; 11056 11057 switch (ent->driver_data) { 11058 case BCM57710: 11059 case BCM57711: 11060 case BCM57711E: 11061 max_cos_est = BNX2X_MULTI_TX_COS_E1X; 11062 break; 11063 11064 case BCM57712: 11065 case BCM57712_MF: 11066 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; 11067 break; 11068 11069 case BCM57800: 11070 case BCM57800_MF: 11071 case BCM57810: 11072 case BCM57810_MF: 11073 case BCM57840: 11074 case BCM57840_MF: 11075 max_cos_est = BNX2X_MULTI_TX_COS_E3B0; 11076 break; 11077 11078 default: 11079 pr_err("Unknown board_type (%ld), aborting\n", 11080 ent->driver_data); 11081 return -ENODEV; 11082 } 11083 11084 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); 11085 11086 /* !!! FIXME !!! 11087 * Do not allow the maximum SB count to grow above 16 11088 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48. 11089 * We will use the FP_SB_MAX_E1x macro for this matter. 11090 */ 11091 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs); 11092 11093 WARN_ON(!max_non_def_sbs); 11094 11095 /* Maximum number of RSS queues: one IGU SB goes to CNIC */ 11096 rss_count = max_non_def_sbs - CNIC_PRESENT; 11097 11098 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ 11099 rx_count = rss_count + FCOE_PRESENT; 11100 11101 /* 11102 * Maximum number of netdev Tx queues: 11103 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 11104 */ 11105 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT; 11106 11107 /* dev zeroed in init_etherdev */ 11108 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); 11109 if (!dev) { 11110 dev_err(&pdev->dev, "Cannot allocate net device\n"); 11111 return -ENOMEM; 11112 } 11113 11114 bp = netdev_priv(dev); 11115 11116 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n", 11117 tx_count, rx_count); 11118 11119 bp->igu_sb_cnt = max_non_def_sbs; 11120 bp->msg_enable = debug; 11121 pci_set_drvdata(pdev, dev); 11122 11123 rc = bnx2x_init_dev(pdev, dev, ent->driver_data); 11124 if (rc < 0) { 11125 free_netdev(dev); 11126 return rc; 11127 } 11128 11129 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs); 11130 11131 rc = bnx2x_init_bp(bp); 11132 if (rc) 11133 goto init_one_exit; 11134 11135 /* 11136 * Map doorbels here as we need the real value of bp->max_cos which 11137 * is initialized in bnx2x_init_bp(). 11138 */ 11139 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), 11140 min_t(u64, BNX2X_DB_SIZE(bp), 11141 pci_resource_len(pdev, 2))); 11142 if (!bp->doorbells) { 11143 dev_err(&bp->pdev->dev, 11144 "Cannot map doorbell space, aborting\n"); 11145 rc = -ENOMEM; 11146 goto init_one_exit; 11147 } 11148 11149 /* calc qm_cid_count */ 11150 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); 11151 11152#ifdef BCM_CNIC 11153 /* disable FCOE L2 queue for E1x */ 11154 if (CHIP_IS_E1x(bp)) 11155 bp->flags |= NO_FCOE_FLAG; 11156 11157#endif 11158 11159 /* Configure interrupt mode: try to enable MSI-X/MSI if 11160 * needed, set bp->num_queues appropriately. 11161 */ 11162 bnx2x_set_int_mode(bp); 11163 11164 /* Add all NAPI objects */ 11165 bnx2x_add_all_napi(bp); 11166 11167 rc = register_netdev(dev); 11168 if (rc) { 11169 dev_err(&pdev->dev, "Cannot register net device\n"); 11170 goto init_one_exit; 11171 } 11172 11173#ifdef BCM_CNIC 11174 if (!NO_FCOE(bp)) { 11175 /* Add storage MAC address */ 11176 rtnl_lock(); 11177 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11178 rtnl_unlock(); 11179 } 11180#endif 11181 11182 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); 11183 11184 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", 11185 board_info[ent->driver_data].name, 11186 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 11187 pcie_width, 11188 ((!CHIP_IS_E2(bp) && pcie_speed == 2) || 11189 (CHIP_IS_E2(bp) && pcie_speed == 1)) ? 11190 "5GHz (Gen2)" : "2.5GHz", 11191 dev->base_addr, bp->pdev->irq, dev->dev_addr); 11192 11193 return 0; 11194 11195init_one_exit: 11196 if (bp->regview) 11197 iounmap(bp->regview); 11198 11199 if (bp->doorbells) 11200 iounmap(bp->doorbells); 11201 11202 free_netdev(dev); 11203 11204 if (atomic_read(&pdev->enable_cnt) == 1) 11205 pci_release_regions(pdev); 11206 11207 pci_disable_device(pdev); 11208 pci_set_drvdata(pdev, NULL); 11209 11210 return rc; 11211} 11212 11213static void __devexit bnx2x_remove_one(struct pci_dev *pdev) 11214{ 11215 struct net_device *dev = pci_get_drvdata(pdev); 11216 struct bnx2x *bp; 11217 11218 if (!dev) { 11219 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); 11220 return; 11221 } 11222 bp = netdev_priv(dev); 11223 11224#ifdef BCM_CNIC 11225 /* Delete storage MAC address */ 11226 if (!NO_FCOE(bp)) { 11227 rtnl_lock(); 11228 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11229 rtnl_unlock(); 11230 } 11231#endif 11232 11233#ifdef BCM_DCBNL 11234 /* Delete app tlvs from dcbnl */ 11235 bnx2x_dcbnl_update_applist(bp, true); 11236#endif 11237 11238 unregister_netdev(dev); 11239 11240 /* Delete all NAPI objects */ 11241 bnx2x_del_all_napi(bp); 11242 11243 /* Power on: we can't let PCI layer write to us while we are in D3 */ 11244 bnx2x_set_power_state(bp, PCI_D0); 11245 11246 /* Disable MSI/MSI-X */ 11247 bnx2x_disable_msi(bp); 11248 11249 /* Power off */ 11250 bnx2x_set_power_state(bp, PCI_D3hot); 11251 11252 /* Make sure RESET task is not scheduled before continuing */ 11253 cancel_delayed_work_sync(&bp->sp_rtnl_task); 11254 11255 if (bp->regview) 11256 iounmap(bp->regview); 11257 11258 if (bp->doorbells) 11259 iounmap(bp->doorbells); 11260 11261 bnx2x_release_firmware(bp); 11262 11263 bnx2x_free_mem_bp(bp); 11264 11265 free_netdev(dev); 11266 11267 if (atomic_read(&pdev->enable_cnt) == 1) 11268 pci_release_regions(pdev); 11269 11270 pci_disable_device(pdev); 11271 pci_set_drvdata(pdev, NULL); 11272} 11273 11274static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 11275{ 11276 int i; 11277 11278 bp->state = BNX2X_STATE_ERROR; 11279 11280 bp->rx_mode = BNX2X_RX_MODE_NONE; 11281 11282#ifdef BCM_CNIC 11283 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); 11284#endif 11285 /* Stop Tx */ 11286 bnx2x_tx_disable(bp); 11287 11288 bnx2x_netif_stop(bp, 0); 11289 11290 del_timer_sync(&bp->timer); 11291 11292 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 11293 11294 /* Release IRQs */ 11295 bnx2x_free_irq(bp); 11296 11297 /* Free SKBs, SGEs, TPA pool and driver internals */ 11298 bnx2x_free_skbs(bp); 11299 11300 for_each_rx_queue(bp, i) 11301 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 11302 11303 bnx2x_free_mem(bp); 11304 11305 bp->state = BNX2X_STATE_CLOSED; 11306 11307 netif_carrier_off(bp->dev); 11308 11309 return 0; 11310} 11311 11312static void bnx2x_eeh_recover(struct bnx2x *bp) 11313{ 11314 u32 val; 11315 11316 mutex_init(&bp->port.phy_mutex); 11317 11318 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 11319 bp->link_params.shmem_base = bp->common.shmem_base; 11320 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base); 11321 11322 if (!bp->common.shmem_base || 11323 (bp->common.shmem_base < 0xA0000) || 11324 (bp->common.shmem_base >= 0xC0000)) { 11325 BNX2X_DEV_INFO("MCP not active\n"); 11326 bp->flags |= NO_MCP_FLAG; 11327 return; 11328 } 11329 11330 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 11331 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11332 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11333 BNX2X_ERR("BAD MCP validity signature\n"); 11334 11335 if (!BP_NOMCP(bp)) { 11336 bp->fw_seq = 11337 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 11338 DRV_MSG_SEQ_NUMBER_MASK); 11339 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 11340 } 11341} 11342 11343/** 11344 * bnx2x_io_error_detected - called when PCI error is detected 11345 * @pdev: Pointer to PCI device 11346 * @state: The current pci connection state 11347 * 11348 * This function is called after a PCI bus error affecting 11349 * this device has been detected. 11350 */ 11351static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, 11352 pci_channel_state_t state) 11353{ 11354 struct net_device *dev = pci_get_drvdata(pdev); 11355 struct bnx2x *bp = netdev_priv(dev); 11356 11357 rtnl_lock(); 11358 11359 netif_device_detach(dev); 11360 11361 if (state == pci_channel_io_perm_failure) { 11362 rtnl_unlock(); 11363 return PCI_ERS_RESULT_DISCONNECT; 11364 } 11365 11366 if (netif_running(dev)) 11367 bnx2x_eeh_nic_unload(bp); 11368 11369 pci_disable_device(pdev); 11370 11371 rtnl_unlock(); 11372 11373 /* Request a slot reset */ 11374 return PCI_ERS_RESULT_NEED_RESET; 11375} 11376 11377/** 11378 * bnx2x_io_slot_reset - called after the PCI bus has been reset 11379 * @pdev: Pointer to PCI device 11380 * 11381 * Restart the card from scratch, as if from a cold-boot. 11382 */ 11383static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) 11384{ 11385 struct net_device *dev = pci_get_drvdata(pdev); 11386 struct bnx2x *bp = netdev_priv(dev); 11387 11388 rtnl_lock(); 11389 11390 if (pci_enable_device(pdev)) { 11391 dev_err(&pdev->dev, 11392 "Cannot re-enable PCI device after reset\n"); 11393 rtnl_unlock(); 11394 return PCI_ERS_RESULT_DISCONNECT; 11395 } 11396 11397 pci_set_master(pdev); 11398 pci_restore_state(pdev); 11399 11400 if (netif_running(dev)) 11401 bnx2x_set_power_state(bp, PCI_D0); 11402 11403 rtnl_unlock(); 11404 11405 return PCI_ERS_RESULT_RECOVERED; 11406} 11407 11408/** 11409 * bnx2x_io_resume - called when traffic can start flowing again 11410 * @pdev: Pointer to PCI device 11411 * 11412 * This callback is called when the error recovery driver tells us that 11413 * its OK to resume normal operation. 11414 */ 11415static void bnx2x_io_resume(struct pci_dev *pdev) 11416{ 11417 struct net_device *dev = pci_get_drvdata(pdev); 11418 struct bnx2x *bp = netdev_priv(dev); 11419 11420 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 11421 netdev_err(bp->dev, "Handling parity error recovery. " 11422 "Try again later\n"); 11423 return; 11424 } 11425 11426 rtnl_lock(); 11427 11428 bnx2x_eeh_recover(bp); 11429 11430 if (netif_running(dev)) 11431 bnx2x_nic_load(bp, LOAD_NORMAL); 11432 11433 netif_device_attach(dev); 11434 11435 rtnl_unlock(); 11436} 11437 11438static struct pci_error_handlers bnx2x_err_handler = { 11439 .error_detected = bnx2x_io_error_detected, 11440 .slot_reset = bnx2x_io_slot_reset, 11441 .resume = bnx2x_io_resume, 11442}; 11443 11444static struct pci_driver bnx2x_pci_driver = { 11445 .name = DRV_MODULE_NAME, 11446 .id_table = bnx2x_pci_tbl, 11447 .probe = bnx2x_init_one, 11448 .remove = __devexit_p(bnx2x_remove_one), 11449 .suspend = bnx2x_suspend, 11450 .resume = bnx2x_resume, 11451 .err_handler = &bnx2x_err_handler, 11452}; 11453 11454static int __init bnx2x_init(void) 11455{ 11456 int ret; 11457 11458 pr_info("%s", version); 11459 11460 bnx2x_wq = create_singlethread_workqueue("bnx2x"); 11461 if (bnx2x_wq == NULL) { 11462 pr_err("Cannot create workqueue\n"); 11463 return -ENOMEM; 11464 } 11465 11466 ret = pci_register_driver(&bnx2x_pci_driver); 11467 if (ret) { 11468 pr_err("Cannot register driver\n"); 11469 destroy_workqueue(bnx2x_wq); 11470 } 11471 return ret; 11472} 11473 11474static void __exit bnx2x_cleanup(void) 11475{ 11476 pci_unregister_driver(&bnx2x_pci_driver); 11477 11478 destroy_workqueue(bnx2x_wq); 11479} 11480 11481void bnx2x_notify_link_changed(struct bnx2x *bp) 11482{ 11483 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); 11484} 11485 11486module_init(bnx2x_init); 11487module_exit(bnx2x_cleanup); 11488 11489#ifdef BCM_CNIC 11490/** 11491 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). 11492 * 11493 * @bp: driver handle 11494 * @set: set or clear the CAM entry 11495 * 11496 * This function will wait until the ramdord completion returns. 11497 * Return 0 if success, -ENODEV if ramrod doesn't return. 11498 */ 11499static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) 11500{ 11501 unsigned long ramrod_flags = 0; 11502 11503 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 11504 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, 11505 &bp->iscsi_l2_mac_obj, true, 11506 BNX2X_ISCSI_ETH_MAC, &ramrod_flags); 11507} 11508 11509/* count denotes the number of new completions we have seen */ 11510static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) 11511{ 11512 struct eth_spe *spe; 11513 11514#ifdef BNX2X_STOP_ON_ERROR 11515 if (unlikely(bp->panic)) 11516 return; 11517#endif 11518 11519 spin_lock_bh(&bp->spq_lock); 11520 BUG_ON(bp->cnic_spq_pending < count); 11521 bp->cnic_spq_pending -= count; 11522 11523 11524 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { 11525 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) 11526 & SPE_HDR_CONN_TYPE) >> 11527 SPE_HDR_CONN_TYPE_SHIFT; 11528 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) 11529 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; 11530 11531 /* Set validation for iSCSI L2 client before sending SETUP 11532 * ramrod 11533 */ 11534 if (type == ETH_CONNECTION_TYPE) { 11535 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) 11536 bnx2x_set_ctx_validation(bp, &bp->context. 11537 vcxt[BNX2X_ISCSI_ETH_CID].eth, 11538 BNX2X_ISCSI_ETH_CID); 11539 } 11540 11541 /* 11542 * There may be not more than 8 L2, not more than 8 L5 SPEs 11543 * and in the air. We also check that number of outstanding 11544 * COMMON ramrods is not more than the EQ and SPQ can 11545 * accommodate. 11546 */ 11547 if (type == ETH_CONNECTION_TYPE) { 11548 if (!atomic_read(&bp->cq_spq_left)) 11549 break; 11550 else 11551 atomic_dec(&bp->cq_spq_left); 11552 } else if (type == NONE_CONNECTION_TYPE) { 11553 if (!atomic_read(&bp->eq_spq_left)) 11554 break; 11555 else 11556 atomic_dec(&bp->eq_spq_left); 11557 } else if ((type == ISCSI_CONNECTION_TYPE) || 11558 (type == FCOE_CONNECTION_TYPE)) { 11559 if (bp->cnic_spq_pending >= 11560 bp->cnic_eth_dev.max_kwqe_pending) 11561 break; 11562 else 11563 bp->cnic_spq_pending++; 11564 } else { 11565 BNX2X_ERR("Unknown SPE type: %d\n", type); 11566 bnx2x_panic(); 11567 break; 11568 } 11569 11570 spe = bnx2x_sp_get_next(bp); 11571 *spe = *bp->cnic_kwq_cons; 11572 11573 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n", 11574 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 11575 11576 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 11577 bp->cnic_kwq_cons = bp->cnic_kwq; 11578 else 11579 bp->cnic_kwq_cons++; 11580 } 11581 bnx2x_sp_prod_update(bp); 11582 spin_unlock_bh(&bp->spq_lock); 11583} 11584 11585static int bnx2x_cnic_sp_queue(struct net_device *dev, 11586 struct kwqe_16 *kwqes[], u32 count) 11587{ 11588 struct bnx2x *bp = netdev_priv(dev); 11589 int i; 11590 11591#ifdef BNX2X_STOP_ON_ERROR 11592 if (unlikely(bp->panic)) 11593 return -EIO; 11594#endif 11595 11596 spin_lock_bh(&bp->spq_lock); 11597 11598 for (i = 0; i < count; i++) { 11599 struct eth_spe *spe = (struct eth_spe *)kwqes[i]; 11600 11601 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) 11602 break; 11603 11604 *bp->cnic_kwq_prod = *spe; 11605 11606 bp->cnic_kwq_pending++; 11607 11608 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n", 11609 spe->hdr.conn_and_cmd_data, spe->hdr.type, 11610 spe->data.update_data_addr.hi, 11611 spe->data.update_data_addr.lo, 11612 bp->cnic_kwq_pending); 11613 11614 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 11615 bp->cnic_kwq_prod = bp->cnic_kwq; 11616 else 11617 bp->cnic_kwq_prod++; 11618 } 11619 11620 spin_unlock_bh(&bp->spq_lock); 11621 11622 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) 11623 bnx2x_cnic_sp_post(bp, 0); 11624 11625 return i; 11626} 11627 11628static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11629{ 11630 struct cnic_ops *c_ops; 11631 int rc = 0; 11632 11633 mutex_lock(&bp->cnic_mutex); 11634 c_ops = rcu_dereference_protected(bp->cnic_ops, 11635 lockdep_is_held(&bp->cnic_mutex)); 11636 if (c_ops) 11637 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11638 mutex_unlock(&bp->cnic_mutex); 11639 11640 return rc; 11641} 11642 11643static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11644{ 11645 struct cnic_ops *c_ops; 11646 int rc = 0; 11647 11648 rcu_read_lock(); 11649 c_ops = rcu_dereference(bp->cnic_ops); 11650 if (c_ops) 11651 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11652 rcu_read_unlock(); 11653 11654 return rc; 11655} 11656 11657/* 11658 * for commands that have no data 11659 */ 11660int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) 11661{ 11662 struct cnic_ctl_info ctl = {0}; 11663 11664 ctl.cmd = cmd; 11665 11666 return bnx2x_cnic_ctl_send(bp, &ctl); 11667} 11668 11669static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) 11670{ 11671 struct cnic_ctl_info ctl = {0}; 11672 11673 /* first we tell CNIC and only then we count this as a completion */ 11674 ctl.cmd = CNIC_CTL_COMPLETION_CMD; 11675 ctl.data.comp.cid = cid; 11676 ctl.data.comp.error = err; 11677 11678 bnx2x_cnic_ctl_send_bh(bp, &ctl); 11679 bnx2x_cnic_sp_post(bp, 0); 11680} 11681 11682 11683/* Called with netif_addr_lock_bh() taken. 11684 * Sets an rx_mode config for an iSCSI ETH client. 11685 * Doesn't block. 11686 * Completion should be checked outside. 11687 */ 11688static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) 11689{ 11690 unsigned long accept_flags = 0, ramrod_flags = 0; 11691 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11692 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; 11693 11694 if (start) { 11695 /* Start accepting on iSCSI L2 ring. Accept all multicasts 11696 * because it's the only way for UIO Queue to accept 11697 * multicasts (in non-promiscuous mode only one Queue per 11698 * function will receive multicast packets (leading in our 11699 * case). 11700 */ 11701 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); 11702 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); 11703 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); 11704 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 11705 11706 /* Clear STOP_PENDING bit if START is requested */ 11707 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); 11708 11709 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; 11710 } else 11711 /* Clear START_PENDING bit if STOP is requested */ 11712 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); 11713 11714 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 11715 set_bit(sched_state, &bp->sp_state); 11716 else { 11717 __set_bit(RAMROD_RX, &ramrod_flags); 11718 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, 11719 ramrod_flags); 11720 } 11721} 11722 11723 11724static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 11725{ 11726 struct bnx2x *bp = netdev_priv(dev); 11727 int rc = 0; 11728 11729 switch (ctl->cmd) { 11730 case DRV_CTL_CTXTBL_WR_CMD: { 11731 u32 index = ctl->data.io.offset; 11732 dma_addr_t addr = ctl->data.io.dma_addr; 11733 11734 bnx2x_ilt_wr(bp, index, addr); 11735 break; 11736 } 11737 11738 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { 11739 int count = ctl->data.credit.credit_count; 11740 11741 bnx2x_cnic_sp_post(bp, count); 11742 break; 11743 } 11744 11745 /* rtnl_lock is held. */ 11746 case DRV_CTL_START_L2_CMD: { 11747 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11748 unsigned long sp_bits = 0; 11749 11750 /* Configure the iSCSI classification object */ 11751 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, 11752 cp->iscsi_l2_client_id, 11753 cp->iscsi_l2_cid, BP_FUNC(bp), 11754 bnx2x_sp(bp, mac_rdata), 11755 bnx2x_sp_mapping(bp, mac_rdata), 11756 BNX2X_FILTER_MAC_PENDING, 11757 &bp->sp_state, BNX2X_OBJ_TYPE_RX, 11758 &bp->macs_pool); 11759 11760 /* Set iSCSI MAC address */ 11761 rc = bnx2x_set_iscsi_eth_mac_addr(bp); 11762 if (rc) 11763 break; 11764 11765 mmiowb(); 11766 barrier(); 11767 11768 /* Start accepting on iSCSI L2 ring */ 11769 11770 netif_addr_lock_bh(dev); 11771 bnx2x_set_iscsi_eth_rx_mode(bp, true); 11772 netif_addr_unlock_bh(dev); 11773 11774 /* bits to wait on */ 11775 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11776 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); 11777 11778 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11779 BNX2X_ERR("rx_mode completion timed out!\n"); 11780 11781 break; 11782 } 11783 11784 /* rtnl_lock is held. */ 11785 case DRV_CTL_STOP_L2_CMD: { 11786 unsigned long sp_bits = 0; 11787 11788 /* Stop accepting on iSCSI L2 ring */ 11789 netif_addr_lock_bh(dev); 11790 bnx2x_set_iscsi_eth_rx_mode(bp, false); 11791 netif_addr_unlock_bh(dev); 11792 11793 /* bits to wait on */ 11794 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11795 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); 11796 11797 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11798 BNX2X_ERR("rx_mode completion timed out!\n"); 11799 11800 mmiowb(); 11801 barrier(); 11802 11803 /* Unset iSCSI L2 MAC */ 11804 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, 11805 BNX2X_ISCSI_ETH_MAC, true); 11806 break; 11807 } 11808 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { 11809 int count = ctl->data.credit.credit_count; 11810 11811 smp_mb__before_atomic_inc(); 11812 atomic_add(count, &bp->cq_spq_left); 11813 smp_mb__after_atomic_inc(); 11814 break; 11815 } 11816 case DRV_CTL_ULP_REGISTER_CMD: { 11817 int ulp_type = ctl->data.ulp_type; 11818 11819 if (CHIP_IS_E3(bp)) { 11820 int idx = BP_FW_MB_IDX(bp); 11821 u32 cap; 11822 11823 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 11824 if (ulp_type == CNIC_ULP_ISCSI) 11825 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 11826 else if (ulp_type == CNIC_ULP_FCOE) 11827 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 11828 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 11829 } 11830 break; 11831 } 11832 case DRV_CTL_ULP_UNREGISTER_CMD: { 11833 int ulp_type = ctl->data.ulp_type; 11834 11835 if (CHIP_IS_E3(bp)) { 11836 int idx = BP_FW_MB_IDX(bp); 11837 u32 cap; 11838 11839 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 11840 if (ulp_type == CNIC_ULP_ISCSI) 11841 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 11842 else if (ulp_type == CNIC_ULP_FCOE) 11843 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 11844 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 11845 } 11846 break; 11847 } 11848 11849 default: 11850 BNX2X_ERR("unknown command %x\n", ctl->cmd); 11851 rc = -EINVAL; 11852 } 11853 11854 return rc; 11855} 11856 11857void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) 11858{ 11859 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11860 11861 if (bp->flags & USING_MSIX_FLAG) { 11862 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 11863 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 11864 cp->irq_arr[0].vector = bp->msix_table[1].vector; 11865 } else { 11866 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 11867 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 11868 } 11869 if (!CHIP_IS_E1x(bp)) 11870 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; 11871 else 11872 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; 11873 11874 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); 11875 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); 11876 cp->irq_arr[1].status_blk = bp->def_status_blk; 11877 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 11878 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; 11879 11880 cp->num_irq = 2; 11881} 11882 11883static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, 11884 void *data) 11885{ 11886 struct bnx2x *bp = netdev_priv(dev); 11887 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11888 11889 if (ops == NULL) 11890 return -EINVAL; 11891 11892 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 11893 if (!bp->cnic_kwq) 11894 return -ENOMEM; 11895 11896 bp->cnic_kwq_cons = bp->cnic_kwq; 11897 bp->cnic_kwq_prod = bp->cnic_kwq; 11898 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; 11899 11900 bp->cnic_spq_pending = 0; 11901 bp->cnic_kwq_pending = 0; 11902 11903 bp->cnic_data = data; 11904 11905 cp->num_irq = 0; 11906 cp->drv_state |= CNIC_DRV_STATE_REGD; 11907 cp->iro_arr = bp->iro_arr; 11908 11909 bnx2x_setup_cnic_irq_info(bp); 11910 11911 rcu_assign_pointer(bp->cnic_ops, ops); 11912 11913 return 0; 11914} 11915 11916static int bnx2x_unregister_cnic(struct net_device *dev) 11917{ 11918 struct bnx2x *bp = netdev_priv(dev); 11919 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11920 11921 mutex_lock(&bp->cnic_mutex); 11922 cp->drv_state = 0; 11923 RCU_INIT_POINTER(bp->cnic_ops, NULL); 11924 mutex_unlock(&bp->cnic_mutex); 11925 synchronize_rcu(); 11926 kfree(bp->cnic_kwq); 11927 bp->cnic_kwq = NULL; 11928 11929 return 0; 11930} 11931 11932struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) 11933{ 11934 struct bnx2x *bp = netdev_priv(dev); 11935 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11936 11937 /* If both iSCSI and FCoE are disabled - return NULL in 11938 * order to indicate CNIC that it should not try to work 11939 * with this device. 11940 */ 11941 if (NO_ISCSI(bp) && NO_FCOE(bp)) 11942 return NULL; 11943 11944 cp->drv_owner = THIS_MODULE; 11945 cp->chip_id = CHIP_ID(bp); 11946 cp->pdev = bp->pdev; 11947 cp->io_base = bp->regview; 11948 cp->io_base2 = bp->doorbells; 11949 cp->max_kwqe_pending = 8; 11950 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; 11951 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 11952 bnx2x_cid_ilt_lines(bp); 11953 cp->ctx_tbl_len = CNIC_ILT_LINES; 11954 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 11955 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 11956 cp->drv_ctl = bnx2x_drv_ctl; 11957 cp->drv_register_cnic = bnx2x_register_cnic; 11958 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 11959 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID; 11960 cp->iscsi_l2_client_id = 11961 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11962 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID; 11963 11964 if (NO_ISCSI_OOO(bp)) 11965 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 11966 11967 if (NO_ISCSI(bp)) 11968 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; 11969 11970 if (NO_FCOE(bp)) 11971 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 11972 11973 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, " 11974 "starting cid %d\n", 11975 cp->ctx_blk_size, 11976 cp->ctx_tbl_offset, 11977 cp->ctx_tbl_len, 11978 cp->starting_cid); 11979 return cp; 11980} 11981EXPORT_SYMBOL(bnx2x_cnic_probe); 11982 11983#endif /* BCM_CNIC */ 11984 11985