bnx2x_main.c revision 89db4ad830fbdde9c2d990b88bbac8245718177d
1/* bnx2x_main.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2011 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20#include <linux/module.h> 21#include <linux/moduleparam.h> 22#include <linux/kernel.h> 23#include <linux/device.h> /* for dev_info() */ 24#include <linux/timer.h> 25#include <linux/errno.h> 26#include <linux/ioport.h> 27#include <linux/slab.h> 28#include <linux/interrupt.h> 29#include <linux/pci.h> 30#include <linux/init.h> 31#include <linux/netdevice.h> 32#include <linux/etherdevice.h> 33#include <linux/skbuff.h> 34#include <linux/dma-mapping.h> 35#include <linux/bitops.h> 36#include <linux/irq.h> 37#include <linux/delay.h> 38#include <asm/byteorder.h> 39#include <linux/time.h> 40#include <linux/ethtool.h> 41#include <linux/mii.h> 42#include <linux/if.h> 43#include <linux/if_vlan.h> 44#include <net/ip.h> 45#include <net/ipv6.h> 46#include <net/tcp.h> 47#include <net/checksum.h> 48#include <net/ip6_checksum.h> 49#include <linux/workqueue.h> 50#include <linux/crc32.h> 51#include <linux/crc32c.h> 52#include <linux/prefetch.h> 53#include <linux/zlib.h> 54#include <linux/io.h> 55#include <linux/stringify.h> 56#include <linux/vmalloc.h> 57 58#include "bnx2x.h" 59#include "bnx2x_init.h" 60#include "bnx2x_init_ops.h" 61#include "bnx2x_cmn.h" 62#include "bnx2x_dcb.h" 63#include "bnx2x_sp.h" 64 65#include <linux/firmware.h> 66#include "bnx2x_fw_file_hdr.h" 67/* FW files */ 68#define FW_FILE_VERSION \ 69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 72 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 73#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 74#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 75#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 76 77/* Time in jiffies before concluding the transmitter is hung */ 78#define TX_TIMEOUT (5*HZ) 79 80static char version[] __devinitdata = 81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " 82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 83 84MODULE_AUTHOR("Eliezer Tamir"); 85MODULE_DESCRIPTION("Broadcom NetXtreme II " 86 "BCM57710/57711/57711E/" 87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 88 "57840/57840_MF Driver"); 89MODULE_LICENSE("GPL"); 90MODULE_VERSION(DRV_MODULE_VERSION); 91MODULE_FIRMWARE(FW_FILE_NAME_E1); 92MODULE_FIRMWARE(FW_FILE_NAME_E1H); 93MODULE_FIRMWARE(FW_FILE_NAME_E2); 94 95static int multi_mode = 1; 96module_param(multi_mode, int, 0); 97MODULE_PARM_DESC(multi_mode, " Multi queue mode " 98 "(0 Disable; 1 Enable (default))"); 99 100int num_queues; 101module_param(num_queues, int, 0); 102MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1" 103 " (default is as a number of CPUs)"); 104 105static int disable_tpa; 106module_param(disable_tpa, int, 0); 107MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 108 109#define INT_MODE_INTx 1 110#define INT_MODE_MSI 2 111static int int_mode; 112module_param(int_mode, int, 0); 113MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 114 "(1 INT#x; 2 MSI)"); 115 116static int dropless_fc; 117module_param(dropless_fc, int, 0); 118MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 119 120static int poll; 121module_param(poll, int, 0); 122MODULE_PARM_DESC(poll, " Use polling (for debug)"); 123 124static int mrrs = -1; 125module_param(mrrs, int, 0); 126MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 127 128static int debug; 129module_param(debug, int, 0); 130MODULE_PARM_DESC(debug, " Default debug msglevel"); 131 132 133 134struct workqueue_struct *bnx2x_wq; 135 136enum bnx2x_board_type { 137 BCM57710 = 0, 138 BCM57711, 139 BCM57711E, 140 BCM57712, 141 BCM57712_MF, 142 BCM57800, 143 BCM57800_MF, 144 BCM57810, 145 BCM57810_MF, 146 BCM57840, 147 BCM57840_MF 148}; 149 150/* indexed by board_type, above */ 151static struct { 152 char *name; 153} board_info[] __devinitdata = { 154 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, 155 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, 156 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, 157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, 158 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, 159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, 160 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, 161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, 162 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, 163 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, 164 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit " 165 "Ethernet Multi Function"} 166}; 167 168#ifndef PCI_DEVICE_ID_NX2_57710 169#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 170#endif 171#ifndef PCI_DEVICE_ID_NX2_57711 172#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 173#endif 174#ifndef PCI_DEVICE_ID_NX2_57711E 175#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 176#endif 177#ifndef PCI_DEVICE_ID_NX2_57712 178#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 179#endif 180#ifndef PCI_DEVICE_ID_NX2_57712_MF 181#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 182#endif 183#ifndef PCI_DEVICE_ID_NX2_57800 184#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 185#endif 186#ifndef PCI_DEVICE_ID_NX2_57800_MF 187#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 188#endif 189#ifndef PCI_DEVICE_ID_NX2_57810 190#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 191#endif 192#ifndef PCI_DEVICE_ID_NX2_57810_MF 193#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 194#endif 195#ifndef PCI_DEVICE_ID_NX2_57840 196#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 197#endif 198#ifndef PCI_DEVICE_ID_NX2_57840_MF 199#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 200#endif 201static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 210 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 211 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, 212 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 213 { 0 } 214}; 215 216MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 217 218/**************************************************************************** 219* General service functions 220****************************************************************************/ 221 222static inline void __storm_memset_dma_mapping(struct bnx2x *bp, 223 u32 addr, dma_addr_t mapping) 224{ 225 REG_WR(bp, addr, U64_LO(mapping)); 226 REG_WR(bp, addr + 4, U64_HI(mapping)); 227} 228 229static inline void storm_memset_spq_addr(struct bnx2x *bp, 230 dma_addr_t mapping, u16 abs_fid) 231{ 232 u32 addr = XSEM_REG_FAST_MEMORY + 233 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 234 235 __storm_memset_dma_mapping(bp, addr, mapping); 236} 237 238static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 239 u16 pf_id) 240{ 241 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 242 pf_id); 243 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 244 pf_id); 245 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 246 pf_id); 247 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 248 pf_id); 249} 250 251static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 252 u8 enable) 253{ 254 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 255 enable); 256 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 257 enable); 258 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 259 enable); 260 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 261 enable); 262} 263 264static inline void storm_memset_eq_data(struct bnx2x *bp, 265 struct event_ring_data *eq_data, 266 u16 pfid) 267{ 268 size_t size = sizeof(struct event_ring_data); 269 270 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 271 272 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 273} 274 275static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 276 u16 pfid) 277{ 278 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 279 REG_WR16(bp, addr, eq_prod); 280} 281 282/* used only at init 283 * locking is done by mcp 284 */ 285static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 286{ 287 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 288 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 289 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 290 PCICFG_VENDOR_ID_OFFSET); 291} 292 293static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 294{ 295 u32 val; 296 297 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 298 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 299 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 300 PCICFG_VENDOR_ID_OFFSET); 301 302 return val; 303} 304 305#define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 306#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 307#define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 308#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 309#define DMAE_DP_DST_NONE "dst_addr [none]" 310 311static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, 312 int msglvl) 313{ 314 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 315 316 switch (dmae->opcode & DMAE_COMMAND_DST) { 317 case DMAE_CMD_DST_PCI: 318 if (src_type == DMAE_CMD_SRC_PCI) 319 DP(msglvl, "DMAE: opcode 0x%08x\n" 320 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 321 "comp_addr [%x:%08x], comp_val 0x%08x\n", 322 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 323 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 324 dmae->comp_addr_hi, dmae->comp_addr_lo, 325 dmae->comp_val); 326 else 327 DP(msglvl, "DMAE: opcode 0x%08x\n" 328 "src [%08x], len [%d*4], dst [%x:%08x]\n" 329 "comp_addr [%x:%08x], comp_val 0x%08x\n", 330 dmae->opcode, dmae->src_addr_lo >> 2, 331 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 332 dmae->comp_addr_hi, dmae->comp_addr_lo, 333 dmae->comp_val); 334 break; 335 case DMAE_CMD_DST_GRC: 336 if (src_type == DMAE_CMD_SRC_PCI) 337 DP(msglvl, "DMAE: opcode 0x%08x\n" 338 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 339 "comp_addr [%x:%08x], comp_val 0x%08x\n", 340 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 341 dmae->len, dmae->dst_addr_lo >> 2, 342 dmae->comp_addr_hi, dmae->comp_addr_lo, 343 dmae->comp_val); 344 else 345 DP(msglvl, "DMAE: opcode 0x%08x\n" 346 "src [%08x], len [%d*4], dst [%08x]\n" 347 "comp_addr [%x:%08x], comp_val 0x%08x\n", 348 dmae->opcode, dmae->src_addr_lo >> 2, 349 dmae->len, dmae->dst_addr_lo >> 2, 350 dmae->comp_addr_hi, dmae->comp_addr_lo, 351 dmae->comp_val); 352 break; 353 default: 354 if (src_type == DMAE_CMD_SRC_PCI) 355 DP(msglvl, "DMAE: opcode 0x%08x\n" 356 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 357 "comp_addr [%x:%08x] comp_val 0x%08x\n", 358 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 359 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 360 dmae->comp_val); 361 else 362 DP(msglvl, "DMAE: opcode 0x%08x\n" 363 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 364 "comp_addr [%x:%08x] comp_val 0x%08x\n", 365 dmae->opcode, dmae->src_addr_lo >> 2, 366 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 367 dmae->comp_val); 368 break; 369 } 370 371} 372 373/* copy command into DMAE command memory and set DMAE command go */ 374void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 375{ 376 u32 cmd_offset; 377 int i; 378 379 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 380 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 381 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 382 383 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n", 384 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); 385 } 386 REG_WR(bp, dmae_reg_go_c[idx], 1); 387} 388 389u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 390{ 391 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 392 DMAE_CMD_C_ENABLE); 393} 394 395u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 396{ 397 return opcode & ~DMAE_CMD_SRC_RESET; 398} 399 400u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 401 bool with_comp, u8 comp_type) 402{ 403 u32 opcode = 0; 404 405 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 406 (dst_type << DMAE_COMMAND_DST_SHIFT)); 407 408 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 409 410 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 411 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | 412 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 413 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 414 415#ifdef __BIG_ENDIAN 416 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 417#else 418 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 419#endif 420 if (with_comp) 421 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 422 return opcode; 423} 424 425static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 426 struct dmae_command *dmae, 427 u8 src_type, u8 dst_type) 428{ 429 memset(dmae, 0, sizeof(struct dmae_command)); 430 431 /* set the opcode */ 432 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 433 true, DMAE_COMP_PCI); 434 435 /* fill in the completion parameters */ 436 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 437 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 438 dmae->comp_val = DMAE_COMP_VAL; 439} 440 441/* issue a dmae command over the init-channel and wailt for completion */ 442static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, 443 struct dmae_command *dmae) 444{ 445 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 446 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 447 int rc = 0; 448 449 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n", 450 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 451 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 452 453 /* 454 * Lock the dmae channel. Disable BHs to prevent a dead-lock 455 * as long as this code is called both from syscall context and 456 * from ndo_set_rx_mode() flow that may be called from BH. 457 */ 458 spin_lock_bh(&bp->dmae_lock); 459 460 /* reset completion */ 461 *wb_comp = 0; 462 463 /* post the command on the channel used for initializations */ 464 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 465 466 /* wait for completion */ 467 udelay(5); 468 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 469 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); 470 471 if (!cnt) { 472 BNX2X_ERR("DMAE timeout!\n"); 473 rc = DMAE_TIMEOUT; 474 goto unlock; 475 } 476 cnt--; 477 udelay(50); 478 } 479 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 480 BNX2X_ERR("DMAE PCI error!\n"); 481 rc = DMAE_PCI_ERROR; 482 } 483 484 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n", 485 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 486 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 487 488unlock: 489 spin_unlock_bh(&bp->dmae_lock); 490 return rc; 491} 492 493void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 494 u32 len32) 495{ 496 struct dmae_command dmae; 497 498 if (!bp->dmae_ready) { 499 u32 *data = bnx2x_sp(bp, wb_data[0]); 500 501 DP(BNX2X_MSG_OFF, 502 "DMAE is not ready (dst_addr %08x len32 %d) using indirect\n", 503 dst_addr, len32); 504 if (CHIP_IS_E1(bp)) 505 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 506 else 507 bnx2x_init_str_wr(bp, dst_addr, data, len32); 508 return; 509 } 510 511 /* set opcode and fixed command fields */ 512 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 513 514 /* fill in addresses and len */ 515 dmae.src_addr_lo = U64_LO(dma_addr); 516 dmae.src_addr_hi = U64_HI(dma_addr); 517 dmae.dst_addr_lo = dst_addr >> 2; 518 dmae.dst_addr_hi = 0; 519 dmae.len = len32; 520 521 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 522 523 /* issue the command and wait for completion */ 524 bnx2x_issue_dmae_with_comp(bp, &dmae); 525} 526 527void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 528{ 529 struct dmae_command dmae; 530 531 if (!bp->dmae_ready) { 532 u32 *data = bnx2x_sp(bp, wb_data[0]); 533 int i; 534 535 if (CHIP_IS_E1(bp)) { 536 DP(BNX2X_MSG_OFF, 537 "DMAE is not ready (src_addr %08x len32 %d) using indirect\n", 538 src_addr, len32); 539 for (i = 0; i < len32; i++) 540 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 541 } else 542 for (i = 0; i < len32; i++) 543 data[i] = REG_RD(bp, src_addr + i*4); 544 545 return; 546 } 547 548 /* set opcode and fixed command fields */ 549 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 550 551 /* fill in addresses and len */ 552 dmae.src_addr_lo = src_addr >> 2; 553 dmae.src_addr_hi = 0; 554 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 555 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 556 dmae.len = len32; 557 558 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 559 560 /* issue the command and wait for completion */ 561 bnx2x_issue_dmae_with_comp(bp, &dmae); 562} 563 564static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 565 u32 addr, u32 len) 566{ 567 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 568 int offset = 0; 569 570 while (len > dmae_wr_max) { 571 bnx2x_write_dmae(bp, phys_addr + offset, 572 addr + offset, dmae_wr_max); 573 offset += dmae_wr_max * 4; 574 len -= dmae_wr_max; 575 } 576 577 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 578} 579 580/* used only for slowpath so not inlined */ 581static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo) 582{ 583 u32 wb_write[2]; 584 585 wb_write[0] = val_hi; 586 wb_write[1] = val_lo; 587 REG_WR_DMAE(bp, reg, wb_write, 2); 588} 589 590#ifdef USE_WB_RD 591static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg) 592{ 593 u32 wb_data[2]; 594 595 REG_RD_DMAE(bp, reg, wb_data, 2); 596 597 return HILO_U64(wb_data[0], wb_data[1]); 598} 599#endif 600 601static int bnx2x_mc_assert(struct bnx2x *bp) 602{ 603 char last_idx; 604 int i, rc = 0; 605 u32 row0, row1, row2, row3; 606 607 /* XSTORM */ 608 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + 609 XSTORM_ASSERT_LIST_INDEX_OFFSET); 610 if (last_idx) 611 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 612 613 /* print the asserts */ 614 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 615 616 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + 617 XSTORM_ASSERT_LIST_OFFSET(i)); 618 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + 619 XSTORM_ASSERT_LIST_OFFSET(i) + 4); 620 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + 621 XSTORM_ASSERT_LIST_OFFSET(i) + 8); 622 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + 623 XSTORM_ASSERT_LIST_OFFSET(i) + 12); 624 625 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 626 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x" 627 " 0x%08x 0x%08x 0x%08x\n", 628 i, row3, row2, row1, row0); 629 rc++; 630 } else { 631 break; 632 } 633 } 634 635 /* TSTORM */ 636 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + 637 TSTORM_ASSERT_LIST_INDEX_OFFSET); 638 if (last_idx) 639 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 640 641 /* print the asserts */ 642 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 643 644 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + 645 TSTORM_ASSERT_LIST_OFFSET(i)); 646 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + 647 TSTORM_ASSERT_LIST_OFFSET(i) + 4); 648 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + 649 TSTORM_ASSERT_LIST_OFFSET(i) + 8); 650 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + 651 TSTORM_ASSERT_LIST_OFFSET(i) + 12); 652 653 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 654 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x" 655 " 0x%08x 0x%08x 0x%08x\n", 656 i, row3, row2, row1, row0); 657 rc++; 658 } else { 659 break; 660 } 661 } 662 663 /* CSTORM */ 664 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + 665 CSTORM_ASSERT_LIST_INDEX_OFFSET); 666 if (last_idx) 667 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 668 669 /* print the asserts */ 670 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 671 672 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + 673 CSTORM_ASSERT_LIST_OFFSET(i)); 674 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + 675 CSTORM_ASSERT_LIST_OFFSET(i) + 4); 676 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + 677 CSTORM_ASSERT_LIST_OFFSET(i) + 8); 678 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + 679 CSTORM_ASSERT_LIST_OFFSET(i) + 12); 680 681 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 682 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x" 683 " 0x%08x 0x%08x 0x%08x\n", 684 i, row3, row2, row1, row0); 685 rc++; 686 } else { 687 break; 688 } 689 } 690 691 /* USTORM */ 692 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + 693 USTORM_ASSERT_LIST_INDEX_OFFSET); 694 if (last_idx) 695 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 696 697 /* print the asserts */ 698 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 699 700 row0 = REG_RD(bp, BAR_USTRORM_INTMEM + 701 USTORM_ASSERT_LIST_OFFSET(i)); 702 row1 = REG_RD(bp, BAR_USTRORM_INTMEM + 703 USTORM_ASSERT_LIST_OFFSET(i) + 4); 704 row2 = REG_RD(bp, BAR_USTRORM_INTMEM + 705 USTORM_ASSERT_LIST_OFFSET(i) + 8); 706 row3 = REG_RD(bp, BAR_USTRORM_INTMEM + 707 USTORM_ASSERT_LIST_OFFSET(i) + 12); 708 709 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 710 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x" 711 " 0x%08x 0x%08x 0x%08x\n", 712 i, row3, row2, row1, row0); 713 rc++; 714 } else { 715 break; 716 } 717 } 718 719 return rc; 720} 721 722void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 723{ 724 u32 addr, val; 725 u32 mark, offset; 726 __be32 data[9]; 727 int word; 728 u32 trace_shmem_base; 729 if (BP_NOMCP(bp)) { 730 BNX2X_ERR("NO MCP - can not dump\n"); 731 return; 732 } 733 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 734 (bp->common.bc_ver & 0xff0000) >> 16, 735 (bp->common.bc_ver & 0xff00) >> 8, 736 (bp->common.bc_ver & 0xff)); 737 738 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 739 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 740 printk("%s" "MCP PC at 0x%x\n", lvl, val); 741 742 if (BP_PATH(bp) == 0) 743 trace_shmem_base = bp->common.shmem_base; 744 else 745 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 746 addr = trace_shmem_base - 0x0800 + 4; 747 mark = REG_RD(bp, addr); 748 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 749 + ((mark + 0x3) & ~0x3) - 0x08000000; 750 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 751 752 printk("%s", lvl); 753 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { 754 for (word = 0; word < 8; word++) 755 data[word] = htonl(REG_RD(bp, offset + 4*word)); 756 data[8] = 0x0; 757 pr_cont("%s", (char *)data); 758 } 759 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 760 for (word = 0; word < 8; word++) 761 data[word] = htonl(REG_RD(bp, offset + 4*word)); 762 data[8] = 0x0; 763 pr_cont("%s", (char *)data); 764 } 765 printk("%s" "end of fw dump\n", lvl); 766} 767 768static inline void bnx2x_fw_dump(struct bnx2x *bp) 769{ 770 bnx2x_fw_dump_lvl(bp, KERN_ERR); 771} 772 773void bnx2x_panic_dump(struct bnx2x *bp) 774{ 775 int i; 776 u16 j; 777 struct hc_sp_status_block_data sp_sb_data; 778 int func = BP_FUNC(bp); 779#ifdef BNX2X_STOP_ON_ERROR 780 u16 start = 0, end = 0; 781 u8 cos; 782#endif 783 784 bp->stats_state = STATS_STATE_DISABLED; 785 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 786 787 BNX2X_ERR("begin crash dump -----------------\n"); 788 789 /* Indices */ 790 /* Common */ 791 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)" 792 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 793 bp->def_idx, bp->def_att_idx, bp->attn_state, 794 bp->spq_prod_idx, bp->stats_counter); 795 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 796 bp->def_status_blk->atten_status_block.attn_bits, 797 bp->def_status_blk->atten_status_block.attn_bits_ack, 798 bp->def_status_blk->atten_status_block.status_block_id, 799 bp->def_status_blk->atten_status_block.attn_bits_index); 800 BNX2X_ERR(" def ("); 801 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 802 pr_cont("0x%x%s", 803 bp->def_status_blk->sp_sb.index_values[i], 804 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 805 806 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 807 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + 808 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 809 i*sizeof(u32)); 810 811 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 812 sp_sb_data.igu_sb_id, 813 sp_sb_data.igu_seg_id, 814 sp_sb_data.p_func.pf_id, 815 sp_sb_data.p_func.vnic_id, 816 sp_sb_data.p_func.vf_id, 817 sp_sb_data.p_func.vf_valid, 818 sp_sb_data.state); 819 820 821 for_each_eth_queue(bp, i) { 822 struct bnx2x_fastpath *fp = &bp->fp[i]; 823 int loop; 824 struct hc_status_block_data_e2 sb_data_e2; 825 struct hc_status_block_data_e1x sb_data_e1x; 826 struct hc_status_block_sm *hc_sm_p = 827 CHIP_IS_E1x(bp) ? 828 sb_data_e1x.common.state_machine : 829 sb_data_e2.common.state_machine; 830 struct hc_index_data *hc_index_p = 831 CHIP_IS_E1x(bp) ? 832 sb_data_e1x.index_data : 833 sb_data_e2.index_data; 834 u8 data_size, cos; 835 u32 *sb_data_p; 836 struct bnx2x_fp_txdata txdata; 837 838 /* Rx */ 839 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)" 840 " rx_comp_prod(0x%x)" 841 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 842 i, fp->rx_bd_prod, fp->rx_bd_cons, 843 fp->rx_comp_prod, 844 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 845 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)" 846 " fp_hc_idx(0x%x)\n", 847 fp->rx_sge_prod, fp->last_max_sge, 848 le16_to_cpu(fp->fp_hc_idx)); 849 850 /* Tx */ 851 for_each_cos_in_tx_queue(fp, cos) 852 { 853 txdata = fp->txdata[cos]; 854 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)" 855 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)" 856 " *tx_cons_sb(0x%x)\n", 857 i, txdata.tx_pkt_prod, 858 txdata.tx_pkt_cons, txdata.tx_bd_prod, 859 txdata.tx_bd_cons, 860 le16_to_cpu(*txdata.tx_cons_sb)); 861 } 862 863 loop = CHIP_IS_E1x(bp) ? 864 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 865 866 /* host sb data */ 867 868#ifdef BCM_CNIC 869 if (IS_FCOE_FP(fp)) 870 continue; 871#endif 872 BNX2X_ERR(" run indexes ("); 873 for (j = 0; j < HC_SB_MAX_SM; j++) 874 pr_cont("0x%x%s", 875 fp->sb_running_index[j], 876 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 877 878 BNX2X_ERR(" indexes ("); 879 for (j = 0; j < loop; j++) 880 pr_cont("0x%x%s", 881 fp->sb_index_values[j], 882 (j == loop - 1) ? ")" : " "); 883 /* fw sb data */ 884 data_size = CHIP_IS_E1x(bp) ? 885 sizeof(struct hc_status_block_data_e1x) : 886 sizeof(struct hc_status_block_data_e2); 887 data_size /= sizeof(u32); 888 sb_data_p = CHIP_IS_E1x(bp) ? 889 (u32 *)&sb_data_e1x : 890 (u32 *)&sb_data_e2; 891 /* copy sb data in here */ 892 for (j = 0; j < data_size; j++) 893 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 894 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 895 j * sizeof(u32)); 896 897 if (!CHIP_IS_E1x(bp)) { 898 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 899 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 900 "state(0x%x)\n", 901 sb_data_e2.common.p_func.pf_id, 902 sb_data_e2.common.p_func.vf_id, 903 sb_data_e2.common.p_func.vf_valid, 904 sb_data_e2.common.p_func.vnic_id, 905 sb_data_e2.common.same_igu_sb_1b, 906 sb_data_e2.common.state); 907 } else { 908 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 909 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 910 "state(0x%x)\n", 911 sb_data_e1x.common.p_func.pf_id, 912 sb_data_e1x.common.p_func.vf_id, 913 sb_data_e1x.common.p_func.vf_valid, 914 sb_data_e1x.common.p_func.vnic_id, 915 sb_data_e1x.common.same_igu_sb_1b, 916 sb_data_e1x.common.state); 917 } 918 919 /* SB_SMs data */ 920 for (j = 0; j < HC_SB_MAX_SM; j++) { 921 pr_cont("SM[%d] __flags (0x%x) " 922 "igu_sb_id (0x%x) igu_seg_id(0x%x) " 923 "time_to_expire (0x%x) " 924 "timer_value(0x%x)\n", j, 925 hc_sm_p[j].__flags, 926 hc_sm_p[j].igu_sb_id, 927 hc_sm_p[j].igu_seg_id, 928 hc_sm_p[j].time_to_expire, 929 hc_sm_p[j].timer_value); 930 } 931 932 /* Indecies data */ 933 for (j = 0; j < loop; j++) { 934 pr_cont("INDEX[%d] flags (0x%x) " 935 "timeout (0x%x)\n", j, 936 hc_index_p[j].flags, 937 hc_index_p[j].timeout); 938 } 939 } 940 941#ifdef BNX2X_STOP_ON_ERROR 942 /* Rings */ 943 /* Rx */ 944 for_each_rx_queue(bp, i) { 945 struct bnx2x_fastpath *fp = &bp->fp[i]; 946 947 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 948 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 949 for (j = start; j != end; j = RX_BD(j + 1)) { 950 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 951 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 952 953 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 954 i, j, rx_bd[1], rx_bd[0], sw_bd->data); 955 } 956 957 start = RX_SGE(fp->rx_sge_prod); 958 end = RX_SGE(fp->last_max_sge); 959 for (j = start; j != end; j = RX_SGE(j + 1)) { 960 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 961 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 962 963 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 964 i, j, rx_sge[1], rx_sge[0], sw_page->page); 965 } 966 967 start = RCQ_BD(fp->rx_comp_cons - 10); 968 end = RCQ_BD(fp->rx_comp_cons + 503); 969 for (j = start; j != end; j = RCQ_BD(j + 1)) { 970 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 971 972 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 973 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 974 } 975 } 976 977 /* Tx */ 978 for_each_tx_queue(bp, i) { 979 struct bnx2x_fastpath *fp = &bp->fp[i]; 980 for_each_cos_in_tx_queue(fp, cos) { 981 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; 982 983 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 984 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 985 for (j = start; j != end; j = TX_BD(j + 1)) { 986 struct sw_tx_bd *sw_bd = 987 &txdata->tx_buf_ring[j]; 988 989 BNX2X_ERR("fp%d: txdata %d, " 990 "packet[%x]=[%p,%x]\n", 991 i, cos, j, sw_bd->skb, 992 sw_bd->first_bd); 993 } 994 995 start = TX_BD(txdata->tx_bd_cons - 10); 996 end = TX_BD(txdata->tx_bd_cons + 254); 997 for (j = start; j != end; j = TX_BD(j + 1)) { 998 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 999 1000 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=" 1001 "[%x:%x:%x:%x]\n", 1002 i, cos, j, tx_bd[0], tx_bd[1], 1003 tx_bd[2], tx_bd[3]); 1004 } 1005 } 1006 } 1007#endif 1008 bnx2x_fw_dump(bp); 1009 bnx2x_mc_assert(bp); 1010 BNX2X_ERR("end crash dump -----------------\n"); 1011} 1012 1013/* 1014 * FLR Support for E2 1015 * 1016 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 1017 * initialization. 1018 */ 1019#define FLR_WAIT_USEC 10000 /* 10 miliseconds */ 1020#define FLR_WAIT_INTERVAL 50 /* usec */ 1021#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ 1022 1023struct pbf_pN_buf_regs { 1024 int pN; 1025 u32 init_crd; 1026 u32 crd; 1027 u32 crd_freed; 1028}; 1029 1030struct pbf_pN_cmd_regs { 1031 int pN; 1032 u32 lines_occup; 1033 u32 lines_freed; 1034}; 1035 1036static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1037 struct pbf_pN_buf_regs *regs, 1038 u32 poll_count) 1039{ 1040 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1041 u32 cur_cnt = poll_count; 1042 1043 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1044 crd = crd_start = REG_RD(bp, regs->crd); 1045 init_crd = REG_RD(bp, regs->init_crd); 1046 1047 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1048 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1049 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1050 1051 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1052 (init_crd - crd_start))) { 1053 if (cur_cnt--) { 1054 udelay(FLR_WAIT_INTERVAL); 1055 crd = REG_RD(bp, regs->crd); 1056 crd_freed = REG_RD(bp, regs->crd_freed); 1057 } else { 1058 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1059 regs->pN); 1060 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1061 regs->pN, crd); 1062 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1063 regs->pN, crd_freed); 1064 break; 1065 } 1066 } 1067 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1068 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1069} 1070 1071static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1072 struct pbf_pN_cmd_regs *regs, 1073 u32 poll_count) 1074{ 1075 u32 occup, to_free, freed, freed_start; 1076 u32 cur_cnt = poll_count; 1077 1078 occup = to_free = REG_RD(bp, regs->lines_occup); 1079 freed = freed_start = REG_RD(bp, regs->lines_freed); 1080 1081 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1082 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1083 1084 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1085 if (cur_cnt--) { 1086 udelay(FLR_WAIT_INTERVAL); 1087 occup = REG_RD(bp, regs->lines_occup); 1088 freed = REG_RD(bp, regs->lines_freed); 1089 } else { 1090 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1091 regs->pN); 1092 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1093 regs->pN, occup); 1094 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1095 regs->pN, freed); 1096 break; 1097 } 1098 } 1099 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1100 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1101} 1102 1103static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1104 u32 expected, u32 poll_count) 1105{ 1106 u32 cur_cnt = poll_count; 1107 u32 val; 1108 1109 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1110 udelay(FLR_WAIT_INTERVAL); 1111 1112 return val; 1113} 1114 1115static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1116 char *msg, u32 poll_cnt) 1117{ 1118 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1119 if (val != 0) { 1120 BNX2X_ERR("%s usage count=%d\n", msg, val); 1121 return 1; 1122 } 1123 return 0; 1124} 1125 1126static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1127{ 1128 /* adjust polling timeout */ 1129 if (CHIP_REV_IS_EMUL(bp)) 1130 return FLR_POLL_CNT * 2000; 1131 1132 if (CHIP_REV_IS_FPGA(bp)) 1133 return FLR_POLL_CNT * 120; 1134 1135 return FLR_POLL_CNT; 1136} 1137 1138static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1139{ 1140 struct pbf_pN_cmd_regs cmd_regs[] = { 1141 {0, (CHIP_IS_E3B0(bp)) ? 1142 PBF_REG_TQ_OCCUPANCY_Q0 : 1143 PBF_REG_P0_TQ_OCCUPANCY, 1144 (CHIP_IS_E3B0(bp)) ? 1145 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1146 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1147 {1, (CHIP_IS_E3B0(bp)) ? 1148 PBF_REG_TQ_OCCUPANCY_Q1 : 1149 PBF_REG_P1_TQ_OCCUPANCY, 1150 (CHIP_IS_E3B0(bp)) ? 1151 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1152 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1153 {4, (CHIP_IS_E3B0(bp)) ? 1154 PBF_REG_TQ_OCCUPANCY_LB_Q : 1155 PBF_REG_P4_TQ_OCCUPANCY, 1156 (CHIP_IS_E3B0(bp)) ? 1157 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1158 PBF_REG_P4_TQ_LINES_FREED_CNT} 1159 }; 1160 1161 struct pbf_pN_buf_regs buf_regs[] = { 1162 {0, (CHIP_IS_E3B0(bp)) ? 1163 PBF_REG_INIT_CRD_Q0 : 1164 PBF_REG_P0_INIT_CRD , 1165 (CHIP_IS_E3B0(bp)) ? 1166 PBF_REG_CREDIT_Q0 : 1167 PBF_REG_P0_CREDIT, 1168 (CHIP_IS_E3B0(bp)) ? 1169 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1170 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1171 {1, (CHIP_IS_E3B0(bp)) ? 1172 PBF_REG_INIT_CRD_Q1 : 1173 PBF_REG_P1_INIT_CRD, 1174 (CHIP_IS_E3B0(bp)) ? 1175 PBF_REG_CREDIT_Q1 : 1176 PBF_REG_P1_CREDIT, 1177 (CHIP_IS_E3B0(bp)) ? 1178 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1179 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1180 {4, (CHIP_IS_E3B0(bp)) ? 1181 PBF_REG_INIT_CRD_LB_Q : 1182 PBF_REG_P4_INIT_CRD, 1183 (CHIP_IS_E3B0(bp)) ? 1184 PBF_REG_CREDIT_LB_Q : 1185 PBF_REG_P4_CREDIT, 1186 (CHIP_IS_E3B0(bp)) ? 1187 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1188 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1189 }; 1190 1191 int i; 1192 1193 /* Verify the command queues are flushed P0, P1, P4 */ 1194 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1195 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1196 1197 1198 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1199 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1200 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1201} 1202 1203#define OP_GEN_PARAM(param) \ 1204 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1205 1206#define OP_GEN_TYPE(type) \ 1207 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1208 1209#define OP_GEN_AGG_VECT(index) \ 1210 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1211 1212 1213static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, 1214 u32 poll_cnt) 1215{ 1216 struct sdm_op_gen op_gen = {0}; 1217 1218 u32 comp_addr = BAR_CSTRORM_INTMEM + 1219 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1220 int ret = 0; 1221 1222 if (REG_RD(bp, comp_addr)) { 1223 BNX2X_ERR("Cleanup complete was not 0 before sending\n"); 1224 return 1; 1225 } 1226 1227 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1228 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1229 op_gen.command |= OP_GEN_AGG_VECT(clnup_func); 1230 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1231 1232 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); 1233 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); 1234 1235 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1236 BNX2X_ERR("FW final cleanup did not succeed\n"); 1237 ret = 1; 1238 } 1239 /* Zero completion for nxt FLR */ 1240 REG_WR(bp, comp_addr, 0); 1241 1242 return ret; 1243} 1244 1245static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1246{ 1247 int pos; 1248 u16 status; 1249 1250 pos = pci_pcie_cap(dev); 1251 if (!pos) 1252 return false; 1253 1254 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 1255 return status & PCI_EXP_DEVSTA_TRPND; 1256} 1257 1258/* PF FLR specific routines 1259*/ 1260static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1261{ 1262 1263 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1264 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1265 CFC_REG_NUM_LCIDS_INSIDE_PF, 1266 "CFC PF usage counter timed out", 1267 poll_cnt)) 1268 return 1; 1269 1270 1271 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1272 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1273 DORQ_REG_PF_USAGE_CNT, 1274 "DQ PF usage counter timed out", 1275 poll_cnt)) 1276 return 1; 1277 1278 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1279 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1280 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1281 "QM PF usage counter timed out", 1282 poll_cnt)) 1283 return 1; 1284 1285 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1286 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1287 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1288 "Timers VNIC usage counter timed out", 1289 poll_cnt)) 1290 return 1; 1291 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1292 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1293 "Timers NUM_SCANS usage counter timed out", 1294 poll_cnt)) 1295 return 1; 1296 1297 /* Wait DMAE PF usage counter to zero */ 1298 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1299 dmae_reg_go_c[INIT_DMAE_C(bp)], 1300 "DMAE dommand register timed out", 1301 poll_cnt)) 1302 return 1; 1303 1304 return 0; 1305} 1306 1307static void bnx2x_hw_enable_status(struct bnx2x *bp) 1308{ 1309 u32 val; 1310 1311 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1312 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1313 1314 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1315 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1316 1317 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1318 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1319 1320 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1321 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1322 1323 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1324 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1325 1326 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1327 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1328 1329 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1330 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1331 1332 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1333 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1334 val); 1335} 1336 1337static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1338{ 1339 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1340 1341 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1342 1343 /* Re-enable PF target read access */ 1344 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1345 1346 /* Poll HW usage counters */ 1347 DP(BNX2X_MSG_SP, "Polling usage counters\n"); 1348 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1349 return -EBUSY; 1350 1351 /* Zero the igu 'trailing edge' and 'leading edge' */ 1352 1353 /* Send the FW cleanup command */ 1354 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1355 return -EBUSY; 1356 1357 /* ATC cleanup */ 1358 1359 /* Verify TX hw is flushed */ 1360 bnx2x_tx_hw_flushed(bp, poll_cnt); 1361 1362 /* Wait 100ms (not adjusted according to platform) */ 1363 msleep(100); 1364 1365 /* Verify no pending pci transactions */ 1366 if (bnx2x_is_pcie_pending(bp->pdev)) 1367 BNX2X_ERR("PCIE Transactions still pending\n"); 1368 1369 /* Debug */ 1370 bnx2x_hw_enable_status(bp); 1371 1372 /* 1373 * Master enable - Due to WB DMAE writes performed before this 1374 * register is re-initialized as part of the regular function init 1375 */ 1376 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1377 1378 return 0; 1379} 1380 1381static void bnx2x_hc_int_enable(struct bnx2x *bp) 1382{ 1383 int port = BP_PORT(bp); 1384 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1385 u32 val = REG_RD(bp, addr); 1386 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1387 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1388 1389 if (msix) { 1390 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1391 HC_CONFIG_0_REG_INT_LINE_EN_0); 1392 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1393 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1394 } else if (msi) { 1395 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1396 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1397 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1398 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1399 } else { 1400 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1401 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1402 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1403 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1404 1405 if (!CHIP_IS_E1(bp)) { 1406 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1407 val, port, addr); 1408 1409 REG_WR(bp, addr, val); 1410 1411 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1412 } 1413 } 1414 1415 if (CHIP_IS_E1(bp)) 1416 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1417 1418 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", 1419 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1420 1421 REG_WR(bp, addr, val); 1422 /* 1423 * Ensure that HC_CONFIG is written before leading/trailing edge config 1424 */ 1425 mmiowb(); 1426 barrier(); 1427 1428 if (!CHIP_IS_E1(bp)) { 1429 /* init leading/trailing edge */ 1430 if (IS_MF(bp)) { 1431 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1432 if (bp->port.pmf) 1433 /* enable nig and gpio3 attention */ 1434 val |= 0x1100; 1435 } else 1436 val = 0xffff; 1437 1438 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1439 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1440 } 1441 1442 /* Make sure that interrupts are indeed enabled from here on */ 1443 mmiowb(); 1444} 1445 1446static void bnx2x_igu_int_enable(struct bnx2x *bp) 1447{ 1448 u32 val; 1449 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1450 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1451 1452 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1453 1454 if (msix) { 1455 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1456 IGU_PF_CONF_SINGLE_ISR_EN); 1457 val |= (IGU_PF_CONF_FUNC_EN | 1458 IGU_PF_CONF_MSI_MSIX_EN | 1459 IGU_PF_CONF_ATTN_BIT_EN); 1460 } else if (msi) { 1461 val &= ~IGU_PF_CONF_INT_LINE_EN; 1462 val |= (IGU_PF_CONF_FUNC_EN | 1463 IGU_PF_CONF_MSI_MSIX_EN | 1464 IGU_PF_CONF_ATTN_BIT_EN | 1465 IGU_PF_CONF_SINGLE_ISR_EN); 1466 } else { 1467 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1468 val |= (IGU_PF_CONF_FUNC_EN | 1469 IGU_PF_CONF_INT_LINE_EN | 1470 IGU_PF_CONF_ATTN_BIT_EN | 1471 IGU_PF_CONF_SINGLE_ISR_EN); 1472 } 1473 1474 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n", 1475 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1476 1477 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1478 1479 barrier(); 1480 1481 /* init leading/trailing edge */ 1482 if (IS_MF(bp)) { 1483 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1484 if (bp->port.pmf) 1485 /* enable nig and gpio3 attention */ 1486 val |= 0x1100; 1487 } else 1488 val = 0xffff; 1489 1490 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1491 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1492 1493 /* Make sure that interrupts are indeed enabled from here on */ 1494 mmiowb(); 1495} 1496 1497void bnx2x_int_enable(struct bnx2x *bp) 1498{ 1499 if (bp->common.int_block == INT_BLOCK_HC) 1500 bnx2x_hc_int_enable(bp); 1501 else 1502 bnx2x_igu_int_enable(bp); 1503} 1504 1505static void bnx2x_hc_int_disable(struct bnx2x *bp) 1506{ 1507 int port = BP_PORT(bp); 1508 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1509 u32 val = REG_RD(bp, addr); 1510 1511 /* 1512 * in E1 we must use only PCI configuration space to disable 1513 * MSI/MSIX capablility 1514 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 1515 */ 1516 if (CHIP_IS_E1(bp)) { 1517 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 1518 * Use mask register to prevent from HC sending interrupts 1519 * after we exit the function 1520 */ 1521 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 1522 1523 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1524 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1525 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1526 } else 1527 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1528 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1529 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1530 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1531 1532 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1533 val, port, addr); 1534 1535 /* flush all outstanding writes */ 1536 mmiowb(); 1537 1538 REG_WR(bp, addr, val); 1539 if (REG_RD(bp, addr) != val) 1540 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1541} 1542 1543static void bnx2x_igu_int_disable(struct bnx2x *bp) 1544{ 1545 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1546 1547 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 1548 IGU_PF_CONF_INT_LINE_EN | 1549 IGU_PF_CONF_ATTN_BIT_EN); 1550 1551 DP(NETIF_MSG_INTR, "write %x to IGU\n", val); 1552 1553 /* flush all outstanding writes */ 1554 mmiowb(); 1555 1556 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1557 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 1558 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1559} 1560 1561void bnx2x_int_disable(struct bnx2x *bp) 1562{ 1563 if (bp->common.int_block == INT_BLOCK_HC) 1564 bnx2x_hc_int_disable(bp); 1565 else 1566 bnx2x_igu_int_disable(bp); 1567} 1568 1569void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1570{ 1571 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1572 int i, offset; 1573 1574 if (disable_hw) 1575 /* prevent the HW from sending interrupts */ 1576 bnx2x_int_disable(bp); 1577 1578 /* make sure all ISRs are done */ 1579 if (msix) { 1580 synchronize_irq(bp->msix_table[0].vector); 1581 offset = 1; 1582#ifdef BCM_CNIC 1583 offset++; 1584#endif 1585 for_each_eth_queue(bp, i) 1586 synchronize_irq(bp->msix_table[offset++].vector); 1587 } else 1588 synchronize_irq(bp->pdev->irq); 1589 1590 /* make sure sp_task is not running */ 1591 cancel_delayed_work(&bp->sp_task); 1592 cancel_delayed_work(&bp->period_task); 1593 flush_workqueue(bnx2x_wq); 1594} 1595 1596/* fast path */ 1597 1598/* 1599 * General service functions 1600 */ 1601 1602/* Return true if succeeded to acquire the lock */ 1603static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1604{ 1605 u32 lock_status; 1606 u32 resource_bit = (1 << resource); 1607 int func = BP_FUNC(bp); 1608 u32 hw_lock_control_reg; 1609 1610 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource); 1611 1612 /* Validating that the resource is within range */ 1613 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1614 DP(NETIF_MSG_HW, 1615 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1616 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1617 return false; 1618 } 1619 1620 if (func <= 5) 1621 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1622 else 1623 hw_lock_control_reg = 1624 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1625 1626 /* Try to acquire the lock */ 1627 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1628 lock_status = REG_RD(bp, hw_lock_control_reg); 1629 if (lock_status & resource_bit) 1630 return true; 1631 1632 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource); 1633 return false; 1634} 1635 1636/** 1637 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1638 * 1639 * @bp: driver handle 1640 * 1641 * Returns the recovery leader resource id according to the engine this function 1642 * belongs to. Currently only only 2 engines is supported. 1643 */ 1644static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1645{ 1646 if (BP_PATH(bp)) 1647 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1648 else 1649 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1650} 1651 1652/** 1653 * bnx2x_trylock_leader_lock- try to aquire a leader lock. 1654 * 1655 * @bp: driver handle 1656 * 1657 * Tries to aquire a leader lock for cuurent engine. 1658 */ 1659static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1660{ 1661 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1662} 1663 1664#ifdef BCM_CNIC 1665static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1666#endif 1667 1668void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1669{ 1670 struct bnx2x *bp = fp->bp; 1671 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1672 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1673 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1674 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj; 1675 1676 DP(BNX2X_MSG_SP, 1677 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1678 fp->index, cid, command, bp->state, 1679 rr_cqe->ramrod_cqe.ramrod_type); 1680 1681 switch (command) { 1682 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1683 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1684 drv_cmd = BNX2X_Q_CMD_UPDATE; 1685 break; 1686 1687 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1688 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1689 drv_cmd = BNX2X_Q_CMD_SETUP; 1690 break; 1691 1692 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1693 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1694 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1695 break; 1696 1697 case (RAMROD_CMD_ID_ETH_HALT): 1698 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1699 drv_cmd = BNX2X_Q_CMD_HALT; 1700 break; 1701 1702 case (RAMROD_CMD_ID_ETH_TERMINATE): 1703 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); 1704 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1705 break; 1706 1707 case (RAMROD_CMD_ID_ETH_EMPTY): 1708 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1709 drv_cmd = BNX2X_Q_CMD_EMPTY; 1710 break; 1711 1712 default: 1713 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1714 command, fp->index); 1715 return; 1716 } 1717 1718 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1719 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1720 /* q_obj->complete_cmd() failure means that this was 1721 * an unexpected completion. 1722 * 1723 * In this case we don't want to increase the bp->spq_left 1724 * because apparently we haven't sent this command the first 1725 * place. 1726 */ 1727#ifdef BNX2X_STOP_ON_ERROR 1728 bnx2x_panic(); 1729#else 1730 return; 1731#endif 1732 1733 smp_mb__before_atomic_inc(); 1734 atomic_inc(&bp->cq_spq_left); 1735 /* push the change in bp->spq_left and towards the memory */ 1736 smp_mb__after_atomic_inc(); 1737 1738 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1739 1740 return; 1741} 1742 1743void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 1744 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) 1745{ 1746 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; 1747 1748 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, 1749 start); 1750} 1751 1752irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1753{ 1754 struct bnx2x *bp = netdev_priv(dev_instance); 1755 u16 status = bnx2x_ack_int(bp); 1756 u16 mask; 1757 int i; 1758 u8 cos; 1759 1760 /* Return here if interrupt is shared and it's not for us */ 1761 if (unlikely(status == 0)) { 1762 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1763 return IRQ_NONE; 1764 } 1765 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1766 1767#ifdef BNX2X_STOP_ON_ERROR 1768 if (unlikely(bp->panic)) 1769 return IRQ_HANDLED; 1770#endif 1771 1772 for_each_eth_queue(bp, i) { 1773 struct bnx2x_fastpath *fp = &bp->fp[i]; 1774 1775 mask = 0x2 << (fp->index + CNIC_PRESENT); 1776 if (status & mask) { 1777 /* Handle Rx or Tx according to SB id */ 1778 prefetch(fp->rx_cons_sb); 1779 for_each_cos_in_tx_queue(fp, cos) 1780 prefetch(fp->txdata[cos].tx_cons_sb); 1781 prefetch(&fp->sb_running_index[SM_RX_ID]); 1782 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 1783 status &= ~mask; 1784 } 1785 } 1786 1787#ifdef BCM_CNIC 1788 mask = 0x2; 1789 if (status & (mask | 0x1)) { 1790 struct cnic_ops *c_ops = NULL; 1791 1792 if (likely(bp->state == BNX2X_STATE_OPEN)) { 1793 rcu_read_lock(); 1794 c_ops = rcu_dereference(bp->cnic_ops); 1795 if (c_ops) 1796 c_ops->cnic_handler(bp->cnic_data, NULL); 1797 rcu_read_unlock(); 1798 } 1799 1800 status &= ~mask; 1801 } 1802#endif 1803 1804 if (unlikely(status & 0x1)) { 1805 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1806 1807 status &= ~0x1; 1808 if (!status) 1809 return IRQ_HANDLED; 1810 } 1811 1812 if (unlikely(status)) 1813 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1814 status); 1815 1816 return IRQ_HANDLED; 1817} 1818 1819/* Link */ 1820 1821/* 1822 * General service functions 1823 */ 1824 1825int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 1826{ 1827 u32 lock_status; 1828 u32 resource_bit = (1 << resource); 1829 int func = BP_FUNC(bp); 1830 u32 hw_lock_control_reg; 1831 int cnt; 1832 1833 /* Validating that the resource is within range */ 1834 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1835 DP(NETIF_MSG_HW, 1836 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1837 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1838 return -EINVAL; 1839 } 1840 1841 if (func <= 5) { 1842 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1843 } else { 1844 hw_lock_control_reg = 1845 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1846 } 1847 1848 /* Validating that the resource is not already taken */ 1849 lock_status = REG_RD(bp, hw_lock_control_reg); 1850 if (lock_status & resource_bit) { 1851 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1852 lock_status, resource_bit); 1853 return -EEXIST; 1854 } 1855 1856 /* Try for 5 second every 5ms */ 1857 for (cnt = 0; cnt < 1000; cnt++) { 1858 /* Try to acquire the lock */ 1859 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1860 lock_status = REG_RD(bp, hw_lock_control_reg); 1861 if (lock_status & resource_bit) 1862 return 0; 1863 1864 msleep(5); 1865 } 1866 DP(NETIF_MSG_HW, "Timeout\n"); 1867 return -EAGAIN; 1868} 1869 1870int bnx2x_release_leader_lock(struct bnx2x *bp) 1871{ 1872 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1873} 1874 1875int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 1876{ 1877 u32 lock_status; 1878 u32 resource_bit = (1 << resource); 1879 int func = BP_FUNC(bp); 1880 u32 hw_lock_control_reg; 1881 1882 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource); 1883 1884 /* Validating that the resource is within range */ 1885 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1886 DP(NETIF_MSG_HW, 1887 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1888 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1889 return -EINVAL; 1890 } 1891 1892 if (func <= 5) { 1893 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1894 } else { 1895 hw_lock_control_reg = 1896 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1897 } 1898 1899 /* Validating that the resource is currently taken */ 1900 lock_status = REG_RD(bp, hw_lock_control_reg); 1901 if (!(lock_status & resource_bit)) { 1902 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1903 lock_status, resource_bit); 1904 return -EFAULT; 1905 } 1906 1907 REG_WR(bp, hw_lock_control_reg, resource_bit); 1908 return 0; 1909} 1910 1911 1912int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 1913{ 1914 /* The GPIO should be swapped if swap register is set and active */ 1915 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1916 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1917 int gpio_shift = gpio_num + 1918 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1919 u32 gpio_mask = (1 << gpio_shift); 1920 u32 gpio_reg; 1921 int value; 1922 1923 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1924 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1925 return -EINVAL; 1926 } 1927 1928 /* read GPIO value */ 1929 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1930 1931 /* get the requested pin value */ 1932 if ((gpio_reg & gpio_mask) == gpio_mask) 1933 value = 1; 1934 else 1935 value = 0; 1936 1937 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); 1938 1939 return value; 1940} 1941 1942int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 1943{ 1944 /* The GPIO should be swapped if swap register is set and active */ 1945 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1946 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1947 int gpio_shift = gpio_num + 1948 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1949 u32 gpio_mask = (1 << gpio_shift); 1950 u32 gpio_reg; 1951 1952 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1953 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1954 return -EINVAL; 1955 } 1956 1957 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1958 /* read GPIO and mask except the float bits */ 1959 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 1960 1961 switch (mode) { 1962 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1963 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n", 1964 gpio_num, gpio_shift); 1965 /* clear FLOAT and set CLR */ 1966 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1967 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 1968 break; 1969 1970 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 1971 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n", 1972 gpio_num, gpio_shift); 1973 /* clear FLOAT and set SET */ 1974 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1975 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 1976 break; 1977 1978 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 1979 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", 1980 gpio_num, gpio_shift); 1981 /* set FLOAT */ 1982 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1983 break; 1984 1985 default: 1986 break; 1987 } 1988 1989 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 1990 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1991 1992 return 0; 1993} 1994 1995int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 1996{ 1997 u32 gpio_reg = 0; 1998 int rc = 0; 1999 2000 /* Any port swapping should be handled by caller. */ 2001 2002 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2003 /* read GPIO and mask except the float bits */ 2004 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 2005 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2006 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 2007 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 2008 2009 switch (mode) { 2010 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2011 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 2012 /* set CLR */ 2013 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2014 break; 2015 2016 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2017 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 2018 /* set SET */ 2019 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2020 break; 2021 2022 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2023 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2024 /* set FLOAT */ 2025 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2026 break; 2027 2028 default: 2029 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2030 rc = -EINVAL; 2031 break; 2032 } 2033 2034 if (rc == 0) 2035 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2036 2037 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2038 2039 return rc; 2040} 2041 2042int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2043{ 2044 /* The GPIO should be swapped if swap register is set and active */ 2045 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2046 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2047 int gpio_shift = gpio_num + 2048 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2049 u32 gpio_mask = (1 << gpio_shift); 2050 u32 gpio_reg; 2051 2052 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2053 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2054 return -EINVAL; 2055 } 2056 2057 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2058 /* read GPIO int */ 2059 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2060 2061 switch (mode) { 2062 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2063 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> " 2064 "output low\n", gpio_num, gpio_shift); 2065 /* clear SET and set CLR */ 2066 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2067 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2068 break; 2069 2070 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2071 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> " 2072 "output high\n", gpio_num, gpio_shift); 2073 /* clear CLR and set SET */ 2074 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2075 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2076 break; 2077 2078 default: 2079 break; 2080 } 2081 2082 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2083 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2084 2085 return 0; 2086} 2087 2088static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) 2089{ 2090 u32 spio_mask = (1 << spio_num); 2091 u32 spio_reg; 2092 2093 if ((spio_num < MISC_REGISTERS_SPIO_4) || 2094 (spio_num > MISC_REGISTERS_SPIO_7)) { 2095 BNX2X_ERR("Invalid SPIO %d\n", spio_num); 2096 return -EINVAL; 2097 } 2098 2099 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2100 /* read SPIO and mask except the float bits */ 2101 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); 2102 2103 switch (mode) { 2104 case MISC_REGISTERS_SPIO_OUTPUT_LOW: 2105 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); 2106 /* clear FLOAT and set CLR */ 2107 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2108 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); 2109 break; 2110 2111 case MISC_REGISTERS_SPIO_OUTPUT_HIGH: 2112 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); 2113 /* clear FLOAT and set SET */ 2114 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2115 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); 2116 break; 2117 2118 case MISC_REGISTERS_SPIO_INPUT_HI_Z: 2119 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num); 2120 /* set FLOAT */ 2121 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2122 break; 2123 2124 default: 2125 break; 2126 } 2127 2128 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2129 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2130 2131 return 0; 2132} 2133 2134void bnx2x_calc_fc_adv(struct bnx2x *bp) 2135{ 2136 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2137 switch (bp->link_vars.ieee_fc & 2138 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2139 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 2140 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2141 ADVERTISED_Pause); 2142 break; 2143 2144 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2145 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2146 ADVERTISED_Pause); 2147 break; 2148 2149 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2150 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2151 break; 2152 2153 default: 2154 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2155 ADVERTISED_Pause); 2156 break; 2157 } 2158} 2159 2160u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2161{ 2162 if (!BP_NOMCP(bp)) { 2163 u8 rc; 2164 int cfx_idx = bnx2x_get_link_cfg_idx(bp); 2165 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2166 /* 2167 * Initialize link parameters structure variables 2168 * It is recommended to turn off RX FC for jumbo frames 2169 * for better performance 2170 */ 2171 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2172 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2173 else 2174 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2175 2176 bnx2x_acquire_phy_lock(bp); 2177 2178 if (load_mode == LOAD_DIAG) { 2179 struct link_params *lp = &bp->link_params; 2180 lp->loopback_mode = LOOPBACK_XGXS; 2181 /* do PHY loopback at 10G speed, if possible */ 2182 if (lp->req_line_speed[cfx_idx] < SPEED_10000) { 2183 if (lp->speed_cap_mask[cfx_idx] & 2184 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2185 lp->req_line_speed[cfx_idx] = 2186 SPEED_10000; 2187 else 2188 lp->req_line_speed[cfx_idx] = 2189 SPEED_1000; 2190 } 2191 } 2192 2193 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2194 2195 bnx2x_release_phy_lock(bp); 2196 2197 bnx2x_calc_fc_adv(bp); 2198 2199 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { 2200 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2201 bnx2x_link_report(bp); 2202 } else 2203 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2204 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2205 return rc; 2206 } 2207 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2208 return -EINVAL; 2209} 2210 2211void bnx2x_link_set(struct bnx2x *bp) 2212{ 2213 if (!BP_NOMCP(bp)) { 2214 bnx2x_acquire_phy_lock(bp); 2215 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2216 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2217 bnx2x_release_phy_lock(bp); 2218 2219 bnx2x_calc_fc_adv(bp); 2220 } else 2221 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2222} 2223 2224static void bnx2x__link_reset(struct bnx2x *bp) 2225{ 2226 if (!BP_NOMCP(bp)) { 2227 bnx2x_acquire_phy_lock(bp); 2228 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2229 bnx2x_release_phy_lock(bp); 2230 } else 2231 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2232} 2233 2234u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2235{ 2236 u8 rc = 0; 2237 2238 if (!BP_NOMCP(bp)) { 2239 bnx2x_acquire_phy_lock(bp); 2240 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2241 is_serdes); 2242 bnx2x_release_phy_lock(bp); 2243 } else 2244 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2245 2246 return rc; 2247} 2248 2249static void bnx2x_init_port_minmax(struct bnx2x *bp) 2250{ 2251 u32 r_param = bp->link_vars.line_speed / 8; 2252 u32 fair_periodic_timeout_usec; 2253 u32 t_fair; 2254 2255 memset(&(bp->cmng.rs_vars), 0, 2256 sizeof(struct rate_shaping_vars_per_port)); 2257 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port)); 2258 2259 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ 2260 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4; 2261 2262 /* this is the threshold below which no timer arming will occur 2263 1.25 coefficient is for the threshold to be a little bigger 2264 than the real time, to compensate for timer in-accuracy */ 2265 bp->cmng.rs_vars.rs_threshold = 2266 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; 2267 2268 /* resolution of fairness timer */ 2269 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; 2270 /* for 10G it is 1000usec. for 1G it is 10000usec. */ 2271 t_fair = T_FAIR_COEF / bp->link_vars.line_speed; 2272 2273 /* this is the threshold below which we won't arm the timer anymore */ 2274 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES; 2275 2276 /* we multiply by 1e3/8 to get bytes/msec. 2277 We don't want the credits to pass a credit 2278 of the t_fair*FAIR_MEM (algorithm resolution) */ 2279 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM; 2280 /* since each tick is 4 usec */ 2281 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4; 2282} 2283 2284/* Calculates the sum of vn_min_rates. 2285 It's needed for further normalizing of the min_rates. 2286 Returns: 2287 sum of vn_min_rates. 2288 or 2289 0 - if all the min_rates are 0. 2290 In the later case fainess algorithm should be deactivated. 2291 If not all min_rates are zero then those that are zeroes will be set to 1. 2292 */ 2293static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) 2294{ 2295 int all_zero = 1; 2296 int vn; 2297 2298 bp->vn_weight_sum = 0; 2299 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2300 u32 vn_cfg = bp->mf_config[vn]; 2301 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2302 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2303 2304 /* Skip hidden vns */ 2305 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2306 continue; 2307 2308 /* If min rate is zero - set it to 1 */ 2309 if (!vn_min_rate) 2310 vn_min_rate = DEF_MIN_RATE; 2311 else 2312 all_zero = 0; 2313 2314 bp->vn_weight_sum += vn_min_rate; 2315 } 2316 2317 /* if ETS or all min rates are zeros - disable fairness */ 2318 if (BNX2X_IS_ETS_ENABLED(bp)) { 2319 bp->cmng.flags.cmng_enables &= 2320 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2321 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2322 } else if (all_zero) { 2323 bp->cmng.flags.cmng_enables &= 2324 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2325 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2326 " fairness will be disabled\n"); 2327 } else 2328 bp->cmng.flags.cmng_enables |= 2329 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2330} 2331 2332static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) 2333{ 2334 struct rate_shaping_vars_per_vn m_rs_vn; 2335 struct fairness_vars_per_vn m_fair_vn; 2336 u32 vn_cfg = bp->mf_config[vn]; 2337 int func = func_by_vn(bp, vn); 2338 u16 vn_min_rate, vn_max_rate; 2339 int i; 2340 2341 /* If function is hidden - set min and max to zeroes */ 2342 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 2343 vn_min_rate = 0; 2344 vn_max_rate = 0; 2345 2346 } else { 2347 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2348 2349 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2350 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2351 /* If fairness is enabled (not all min rates are zeroes) and 2352 if current min rate is zero - set it to 1. 2353 This is a requirement of the algorithm. */ 2354 if (bp->vn_weight_sum && (vn_min_rate == 0)) 2355 vn_min_rate = DEF_MIN_RATE; 2356 2357 if (IS_MF_SI(bp)) 2358 /* maxCfg in percents of linkspeed */ 2359 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2360 else 2361 /* maxCfg is absolute in 100Mb units */ 2362 vn_max_rate = maxCfg * 100; 2363 } 2364 2365 DP(NETIF_MSG_IFUP, 2366 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n", 2367 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); 2368 2369 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn)); 2370 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); 2371 2372 /* global vn counter - maximal Mbps for this vn */ 2373 m_rs_vn.vn_counter.rate = vn_max_rate; 2374 2375 /* quota - number of bytes transmitted in this period */ 2376 m_rs_vn.vn_counter.quota = 2377 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8; 2378 2379 if (bp->vn_weight_sum) { 2380 /* credit for each period of the fairness algorithm: 2381 number of bytes in T_FAIR (the vn share the port rate). 2382 vn_weight_sum should not be larger than 10000, thus 2383 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater 2384 than zero */ 2385 m_fair_vn.vn_credit_delta = 2386 max_t(u32, (vn_min_rate * (T_FAIR_COEF / 2387 (8 * bp->vn_weight_sum))), 2388 (bp->cmng.fair_vars.fair_threshold + 2389 MIN_ABOVE_THRESH)); 2390 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n", 2391 m_fair_vn.vn_credit_delta); 2392 } 2393 2394 /* Store it to internal memory */ 2395 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++) 2396 REG_WR(bp, BAR_XSTRORM_INTMEM + 2397 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4, 2398 ((u32 *)(&m_rs_vn))[i]); 2399 2400 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++) 2401 REG_WR(bp, BAR_XSTRORM_INTMEM + 2402 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4, 2403 ((u32 *)(&m_fair_vn))[i]); 2404} 2405 2406static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2407{ 2408 if (CHIP_REV_IS_SLOW(bp)) 2409 return CMNG_FNS_NONE; 2410 if (IS_MF(bp)) 2411 return CMNG_FNS_MINMAX; 2412 2413 return CMNG_FNS_NONE; 2414} 2415 2416void bnx2x_read_mf_cfg(struct bnx2x *bp) 2417{ 2418 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2419 2420 if (BP_NOMCP(bp)) 2421 return; /* what should be the default bvalue in this case */ 2422 2423 /* For 2 port configuration the absolute function number formula 2424 * is: 2425 * abs_func = 2 * vn + BP_PORT + BP_PATH 2426 * 2427 * and there are 4 functions per port 2428 * 2429 * For 4 port configuration it is 2430 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2431 * 2432 * and there are 2 functions per port 2433 */ 2434 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2435 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2436 2437 if (func >= E1H_FUNC_MAX) 2438 break; 2439 2440 bp->mf_config[vn] = 2441 MF_CFG_RD(bp, func_mf_config[func].config); 2442 } 2443} 2444 2445static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2446{ 2447 2448 if (cmng_type == CMNG_FNS_MINMAX) { 2449 int vn; 2450 2451 /* clear cmng_enables */ 2452 bp->cmng.flags.cmng_enables = 0; 2453 2454 /* read mf conf from shmem */ 2455 if (read_cfg) 2456 bnx2x_read_mf_cfg(bp); 2457 2458 /* Init rate shaping and fairness contexts */ 2459 bnx2x_init_port_minmax(bp); 2460 2461 /* vn_weight_sum and enable fairness if not 0 */ 2462 bnx2x_calc_vn_weight_sum(bp); 2463 2464 /* calculate and set min-max rate for each vn */ 2465 if (bp->port.pmf) 2466 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) 2467 bnx2x_init_vn_minmax(bp, vn); 2468 2469 /* always enable rate shaping and fairness */ 2470 bp->cmng.flags.cmng_enables |= 2471 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2472 if (!bp->vn_weight_sum) 2473 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2474 " fairness will be disabled\n"); 2475 return; 2476 } 2477 2478 /* rate shaping and fairness are disabled */ 2479 DP(NETIF_MSG_IFUP, 2480 "rate shaping and fairness are disabled\n"); 2481} 2482 2483/* This function is called upon link interrupt */ 2484static void bnx2x_link_attn(struct bnx2x *bp) 2485{ 2486 /* Make sure that we are synced with the current statistics */ 2487 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2488 2489 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2490 2491 if (bp->link_vars.link_up) { 2492 2493 /* dropless flow control */ 2494 if (!CHIP_IS_E1(bp) && bp->dropless_fc) { 2495 int port = BP_PORT(bp); 2496 u32 pause_enabled = 0; 2497 2498 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2499 pause_enabled = 1; 2500 2501 REG_WR(bp, BAR_USTRORM_INTMEM + 2502 USTORM_ETH_PAUSE_ENABLED_OFFSET(port), 2503 pause_enabled); 2504 } 2505 2506 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2507 struct host_port_stats *pstats; 2508 2509 pstats = bnx2x_sp(bp, port_stats); 2510 /* reset old mac stats */ 2511 memset(&(pstats->mac_stx[0]), 0, 2512 sizeof(struct mac_stx)); 2513 } 2514 if (bp->state == BNX2X_STATE_OPEN) 2515 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2516 } 2517 2518 if (bp->link_vars.link_up && bp->link_vars.line_speed) { 2519 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2520 2521 if (cmng_fns != CMNG_FNS_NONE) { 2522 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2523 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2524 } else 2525 /* rate shaping and fairness are disabled */ 2526 DP(NETIF_MSG_IFUP, 2527 "single function mode without fairness\n"); 2528 } 2529 2530 __bnx2x_link_report(bp); 2531 2532 if (IS_MF(bp)) 2533 bnx2x_link_sync_notify(bp); 2534} 2535 2536void bnx2x__link_status_update(struct bnx2x *bp) 2537{ 2538 if (bp->state != BNX2X_STATE_OPEN) 2539 return; 2540 2541 /* read updated dcb configuration */ 2542 bnx2x_dcbx_pmf_update(bp); 2543 2544 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2545 2546 if (bp->link_vars.link_up) 2547 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2548 else 2549 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2550 2551 /* indicate link status */ 2552 bnx2x_link_report(bp); 2553} 2554 2555static void bnx2x_pmf_update(struct bnx2x *bp) 2556{ 2557 int port = BP_PORT(bp); 2558 u32 val; 2559 2560 bp->port.pmf = 1; 2561 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf); 2562 2563 /* 2564 * We need the mb() to ensure the ordering between the writing to 2565 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2566 */ 2567 smp_mb(); 2568 2569 /* queue a periodic task */ 2570 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2571 2572 bnx2x_dcbx_pmf_update(bp); 2573 2574 /* enable nig attention */ 2575 val = (0xff0f | (1 << (BP_VN(bp) + 4))); 2576 if (bp->common.int_block == INT_BLOCK_HC) { 2577 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 2578 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 2579 } else if (!CHIP_IS_E1x(bp)) { 2580 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 2581 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 2582 } 2583 2584 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 2585} 2586 2587/* end of Link */ 2588 2589/* slow path */ 2590 2591/* 2592 * General service functions 2593 */ 2594 2595/* send the MCP a request, block until there is a reply */ 2596u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 2597{ 2598 int mb_idx = BP_FW_MB_IDX(bp); 2599 u32 seq; 2600 u32 rc = 0; 2601 u32 cnt = 1; 2602 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 2603 2604 mutex_lock(&bp->fw_mb_mutex); 2605 seq = ++bp->fw_seq; 2606 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 2607 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 2608 2609 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 2610 (command | seq), param); 2611 2612 do { 2613 /* let the FW do it's magic ... */ 2614 msleep(delay); 2615 2616 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 2617 2618 /* Give the FW up to 5 second (500*10ms) */ 2619 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2620 2621 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 2622 cnt*delay, rc, seq); 2623 2624 /* is this a reply to our command? */ 2625 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 2626 rc &= FW_MSG_CODE_MASK; 2627 else { 2628 /* FW BUG! */ 2629 BNX2X_ERR("FW failed to respond!\n"); 2630 bnx2x_fw_dump(bp); 2631 rc = 0; 2632 } 2633 mutex_unlock(&bp->fw_mb_mutex); 2634 2635 return rc; 2636} 2637 2638 2639void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 2640{ 2641 if (CHIP_IS_E1x(bp)) { 2642 struct tstorm_eth_function_common_config tcfg = {0}; 2643 2644 storm_memset_func_cfg(bp, &tcfg, p->func_id); 2645 } 2646 2647 /* Enable the function in the FW */ 2648 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 2649 storm_memset_func_en(bp, p->func_id, 1); 2650 2651 /* spq */ 2652 if (p->func_flgs & FUNC_FLG_SPQ) { 2653 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 2654 REG_WR(bp, XSEM_REG_FAST_MEMORY + 2655 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 2656 } 2657} 2658 2659/** 2660 * bnx2x_get_tx_only_flags - Return common flags 2661 * 2662 * @bp device handle 2663 * @fp queue handle 2664 * @zero_stats TRUE if statistics zeroing is needed 2665 * 2666 * Return the flags that are common for the Tx-only and not normal connections. 2667 */ 2668static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 2669 struct bnx2x_fastpath *fp, 2670 bool zero_stats) 2671{ 2672 unsigned long flags = 0; 2673 2674 /* PF driver will always initialize the Queue to an ACTIVE state */ 2675 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 2676 2677 /* tx only connections collect statistics (on the same index as the 2678 * parent connection). The statistics are zeroed when the parent 2679 * connection is initialized. 2680 */ 2681 2682 __set_bit(BNX2X_Q_FLG_STATS, &flags); 2683 if (zero_stats) 2684 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 2685 2686 2687 return flags; 2688} 2689 2690static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 2691 struct bnx2x_fastpath *fp, 2692 bool leading) 2693{ 2694 unsigned long flags = 0; 2695 2696 /* calculate other queue flags */ 2697 if (IS_MF_SD(bp)) 2698 __set_bit(BNX2X_Q_FLG_OV, &flags); 2699 2700 if (IS_FCOE_FP(fp)) 2701 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 2702 2703 if (!fp->disable_tpa) { 2704 __set_bit(BNX2X_Q_FLG_TPA, &flags); 2705 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 2706 } 2707 2708 if (leading) { 2709 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 2710 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 2711 } 2712 2713 /* Always set HW VLAN stripping */ 2714 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 2715 2716 2717 return flags | bnx2x_get_common_flags(bp, fp, true); 2718} 2719 2720static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 2721 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 2722 u8 cos) 2723{ 2724 gen_init->stat_id = bnx2x_stats_id(fp); 2725 gen_init->spcl_id = fp->cl_id; 2726 2727 /* Always use mini-jumbo MTU for FCoE L2 ring */ 2728 if (IS_FCOE_FP(fp)) 2729 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 2730 else 2731 gen_init->mtu = bp->dev->mtu; 2732 2733 gen_init->cos = cos; 2734} 2735 2736static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 2737 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 2738 struct bnx2x_rxq_setup_params *rxq_init) 2739{ 2740 u8 max_sge = 0; 2741 u16 sge_sz = 0; 2742 u16 tpa_agg_size = 0; 2743 2744 if (!fp->disable_tpa) { 2745 pause->sge_th_lo = SGE_TH_LO(bp); 2746 pause->sge_th_hi = SGE_TH_HI(bp); 2747 2748 /* validate SGE ring has enough to cross high threshold */ 2749 WARN_ON(bp->dropless_fc && 2750 pause->sge_th_hi + FW_PREFETCH_CNT > 2751 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); 2752 2753 tpa_agg_size = min_t(u32, 2754 (min_t(u32, 8, MAX_SKB_FRAGS) * 2755 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); 2756 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 2757 SGE_PAGE_SHIFT; 2758 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 2759 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 2760 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, 2761 0xffff); 2762 } 2763 2764 /* pause - not for e1 */ 2765 if (!CHIP_IS_E1(bp)) { 2766 pause->bd_th_lo = BD_TH_LO(bp); 2767 pause->bd_th_hi = BD_TH_HI(bp); 2768 2769 pause->rcq_th_lo = RCQ_TH_LO(bp); 2770 pause->rcq_th_hi = RCQ_TH_HI(bp); 2771 /* 2772 * validate that rings have enough entries to cross 2773 * high thresholds 2774 */ 2775 WARN_ON(bp->dropless_fc && 2776 pause->bd_th_hi + FW_PREFETCH_CNT > 2777 bp->rx_ring_size); 2778 WARN_ON(bp->dropless_fc && 2779 pause->rcq_th_hi + FW_PREFETCH_CNT > 2780 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); 2781 2782 pause->pri_map = 1; 2783 } 2784 2785 /* rxq setup */ 2786 rxq_init->dscr_map = fp->rx_desc_mapping; 2787 rxq_init->sge_map = fp->rx_sge_mapping; 2788 rxq_init->rcq_map = fp->rx_comp_mapping; 2789 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 2790 2791 /* This should be a maximum number of data bytes that may be 2792 * placed on the BD (not including paddings). 2793 */ 2794 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - 2795 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; 2796 2797 rxq_init->cl_qzone_id = fp->cl_qzone_id; 2798 rxq_init->tpa_agg_sz = tpa_agg_size; 2799 rxq_init->sge_buf_sz = sge_sz; 2800 rxq_init->max_sges_pkt = max_sge; 2801 rxq_init->rss_engine_id = BP_FUNC(bp); 2802 2803 /* Maximum number or simultaneous TPA aggregation for this Queue. 2804 * 2805 * For PF Clients it should be the maximum avaliable number. 2806 * VF driver(s) may want to define it to a smaller value. 2807 */ 2808 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); 2809 2810 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 2811 rxq_init->fw_sb_id = fp->fw_sb_id; 2812 2813 if (IS_FCOE_FP(fp)) 2814 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 2815 else 2816 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 2817} 2818 2819static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 2820 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 2821 u8 cos) 2822{ 2823 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping; 2824 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 2825 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 2826 txq_init->fw_sb_id = fp->fw_sb_id; 2827 2828 /* 2829 * set the tss leading client id for TX classfication == 2830 * leading RSS client id 2831 */ 2832 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 2833 2834 if (IS_FCOE_FP(fp)) { 2835 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 2836 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 2837 } 2838} 2839 2840static void bnx2x_pf_init(struct bnx2x *bp) 2841{ 2842 struct bnx2x_func_init_params func_init = {0}; 2843 struct event_ring_data eq_data = { {0} }; 2844 u16 flags; 2845 2846 if (!CHIP_IS_E1x(bp)) { 2847 /* reset IGU PF statistics: MSIX + ATTN */ 2848 /* PF */ 2849 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2850 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2851 (CHIP_MODE_IS_4_PORT(bp) ? 2852 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2853 /* ATTN */ 2854 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2855 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2856 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 2857 (CHIP_MODE_IS_4_PORT(bp) ? 2858 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2859 } 2860 2861 /* function setup flags */ 2862 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 2863 2864 /* This flag is relevant for E1x only. 2865 * E2 doesn't have a TPA configuration in a function level. 2866 */ 2867 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; 2868 2869 func_init.func_flgs = flags; 2870 func_init.pf_id = BP_FUNC(bp); 2871 func_init.func_id = BP_FUNC(bp); 2872 func_init.spq_map = bp->spq_mapping; 2873 func_init.spq_prod = bp->spq_prod_idx; 2874 2875 bnx2x_func_init(bp, &func_init); 2876 2877 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 2878 2879 /* 2880 * Congestion management values depend on the link rate 2881 * There is no active link so initial link rate is set to 10 Gbps. 2882 * When the link comes up The congestion management values are 2883 * re-calculated according to the actual link rate. 2884 */ 2885 bp->link_vars.line_speed = SPEED_10000; 2886 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 2887 2888 /* Only the PMF sets the HW */ 2889 if (bp->port.pmf) 2890 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2891 2892 /* init Event Queue */ 2893 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 2894 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 2895 eq_data.producer = bp->eq_prod; 2896 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 2897 eq_data.sb_id = DEF_SB_ID; 2898 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 2899} 2900 2901 2902static void bnx2x_e1h_disable(struct bnx2x *bp) 2903{ 2904 int port = BP_PORT(bp); 2905 2906 bnx2x_tx_disable(bp); 2907 2908 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 2909} 2910 2911static void bnx2x_e1h_enable(struct bnx2x *bp) 2912{ 2913 int port = BP_PORT(bp); 2914 2915 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 2916 2917 /* Tx queue should be only reenabled */ 2918 netif_tx_wake_all_queues(bp->dev); 2919 2920 /* 2921 * Should not call netif_carrier_on since it will be called if the link 2922 * is up when checking for link state 2923 */ 2924} 2925 2926#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 2927 2928static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) 2929{ 2930 struct eth_stats_info *ether_stat = 2931 &bp->slowpath->drv_info_to_mcp.ether_stat; 2932 2933 /* leave last char as NULL */ 2934 memcpy(ether_stat->version, DRV_MODULE_VERSION, 2935 ETH_STAT_INFO_VERSION_LEN - 1); 2936 2937 bp->fp[0].mac_obj.get_n_elements(bp, &bp->fp[0].mac_obj, 2938 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 2939 ether_stat->mac_local); 2940 2941 ether_stat->mtu_size = bp->dev->mtu; 2942 2943 if (bp->dev->features & NETIF_F_RXCSUM) 2944 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 2945 if (bp->dev->features & NETIF_F_TSO) 2946 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 2947 ether_stat->feature_flags |= bp->common.boot_mode; 2948 2949 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; 2950 2951 ether_stat->txq_size = bp->tx_ring_size; 2952 ether_stat->rxq_size = bp->rx_ring_size; 2953} 2954 2955static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) 2956{ 2957#ifdef BCM_CNIC 2958 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 2959 struct fcoe_stats_info *fcoe_stat = 2960 &bp->slowpath->drv_info_to_mcp.fcoe_stat; 2961 2962 memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN); 2963 2964 fcoe_stat->qos_priority = 2965 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; 2966 2967 /* insert FCoE stats from ramrod response */ 2968 if (!NO_FCOE(bp)) { 2969 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = 2970 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2971 tstorm_queue_statistics; 2972 2973 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = 2974 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2975 xstorm_queue_statistics; 2976 2977 struct fcoe_statistics_params *fw_fcoe_stat = 2978 &bp->fw_stats_data->fcoe; 2979 2980 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo, 2981 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); 2982 2983 ADD_64(fcoe_stat->rx_bytes_hi, 2984 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, 2985 fcoe_stat->rx_bytes_lo, 2986 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); 2987 2988 ADD_64(fcoe_stat->rx_bytes_hi, 2989 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, 2990 fcoe_stat->rx_bytes_lo, 2991 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); 2992 2993 ADD_64(fcoe_stat->rx_bytes_hi, 2994 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, 2995 fcoe_stat->rx_bytes_lo, 2996 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); 2997 2998 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2999 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); 3000 3001 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3002 fcoe_q_tstorm_stats->rcv_ucast_pkts); 3003 3004 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3005 fcoe_q_tstorm_stats->rcv_bcast_pkts); 3006 3007 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3008 fcoe_q_tstorm_stats->rcv_mcast_pkts); 3009 3010 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo, 3011 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); 3012 3013 ADD_64(fcoe_stat->tx_bytes_hi, 3014 fcoe_q_xstorm_stats->ucast_bytes_sent.hi, 3015 fcoe_stat->tx_bytes_lo, 3016 fcoe_q_xstorm_stats->ucast_bytes_sent.lo); 3017 3018 ADD_64(fcoe_stat->tx_bytes_hi, 3019 fcoe_q_xstorm_stats->bcast_bytes_sent.hi, 3020 fcoe_stat->tx_bytes_lo, 3021 fcoe_q_xstorm_stats->bcast_bytes_sent.lo); 3022 3023 ADD_64(fcoe_stat->tx_bytes_hi, 3024 fcoe_q_xstorm_stats->mcast_bytes_sent.hi, 3025 fcoe_stat->tx_bytes_lo, 3026 fcoe_q_xstorm_stats->mcast_bytes_sent.lo); 3027 3028 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3029 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); 3030 3031 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3032 fcoe_q_xstorm_stats->ucast_pkts_sent); 3033 3034 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3035 fcoe_q_xstorm_stats->bcast_pkts_sent); 3036 3037 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3038 fcoe_q_xstorm_stats->mcast_pkts_sent); 3039 } 3040 3041 /* ask L5 driver to add data to the struct */ 3042 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); 3043#endif 3044} 3045 3046static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) 3047{ 3048#ifdef BCM_CNIC 3049 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3050 struct iscsi_stats_info *iscsi_stat = 3051 &bp->slowpath->drv_info_to_mcp.iscsi_stat; 3052 3053 memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); 3054 3055 iscsi_stat->qos_priority = 3056 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; 3057 3058 /* ask L5 driver to add data to the struct */ 3059 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); 3060#endif 3061} 3062 3063/* called due to MCP event (on pmf): 3064 * reread new bandwidth configuration 3065 * configure FW 3066 * notify others function about the change 3067 */ 3068static inline void bnx2x_config_mf_bw(struct bnx2x *bp) 3069{ 3070 if (bp->link_vars.link_up) { 3071 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 3072 bnx2x_link_sync_notify(bp); 3073 } 3074 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3075} 3076 3077static inline void bnx2x_set_mf_bw(struct bnx2x *bp) 3078{ 3079 bnx2x_config_mf_bw(bp); 3080 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 3081} 3082 3083static void bnx2x_handle_drv_info_req(struct bnx2x *bp) 3084{ 3085 enum drv_info_opcode op_code; 3086 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); 3087 3088 /* if drv_info version supported by MFW doesn't match - send NACK */ 3089 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 3090 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3091 return; 3092 } 3093 3094 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 3095 DRV_INFO_CONTROL_OP_CODE_SHIFT; 3096 3097 memset(&bp->slowpath->drv_info_to_mcp, 0, 3098 sizeof(union drv_info_to_mcp)); 3099 3100 switch (op_code) { 3101 case ETH_STATS_OPCODE: 3102 bnx2x_drv_info_ether_stat(bp); 3103 break; 3104 case FCOE_STATS_OPCODE: 3105 bnx2x_drv_info_fcoe_stat(bp); 3106 break; 3107 case ISCSI_STATS_OPCODE: 3108 bnx2x_drv_info_iscsi_stat(bp); 3109 break; 3110 default: 3111 /* if op code isn't supported - send NACK */ 3112 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3113 return; 3114 } 3115 3116 /* if we got drv_info attn from MFW then these fields are defined in 3117 * shmem2 for sure 3118 */ 3119 SHMEM2_WR(bp, drv_info_host_addr_lo, 3120 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3121 SHMEM2_WR(bp, drv_info_host_addr_hi, 3122 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3123 3124 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); 3125} 3126 3127static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) 3128{ 3129 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); 3130 3131 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 3132 3133 /* 3134 * This is the only place besides the function initialization 3135 * where the bp->flags can change so it is done without any 3136 * locks 3137 */ 3138 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 3139 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n"); 3140 bp->flags |= MF_FUNC_DIS; 3141 3142 bnx2x_e1h_disable(bp); 3143 } else { 3144 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); 3145 bp->flags &= ~MF_FUNC_DIS; 3146 3147 bnx2x_e1h_enable(bp); 3148 } 3149 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 3150 } 3151 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 3152 bnx2x_config_mf_bw(bp); 3153 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 3154 } 3155 3156 /* Report results to MCP */ 3157 if (dcc_event) 3158 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); 3159 else 3160 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); 3161} 3162 3163/* must be called under the spq lock */ 3164static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 3165{ 3166 struct eth_spe *next_spe = bp->spq_prod_bd; 3167 3168 if (bp->spq_prod_bd == bp->spq_last_bd) { 3169 bp->spq_prod_bd = bp->spq; 3170 bp->spq_prod_idx = 0; 3171 DP(NETIF_MSG_TIMER, "end of spq\n"); 3172 } else { 3173 bp->spq_prod_bd++; 3174 bp->spq_prod_idx++; 3175 } 3176 return next_spe; 3177} 3178 3179/* must be called under the spq lock */ 3180static inline void bnx2x_sp_prod_update(struct bnx2x *bp) 3181{ 3182 int func = BP_FUNC(bp); 3183 3184 /* 3185 * Make sure that BD data is updated before writing the producer: 3186 * BD data is written to the memory, the producer is read from the 3187 * memory, thus we need a full memory barrier to ensure the ordering. 3188 */ 3189 mb(); 3190 3191 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3192 bp->spq_prod_idx); 3193 mmiowb(); 3194} 3195 3196/** 3197 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3198 * 3199 * @cmd: command to check 3200 * @cmd_type: command type 3201 */ 3202static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3203{ 3204 if ((cmd_type == NONE_CONNECTION_TYPE) || 3205 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3206 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3207 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3208 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3209 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3210 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3211 return true; 3212 else 3213 return false; 3214 3215} 3216 3217 3218/** 3219 * bnx2x_sp_post - place a single command on an SP ring 3220 * 3221 * @bp: driver handle 3222 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3223 * @cid: SW CID the command is related to 3224 * @data_hi: command private data address (high 32 bits) 3225 * @data_lo: command private data address (low 32 bits) 3226 * @cmd_type: command type (e.g. NONE, ETH) 3227 * 3228 * SP data is handled as if it's always an address pair, thus data fields are 3229 * not swapped to little endian in upper functions. Instead this function swaps 3230 * data as if it's two u32 fields. 3231 */ 3232int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3233 u32 data_hi, u32 data_lo, int cmd_type) 3234{ 3235 struct eth_spe *spe; 3236 u16 type; 3237 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3238 3239#ifdef BNX2X_STOP_ON_ERROR 3240 if (unlikely(bp->panic)) 3241 return -EIO; 3242#endif 3243 3244 spin_lock_bh(&bp->spq_lock); 3245 3246 if (common) { 3247 if (!atomic_read(&bp->eq_spq_left)) { 3248 BNX2X_ERR("BUG! EQ ring full!\n"); 3249 spin_unlock_bh(&bp->spq_lock); 3250 bnx2x_panic(); 3251 return -EBUSY; 3252 } 3253 } else if (!atomic_read(&bp->cq_spq_left)) { 3254 BNX2X_ERR("BUG! SPQ ring full!\n"); 3255 spin_unlock_bh(&bp->spq_lock); 3256 bnx2x_panic(); 3257 return -EBUSY; 3258 } 3259 3260 spe = bnx2x_sp_get_next(bp); 3261 3262 /* CID needs port number to be encoded int it */ 3263 spe->hdr.conn_and_cmd_data = 3264 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3265 HW_CID(bp, cid)); 3266 3267 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; 3268 3269 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3270 SPE_HDR_FUNCTION_ID); 3271 3272 spe->hdr.type = cpu_to_le16(type); 3273 3274 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3275 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3276 3277 /* 3278 * It's ok if the actual decrement is issued towards the memory 3279 * somewhere between the spin_lock and spin_unlock. Thus no 3280 * more explict memory barrier is needed. 3281 */ 3282 if (common) 3283 atomic_dec(&bp->eq_spq_left); 3284 else 3285 atomic_dec(&bp->cq_spq_left); 3286 3287 3288 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/, 3289 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) " 3290 "type(0x%x) left (CQ, EQ) (%x,%x)\n", 3291 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3292 (u32)(U64_LO(bp->spq_mapping) + 3293 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3294 HW_CID(bp, cid), data_hi, data_lo, type, 3295 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3296 3297 bnx2x_sp_prod_update(bp); 3298 spin_unlock_bh(&bp->spq_lock); 3299 return 0; 3300} 3301 3302/* acquire split MCP access lock register */ 3303static int bnx2x_acquire_alr(struct bnx2x *bp) 3304{ 3305 u32 j, val; 3306 int rc = 0; 3307 3308 might_sleep(); 3309 for (j = 0; j < 1000; j++) { 3310 val = (1UL << 31); 3311 REG_WR(bp, GRCBASE_MCP + 0x9c, val); 3312 val = REG_RD(bp, GRCBASE_MCP + 0x9c); 3313 if (val & (1L << 31)) 3314 break; 3315 3316 msleep(5); 3317 } 3318 if (!(val & (1L << 31))) { 3319 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3320 rc = -EBUSY; 3321 } 3322 3323 return rc; 3324} 3325 3326/* release split MCP access lock register */ 3327static void bnx2x_release_alr(struct bnx2x *bp) 3328{ 3329 REG_WR(bp, GRCBASE_MCP + 0x9c, 0); 3330} 3331 3332#define BNX2X_DEF_SB_ATT_IDX 0x0001 3333#define BNX2X_DEF_SB_IDX 0x0002 3334 3335static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3336{ 3337 struct host_sp_status_block *def_sb = bp->def_status_blk; 3338 u16 rc = 0; 3339 3340 barrier(); /* status block is written to by the chip */ 3341 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3342 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 3343 rc |= BNX2X_DEF_SB_ATT_IDX; 3344 } 3345 3346 if (bp->def_idx != def_sb->sp_sb.running_index) { 3347 bp->def_idx = def_sb->sp_sb.running_index; 3348 rc |= BNX2X_DEF_SB_IDX; 3349 } 3350 3351 /* Do not reorder: indecies reading should complete before handling */ 3352 barrier(); 3353 return rc; 3354} 3355 3356/* 3357 * slow path service functions 3358 */ 3359 3360static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 3361{ 3362 int port = BP_PORT(bp); 3363 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 3364 MISC_REG_AEU_MASK_ATTN_FUNC_0; 3365 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 3366 NIG_REG_MASK_INTERRUPT_PORT0; 3367 u32 aeu_mask; 3368 u32 nig_mask = 0; 3369 u32 reg_addr; 3370 3371 if (bp->attn_state & asserted) 3372 BNX2X_ERR("IGU ERROR\n"); 3373 3374 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3375 aeu_mask = REG_RD(bp, aeu_addr); 3376 3377 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 3378 aeu_mask, asserted); 3379 aeu_mask &= ~(asserted & 0x3ff); 3380 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 3381 3382 REG_WR(bp, aeu_addr, aeu_mask); 3383 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3384 3385 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 3386 bp->attn_state |= asserted; 3387 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 3388 3389 if (asserted & ATTN_HARD_WIRED_MASK) { 3390 if (asserted & ATTN_NIG_FOR_FUNC) { 3391 3392 bnx2x_acquire_phy_lock(bp); 3393 3394 /* save nig interrupt mask */ 3395 nig_mask = REG_RD(bp, nig_int_mask_addr); 3396 3397 /* If nig_mask is not set, no need to call the update 3398 * function. 3399 */ 3400 if (nig_mask) { 3401 REG_WR(bp, nig_int_mask_addr, 0); 3402 3403 bnx2x_link_attn(bp); 3404 } 3405 3406 /* handle unicore attn? */ 3407 } 3408 if (asserted & ATTN_SW_TIMER_4_FUNC) 3409 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 3410 3411 if (asserted & GPIO_2_FUNC) 3412 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 3413 3414 if (asserted & GPIO_3_FUNC) 3415 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 3416 3417 if (asserted & GPIO_4_FUNC) 3418 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 3419 3420 if (port == 0) { 3421 if (asserted & ATTN_GENERAL_ATTN_1) { 3422 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 3423 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 3424 } 3425 if (asserted & ATTN_GENERAL_ATTN_2) { 3426 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 3427 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 3428 } 3429 if (asserted & ATTN_GENERAL_ATTN_3) { 3430 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 3431 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 3432 } 3433 } else { 3434 if (asserted & ATTN_GENERAL_ATTN_4) { 3435 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 3436 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 3437 } 3438 if (asserted & ATTN_GENERAL_ATTN_5) { 3439 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 3440 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 3441 } 3442 if (asserted & ATTN_GENERAL_ATTN_6) { 3443 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 3444 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 3445 } 3446 } 3447 3448 } /* if hardwired */ 3449 3450 if (bp->common.int_block == INT_BLOCK_HC) 3451 reg_addr = (HC_REG_COMMAND_REG + port*32 + 3452 COMMAND_REG_ATTN_BITS_SET); 3453 else 3454 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 3455 3456 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 3457 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 3458 REG_WR(bp, reg_addr, asserted); 3459 3460 /* now set back the mask */ 3461 if (asserted & ATTN_NIG_FOR_FUNC) { 3462 REG_WR(bp, nig_int_mask_addr, nig_mask); 3463 bnx2x_release_phy_lock(bp); 3464 } 3465} 3466 3467static inline void bnx2x_fan_failure(struct bnx2x *bp) 3468{ 3469 int port = BP_PORT(bp); 3470 u32 ext_phy_config; 3471 /* mark the failure */ 3472 ext_phy_config = 3473 SHMEM_RD(bp, 3474 dev_info.port_hw_config[port].external_phy_config); 3475 3476 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 3477 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 3478 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 3479 ext_phy_config); 3480 3481 /* log the failure */ 3482 netdev_err(bp->dev, "Fan Failure on Network Controller has caused" 3483 " the driver to shutdown the card to prevent permanent" 3484 " damage. Please contact OEM Support for assistance\n"); 3485 3486 /* 3487 * Scheudle device reset (unload) 3488 * This is due to some boards consuming sufficient power when driver is 3489 * up to overheat if fan fails. 3490 */ 3491 smp_mb__before_clear_bit(); 3492 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); 3493 smp_mb__after_clear_bit(); 3494 schedule_delayed_work(&bp->sp_rtnl_task, 0); 3495 3496} 3497 3498static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 3499{ 3500 int port = BP_PORT(bp); 3501 int reg_offset; 3502 u32 val; 3503 3504 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 3505 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 3506 3507 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 3508 3509 val = REG_RD(bp, reg_offset); 3510 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 3511 REG_WR(bp, reg_offset, val); 3512 3513 BNX2X_ERR("SPIO5 hw attention\n"); 3514 3515 /* Fan failure attention */ 3516 bnx2x_hw_reset_phy(&bp->link_params); 3517 bnx2x_fan_failure(bp); 3518 } 3519 3520 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 3521 bnx2x_acquire_phy_lock(bp); 3522 bnx2x_handle_module_detect_int(&bp->link_params); 3523 bnx2x_release_phy_lock(bp); 3524 } 3525 3526 if (attn & HW_INTERRUT_ASSERT_SET_0) { 3527 3528 val = REG_RD(bp, reg_offset); 3529 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 3530 REG_WR(bp, reg_offset, val); 3531 3532 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 3533 (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); 3534 bnx2x_panic(); 3535 } 3536} 3537 3538static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 3539{ 3540 u32 val; 3541 3542 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 3543 3544 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 3545 BNX2X_ERR("DB hw attention 0x%x\n", val); 3546 /* DORQ discard attention */ 3547 if (val & 0x2) 3548 BNX2X_ERR("FATAL error from DORQ\n"); 3549 } 3550 3551 if (attn & HW_INTERRUT_ASSERT_SET_1) { 3552 3553 int port = BP_PORT(bp); 3554 int reg_offset; 3555 3556 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 3557 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 3558 3559 val = REG_RD(bp, reg_offset); 3560 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 3561 REG_WR(bp, reg_offset, val); 3562 3563 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 3564 (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); 3565 bnx2x_panic(); 3566 } 3567} 3568 3569static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 3570{ 3571 u32 val; 3572 3573 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 3574 3575 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 3576 BNX2X_ERR("CFC hw attention 0x%x\n", val); 3577 /* CFC error attention */ 3578 if (val & 0x2) 3579 BNX2X_ERR("FATAL error from CFC\n"); 3580 } 3581 3582 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 3583 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 3584 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 3585 /* RQ_USDMDP_FIFO_OVERFLOW */ 3586 if (val & 0x18000) 3587 BNX2X_ERR("FATAL error from PXP\n"); 3588 3589 if (!CHIP_IS_E1x(bp)) { 3590 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 3591 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 3592 } 3593 } 3594 3595 if (attn & HW_INTERRUT_ASSERT_SET_2) { 3596 3597 int port = BP_PORT(bp); 3598 int reg_offset; 3599 3600 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 3601 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 3602 3603 val = REG_RD(bp, reg_offset); 3604 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 3605 REG_WR(bp, reg_offset, val); 3606 3607 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 3608 (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); 3609 bnx2x_panic(); 3610 } 3611} 3612 3613static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 3614{ 3615 u32 val; 3616 3617 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 3618 3619 if (attn & BNX2X_PMF_LINK_ASSERT) { 3620 int func = BP_FUNC(bp); 3621 3622 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 3623 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 3624 func_mf_config[BP_ABS_FUNC(bp)].config); 3625 val = SHMEM_RD(bp, 3626 func_mb[BP_FW_MB_IDX(bp)].drv_status); 3627 if (val & DRV_STATUS_DCC_EVENT_MASK) 3628 bnx2x_dcc_event(bp, 3629 (val & DRV_STATUS_DCC_EVENT_MASK)); 3630 3631 if (val & DRV_STATUS_SET_MF_BW) 3632 bnx2x_set_mf_bw(bp); 3633 3634 if (val & DRV_STATUS_DRV_INFO_REQ) 3635 bnx2x_handle_drv_info_req(bp); 3636 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 3637 bnx2x_pmf_update(bp); 3638 3639 if (bp->port.pmf && 3640 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 3641 bp->dcbx_enabled > 0) 3642 /* start dcbx state machine */ 3643 bnx2x_dcbx_set_params(bp, 3644 BNX2X_DCBX_STATE_NEG_RECEIVED); 3645 if (bp->link_vars.periodic_flags & 3646 PERIODIC_FLAGS_LINK_EVENT) { 3647 /* sync with link */ 3648 bnx2x_acquire_phy_lock(bp); 3649 bp->link_vars.periodic_flags &= 3650 ~PERIODIC_FLAGS_LINK_EVENT; 3651 bnx2x_release_phy_lock(bp); 3652 if (IS_MF(bp)) 3653 bnx2x_link_sync_notify(bp); 3654 bnx2x_link_report(bp); 3655 } 3656 /* Always call it here: bnx2x_link_report() will 3657 * prevent the link indication duplication. 3658 */ 3659 bnx2x__link_status_update(bp); 3660 } else if (attn & BNX2X_MC_ASSERT_BITS) { 3661 3662 BNX2X_ERR("MC assert!\n"); 3663 bnx2x_mc_assert(bp); 3664 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 3665 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 3666 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 3667 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 3668 bnx2x_panic(); 3669 3670 } else if (attn & BNX2X_MCP_ASSERT) { 3671 3672 BNX2X_ERR("MCP assert!\n"); 3673 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 3674 bnx2x_fw_dump(bp); 3675 3676 } else 3677 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 3678 } 3679 3680 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 3681 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 3682 if (attn & BNX2X_GRC_TIMEOUT) { 3683 val = CHIP_IS_E1(bp) ? 0 : 3684 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 3685 BNX2X_ERR("GRC time-out 0x%08x\n", val); 3686 } 3687 if (attn & BNX2X_GRC_RSV) { 3688 val = CHIP_IS_E1(bp) ? 0 : 3689 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 3690 BNX2X_ERR("GRC reserved 0x%08x\n", val); 3691 } 3692 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 3693 } 3694} 3695 3696/* 3697 * Bits map: 3698 * 0-7 - Engine0 load counter. 3699 * 8-15 - Engine1 load counter. 3700 * 16 - Engine0 RESET_IN_PROGRESS bit. 3701 * 17 - Engine1 RESET_IN_PROGRESS bit. 3702 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 3703 * on the engine 3704 * 19 - Engine1 ONE_IS_LOADED. 3705 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 3706 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 3707 * just the one belonging to its engine). 3708 * 3709 */ 3710#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 3711 3712#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 3713#define BNX2X_PATH0_LOAD_CNT_SHIFT 0 3714#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 3715#define BNX2X_PATH1_LOAD_CNT_SHIFT 8 3716#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 3717#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 3718#define BNX2X_GLOBAL_RESET_BIT 0x00040000 3719 3720/* 3721 * Set the GLOBAL_RESET bit. 3722 * 3723 * Should be run under rtnl lock 3724 */ 3725void bnx2x_set_reset_global(struct bnx2x *bp) 3726{ 3727 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3728 3729 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 3730 barrier(); 3731 mmiowb(); 3732} 3733 3734/* 3735 * Clear the GLOBAL_RESET bit. 3736 * 3737 * Should be run under rtnl lock 3738 */ 3739static inline void bnx2x_clear_reset_global(struct bnx2x *bp) 3740{ 3741 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3742 3743 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 3744 barrier(); 3745 mmiowb(); 3746} 3747 3748/* 3749 * Checks the GLOBAL_RESET bit. 3750 * 3751 * should be run under rtnl lock 3752 */ 3753static inline bool bnx2x_reset_is_global(struct bnx2x *bp) 3754{ 3755 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3756 3757 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 3758 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 3759} 3760 3761/* 3762 * Clear RESET_IN_PROGRESS bit for the current engine. 3763 * 3764 * Should be run under rtnl lock 3765 */ 3766static inline void bnx2x_set_reset_done(struct bnx2x *bp) 3767{ 3768 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3769 u32 bit = BP_PATH(bp) ? 3770 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3771 3772 /* Clear the bit */ 3773 val &= ~bit; 3774 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3775 barrier(); 3776 mmiowb(); 3777} 3778 3779/* 3780 * Set RESET_IN_PROGRESS for the current engine. 3781 * 3782 * should be run under rtnl lock 3783 */ 3784void bnx2x_set_reset_in_progress(struct bnx2x *bp) 3785{ 3786 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3787 u32 bit = BP_PATH(bp) ? 3788 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3789 3790 /* Set the bit */ 3791 val |= bit; 3792 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3793 barrier(); 3794 mmiowb(); 3795} 3796 3797/* 3798 * Checks the RESET_IN_PROGRESS bit for the given engine. 3799 * should be run under rtnl lock 3800 */ 3801bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 3802{ 3803 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3804 u32 bit = engine ? 3805 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3806 3807 /* return false if bit is set */ 3808 return (val & bit) ? false : true; 3809} 3810 3811/* 3812 * Increment the load counter for the current engine. 3813 * 3814 * should be run under rtnl lock 3815 */ 3816void bnx2x_inc_load_cnt(struct bnx2x *bp) 3817{ 3818 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3819 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3820 BNX2X_PATH0_LOAD_CNT_MASK; 3821 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3822 BNX2X_PATH0_LOAD_CNT_SHIFT; 3823 3824 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3825 3826 /* get the current counter value */ 3827 val1 = (val & mask) >> shift; 3828 3829 /* increment... */ 3830 val1++; 3831 3832 /* clear the old value */ 3833 val &= ~mask; 3834 3835 /* set the new one */ 3836 val |= ((val1 << shift) & mask); 3837 3838 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3839 barrier(); 3840 mmiowb(); 3841} 3842 3843/** 3844 * bnx2x_dec_load_cnt - decrement the load counter 3845 * 3846 * @bp: driver handle 3847 * 3848 * Should be run under rtnl lock. 3849 * Decrements the load counter for the current engine. Returns 3850 * the new counter value. 3851 */ 3852u32 bnx2x_dec_load_cnt(struct bnx2x *bp) 3853{ 3854 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3855 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3856 BNX2X_PATH0_LOAD_CNT_MASK; 3857 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3858 BNX2X_PATH0_LOAD_CNT_SHIFT; 3859 3860 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3861 3862 /* get the current counter value */ 3863 val1 = (val & mask) >> shift; 3864 3865 /* decrement... */ 3866 val1--; 3867 3868 /* clear the old value */ 3869 val &= ~mask; 3870 3871 /* set the new one */ 3872 val |= ((val1 << shift) & mask); 3873 3874 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3875 barrier(); 3876 mmiowb(); 3877 3878 return val1; 3879} 3880 3881/* 3882 * Read the load counter for the current engine. 3883 * 3884 * should be run under rtnl lock 3885 */ 3886static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine) 3887{ 3888 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 3889 BNX2X_PATH0_LOAD_CNT_MASK); 3890 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3891 BNX2X_PATH0_LOAD_CNT_SHIFT); 3892 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3893 3894 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val); 3895 3896 val = (val & mask) >> shift; 3897 3898 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val); 3899 3900 return val; 3901} 3902 3903/* 3904 * Reset the load counter for the current engine. 3905 * 3906 * should be run under rtnl lock 3907 */ 3908static inline void bnx2x_clear_load_cnt(struct bnx2x *bp) 3909{ 3910 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3911 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3912 BNX2X_PATH0_LOAD_CNT_MASK); 3913 3914 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); 3915} 3916 3917static inline void _print_next_block(int idx, const char *blk) 3918{ 3919 pr_cont("%s%s", idx ? ", " : "", blk); 3920} 3921 3922static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, 3923 bool print) 3924{ 3925 int i = 0; 3926 u32 cur_bit = 0; 3927 for (i = 0; sig; i++) { 3928 cur_bit = ((u32)0x1 << i); 3929 if (sig & cur_bit) { 3930 switch (cur_bit) { 3931 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 3932 if (print) 3933 _print_next_block(par_num++, "BRB"); 3934 break; 3935 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 3936 if (print) 3937 _print_next_block(par_num++, "PARSER"); 3938 break; 3939 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 3940 if (print) 3941 _print_next_block(par_num++, "TSDM"); 3942 break; 3943 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 3944 if (print) 3945 _print_next_block(par_num++, 3946 "SEARCHER"); 3947 break; 3948 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 3949 if (print) 3950 _print_next_block(par_num++, "TCM"); 3951 break; 3952 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 3953 if (print) 3954 _print_next_block(par_num++, "TSEMI"); 3955 break; 3956 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 3957 if (print) 3958 _print_next_block(par_num++, "XPB"); 3959 break; 3960 } 3961 3962 /* Clear the bit */ 3963 sig &= ~cur_bit; 3964 } 3965 } 3966 3967 return par_num; 3968} 3969 3970static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, 3971 bool *global, bool print) 3972{ 3973 int i = 0; 3974 u32 cur_bit = 0; 3975 for (i = 0; sig; i++) { 3976 cur_bit = ((u32)0x1 << i); 3977 if (sig & cur_bit) { 3978 switch (cur_bit) { 3979 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 3980 if (print) 3981 _print_next_block(par_num++, "PBF"); 3982 break; 3983 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 3984 if (print) 3985 _print_next_block(par_num++, "QM"); 3986 break; 3987 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 3988 if (print) 3989 _print_next_block(par_num++, "TM"); 3990 break; 3991 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 3992 if (print) 3993 _print_next_block(par_num++, "XSDM"); 3994 break; 3995 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 3996 if (print) 3997 _print_next_block(par_num++, "XCM"); 3998 break; 3999 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 4000 if (print) 4001 _print_next_block(par_num++, "XSEMI"); 4002 break; 4003 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 4004 if (print) 4005 _print_next_block(par_num++, 4006 "DOORBELLQ"); 4007 break; 4008 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 4009 if (print) 4010 _print_next_block(par_num++, "NIG"); 4011 break; 4012 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 4013 if (print) 4014 _print_next_block(par_num++, 4015 "VAUX PCI CORE"); 4016 *global = true; 4017 break; 4018 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 4019 if (print) 4020 _print_next_block(par_num++, "DEBUG"); 4021 break; 4022 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 4023 if (print) 4024 _print_next_block(par_num++, "USDM"); 4025 break; 4026 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 4027 if (print) 4028 _print_next_block(par_num++, "UCM"); 4029 break; 4030 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 4031 if (print) 4032 _print_next_block(par_num++, "USEMI"); 4033 break; 4034 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 4035 if (print) 4036 _print_next_block(par_num++, "UPB"); 4037 break; 4038 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 4039 if (print) 4040 _print_next_block(par_num++, "CSDM"); 4041 break; 4042 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 4043 if (print) 4044 _print_next_block(par_num++, "CCM"); 4045 break; 4046 } 4047 4048 /* Clear the bit */ 4049 sig &= ~cur_bit; 4050 } 4051 } 4052 4053 return par_num; 4054} 4055 4056static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, 4057 bool print) 4058{ 4059 int i = 0; 4060 u32 cur_bit = 0; 4061 for (i = 0; sig; i++) { 4062 cur_bit = ((u32)0x1 << i); 4063 if (sig & cur_bit) { 4064 switch (cur_bit) { 4065 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 4066 if (print) 4067 _print_next_block(par_num++, "CSEMI"); 4068 break; 4069 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 4070 if (print) 4071 _print_next_block(par_num++, "PXP"); 4072 break; 4073 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 4074 if (print) 4075 _print_next_block(par_num++, 4076 "PXPPCICLOCKCLIENT"); 4077 break; 4078 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 4079 if (print) 4080 _print_next_block(par_num++, "CFC"); 4081 break; 4082 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 4083 if (print) 4084 _print_next_block(par_num++, "CDU"); 4085 break; 4086 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 4087 if (print) 4088 _print_next_block(par_num++, "DMAE"); 4089 break; 4090 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 4091 if (print) 4092 _print_next_block(par_num++, "IGU"); 4093 break; 4094 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 4095 if (print) 4096 _print_next_block(par_num++, "MISC"); 4097 break; 4098 } 4099 4100 /* Clear the bit */ 4101 sig &= ~cur_bit; 4102 } 4103 } 4104 4105 return par_num; 4106} 4107 4108static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, 4109 bool *global, bool print) 4110{ 4111 int i = 0; 4112 u32 cur_bit = 0; 4113 for (i = 0; sig; i++) { 4114 cur_bit = ((u32)0x1 << i); 4115 if (sig & cur_bit) { 4116 switch (cur_bit) { 4117 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 4118 if (print) 4119 _print_next_block(par_num++, "MCP ROM"); 4120 *global = true; 4121 break; 4122 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 4123 if (print) 4124 _print_next_block(par_num++, 4125 "MCP UMP RX"); 4126 *global = true; 4127 break; 4128 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 4129 if (print) 4130 _print_next_block(par_num++, 4131 "MCP UMP TX"); 4132 *global = true; 4133 break; 4134 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 4135 if (print) 4136 _print_next_block(par_num++, 4137 "MCP SCPAD"); 4138 *global = true; 4139 break; 4140 } 4141 4142 /* Clear the bit */ 4143 sig &= ~cur_bit; 4144 } 4145 } 4146 4147 return par_num; 4148} 4149 4150static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, 4151 bool print) 4152{ 4153 int i = 0; 4154 u32 cur_bit = 0; 4155 for (i = 0; sig; i++) { 4156 cur_bit = ((u32)0x1 << i); 4157 if (sig & cur_bit) { 4158 switch (cur_bit) { 4159 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 4160 if (print) 4161 _print_next_block(par_num++, "PGLUE_B"); 4162 break; 4163 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 4164 if (print) 4165 _print_next_block(par_num++, "ATC"); 4166 break; 4167 } 4168 4169 /* Clear the bit */ 4170 sig &= ~cur_bit; 4171 } 4172 } 4173 4174 return par_num; 4175} 4176 4177static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4178 u32 *sig) 4179{ 4180 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4181 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4182 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4183 (sig[3] & HW_PRTY_ASSERT_SET_3) || 4184 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4185 int par_num = 0; 4186 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: " 4187 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x " 4188 "[4]:0x%08x\n", 4189 sig[0] & HW_PRTY_ASSERT_SET_0, 4190 sig[1] & HW_PRTY_ASSERT_SET_1, 4191 sig[2] & HW_PRTY_ASSERT_SET_2, 4192 sig[3] & HW_PRTY_ASSERT_SET_3, 4193 sig[4] & HW_PRTY_ASSERT_SET_4); 4194 if (print) 4195 netdev_err(bp->dev, 4196 "Parity errors detected in blocks: "); 4197 par_num = bnx2x_check_blocks_with_parity0( 4198 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); 4199 par_num = bnx2x_check_blocks_with_parity1( 4200 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); 4201 par_num = bnx2x_check_blocks_with_parity2( 4202 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); 4203 par_num = bnx2x_check_blocks_with_parity3( 4204 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); 4205 par_num = bnx2x_check_blocks_with_parity4( 4206 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); 4207 4208 if (print) 4209 pr_cont("\n"); 4210 4211 return true; 4212 } else 4213 return false; 4214} 4215 4216/** 4217 * bnx2x_chk_parity_attn - checks for parity attentions. 4218 * 4219 * @bp: driver handle 4220 * @global: true if there was a global attention 4221 * @print: show parity attention in syslog 4222 */ 4223bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 4224{ 4225 struct attn_route attn = { {0} }; 4226 int port = BP_PORT(bp); 4227 4228 attn.sig[0] = REG_RD(bp, 4229 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 4230 port*4); 4231 attn.sig[1] = REG_RD(bp, 4232 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 4233 port*4); 4234 attn.sig[2] = REG_RD(bp, 4235 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 4236 port*4); 4237 attn.sig[3] = REG_RD(bp, 4238 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 4239 port*4); 4240 4241 if (!CHIP_IS_E1x(bp)) 4242 attn.sig[4] = REG_RD(bp, 4243 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 4244 port*4); 4245 4246 return bnx2x_parity_attn(bp, global, print, attn.sig); 4247} 4248 4249 4250static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 4251{ 4252 u32 val; 4253 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 4254 4255 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 4256 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 4257 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 4258 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4259 "ADDRESS_ERROR\n"); 4260 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 4261 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4262 "INCORRECT_RCV_BEHAVIOR\n"); 4263 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 4264 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4265 "WAS_ERROR_ATTN\n"); 4266 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 4267 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4268 "VF_LENGTH_VIOLATION_ATTN\n"); 4269 if (val & 4270 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 4271 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4272 "VF_GRC_SPACE_VIOLATION_ATTN\n"); 4273 if (val & 4274 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 4275 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4276 "VF_MSIX_BAR_VIOLATION_ATTN\n"); 4277 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 4278 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4279 "TCPL_ERROR_ATTN\n"); 4280 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 4281 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4282 "TCPL_IN_TWO_RCBS_ATTN\n"); 4283 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 4284 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4285 "CSSNOOP_FIFO_OVERFLOW\n"); 4286 } 4287 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 4288 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 4289 BNX2X_ERR("ATC hw attention 0x%x\n", val); 4290 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 4291 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 4292 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 4293 BNX2X_ERR("ATC_ATC_INT_STS_REG" 4294 "_ATC_TCPL_TO_NOT_PEND\n"); 4295 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 4296 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4297 "ATC_GPA_MULTIPLE_HITS\n"); 4298 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 4299 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4300 "ATC_RCPL_TO_EMPTY_CNT\n"); 4301 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 4302 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 4303 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 4304 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4305 "ATC_IREQ_LESS_THAN_STU\n"); 4306 } 4307 4308 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4309 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 4310 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 4311 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4312 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 4313 } 4314 4315} 4316 4317static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 4318{ 4319 struct attn_route attn, *group_mask; 4320 int port = BP_PORT(bp); 4321 int index; 4322 u32 reg_addr; 4323 u32 val; 4324 u32 aeu_mask; 4325 bool global = false; 4326 4327 /* need to take HW lock because MCP or other port might also 4328 try to handle this event */ 4329 bnx2x_acquire_alr(bp); 4330 4331 if (bnx2x_chk_parity_attn(bp, &global, true)) { 4332#ifndef BNX2X_STOP_ON_ERROR 4333 bp->recovery_state = BNX2X_RECOVERY_INIT; 4334 schedule_delayed_work(&bp->sp_rtnl_task, 0); 4335 /* Disable HW interrupts */ 4336 bnx2x_int_disable(bp); 4337 /* In case of parity errors don't handle attentions so that 4338 * other function would "see" parity errors. 4339 */ 4340#else 4341 bnx2x_panic(); 4342#endif 4343 bnx2x_release_alr(bp); 4344 return; 4345 } 4346 4347 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 4348 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 4349 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 4350 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 4351 if (!CHIP_IS_E1x(bp)) 4352 attn.sig[4] = 4353 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 4354 else 4355 attn.sig[4] = 0; 4356 4357 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 4358 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 4359 4360 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4361 if (deasserted & (1 << index)) { 4362 group_mask = &bp->attn_group[index]; 4363 4364 DP(NETIF_MSG_HW, "group[%d]: %08x %08x " 4365 "%08x %08x %08x\n", 4366 index, 4367 group_mask->sig[0], group_mask->sig[1], 4368 group_mask->sig[2], group_mask->sig[3], 4369 group_mask->sig[4]); 4370 4371 bnx2x_attn_int_deasserted4(bp, 4372 attn.sig[4] & group_mask->sig[4]); 4373 bnx2x_attn_int_deasserted3(bp, 4374 attn.sig[3] & group_mask->sig[3]); 4375 bnx2x_attn_int_deasserted1(bp, 4376 attn.sig[1] & group_mask->sig[1]); 4377 bnx2x_attn_int_deasserted2(bp, 4378 attn.sig[2] & group_mask->sig[2]); 4379 bnx2x_attn_int_deasserted0(bp, 4380 attn.sig[0] & group_mask->sig[0]); 4381 } 4382 } 4383 4384 bnx2x_release_alr(bp); 4385 4386 if (bp->common.int_block == INT_BLOCK_HC) 4387 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4388 COMMAND_REG_ATTN_BITS_CLR); 4389 else 4390 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 4391 4392 val = ~deasserted; 4393 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 4394 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4395 REG_WR(bp, reg_addr, val); 4396 4397 if (~bp->attn_state & deasserted) 4398 BNX2X_ERR("IGU ERROR\n"); 4399 4400 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4401 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4402 4403 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4404 aeu_mask = REG_RD(bp, reg_addr); 4405 4406 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 4407 aeu_mask, deasserted); 4408 aeu_mask |= (deasserted & 0x3ff); 4409 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4410 4411 REG_WR(bp, reg_addr, aeu_mask); 4412 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4413 4414 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4415 bp->attn_state &= ~deasserted; 4416 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4417} 4418 4419static void bnx2x_attn_int(struct bnx2x *bp) 4420{ 4421 /* read local copy of bits */ 4422 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 4423 attn_bits); 4424 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 4425 attn_bits_ack); 4426 u32 attn_state = bp->attn_state; 4427 4428 /* look for changed bits */ 4429 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 4430 u32 deasserted = ~attn_bits & attn_ack & attn_state; 4431 4432 DP(NETIF_MSG_HW, 4433 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 4434 attn_bits, attn_ack, asserted, deasserted); 4435 4436 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 4437 BNX2X_ERR("BAD attention state\n"); 4438 4439 /* handle bits that were raised */ 4440 if (asserted) 4441 bnx2x_attn_int_asserted(bp, asserted); 4442 4443 if (deasserted) 4444 bnx2x_attn_int_deasserted(bp, deasserted); 4445} 4446 4447void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 4448 u16 index, u8 op, u8 update) 4449{ 4450 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 4451 4452 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 4453 igu_addr); 4454} 4455 4456static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 4457{ 4458 /* No memory barriers */ 4459 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 4460 mmiowb(); /* keep prod updates ordered */ 4461} 4462 4463#ifdef BCM_CNIC 4464static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 4465 union event_ring_elem *elem) 4466{ 4467 u8 err = elem->message.error; 4468 4469 if (!bp->cnic_eth_dev.starting_cid || 4470 (cid < bp->cnic_eth_dev.starting_cid && 4471 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 4472 return 1; 4473 4474 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 4475 4476 if (unlikely(err)) { 4477 4478 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 4479 cid); 4480 bnx2x_panic_dump(bp); 4481 } 4482 bnx2x_cnic_cfc_comp(bp, cid, err); 4483 return 0; 4484} 4485#endif 4486 4487static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 4488{ 4489 struct bnx2x_mcast_ramrod_params rparam; 4490 int rc; 4491 4492 memset(&rparam, 0, sizeof(rparam)); 4493 4494 rparam.mcast_obj = &bp->mcast_obj; 4495 4496 netif_addr_lock_bh(bp->dev); 4497 4498 /* Clear pending state for the last command */ 4499 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 4500 4501 /* If there are pending mcast commands - send them */ 4502 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 4503 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 4504 if (rc < 0) 4505 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 4506 rc); 4507 } 4508 4509 netif_addr_unlock_bh(bp->dev); 4510} 4511 4512static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp, 4513 union event_ring_elem *elem) 4514{ 4515 unsigned long ramrod_flags = 0; 4516 int rc = 0; 4517 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; 4518 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 4519 4520 /* Always push next commands out, don't wait here */ 4521 __set_bit(RAMROD_CONT, &ramrod_flags); 4522 4523 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 4524 case BNX2X_FILTER_MAC_PENDING: 4525#ifdef BCM_CNIC 4526 if (cid == BNX2X_ISCSI_ETH_CID) 4527 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 4528 else 4529#endif 4530 vlan_mac_obj = &bp->fp[cid].mac_obj; 4531 4532 break; 4533 case BNX2X_FILTER_MCAST_PENDING: 4534 /* This is only relevant for 57710 where multicast MACs are 4535 * configured as unicast MACs using the same ramrod. 4536 */ 4537 bnx2x_handle_mcast_eqe(bp); 4538 return; 4539 default: 4540 BNX2X_ERR("Unsupported classification command: %d\n", 4541 elem->message.data.eth_event.echo); 4542 return; 4543 } 4544 4545 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 4546 4547 if (rc < 0) 4548 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 4549 else if (rc > 0) 4550 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 4551 4552} 4553 4554#ifdef BCM_CNIC 4555static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 4556#endif 4557 4558static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 4559{ 4560 netif_addr_lock_bh(bp->dev); 4561 4562 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 4563 4564 /* Send rx_mode command again if was requested */ 4565 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 4566 bnx2x_set_storm_rx_mode(bp); 4567#ifdef BCM_CNIC 4568 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 4569 &bp->sp_state)) 4570 bnx2x_set_iscsi_eth_rx_mode(bp, true); 4571 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 4572 &bp->sp_state)) 4573 bnx2x_set_iscsi_eth_rx_mode(bp, false); 4574#endif 4575 4576 netif_addr_unlock_bh(bp->dev); 4577} 4578 4579static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 4580 struct bnx2x *bp, u32 cid) 4581{ 4582 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 4583#ifdef BCM_CNIC 4584 if (cid == BNX2X_FCOE_ETH_CID) 4585 return &bnx2x_fcoe(bp, q_obj); 4586 else 4587#endif 4588 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj); 4589} 4590 4591static void bnx2x_eq_int(struct bnx2x *bp) 4592{ 4593 u16 hw_cons, sw_cons, sw_prod; 4594 union event_ring_elem *elem; 4595 u32 cid; 4596 u8 opcode; 4597 int spqe_cnt = 0; 4598 struct bnx2x_queue_sp_obj *q_obj; 4599 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 4600 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 4601 4602 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 4603 4604 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 4605 * when we get the the next-page we nned to adjust so the loop 4606 * condition below will be met. The next element is the size of a 4607 * regular element and hence incrementing by 1 4608 */ 4609 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 4610 hw_cons++; 4611 4612 /* This function may never run in parallel with itself for a 4613 * specific bp, thus there is no need in "paired" read memory 4614 * barrier here. 4615 */ 4616 sw_cons = bp->eq_cons; 4617 sw_prod = bp->eq_prod; 4618 4619 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 4620 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 4621 4622 for (; sw_cons != hw_cons; 4623 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 4624 4625 4626 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 4627 4628 cid = SW_CID(elem->message.data.cfc_del_event.cid); 4629 opcode = elem->message.opcode; 4630 4631 4632 /* handle eq element */ 4633 switch (opcode) { 4634 case EVENT_RING_OPCODE_STAT_QUERY: 4635 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n", 4636 bp->stats_comp++); 4637 /* nothing to do with stats comp */ 4638 goto next_spqe; 4639 4640 case EVENT_RING_OPCODE_CFC_DEL: 4641 /* handle according to cid range */ 4642 /* 4643 * we may want to verify here that the bp state is 4644 * HALTING 4645 */ 4646 DP(BNX2X_MSG_SP, 4647 "got delete ramrod for MULTI[%d]\n", cid); 4648#ifdef BCM_CNIC 4649 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 4650 goto next_spqe; 4651#endif 4652 q_obj = bnx2x_cid_to_q_obj(bp, cid); 4653 4654 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 4655 break; 4656 4657 4658 4659 goto next_spqe; 4660 4661 case EVENT_RING_OPCODE_STOP_TRAFFIC: 4662 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n"); 4663 if (f_obj->complete_cmd(bp, f_obj, 4664 BNX2X_F_CMD_TX_STOP)) 4665 break; 4666 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 4667 goto next_spqe; 4668 4669 case EVENT_RING_OPCODE_START_TRAFFIC: 4670 DP(BNX2X_MSG_SP, "got START TRAFFIC\n"); 4671 if (f_obj->complete_cmd(bp, f_obj, 4672 BNX2X_F_CMD_TX_START)) 4673 break; 4674 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 4675 goto next_spqe; 4676 case EVENT_RING_OPCODE_FUNCTION_START: 4677 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n"); 4678 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 4679 break; 4680 4681 goto next_spqe; 4682 4683 case EVENT_RING_OPCODE_FUNCTION_STOP: 4684 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n"); 4685 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 4686 break; 4687 4688 goto next_spqe; 4689 } 4690 4691 switch (opcode | bp->state) { 4692 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4693 BNX2X_STATE_OPEN): 4694 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4695 BNX2X_STATE_OPENING_WAIT4_PORT): 4696 cid = elem->message.data.eth_event.echo & 4697 BNX2X_SWCID_MASK; 4698 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 4699 cid); 4700 rss_raw->clear_pending(rss_raw); 4701 break; 4702 4703 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 4704 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 4705 case (EVENT_RING_OPCODE_SET_MAC | 4706 BNX2X_STATE_CLOSING_WAIT4_HALT): 4707 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4708 BNX2X_STATE_OPEN): 4709 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4710 BNX2X_STATE_DIAG): 4711 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4712 BNX2X_STATE_CLOSING_WAIT4_HALT): 4713 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); 4714 bnx2x_handle_classification_eqe(bp, elem); 4715 break; 4716 4717 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4718 BNX2X_STATE_OPEN): 4719 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4720 BNX2X_STATE_DIAG): 4721 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4722 BNX2X_STATE_CLOSING_WAIT4_HALT): 4723 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 4724 bnx2x_handle_mcast_eqe(bp); 4725 break; 4726 4727 case (EVENT_RING_OPCODE_FILTERS_RULES | 4728 BNX2X_STATE_OPEN): 4729 case (EVENT_RING_OPCODE_FILTERS_RULES | 4730 BNX2X_STATE_DIAG): 4731 case (EVENT_RING_OPCODE_FILTERS_RULES | 4732 BNX2X_STATE_CLOSING_WAIT4_HALT): 4733 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 4734 bnx2x_handle_rx_mode_eqe(bp); 4735 break; 4736 default: 4737 /* unknown event log error and continue */ 4738 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 4739 elem->message.opcode, bp->state); 4740 } 4741next_spqe: 4742 spqe_cnt++; 4743 } /* for */ 4744 4745 smp_mb__before_atomic_inc(); 4746 atomic_add(spqe_cnt, &bp->eq_spq_left); 4747 4748 bp->eq_cons = sw_cons; 4749 bp->eq_prod = sw_prod; 4750 /* Make sure that above mem writes were issued towards the memory */ 4751 smp_wmb(); 4752 4753 /* update producer */ 4754 bnx2x_update_eq_prod(bp, bp->eq_prod); 4755} 4756 4757static void bnx2x_sp_task(struct work_struct *work) 4758{ 4759 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 4760 u16 status; 4761 4762 status = bnx2x_update_dsb_idx(bp); 4763/* if (status == 0) */ 4764/* BNX2X_ERR("spurious slowpath interrupt!\n"); */ 4765 4766 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status); 4767 4768 /* HW attentions */ 4769 if (status & BNX2X_DEF_SB_ATT_IDX) { 4770 bnx2x_attn_int(bp); 4771 status &= ~BNX2X_DEF_SB_ATT_IDX; 4772 } 4773 4774 /* SP events: STAT_QUERY and others */ 4775 if (status & BNX2X_DEF_SB_IDX) { 4776#ifdef BCM_CNIC 4777 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 4778 4779 if ((!NO_FCOE(bp)) && 4780 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 4781 /* 4782 * Prevent local bottom-halves from running as 4783 * we are going to change the local NAPI list. 4784 */ 4785 local_bh_disable(); 4786 napi_schedule(&bnx2x_fcoe(bp, napi)); 4787 local_bh_enable(); 4788 } 4789#endif 4790 /* Handle EQ completions */ 4791 bnx2x_eq_int(bp); 4792 4793 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 4794 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 4795 4796 status &= ~BNX2X_DEF_SB_IDX; 4797 } 4798 4799 if (unlikely(status)) 4800 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 4801 status); 4802 4803 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 4804 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 4805} 4806 4807irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 4808{ 4809 struct net_device *dev = dev_instance; 4810 struct bnx2x *bp = netdev_priv(dev); 4811 4812 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 4813 IGU_INT_DISABLE, 0); 4814 4815#ifdef BNX2X_STOP_ON_ERROR 4816 if (unlikely(bp->panic)) 4817 return IRQ_HANDLED; 4818#endif 4819 4820#ifdef BCM_CNIC 4821 { 4822 struct cnic_ops *c_ops; 4823 4824 rcu_read_lock(); 4825 c_ops = rcu_dereference(bp->cnic_ops); 4826 if (c_ops) 4827 c_ops->cnic_handler(bp->cnic_data, NULL); 4828 rcu_read_unlock(); 4829 } 4830#endif 4831 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 4832 4833 return IRQ_HANDLED; 4834} 4835 4836/* end of slow path */ 4837 4838 4839void bnx2x_drv_pulse(struct bnx2x *bp) 4840{ 4841 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 4842 bp->fw_drv_pulse_wr_seq); 4843} 4844 4845 4846static void bnx2x_timer(unsigned long data) 4847{ 4848 u8 cos; 4849 struct bnx2x *bp = (struct bnx2x *) data; 4850 4851 if (!netif_running(bp->dev)) 4852 return; 4853 4854 if (poll) { 4855 struct bnx2x_fastpath *fp = &bp->fp[0]; 4856 4857 for_each_cos_in_tx_queue(fp, cos) 4858 bnx2x_tx_int(bp, &fp->txdata[cos]); 4859 bnx2x_rx_int(fp, 1000); 4860 } 4861 4862 if (!BP_NOMCP(bp)) { 4863 int mb_idx = BP_FW_MB_IDX(bp); 4864 u32 drv_pulse; 4865 u32 mcp_pulse; 4866 4867 ++bp->fw_drv_pulse_wr_seq; 4868 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 4869 /* TBD - add SYSTEM_TIME */ 4870 drv_pulse = bp->fw_drv_pulse_wr_seq; 4871 bnx2x_drv_pulse(bp); 4872 4873 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 4874 MCP_PULSE_SEQ_MASK); 4875 /* The delta between driver pulse and mcp response 4876 * should be 1 (before mcp response) or 0 (after mcp response) 4877 */ 4878 if ((drv_pulse != mcp_pulse) && 4879 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 4880 /* someone lost a heartbeat... */ 4881 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 4882 drv_pulse, mcp_pulse); 4883 } 4884 } 4885 4886 if (bp->state == BNX2X_STATE_OPEN) 4887 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 4888 4889 mod_timer(&bp->timer, jiffies + bp->current_interval); 4890} 4891 4892/* end of Statistics */ 4893 4894/* nic init */ 4895 4896/* 4897 * nic init service functions 4898 */ 4899 4900static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 4901{ 4902 u32 i; 4903 if (!(len%4) && !(addr%4)) 4904 for (i = 0; i < len; i += 4) 4905 REG_WR(bp, addr + i, fill); 4906 else 4907 for (i = 0; i < len; i++) 4908 REG_WR8(bp, addr + i, fill); 4909 4910} 4911 4912/* helper: writes FP SP data to FW - data_size in dwords */ 4913static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 4914 int fw_sb_id, 4915 u32 *sb_data_p, 4916 u32 data_size) 4917{ 4918 int index; 4919 for (index = 0; index < data_size; index++) 4920 REG_WR(bp, BAR_CSTRORM_INTMEM + 4921 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 4922 sizeof(u32)*index, 4923 *(sb_data_p + index)); 4924} 4925 4926static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 4927{ 4928 u32 *sb_data_p; 4929 u32 data_size = 0; 4930 struct hc_status_block_data_e2 sb_data_e2; 4931 struct hc_status_block_data_e1x sb_data_e1x; 4932 4933 /* disable the function first */ 4934 if (!CHIP_IS_E1x(bp)) { 4935 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 4936 sb_data_e2.common.state = SB_DISABLED; 4937 sb_data_e2.common.p_func.vf_valid = false; 4938 sb_data_p = (u32 *)&sb_data_e2; 4939 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 4940 } else { 4941 memset(&sb_data_e1x, 0, 4942 sizeof(struct hc_status_block_data_e1x)); 4943 sb_data_e1x.common.state = SB_DISABLED; 4944 sb_data_e1x.common.p_func.vf_valid = false; 4945 sb_data_p = (u32 *)&sb_data_e1x; 4946 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 4947 } 4948 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 4949 4950 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4951 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 4952 CSTORM_STATUS_BLOCK_SIZE); 4953 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4954 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 4955 CSTORM_SYNC_BLOCK_SIZE); 4956} 4957 4958/* helper: writes SP SB data to FW */ 4959static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 4960 struct hc_sp_status_block_data *sp_sb_data) 4961{ 4962 int func = BP_FUNC(bp); 4963 int i; 4964 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 4965 REG_WR(bp, BAR_CSTRORM_INTMEM + 4966 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 4967 i*sizeof(u32), 4968 *((u32 *)sp_sb_data + i)); 4969} 4970 4971static inline void bnx2x_zero_sp_sb(struct bnx2x *bp) 4972{ 4973 int func = BP_FUNC(bp); 4974 struct hc_sp_status_block_data sp_sb_data; 4975 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 4976 4977 sp_sb_data.state = SB_DISABLED; 4978 sp_sb_data.p_func.vf_valid = false; 4979 4980 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 4981 4982 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4983 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 4984 CSTORM_SP_STATUS_BLOCK_SIZE); 4985 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4986 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 4987 CSTORM_SP_SYNC_BLOCK_SIZE); 4988 4989} 4990 4991 4992static inline 4993void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 4994 int igu_sb_id, int igu_seg_id) 4995{ 4996 hc_sm->igu_sb_id = igu_sb_id; 4997 hc_sm->igu_seg_id = igu_seg_id; 4998 hc_sm->timer_value = 0xFF; 4999 hc_sm->time_to_expire = 0xFFFFFFFF; 5000} 5001 5002 5003/* allocates state machine ids. */ 5004static inline 5005void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) 5006{ 5007 /* zero out state machine indices */ 5008 /* rx indices */ 5009 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5010 5011 /* tx indices */ 5012 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5013 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 5014 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 5015 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 5016 5017 /* map indices */ 5018 /* rx indices */ 5019 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 5020 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5021 5022 /* tx indices */ 5023 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 5024 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5025 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 5026 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5027 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 5028 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5029 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 5030 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5031} 5032 5033static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 5034 u8 vf_valid, int fw_sb_id, int igu_sb_id) 5035{ 5036 int igu_seg_id; 5037 5038 struct hc_status_block_data_e2 sb_data_e2; 5039 struct hc_status_block_data_e1x sb_data_e1x; 5040 struct hc_status_block_sm *hc_sm_p; 5041 int data_size; 5042 u32 *sb_data_p; 5043 5044 if (CHIP_INT_MODE_IS_BC(bp)) 5045 igu_seg_id = HC_SEG_ACCESS_NORM; 5046 else 5047 igu_seg_id = IGU_SEG_ACCESS_NORM; 5048 5049 bnx2x_zero_fp_sb(bp, fw_sb_id); 5050 5051 if (!CHIP_IS_E1x(bp)) { 5052 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5053 sb_data_e2.common.state = SB_ENABLED; 5054 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 5055 sb_data_e2.common.p_func.vf_id = vfid; 5056 sb_data_e2.common.p_func.vf_valid = vf_valid; 5057 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 5058 sb_data_e2.common.same_igu_sb_1b = true; 5059 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 5060 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 5061 hc_sm_p = sb_data_e2.common.state_machine; 5062 sb_data_p = (u32 *)&sb_data_e2; 5063 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5064 bnx2x_map_sb_state_machines(sb_data_e2.index_data); 5065 } else { 5066 memset(&sb_data_e1x, 0, 5067 sizeof(struct hc_status_block_data_e1x)); 5068 sb_data_e1x.common.state = SB_ENABLED; 5069 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 5070 sb_data_e1x.common.p_func.vf_id = 0xff; 5071 sb_data_e1x.common.p_func.vf_valid = false; 5072 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 5073 sb_data_e1x.common.same_igu_sb_1b = true; 5074 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 5075 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 5076 hc_sm_p = sb_data_e1x.common.state_machine; 5077 sb_data_p = (u32 *)&sb_data_e1x; 5078 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5079 bnx2x_map_sb_state_machines(sb_data_e1x.index_data); 5080 } 5081 5082 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 5083 igu_sb_id, igu_seg_id); 5084 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 5085 igu_sb_id, igu_seg_id); 5086 5087 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id); 5088 5089 /* write indecies to HW */ 5090 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5091} 5092 5093static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 5094 u16 tx_usec, u16 rx_usec) 5095{ 5096 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 5097 false, rx_usec); 5098 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5099 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 5100 tx_usec); 5101 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5102 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 5103 tx_usec); 5104 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5105 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 5106 tx_usec); 5107} 5108 5109static void bnx2x_init_def_sb(struct bnx2x *bp) 5110{ 5111 struct host_sp_status_block *def_sb = bp->def_status_blk; 5112 dma_addr_t mapping = bp->def_status_blk_mapping; 5113 int igu_sp_sb_index; 5114 int igu_seg_id; 5115 int port = BP_PORT(bp); 5116 int func = BP_FUNC(bp); 5117 int reg_offset, reg_offset_en5; 5118 u64 section; 5119 int index; 5120 struct hc_sp_status_block_data sp_sb_data; 5121 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5122 5123 if (CHIP_INT_MODE_IS_BC(bp)) { 5124 igu_sp_sb_index = DEF_SB_IGU_ID; 5125 igu_seg_id = HC_SEG_ACCESS_DEF; 5126 } else { 5127 igu_sp_sb_index = bp->igu_dsb_id; 5128 igu_seg_id = IGU_SEG_ACCESS_DEF; 5129 } 5130 5131 /* ATTN */ 5132 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5133 atten_status_block); 5134 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 5135 5136 bp->attn_state = 0; 5137 5138 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 5139 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 5140 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 5141 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); 5142 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 5143 int sindex; 5144 /* take care of sig[0]..sig[4] */ 5145 for (sindex = 0; sindex < 4; sindex++) 5146 bp->attn_group[index].sig[sindex] = 5147 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 5148 5149 if (!CHIP_IS_E1x(bp)) 5150 /* 5151 * enable5 is separate from the rest of the registers, 5152 * and therefore the address skip is 4 5153 * and not 16 between the different groups 5154 */ 5155 bp->attn_group[index].sig[4] = REG_RD(bp, 5156 reg_offset_en5 + 0x4*index); 5157 else 5158 bp->attn_group[index].sig[4] = 0; 5159 } 5160 5161 if (bp->common.int_block == INT_BLOCK_HC) { 5162 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 5163 HC_REG_ATTN_MSG0_ADDR_L); 5164 5165 REG_WR(bp, reg_offset, U64_LO(section)); 5166 REG_WR(bp, reg_offset + 4, U64_HI(section)); 5167 } else if (!CHIP_IS_E1x(bp)) { 5168 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 5169 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 5170 } 5171 5172 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5173 sp_sb); 5174 5175 bnx2x_zero_sp_sb(bp); 5176 5177 sp_sb_data.state = SB_ENABLED; 5178 sp_sb_data.host_sb_addr.lo = U64_LO(section); 5179 sp_sb_data.host_sb_addr.hi = U64_HI(section); 5180 sp_sb_data.igu_sb_id = igu_sp_sb_index; 5181 sp_sb_data.igu_seg_id = igu_seg_id; 5182 sp_sb_data.p_func.pf_id = func; 5183 sp_sb_data.p_func.vnic_id = BP_VN(bp); 5184 sp_sb_data.p_func.vf_id = 0xff; 5185 5186 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5187 5188 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 5189} 5190 5191void bnx2x_update_coalesce(struct bnx2x *bp) 5192{ 5193 int i; 5194 5195 for_each_eth_queue(bp, i) 5196 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 5197 bp->tx_ticks, bp->rx_ticks); 5198} 5199 5200static void bnx2x_init_sp_ring(struct bnx2x *bp) 5201{ 5202 spin_lock_init(&bp->spq_lock); 5203 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 5204 5205 bp->spq_prod_idx = 0; 5206 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 5207 bp->spq_prod_bd = bp->spq; 5208 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 5209} 5210 5211static void bnx2x_init_eq_ring(struct bnx2x *bp) 5212{ 5213 int i; 5214 for (i = 1; i <= NUM_EQ_PAGES; i++) { 5215 union event_ring_elem *elem = 5216 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 5217 5218 elem->next_page.addr.hi = 5219 cpu_to_le32(U64_HI(bp->eq_mapping + 5220 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 5221 elem->next_page.addr.lo = 5222 cpu_to_le32(U64_LO(bp->eq_mapping + 5223 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 5224 } 5225 bp->eq_cons = 0; 5226 bp->eq_prod = NUM_EQ_DESC; 5227 bp->eq_cons_sb = BNX2X_EQ_INDEX; 5228 /* we want a warning message before it gets rought... */ 5229 atomic_set(&bp->eq_spq_left, 5230 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 5231} 5232 5233 5234/* called with netif_addr_lock_bh() */ 5235void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 5236 unsigned long rx_mode_flags, 5237 unsigned long rx_accept_flags, 5238 unsigned long tx_accept_flags, 5239 unsigned long ramrod_flags) 5240{ 5241 struct bnx2x_rx_mode_ramrod_params ramrod_param; 5242 int rc; 5243 5244 memset(&ramrod_param, 0, sizeof(ramrod_param)); 5245 5246 /* Prepare ramrod parameters */ 5247 ramrod_param.cid = 0; 5248 ramrod_param.cl_id = cl_id; 5249 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 5250 ramrod_param.func_id = BP_FUNC(bp); 5251 5252 ramrod_param.pstate = &bp->sp_state; 5253 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 5254 5255 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 5256 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 5257 5258 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5259 5260 ramrod_param.ramrod_flags = ramrod_flags; 5261 ramrod_param.rx_mode_flags = rx_mode_flags; 5262 5263 ramrod_param.rx_accept_flags = rx_accept_flags; 5264 ramrod_param.tx_accept_flags = tx_accept_flags; 5265 5266 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 5267 if (rc < 0) { 5268 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 5269 return; 5270 } 5271} 5272 5273/* called with netif_addr_lock_bh() */ 5274void bnx2x_set_storm_rx_mode(struct bnx2x *bp) 5275{ 5276 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 5277 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 5278 5279#ifdef BCM_CNIC 5280 if (!NO_FCOE(bp)) 5281 5282 /* Configure rx_mode of FCoE Queue */ 5283 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 5284#endif 5285 5286 switch (bp->rx_mode) { 5287 case BNX2X_RX_MODE_NONE: 5288 /* 5289 * 'drop all' supersedes any accept flags that may have been 5290 * passed to the function. 5291 */ 5292 break; 5293 case BNX2X_RX_MODE_NORMAL: 5294 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5295 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); 5296 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5297 5298 /* internal switching mode */ 5299 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5300 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); 5301 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5302 5303 break; 5304 case BNX2X_RX_MODE_ALLMULTI: 5305 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5306 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5307 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5308 5309 /* internal switching mode */ 5310 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5311 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5312 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5313 5314 break; 5315 case BNX2X_RX_MODE_PROMISC: 5316 /* According to deffinition of SI mode, iface in promisc mode 5317 * should receive matched and unmatched (in resolution of port) 5318 * unicast packets. 5319 */ 5320 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); 5321 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5322 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5323 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5324 5325 /* internal switching mode */ 5326 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5327 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5328 5329 if (IS_MF_SI(bp)) 5330 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); 5331 else 5332 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5333 5334 break; 5335 default: 5336 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); 5337 return; 5338 } 5339 5340 if (bp->rx_mode != BNX2X_RX_MODE_NONE) { 5341 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); 5342 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); 5343 } 5344 5345 __set_bit(RAMROD_RX, &ramrod_flags); 5346 __set_bit(RAMROD_TX, &ramrod_flags); 5347 5348 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, 5349 tx_accept_flags, ramrod_flags); 5350} 5351 5352static void bnx2x_init_internal_common(struct bnx2x *bp) 5353{ 5354 int i; 5355 5356 if (IS_MF_SI(bp)) 5357 /* 5358 * In switch independent mode, the TSTORM needs to accept 5359 * packets that failed classification, since approximate match 5360 * mac addresses aren't written to NIG LLH 5361 */ 5362 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5363 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); 5364 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ 5365 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5366 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); 5367 5368 /* Zero this manually as its initialization is 5369 currently missing in the initTool */ 5370 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 5371 REG_WR(bp, BAR_USTRORM_INTMEM + 5372 USTORM_AGG_DATA_OFFSET + i * 4, 0); 5373 if (!CHIP_IS_E1x(bp)) { 5374 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 5375 CHIP_INT_MODE_IS_BC(bp) ? 5376 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 5377 } 5378} 5379 5380static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 5381{ 5382 switch (load_code) { 5383 case FW_MSG_CODE_DRV_LOAD_COMMON: 5384 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5385 bnx2x_init_internal_common(bp); 5386 /* no break */ 5387 5388 case FW_MSG_CODE_DRV_LOAD_PORT: 5389 /* nothing to do */ 5390 /* no break */ 5391 5392 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5393 /* internal memory per function is 5394 initialized inside bnx2x_pf_init */ 5395 break; 5396 5397 default: 5398 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5399 break; 5400 } 5401} 5402 5403static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 5404{ 5405 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; 5406} 5407 5408static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 5409{ 5410 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; 5411} 5412 5413static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 5414{ 5415 if (CHIP_IS_E1x(fp->bp)) 5416 return BP_L_ID(fp->bp) + fp->index; 5417 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 5418 return bnx2x_fp_igu_sb_id(fp); 5419} 5420 5421static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 5422{ 5423 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 5424 u8 cos; 5425 unsigned long q_type = 0; 5426 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 5427 fp->rx_queue = fp_idx; 5428 fp->cid = fp_idx; 5429 fp->cl_id = bnx2x_fp_cl_id(fp); 5430 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 5431 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 5432 /* qZone id equals to FW (per path) client id */ 5433 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 5434 5435 /* init shortcut */ 5436 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 5437 /* Setup SB indicies */ 5438 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 5439 5440 /* Configure Queue State object */ 5441 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 5442 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 5443 5444 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 5445 5446 /* init tx data */ 5447 for_each_cos_in_tx_queue(fp, cos) { 5448 bnx2x_init_txdata(bp, &fp->txdata[cos], 5449 CID_COS_TO_TX_ONLY_CID(fp->cid, cos), 5450 FP_COS_TO_TXQ(fp, cos), 5451 BNX2X_TX_SB_INDEX_BASE + cos); 5452 cids[cos] = fp->txdata[cos].cid; 5453 } 5454 5455 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos, 5456 BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 5457 bnx2x_sp_mapping(bp, q_rdata), q_type); 5458 5459 /** 5460 * Configure classification DBs: Always enable Tx switching 5461 */ 5462 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 5463 5464 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) " 5465 "cl_id %d fw_sb %d igu_sb %d\n", 5466 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 5467 fp->igu_sb_id); 5468 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 5469 fp->fw_sb_id, fp->igu_sb_id); 5470 5471 bnx2x_update_fpsb_idx(fp); 5472} 5473 5474void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) 5475{ 5476 int i; 5477 5478 for_each_eth_queue(bp, i) 5479 bnx2x_init_eth_fp(bp, i); 5480#ifdef BCM_CNIC 5481 if (!NO_FCOE(bp)) 5482 bnx2x_init_fcoe_fp(bp); 5483 5484 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 5485 BNX2X_VF_ID_INVALID, false, 5486 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 5487 5488#endif 5489 5490 /* Initialize MOD_ABS interrupts */ 5491 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 5492 bp->common.shmem_base, bp->common.shmem2_base, 5493 BP_PORT(bp)); 5494 /* ensure status block indices were read */ 5495 rmb(); 5496 5497 bnx2x_init_def_sb(bp); 5498 bnx2x_update_dsb_idx(bp); 5499 bnx2x_init_rx_rings(bp); 5500 bnx2x_init_tx_rings(bp); 5501 bnx2x_init_sp_ring(bp); 5502 bnx2x_init_eq_ring(bp); 5503 bnx2x_init_internal(bp, load_code); 5504 bnx2x_pf_init(bp); 5505 bnx2x_stats_init(bp); 5506 5507 /* flush all before enabling interrupts */ 5508 mb(); 5509 mmiowb(); 5510 5511 bnx2x_int_enable(bp); 5512 5513 /* Check for SPIO5 */ 5514 bnx2x_attn_int_deasserted0(bp, 5515 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 5516 AEU_INPUTS_ATTN_BITS_SPIO5); 5517} 5518 5519/* end of nic init */ 5520 5521/* 5522 * gzip service functions 5523 */ 5524 5525static int bnx2x_gunzip_init(struct bnx2x *bp) 5526{ 5527 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 5528 &bp->gunzip_mapping, GFP_KERNEL); 5529 if (bp->gunzip_buf == NULL) 5530 goto gunzip_nomem1; 5531 5532 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 5533 if (bp->strm == NULL) 5534 goto gunzip_nomem2; 5535 5536 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 5537 if (bp->strm->workspace == NULL) 5538 goto gunzip_nomem3; 5539 5540 return 0; 5541 5542gunzip_nomem3: 5543 kfree(bp->strm); 5544 bp->strm = NULL; 5545 5546gunzip_nomem2: 5547 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5548 bp->gunzip_mapping); 5549 bp->gunzip_buf = NULL; 5550 5551gunzip_nomem1: 5552 netdev_err(bp->dev, "Cannot allocate firmware buffer for" 5553 " un-compression\n"); 5554 return -ENOMEM; 5555} 5556 5557static void bnx2x_gunzip_end(struct bnx2x *bp) 5558{ 5559 if (bp->strm) { 5560 vfree(bp->strm->workspace); 5561 kfree(bp->strm); 5562 bp->strm = NULL; 5563 } 5564 5565 if (bp->gunzip_buf) { 5566 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5567 bp->gunzip_mapping); 5568 bp->gunzip_buf = NULL; 5569 } 5570} 5571 5572static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 5573{ 5574 int n, rc; 5575 5576 /* check gzip header */ 5577 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 5578 BNX2X_ERR("Bad gzip header\n"); 5579 return -EINVAL; 5580 } 5581 5582 n = 10; 5583 5584#define FNAME 0x8 5585 5586 if (zbuf[3] & FNAME) 5587 while ((zbuf[n++] != 0) && (n < len)); 5588 5589 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 5590 bp->strm->avail_in = len - n; 5591 bp->strm->next_out = bp->gunzip_buf; 5592 bp->strm->avail_out = FW_BUF_SIZE; 5593 5594 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 5595 if (rc != Z_OK) 5596 return rc; 5597 5598 rc = zlib_inflate(bp->strm, Z_FINISH); 5599 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 5600 netdev_err(bp->dev, "Firmware decompression error: %s\n", 5601 bp->strm->msg); 5602 5603 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 5604 if (bp->gunzip_outlen & 0x3) 5605 netdev_err(bp->dev, "Firmware decompression error:" 5606 " gunzip_outlen (%d) not aligned\n", 5607 bp->gunzip_outlen); 5608 bp->gunzip_outlen >>= 2; 5609 5610 zlib_inflateEnd(bp->strm); 5611 5612 if (rc == Z_STREAM_END) 5613 return 0; 5614 5615 return rc; 5616} 5617 5618/* nic load/unload */ 5619 5620/* 5621 * General service functions 5622 */ 5623 5624/* send a NIG loopback debug packet */ 5625static void bnx2x_lb_pckt(struct bnx2x *bp) 5626{ 5627 u32 wb_write[3]; 5628 5629 /* Ethernet source and destination addresses */ 5630 wb_write[0] = 0x55555555; 5631 wb_write[1] = 0x55555555; 5632 wb_write[2] = 0x20; /* SOP */ 5633 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5634 5635 /* NON-IP protocol */ 5636 wb_write[0] = 0x09000000; 5637 wb_write[1] = 0x55555555; 5638 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 5639 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5640} 5641 5642/* some of the internal memories 5643 * are not directly readable from the driver 5644 * to test them we send debug packets 5645 */ 5646static int bnx2x_int_mem_test(struct bnx2x *bp) 5647{ 5648 int factor; 5649 int count, i; 5650 u32 val = 0; 5651 5652 if (CHIP_REV_IS_FPGA(bp)) 5653 factor = 120; 5654 else if (CHIP_REV_IS_EMUL(bp)) 5655 factor = 200; 5656 else 5657 factor = 1; 5658 5659 /* Disable inputs of parser neighbor blocks */ 5660 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5661 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5662 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5663 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5664 5665 /* Write 0 to parser credits for CFC search request */ 5666 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5667 5668 /* send Ethernet packet */ 5669 bnx2x_lb_pckt(bp); 5670 5671 /* TODO do i reset NIG statistic? */ 5672 /* Wait until NIG register shows 1 packet of size 0x10 */ 5673 count = 1000 * factor; 5674 while (count) { 5675 5676 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5677 val = *bnx2x_sp(bp, wb_data[0]); 5678 if (val == 0x10) 5679 break; 5680 5681 msleep(10); 5682 count--; 5683 } 5684 if (val != 0x10) { 5685 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5686 return -1; 5687 } 5688 5689 /* Wait until PRS register shows 1 packet */ 5690 count = 1000 * factor; 5691 while (count) { 5692 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5693 if (val == 1) 5694 break; 5695 5696 msleep(10); 5697 count--; 5698 } 5699 if (val != 0x1) { 5700 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5701 return -2; 5702 } 5703 5704 /* Reset and init BRB, PRS */ 5705 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5706 msleep(50); 5707 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5708 msleep(50); 5709 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5710 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5711 5712 DP(NETIF_MSG_HW, "part2\n"); 5713 5714 /* Disable inputs of parser neighbor blocks */ 5715 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5716 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5717 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5718 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5719 5720 /* Write 0 to parser credits for CFC search request */ 5721 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5722 5723 /* send 10 Ethernet packets */ 5724 for (i = 0; i < 10; i++) 5725 bnx2x_lb_pckt(bp); 5726 5727 /* Wait until NIG register shows 10 + 1 5728 packets of size 11*0x10 = 0xb0 */ 5729 count = 1000 * factor; 5730 while (count) { 5731 5732 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5733 val = *bnx2x_sp(bp, wb_data[0]); 5734 if (val == 0xb0) 5735 break; 5736 5737 msleep(10); 5738 count--; 5739 } 5740 if (val != 0xb0) { 5741 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5742 return -3; 5743 } 5744 5745 /* Wait until PRS register shows 2 packets */ 5746 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5747 if (val != 2) 5748 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5749 5750 /* Write 1 to parser credits for CFC search request */ 5751 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 5752 5753 /* Wait until PRS register shows 3 packets */ 5754 msleep(10 * factor); 5755 /* Wait until NIG register shows 1 packet of size 0x10 */ 5756 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5757 if (val != 3) 5758 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5759 5760 /* clear NIG EOP FIFO */ 5761 for (i = 0; i < 11; i++) 5762 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 5763 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 5764 if (val != 1) { 5765 BNX2X_ERR("clear of NIG failed\n"); 5766 return -4; 5767 } 5768 5769 /* Reset and init BRB, PRS, NIG */ 5770 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5771 msleep(50); 5772 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5773 msleep(50); 5774 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5775 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5776#ifndef BCM_CNIC 5777 /* set NIC mode */ 5778 REG_WR(bp, PRS_REG_NIC_MODE, 1); 5779#endif 5780 5781 /* Enable inputs of parser neighbor blocks */ 5782 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 5783 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 5784 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 5785 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 5786 5787 DP(NETIF_MSG_HW, "done\n"); 5788 5789 return 0; /* OK */ 5790} 5791 5792static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 5793{ 5794 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 5795 if (!CHIP_IS_E1x(bp)) 5796 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 5797 else 5798 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 5799 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 5800 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 5801 /* 5802 * mask read length error interrupts in brb for parser 5803 * (parsing unit and 'checksum and crc' unit) 5804 * these errors are legal (PU reads fixed length and CAC can cause 5805 * read length error on truncated packets) 5806 */ 5807 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 5808 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 5809 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 5810 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 5811 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 5812 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 5813/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 5814/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 5815 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 5816 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 5817 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 5818/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 5819/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 5820 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 5821 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 5822 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 5823 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 5824/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 5825/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 5826 5827 if (CHIP_REV_IS_FPGA(bp)) 5828 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); 5829 else if (!CHIP_IS_E1x(bp)) 5830 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 5831 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF 5832 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT 5833 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN 5834 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED 5835 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); 5836 else 5837 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); 5838 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 5839 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 5840 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 5841/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 5842 5843 if (!CHIP_IS_E1x(bp)) 5844 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 5845 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 5846 5847 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 5848 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 5849/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 5850 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 5851} 5852 5853static void bnx2x_reset_common(struct bnx2x *bp) 5854{ 5855 u32 val = 0x1400; 5856 5857 /* reset_common */ 5858 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 5859 0xd3ffff7f); 5860 5861 if (CHIP_IS_E3(bp)) { 5862 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 5863 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 5864 } 5865 5866 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); 5867} 5868 5869static void bnx2x_setup_dmae(struct bnx2x *bp) 5870{ 5871 bp->dmae_ready = 0; 5872 spin_lock_init(&bp->dmae_lock); 5873} 5874 5875static void bnx2x_init_pxp(struct bnx2x *bp) 5876{ 5877 u16 devctl; 5878 int r_order, w_order; 5879 5880 pci_read_config_word(bp->pdev, 5881 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); 5882 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); 5883 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 5884 if (bp->mrrs == -1) 5885 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); 5886 else { 5887 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); 5888 r_order = bp->mrrs; 5889 } 5890 5891 bnx2x_init_pxp_arb(bp, r_order, w_order); 5892} 5893 5894static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 5895{ 5896 int is_required; 5897 u32 val; 5898 int port; 5899 5900 if (BP_NOMCP(bp)) 5901 return; 5902 5903 is_required = 0; 5904 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 5905 SHARED_HW_CFG_FAN_FAILURE_MASK; 5906 5907 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) 5908 is_required = 1; 5909 5910 /* 5911 * The fan failure mechanism is usually related to the PHY type since 5912 * the power consumption of the board is affected by the PHY. Currently, 5913 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 5914 */ 5915 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 5916 for (port = PORT_0; port < PORT_MAX; port++) { 5917 is_required |= 5918 bnx2x_fan_failure_det_req( 5919 bp, 5920 bp->common.shmem_base, 5921 bp->common.shmem2_base, 5922 port); 5923 } 5924 5925 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 5926 5927 if (is_required == 0) 5928 return; 5929 5930 /* Fan failure is indicated by SPIO 5 */ 5931 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, 5932 MISC_REGISTERS_SPIO_INPUT_HI_Z); 5933 5934 /* set to active low mode */ 5935 val = REG_RD(bp, MISC_REG_SPIO_INT); 5936 val |= ((1 << MISC_REGISTERS_SPIO_5) << 5937 MISC_REGISTERS_SPIO_INT_OLD_SET_POS); 5938 REG_WR(bp, MISC_REG_SPIO_INT, val); 5939 5940 /* enable interrupt to signal the IGU */ 5941 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 5942 val |= (1 << MISC_REGISTERS_SPIO_5); 5943 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 5944} 5945 5946static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) 5947{ 5948 u32 offset = 0; 5949 5950 if (CHIP_IS_E1(bp)) 5951 return; 5952 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) 5953 return; 5954 5955 switch (BP_ABS_FUNC(bp)) { 5956 case 0: 5957 offset = PXP2_REG_PGL_PRETEND_FUNC_F0; 5958 break; 5959 case 1: 5960 offset = PXP2_REG_PGL_PRETEND_FUNC_F1; 5961 break; 5962 case 2: 5963 offset = PXP2_REG_PGL_PRETEND_FUNC_F2; 5964 break; 5965 case 3: 5966 offset = PXP2_REG_PGL_PRETEND_FUNC_F3; 5967 break; 5968 case 4: 5969 offset = PXP2_REG_PGL_PRETEND_FUNC_F4; 5970 break; 5971 case 5: 5972 offset = PXP2_REG_PGL_PRETEND_FUNC_F5; 5973 break; 5974 case 6: 5975 offset = PXP2_REG_PGL_PRETEND_FUNC_F6; 5976 break; 5977 case 7: 5978 offset = PXP2_REG_PGL_PRETEND_FUNC_F7; 5979 break; 5980 default: 5981 return; 5982 } 5983 5984 REG_WR(bp, offset, pretend_func_num); 5985 REG_RD(bp, offset); 5986 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); 5987} 5988 5989void bnx2x_pf_disable(struct bnx2x *bp) 5990{ 5991 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 5992 val &= ~IGU_PF_CONF_FUNC_EN; 5993 5994 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 5995 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 5996 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); 5997} 5998 5999static inline void bnx2x__common_init_phy(struct bnx2x *bp) 6000{ 6001 u32 shmem_base[2], shmem2_base[2]; 6002 shmem_base[0] = bp->common.shmem_base; 6003 shmem2_base[0] = bp->common.shmem2_base; 6004 if (!CHIP_IS_E1x(bp)) { 6005 shmem_base[1] = 6006 SHMEM2_RD(bp, other_shmem_base_addr); 6007 shmem2_base[1] = 6008 SHMEM2_RD(bp, other_shmem2_base_addr); 6009 } 6010 bnx2x_acquire_phy_lock(bp); 6011 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, 6012 bp->common.chip_id); 6013 bnx2x_release_phy_lock(bp); 6014} 6015 6016/** 6017 * bnx2x_init_hw_common - initialize the HW at the COMMON phase. 6018 * 6019 * @bp: driver handle 6020 */ 6021static int bnx2x_init_hw_common(struct bnx2x *bp) 6022{ 6023 u32 val; 6024 6025 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp)); 6026 6027 /* 6028 * take the UNDI lock to protect undi_unload flow from accessing 6029 * registers while we're resetting the chip 6030 */ 6031 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6032 6033 bnx2x_reset_common(bp); 6034 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 6035 6036 val = 0xfffc; 6037 if (CHIP_IS_E3(bp)) { 6038 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 6039 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 6040 } 6041 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 6042 6043 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6044 6045 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 6046 6047 if (!CHIP_IS_E1x(bp)) { 6048 u8 abs_func_id; 6049 6050 /** 6051 * 4-port mode or 2-port mode we need to turn of master-enable 6052 * for everyone, after that, turn it back on for self. 6053 * so, we disregard multi-function or not, and always disable 6054 * for all functions on the given path, this means 0,2,4,6 for 6055 * path 0 and 1,3,5,7 for path 1 6056 */ 6057 for (abs_func_id = BP_PATH(bp); 6058 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { 6059 if (abs_func_id == BP_ABS_FUNC(bp)) { 6060 REG_WR(bp, 6061 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 6062 1); 6063 continue; 6064 } 6065 6066 bnx2x_pretend_func(bp, abs_func_id); 6067 /* clear pf enable */ 6068 bnx2x_pf_disable(bp); 6069 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6070 } 6071 } 6072 6073 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); 6074 if (CHIP_IS_E1(bp)) { 6075 /* enable HW interrupt from PXP on USDM overflow 6076 bit 16 on INT_MASK_0 */ 6077 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 6078 } 6079 6080 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); 6081 bnx2x_init_pxp(bp); 6082 6083#ifdef __BIG_ENDIAN 6084 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); 6085 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); 6086 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 6087 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 6088 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 6089 /* make sure this value is 0 */ 6090 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); 6091 6092/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ 6093 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); 6094 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); 6095 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); 6096 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 6097#endif 6098 6099 bnx2x_ilt_init_page_size(bp, INITOP_SET); 6100 6101 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 6102 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 6103 6104 /* let the HW do it's magic ... */ 6105 msleep(100); 6106 /* finish PXP init */ 6107 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); 6108 if (val != 1) { 6109 BNX2X_ERR("PXP2 CFG failed\n"); 6110 return -EBUSY; 6111 } 6112 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); 6113 if (val != 1) { 6114 BNX2X_ERR("PXP2 RD_INIT failed\n"); 6115 return -EBUSY; 6116 } 6117 6118 /* Timers bug workaround E2 only. We need to set the entire ILT to 6119 * have entries with value "0" and valid bit on. 6120 * This needs to be done by the first PF that is loaded in a path 6121 * (i.e. common phase) 6122 */ 6123 if (!CHIP_IS_E1x(bp)) { 6124/* In E2 there is a bug in the timers block that can cause function 6 / 7 6125 * (i.e. vnic3) to start even if it is marked as "scan-off". 6126 * This occurs when a different function (func2,3) is being marked 6127 * as "scan-off". Real-life scenario for example: if a driver is being 6128 * load-unloaded while func6,7 are down. This will cause the timer to access 6129 * the ilt, translate to a logical address and send a request to read/write. 6130 * Since the ilt for the function that is down is not valid, this will cause 6131 * a translation error which is unrecoverable. 6132 * The Workaround is intended to make sure that when this happens nothing fatal 6133 * will occur. The workaround: 6134 * 1. First PF driver which loads on a path will: 6135 * a. After taking the chip out of reset, by using pretend, 6136 * it will write "0" to the following registers of 6137 * the other vnics. 6138 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6139 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 6140 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 6141 * And for itself it will write '1' to 6142 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 6143 * dmae-operations (writing to pram for example.) 6144 * note: can be done for only function 6,7 but cleaner this 6145 * way. 6146 * b. Write zero+valid to the entire ILT. 6147 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 6148 * VNIC3 (of that port). The range allocated will be the 6149 * entire ILT. This is needed to prevent ILT range error. 6150 * 2. Any PF driver load flow: 6151 * a. ILT update with the physical addresses of the allocated 6152 * logical pages. 6153 * b. Wait 20msec. - note that this timeout is needed to make 6154 * sure there are no requests in one of the PXP internal 6155 * queues with "old" ILT addresses. 6156 * c. PF enable in the PGLC. 6157 * d. Clear the was_error of the PF in the PGLC. (could have 6158 * occured while driver was down) 6159 * e. PF enable in the CFC (WEAK + STRONG) 6160 * f. Timers scan enable 6161 * 3. PF driver unload flow: 6162 * a. Clear the Timers scan_en. 6163 * b. Polling for scan_on=0 for that PF. 6164 * c. Clear the PF enable bit in the PXP. 6165 * d. Clear the PF enable in the CFC (WEAK + STRONG) 6166 * e. Write zero+valid to all ILT entries (The valid bit must 6167 * stay set) 6168 * f. If this is VNIC 3 of a port then also init 6169 * first_timers_ilt_entry to zero and last_timers_ilt_entry 6170 * to the last enrty in the ILT. 6171 * 6172 * Notes: 6173 * Currently the PF error in the PGLC is non recoverable. 6174 * In the future the there will be a recovery routine for this error. 6175 * Currently attention is masked. 6176 * Having an MCP lock on the load/unload process does not guarantee that 6177 * there is no Timer disable during Func6/7 enable. This is because the 6178 * Timers scan is currently being cleared by the MCP on FLR. 6179 * Step 2.d can be done only for PF6/7 and the driver can also check if 6180 * there is error before clearing it. But the flow above is simpler and 6181 * more general. 6182 * All ILT entries are written by zero+valid and not just PF6/7 6183 * ILT entries since in the future the ILT entries allocation for 6184 * PF-s might be dynamic. 6185 */ 6186 struct ilt_client_info ilt_cli; 6187 struct bnx2x_ilt ilt; 6188 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 6189 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); 6190 6191 /* initialize dummy TM client */ 6192 ilt_cli.start = 0; 6193 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 6194 ilt_cli.client_num = ILT_CLIENT_TM; 6195 6196 /* Step 1: set zeroes to all ilt page entries with valid bit on 6197 * Step 2: set the timers first/last ilt entry to point 6198 * to the entire range to prevent ILT range error for 3rd/4th 6199 * vnic (this code assumes existance of the vnic) 6200 * 6201 * both steps performed by call to bnx2x_ilt_client_init_op() 6202 * with dummy TM client 6203 * 6204 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 6205 * and his brother are split registers 6206 */ 6207 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); 6208 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); 6209 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6210 6211 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); 6212 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); 6213 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 6214 } 6215 6216 6217 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 6218 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 6219 6220 if (!CHIP_IS_E1x(bp)) { 6221 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : 6222 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); 6223 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); 6224 6225 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); 6226 6227 /* let the HW do it's magic ... */ 6228 do { 6229 msleep(200); 6230 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); 6231 } while (factor-- && (val != 1)); 6232 6233 if (val != 1) { 6234 BNX2X_ERR("ATC_INIT failed\n"); 6235 return -EBUSY; 6236 } 6237 } 6238 6239 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); 6240 6241 /* clean the DMAE memory */ 6242 bp->dmae_ready = 1; 6243 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); 6244 6245 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); 6246 6247 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); 6248 6249 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); 6250 6251 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); 6252 6253 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); 6254 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); 6255 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); 6256 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); 6257 6258 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); 6259 6260 6261 /* QM queues pointers table */ 6262 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); 6263 6264 /* soft reset pulse */ 6265 REG_WR(bp, QM_REG_SOFT_RESET, 1); 6266 REG_WR(bp, QM_REG_SOFT_RESET, 0); 6267 6268#ifdef BCM_CNIC 6269 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); 6270#endif 6271 6272 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); 6273 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); 6274 if (!CHIP_REV_IS_SLOW(bp)) 6275 /* enable hw interrupt from doorbell Q */ 6276 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6277 6278 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6279 6280 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6281 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 6282 6283 if (!CHIP_IS_E1(bp)) 6284 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); 6285 6286 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) 6287 /* Bit-map indicating which L2 hdrs may appear 6288 * after the basic Ethernet header 6289 */ 6290 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 6291 bp->path_has_ovlan ? 7 : 6); 6292 6293 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); 6294 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); 6295 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); 6296 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); 6297 6298 if (!CHIP_IS_E1x(bp)) { 6299 /* reset VFC memories */ 6300 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6301 VFC_MEMORIES_RST_REG_CAM_RST | 6302 VFC_MEMORIES_RST_REG_RAM_RST); 6303 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6304 VFC_MEMORIES_RST_REG_CAM_RST | 6305 VFC_MEMORIES_RST_REG_RAM_RST); 6306 6307 msleep(20); 6308 } 6309 6310 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); 6311 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); 6312 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); 6313 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); 6314 6315 /* sync semi rtc */ 6316 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6317 0x80000000); 6318 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 6319 0x80000000); 6320 6321 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); 6322 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); 6323 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); 6324 6325 if (!CHIP_IS_E1x(bp)) 6326 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 6327 bp->path_has_ovlan ? 7 : 6); 6328 6329 REG_WR(bp, SRC_REG_SOFT_RST, 1); 6330 6331 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); 6332 6333#ifdef BCM_CNIC 6334 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 6335 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 6336 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); 6337 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); 6338 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); 6339 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 6340 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); 6341 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 6342 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); 6343 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); 6344#endif 6345 REG_WR(bp, SRC_REG_SOFT_RST, 0); 6346 6347 if (sizeof(union cdu_context) != 1024) 6348 /* we currently assume that a context is 1024 bytes */ 6349 dev_alert(&bp->pdev->dev, "please adjust the size " 6350 "of cdu_context(%ld)\n", 6351 (long)sizeof(union cdu_context)); 6352 6353 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 6354 val = (4 << 24) + (0 << 12) + 1024; 6355 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); 6356 6357 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); 6358 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); 6359 /* enable context validation interrupt from CFC */ 6360 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6361 6362 /* set the thresholds to prevent CFC/CDU race */ 6363 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 6364 6365 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); 6366 6367 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) 6368 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); 6369 6370 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); 6371 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); 6372 6373 /* Reset PCIE errors for debug */ 6374 REG_WR(bp, 0x2814, 0xffffffff); 6375 REG_WR(bp, 0x3820, 0xffffffff); 6376 6377 if (!CHIP_IS_E1x(bp)) { 6378 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 6379 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 6380 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 6381 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 6382 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 6383 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 6384 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 6385 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 6386 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 6387 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 6388 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 6389 } 6390 6391 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); 6392 if (!CHIP_IS_E1(bp)) { 6393 /* in E3 this done in per-port section */ 6394 if (!CHIP_IS_E3(bp)) 6395 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6396 } 6397 if (CHIP_IS_E1H(bp)) 6398 /* not applicable for E2 (and above ...) */ 6399 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); 6400 6401 if (CHIP_REV_IS_SLOW(bp)) 6402 msleep(200); 6403 6404 /* finish CFC init */ 6405 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); 6406 if (val != 1) { 6407 BNX2X_ERR("CFC LL_INIT failed\n"); 6408 return -EBUSY; 6409 } 6410 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); 6411 if (val != 1) { 6412 BNX2X_ERR("CFC AC_INIT failed\n"); 6413 return -EBUSY; 6414 } 6415 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 6416 if (val != 1) { 6417 BNX2X_ERR("CFC CAM_INIT failed\n"); 6418 return -EBUSY; 6419 } 6420 REG_WR(bp, CFC_REG_DEBUG0, 0); 6421 6422 if (CHIP_IS_E1(bp)) { 6423 /* read NIG statistic 6424 to see if this is our first up since powerup */ 6425 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6426 val = *bnx2x_sp(bp, wb_data[0]); 6427 6428 /* do internal memory self test */ 6429 if ((val == 0) && bnx2x_int_mem_test(bp)) { 6430 BNX2X_ERR("internal mem self test failed\n"); 6431 return -EBUSY; 6432 } 6433 } 6434 6435 bnx2x_setup_fan_failure_detection(bp); 6436 6437 /* clear PXP2 attentions */ 6438 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 6439 6440 bnx2x_enable_blocks_attention(bp); 6441 bnx2x_enable_blocks_parity(bp); 6442 6443 if (!BP_NOMCP(bp)) { 6444 if (CHIP_IS_E1x(bp)) 6445 bnx2x__common_init_phy(bp); 6446 } else 6447 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 6448 6449 return 0; 6450} 6451 6452/** 6453 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. 6454 * 6455 * @bp: driver handle 6456 */ 6457static int bnx2x_init_hw_common_chip(struct bnx2x *bp) 6458{ 6459 int rc = bnx2x_init_hw_common(bp); 6460 6461 if (rc) 6462 return rc; 6463 6464 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 6465 if (!BP_NOMCP(bp)) 6466 bnx2x__common_init_phy(bp); 6467 6468 return 0; 6469} 6470 6471static int bnx2x_init_hw_port(struct bnx2x *bp) 6472{ 6473 int port = BP_PORT(bp); 6474 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 6475 u32 low, high; 6476 u32 val; 6477 6478 bnx2x__link_reset(bp); 6479 6480 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port); 6481 6482 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 6483 6484 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6485 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6486 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6487 6488 /* Timers bug workaround: disables the pf_master bit in pglue at 6489 * common phase, we need to enable it here before any dmae access are 6490 * attempted. Therefore we manually added the enable-master to the 6491 * port phase (it also happens in the function phase) 6492 */ 6493 if (!CHIP_IS_E1x(bp)) 6494 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6495 6496 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6497 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6498 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6499 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6500 6501 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6502 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6503 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6504 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6505 6506 /* QM cid (connection) count */ 6507 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); 6508 6509#ifdef BCM_CNIC 6510 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6511 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 6512 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 6513#endif 6514 6515 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6516 6517 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { 6518 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6519 6520 if (IS_MF(bp)) 6521 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 6522 else if (bp->dev->mtu > 4096) { 6523 if (bp->flags & ONE_PORT_FLAG) 6524 low = 160; 6525 else { 6526 val = bp->dev->mtu; 6527 /* (24*1024 + val*4)/256 */ 6528 low = 96 + (val/64) + 6529 ((val % 64) ? 1 : 0); 6530 } 6531 } else 6532 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 6533 high = low + 56; /* 14*1024/256 */ 6534 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 6535 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 6536 } 6537 6538 if (CHIP_MODE_IS_4_PORT(bp)) 6539 REG_WR(bp, (BP_PORT(bp) ? 6540 BRB1_REG_MAC_GUARANTIED_1 : 6541 BRB1_REG_MAC_GUARANTIED_0), 40); 6542 6543 6544 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6545 if (CHIP_IS_E3B0(bp)) 6546 /* Ovlan exists only if we are in multi-function + 6547 * switch-dependent mode, in switch-independent there 6548 * is no ovlan headers 6549 */ 6550 REG_WR(bp, BP_PORT(bp) ? 6551 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 6552 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 6553 (bp->path_has_ovlan ? 7 : 6)); 6554 6555 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6556 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6557 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6558 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6559 6560 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6561 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6562 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6563 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6564 6565 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6566 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6567 6568 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6569 6570 if (CHIP_IS_E1x(bp)) { 6571 /* configure PBF to work without PAUSE mtu 9000 */ 6572 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 6573 6574 /* update threshold */ 6575 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 6576 /* update init credit */ 6577 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 6578 6579 /* probe changes */ 6580 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 6581 udelay(50); 6582 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 6583 } 6584 6585#ifdef BCM_CNIC 6586 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6587#endif 6588 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6589 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6590 6591 if (CHIP_IS_E1(bp)) { 6592 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6593 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6594 } 6595 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6596 6597 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6598 6599 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6600 /* init aeu_mask_attn_func_0/1: 6601 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 6602 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 6603 * bits 4-7 are used for "per vn group attention" */ 6604 val = IS_MF(bp) ? 0xF7 : 0x7; 6605 /* Enable DCBX attention for all but E1 */ 6606 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 6607 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 6608 6609 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6610 6611 if (!CHIP_IS_E1x(bp)) { 6612 /* Bit-map indicating which L2 hdrs may appear after the 6613 * basic Ethernet header 6614 */ 6615 REG_WR(bp, BP_PORT(bp) ? 6616 NIG_REG_P1_HDRS_AFTER_BASIC : 6617 NIG_REG_P0_HDRS_AFTER_BASIC, 6618 IS_MF_SD(bp) ? 7 : 6); 6619 6620 if (CHIP_IS_E3(bp)) 6621 REG_WR(bp, BP_PORT(bp) ? 6622 NIG_REG_LLH1_MF_MODE : 6623 NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6624 } 6625 if (!CHIP_IS_E3(bp)) 6626 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 6627 6628 if (!CHIP_IS_E1(bp)) { 6629 /* 0x2 disable mf_ov, 0x1 enable */ 6630 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 6631 (IS_MF_SD(bp) ? 0x1 : 0x2)); 6632 6633 if (!CHIP_IS_E1x(bp)) { 6634 val = 0; 6635 switch (bp->mf_mode) { 6636 case MULTI_FUNCTION_SD: 6637 val = 1; 6638 break; 6639 case MULTI_FUNCTION_SI: 6640 val = 2; 6641 break; 6642 } 6643 6644 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : 6645 NIG_REG_LLH0_CLS_TYPE), val); 6646 } 6647 { 6648 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 6649 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 6650 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 6651 } 6652 } 6653 6654 6655 /* If SPIO5 is set to generate interrupts, enable it for this port */ 6656 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6657 if (val & (1 << MISC_REGISTERS_SPIO_5)) { 6658 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 6659 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 6660 val = REG_RD(bp, reg_addr); 6661 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 6662 REG_WR(bp, reg_addr, val); 6663 } 6664 6665 return 0; 6666} 6667 6668static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 6669{ 6670 int reg; 6671 6672 if (CHIP_IS_E1(bp)) 6673 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 6674 else 6675 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 6676 6677 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr)); 6678} 6679 6680static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) 6681{ 6682 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); 6683} 6684 6685static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) 6686{ 6687 u32 i, base = FUNC_ILT_BASE(func); 6688 for (i = base; i < base + ILT_PER_FUNC; i++) 6689 bnx2x_ilt_wr(bp, i, 0); 6690} 6691 6692static int bnx2x_init_hw_func(struct bnx2x *bp) 6693{ 6694 int port = BP_PORT(bp); 6695 int func = BP_FUNC(bp); 6696 int init_phase = PHASE_PF0 + func; 6697 struct bnx2x_ilt *ilt = BP_ILT(bp); 6698 u16 cdu_ilt_start; 6699 u32 addr, val; 6700 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 6701 int i, main_mem_width, rc; 6702 6703 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func); 6704 6705 /* FLR cleanup - hmmm */ 6706 if (!CHIP_IS_E1x(bp)) { 6707 rc = bnx2x_pf_flr_clnup(bp); 6708 if (rc) 6709 return rc; 6710 } 6711 6712 /* set MSI reconfigure capability */ 6713 if (bp->common.int_block == INT_BLOCK_HC) { 6714 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 6715 val = REG_RD(bp, addr); 6716 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 6717 REG_WR(bp, addr, val); 6718 } 6719 6720 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6721 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6722 6723 ilt = BP_ILT(bp); 6724 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 6725 6726 for (i = 0; i < L2_ILT_LINES(bp); i++) { 6727 ilt->lines[cdu_ilt_start + i].page = 6728 bp->context.vcxt + (ILT_PAGE_CIDS * i); 6729 ilt->lines[cdu_ilt_start + i].page_mapping = 6730 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i); 6731 /* cdu ilt pages are allocated manually so there's no need to 6732 set the size */ 6733 } 6734 bnx2x_ilt_init_op(bp, INITOP_SET); 6735 6736#ifdef BCM_CNIC 6737 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); 6738 6739 /* T1 hash bits value determines the T1 number of entries */ 6740 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 6741#endif 6742 6743#ifndef BCM_CNIC 6744 /* set NIC mode */ 6745 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6746#endif /* BCM_CNIC */ 6747 6748 if (!CHIP_IS_E1x(bp)) { 6749 u32 pf_conf = IGU_PF_CONF_FUNC_EN; 6750 6751 /* Turn on a single ISR mode in IGU if driver is going to use 6752 * INT#x or MSI 6753 */ 6754 if (!(bp->flags & USING_MSIX_FLAG)) 6755 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 6756 /* 6757 * Timers workaround bug: function init part. 6758 * Need to wait 20msec after initializing ILT, 6759 * needed to make sure there are no requests in 6760 * one of the PXP internal queues with "old" ILT addresses 6761 */ 6762 msleep(20); 6763 /* 6764 * Master enable - Due to WB DMAE writes performed before this 6765 * register is re-initialized as part of the regular function 6766 * init 6767 */ 6768 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6769 /* Enable the function in IGU */ 6770 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); 6771 } 6772 6773 bp->dmae_ready = 1; 6774 6775 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6776 6777 if (!CHIP_IS_E1x(bp)) 6778 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); 6779 6780 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6781 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6782 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6783 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6784 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6785 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6786 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6787 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6788 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6789 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6790 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6791 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6792 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6793 6794 if (!CHIP_IS_E1x(bp)) 6795 REG_WR(bp, QM_REG_PF_EN, 1); 6796 6797 if (!CHIP_IS_E1x(bp)) { 6798 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6799 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6800 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6801 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6802 } 6803 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6804 6805 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6806 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6807 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6808 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6809 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6810 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6811 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6812 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6813 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6814 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6815 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6816 if (!CHIP_IS_E1x(bp)) 6817 REG_WR(bp, PBF_REG_DISABLE_PF, 0); 6818 6819 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6820 6821 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6822 6823 if (!CHIP_IS_E1x(bp)) 6824 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); 6825 6826 if (IS_MF(bp)) { 6827 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 6828 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); 6829 } 6830 6831 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6832 6833 /* HC init per function */ 6834 if (bp->common.int_block == INT_BLOCK_HC) { 6835 if (CHIP_IS_E1H(bp)) { 6836 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6837 6838 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6839 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6840 } 6841 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6842 6843 } else { 6844 int num_segs, sb_idx, prod_offset; 6845 6846 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6847 6848 if (!CHIP_IS_E1x(bp)) { 6849 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 6850 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 6851 } 6852 6853 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6854 6855 if (!CHIP_IS_E1x(bp)) { 6856 int dsb_idx = 0; 6857 /** 6858 * Producer memory: 6859 * E2 mode: address 0-135 match to the mapping memory; 6860 * 136 - PF0 default prod; 137 - PF1 default prod; 6861 * 138 - PF2 default prod; 139 - PF3 default prod; 6862 * 140 - PF0 attn prod; 141 - PF1 attn prod; 6863 * 142 - PF2 attn prod; 143 - PF3 attn prod; 6864 * 144-147 reserved. 6865 * 6866 * E1.5 mode - In backward compatible mode; 6867 * for non default SB; each even line in the memory 6868 * holds the U producer and each odd line hold 6869 * the C producer. The first 128 producers are for 6870 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 6871 * producers are for the DSB for each PF. 6872 * Each PF has five segments: (the order inside each 6873 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 6874 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 6875 * 144-147 attn prods; 6876 */ 6877 /* non-default-status-blocks */ 6878 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6879 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 6880 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { 6881 prod_offset = (bp->igu_base_sb + sb_idx) * 6882 num_segs; 6883 6884 for (i = 0; i < num_segs; i++) { 6885 addr = IGU_REG_PROD_CONS_MEMORY + 6886 (prod_offset + i) * 4; 6887 REG_WR(bp, addr, 0); 6888 } 6889 /* send consumer update with value 0 */ 6890 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, 6891 USTORM_ID, 0, IGU_INT_NOP, 1); 6892 bnx2x_igu_clear_sb(bp, 6893 bp->igu_base_sb + sb_idx); 6894 } 6895 6896 /* default-status-blocks */ 6897 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6898 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 6899 6900 if (CHIP_MODE_IS_4_PORT(bp)) 6901 dsb_idx = BP_FUNC(bp); 6902 else 6903 dsb_idx = BP_VN(bp); 6904 6905 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 6906 IGU_BC_BASE_DSB_PROD + dsb_idx : 6907 IGU_NORM_BASE_DSB_PROD + dsb_idx); 6908 6909 /* 6910 * igu prods come in chunks of E1HVN_MAX (4) - 6911 * does not matters what is the current chip mode 6912 */ 6913 for (i = 0; i < (num_segs * E1HVN_MAX); 6914 i += E1HVN_MAX) { 6915 addr = IGU_REG_PROD_CONS_MEMORY + 6916 (prod_offset + i)*4; 6917 REG_WR(bp, addr, 0); 6918 } 6919 /* send consumer update with 0 */ 6920 if (CHIP_INT_MODE_IS_BC(bp)) { 6921 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6922 USTORM_ID, 0, IGU_INT_NOP, 1); 6923 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6924 CSTORM_ID, 0, IGU_INT_NOP, 1); 6925 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6926 XSTORM_ID, 0, IGU_INT_NOP, 1); 6927 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6928 TSTORM_ID, 0, IGU_INT_NOP, 1); 6929 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6930 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6931 } else { 6932 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6933 USTORM_ID, 0, IGU_INT_NOP, 1); 6934 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6935 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6936 } 6937 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); 6938 6939 /* !!! these should become driver const once 6940 rf-tool supports split-68 const */ 6941 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 6942 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 6943 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 6944 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 6945 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 6946 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 6947 } 6948 } 6949 6950 /* Reset PCIE errors for debug */ 6951 REG_WR(bp, 0x2114, 0xffffffff); 6952 REG_WR(bp, 0x2120, 0xffffffff); 6953 6954 if (CHIP_IS_E1x(bp)) { 6955 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 6956 main_mem_base = HC_REG_MAIN_MEMORY + 6957 BP_PORT(bp) * (main_mem_size * 4); 6958 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 6959 main_mem_width = 8; 6960 6961 val = REG_RD(bp, main_mem_prty_clr); 6962 if (val) 6963 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC " 6964 "block during " 6965 "function init (0x%x)!\n", val); 6966 6967 /* Clear "false" parity errors in MSI-X table */ 6968 for (i = main_mem_base; 6969 i < main_mem_base + main_mem_size * 4; 6970 i += main_mem_width) { 6971 bnx2x_read_dmae(bp, i, main_mem_width / 4); 6972 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), 6973 i, main_mem_width / 4); 6974 } 6975 /* Clear HC parity attention */ 6976 REG_RD(bp, main_mem_prty_clr); 6977 } 6978 6979#ifdef BNX2X_STOP_ON_ERROR 6980 /* Enable STORMs SP logging */ 6981 REG_WR8(bp, BAR_USTRORM_INTMEM + 6982 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6983 REG_WR8(bp, BAR_TSTRORM_INTMEM + 6984 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6985 REG_WR8(bp, BAR_CSTRORM_INTMEM + 6986 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6987 REG_WR8(bp, BAR_XSTRORM_INTMEM + 6988 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6989#endif 6990 6991 bnx2x_phy_probe(&bp->link_params); 6992 6993 return 0; 6994} 6995 6996 6997void bnx2x_free_mem(struct bnx2x *bp) 6998{ 6999 /* fastpath */ 7000 bnx2x_free_fp_mem(bp); 7001 /* end of fastpath */ 7002 7003 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 7004 sizeof(struct host_sp_status_block)); 7005 7006 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 7007 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7008 7009 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 7010 sizeof(struct bnx2x_slowpath)); 7011 7012 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping, 7013 bp->context.size); 7014 7015 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); 7016 7017 BNX2X_FREE(bp->ilt->lines); 7018 7019#ifdef BCM_CNIC 7020 if (!CHIP_IS_E1x(bp)) 7021 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, 7022 sizeof(struct host_hc_status_block_e2)); 7023 else 7024 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, 7025 sizeof(struct host_hc_status_block_e1x)); 7026 7027 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 7028#endif 7029 7030 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 7031 7032 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, 7033 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7034} 7035 7036static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) 7037{ 7038 int num_groups; 7039 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1; 7040 7041 /* number of queues for statistics is number of eth queues + FCoE */ 7042 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats; 7043 7044 /* Total number of FW statistics requests = 7045 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats + 7046 * num of queues 7047 */ 7048 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats; 7049 7050 7051 /* Request is built from stats_query_header and an array of 7052 * stats_query_cmd_group each of which contains 7053 * STATS_QUERY_CMD_COUNT rules. The real number or requests is 7054 * configured in the stats_query_header. 7055 */ 7056 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) + 7057 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0); 7058 7059 bp->fw_stats_req_sz = sizeof(struct stats_query_header) + 7060 num_groups * sizeof(struct stats_query_cmd_group); 7061 7062 /* Data for statistics requests + stats_conter 7063 * 7064 * stats_counter holds per-STORM counters that are incremented 7065 * when STORM has finished with the current request. 7066 * 7067 * memory for FCoE offloaded statistics are counted anyway, 7068 * even if they will not be sent. 7069 */ 7070 bp->fw_stats_data_sz = sizeof(struct per_port_stats) + 7071 sizeof(struct per_pf_stats) + 7072 sizeof(struct fcoe_statistics_params) + 7073 sizeof(struct per_queue_stats) * num_queue_stats + 7074 sizeof(struct stats_counter); 7075 7076 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, 7077 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7078 7079 /* Set shortcuts */ 7080 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; 7081 bp->fw_stats_req_mapping = bp->fw_stats_mapping; 7082 7083 bp->fw_stats_data = (struct bnx2x_fw_stats_data *) 7084 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); 7085 7086 bp->fw_stats_data_mapping = bp->fw_stats_mapping + 7087 bp->fw_stats_req_sz; 7088 return 0; 7089 7090alloc_mem_err: 7091 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 7092 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7093 return -ENOMEM; 7094} 7095 7096 7097int bnx2x_alloc_mem(struct bnx2x *bp) 7098{ 7099#ifdef BCM_CNIC 7100 if (!CHIP_IS_E1x(bp)) 7101 /* size = the status block + ramrod buffers */ 7102 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, 7103 sizeof(struct host_hc_status_block_e2)); 7104 else 7105 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, 7106 sizeof(struct host_hc_status_block_e1x)); 7107 7108 /* allocate searcher T2 table */ 7109 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); 7110#endif 7111 7112 7113 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, 7114 sizeof(struct host_sp_status_block)); 7115 7116 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, 7117 sizeof(struct bnx2x_slowpath)); 7118 7119 /* Allocated memory for FW statistics */ 7120 if (bnx2x_alloc_fw_stats_mem(bp)) 7121 goto alloc_mem_err; 7122 7123 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); 7124 7125 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping, 7126 bp->context.size); 7127 7128 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); 7129 7130 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) 7131 goto alloc_mem_err; 7132 7133 /* Slow path ring */ 7134 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); 7135 7136 /* EQ */ 7137 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, 7138 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7139 7140 7141 /* fastpath */ 7142 /* need to be done at the end, since it's self adjusting to amount 7143 * of memory available for RSS queues 7144 */ 7145 if (bnx2x_alloc_fp_mem(bp)) 7146 goto alloc_mem_err; 7147 return 0; 7148 7149alloc_mem_err: 7150 bnx2x_free_mem(bp); 7151 return -ENOMEM; 7152} 7153 7154/* 7155 * Init service functions 7156 */ 7157 7158int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 7159 struct bnx2x_vlan_mac_obj *obj, bool set, 7160 int mac_type, unsigned long *ramrod_flags) 7161{ 7162 int rc; 7163 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 7164 7165 memset(&ramrod_param, 0, sizeof(ramrod_param)); 7166 7167 /* Fill general parameters */ 7168 ramrod_param.vlan_mac_obj = obj; 7169 ramrod_param.ramrod_flags = *ramrod_flags; 7170 7171 /* Fill a user request section if needed */ 7172 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 7173 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 7174 7175 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 7176 7177 /* Set the command: ADD or DEL */ 7178 if (set) 7179 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 7180 else 7181 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 7182 } 7183 7184 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 7185 if (rc < 0) 7186 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); 7187 return rc; 7188} 7189 7190int bnx2x_del_all_macs(struct bnx2x *bp, 7191 struct bnx2x_vlan_mac_obj *mac_obj, 7192 int mac_type, bool wait_for_comp) 7193{ 7194 int rc; 7195 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 7196 7197 /* Wait for completion of requested */ 7198 if (wait_for_comp) 7199 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7200 7201 /* Set the mac type of addresses we want to clear */ 7202 __set_bit(mac_type, &vlan_mac_flags); 7203 7204 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); 7205 if (rc < 0) 7206 BNX2X_ERR("Failed to delete MACs: %d\n", rc); 7207 7208 return rc; 7209} 7210 7211int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) 7212{ 7213 unsigned long ramrod_flags = 0; 7214 7215#ifdef BCM_CNIC 7216 if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_ISCSI_SD(bp)) { 7217 DP(NETIF_MSG_IFUP, "Ignoring Zero MAC for iSCSI SD mode\n"); 7218 return 0; 7219 } 7220#endif 7221 7222 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); 7223 7224 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7225 /* Eth MAC is set on RSS leading client (fp[0]) */ 7226 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set, 7227 BNX2X_ETH_MAC, &ramrod_flags); 7228} 7229 7230int bnx2x_setup_leading(struct bnx2x *bp) 7231{ 7232 return bnx2x_setup_queue(bp, &bp->fp[0], 1); 7233} 7234 7235/** 7236 * bnx2x_set_int_mode - configure interrupt mode 7237 * 7238 * @bp: driver handle 7239 * 7240 * In case of MSI-X it will also try to enable MSI-X. 7241 */ 7242static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) 7243{ 7244 switch (int_mode) { 7245 case INT_MODE_MSI: 7246 bnx2x_enable_msi(bp); 7247 /* falling through... */ 7248 case INT_MODE_INTx: 7249 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7250 DP(NETIF_MSG_IFUP, "set number of queues to 1\n"); 7251 break; 7252 default: 7253 /* Set number of queues according to bp->multi_mode value */ 7254 bnx2x_set_num_queues(bp); 7255 7256 DP(NETIF_MSG_IFUP, "set number of queues to %d\n", 7257 bp->num_queues); 7258 7259 /* if we can't use MSI-X we only need one fp, 7260 * so try to enable MSI-X with the requested number of fp's 7261 * and fallback to MSI or legacy INTx with one fp 7262 */ 7263 if (bnx2x_enable_msix(bp)) { 7264 /* failed to enable MSI-X */ 7265 if (bp->multi_mode) 7266 DP(NETIF_MSG_IFUP, 7267 "Multi requested but failed to " 7268 "enable MSI-X (%d), " 7269 "set number of queues to %d\n", 7270 bp->num_queues, 7271 1 + NON_ETH_CONTEXT_USE); 7272 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7273 7274 /* Try to enable MSI */ 7275 if (!(bp->flags & DISABLE_MSI_FLAG)) 7276 bnx2x_enable_msi(bp); 7277 } 7278 break; 7279 } 7280} 7281 7282/* must be called prioir to any HW initializations */ 7283static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) 7284{ 7285 return L2_ILT_LINES(bp); 7286} 7287 7288void bnx2x_ilt_set_info(struct bnx2x *bp) 7289{ 7290 struct ilt_client_info *ilt_client; 7291 struct bnx2x_ilt *ilt = BP_ILT(bp); 7292 u16 line = 0; 7293 7294 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); 7295 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); 7296 7297 /* CDU */ 7298 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 7299 ilt_client->client_num = ILT_CLIENT_CDU; 7300 ilt_client->page_size = CDU_ILT_PAGE_SZ; 7301 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 7302 ilt_client->start = line; 7303 line += bnx2x_cid_ilt_lines(bp); 7304#ifdef BCM_CNIC 7305 line += CNIC_ILT_LINES; 7306#endif 7307 ilt_client->end = line - 1; 7308 7309 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, " 7310 "flags 0x%x, hw psz %d\n", 7311 ilt_client->start, 7312 ilt_client->end, 7313 ilt_client->page_size, 7314 ilt_client->flags, 7315 ilog2(ilt_client->page_size >> 12)); 7316 7317 /* QM */ 7318 if (QM_INIT(bp->qm_cid_count)) { 7319 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 7320 ilt_client->client_num = ILT_CLIENT_QM; 7321 ilt_client->page_size = QM_ILT_PAGE_SZ; 7322 ilt_client->flags = 0; 7323 ilt_client->start = line; 7324 7325 /* 4 bytes for each cid */ 7326 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 7327 QM_ILT_PAGE_SZ); 7328 7329 ilt_client->end = line - 1; 7330 7331 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, " 7332 "flags 0x%x, hw psz %d\n", 7333 ilt_client->start, 7334 ilt_client->end, 7335 ilt_client->page_size, 7336 ilt_client->flags, 7337 ilog2(ilt_client->page_size >> 12)); 7338 7339 } 7340 /* SRC */ 7341 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 7342#ifdef BCM_CNIC 7343 ilt_client->client_num = ILT_CLIENT_SRC; 7344 ilt_client->page_size = SRC_ILT_PAGE_SZ; 7345 ilt_client->flags = 0; 7346 ilt_client->start = line; 7347 line += SRC_ILT_LINES; 7348 ilt_client->end = line - 1; 7349 7350 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, " 7351 "flags 0x%x, hw psz %d\n", 7352 ilt_client->start, 7353 ilt_client->end, 7354 ilt_client->page_size, 7355 ilt_client->flags, 7356 ilog2(ilt_client->page_size >> 12)); 7357 7358#else 7359 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7360#endif 7361 7362 /* TM */ 7363 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 7364#ifdef BCM_CNIC 7365 ilt_client->client_num = ILT_CLIENT_TM; 7366 ilt_client->page_size = TM_ILT_PAGE_SZ; 7367 ilt_client->flags = 0; 7368 ilt_client->start = line; 7369 line += TM_ILT_LINES; 7370 ilt_client->end = line - 1; 7371 7372 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, " 7373 "flags 0x%x, hw psz %d\n", 7374 ilt_client->start, 7375 ilt_client->end, 7376 ilt_client->page_size, 7377 ilt_client->flags, 7378 ilog2(ilt_client->page_size >> 12)); 7379 7380#else 7381 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7382#endif 7383 BUG_ON(line > ILT_MAX_LINES); 7384} 7385 7386/** 7387 * bnx2x_pf_q_prep_init - prepare INIT transition parameters 7388 * 7389 * @bp: driver handle 7390 * @fp: pointer to fastpath 7391 * @init_params: pointer to parameters structure 7392 * 7393 * parameters configured: 7394 * - HC configuration 7395 * - Queue's CDU context 7396 */ 7397static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp, 7398 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) 7399{ 7400 7401 u8 cos; 7402 /* FCoE Queue uses Default SB, thus has no HC capabilities */ 7403 if (!IS_FCOE_FP(fp)) { 7404 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); 7405 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); 7406 7407 /* If HC is supporterd, enable host coalescing in the transition 7408 * to INIT state. 7409 */ 7410 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); 7411 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); 7412 7413 /* HC rate */ 7414 init_params->rx.hc_rate = bp->rx_ticks ? 7415 (1000000 / bp->rx_ticks) : 0; 7416 init_params->tx.hc_rate = bp->tx_ticks ? 7417 (1000000 / bp->tx_ticks) : 0; 7418 7419 /* FW SB ID */ 7420 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = 7421 fp->fw_sb_id; 7422 7423 /* 7424 * CQ index among the SB indices: FCoE clients uses the default 7425 * SB, therefore it's different. 7426 */ 7427 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 7428 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 7429 } 7430 7431 /* set maximum number of COSs supported by this queue */ 7432 init_params->max_cos = fp->max_cos; 7433 7434 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n", 7435 fp->index, init_params->max_cos); 7436 7437 /* set the context pointers queue object */ 7438 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) 7439 init_params->cxts[cos] = 7440 &bp->context.vcxt[fp->txdata[cos].cid].eth; 7441} 7442 7443int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7444 struct bnx2x_queue_state_params *q_params, 7445 struct bnx2x_queue_setup_tx_only_params *tx_only_params, 7446 int tx_index, bool leading) 7447{ 7448 memset(tx_only_params, 0, sizeof(*tx_only_params)); 7449 7450 /* Set the command */ 7451 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 7452 7453 /* Set tx-only QUEUE flags: don't zero statistics */ 7454 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); 7455 7456 /* choose the index of the cid to send the slow path on */ 7457 tx_only_params->cid_index = tx_index; 7458 7459 /* Set general TX_ONLY_SETUP parameters */ 7460 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); 7461 7462 /* Set Tx TX_ONLY_SETUP parameters */ 7463 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 7464 7465 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:" 7466 "cos %d, primary cid %d, cid %d, " 7467 "client id %d, sp-client id %d, flags %lx\n", 7468 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 7469 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 7470 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 7471 7472 /* send the ramrod */ 7473 return bnx2x_queue_state_change(bp, q_params); 7474} 7475 7476 7477/** 7478 * bnx2x_setup_queue - setup queue 7479 * 7480 * @bp: driver handle 7481 * @fp: pointer to fastpath 7482 * @leading: is leading 7483 * 7484 * This function performs 2 steps in a Queue state machine 7485 * actually: 1) RESET->INIT 2) INIT->SETUP 7486 */ 7487 7488int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7489 bool leading) 7490{ 7491 struct bnx2x_queue_state_params q_params = {0}; 7492 struct bnx2x_queue_setup_params *setup_params = 7493 &q_params.params.setup; 7494 struct bnx2x_queue_setup_tx_only_params *tx_only_params = 7495 &q_params.params.tx_only; 7496 int rc; 7497 u8 tx_index; 7498 7499 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index); 7500 7501 /* reset IGU state skip FCoE L2 queue */ 7502 if (!IS_FCOE_FP(fp)) 7503 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, 7504 IGU_INT_ENABLE, 0); 7505 7506 q_params.q_obj = &fp->q_obj; 7507 /* We want to wait for completion in this context */ 7508 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7509 7510 /* Prepare the INIT parameters */ 7511 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); 7512 7513 /* Set the command */ 7514 q_params.cmd = BNX2X_Q_CMD_INIT; 7515 7516 /* Change the state to INIT */ 7517 rc = bnx2x_queue_state_change(bp, &q_params); 7518 if (rc) { 7519 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); 7520 return rc; 7521 } 7522 7523 DP(BNX2X_MSG_SP, "init complete\n"); 7524 7525 7526 /* Now move the Queue to the SETUP state... */ 7527 memset(setup_params, 0, sizeof(*setup_params)); 7528 7529 /* Set QUEUE flags */ 7530 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); 7531 7532 /* Set general SETUP parameters */ 7533 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, 7534 FIRST_TX_COS_INDEX); 7535 7536 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, 7537 &setup_params->rxq_params); 7538 7539 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, 7540 FIRST_TX_COS_INDEX); 7541 7542 /* Set the command */ 7543 q_params.cmd = BNX2X_Q_CMD_SETUP; 7544 7545 /* Change the state to SETUP */ 7546 rc = bnx2x_queue_state_change(bp, &q_params); 7547 if (rc) { 7548 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); 7549 return rc; 7550 } 7551 7552 /* loop through the relevant tx-only indices */ 7553 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7554 tx_index < fp->max_cos; 7555 tx_index++) { 7556 7557 /* prepare and send tx-only ramrod*/ 7558 rc = bnx2x_setup_tx_only(bp, fp, &q_params, 7559 tx_only_params, tx_index, leading); 7560 if (rc) { 7561 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", 7562 fp->index, tx_index); 7563 return rc; 7564 } 7565 } 7566 7567 return rc; 7568} 7569 7570static int bnx2x_stop_queue(struct bnx2x *bp, int index) 7571{ 7572 struct bnx2x_fastpath *fp = &bp->fp[index]; 7573 struct bnx2x_fp_txdata *txdata; 7574 struct bnx2x_queue_state_params q_params = {0}; 7575 int rc, tx_index; 7576 7577 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid); 7578 7579 q_params.q_obj = &fp->q_obj; 7580 /* We want to wait for completion in this context */ 7581 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7582 7583 7584 /* close tx-only connections */ 7585 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7586 tx_index < fp->max_cos; 7587 tx_index++){ 7588 7589 /* ascertain this is a normal queue*/ 7590 txdata = &fp->txdata[tx_index]; 7591 7592 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n", 7593 txdata->txq_index); 7594 7595 /* send halt terminate on tx-only connection */ 7596 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7597 memset(&q_params.params.terminate, 0, 7598 sizeof(q_params.params.terminate)); 7599 q_params.params.terminate.cid_index = tx_index; 7600 7601 rc = bnx2x_queue_state_change(bp, &q_params); 7602 if (rc) 7603 return rc; 7604 7605 /* send halt terminate on tx-only connection */ 7606 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7607 memset(&q_params.params.cfc_del, 0, 7608 sizeof(q_params.params.cfc_del)); 7609 q_params.params.cfc_del.cid_index = tx_index; 7610 rc = bnx2x_queue_state_change(bp, &q_params); 7611 if (rc) 7612 return rc; 7613 } 7614 /* Stop the primary connection: */ 7615 /* ...halt the connection */ 7616 q_params.cmd = BNX2X_Q_CMD_HALT; 7617 rc = bnx2x_queue_state_change(bp, &q_params); 7618 if (rc) 7619 return rc; 7620 7621 /* ...terminate the connection */ 7622 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7623 memset(&q_params.params.terminate, 0, 7624 sizeof(q_params.params.terminate)); 7625 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 7626 rc = bnx2x_queue_state_change(bp, &q_params); 7627 if (rc) 7628 return rc; 7629 /* ...delete cfc entry */ 7630 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7631 memset(&q_params.params.cfc_del, 0, 7632 sizeof(q_params.params.cfc_del)); 7633 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 7634 return bnx2x_queue_state_change(bp, &q_params); 7635} 7636 7637 7638static void bnx2x_reset_func(struct bnx2x *bp) 7639{ 7640 int port = BP_PORT(bp); 7641 int func = BP_FUNC(bp); 7642 int i; 7643 7644 /* Disable the function in the FW */ 7645 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 7646 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 7647 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 7648 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 7649 7650 /* FP SBs */ 7651 for_each_eth_queue(bp, i) { 7652 struct bnx2x_fastpath *fp = &bp->fp[i]; 7653 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7654 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 7655 SB_DISABLED); 7656 } 7657 7658#ifdef BCM_CNIC 7659 /* CNIC SB */ 7660 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7661 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), 7662 SB_DISABLED); 7663#endif 7664 /* SP SB */ 7665 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7666 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 7667 SB_DISABLED); 7668 7669 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) 7670 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 7671 0); 7672 7673 /* Configure IGU */ 7674 if (bp->common.int_block == INT_BLOCK_HC) { 7675 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7676 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7677 } else { 7678 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 7679 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 7680 } 7681 7682#ifdef BCM_CNIC 7683 /* Disable Timer scan */ 7684 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 7685 /* 7686 * Wait for at least 10ms and up to 2 second for the timers scan to 7687 * complete 7688 */ 7689 for (i = 0; i < 200; i++) { 7690 msleep(10); 7691 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) 7692 break; 7693 } 7694#endif 7695 /* Clear ILT */ 7696 bnx2x_clear_func_ilt(bp, func); 7697 7698 /* Timers workaround bug for E2: if this is vnic-3, 7699 * we need to set the entire ilt range for this timers. 7700 */ 7701 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { 7702 struct ilt_client_info ilt_cli; 7703 /* use dummy TM client */ 7704 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 7705 ilt_cli.start = 0; 7706 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 7707 ilt_cli.client_num = ILT_CLIENT_TM; 7708 7709 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); 7710 } 7711 7712 /* this assumes that reset_port() called before reset_func()*/ 7713 if (!CHIP_IS_E1x(bp)) 7714 bnx2x_pf_disable(bp); 7715 7716 bp->dmae_ready = 0; 7717} 7718 7719static void bnx2x_reset_port(struct bnx2x *bp) 7720{ 7721 int port = BP_PORT(bp); 7722 u32 val; 7723 7724 /* Reset physical Link */ 7725 bnx2x__link_reset(bp); 7726 7727 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 7728 7729 /* Do not rcv packets to BRB */ 7730 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 7731 /* Do not direct rcv packets that are not for MCP to the BRB */ 7732 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 7733 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 7734 7735 /* Configure AEU */ 7736 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 7737 7738 msleep(100); 7739 /* Check for BRB port occupancy */ 7740 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 7741 if (val) 7742 DP(NETIF_MSG_IFDOWN, 7743 "BRB1 is not empty %d blocks are occupied\n", val); 7744 7745 /* TODO: Close Doorbell port? */ 7746} 7747 7748static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) 7749{ 7750 struct bnx2x_func_state_params func_params = {0}; 7751 7752 /* Prepare parameters for function state transitions */ 7753 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7754 7755 func_params.f_obj = &bp->func_obj; 7756 func_params.cmd = BNX2X_F_CMD_HW_RESET; 7757 7758 func_params.params.hw_init.load_phase = load_code; 7759 7760 return bnx2x_func_state_change(bp, &func_params); 7761} 7762 7763static inline int bnx2x_func_stop(struct bnx2x *bp) 7764{ 7765 struct bnx2x_func_state_params func_params = {0}; 7766 int rc; 7767 7768 /* Prepare parameters for function state transitions */ 7769 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7770 func_params.f_obj = &bp->func_obj; 7771 func_params.cmd = BNX2X_F_CMD_STOP; 7772 7773 /* 7774 * Try to stop the function the 'good way'. If fails (in case 7775 * of a parity error during bnx2x_chip_cleanup()) and we are 7776 * not in a debug mode, perform a state transaction in order to 7777 * enable further HW_RESET transaction. 7778 */ 7779 rc = bnx2x_func_state_change(bp, &func_params); 7780 if (rc) { 7781#ifdef BNX2X_STOP_ON_ERROR 7782 return rc; 7783#else 7784 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry " 7785 "transaction\n"); 7786 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 7787 return bnx2x_func_state_change(bp, &func_params); 7788#endif 7789 } 7790 7791 return 0; 7792} 7793 7794/** 7795 * bnx2x_send_unload_req - request unload mode from the MCP. 7796 * 7797 * @bp: driver handle 7798 * @unload_mode: requested function's unload mode 7799 * 7800 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 7801 */ 7802u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 7803{ 7804 u32 reset_code = 0; 7805 int port = BP_PORT(bp); 7806 7807 /* Select the UNLOAD request mode */ 7808 if (unload_mode == UNLOAD_NORMAL) 7809 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7810 7811 else if (bp->flags & NO_WOL_FLAG) 7812 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 7813 7814 else if (bp->wol) { 7815 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 7816 u8 *mac_addr = bp->dev->dev_addr; 7817 u32 val; 7818 u16 pmc; 7819 7820 /* The mac address is written to entries 1-4 to 7821 * preserve entry 0 which is used by the PMF 7822 */ 7823 u8 entry = (BP_VN(bp) + 1)*8; 7824 7825 val = (mac_addr[0] << 8) | mac_addr[1]; 7826 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 7827 7828 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 7829 (mac_addr[4] << 8) | mac_addr[5]; 7830 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 7831 7832 /* Enable the PME and clear the status */ 7833 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); 7834 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; 7835 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); 7836 7837 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 7838 7839 } else 7840 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7841 7842 /* Send the request to the MCP */ 7843 if (!BP_NOMCP(bp)) 7844 reset_code = bnx2x_fw_command(bp, reset_code, 0); 7845 else { 7846 int path = BP_PATH(bp); 7847 7848 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] " 7849 "%d, %d, %d\n", 7850 path, load_count[path][0], load_count[path][1], 7851 load_count[path][2]); 7852 load_count[path][0]--; 7853 load_count[path][1 + port]--; 7854 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] " 7855 "%d, %d, %d\n", 7856 path, load_count[path][0], load_count[path][1], 7857 load_count[path][2]); 7858 if (load_count[path][0] == 0) 7859 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 7860 else if (load_count[path][1 + port] == 0) 7861 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 7862 else 7863 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 7864 } 7865 7866 return reset_code; 7867} 7868 7869/** 7870 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 7871 * 7872 * @bp: driver handle 7873 */ 7874void bnx2x_send_unload_done(struct bnx2x *bp) 7875{ 7876 /* Report UNLOAD_DONE to MCP */ 7877 if (!BP_NOMCP(bp)) 7878 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 7879} 7880 7881static inline int bnx2x_func_wait_started(struct bnx2x *bp) 7882{ 7883 int tout = 50; 7884 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 7885 7886 if (!bp->port.pmf) 7887 return 0; 7888 7889 /* 7890 * (assumption: No Attention from MCP at this stage) 7891 * PMF probably in the middle of TXdisable/enable transaction 7892 * 1. Sync IRS for default SB 7893 * 2. Sync SP queue - this guarantes us that attention handling started 7894 * 3. Wait, that TXdisable/enable transaction completes 7895 * 7896 * 1+2 guranty that if DCBx attention was scheduled it already changed 7897 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy 7898 * received complettion for the transaction the state is TX_STOPPED. 7899 * State will return to STARTED after completion of TX_STOPPED-->STARTED 7900 * transaction. 7901 */ 7902 7903 /* make sure default SB ISR is done */ 7904 if (msix) 7905 synchronize_irq(bp->msix_table[0].vector); 7906 else 7907 synchronize_irq(bp->pdev->irq); 7908 7909 flush_workqueue(bnx2x_wq); 7910 7911 while (bnx2x_func_get_state(bp, &bp->func_obj) != 7912 BNX2X_F_STATE_STARTED && tout--) 7913 msleep(20); 7914 7915 if (bnx2x_func_get_state(bp, &bp->func_obj) != 7916 BNX2X_F_STATE_STARTED) { 7917#ifdef BNX2X_STOP_ON_ERROR 7918 return -EBUSY; 7919#else 7920 /* 7921 * Failed to complete the transaction in a "good way" 7922 * Force both transactions with CLR bit 7923 */ 7924 struct bnx2x_func_state_params func_params = {0}; 7925 7926 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! " 7927 "Forcing STARTED-->TX_ST0PPED-->STARTED\n"); 7928 7929 func_params.f_obj = &bp->func_obj; 7930 __set_bit(RAMROD_DRV_CLR_ONLY, 7931 &func_params.ramrod_flags); 7932 7933 /* STARTED-->TX_ST0PPED */ 7934 func_params.cmd = BNX2X_F_CMD_TX_STOP; 7935 bnx2x_func_state_change(bp, &func_params); 7936 7937 /* TX_ST0PPED-->STARTED */ 7938 func_params.cmd = BNX2X_F_CMD_TX_START; 7939 return bnx2x_func_state_change(bp, &func_params); 7940#endif 7941 } 7942 7943 return 0; 7944} 7945 7946void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) 7947{ 7948 int port = BP_PORT(bp); 7949 int i, rc = 0; 7950 u8 cos; 7951 struct bnx2x_mcast_ramrod_params rparam = {0}; 7952 u32 reset_code; 7953 7954 /* Wait until tx fastpath tasks complete */ 7955 for_each_tx_queue(bp, i) { 7956 struct bnx2x_fastpath *fp = &bp->fp[i]; 7957 7958 for_each_cos_in_tx_queue(fp, cos) 7959 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]); 7960#ifdef BNX2X_STOP_ON_ERROR 7961 if (rc) 7962 return; 7963#endif 7964 } 7965 7966 /* Give HW time to discard old tx messages */ 7967 usleep_range(1000, 1000); 7968 7969 /* Clean all ETH MACs */ 7970 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false); 7971 if (rc < 0) 7972 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); 7973 7974 /* Clean up UC list */ 7975 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, 7976 true); 7977 if (rc < 0) 7978 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: " 7979 "%d\n", rc); 7980 7981 /* Disable LLH */ 7982 if (!CHIP_IS_E1(bp)) 7983 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 7984 7985 /* Set "drop all" (stop Rx). 7986 * We need to take a netif_addr_lock() here in order to prevent 7987 * a race between the completion code and this code. 7988 */ 7989 netif_addr_lock_bh(bp->dev); 7990 /* Schedule the rx_mode command */ 7991 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 7992 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 7993 else 7994 bnx2x_set_storm_rx_mode(bp); 7995 7996 /* Cleanup multicast configuration */ 7997 rparam.mcast_obj = &bp->mcast_obj; 7998 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 7999 if (rc < 0) 8000 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); 8001 8002 netif_addr_unlock_bh(bp->dev); 8003 8004 8005 8006 /* 8007 * Send the UNLOAD_REQUEST to the MCP. This will return if 8008 * this function should perform FUNC, PORT or COMMON HW 8009 * reset. 8010 */ 8011 reset_code = bnx2x_send_unload_req(bp, unload_mode); 8012 8013 /* 8014 * (assumption: No Attention from MCP at this stage) 8015 * PMF probably in the middle of TXdisable/enable transaction 8016 */ 8017 rc = bnx2x_func_wait_started(bp); 8018 if (rc) { 8019 BNX2X_ERR("bnx2x_func_wait_started failed\n"); 8020#ifdef BNX2X_STOP_ON_ERROR 8021 return; 8022#endif 8023 } 8024 8025 /* Close multi and leading connections 8026 * Completions for ramrods are collected in a synchronous way 8027 */ 8028 for_each_queue(bp, i) 8029 if (bnx2x_stop_queue(bp, i)) 8030#ifdef BNX2X_STOP_ON_ERROR 8031 return; 8032#else 8033 goto unload_error; 8034#endif 8035 /* If SP settings didn't get completed so far - something 8036 * very wrong has happen. 8037 */ 8038 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) 8039 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); 8040 8041#ifndef BNX2X_STOP_ON_ERROR 8042unload_error: 8043#endif 8044 rc = bnx2x_func_stop(bp); 8045 if (rc) { 8046 BNX2X_ERR("Function stop failed!\n"); 8047#ifdef BNX2X_STOP_ON_ERROR 8048 return; 8049#endif 8050 } 8051 8052 /* Disable HW interrupts, NAPI */ 8053 bnx2x_netif_stop(bp, 1); 8054 8055 /* Release IRQs */ 8056 bnx2x_free_irq(bp); 8057 8058 /* Reset the chip */ 8059 rc = bnx2x_reset_hw(bp, reset_code); 8060 if (rc) 8061 BNX2X_ERR("HW_RESET failed\n"); 8062 8063 8064 /* Report UNLOAD_DONE to MCP */ 8065 bnx2x_send_unload_done(bp); 8066} 8067 8068void bnx2x_disable_close_the_gate(struct bnx2x *bp) 8069{ 8070 u32 val; 8071 8072 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n"); 8073 8074 if (CHIP_IS_E1(bp)) { 8075 int port = BP_PORT(bp); 8076 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8077 MISC_REG_AEU_MASK_ATTN_FUNC_0; 8078 8079 val = REG_RD(bp, addr); 8080 val &= ~(0x300); 8081 REG_WR(bp, addr, val); 8082 } else { 8083 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); 8084 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 8085 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 8086 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); 8087 } 8088} 8089 8090/* Close gates #2, #3 and #4: */ 8091static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 8092{ 8093 u32 val; 8094 8095 /* Gates #2 and #4a are closed/opened for "not E1" only */ 8096 if (!CHIP_IS_E1(bp)) { 8097 /* #4 */ 8098 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 8099 /* #2 */ 8100 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 8101 } 8102 8103 /* #3 */ 8104 if (CHIP_IS_E1x(bp)) { 8105 /* Prevent interrupts from HC on both ports */ 8106 val = REG_RD(bp, HC_REG_CONFIG_1); 8107 REG_WR(bp, HC_REG_CONFIG_1, 8108 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 8109 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 8110 8111 val = REG_RD(bp, HC_REG_CONFIG_0); 8112 REG_WR(bp, HC_REG_CONFIG_0, 8113 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 8114 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 8115 } else { 8116 /* Prevent incomming interrupts in IGU */ 8117 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 8118 8119 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, 8120 (!close) ? 8121 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 8122 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 8123 } 8124 8125 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n", 8126 close ? "closing" : "opening"); 8127 mmiowb(); 8128} 8129 8130#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ 8131 8132static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) 8133{ 8134 /* Do some magic... */ 8135 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8136 *magic_val = val & SHARED_MF_CLP_MAGIC; 8137 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 8138} 8139 8140/** 8141 * bnx2x_clp_reset_done - restore the value of the `magic' bit. 8142 * 8143 * @bp: driver handle 8144 * @magic_val: old value of the `magic' bit. 8145 */ 8146static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 8147{ 8148 /* Restore the `magic' bit value... */ 8149 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8150 MF_CFG_WR(bp, shared_mf_config.clp_mb, 8151 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 8152} 8153 8154/** 8155 * bnx2x_reset_mcp_prep - prepare for MCP reset. 8156 * 8157 * @bp: driver handle 8158 * @magic_val: old value of 'magic' bit. 8159 * 8160 * Takes care of CLP configurations. 8161 */ 8162static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 8163{ 8164 u32 shmem; 8165 u32 validity_offset; 8166 8167 DP(NETIF_MSG_HW, "Starting\n"); 8168 8169 /* Set `magic' bit in order to save MF config */ 8170 if (!CHIP_IS_E1(bp)) 8171 bnx2x_clp_reset_prep(bp, magic_val); 8172 8173 /* Get shmem offset */ 8174 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8175 validity_offset = offsetof(struct shmem_region, validity_map[0]); 8176 8177 /* Clear validity map flags */ 8178 if (shmem > 0) 8179 REG_WR(bp, shmem + validity_offset, 0); 8180} 8181 8182#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 8183#define MCP_ONE_TIMEOUT 100 /* 100 ms */ 8184 8185/** 8186 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT 8187 * 8188 * @bp: driver handle 8189 */ 8190static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) 8191{ 8192 /* special handling for emulation and FPGA, 8193 wait 10 times longer */ 8194 if (CHIP_REV_IS_SLOW(bp)) 8195 msleep(MCP_ONE_TIMEOUT*10); 8196 else 8197 msleep(MCP_ONE_TIMEOUT); 8198} 8199 8200/* 8201 * initializes bp->common.shmem_base and waits for validity signature to appear 8202 */ 8203static int bnx2x_init_shmem(struct bnx2x *bp) 8204{ 8205 int cnt = 0; 8206 u32 val = 0; 8207 8208 do { 8209 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8210 if (bp->common.shmem_base) { 8211 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 8212 if (val & SHR_MEM_VALIDITY_MB) 8213 return 0; 8214 } 8215 8216 bnx2x_mcp_wait_one(bp); 8217 8218 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 8219 8220 BNX2X_ERR("BAD MCP validity signature\n"); 8221 8222 return -ENODEV; 8223} 8224 8225static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 8226{ 8227 int rc = bnx2x_init_shmem(bp); 8228 8229 /* Restore the `magic' bit value */ 8230 if (!CHIP_IS_E1(bp)) 8231 bnx2x_clp_reset_done(bp, magic_val); 8232 8233 return rc; 8234} 8235 8236static void bnx2x_pxp_prep(struct bnx2x *bp) 8237{ 8238 if (!CHIP_IS_E1(bp)) { 8239 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 8240 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 8241 mmiowb(); 8242 } 8243} 8244 8245/* 8246 * Reset the whole chip except for: 8247 * - PCIE core 8248 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by 8249 * one reset bit) 8250 * - IGU 8251 * - MISC (including AEU) 8252 * - GRC 8253 * - RBCN, RBCP 8254 */ 8255static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) 8256{ 8257 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 8258 u32 global_bits2, stay_reset2; 8259 8260 /* 8261 * Bits that have to be set in reset_mask2 if we want to reset 'global' 8262 * (per chip) blocks. 8263 */ 8264 global_bits2 = 8265 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 8266 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 8267 8268 /* Don't reset the following blocks */ 8269 not_reset_mask1 = 8270 MISC_REGISTERS_RESET_REG_1_RST_HC | 8271 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 8272 MISC_REGISTERS_RESET_REG_1_RST_PXP; 8273 8274 not_reset_mask2 = 8275 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 8276 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 8277 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 8278 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 8279 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 8280 MISC_REGISTERS_RESET_REG_2_RST_GRC | 8281 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 8282 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 8283 MISC_REGISTERS_RESET_REG_2_RST_ATC | 8284 MISC_REGISTERS_RESET_REG_2_PGLC; 8285 8286 /* 8287 * Keep the following blocks in reset: 8288 * - all xxMACs are handled by the bnx2x_link code. 8289 */ 8290 stay_reset2 = 8291 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 8292 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 8293 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 8294 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 8295 MISC_REGISTERS_RESET_REG_2_UMAC0 | 8296 MISC_REGISTERS_RESET_REG_2_UMAC1 | 8297 MISC_REGISTERS_RESET_REG_2_XMAC | 8298 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 8299 8300 /* Full reset masks according to the chip */ 8301 reset_mask1 = 0xffffffff; 8302 8303 if (CHIP_IS_E1(bp)) 8304 reset_mask2 = 0xffff; 8305 else if (CHIP_IS_E1H(bp)) 8306 reset_mask2 = 0x1ffff; 8307 else if (CHIP_IS_E2(bp)) 8308 reset_mask2 = 0xfffff; 8309 else /* CHIP_IS_E3 */ 8310 reset_mask2 = 0x3ffffff; 8311 8312 /* Don't reset global blocks unless we need to */ 8313 if (!global) 8314 reset_mask2 &= ~global_bits2; 8315 8316 /* 8317 * In case of attention in the QM, we need to reset PXP 8318 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 8319 * because otherwise QM reset would release 'close the gates' shortly 8320 * before resetting the PXP, then the PSWRQ would send a write 8321 * request to PGLUE. Then when PXP is reset, PGLUE would try to 8322 * read the payload data from PSWWR, but PSWWR would not 8323 * respond. The write queue in PGLUE would stuck, dmae commands 8324 * would not return. Therefore it's important to reset the second 8325 * reset register (containing the 8326 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 8327 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 8328 * bit). 8329 */ 8330 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8331 reset_mask2 & (~not_reset_mask2)); 8332 8333 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8334 reset_mask1 & (~not_reset_mask1)); 8335 8336 barrier(); 8337 mmiowb(); 8338 8339 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 8340 reset_mask2 & (~stay_reset2)); 8341 8342 barrier(); 8343 mmiowb(); 8344 8345 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 8346 mmiowb(); 8347} 8348 8349/** 8350 * bnx2x_er_poll_igu_vq - poll for pending writes bit. 8351 * It should get cleared in no more than 1s. 8352 * 8353 * @bp: driver handle 8354 * 8355 * It should get cleared in no more than 1s. Returns 0 if 8356 * pending writes bit gets cleared. 8357 */ 8358static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) 8359{ 8360 u32 cnt = 1000; 8361 u32 pend_bits = 0; 8362 8363 do { 8364 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); 8365 8366 if (pend_bits == 0) 8367 break; 8368 8369 usleep_range(1000, 1000); 8370 } while (cnt-- > 0); 8371 8372 if (cnt <= 0) { 8373 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", 8374 pend_bits); 8375 return -EBUSY; 8376 } 8377 8378 return 0; 8379} 8380 8381static int bnx2x_process_kill(struct bnx2x *bp, bool global) 8382{ 8383 int cnt = 1000; 8384 u32 val = 0; 8385 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 8386 8387 8388 /* Empty the Tetris buffer, wait for 1s */ 8389 do { 8390 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); 8391 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); 8392 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); 8393 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); 8394 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); 8395 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 8396 ((port_is_idle_0 & 0x1) == 0x1) && 8397 ((port_is_idle_1 & 0x1) == 0x1) && 8398 (pgl_exp_rom2 == 0xffffffff)) 8399 break; 8400 usleep_range(1000, 1000); 8401 } while (cnt-- > 0); 8402 8403 if (cnt <= 0) { 8404 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there" 8405 " are still" 8406 " outstanding read requests after 1s!\n"); 8407 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x," 8408 " port_is_idle_0=0x%08x," 8409 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 8410 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 8411 pgl_exp_rom2); 8412 return -EAGAIN; 8413 } 8414 8415 barrier(); 8416 8417 /* Close gates #2, #3 and #4 */ 8418 bnx2x_set_234_gates(bp, true); 8419 8420 /* Poll for IGU VQs for 57712 and newer chips */ 8421 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) 8422 return -EAGAIN; 8423 8424 8425 /* TBD: Indicate that "process kill" is in progress to MCP */ 8426 8427 /* Clear "unprepared" bit */ 8428 REG_WR(bp, MISC_REG_UNPREPARED, 0); 8429 barrier(); 8430 8431 /* Make sure all is written to the chip before the reset */ 8432 mmiowb(); 8433 8434 /* Wait for 1ms to empty GLUE and PCI-E core queues, 8435 * PSWHST, GRC and PSWRD Tetris buffer. 8436 */ 8437 usleep_range(1000, 1000); 8438 8439 /* Prepare to chip reset: */ 8440 /* MCP */ 8441 if (global) 8442 bnx2x_reset_mcp_prep(bp, &val); 8443 8444 /* PXP */ 8445 bnx2x_pxp_prep(bp); 8446 barrier(); 8447 8448 /* reset the chip */ 8449 bnx2x_process_kill_chip_reset(bp, global); 8450 barrier(); 8451 8452 /* Recover after reset: */ 8453 /* MCP */ 8454 if (global && bnx2x_reset_mcp_comp(bp, val)) 8455 return -EAGAIN; 8456 8457 /* TBD: Add resetting the NO_MCP mode DB here */ 8458 8459 /* PXP */ 8460 bnx2x_pxp_prep(bp); 8461 8462 /* Open the gates #2, #3 and #4 */ 8463 bnx2x_set_234_gates(bp, false); 8464 8465 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a 8466 * reset state, re-enable attentions. */ 8467 8468 return 0; 8469} 8470 8471int bnx2x_leader_reset(struct bnx2x *bp) 8472{ 8473 int rc = 0; 8474 bool global = bnx2x_reset_is_global(bp); 8475 8476 /* Try to recover after the failure */ 8477 if (bnx2x_process_kill(bp, global)) { 8478 netdev_err(bp->dev, "Something bad had happen on engine %d! " 8479 "Aii!\n", BP_PATH(bp)); 8480 rc = -EAGAIN; 8481 goto exit_leader_reset; 8482 } 8483 8484 /* 8485 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver 8486 * state. 8487 */ 8488 bnx2x_set_reset_done(bp); 8489 if (global) 8490 bnx2x_clear_reset_global(bp); 8491 8492exit_leader_reset: 8493 bp->is_leader = 0; 8494 bnx2x_release_leader_lock(bp); 8495 smp_mb(); 8496 return rc; 8497} 8498 8499static inline void bnx2x_recovery_failed(struct bnx2x *bp) 8500{ 8501 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); 8502 8503 /* Disconnect this device */ 8504 netif_device_detach(bp->dev); 8505 8506 /* 8507 * Block ifup for all function on this engine until "process kill" 8508 * or power cycle. 8509 */ 8510 bnx2x_set_reset_in_progress(bp); 8511 8512 /* Shut down the power */ 8513 bnx2x_set_power_state(bp, PCI_D3hot); 8514 8515 bp->recovery_state = BNX2X_RECOVERY_FAILED; 8516 8517 smp_mb(); 8518} 8519 8520/* 8521 * Assumption: runs under rtnl lock. This together with the fact 8522 * that it's called only from bnx2x_sp_rtnl() ensure that it 8523 * will never be called when netif_running(bp->dev) is false. 8524 */ 8525static void bnx2x_parity_recover(struct bnx2x *bp) 8526{ 8527 bool global = false; 8528 8529 DP(NETIF_MSG_HW, "Handling parity\n"); 8530 while (1) { 8531 switch (bp->recovery_state) { 8532 case BNX2X_RECOVERY_INIT: 8533 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 8534 bnx2x_chk_parity_attn(bp, &global, false); 8535 8536 /* Try to get a LEADER_LOCK HW lock */ 8537 if (bnx2x_trylock_leader_lock(bp)) { 8538 bnx2x_set_reset_in_progress(bp); 8539 /* 8540 * Check if there is a global attention and if 8541 * there was a global attention, set the global 8542 * reset bit. 8543 */ 8544 8545 if (global) 8546 bnx2x_set_reset_global(bp); 8547 8548 bp->is_leader = 1; 8549 } 8550 8551 /* Stop the driver */ 8552 /* If interface has been removed - break */ 8553 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) 8554 return; 8555 8556 bp->recovery_state = BNX2X_RECOVERY_WAIT; 8557 8558 /* 8559 * Reset MCP command sequence number and MCP mail box 8560 * sequence as we are going to reset the MCP. 8561 */ 8562 if (global) { 8563 bp->fw_seq = 0; 8564 bp->fw_drv_pulse_wr_seq = 0; 8565 } 8566 8567 /* Ensure "is_leader", MCP command sequence and 8568 * "recovery_state" update values are seen on other 8569 * CPUs. 8570 */ 8571 smp_mb(); 8572 break; 8573 8574 case BNX2X_RECOVERY_WAIT: 8575 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 8576 if (bp->is_leader) { 8577 int other_engine = BP_PATH(bp) ? 0 : 1; 8578 u32 other_load_counter = 8579 bnx2x_get_load_cnt(bp, other_engine); 8580 u32 load_counter = 8581 bnx2x_get_load_cnt(bp, BP_PATH(bp)); 8582 global = bnx2x_reset_is_global(bp); 8583 8584 /* 8585 * In case of a parity in a global block, let 8586 * the first leader that performs a 8587 * leader_reset() reset the global blocks in 8588 * order to clear global attentions. Otherwise 8589 * the the gates will remain closed for that 8590 * engine. 8591 */ 8592 if (load_counter || 8593 (global && other_load_counter)) { 8594 /* Wait until all other functions get 8595 * down. 8596 */ 8597 schedule_delayed_work(&bp->sp_rtnl_task, 8598 HZ/10); 8599 return; 8600 } else { 8601 /* If all other functions got down - 8602 * try to bring the chip back to 8603 * normal. In any case it's an exit 8604 * point for a leader. 8605 */ 8606 if (bnx2x_leader_reset(bp)) { 8607 bnx2x_recovery_failed(bp); 8608 return; 8609 } 8610 8611 /* If we are here, means that the 8612 * leader has succeeded and doesn't 8613 * want to be a leader any more. Try 8614 * to continue as a none-leader. 8615 */ 8616 break; 8617 } 8618 } else { /* non-leader */ 8619 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { 8620 /* Try to get a LEADER_LOCK HW lock as 8621 * long as a former leader may have 8622 * been unloaded by the user or 8623 * released a leadership by another 8624 * reason. 8625 */ 8626 if (bnx2x_trylock_leader_lock(bp)) { 8627 /* I'm a leader now! Restart a 8628 * switch case. 8629 */ 8630 bp->is_leader = 1; 8631 break; 8632 } 8633 8634 schedule_delayed_work(&bp->sp_rtnl_task, 8635 HZ/10); 8636 return; 8637 8638 } else { 8639 /* 8640 * If there was a global attention, wait 8641 * for it to be cleared. 8642 */ 8643 if (bnx2x_reset_is_global(bp)) { 8644 schedule_delayed_work( 8645 &bp->sp_rtnl_task, 8646 HZ/10); 8647 return; 8648 } 8649 8650 if (bnx2x_nic_load(bp, LOAD_NORMAL)) 8651 bnx2x_recovery_failed(bp); 8652 else { 8653 bp->recovery_state = 8654 BNX2X_RECOVERY_DONE; 8655 smp_mb(); 8656 } 8657 8658 return; 8659 } 8660 } 8661 default: 8662 return; 8663 } 8664 } 8665} 8666 8667/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is 8668 * scheduled on a general queue in order to prevent a dead lock. 8669 */ 8670static void bnx2x_sp_rtnl_task(struct work_struct *work) 8671{ 8672 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); 8673 8674 rtnl_lock(); 8675 8676 if (!netif_running(bp->dev)) 8677 goto sp_rtnl_exit; 8678 8679 /* if stop on error is defined no recovery flows should be executed */ 8680#ifdef BNX2X_STOP_ON_ERROR 8681 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined " 8682 "so reset not done to allow debug dump,\n" 8683 "you will need to reboot when done\n"); 8684 goto sp_rtnl_not_reset; 8685#endif 8686 8687 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { 8688 /* 8689 * Clear all pending SP commands as we are going to reset the 8690 * function anyway. 8691 */ 8692 bp->sp_rtnl_state = 0; 8693 smp_mb(); 8694 8695 bnx2x_parity_recover(bp); 8696 8697 goto sp_rtnl_exit; 8698 } 8699 8700 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { 8701 /* 8702 * Clear all pending SP commands as we are going to reset the 8703 * function anyway. 8704 */ 8705 bp->sp_rtnl_state = 0; 8706 smp_mb(); 8707 8708 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 8709 bnx2x_nic_load(bp, LOAD_NORMAL); 8710 8711 goto sp_rtnl_exit; 8712 } 8713#ifdef BNX2X_STOP_ON_ERROR 8714sp_rtnl_not_reset: 8715#endif 8716 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) 8717 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); 8718 8719 /* 8720 * in case of fan failure we need to reset id if the "stop on error" 8721 * debug flag is set, since we trying to prevent permanent overheating 8722 * damage 8723 */ 8724 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { 8725 DP(BNX2X_MSG_SP, "fan failure detected. Unloading driver\n"); 8726 netif_device_detach(bp->dev); 8727 bnx2x_close(bp->dev); 8728 } 8729 8730sp_rtnl_exit: 8731 rtnl_unlock(); 8732} 8733 8734/* end of nic load/unload */ 8735 8736static void bnx2x_period_task(struct work_struct *work) 8737{ 8738 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); 8739 8740 if (!netif_running(bp->dev)) 8741 goto period_task_exit; 8742 8743 if (CHIP_REV_IS_SLOW(bp)) { 8744 BNX2X_ERR("period task called on emulation, ignoring\n"); 8745 goto period_task_exit; 8746 } 8747 8748 bnx2x_acquire_phy_lock(bp); 8749 /* 8750 * The barrier is needed to ensure the ordering between the writing to 8751 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and 8752 * the reading here. 8753 */ 8754 smp_mb(); 8755 if (bp->port.pmf) { 8756 bnx2x_period_func(&bp->link_params, &bp->link_vars); 8757 8758 /* Re-queue task in 1 sec */ 8759 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); 8760 } 8761 8762 bnx2x_release_phy_lock(bp); 8763period_task_exit: 8764 return; 8765} 8766 8767/* 8768 * Init service functions 8769 */ 8770 8771static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) 8772{ 8773 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; 8774 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; 8775 return base + (BP_ABS_FUNC(bp)) * stride; 8776} 8777 8778static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) 8779{ 8780 u32 reg = bnx2x_get_pretend_reg(bp); 8781 8782 /* Flush all outstanding writes */ 8783 mmiowb(); 8784 8785 /* Pretend to be function 0 */ 8786 REG_WR(bp, reg, 0); 8787 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ 8788 8789 /* From now we are in the "like-E1" mode */ 8790 bnx2x_int_disable(bp); 8791 8792 /* Flush all outstanding writes */ 8793 mmiowb(); 8794 8795 /* Restore the original function */ 8796 REG_WR(bp, reg, BP_ABS_FUNC(bp)); 8797 REG_RD(bp, reg); 8798} 8799 8800static inline void bnx2x_undi_int_disable(struct bnx2x *bp) 8801{ 8802 if (CHIP_IS_E1(bp)) 8803 bnx2x_int_disable(bp); 8804 else 8805 bnx2x_undi_int_disable_e1h(bp); 8806} 8807 8808static void __devinit bnx2x_undi_unload(struct bnx2x *bp) 8809{ 8810 u32 val; 8811 8812 /* Check if there is any driver already loaded */ 8813 val = REG_RD(bp, MISC_REG_UNPREPARED); 8814 if (val == 0x1) { 8815 8816 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8817 /* 8818 * Check if it is the UNDI driver 8819 * UNDI driver initializes CID offset for normal bell to 0x7 8820 */ 8821 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 8822 if (val == 0x7) { 8823 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8824 /* save our pf_num */ 8825 int orig_pf_num = bp->pf_num; 8826 int port; 8827 u32 swap_en, swap_val, value; 8828 8829 /* clear the UNDI indication */ 8830 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 8831 8832 BNX2X_DEV_INFO("UNDI is active! reset device\n"); 8833 8834 /* try unload UNDI on port 0 */ 8835 bp->pf_num = 0; 8836 bp->fw_seq = 8837 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8838 DRV_MSG_SEQ_NUMBER_MASK); 8839 reset_code = bnx2x_fw_command(bp, reset_code, 0); 8840 8841 /* if UNDI is loaded on the other port */ 8842 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { 8843 8844 /* send "DONE" for previous unload */ 8845 bnx2x_fw_command(bp, 8846 DRV_MSG_CODE_UNLOAD_DONE, 0); 8847 8848 /* unload UNDI on port 1 */ 8849 bp->pf_num = 1; 8850 bp->fw_seq = 8851 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8852 DRV_MSG_SEQ_NUMBER_MASK); 8853 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8854 8855 bnx2x_fw_command(bp, reset_code, 0); 8856 } 8857 8858 bnx2x_undi_int_disable(bp); 8859 port = BP_PORT(bp); 8860 8861 /* close input traffic and wait for it */ 8862 /* Do not rcv packets to BRB */ 8863 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK : 8864 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0); 8865 /* Do not direct rcv packets that are not for MCP to 8866 * the BRB */ 8867 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 8868 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 8869 /* clear AEU */ 8870 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8871 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0); 8872 msleep(10); 8873 8874 /* save NIG port swap info */ 8875 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 8876 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 8877 /* reset device */ 8878 REG_WR(bp, 8879 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8880 0xd3ffffff); 8881 8882 value = 0x1400; 8883 if (CHIP_IS_E3(bp)) { 8884 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 8885 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 8886 } 8887 8888 REG_WR(bp, 8889 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8890 value); 8891 8892 /* take the NIG out of reset and restore swap values */ 8893 REG_WR(bp, 8894 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 8895 MISC_REGISTERS_RESET_REG_1_RST_NIG); 8896 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val); 8897 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en); 8898 8899 /* send unload done to the MCP */ 8900 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 8901 8902 /* restore our func and fw_seq */ 8903 bp->pf_num = orig_pf_num; 8904 bp->fw_seq = 8905 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8906 DRV_MSG_SEQ_NUMBER_MASK); 8907 } 8908 8909 /* now it's safe to release the lock */ 8910 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8911 } 8912} 8913 8914static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) 8915{ 8916 u32 val, val2, val3, val4, id, boot_mode; 8917 u16 pmc; 8918 8919 /* Get the chip revision id and number. */ 8920 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 8921 val = REG_RD(bp, MISC_REG_CHIP_NUM); 8922 id = ((val & 0xffff) << 16); 8923 val = REG_RD(bp, MISC_REG_CHIP_REV); 8924 id |= ((val & 0xf) << 12); 8925 val = REG_RD(bp, MISC_REG_CHIP_METAL); 8926 id |= ((val & 0xff) << 4); 8927 val = REG_RD(bp, MISC_REG_BOND_ID); 8928 id |= (val & 0xf); 8929 bp->common.chip_id = id; 8930 8931 /* Set doorbell size */ 8932 bp->db_size = (1 << BNX2X_DB_SHIFT); 8933 8934 if (!CHIP_IS_E1x(bp)) { 8935 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 8936 if ((val & 1) == 0) 8937 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); 8938 else 8939 val = (val >> 1) & 1; 8940 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : 8941 "2_PORT_MODE"); 8942 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : 8943 CHIP_2_PORT_MODE; 8944 8945 if (CHIP_MODE_IS_4_PORT(bp)) 8946 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ 8947 else 8948 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ 8949 } else { 8950 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ 8951 bp->pfid = bp->pf_num; /* 0..7 */ 8952 } 8953 8954 bp->link_params.chip_id = bp->common.chip_id; 8955 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 8956 8957 val = (REG_RD(bp, 0x2874) & 0x55); 8958 if ((bp->common.chip_id & 0x1) || 8959 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { 8960 bp->flags |= ONE_PORT_FLAG; 8961 BNX2X_DEV_INFO("single port device\n"); 8962 } 8963 8964 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); 8965 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << 8966 (val & MCPR_NVM_CFG4_FLASH_SIZE)); 8967 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 8968 bp->common.flash_size, bp->common.flash_size); 8969 8970 bnx2x_init_shmem(bp); 8971 8972 8973 8974 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? 8975 MISC_REG_GENERIC_CR_1 : 8976 MISC_REG_GENERIC_CR_0)); 8977 8978 bp->link_params.shmem_base = bp->common.shmem_base; 8979 bp->link_params.shmem2_base = bp->common.shmem2_base; 8980 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 8981 bp->common.shmem_base, bp->common.shmem2_base); 8982 8983 if (!bp->common.shmem_base) { 8984 BNX2X_DEV_INFO("MCP not active\n"); 8985 bp->flags |= NO_MCP_FLAG; 8986 return; 8987 } 8988 8989 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 8990 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 8991 8992 bp->link_params.hw_led_mode = ((bp->common.hw_config & 8993 SHARED_HW_CFG_LED_MODE_MASK) >> 8994 SHARED_HW_CFG_LED_MODE_SHIFT); 8995 8996 bp->link_params.feature_config_flags = 0; 8997 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); 8998 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) 8999 bp->link_params.feature_config_flags |= 9000 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 9001 else 9002 bp->link_params.feature_config_flags &= 9003 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 9004 9005 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 9006 bp->common.bc_ver = val; 9007 BNX2X_DEV_INFO("bc_ver %X\n", val); 9008 if (val < BNX2X_BC_VER) { 9009 /* for now only warn 9010 * later we might need to enforce this */ 9011 BNX2X_ERR("This driver needs bc_ver %X but found %X, " 9012 "please upgrade BC\n", BNX2X_BC_VER, val); 9013 } 9014 bp->link_params.feature_config_flags |= 9015 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 9016 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 9017 9018 bp->link_params.feature_config_flags |= 9019 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? 9020 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; 9021 9022 bp->link_params.feature_config_flags |= 9023 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? 9024 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; 9025 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? 9026 BC_SUPPORTS_PFC_STATS : 0; 9027 9028 boot_mode = SHMEM_RD(bp, 9029 dev_info.port_feature_config[BP_PORT(bp)].mba_config) & 9030 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; 9031 switch (boot_mode) { 9032 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: 9033 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; 9034 break; 9035 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: 9036 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; 9037 break; 9038 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: 9039 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; 9040 break; 9041 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: 9042 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; 9043 break; 9044 } 9045 9046 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); 9047 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; 9048 9049 BNX2X_DEV_INFO("%sWoL capable\n", 9050 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 9051 9052 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 9053 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 9054 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); 9055 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); 9056 9057 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", 9058 val, val2, val3, val4); 9059} 9060 9061#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 9062#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 9063 9064static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) 9065{ 9066 int pfid = BP_FUNC(bp); 9067 int igu_sb_id; 9068 u32 val; 9069 u8 fid, igu_sb_cnt = 0; 9070 9071 bp->igu_base_sb = 0xff; 9072 if (CHIP_INT_MODE_IS_BC(bp)) { 9073 int vn = BP_VN(bp); 9074 igu_sb_cnt = bp->igu_sb_cnt; 9075 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 9076 FP_SB_MAX_E1x; 9077 9078 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + 9079 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); 9080 9081 return; 9082 } 9083 9084 /* IGU in normal mode - read CAM */ 9085 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 9086 igu_sb_id++) { 9087 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 9088 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 9089 continue; 9090 fid = IGU_FID(val); 9091 if ((fid & IGU_FID_ENCODE_IS_PF)) { 9092 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) 9093 continue; 9094 if (IGU_VEC(val) == 0) 9095 /* default status block */ 9096 bp->igu_dsb_id = igu_sb_id; 9097 else { 9098 if (bp->igu_base_sb == 0xff) 9099 bp->igu_base_sb = igu_sb_id; 9100 igu_sb_cnt++; 9101 } 9102 } 9103 } 9104 9105#ifdef CONFIG_PCI_MSI 9106 /* 9107 * It's expected that number of CAM entries for this functions is equal 9108 * to the number evaluated based on the MSI-X table size. We want a 9109 * harsh warning if these values are different! 9110 */ 9111 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); 9112#endif 9113 9114 if (igu_sb_cnt == 0) 9115 BNX2X_ERR("CAM configuration error\n"); 9116} 9117 9118static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, 9119 u32 switch_cfg) 9120{ 9121 int cfg_size = 0, idx, port = BP_PORT(bp); 9122 9123 /* Aggregation of supported attributes of all external phys */ 9124 bp->port.supported[0] = 0; 9125 bp->port.supported[1] = 0; 9126 switch (bp->link_params.num_phys) { 9127 case 1: 9128 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; 9129 cfg_size = 1; 9130 break; 9131 case 2: 9132 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; 9133 cfg_size = 1; 9134 break; 9135 case 3: 9136 if (bp->link_params.multi_phy_config & 9137 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 9138 bp->port.supported[1] = 9139 bp->link_params.phy[EXT_PHY1].supported; 9140 bp->port.supported[0] = 9141 bp->link_params.phy[EXT_PHY2].supported; 9142 } else { 9143 bp->port.supported[0] = 9144 bp->link_params.phy[EXT_PHY1].supported; 9145 bp->port.supported[1] = 9146 bp->link_params.phy[EXT_PHY2].supported; 9147 } 9148 cfg_size = 2; 9149 break; 9150 } 9151 9152 if (!(bp->port.supported[0] || bp->port.supported[1])) { 9153 BNX2X_ERR("NVRAM config error. BAD phy config." 9154 "PHY1 config 0x%x, PHY2 config 0x%x\n", 9155 SHMEM_RD(bp, 9156 dev_info.port_hw_config[port].external_phy_config), 9157 SHMEM_RD(bp, 9158 dev_info.port_hw_config[port].external_phy_config2)); 9159 return; 9160 } 9161 9162 if (CHIP_IS_E3(bp)) 9163 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); 9164 else { 9165 switch (switch_cfg) { 9166 case SWITCH_CFG_1G: 9167 bp->port.phy_addr = REG_RD( 9168 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 9169 break; 9170 case SWITCH_CFG_10G: 9171 bp->port.phy_addr = REG_RD( 9172 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 9173 break; 9174 default: 9175 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 9176 bp->port.link_config[0]); 9177 return; 9178 } 9179 } 9180 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 9181 /* mask what we support according to speed_cap_mask per configuration */ 9182 for (idx = 0; idx < cfg_size; idx++) { 9183 if (!(bp->link_params.speed_cap_mask[idx] & 9184 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 9185 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; 9186 9187 if (!(bp->link_params.speed_cap_mask[idx] & 9188 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 9189 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; 9190 9191 if (!(bp->link_params.speed_cap_mask[idx] & 9192 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 9193 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; 9194 9195 if (!(bp->link_params.speed_cap_mask[idx] & 9196 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 9197 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; 9198 9199 if (!(bp->link_params.speed_cap_mask[idx] & 9200 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 9201 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | 9202 SUPPORTED_1000baseT_Full); 9203 9204 if (!(bp->link_params.speed_cap_mask[idx] & 9205 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 9206 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; 9207 9208 if (!(bp->link_params.speed_cap_mask[idx] & 9209 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 9210 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; 9211 9212 } 9213 9214 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], 9215 bp->port.supported[1]); 9216} 9217 9218static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) 9219{ 9220 u32 link_config, idx, cfg_size = 0; 9221 bp->port.advertising[0] = 0; 9222 bp->port.advertising[1] = 0; 9223 switch (bp->link_params.num_phys) { 9224 case 1: 9225 case 2: 9226 cfg_size = 1; 9227 break; 9228 case 3: 9229 cfg_size = 2; 9230 break; 9231 } 9232 for (idx = 0; idx < cfg_size; idx++) { 9233 bp->link_params.req_duplex[idx] = DUPLEX_FULL; 9234 link_config = bp->port.link_config[idx]; 9235 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 9236 case PORT_FEATURE_LINK_SPEED_AUTO: 9237 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { 9238 bp->link_params.req_line_speed[idx] = 9239 SPEED_AUTO_NEG; 9240 bp->port.advertising[idx] |= 9241 bp->port.supported[idx]; 9242 } else { 9243 /* force 10G, no AN */ 9244 bp->link_params.req_line_speed[idx] = 9245 SPEED_10000; 9246 bp->port.advertising[idx] |= 9247 (ADVERTISED_10000baseT_Full | 9248 ADVERTISED_FIBRE); 9249 continue; 9250 } 9251 break; 9252 9253 case PORT_FEATURE_LINK_SPEED_10M_FULL: 9254 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { 9255 bp->link_params.req_line_speed[idx] = 9256 SPEED_10; 9257 bp->port.advertising[idx] |= 9258 (ADVERTISED_10baseT_Full | 9259 ADVERTISED_TP); 9260 } else { 9261 BNX2X_ERR("NVRAM config error. " 9262 "Invalid link_config 0x%x" 9263 " speed_cap_mask 0x%x\n", 9264 link_config, 9265 bp->link_params.speed_cap_mask[idx]); 9266 return; 9267 } 9268 break; 9269 9270 case PORT_FEATURE_LINK_SPEED_10M_HALF: 9271 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { 9272 bp->link_params.req_line_speed[idx] = 9273 SPEED_10; 9274 bp->link_params.req_duplex[idx] = 9275 DUPLEX_HALF; 9276 bp->port.advertising[idx] |= 9277 (ADVERTISED_10baseT_Half | 9278 ADVERTISED_TP); 9279 } else { 9280 BNX2X_ERR("NVRAM config error. " 9281 "Invalid link_config 0x%x" 9282 " speed_cap_mask 0x%x\n", 9283 link_config, 9284 bp->link_params.speed_cap_mask[idx]); 9285 return; 9286 } 9287 break; 9288 9289 case PORT_FEATURE_LINK_SPEED_100M_FULL: 9290 if (bp->port.supported[idx] & 9291 SUPPORTED_100baseT_Full) { 9292 bp->link_params.req_line_speed[idx] = 9293 SPEED_100; 9294 bp->port.advertising[idx] |= 9295 (ADVERTISED_100baseT_Full | 9296 ADVERTISED_TP); 9297 } else { 9298 BNX2X_ERR("NVRAM config error. " 9299 "Invalid link_config 0x%x" 9300 " speed_cap_mask 0x%x\n", 9301 link_config, 9302 bp->link_params.speed_cap_mask[idx]); 9303 return; 9304 } 9305 break; 9306 9307 case PORT_FEATURE_LINK_SPEED_100M_HALF: 9308 if (bp->port.supported[idx] & 9309 SUPPORTED_100baseT_Half) { 9310 bp->link_params.req_line_speed[idx] = 9311 SPEED_100; 9312 bp->link_params.req_duplex[idx] = 9313 DUPLEX_HALF; 9314 bp->port.advertising[idx] |= 9315 (ADVERTISED_100baseT_Half | 9316 ADVERTISED_TP); 9317 } else { 9318 BNX2X_ERR("NVRAM config error. " 9319 "Invalid link_config 0x%x" 9320 " speed_cap_mask 0x%x\n", 9321 link_config, 9322 bp->link_params.speed_cap_mask[idx]); 9323 return; 9324 } 9325 break; 9326 9327 case PORT_FEATURE_LINK_SPEED_1G: 9328 if (bp->port.supported[idx] & 9329 SUPPORTED_1000baseT_Full) { 9330 bp->link_params.req_line_speed[idx] = 9331 SPEED_1000; 9332 bp->port.advertising[idx] |= 9333 (ADVERTISED_1000baseT_Full | 9334 ADVERTISED_TP); 9335 } else { 9336 BNX2X_ERR("NVRAM config error. " 9337 "Invalid link_config 0x%x" 9338 " speed_cap_mask 0x%x\n", 9339 link_config, 9340 bp->link_params.speed_cap_mask[idx]); 9341 return; 9342 } 9343 break; 9344 9345 case PORT_FEATURE_LINK_SPEED_2_5G: 9346 if (bp->port.supported[idx] & 9347 SUPPORTED_2500baseX_Full) { 9348 bp->link_params.req_line_speed[idx] = 9349 SPEED_2500; 9350 bp->port.advertising[idx] |= 9351 (ADVERTISED_2500baseX_Full | 9352 ADVERTISED_TP); 9353 } else { 9354 BNX2X_ERR("NVRAM config error. " 9355 "Invalid link_config 0x%x" 9356 " speed_cap_mask 0x%x\n", 9357 link_config, 9358 bp->link_params.speed_cap_mask[idx]); 9359 return; 9360 } 9361 break; 9362 9363 case PORT_FEATURE_LINK_SPEED_10G_CX4: 9364 if (bp->port.supported[idx] & 9365 SUPPORTED_10000baseT_Full) { 9366 bp->link_params.req_line_speed[idx] = 9367 SPEED_10000; 9368 bp->port.advertising[idx] |= 9369 (ADVERTISED_10000baseT_Full | 9370 ADVERTISED_FIBRE); 9371 } else { 9372 BNX2X_ERR("NVRAM config error. " 9373 "Invalid link_config 0x%x" 9374 " speed_cap_mask 0x%x\n", 9375 link_config, 9376 bp->link_params.speed_cap_mask[idx]); 9377 return; 9378 } 9379 break; 9380 case PORT_FEATURE_LINK_SPEED_20G: 9381 bp->link_params.req_line_speed[idx] = SPEED_20000; 9382 9383 break; 9384 default: 9385 BNX2X_ERR("NVRAM config error. " 9386 "BAD link speed link_config 0x%x\n", 9387 link_config); 9388 bp->link_params.req_line_speed[idx] = 9389 SPEED_AUTO_NEG; 9390 bp->port.advertising[idx] = 9391 bp->port.supported[idx]; 9392 break; 9393 } 9394 9395 bp->link_params.req_flow_ctrl[idx] = (link_config & 9396 PORT_FEATURE_FLOW_CONTROL_MASK); 9397 if ((bp->link_params.req_flow_ctrl[idx] == 9398 BNX2X_FLOW_CTRL_AUTO) && 9399 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { 9400 bp->link_params.req_flow_ctrl[idx] = 9401 BNX2X_FLOW_CTRL_NONE; 9402 } 9403 9404 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl" 9405 " 0x%x advertising 0x%x\n", 9406 bp->link_params.req_line_speed[idx], 9407 bp->link_params.req_duplex[idx], 9408 bp->link_params.req_flow_ctrl[idx], 9409 bp->port.advertising[idx]); 9410 } 9411} 9412 9413static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 9414{ 9415 mac_hi = cpu_to_be16(mac_hi); 9416 mac_lo = cpu_to_be32(mac_lo); 9417 memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); 9418 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); 9419} 9420 9421static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) 9422{ 9423 int port = BP_PORT(bp); 9424 u32 config; 9425 u32 ext_phy_type, ext_phy_config; 9426 9427 bp->link_params.bp = bp; 9428 bp->link_params.port = port; 9429 9430 bp->link_params.lane_config = 9431 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 9432 9433 bp->link_params.speed_cap_mask[0] = 9434 SHMEM_RD(bp, 9435 dev_info.port_hw_config[port].speed_capability_mask); 9436 bp->link_params.speed_cap_mask[1] = 9437 SHMEM_RD(bp, 9438 dev_info.port_hw_config[port].speed_capability_mask2); 9439 bp->port.link_config[0] = 9440 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 9441 9442 bp->port.link_config[1] = 9443 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); 9444 9445 bp->link_params.multi_phy_config = 9446 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); 9447 /* If the device is capable of WoL, set the default state according 9448 * to the HW 9449 */ 9450 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 9451 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 9452 (config & PORT_FEATURE_WOL_ENABLED)); 9453 9454 BNX2X_DEV_INFO("lane_config 0x%08x " 9455 "speed_cap_mask0 0x%08x link_config0 0x%08x\n", 9456 bp->link_params.lane_config, 9457 bp->link_params.speed_cap_mask[0], 9458 bp->port.link_config[0]); 9459 9460 bp->link_params.switch_cfg = (bp->port.link_config[0] & 9461 PORT_FEATURE_CONNECTED_SWITCH_MASK); 9462 bnx2x_phy_probe(&bp->link_params); 9463 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 9464 9465 bnx2x_link_settings_requested(bp); 9466 9467 /* 9468 * If connected directly, work with the internal PHY, otherwise, work 9469 * with the external PHY 9470 */ 9471 ext_phy_config = 9472 SHMEM_RD(bp, 9473 dev_info.port_hw_config[port].external_phy_config); 9474 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 9475 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 9476 bp->mdio.prtad = bp->port.phy_addr; 9477 9478 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 9479 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 9480 bp->mdio.prtad = 9481 XGXS_EXT_PHY_ADDR(ext_phy_config); 9482 9483 /* 9484 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) 9485 * In MF mode, it is set to cover self test cases 9486 */ 9487 if (IS_MF(bp)) 9488 bp->port.need_hw_lock = 1; 9489 else 9490 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, 9491 bp->common.shmem_base, 9492 bp->common.shmem2_base); 9493} 9494 9495void bnx2x_get_iscsi_info(struct bnx2x *bp) 9496{ 9497#ifdef BCM_CNIC 9498 int port = BP_PORT(bp); 9499 9500 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9501 drv_lic_key[port].max_iscsi_conn); 9502 9503 /* Get the number of maximum allowed iSCSI connections */ 9504 bp->cnic_eth_dev.max_iscsi_conn = 9505 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> 9506 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; 9507 9508 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", 9509 bp->cnic_eth_dev.max_iscsi_conn); 9510 9511 /* 9512 * If maximum allowed number of connections is zero - 9513 * disable the feature. 9514 */ 9515 if (!bp->cnic_eth_dev.max_iscsi_conn) 9516 bp->flags |= NO_ISCSI_FLAG; 9517#else 9518 bp->flags |= NO_ISCSI_FLAG; 9519#endif 9520} 9521 9522static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp) 9523{ 9524#ifdef BCM_CNIC 9525 int port = BP_PORT(bp); 9526 int func = BP_ABS_FUNC(bp); 9527 9528 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9529 drv_lic_key[port].max_fcoe_conn); 9530 9531 /* Get the number of maximum allowed FCoE connections */ 9532 bp->cnic_eth_dev.max_fcoe_conn = 9533 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> 9534 BNX2X_MAX_FCOE_INIT_CONN_SHIFT; 9535 9536 /* Read the WWN: */ 9537 if (!IS_MF(bp)) { 9538 /* Port info */ 9539 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9540 SHMEM_RD(bp, 9541 dev_info.port_hw_config[port]. 9542 fcoe_wwn_port_name_upper); 9543 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9544 SHMEM_RD(bp, 9545 dev_info.port_hw_config[port]. 9546 fcoe_wwn_port_name_lower); 9547 9548 /* Node info */ 9549 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9550 SHMEM_RD(bp, 9551 dev_info.port_hw_config[port]. 9552 fcoe_wwn_node_name_upper); 9553 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9554 SHMEM_RD(bp, 9555 dev_info.port_hw_config[port]. 9556 fcoe_wwn_node_name_lower); 9557 } else if (!IS_MF_SD(bp)) { 9558 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9559 9560 /* 9561 * Read the WWN info only if the FCoE feature is enabled for 9562 * this function. 9563 */ 9564 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9565 /* Port info */ 9566 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9567 MF_CFG_RD(bp, func_ext_config[func]. 9568 fcoe_wwn_port_name_upper); 9569 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9570 MF_CFG_RD(bp, func_ext_config[func]. 9571 fcoe_wwn_port_name_lower); 9572 9573 /* Node info */ 9574 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9575 MF_CFG_RD(bp, func_ext_config[func]. 9576 fcoe_wwn_node_name_upper); 9577 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9578 MF_CFG_RD(bp, func_ext_config[func]. 9579 fcoe_wwn_node_name_lower); 9580 } 9581 } 9582 9583 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); 9584 9585 /* 9586 * If maximum allowed number of connections is zero - 9587 * disable the feature. 9588 */ 9589 if (!bp->cnic_eth_dev.max_fcoe_conn) 9590 bp->flags |= NO_FCOE_FLAG; 9591#else 9592 bp->flags |= NO_FCOE_FLAG; 9593#endif 9594} 9595 9596static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) 9597{ 9598 /* 9599 * iSCSI may be dynamically disabled but reading 9600 * info here we will decrease memory usage by driver 9601 * if the feature is disabled for good 9602 */ 9603 bnx2x_get_iscsi_info(bp); 9604 bnx2x_get_fcoe_info(bp); 9605} 9606 9607static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) 9608{ 9609 u32 val, val2; 9610 int func = BP_ABS_FUNC(bp); 9611 int port = BP_PORT(bp); 9612#ifdef BCM_CNIC 9613 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; 9614 u8 *fip_mac = bp->fip_mac; 9615#endif 9616 9617 /* Zero primary MAC configuration */ 9618 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9619 9620 if (BP_NOMCP(bp)) { 9621 BNX2X_ERROR("warning: random MAC workaround active\n"); 9622 random_ether_addr(bp->dev->dev_addr); 9623 } else if (IS_MF(bp)) { 9624 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 9625 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); 9626 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && 9627 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) 9628 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9629 9630#ifdef BCM_CNIC 9631 /* 9632 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or 9633 * FCoE MAC then the appropriate feature should be disabled. 9634 */ 9635 if (IS_MF_SI(bp)) { 9636 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9637 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 9638 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9639 iscsi_mac_addr_upper); 9640 val = MF_CFG_RD(bp, func_ext_config[func]. 9641 iscsi_mac_addr_lower); 9642 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9643 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9644 iscsi_mac); 9645 } else 9646 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 9647 9648 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9649 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9650 fcoe_mac_addr_upper); 9651 val = MF_CFG_RD(bp, func_ext_config[func]. 9652 fcoe_mac_addr_lower); 9653 bnx2x_set_mac_buf(fip_mac, val, val2); 9654 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n", 9655 fip_mac); 9656 9657 } else 9658 bp->flags |= NO_FCOE_FLAG; 9659 } else { /* SD mode */ 9660 if (BNX2X_IS_MF_PROTOCOL_ISCSI(bp)) { 9661 /* use primary mac as iscsi mac */ 9662 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); 9663 /* Zero primary MAC configuration */ 9664 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9665 9666 BNX2X_DEV_INFO("SD ISCSI MODE\n"); 9667 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9668 iscsi_mac); 9669 } 9670 } 9671#endif 9672 } else { 9673 /* in SF read MACs from port configuration */ 9674 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 9675 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 9676 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9677 9678#ifdef BCM_CNIC 9679 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9680 iscsi_mac_upper); 9681 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9682 iscsi_mac_lower); 9683 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9684 9685 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9686 fcoe_fip_mac_upper); 9687 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9688 fcoe_fip_mac_lower); 9689 bnx2x_set_mac_buf(fip_mac, val, val2); 9690#endif 9691 } 9692 9693 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 9694 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); 9695 9696#ifdef BCM_CNIC 9697 /* Set the FCoE MAC in MF_SD mode */ 9698 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp)) 9699 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); 9700 9701 /* Disable iSCSI if MAC configuration is 9702 * invalid. 9703 */ 9704 if (!is_valid_ether_addr(iscsi_mac)) { 9705 bp->flags |= NO_ISCSI_FLAG; 9706 memset(iscsi_mac, 0, ETH_ALEN); 9707 } 9708 9709 /* Disable FCoE if MAC configuration is 9710 * invalid. 9711 */ 9712 if (!is_valid_ether_addr(fip_mac)) { 9713 bp->flags |= NO_FCOE_FLAG; 9714 memset(bp->fip_mac, 0, ETH_ALEN); 9715 } 9716#endif 9717 9718 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) 9719 dev_err(&bp->pdev->dev, 9720 "bad Ethernet MAC address configuration: " 9721 "%pM, change it manually before bringing up " 9722 "the appropriate network interface\n", 9723 bp->dev->dev_addr); 9724} 9725 9726static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) 9727{ 9728 int /*abs*/func = BP_ABS_FUNC(bp); 9729 int vn; 9730 u32 val = 0; 9731 int rc = 0; 9732 9733 bnx2x_get_common_hwinfo(bp); 9734 9735 /* 9736 * initialize IGU parameters 9737 */ 9738 if (CHIP_IS_E1x(bp)) { 9739 bp->common.int_block = INT_BLOCK_HC; 9740 9741 bp->igu_dsb_id = DEF_SB_IGU_ID; 9742 bp->igu_base_sb = 0; 9743 } else { 9744 bp->common.int_block = INT_BLOCK_IGU; 9745 9746 /* do not allow device reset during IGU info preocessing */ 9747 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9748 9749 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 9750 9751 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9752 int tout = 5000; 9753 9754 BNX2X_DEV_INFO("FORCING Normal Mode\n"); 9755 9756 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 9757 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); 9758 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); 9759 9760 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9761 tout--; 9762 usleep_range(1000, 1000); 9763 } 9764 9765 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9766 dev_err(&bp->pdev->dev, 9767 "FORCING Normal Mode failed!!!\n"); 9768 return -EPERM; 9769 } 9770 } 9771 9772 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9773 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); 9774 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; 9775 } else 9776 BNX2X_DEV_INFO("IGU Normal Mode\n"); 9777 9778 bnx2x_get_igu_cam_info(bp); 9779 9780 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9781 } 9782 9783 /* 9784 * set base FW non-default (fast path) status block id, this value is 9785 * used to initialize the fw_sb_id saved on the fp/queue structure to 9786 * determine the id used by the FW. 9787 */ 9788 if (CHIP_IS_E1x(bp)) 9789 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); 9790 else /* 9791 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of 9792 * the same queue are indicated on the same IGU SB). So we prefer 9793 * FW and IGU SBs to be the same value. 9794 */ 9795 bp->base_fw_ndsb = bp->igu_base_sb; 9796 9797 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" 9798 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, 9799 bp->igu_sb_cnt, bp->base_fw_ndsb); 9800 9801 /* 9802 * Initialize MF configuration 9803 */ 9804 9805 bp->mf_ov = 0; 9806 bp->mf_mode = 0; 9807 vn = BP_VN(bp); 9808 9809 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 9810 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 9811 bp->common.shmem2_base, SHMEM2_RD(bp, size), 9812 (u32)offsetof(struct shmem2_region, mf_cfg_addr)); 9813 9814 if (SHMEM2_HAS(bp, mf_cfg_addr)) 9815 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); 9816 else 9817 bp->common.mf_cfg_base = bp->common.shmem_base + 9818 offsetof(struct shmem_region, func_mb) + 9819 E1H_FUNC_MAX * sizeof(struct drv_func_mb); 9820 /* 9821 * get mf configuration: 9822 * 1. existence of MF configuration 9823 * 2. MAC address must be legal (check only upper bytes) 9824 * for Switch-Independent mode; 9825 * OVLAN must be legal for Switch-Dependent mode 9826 * 3. SF_MODE configures specific MF mode 9827 */ 9828 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9829 /* get mf configuration */ 9830 val = SHMEM_RD(bp, 9831 dev_info.shared_feature_config.config); 9832 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; 9833 9834 switch (val) { 9835 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 9836 val = MF_CFG_RD(bp, func_mf_config[func]. 9837 mac_upper); 9838 /* check for legal mac (upper bytes)*/ 9839 if (val != 0xffff) { 9840 bp->mf_mode = MULTI_FUNCTION_SI; 9841 bp->mf_config[vn] = MF_CFG_RD(bp, 9842 func_mf_config[func].config); 9843 } else 9844 BNX2X_DEV_INFO("illegal MAC address " 9845 "for SI\n"); 9846 break; 9847 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 9848 /* get OV configuration */ 9849 val = MF_CFG_RD(bp, 9850 func_mf_config[FUNC_0].e1hov_tag); 9851 val &= FUNC_MF_CFG_E1HOV_TAG_MASK; 9852 9853 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9854 bp->mf_mode = MULTI_FUNCTION_SD; 9855 bp->mf_config[vn] = MF_CFG_RD(bp, 9856 func_mf_config[func].config); 9857 } else 9858 BNX2X_DEV_INFO("illegal OV for SD\n"); 9859 break; 9860 default: 9861 /* Unknown configuration: reset mf_config */ 9862 bp->mf_config[vn] = 0; 9863 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val); 9864 } 9865 } 9866 9867 BNX2X_DEV_INFO("%s function mode\n", 9868 IS_MF(bp) ? "multi" : "single"); 9869 9870 switch (bp->mf_mode) { 9871 case MULTI_FUNCTION_SD: 9872 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 9873 FUNC_MF_CFG_E1HOV_TAG_MASK; 9874 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9875 bp->mf_ov = val; 9876 bp->path_has_ovlan = true; 9877 9878 BNX2X_DEV_INFO("MF OV for func %d is %d " 9879 "(0x%04x)\n", func, bp->mf_ov, 9880 bp->mf_ov); 9881 } else { 9882 dev_err(&bp->pdev->dev, 9883 "No valid MF OV for func %d, " 9884 "aborting\n", func); 9885 return -EPERM; 9886 } 9887 break; 9888 case MULTI_FUNCTION_SI: 9889 BNX2X_DEV_INFO("func %d is in MF " 9890 "switch-independent mode\n", func); 9891 break; 9892 default: 9893 if (vn) { 9894 dev_err(&bp->pdev->dev, 9895 "VN %d is in a single function mode, " 9896 "aborting\n", vn); 9897 return -EPERM; 9898 } 9899 break; 9900 } 9901 9902 /* check if other port on the path needs ovlan: 9903 * Since MF configuration is shared between ports 9904 * Possible mixed modes are only 9905 * {SF, SI} {SF, SD} {SD, SF} {SI, SF} 9906 */ 9907 if (CHIP_MODE_IS_4_PORT(bp) && 9908 !bp->path_has_ovlan && 9909 !IS_MF(bp) && 9910 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9911 u8 other_port = !BP_PORT(bp); 9912 u8 other_func = BP_PATH(bp) + 2*other_port; 9913 val = MF_CFG_RD(bp, 9914 func_mf_config[other_func].e1hov_tag); 9915 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) 9916 bp->path_has_ovlan = true; 9917 } 9918 } 9919 9920 /* adjust igu_sb_cnt to MF for E1x */ 9921 if (CHIP_IS_E1x(bp) && IS_MF(bp)) 9922 bp->igu_sb_cnt /= E1HVN_MAX; 9923 9924 /* port info */ 9925 bnx2x_get_port_hwinfo(bp); 9926 9927 /* Get MAC addresses */ 9928 bnx2x_get_mac_hwinfo(bp); 9929 9930 bnx2x_get_cnic_info(bp); 9931 9932 /* Get current FW pulse sequence */ 9933 if (!BP_NOMCP(bp)) { 9934 int mb_idx = BP_FW_MB_IDX(bp); 9935 9936 bp->fw_drv_pulse_wr_seq = 9937 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) & 9938 DRV_PULSE_SEQ_MASK); 9939 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq); 9940 } 9941 9942 return rc; 9943} 9944 9945static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) 9946{ 9947 int cnt, i, block_end, rodi; 9948 char vpd_start[BNX2X_VPD_LEN+1]; 9949 char str_id_reg[VENDOR_ID_LEN+1]; 9950 char str_id_cap[VENDOR_ID_LEN+1]; 9951 char *vpd_data; 9952 char *vpd_extended_data = NULL; 9953 u8 len; 9954 9955 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); 9956 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); 9957 9958 if (cnt < BNX2X_VPD_LEN) 9959 goto out_not_found; 9960 9961 /* VPD RO tag should be first tag after identifier string, hence 9962 * we should be able to find it in first BNX2X_VPD_LEN chars 9963 */ 9964 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, 9965 PCI_VPD_LRDT_RO_DATA); 9966 if (i < 0) 9967 goto out_not_found; 9968 9969 block_end = i + PCI_VPD_LRDT_TAG_SIZE + 9970 pci_vpd_lrdt_size(&vpd_start[i]); 9971 9972 i += PCI_VPD_LRDT_TAG_SIZE; 9973 9974 if (block_end > BNX2X_VPD_LEN) { 9975 vpd_extended_data = kmalloc(block_end, GFP_KERNEL); 9976 if (vpd_extended_data == NULL) 9977 goto out_not_found; 9978 9979 /* read rest of vpd image into vpd_extended_data */ 9980 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); 9981 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, 9982 block_end - BNX2X_VPD_LEN, 9983 vpd_extended_data + BNX2X_VPD_LEN); 9984 if (cnt < (block_end - BNX2X_VPD_LEN)) 9985 goto out_not_found; 9986 vpd_data = vpd_extended_data; 9987 } else 9988 vpd_data = vpd_start; 9989 9990 /* now vpd_data holds full vpd content in both cases */ 9991 9992 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 9993 PCI_VPD_RO_KEYWORD_MFR_ID); 9994 if (rodi < 0) 9995 goto out_not_found; 9996 9997 len = pci_vpd_info_field_size(&vpd_data[rodi]); 9998 9999 if (len != VENDOR_ID_LEN) 10000 goto out_not_found; 10001 10002 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 10003 10004 /* vendor specific info */ 10005 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); 10006 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); 10007 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || 10008 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { 10009 10010 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 10011 PCI_VPD_RO_KEYWORD_VENDOR0); 10012 if (rodi >= 0) { 10013 len = pci_vpd_info_field_size(&vpd_data[rodi]); 10014 10015 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 10016 10017 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { 10018 memcpy(bp->fw_ver, &vpd_data[rodi], len); 10019 bp->fw_ver[len] = ' '; 10020 } 10021 } 10022 kfree(vpd_extended_data); 10023 return; 10024 } 10025out_not_found: 10026 kfree(vpd_extended_data); 10027 return; 10028} 10029 10030static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) 10031{ 10032 u32 flags = 0; 10033 10034 if (CHIP_REV_IS_FPGA(bp)) 10035 SET_FLAGS(flags, MODE_FPGA); 10036 else if (CHIP_REV_IS_EMUL(bp)) 10037 SET_FLAGS(flags, MODE_EMUL); 10038 else 10039 SET_FLAGS(flags, MODE_ASIC); 10040 10041 if (CHIP_MODE_IS_4_PORT(bp)) 10042 SET_FLAGS(flags, MODE_PORT4); 10043 else 10044 SET_FLAGS(flags, MODE_PORT2); 10045 10046 if (CHIP_IS_E2(bp)) 10047 SET_FLAGS(flags, MODE_E2); 10048 else if (CHIP_IS_E3(bp)) { 10049 SET_FLAGS(flags, MODE_E3); 10050 if (CHIP_REV(bp) == CHIP_REV_Ax) 10051 SET_FLAGS(flags, MODE_E3_A0); 10052 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ 10053 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 10054 } 10055 10056 if (IS_MF(bp)) { 10057 SET_FLAGS(flags, MODE_MF); 10058 switch (bp->mf_mode) { 10059 case MULTI_FUNCTION_SD: 10060 SET_FLAGS(flags, MODE_MF_SD); 10061 break; 10062 case MULTI_FUNCTION_SI: 10063 SET_FLAGS(flags, MODE_MF_SI); 10064 break; 10065 } 10066 } else 10067 SET_FLAGS(flags, MODE_SF); 10068 10069#if defined(__LITTLE_ENDIAN) 10070 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 10071#else /*(__BIG_ENDIAN)*/ 10072 SET_FLAGS(flags, MODE_BIG_ENDIAN); 10073#endif 10074 INIT_MODE_FLAGS(bp) = flags; 10075} 10076 10077static int __devinit bnx2x_init_bp(struct bnx2x *bp) 10078{ 10079 int func; 10080 int timer_interval; 10081 int rc; 10082 10083 mutex_init(&bp->port.phy_mutex); 10084 mutex_init(&bp->fw_mb_mutex); 10085 spin_lock_init(&bp->stats_lock); 10086#ifdef BCM_CNIC 10087 mutex_init(&bp->cnic_mutex); 10088#endif 10089 10090 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); 10091 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); 10092 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); 10093 rc = bnx2x_get_hwinfo(bp); 10094 if (rc) 10095 return rc; 10096 10097 bnx2x_set_modes_bitmap(bp); 10098 10099 rc = bnx2x_alloc_mem_bp(bp); 10100 if (rc) 10101 return rc; 10102 10103 bnx2x_read_fwinfo(bp); 10104 10105 func = BP_FUNC(bp); 10106 10107 /* need to reset chip if undi was active */ 10108 if (!BP_NOMCP(bp)) 10109 bnx2x_undi_unload(bp); 10110 10111 /* init fw_seq after undi_unload! */ 10112 if (!BP_NOMCP(bp)) { 10113 bp->fw_seq = 10114 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 10115 DRV_MSG_SEQ_NUMBER_MASK); 10116 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 10117 } 10118 10119 if (CHIP_REV_IS_FPGA(bp)) 10120 dev_err(&bp->pdev->dev, "FPGA detected\n"); 10121 10122 if (BP_NOMCP(bp) && (func == 0)) 10123 dev_err(&bp->pdev->dev, "MCP disabled, " 10124 "must load devices in order!\n"); 10125 10126 bp->multi_mode = multi_mode; 10127 10128 bp->disable_tpa = disable_tpa; 10129 10130#ifdef BCM_CNIC 10131 bp->disable_tpa |= IS_MF_ISCSI_SD(bp); 10132#endif 10133 10134 /* Set TPA flags */ 10135 if (bp->disable_tpa) { 10136 bp->flags &= ~TPA_ENABLE_FLAG; 10137 bp->dev->features &= ~NETIF_F_LRO; 10138 } else { 10139 bp->flags |= TPA_ENABLE_FLAG; 10140 bp->dev->features |= NETIF_F_LRO; 10141 } 10142 10143 if (CHIP_IS_E1(bp)) 10144 bp->dropless_fc = 0; 10145 else 10146 bp->dropless_fc = dropless_fc; 10147 10148 bp->mrrs = mrrs; 10149 10150 bp->tx_ring_size = MAX_TX_AVAIL; 10151 10152 /* make sure that the numbers are in the right granularity */ 10153 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; 10154 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; 10155 10156 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ); 10157 bp->current_interval = (poll ? poll : timer_interval); 10158 10159 init_timer(&bp->timer); 10160 bp->timer.expires = jiffies + bp->current_interval; 10161 bp->timer.data = (unsigned long) bp; 10162 bp->timer.function = bnx2x_timer; 10163 10164 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); 10165 bnx2x_dcbx_init_params(bp); 10166 10167#ifdef BCM_CNIC 10168 if (CHIP_IS_E1x(bp)) 10169 bp->cnic_base_cl_id = FP_SB_MAX_E1x; 10170 else 10171 bp->cnic_base_cl_id = FP_SB_MAX_E2; 10172#endif 10173 10174 /* multiple tx priority */ 10175 if (CHIP_IS_E1x(bp)) 10176 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; 10177 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) 10178 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; 10179 if (CHIP_IS_E3B0(bp)) 10180 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; 10181 10182 return rc; 10183} 10184 10185 10186/**************************************************************************** 10187* General service functions 10188****************************************************************************/ 10189 10190/* 10191 * net_device service functions 10192 */ 10193 10194/* called with rtnl_lock */ 10195static int bnx2x_open(struct net_device *dev) 10196{ 10197 struct bnx2x *bp = netdev_priv(dev); 10198 bool global = false; 10199 int other_engine = BP_PATH(bp) ? 0 : 1; 10200 u32 other_load_counter, load_counter; 10201 10202 netif_carrier_off(dev); 10203 10204 bnx2x_set_power_state(bp, PCI_D0); 10205 10206 other_load_counter = bnx2x_get_load_cnt(bp, other_engine); 10207 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp)); 10208 10209 /* 10210 * If parity had happen during the unload, then attentions 10211 * and/or RECOVERY_IN_PROGRES may still be set. In this case we 10212 * want the first function loaded on the current engine to 10213 * complete the recovery. 10214 */ 10215 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 10216 bnx2x_chk_parity_attn(bp, &global, true)) 10217 do { 10218 /* 10219 * If there are attentions and they are in a global 10220 * blocks, set the GLOBAL_RESET bit regardless whether 10221 * it will be this function that will complete the 10222 * recovery or not. 10223 */ 10224 if (global) 10225 bnx2x_set_reset_global(bp); 10226 10227 /* 10228 * Only the first function on the current engine should 10229 * try to recover in open. In case of attentions in 10230 * global blocks only the first in the chip should try 10231 * to recover. 10232 */ 10233 if ((!load_counter && 10234 (!global || !other_load_counter)) && 10235 bnx2x_trylock_leader_lock(bp) && 10236 !bnx2x_leader_reset(bp)) { 10237 netdev_info(bp->dev, "Recovered in open\n"); 10238 break; 10239 } 10240 10241 /* recovery has failed... */ 10242 bnx2x_set_power_state(bp, PCI_D3hot); 10243 bp->recovery_state = BNX2X_RECOVERY_FAILED; 10244 10245 netdev_err(bp->dev, "Recovery flow hasn't been properly" 10246 " completed yet. Try again later. If u still see this" 10247 " message after a few retries then power cycle is" 10248 " required.\n"); 10249 10250 return -EAGAIN; 10251 } while (0); 10252 10253 bp->recovery_state = BNX2X_RECOVERY_DONE; 10254 return bnx2x_nic_load(bp, LOAD_OPEN); 10255} 10256 10257/* called with rtnl_lock */ 10258int bnx2x_close(struct net_device *dev) 10259{ 10260 struct bnx2x *bp = netdev_priv(dev); 10261 10262 /* Unload the driver, release IRQs */ 10263 bnx2x_nic_unload(bp, UNLOAD_CLOSE); 10264 10265 /* Power off */ 10266 bnx2x_set_power_state(bp, PCI_D3hot); 10267 10268 return 0; 10269} 10270 10271static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp, 10272 struct bnx2x_mcast_ramrod_params *p) 10273{ 10274 int mc_count = netdev_mc_count(bp->dev); 10275 struct bnx2x_mcast_list_elem *mc_mac = 10276 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); 10277 struct netdev_hw_addr *ha; 10278 10279 if (!mc_mac) 10280 return -ENOMEM; 10281 10282 INIT_LIST_HEAD(&p->mcast_list); 10283 10284 netdev_for_each_mc_addr(ha, bp->dev) { 10285 mc_mac->mac = bnx2x_mc_addr(ha); 10286 list_add_tail(&mc_mac->link, &p->mcast_list); 10287 mc_mac++; 10288 } 10289 10290 p->mcast_list_len = mc_count; 10291 10292 return 0; 10293} 10294 10295static inline void bnx2x_free_mcast_macs_list( 10296 struct bnx2x_mcast_ramrod_params *p) 10297{ 10298 struct bnx2x_mcast_list_elem *mc_mac = 10299 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, 10300 link); 10301 10302 WARN_ON(!mc_mac); 10303 kfree(mc_mac); 10304} 10305 10306/** 10307 * bnx2x_set_uc_list - configure a new unicast MACs list. 10308 * 10309 * @bp: driver handle 10310 * 10311 * We will use zero (0) as a MAC type for these MACs. 10312 */ 10313static inline int bnx2x_set_uc_list(struct bnx2x *bp) 10314{ 10315 int rc; 10316 struct net_device *dev = bp->dev; 10317 struct netdev_hw_addr *ha; 10318 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj; 10319 unsigned long ramrod_flags = 0; 10320 10321 /* First schedule a cleanup up of old configuration */ 10322 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); 10323 if (rc < 0) { 10324 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); 10325 return rc; 10326 } 10327 10328 netdev_for_each_uc_addr(ha, dev) { 10329 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, 10330 BNX2X_UC_LIST_MAC, &ramrod_flags); 10331 if (rc < 0) { 10332 BNX2X_ERR("Failed to schedule ADD operations: %d\n", 10333 rc); 10334 return rc; 10335 } 10336 } 10337 10338 /* Execute the pending commands */ 10339 __set_bit(RAMROD_CONT, &ramrod_flags); 10340 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, 10341 BNX2X_UC_LIST_MAC, &ramrod_flags); 10342} 10343 10344static inline int bnx2x_set_mc_list(struct bnx2x *bp) 10345{ 10346 struct net_device *dev = bp->dev; 10347 struct bnx2x_mcast_ramrod_params rparam = {0}; 10348 int rc = 0; 10349 10350 rparam.mcast_obj = &bp->mcast_obj; 10351 10352 /* first, clear all configured multicast MACs */ 10353 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 10354 if (rc < 0) { 10355 BNX2X_ERR("Failed to clear multicast " 10356 "configuration: %d\n", rc); 10357 return rc; 10358 } 10359 10360 /* then, configure a new MACs list */ 10361 if (netdev_mc_count(dev)) { 10362 rc = bnx2x_init_mcast_macs_list(bp, &rparam); 10363 if (rc) { 10364 BNX2X_ERR("Failed to create multicast MACs " 10365 "list: %d\n", rc); 10366 return rc; 10367 } 10368 10369 /* Now add the new MACs */ 10370 rc = bnx2x_config_mcast(bp, &rparam, 10371 BNX2X_MCAST_CMD_ADD); 10372 if (rc < 0) 10373 BNX2X_ERR("Failed to set a new multicast " 10374 "configuration: %d\n", rc); 10375 10376 bnx2x_free_mcast_macs_list(&rparam); 10377 } 10378 10379 return rc; 10380} 10381 10382 10383/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ 10384void bnx2x_set_rx_mode(struct net_device *dev) 10385{ 10386 struct bnx2x *bp = netdev_priv(dev); 10387 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 10388 10389 if (bp->state != BNX2X_STATE_OPEN) { 10390 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 10391 return; 10392 } 10393 10394 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); 10395 10396 if (dev->flags & IFF_PROMISC) 10397 rx_mode = BNX2X_RX_MODE_PROMISC; 10398 else if ((dev->flags & IFF_ALLMULTI) || 10399 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && 10400 CHIP_IS_E1(bp))) 10401 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10402 else { 10403 /* some multicasts */ 10404 if (bnx2x_set_mc_list(bp) < 0) 10405 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10406 10407 if (bnx2x_set_uc_list(bp) < 0) 10408 rx_mode = BNX2X_RX_MODE_PROMISC; 10409 } 10410 10411 bp->rx_mode = rx_mode; 10412#ifdef BCM_CNIC 10413 /* handle ISCSI SD mode */ 10414 if (IS_MF_ISCSI_SD(bp)) 10415 bp->rx_mode = BNX2X_RX_MODE_NONE; 10416#endif 10417 10418 /* Schedule the rx_mode command */ 10419 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { 10420 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 10421 return; 10422 } 10423 10424 bnx2x_set_storm_rx_mode(bp); 10425} 10426 10427/* called with rtnl_lock */ 10428static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 10429 int devad, u16 addr) 10430{ 10431 struct bnx2x *bp = netdev_priv(netdev); 10432 u16 value; 10433 int rc; 10434 10435 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 10436 prtad, devad, addr); 10437 10438 /* The HW expects different devad if CL22 is used */ 10439 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10440 10441 bnx2x_acquire_phy_lock(bp); 10442 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); 10443 bnx2x_release_phy_lock(bp); 10444 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 10445 10446 if (!rc) 10447 rc = value; 10448 return rc; 10449} 10450 10451/* called with rtnl_lock */ 10452static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, 10453 u16 addr, u16 value) 10454{ 10455 struct bnx2x *bp = netdev_priv(netdev); 10456 int rc; 10457 10458 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x," 10459 " value 0x%x\n", prtad, devad, addr, value); 10460 10461 /* The HW expects different devad if CL22 is used */ 10462 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10463 10464 bnx2x_acquire_phy_lock(bp); 10465 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); 10466 bnx2x_release_phy_lock(bp); 10467 return rc; 10468} 10469 10470/* called with rtnl_lock */ 10471static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 10472{ 10473 struct bnx2x *bp = netdev_priv(dev); 10474 struct mii_ioctl_data *mdio = if_mii(ifr); 10475 10476 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", 10477 mdio->phy_id, mdio->reg_num, mdio->val_in); 10478 10479 if (!netif_running(dev)) 10480 return -EAGAIN; 10481 10482 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); 10483} 10484 10485#ifdef CONFIG_NET_POLL_CONTROLLER 10486static void poll_bnx2x(struct net_device *dev) 10487{ 10488 struct bnx2x *bp = netdev_priv(dev); 10489 10490 disable_irq(bp->pdev->irq); 10491 bnx2x_interrupt(bp->pdev->irq, dev); 10492 enable_irq(bp->pdev->irq); 10493} 10494#endif 10495 10496static int bnx2x_validate_addr(struct net_device *dev) 10497{ 10498 struct bnx2x *bp = netdev_priv(dev); 10499 10500 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) 10501 return -EADDRNOTAVAIL; 10502 return 0; 10503} 10504 10505static const struct net_device_ops bnx2x_netdev_ops = { 10506 .ndo_open = bnx2x_open, 10507 .ndo_stop = bnx2x_close, 10508 .ndo_start_xmit = bnx2x_start_xmit, 10509 .ndo_select_queue = bnx2x_select_queue, 10510 .ndo_set_rx_mode = bnx2x_set_rx_mode, 10511 .ndo_set_mac_address = bnx2x_change_mac_addr, 10512 .ndo_validate_addr = bnx2x_validate_addr, 10513 .ndo_do_ioctl = bnx2x_ioctl, 10514 .ndo_change_mtu = bnx2x_change_mtu, 10515 .ndo_fix_features = bnx2x_fix_features, 10516 .ndo_set_features = bnx2x_set_features, 10517 .ndo_tx_timeout = bnx2x_tx_timeout, 10518#ifdef CONFIG_NET_POLL_CONTROLLER 10519 .ndo_poll_controller = poll_bnx2x, 10520#endif 10521 .ndo_setup_tc = bnx2x_setup_tc, 10522 10523#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) 10524 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, 10525#endif 10526}; 10527 10528static inline int bnx2x_set_coherency_mask(struct bnx2x *bp) 10529{ 10530 struct device *dev = &bp->pdev->dev; 10531 10532 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 10533 bp->flags |= USING_DAC_FLAG; 10534 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 10535 dev_err(dev, "dma_set_coherent_mask failed, " 10536 "aborting\n"); 10537 return -EIO; 10538 } 10539 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 10540 dev_err(dev, "System does not support DMA, aborting\n"); 10541 return -EIO; 10542 } 10543 10544 return 0; 10545} 10546 10547static int __devinit bnx2x_init_dev(struct pci_dev *pdev, 10548 struct net_device *dev, 10549 unsigned long board_type) 10550{ 10551 struct bnx2x *bp; 10552 int rc; 10553 u32 pci_cfg_dword; 10554 bool chip_is_e1x = (board_type == BCM57710 || 10555 board_type == BCM57711 || 10556 board_type == BCM57711E); 10557 10558 SET_NETDEV_DEV(dev, &pdev->dev); 10559 bp = netdev_priv(dev); 10560 10561 bp->dev = dev; 10562 bp->pdev = pdev; 10563 bp->flags = 0; 10564 10565 rc = pci_enable_device(pdev); 10566 if (rc) { 10567 dev_err(&bp->pdev->dev, 10568 "Cannot enable PCI device, aborting\n"); 10569 goto err_out; 10570 } 10571 10572 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 10573 dev_err(&bp->pdev->dev, 10574 "Cannot find PCI device base address, aborting\n"); 10575 rc = -ENODEV; 10576 goto err_out_disable; 10577 } 10578 10579 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 10580 dev_err(&bp->pdev->dev, "Cannot find second PCI device" 10581 " base address, aborting\n"); 10582 rc = -ENODEV; 10583 goto err_out_disable; 10584 } 10585 10586 if (atomic_read(&pdev->enable_cnt) == 1) { 10587 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 10588 if (rc) { 10589 dev_err(&bp->pdev->dev, 10590 "Cannot obtain PCI resources, aborting\n"); 10591 goto err_out_disable; 10592 } 10593 10594 pci_set_master(pdev); 10595 pci_save_state(pdev); 10596 } 10597 10598 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 10599 if (bp->pm_cap == 0) { 10600 dev_err(&bp->pdev->dev, 10601 "Cannot find power management capability, aborting\n"); 10602 rc = -EIO; 10603 goto err_out_release; 10604 } 10605 10606 if (!pci_is_pcie(pdev)) { 10607 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 10608 rc = -EIO; 10609 goto err_out_release; 10610 } 10611 10612 rc = bnx2x_set_coherency_mask(bp); 10613 if (rc) 10614 goto err_out_release; 10615 10616 dev->mem_start = pci_resource_start(pdev, 0); 10617 dev->base_addr = dev->mem_start; 10618 dev->mem_end = pci_resource_end(pdev, 0); 10619 10620 dev->irq = pdev->irq; 10621 10622 bp->regview = pci_ioremap_bar(pdev, 0); 10623 if (!bp->regview) { 10624 dev_err(&bp->pdev->dev, 10625 "Cannot map register space, aborting\n"); 10626 rc = -ENOMEM; 10627 goto err_out_release; 10628 } 10629 10630 /* In E1/E1H use pci device function given by kernel. 10631 * In E2/E3 read physical function from ME register since these chips 10632 * support Physical Device Assignment where kernel BDF maybe arbitrary 10633 * (depending on hypervisor). 10634 */ 10635 if (chip_is_e1x) 10636 bp->pf_num = PCI_FUNC(pdev->devfn); 10637 else {/* chip is E2/3*/ 10638 pci_read_config_dword(bp->pdev, 10639 PCICFG_ME_REGISTER, &pci_cfg_dword); 10640 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> 10641 ME_REG_ABS_PF_NUM_SHIFT); 10642 } 10643 DP(BNX2X_MSG_SP, "me reg PF num: %d\n", bp->pf_num); 10644 10645 bnx2x_set_power_state(bp, PCI_D0); 10646 10647 /* clean indirect addresses */ 10648 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 10649 PCICFG_VENDOR_ID_OFFSET); 10650 /* 10651 * Clean the following indirect addresses for all functions since it 10652 * is not used by the driver. 10653 */ 10654 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); 10655 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); 10656 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 10657 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 10658 10659 if (chip_is_e1x) { 10660 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 10661 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 10662 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 10663 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); 10664 } 10665 10666 /* 10667 * Enable internal target-read (in case we are probed after PF FLR). 10668 * Must be done prior to any BAR read access. Only for 57712 and up 10669 */ 10670 if (!chip_is_e1x) 10671 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 10672 10673 /* Reset the load counter */ 10674 bnx2x_clear_load_cnt(bp); 10675 10676 dev->watchdog_timeo = TX_TIMEOUT; 10677 10678 dev->netdev_ops = &bnx2x_netdev_ops; 10679 bnx2x_set_ethtool_ops(dev); 10680 10681 dev->priv_flags |= IFF_UNICAST_FLT; 10682 10683 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10684 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_LRO | 10685 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; 10686 10687 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10688 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 10689 10690 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; 10691 if (bp->flags & USING_DAC_FLAG) 10692 dev->features |= NETIF_F_HIGHDMA; 10693 10694 /* Add Loopback capability to the device */ 10695 dev->hw_features |= NETIF_F_LOOPBACK; 10696 10697#ifdef BCM_DCBNL 10698 dev->dcbnl_ops = &bnx2x_dcbnl_ops; 10699#endif 10700 10701 /* get_port_hwinfo() will set prtad and mmds properly */ 10702 bp->mdio.prtad = MDIO_PRTAD_NONE; 10703 bp->mdio.mmds = 0; 10704 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10705 bp->mdio.dev = dev; 10706 bp->mdio.mdio_read = bnx2x_mdio_read; 10707 bp->mdio.mdio_write = bnx2x_mdio_write; 10708 10709 return 0; 10710 10711err_out_release: 10712 if (atomic_read(&pdev->enable_cnt) == 1) 10713 pci_release_regions(pdev); 10714 10715err_out_disable: 10716 pci_disable_device(pdev); 10717 pci_set_drvdata(pdev, NULL); 10718 10719err_out: 10720 return rc; 10721} 10722 10723static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, 10724 int *width, int *speed) 10725{ 10726 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); 10727 10728 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; 10729 10730 /* return value of 1=2.5GHz 2=5GHz */ 10731 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; 10732} 10733 10734static int bnx2x_check_firmware(struct bnx2x *bp) 10735{ 10736 const struct firmware *firmware = bp->firmware; 10737 struct bnx2x_fw_file_hdr *fw_hdr; 10738 struct bnx2x_fw_file_section *sections; 10739 u32 offset, len, num_ops; 10740 u16 *ops_offsets; 10741 int i; 10742 const u8 *fw_ver; 10743 10744 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) 10745 return -EINVAL; 10746 10747 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 10748 sections = (struct bnx2x_fw_file_section *)fw_hdr; 10749 10750 /* Make sure none of the offsets and sizes make us read beyond 10751 * the end of the firmware data */ 10752 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { 10753 offset = be32_to_cpu(sections[i].offset); 10754 len = be32_to_cpu(sections[i].len); 10755 if (offset + len > firmware->size) { 10756 dev_err(&bp->pdev->dev, 10757 "Section %d length is out of bounds\n", i); 10758 return -EINVAL; 10759 } 10760 } 10761 10762 /* Likewise for the init_ops offsets */ 10763 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); 10764 ops_offsets = (u16 *)(firmware->data + offset); 10765 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); 10766 10767 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 10768 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 10769 dev_err(&bp->pdev->dev, 10770 "Section offset %d is out of bounds\n", i); 10771 return -EINVAL; 10772 } 10773 } 10774 10775 /* Check FW version */ 10776 offset = be32_to_cpu(fw_hdr->fw_version.offset); 10777 fw_ver = firmware->data + offset; 10778 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || 10779 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || 10780 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || 10781 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { 10782 dev_err(&bp->pdev->dev, 10783 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 10784 fw_ver[0], fw_ver[1], fw_ver[2], 10785 fw_ver[3], BCM_5710_FW_MAJOR_VERSION, 10786 BCM_5710_FW_MINOR_VERSION, 10787 BCM_5710_FW_REVISION_VERSION, 10788 BCM_5710_FW_ENGINEERING_VERSION); 10789 return -EINVAL; 10790 } 10791 10792 return 0; 10793} 10794 10795static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10796{ 10797 const __be32 *source = (const __be32 *)_source; 10798 u32 *target = (u32 *)_target; 10799 u32 i; 10800 10801 for (i = 0; i < n/4; i++) 10802 target[i] = be32_to_cpu(source[i]); 10803} 10804 10805/* 10806 Ops array is stored in the following format: 10807 {op(8bit), offset(24bit, big endian), data(32bit, big endian)} 10808 */ 10809static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) 10810{ 10811 const __be32 *source = (const __be32 *)_source; 10812 struct raw_op *target = (struct raw_op *)_target; 10813 u32 i, j, tmp; 10814 10815 for (i = 0, j = 0; i < n/8; i++, j += 2) { 10816 tmp = be32_to_cpu(source[j]); 10817 target[i].op = (tmp >> 24) & 0xff; 10818 target[i].offset = tmp & 0xffffff; 10819 target[i].raw_data = be32_to_cpu(source[j + 1]); 10820 } 10821} 10822 10823/** 10824 * IRO array is stored in the following format: 10825 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } 10826 */ 10827static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) 10828{ 10829 const __be32 *source = (const __be32 *)_source; 10830 struct iro *target = (struct iro *)_target; 10831 u32 i, j, tmp; 10832 10833 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { 10834 target[i].base = be32_to_cpu(source[j]); 10835 j++; 10836 tmp = be32_to_cpu(source[j]); 10837 target[i].m1 = (tmp >> 16) & 0xffff; 10838 target[i].m2 = tmp & 0xffff; 10839 j++; 10840 tmp = be32_to_cpu(source[j]); 10841 target[i].m3 = (tmp >> 16) & 0xffff; 10842 target[i].size = tmp & 0xffff; 10843 j++; 10844 } 10845} 10846 10847static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10848{ 10849 const __be16 *source = (const __be16 *)_source; 10850 u16 *target = (u16 *)_target; 10851 u32 i; 10852 10853 for (i = 0; i < n/2; i++) 10854 target[i] = be16_to_cpu(source[i]); 10855} 10856 10857#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ 10858do { \ 10859 u32 len = be32_to_cpu(fw_hdr->arr.len); \ 10860 bp->arr = kmalloc(len, GFP_KERNEL); \ 10861 if (!bp->arr) { \ 10862 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \ 10863 goto lbl; \ 10864 } \ 10865 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ 10866 (u8 *)bp->arr, len); \ 10867} while (0) 10868 10869int bnx2x_init_firmware(struct bnx2x *bp) 10870{ 10871 struct bnx2x_fw_file_hdr *fw_hdr; 10872 int rc; 10873 10874 10875 if (!bp->firmware) { 10876 const char *fw_file_name; 10877 10878 if (CHIP_IS_E1(bp)) 10879 fw_file_name = FW_FILE_NAME_E1; 10880 else if (CHIP_IS_E1H(bp)) 10881 fw_file_name = FW_FILE_NAME_E1H; 10882 else if (!CHIP_IS_E1x(bp)) 10883 fw_file_name = FW_FILE_NAME_E2; 10884 else { 10885 BNX2X_ERR("Unsupported chip revision\n"); 10886 return -EINVAL; 10887 } 10888 BNX2X_DEV_INFO("Loading %s\n", fw_file_name); 10889 10890 rc = request_firmware(&bp->firmware, fw_file_name, 10891 &bp->pdev->dev); 10892 if (rc) { 10893 BNX2X_ERR("Can't load firmware file %s\n", 10894 fw_file_name); 10895 goto request_firmware_exit; 10896 } 10897 10898 rc = bnx2x_check_firmware(bp); 10899 if (rc) { 10900 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); 10901 goto request_firmware_exit; 10902 } 10903 } 10904 10905 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; 10906 10907 /* Initialize the pointers to the init arrays */ 10908 /* Blob */ 10909 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); 10910 10911 /* Opcodes */ 10912 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); 10913 10914 /* Offsets */ 10915 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, 10916 be16_to_cpu_n); 10917 10918 /* STORMs firmware */ 10919 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10920 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); 10921 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + 10922 be32_to_cpu(fw_hdr->tsem_pram_data.offset); 10923 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10924 be32_to_cpu(fw_hdr->usem_int_table_data.offset); 10925 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + 10926 be32_to_cpu(fw_hdr->usem_pram_data.offset); 10927 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10928 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); 10929 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + 10930 be32_to_cpu(fw_hdr->xsem_pram_data.offset); 10931 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10932 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 10933 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 10934 be32_to_cpu(fw_hdr->csem_pram_data.offset); 10935 /* IRO */ 10936 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); 10937 10938 return 0; 10939 10940iro_alloc_err: 10941 kfree(bp->init_ops_offsets); 10942init_offsets_alloc_err: 10943 kfree(bp->init_ops); 10944init_ops_alloc_err: 10945 kfree(bp->init_data); 10946request_firmware_exit: 10947 release_firmware(bp->firmware); 10948 10949 return rc; 10950} 10951 10952static void bnx2x_release_firmware(struct bnx2x *bp) 10953{ 10954 kfree(bp->init_ops_offsets); 10955 kfree(bp->init_ops); 10956 kfree(bp->init_data); 10957 release_firmware(bp->firmware); 10958 bp->firmware = NULL; 10959} 10960 10961 10962static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { 10963 .init_hw_cmn_chip = bnx2x_init_hw_common_chip, 10964 .init_hw_cmn = bnx2x_init_hw_common, 10965 .init_hw_port = bnx2x_init_hw_port, 10966 .init_hw_func = bnx2x_init_hw_func, 10967 10968 .reset_hw_cmn = bnx2x_reset_common, 10969 .reset_hw_port = bnx2x_reset_port, 10970 .reset_hw_func = bnx2x_reset_func, 10971 10972 .gunzip_init = bnx2x_gunzip_init, 10973 .gunzip_end = bnx2x_gunzip_end, 10974 10975 .init_fw = bnx2x_init_firmware, 10976 .release_fw = bnx2x_release_firmware, 10977}; 10978 10979void bnx2x__init_func_obj(struct bnx2x *bp) 10980{ 10981 /* Prepare DMAE related driver resources */ 10982 bnx2x_setup_dmae(bp); 10983 10984 bnx2x_init_func_obj(bp, &bp->func_obj, 10985 bnx2x_sp(bp, func_rdata), 10986 bnx2x_sp_mapping(bp, func_rdata), 10987 &bnx2x_func_sp_drv); 10988} 10989 10990/* must be called after sriov-enable */ 10991static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp) 10992{ 10993 int cid_count = BNX2X_L2_CID_COUNT(bp); 10994 10995#ifdef BCM_CNIC 10996 cid_count += CNIC_CID_MAX; 10997#endif 10998 return roundup(cid_count, QM_CID_ROUND); 10999} 11000 11001/** 11002 * bnx2x_get_num_none_def_sbs - return the number of none default SBs 11003 * 11004 * @dev: pci device 11005 * 11006 */ 11007static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) 11008{ 11009 int pos; 11010 u16 control; 11011 11012 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 11013 11014 /* 11015 * If MSI-X is not supported - return number of SBs needed to support 11016 * one fast path queue: one FP queue + SB for CNIC 11017 */ 11018 if (!pos) 11019 return 1 + CNIC_PRESENT; 11020 11021 /* 11022 * The value in the PCI configuration space is the index of the last 11023 * entry, namely one less than the actual size of the table, which is 11024 * exactly what we want to return from this function: number of all SBs 11025 * without the default SB. 11026 */ 11027 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 11028 return control & PCI_MSIX_FLAGS_QSIZE; 11029} 11030 11031static int __devinit bnx2x_init_one(struct pci_dev *pdev, 11032 const struct pci_device_id *ent) 11033{ 11034 struct net_device *dev = NULL; 11035 struct bnx2x *bp; 11036 int pcie_width, pcie_speed; 11037 int rc, max_non_def_sbs; 11038 int rx_count, tx_count, rss_count; 11039 /* 11040 * An estimated maximum supported CoS number according to the chip 11041 * version. 11042 * We will try to roughly estimate the maximum number of CoSes this chip 11043 * may support in order to minimize the memory allocated for Tx 11044 * netdev_queue's. This number will be accurately calculated during the 11045 * initialization of bp->max_cos based on the chip versions AND chip 11046 * revision in the bnx2x_init_bp(). 11047 */ 11048 u8 max_cos_est = 0; 11049 11050 switch (ent->driver_data) { 11051 case BCM57710: 11052 case BCM57711: 11053 case BCM57711E: 11054 max_cos_est = BNX2X_MULTI_TX_COS_E1X; 11055 break; 11056 11057 case BCM57712: 11058 case BCM57712_MF: 11059 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; 11060 break; 11061 11062 case BCM57800: 11063 case BCM57800_MF: 11064 case BCM57810: 11065 case BCM57810_MF: 11066 case BCM57840: 11067 case BCM57840_MF: 11068 max_cos_est = BNX2X_MULTI_TX_COS_E3B0; 11069 break; 11070 11071 default: 11072 pr_err("Unknown board_type (%ld), aborting\n", 11073 ent->driver_data); 11074 return -ENODEV; 11075 } 11076 11077 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); 11078 11079 /* !!! FIXME !!! 11080 * Do not allow the maximum SB count to grow above 16 11081 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48. 11082 * We will use the FP_SB_MAX_E1x macro for this matter. 11083 */ 11084 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs); 11085 11086 WARN_ON(!max_non_def_sbs); 11087 11088 /* Maximum number of RSS queues: one IGU SB goes to CNIC */ 11089 rss_count = max_non_def_sbs - CNIC_PRESENT; 11090 11091 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ 11092 rx_count = rss_count + FCOE_PRESENT; 11093 11094 /* 11095 * Maximum number of netdev Tx queues: 11096 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 11097 */ 11098 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT; 11099 11100 /* dev zeroed in init_etherdev */ 11101 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); 11102 if (!dev) { 11103 dev_err(&pdev->dev, "Cannot allocate net device\n"); 11104 return -ENOMEM; 11105 } 11106 11107 bp = netdev_priv(dev); 11108 11109 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n", 11110 tx_count, rx_count); 11111 11112 bp->igu_sb_cnt = max_non_def_sbs; 11113 bp->msg_enable = debug; 11114 pci_set_drvdata(pdev, dev); 11115 11116 rc = bnx2x_init_dev(pdev, dev, ent->driver_data); 11117 if (rc < 0) { 11118 free_netdev(dev); 11119 return rc; 11120 } 11121 11122 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs); 11123 11124 rc = bnx2x_init_bp(bp); 11125 if (rc) 11126 goto init_one_exit; 11127 11128 /* 11129 * Map doorbels here as we need the real value of bp->max_cos which 11130 * is initialized in bnx2x_init_bp(). 11131 */ 11132 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), 11133 min_t(u64, BNX2X_DB_SIZE(bp), 11134 pci_resource_len(pdev, 2))); 11135 if (!bp->doorbells) { 11136 dev_err(&bp->pdev->dev, 11137 "Cannot map doorbell space, aborting\n"); 11138 rc = -ENOMEM; 11139 goto init_one_exit; 11140 } 11141 11142 /* calc qm_cid_count */ 11143 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); 11144 11145#ifdef BCM_CNIC 11146 /* disable FCOE L2 queue for E1x */ 11147 if (CHIP_IS_E1x(bp)) 11148 bp->flags |= NO_FCOE_FLAG; 11149 11150#endif 11151 11152 /* Configure interrupt mode: try to enable MSI-X/MSI if 11153 * needed, set bp->num_queues appropriately. 11154 */ 11155 bnx2x_set_int_mode(bp); 11156 11157 /* Add all NAPI objects */ 11158 bnx2x_add_all_napi(bp); 11159 11160 rc = register_netdev(dev); 11161 if (rc) { 11162 dev_err(&pdev->dev, "Cannot register net device\n"); 11163 goto init_one_exit; 11164 } 11165 11166#ifdef BCM_CNIC 11167 if (!NO_FCOE(bp)) { 11168 /* Add storage MAC address */ 11169 rtnl_lock(); 11170 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11171 rtnl_unlock(); 11172 } 11173#endif 11174 11175 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); 11176 11177 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", 11178 board_info[ent->driver_data].name, 11179 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 11180 pcie_width, 11181 ((!CHIP_IS_E2(bp) && pcie_speed == 2) || 11182 (CHIP_IS_E2(bp) && pcie_speed == 1)) ? 11183 "5GHz (Gen2)" : "2.5GHz", 11184 dev->base_addr, bp->pdev->irq, dev->dev_addr); 11185 11186 return 0; 11187 11188init_one_exit: 11189 if (bp->regview) 11190 iounmap(bp->regview); 11191 11192 if (bp->doorbells) 11193 iounmap(bp->doorbells); 11194 11195 free_netdev(dev); 11196 11197 if (atomic_read(&pdev->enable_cnt) == 1) 11198 pci_release_regions(pdev); 11199 11200 pci_disable_device(pdev); 11201 pci_set_drvdata(pdev, NULL); 11202 11203 return rc; 11204} 11205 11206static void __devexit bnx2x_remove_one(struct pci_dev *pdev) 11207{ 11208 struct net_device *dev = pci_get_drvdata(pdev); 11209 struct bnx2x *bp; 11210 11211 if (!dev) { 11212 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); 11213 return; 11214 } 11215 bp = netdev_priv(dev); 11216 11217#ifdef BCM_CNIC 11218 /* Delete storage MAC address */ 11219 if (!NO_FCOE(bp)) { 11220 rtnl_lock(); 11221 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11222 rtnl_unlock(); 11223 } 11224#endif 11225 11226#ifdef BCM_DCBNL 11227 /* Delete app tlvs from dcbnl */ 11228 bnx2x_dcbnl_update_applist(bp, true); 11229#endif 11230 11231 unregister_netdev(dev); 11232 11233 /* Delete all NAPI objects */ 11234 bnx2x_del_all_napi(bp); 11235 11236 /* Power on: we can't let PCI layer write to us while we are in D3 */ 11237 bnx2x_set_power_state(bp, PCI_D0); 11238 11239 /* Disable MSI/MSI-X */ 11240 bnx2x_disable_msi(bp); 11241 11242 /* Power off */ 11243 bnx2x_set_power_state(bp, PCI_D3hot); 11244 11245 /* Make sure RESET task is not scheduled before continuing */ 11246 cancel_delayed_work_sync(&bp->sp_rtnl_task); 11247 11248 if (bp->regview) 11249 iounmap(bp->regview); 11250 11251 if (bp->doorbells) 11252 iounmap(bp->doorbells); 11253 11254 bnx2x_release_firmware(bp); 11255 11256 bnx2x_free_mem_bp(bp); 11257 11258 free_netdev(dev); 11259 11260 if (atomic_read(&pdev->enable_cnt) == 1) 11261 pci_release_regions(pdev); 11262 11263 pci_disable_device(pdev); 11264 pci_set_drvdata(pdev, NULL); 11265} 11266 11267static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 11268{ 11269 int i; 11270 11271 bp->state = BNX2X_STATE_ERROR; 11272 11273 bp->rx_mode = BNX2X_RX_MODE_NONE; 11274 11275#ifdef BCM_CNIC 11276 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); 11277#endif 11278 /* Stop Tx */ 11279 bnx2x_tx_disable(bp); 11280 11281 bnx2x_netif_stop(bp, 0); 11282 11283 del_timer_sync(&bp->timer); 11284 11285 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 11286 11287 /* Release IRQs */ 11288 bnx2x_free_irq(bp); 11289 11290 /* Free SKBs, SGEs, TPA pool and driver internals */ 11291 bnx2x_free_skbs(bp); 11292 11293 for_each_rx_queue(bp, i) 11294 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 11295 11296 bnx2x_free_mem(bp); 11297 11298 bp->state = BNX2X_STATE_CLOSED; 11299 11300 netif_carrier_off(bp->dev); 11301 11302 return 0; 11303} 11304 11305static void bnx2x_eeh_recover(struct bnx2x *bp) 11306{ 11307 u32 val; 11308 11309 mutex_init(&bp->port.phy_mutex); 11310 11311 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 11312 bp->link_params.shmem_base = bp->common.shmem_base; 11313 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base); 11314 11315 if (!bp->common.shmem_base || 11316 (bp->common.shmem_base < 0xA0000) || 11317 (bp->common.shmem_base >= 0xC0000)) { 11318 BNX2X_DEV_INFO("MCP not active\n"); 11319 bp->flags |= NO_MCP_FLAG; 11320 return; 11321 } 11322 11323 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 11324 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11325 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11326 BNX2X_ERR("BAD MCP validity signature\n"); 11327 11328 if (!BP_NOMCP(bp)) { 11329 bp->fw_seq = 11330 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 11331 DRV_MSG_SEQ_NUMBER_MASK); 11332 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 11333 } 11334} 11335 11336/** 11337 * bnx2x_io_error_detected - called when PCI error is detected 11338 * @pdev: Pointer to PCI device 11339 * @state: The current pci connection state 11340 * 11341 * This function is called after a PCI bus error affecting 11342 * this device has been detected. 11343 */ 11344static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, 11345 pci_channel_state_t state) 11346{ 11347 struct net_device *dev = pci_get_drvdata(pdev); 11348 struct bnx2x *bp = netdev_priv(dev); 11349 11350 rtnl_lock(); 11351 11352 netif_device_detach(dev); 11353 11354 if (state == pci_channel_io_perm_failure) { 11355 rtnl_unlock(); 11356 return PCI_ERS_RESULT_DISCONNECT; 11357 } 11358 11359 if (netif_running(dev)) 11360 bnx2x_eeh_nic_unload(bp); 11361 11362 pci_disable_device(pdev); 11363 11364 rtnl_unlock(); 11365 11366 /* Request a slot reset */ 11367 return PCI_ERS_RESULT_NEED_RESET; 11368} 11369 11370/** 11371 * bnx2x_io_slot_reset - called after the PCI bus has been reset 11372 * @pdev: Pointer to PCI device 11373 * 11374 * Restart the card from scratch, as if from a cold-boot. 11375 */ 11376static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) 11377{ 11378 struct net_device *dev = pci_get_drvdata(pdev); 11379 struct bnx2x *bp = netdev_priv(dev); 11380 11381 rtnl_lock(); 11382 11383 if (pci_enable_device(pdev)) { 11384 dev_err(&pdev->dev, 11385 "Cannot re-enable PCI device after reset\n"); 11386 rtnl_unlock(); 11387 return PCI_ERS_RESULT_DISCONNECT; 11388 } 11389 11390 pci_set_master(pdev); 11391 pci_restore_state(pdev); 11392 11393 if (netif_running(dev)) 11394 bnx2x_set_power_state(bp, PCI_D0); 11395 11396 rtnl_unlock(); 11397 11398 return PCI_ERS_RESULT_RECOVERED; 11399} 11400 11401/** 11402 * bnx2x_io_resume - called when traffic can start flowing again 11403 * @pdev: Pointer to PCI device 11404 * 11405 * This callback is called when the error recovery driver tells us that 11406 * its OK to resume normal operation. 11407 */ 11408static void bnx2x_io_resume(struct pci_dev *pdev) 11409{ 11410 struct net_device *dev = pci_get_drvdata(pdev); 11411 struct bnx2x *bp = netdev_priv(dev); 11412 11413 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 11414 netdev_err(bp->dev, "Handling parity error recovery. " 11415 "Try again later\n"); 11416 return; 11417 } 11418 11419 rtnl_lock(); 11420 11421 bnx2x_eeh_recover(bp); 11422 11423 if (netif_running(dev)) 11424 bnx2x_nic_load(bp, LOAD_NORMAL); 11425 11426 netif_device_attach(dev); 11427 11428 rtnl_unlock(); 11429} 11430 11431static struct pci_error_handlers bnx2x_err_handler = { 11432 .error_detected = bnx2x_io_error_detected, 11433 .slot_reset = bnx2x_io_slot_reset, 11434 .resume = bnx2x_io_resume, 11435}; 11436 11437static struct pci_driver bnx2x_pci_driver = { 11438 .name = DRV_MODULE_NAME, 11439 .id_table = bnx2x_pci_tbl, 11440 .probe = bnx2x_init_one, 11441 .remove = __devexit_p(bnx2x_remove_one), 11442 .suspend = bnx2x_suspend, 11443 .resume = bnx2x_resume, 11444 .err_handler = &bnx2x_err_handler, 11445}; 11446 11447static int __init bnx2x_init(void) 11448{ 11449 int ret; 11450 11451 pr_info("%s", version); 11452 11453 bnx2x_wq = create_singlethread_workqueue("bnx2x"); 11454 if (bnx2x_wq == NULL) { 11455 pr_err("Cannot create workqueue\n"); 11456 return -ENOMEM; 11457 } 11458 11459 ret = pci_register_driver(&bnx2x_pci_driver); 11460 if (ret) { 11461 pr_err("Cannot register driver\n"); 11462 destroy_workqueue(bnx2x_wq); 11463 } 11464 return ret; 11465} 11466 11467static void __exit bnx2x_cleanup(void) 11468{ 11469 pci_unregister_driver(&bnx2x_pci_driver); 11470 11471 destroy_workqueue(bnx2x_wq); 11472} 11473 11474void bnx2x_notify_link_changed(struct bnx2x *bp) 11475{ 11476 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); 11477} 11478 11479module_init(bnx2x_init); 11480module_exit(bnx2x_cleanup); 11481 11482#ifdef BCM_CNIC 11483/** 11484 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). 11485 * 11486 * @bp: driver handle 11487 * @set: set or clear the CAM entry 11488 * 11489 * This function will wait until the ramdord completion returns. 11490 * Return 0 if success, -ENODEV if ramrod doesn't return. 11491 */ 11492static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) 11493{ 11494 unsigned long ramrod_flags = 0; 11495 11496 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 11497 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, 11498 &bp->iscsi_l2_mac_obj, true, 11499 BNX2X_ISCSI_ETH_MAC, &ramrod_flags); 11500} 11501 11502/* count denotes the number of new completions we have seen */ 11503static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) 11504{ 11505 struct eth_spe *spe; 11506 11507#ifdef BNX2X_STOP_ON_ERROR 11508 if (unlikely(bp->panic)) 11509 return; 11510#endif 11511 11512 spin_lock_bh(&bp->spq_lock); 11513 BUG_ON(bp->cnic_spq_pending < count); 11514 bp->cnic_spq_pending -= count; 11515 11516 11517 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { 11518 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) 11519 & SPE_HDR_CONN_TYPE) >> 11520 SPE_HDR_CONN_TYPE_SHIFT; 11521 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) 11522 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; 11523 11524 /* Set validation for iSCSI L2 client before sending SETUP 11525 * ramrod 11526 */ 11527 if (type == ETH_CONNECTION_TYPE) { 11528 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) 11529 bnx2x_set_ctx_validation(bp, &bp->context. 11530 vcxt[BNX2X_ISCSI_ETH_CID].eth, 11531 BNX2X_ISCSI_ETH_CID); 11532 } 11533 11534 /* 11535 * There may be not more than 8 L2, not more than 8 L5 SPEs 11536 * and in the air. We also check that number of outstanding 11537 * COMMON ramrods is not more than the EQ and SPQ can 11538 * accommodate. 11539 */ 11540 if (type == ETH_CONNECTION_TYPE) { 11541 if (!atomic_read(&bp->cq_spq_left)) 11542 break; 11543 else 11544 atomic_dec(&bp->cq_spq_left); 11545 } else if (type == NONE_CONNECTION_TYPE) { 11546 if (!atomic_read(&bp->eq_spq_left)) 11547 break; 11548 else 11549 atomic_dec(&bp->eq_spq_left); 11550 } else if ((type == ISCSI_CONNECTION_TYPE) || 11551 (type == FCOE_CONNECTION_TYPE)) { 11552 if (bp->cnic_spq_pending >= 11553 bp->cnic_eth_dev.max_kwqe_pending) 11554 break; 11555 else 11556 bp->cnic_spq_pending++; 11557 } else { 11558 BNX2X_ERR("Unknown SPE type: %d\n", type); 11559 bnx2x_panic(); 11560 break; 11561 } 11562 11563 spe = bnx2x_sp_get_next(bp); 11564 *spe = *bp->cnic_kwq_cons; 11565 11566 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n", 11567 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 11568 11569 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 11570 bp->cnic_kwq_cons = bp->cnic_kwq; 11571 else 11572 bp->cnic_kwq_cons++; 11573 } 11574 bnx2x_sp_prod_update(bp); 11575 spin_unlock_bh(&bp->spq_lock); 11576} 11577 11578static int bnx2x_cnic_sp_queue(struct net_device *dev, 11579 struct kwqe_16 *kwqes[], u32 count) 11580{ 11581 struct bnx2x *bp = netdev_priv(dev); 11582 int i; 11583 11584#ifdef BNX2X_STOP_ON_ERROR 11585 if (unlikely(bp->panic)) 11586 return -EIO; 11587#endif 11588 11589 spin_lock_bh(&bp->spq_lock); 11590 11591 for (i = 0; i < count; i++) { 11592 struct eth_spe *spe = (struct eth_spe *)kwqes[i]; 11593 11594 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) 11595 break; 11596 11597 *bp->cnic_kwq_prod = *spe; 11598 11599 bp->cnic_kwq_pending++; 11600 11601 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n", 11602 spe->hdr.conn_and_cmd_data, spe->hdr.type, 11603 spe->data.update_data_addr.hi, 11604 spe->data.update_data_addr.lo, 11605 bp->cnic_kwq_pending); 11606 11607 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 11608 bp->cnic_kwq_prod = bp->cnic_kwq; 11609 else 11610 bp->cnic_kwq_prod++; 11611 } 11612 11613 spin_unlock_bh(&bp->spq_lock); 11614 11615 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) 11616 bnx2x_cnic_sp_post(bp, 0); 11617 11618 return i; 11619} 11620 11621static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11622{ 11623 struct cnic_ops *c_ops; 11624 int rc = 0; 11625 11626 mutex_lock(&bp->cnic_mutex); 11627 c_ops = rcu_dereference_protected(bp->cnic_ops, 11628 lockdep_is_held(&bp->cnic_mutex)); 11629 if (c_ops) 11630 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11631 mutex_unlock(&bp->cnic_mutex); 11632 11633 return rc; 11634} 11635 11636static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11637{ 11638 struct cnic_ops *c_ops; 11639 int rc = 0; 11640 11641 rcu_read_lock(); 11642 c_ops = rcu_dereference(bp->cnic_ops); 11643 if (c_ops) 11644 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11645 rcu_read_unlock(); 11646 11647 return rc; 11648} 11649 11650/* 11651 * for commands that have no data 11652 */ 11653int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) 11654{ 11655 struct cnic_ctl_info ctl = {0}; 11656 11657 ctl.cmd = cmd; 11658 11659 return bnx2x_cnic_ctl_send(bp, &ctl); 11660} 11661 11662static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) 11663{ 11664 struct cnic_ctl_info ctl = {0}; 11665 11666 /* first we tell CNIC and only then we count this as a completion */ 11667 ctl.cmd = CNIC_CTL_COMPLETION_CMD; 11668 ctl.data.comp.cid = cid; 11669 ctl.data.comp.error = err; 11670 11671 bnx2x_cnic_ctl_send_bh(bp, &ctl); 11672 bnx2x_cnic_sp_post(bp, 0); 11673} 11674 11675 11676/* Called with netif_addr_lock_bh() taken. 11677 * Sets an rx_mode config for an iSCSI ETH client. 11678 * Doesn't block. 11679 * Completion should be checked outside. 11680 */ 11681static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) 11682{ 11683 unsigned long accept_flags = 0, ramrod_flags = 0; 11684 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11685 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; 11686 11687 if (start) { 11688 /* Start accepting on iSCSI L2 ring. Accept all multicasts 11689 * because it's the only way for UIO Queue to accept 11690 * multicasts (in non-promiscuous mode only one Queue per 11691 * function will receive multicast packets (leading in our 11692 * case). 11693 */ 11694 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); 11695 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); 11696 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); 11697 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 11698 11699 /* Clear STOP_PENDING bit if START is requested */ 11700 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); 11701 11702 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; 11703 } else 11704 /* Clear START_PENDING bit if STOP is requested */ 11705 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); 11706 11707 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 11708 set_bit(sched_state, &bp->sp_state); 11709 else { 11710 __set_bit(RAMROD_RX, &ramrod_flags); 11711 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, 11712 ramrod_flags); 11713 } 11714} 11715 11716 11717static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 11718{ 11719 struct bnx2x *bp = netdev_priv(dev); 11720 int rc = 0; 11721 11722 switch (ctl->cmd) { 11723 case DRV_CTL_CTXTBL_WR_CMD: { 11724 u32 index = ctl->data.io.offset; 11725 dma_addr_t addr = ctl->data.io.dma_addr; 11726 11727 bnx2x_ilt_wr(bp, index, addr); 11728 break; 11729 } 11730 11731 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { 11732 int count = ctl->data.credit.credit_count; 11733 11734 bnx2x_cnic_sp_post(bp, count); 11735 break; 11736 } 11737 11738 /* rtnl_lock is held. */ 11739 case DRV_CTL_START_L2_CMD: { 11740 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11741 unsigned long sp_bits = 0; 11742 11743 /* Configure the iSCSI classification object */ 11744 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, 11745 cp->iscsi_l2_client_id, 11746 cp->iscsi_l2_cid, BP_FUNC(bp), 11747 bnx2x_sp(bp, mac_rdata), 11748 bnx2x_sp_mapping(bp, mac_rdata), 11749 BNX2X_FILTER_MAC_PENDING, 11750 &bp->sp_state, BNX2X_OBJ_TYPE_RX, 11751 &bp->macs_pool); 11752 11753 /* Set iSCSI MAC address */ 11754 rc = bnx2x_set_iscsi_eth_mac_addr(bp); 11755 if (rc) 11756 break; 11757 11758 mmiowb(); 11759 barrier(); 11760 11761 /* Start accepting on iSCSI L2 ring */ 11762 11763 netif_addr_lock_bh(dev); 11764 bnx2x_set_iscsi_eth_rx_mode(bp, true); 11765 netif_addr_unlock_bh(dev); 11766 11767 /* bits to wait on */ 11768 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11769 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); 11770 11771 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11772 BNX2X_ERR("rx_mode completion timed out!\n"); 11773 11774 break; 11775 } 11776 11777 /* rtnl_lock is held. */ 11778 case DRV_CTL_STOP_L2_CMD: { 11779 unsigned long sp_bits = 0; 11780 11781 /* Stop accepting on iSCSI L2 ring */ 11782 netif_addr_lock_bh(dev); 11783 bnx2x_set_iscsi_eth_rx_mode(bp, false); 11784 netif_addr_unlock_bh(dev); 11785 11786 /* bits to wait on */ 11787 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11788 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); 11789 11790 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11791 BNX2X_ERR("rx_mode completion timed out!\n"); 11792 11793 mmiowb(); 11794 barrier(); 11795 11796 /* Unset iSCSI L2 MAC */ 11797 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, 11798 BNX2X_ISCSI_ETH_MAC, true); 11799 break; 11800 } 11801 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { 11802 int count = ctl->data.credit.credit_count; 11803 11804 smp_mb__before_atomic_inc(); 11805 atomic_add(count, &bp->cq_spq_left); 11806 smp_mb__after_atomic_inc(); 11807 break; 11808 } 11809 case DRV_CTL_ULP_REGISTER_CMD: { 11810 int ulp_type = ctl->data.ulp_type; 11811 11812 if (CHIP_IS_E3(bp)) { 11813 int idx = BP_FW_MB_IDX(bp); 11814 u32 cap; 11815 11816 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 11817 if (ulp_type == CNIC_ULP_ISCSI) 11818 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 11819 else if (ulp_type == CNIC_ULP_FCOE) 11820 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 11821 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 11822 } 11823 break; 11824 } 11825 case DRV_CTL_ULP_UNREGISTER_CMD: { 11826 int ulp_type = ctl->data.ulp_type; 11827 11828 if (CHIP_IS_E3(bp)) { 11829 int idx = BP_FW_MB_IDX(bp); 11830 u32 cap; 11831 11832 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 11833 if (ulp_type == CNIC_ULP_ISCSI) 11834 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 11835 else if (ulp_type == CNIC_ULP_FCOE) 11836 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 11837 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 11838 } 11839 break; 11840 } 11841 11842 default: 11843 BNX2X_ERR("unknown command %x\n", ctl->cmd); 11844 rc = -EINVAL; 11845 } 11846 11847 return rc; 11848} 11849 11850void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) 11851{ 11852 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11853 11854 if (bp->flags & USING_MSIX_FLAG) { 11855 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 11856 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 11857 cp->irq_arr[0].vector = bp->msix_table[1].vector; 11858 } else { 11859 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 11860 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 11861 } 11862 if (!CHIP_IS_E1x(bp)) 11863 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; 11864 else 11865 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; 11866 11867 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); 11868 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); 11869 cp->irq_arr[1].status_blk = bp->def_status_blk; 11870 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 11871 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; 11872 11873 cp->num_irq = 2; 11874} 11875 11876static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, 11877 void *data) 11878{ 11879 struct bnx2x *bp = netdev_priv(dev); 11880 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11881 11882 if (ops == NULL) 11883 return -EINVAL; 11884 11885 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 11886 if (!bp->cnic_kwq) 11887 return -ENOMEM; 11888 11889 bp->cnic_kwq_cons = bp->cnic_kwq; 11890 bp->cnic_kwq_prod = bp->cnic_kwq; 11891 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; 11892 11893 bp->cnic_spq_pending = 0; 11894 bp->cnic_kwq_pending = 0; 11895 11896 bp->cnic_data = data; 11897 11898 cp->num_irq = 0; 11899 cp->drv_state |= CNIC_DRV_STATE_REGD; 11900 cp->iro_arr = bp->iro_arr; 11901 11902 bnx2x_setup_cnic_irq_info(bp); 11903 11904 rcu_assign_pointer(bp->cnic_ops, ops); 11905 11906 return 0; 11907} 11908 11909static int bnx2x_unregister_cnic(struct net_device *dev) 11910{ 11911 struct bnx2x *bp = netdev_priv(dev); 11912 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11913 11914 mutex_lock(&bp->cnic_mutex); 11915 cp->drv_state = 0; 11916 RCU_INIT_POINTER(bp->cnic_ops, NULL); 11917 mutex_unlock(&bp->cnic_mutex); 11918 synchronize_rcu(); 11919 kfree(bp->cnic_kwq); 11920 bp->cnic_kwq = NULL; 11921 11922 return 0; 11923} 11924 11925struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) 11926{ 11927 struct bnx2x *bp = netdev_priv(dev); 11928 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11929 11930 /* If both iSCSI and FCoE are disabled - return NULL in 11931 * order to indicate CNIC that it should not try to work 11932 * with this device. 11933 */ 11934 if (NO_ISCSI(bp) && NO_FCOE(bp)) 11935 return NULL; 11936 11937 cp->drv_owner = THIS_MODULE; 11938 cp->chip_id = CHIP_ID(bp); 11939 cp->pdev = bp->pdev; 11940 cp->io_base = bp->regview; 11941 cp->io_base2 = bp->doorbells; 11942 cp->max_kwqe_pending = 8; 11943 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; 11944 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 11945 bnx2x_cid_ilt_lines(bp); 11946 cp->ctx_tbl_len = CNIC_ILT_LINES; 11947 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 11948 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 11949 cp->drv_ctl = bnx2x_drv_ctl; 11950 cp->drv_register_cnic = bnx2x_register_cnic; 11951 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 11952 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID; 11953 cp->iscsi_l2_client_id = 11954 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11955 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID; 11956 11957 if (NO_ISCSI_OOO(bp)) 11958 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 11959 11960 if (NO_ISCSI(bp)) 11961 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; 11962 11963 if (NO_FCOE(bp)) 11964 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 11965 11966 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, " 11967 "starting cid %d\n", 11968 cp->ctx_blk_size, 11969 cp->ctx_tbl_offset, 11970 cp->ctx_tbl_len, 11971 cp->starting_cid); 11972 return cp; 11973} 11974EXPORT_SYMBOL(bnx2x_cnic_probe); 11975 11976#endif /* BCM_CNIC */ 11977 11978