bnx2x_main.c revision fe603b4d680a2bba9d8c6d4267450fcf295f30d1
1/* bnx2x_main.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20#include <linux/module.h> 21#include <linux/moduleparam.h> 22#include <linux/kernel.h> 23#include <linux/device.h> /* for dev_info() */ 24#include <linux/timer.h> 25#include <linux/errno.h> 26#include <linux/ioport.h> 27#include <linux/slab.h> 28#include <linux/interrupt.h> 29#include <linux/pci.h> 30#include <linux/init.h> 31#include <linux/netdevice.h> 32#include <linux/etherdevice.h> 33#include <linux/skbuff.h> 34#include <linux/dma-mapping.h> 35#include <linux/bitops.h> 36#include <linux/irq.h> 37#include <linux/delay.h> 38#include <asm/byteorder.h> 39#include <linux/time.h> 40#include <linux/ethtool.h> 41#include <linux/mii.h> 42#include <linux/if.h> 43#include <linux/if_vlan.h> 44#include <net/ip.h> 45#include <net/ipv6.h> 46#include <net/tcp.h> 47#include <net/checksum.h> 48#include <net/ip6_checksum.h> 49#include <linux/workqueue.h> 50#include <linux/crc32.h> 51#include <linux/crc32c.h> 52#include <linux/prefetch.h> 53#include <linux/zlib.h> 54#include <linux/io.h> 55#include <linux/stringify.h> 56#include <linux/vmalloc.h> 57 58#include "bnx2x.h" 59#include "bnx2x_init.h" 60#include "bnx2x_init_ops.h" 61#include "bnx2x_cmn.h" 62#include "bnx2x_dcb.h" 63#include "bnx2x_sp.h" 64 65#include <linux/firmware.h> 66#include "bnx2x_fw_file_hdr.h" 67/* FW files */ 68#define FW_FILE_VERSION \ 69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 72 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 73#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 74#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 75#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 76 77/* Time in jiffies before concluding the transmitter is hung */ 78#define TX_TIMEOUT (5*HZ) 79 80static char version[] __devinitdata = 81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " 82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 83 84MODULE_AUTHOR("Eliezer Tamir"); 85MODULE_DESCRIPTION("Broadcom NetXtreme II " 86 "BCM57710/57711/57711E/" 87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 88 "57840/57840_MF Driver"); 89MODULE_LICENSE("GPL"); 90MODULE_VERSION(DRV_MODULE_VERSION); 91MODULE_FIRMWARE(FW_FILE_NAME_E1); 92MODULE_FIRMWARE(FW_FILE_NAME_E1H); 93MODULE_FIRMWARE(FW_FILE_NAME_E2); 94 95static int multi_mode = 1; 96module_param(multi_mode, int, 0); 97MODULE_PARM_DESC(multi_mode, " Multi queue mode " 98 "(0 Disable; 1 Enable (default))"); 99 100int num_queues; 101module_param(num_queues, int, 0); 102MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1" 103 " (default is as a number of CPUs)"); 104 105static int disable_tpa; 106module_param(disable_tpa, int, 0); 107MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 108 109#define INT_MODE_INTx 1 110#define INT_MODE_MSI 2 111static int int_mode; 112module_param(int_mode, int, 0); 113MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 114 "(1 INT#x; 2 MSI)"); 115 116static int dropless_fc; 117module_param(dropless_fc, int, 0); 118MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 119 120static int mrrs = -1; 121module_param(mrrs, int, 0); 122MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 123 124static int debug; 125module_param(debug, int, 0); 126MODULE_PARM_DESC(debug, " Default debug msglevel"); 127 128 129 130struct workqueue_struct *bnx2x_wq; 131 132enum bnx2x_board_type { 133 BCM57710 = 0, 134 BCM57711, 135 BCM57711E, 136 BCM57712, 137 BCM57712_MF, 138 BCM57800, 139 BCM57800_MF, 140 BCM57810, 141 BCM57810_MF, 142 BCM57840, 143 BCM57840_MF 144}; 145 146/* indexed by board_type, above */ 147static struct { 148 char *name; 149} board_info[] __devinitdata = { 150 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, 151 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, 152 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, 153 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, 154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, 155 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, 156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, 157 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, 158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, 159 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, 160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit " 161 "Ethernet Multi Function"} 162}; 163 164#ifndef PCI_DEVICE_ID_NX2_57710 165#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 166#endif 167#ifndef PCI_DEVICE_ID_NX2_57711 168#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 169#endif 170#ifndef PCI_DEVICE_ID_NX2_57711E 171#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 172#endif 173#ifndef PCI_DEVICE_ID_NX2_57712 174#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 175#endif 176#ifndef PCI_DEVICE_ID_NX2_57712_MF 177#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 178#endif 179#ifndef PCI_DEVICE_ID_NX2_57800 180#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 181#endif 182#ifndef PCI_DEVICE_ID_NX2_57800_MF 183#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 184#endif 185#ifndef PCI_DEVICE_ID_NX2_57810 186#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 187#endif 188#ifndef PCI_DEVICE_ID_NX2_57810_MF 189#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 190#endif 191#ifndef PCI_DEVICE_ID_NX2_57840 192#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 193#endif 194#ifndef PCI_DEVICE_ID_NX2_57840_MF 195#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 196#endif 197static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { 198 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, 208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 209 { 0 } 210}; 211 212MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 213 214/**************************************************************************** 215* General service functions 216****************************************************************************/ 217 218static inline void __storm_memset_dma_mapping(struct bnx2x *bp, 219 u32 addr, dma_addr_t mapping) 220{ 221 REG_WR(bp, addr, U64_LO(mapping)); 222 REG_WR(bp, addr + 4, U64_HI(mapping)); 223} 224 225static inline void storm_memset_spq_addr(struct bnx2x *bp, 226 dma_addr_t mapping, u16 abs_fid) 227{ 228 u32 addr = XSEM_REG_FAST_MEMORY + 229 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 230 231 __storm_memset_dma_mapping(bp, addr, mapping); 232} 233 234static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 235 u16 pf_id) 236{ 237 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 238 pf_id); 239 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 240 pf_id); 241 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 242 pf_id); 243 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 244 pf_id); 245} 246 247static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 248 u8 enable) 249{ 250 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 251 enable); 252 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 253 enable); 254 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 255 enable); 256 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 257 enable); 258} 259 260static inline void storm_memset_eq_data(struct bnx2x *bp, 261 struct event_ring_data *eq_data, 262 u16 pfid) 263{ 264 size_t size = sizeof(struct event_ring_data); 265 266 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 267 268 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 269} 270 271static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 272 u16 pfid) 273{ 274 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 275 REG_WR16(bp, addr, eq_prod); 276} 277 278/* used only at init 279 * locking is done by mcp 280 */ 281static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 282{ 283 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 284 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 285 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 286 PCICFG_VENDOR_ID_OFFSET); 287} 288 289static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 290{ 291 u32 val; 292 293 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 294 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 295 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 296 PCICFG_VENDOR_ID_OFFSET); 297 298 return val; 299} 300 301#define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 302#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 303#define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 304#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 305#define DMAE_DP_DST_NONE "dst_addr [none]" 306 307static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, 308 int msglvl) 309{ 310 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 311 312 switch (dmae->opcode & DMAE_COMMAND_DST) { 313 case DMAE_CMD_DST_PCI: 314 if (src_type == DMAE_CMD_SRC_PCI) 315 DP(msglvl, "DMAE: opcode 0x%08x\n" 316 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 317 "comp_addr [%x:%08x], comp_val 0x%08x\n", 318 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 319 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 320 dmae->comp_addr_hi, dmae->comp_addr_lo, 321 dmae->comp_val); 322 else 323 DP(msglvl, "DMAE: opcode 0x%08x\n" 324 "src [%08x], len [%d*4], dst [%x:%08x]\n" 325 "comp_addr [%x:%08x], comp_val 0x%08x\n", 326 dmae->opcode, dmae->src_addr_lo >> 2, 327 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 328 dmae->comp_addr_hi, dmae->comp_addr_lo, 329 dmae->comp_val); 330 break; 331 case DMAE_CMD_DST_GRC: 332 if (src_type == DMAE_CMD_SRC_PCI) 333 DP(msglvl, "DMAE: opcode 0x%08x\n" 334 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 335 "comp_addr [%x:%08x], comp_val 0x%08x\n", 336 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 337 dmae->len, dmae->dst_addr_lo >> 2, 338 dmae->comp_addr_hi, dmae->comp_addr_lo, 339 dmae->comp_val); 340 else 341 DP(msglvl, "DMAE: opcode 0x%08x\n" 342 "src [%08x], len [%d*4], dst [%08x]\n" 343 "comp_addr [%x:%08x], comp_val 0x%08x\n", 344 dmae->opcode, dmae->src_addr_lo >> 2, 345 dmae->len, dmae->dst_addr_lo >> 2, 346 dmae->comp_addr_hi, dmae->comp_addr_lo, 347 dmae->comp_val); 348 break; 349 default: 350 if (src_type == DMAE_CMD_SRC_PCI) 351 DP(msglvl, "DMAE: opcode 0x%08x\n" 352 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 353 "comp_addr [%x:%08x] comp_val 0x%08x\n", 354 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 355 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 356 dmae->comp_val); 357 else 358 DP(msglvl, "DMAE: opcode 0x%08x\n" 359 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 360 "comp_addr [%x:%08x] comp_val 0x%08x\n", 361 dmae->opcode, dmae->src_addr_lo >> 2, 362 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 363 dmae->comp_val); 364 break; 365 } 366 367} 368 369/* copy command into DMAE command memory and set DMAE command go */ 370void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 371{ 372 u32 cmd_offset; 373 int i; 374 375 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 376 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 377 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 378 379 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n", 380 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); 381 } 382 REG_WR(bp, dmae_reg_go_c[idx], 1); 383} 384 385u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 386{ 387 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 388 DMAE_CMD_C_ENABLE); 389} 390 391u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 392{ 393 return opcode & ~DMAE_CMD_SRC_RESET; 394} 395 396u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 397 bool with_comp, u8 comp_type) 398{ 399 u32 opcode = 0; 400 401 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 402 (dst_type << DMAE_COMMAND_DST_SHIFT)); 403 404 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 405 406 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 407 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | 408 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 409 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 410 411#ifdef __BIG_ENDIAN 412 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 413#else 414 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 415#endif 416 if (with_comp) 417 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 418 return opcode; 419} 420 421static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 422 struct dmae_command *dmae, 423 u8 src_type, u8 dst_type) 424{ 425 memset(dmae, 0, sizeof(struct dmae_command)); 426 427 /* set the opcode */ 428 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 429 true, DMAE_COMP_PCI); 430 431 /* fill in the completion parameters */ 432 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 433 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 434 dmae->comp_val = DMAE_COMP_VAL; 435} 436 437/* issue a dmae command over the init-channel and wailt for completion */ 438static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, 439 struct dmae_command *dmae) 440{ 441 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 442 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 443 int rc = 0; 444 445 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n", 446 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 447 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 448 449 /* 450 * Lock the dmae channel. Disable BHs to prevent a dead-lock 451 * as long as this code is called both from syscall context and 452 * from ndo_set_rx_mode() flow that may be called from BH. 453 */ 454 spin_lock_bh(&bp->dmae_lock); 455 456 /* reset completion */ 457 *wb_comp = 0; 458 459 /* post the command on the channel used for initializations */ 460 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 461 462 /* wait for completion */ 463 udelay(5); 464 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 465 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); 466 467 if (!cnt || 468 (bp->recovery_state != BNX2X_RECOVERY_DONE && 469 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 470 BNX2X_ERR("DMAE timeout!\n"); 471 rc = DMAE_TIMEOUT; 472 goto unlock; 473 } 474 cnt--; 475 udelay(50); 476 } 477 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 478 BNX2X_ERR("DMAE PCI error!\n"); 479 rc = DMAE_PCI_ERROR; 480 } 481 482 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n", 483 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 484 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 485 486unlock: 487 spin_unlock_bh(&bp->dmae_lock); 488 return rc; 489} 490 491void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 492 u32 len32) 493{ 494 struct dmae_command dmae; 495 496 if (!bp->dmae_ready) { 497 u32 *data = bnx2x_sp(bp, wb_data[0]); 498 499 DP(BNX2X_MSG_OFF, 500 "DMAE is not ready (dst_addr %08x len32 %d) using indirect\n", 501 dst_addr, len32); 502 if (CHIP_IS_E1(bp)) 503 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 504 else 505 bnx2x_init_str_wr(bp, dst_addr, data, len32); 506 return; 507 } 508 509 /* set opcode and fixed command fields */ 510 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 511 512 /* fill in addresses and len */ 513 dmae.src_addr_lo = U64_LO(dma_addr); 514 dmae.src_addr_hi = U64_HI(dma_addr); 515 dmae.dst_addr_lo = dst_addr >> 2; 516 dmae.dst_addr_hi = 0; 517 dmae.len = len32; 518 519 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 520 521 /* issue the command and wait for completion */ 522 bnx2x_issue_dmae_with_comp(bp, &dmae); 523} 524 525void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 526{ 527 struct dmae_command dmae; 528 529 if (!bp->dmae_ready) { 530 u32 *data = bnx2x_sp(bp, wb_data[0]); 531 int i; 532 533 if (CHIP_IS_E1(bp)) { 534 DP(BNX2X_MSG_OFF, 535 "DMAE is not ready (src_addr %08x len32 %d) using indirect\n", 536 src_addr, len32); 537 for (i = 0; i < len32; i++) 538 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 539 } else 540 for (i = 0; i < len32; i++) 541 data[i] = REG_RD(bp, src_addr + i*4); 542 543 return; 544 } 545 546 /* set opcode and fixed command fields */ 547 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 548 549 /* fill in addresses and len */ 550 dmae.src_addr_lo = src_addr >> 2; 551 dmae.src_addr_hi = 0; 552 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 553 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 554 dmae.len = len32; 555 556 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 557 558 /* issue the command and wait for completion */ 559 bnx2x_issue_dmae_with_comp(bp, &dmae); 560} 561 562static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 563 u32 addr, u32 len) 564{ 565 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 566 int offset = 0; 567 568 while (len > dmae_wr_max) { 569 bnx2x_write_dmae(bp, phys_addr + offset, 570 addr + offset, dmae_wr_max); 571 offset += dmae_wr_max * 4; 572 len -= dmae_wr_max; 573 } 574 575 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 576} 577 578/* used only for slowpath so not inlined */ 579static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo) 580{ 581 u32 wb_write[2]; 582 583 wb_write[0] = val_hi; 584 wb_write[1] = val_lo; 585 REG_WR_DMAE(bp, reg, wb_write, 2); 586} 587 588#ifdef USE_WB_RD 589static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg) 590{ 591 u32 wb_data[2]; 592 593 REG_RD_DMAE(bp, reg, wb_data, 2); 594 595 return HILO_U64(wb_data[0], wb_data[1]); 596} 597#endif 598 599static int bnx2x_mc_assert(struct bnx2x *bp) 600{ 601 char last_idx; 602 int i, rc = 0; 603 u32 row0, row1, row2, row3; 604 605 /* XSTORM */ 606 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + 607 XSTORM_ASSERT_LIST_INDEX_OFFSET); 608 if (last_idx) 609 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 610 611 /* print the asserts */ 612 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 613 614 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + 615 XSTORM_ASSERT_LIST_OFFSET(i)); 616 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + 617 XSTORM_ASSERT_LIST_OFFSET(i) + 4); 618 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + 619 XSTORM_ASSERT_LIST_OFFSET(i) + 8); 620 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + 621 XSTORM_ASSERT_LIST_OFFSET(i) + 12); 622 623 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 624 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x" 625 " 0x%08x 0x%08x 0x%08x\n", 626 i, row3, row2, row1, row0); 627 rc++; 628 } else { 629 break; 630 } 631 } 632 633 /* TSTORM */ 634 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + 635 TSTORM_ASSERT_LIST_INDEX_OFFSET); 636 if (last_idx) 637 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 638 639 /* print the asserts */ 640 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 641 642 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + 643 TSTORM_ASSERT_LIST_OFFSET(i)); 644 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + 645 TSTORM_ASSERT_LIST_OFFSET(i) + 4); 646 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + 647 TSTORM_ASSERT_LIST_OFFSET(i) + 8); 648 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + 649 TSTORM_ASSERT_LIST_OFFSET(i) + 12); 650 651 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 652 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x" 653 " 0x%08x 0x%08x 0x%08x\n", 654 i, row3, row2, row1, row0); 655 rc++; 656 } else { 657 break; 658 } 659 } 660 661 /* CSTORM */ 662 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + 663 CSTORM_ASSERT_LIST_INDEX_OFFSET); 664 if (last_idx) 665 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 666 667 /* print the asserts */ 668 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 669 670 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + 671 CSTORM_ASSERT_LIST_OFFSET(i)); 672 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + 673 CSTORM_ASSERT_LIST_OFFSET(i) + 4); 674 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + 675 CSTORM_ASSERT_LIST_OFFSET(i) + 8); 676 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + 677 CSTORM_ASSERT_LIST_OFFSET(i) + 12); 678 679 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 680 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x" 681 " 0x%08x 0x%08x 0x%08x\n", 682 i, row3, row2, row1, row0); 683 rc++; 684 } else { 685 break; 686 } 687 } 688 689 /* USTORM */ 690 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + 691 USTORM_ASSERT_LIST_INDEX_OFFSET); 692 if (last_idx) 693 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 694 695 /* print the asserts */ 696 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 697 698 row0 = REG_RD(bp, BAR_USTRORM_INTMEM + 699 USTORM_ASSERT_LIST_OFFSET(i)); 700 row1 = REG_RD(bp, BAR_USTRORM_INTMEM + 701 USTORM_ASSERT_LIST_OFFSET(i) + 4); 702 row2 = REG_RD(bp, BAR_USTRORM_INTMEM + 703 USTORM_ASSERT_LIST_OFFSET(i) + 8); 704 row3 = REG_RD(bp, BAR_USTRORM_INTMEM + 705 USTORM_ASSERT_LIST_OFFSET(i) + 12); 706 707 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 708 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x" 709 " 0x%08x 0x%08x 0x%08x\n", 710 i, row3, row2, row1, row0); 711 rc++; 712 } else { 713 break; 714 } 715 } 716 717 return rc; 718} 719 720void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 721{ 722 u32 addr, val; 723 u32 mark, offset; 724 __be32 data[9]; 725 int word; 726 u32 trace_shmem_base; 727 if (BP_NOMCP(bp)) { 728 BNX2X_ERR("NO MCP - can not dump\n"); 729 return; 730 } 731 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 732 (bp->common.bc_ver & 0xff0000) >> 16, 733 (bp->common.bc_ver & 0xff00) >> 8, 734 (bp->common.bc_ver & 0xff)); 735 736 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 737 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 738 printk("%s" "MCP PC at 0x%x\n", lvl, val); 739 740 if (BP_PATH(bp) == 0) 741 trace_shmem_base = bp->common.shmem_base; 742 else 743 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 744 addr = trace_shmem_base - 0x0800 + 4; 745 mark = REG_RD(bp, addr); 746 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 747 + ((mark + 0x3) & ~0x3) - 0x08000000; 748 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 749 750 printk("%s", lvl); 751 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { 752 for (word = 0; word < 8; word++) 753 data[word] = htonl(REG_RD(bp, offset + 4*word)); 754 data[8] = 0x0; 755 pr_cont("%s", (char *)data); 756 } 757 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 758 for (word = 0; word < 8; word++) 759 data[word] = htonl(REG_RD(bp, offset + 4*word)); 760 data[8] = 0x0; 761 pr_cont("%s", (char *)data); 762 } 763 printk("%s" "end of fw dump\n", lvl); 764} 765 766static inline void bnx2x_fw_dump(struct bnx2x *bp) 767{ 768 bnx2x_fw_dump_lvl(bp, KERN_ERR); 769} 770 771void bnx2x_panic_dump(struct bnx2x *bp) 772{ 773 int i; 774 u16 j; 775 struct hc_sp_status_block_data sp_sb_data; 776 int func = BP_FUNC(bp); 777#ifdef BNX2X_STOP_ON_ERROR 778 u16 start = 0, end = 0; 779 u8 cos; 780#endif 781 782 bp->stats_state = STATS_STATE_DISABLED; 783 bp->eth_stats.unrecoverable_error++; 784 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 785 786 BNX2X_ERR("begin crash dump -----------------\n"); 787 788 /* Indices */ 789 /* Common */ 790 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)" 791 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 792 bp->def_idx, bp->def_att_idx, bp->attn_state, 793 bp->spq_prod_idx, bp->stats_counter); 794 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 795 bp->def_status_blk->atten_status_block.attn_bits, 796 bp->def_status_blk->atten_status_block.attn_bits_ack, 797 bp->def_status_blk->atten_status_block.status_block_id, 798 bp->def_status_blk->atten_status_block.attn_bits_index); 799 BNX2X_ERR(" def ("); 800 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 801 pr_cont("0x%x%s", 802 bp->def_status_blk->sp_sb.index_values[i], 803 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 804 805 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 806 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + 807 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 808 i*sizeof(u32)); 809 810 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 811 sp_sb_data.igu_sb_id, 812 sp_sb_data.igu_seg_id, 813 sp_sb_data.p_func.pf_id, 814 sp_sb_data.p_func.vnic_id, 815 sp_sb_data.p_func.vf_id, 816 sp_sb_data.p_func.vf_valid, 817 sp_sb_data.state); 818 819 820 for_each_eth_queue(bp, i) { 821 struct bnx2x_fastpath *fp = &bp->fp[i]; 822 int loop; 823 struct hc_status_block_data_e2 sb_data_e2; 824 struct hc_status_block_data_e1x sb_data_e1x; 825 struct hc_status_block_sm *hc_sm_p = 826 CHIP_IS_E1x(bp) ? 827 sb_data_e1x.common.state_machine : 828 sb_data_e2.common.state_machine; 829 struct hc_index_data *hc_index_p = 830 CHIP_IS_E1x(bp) ? 831 sb_data_e1x.index_data : 832 sb_data_e2.index_data; 833 u8 data_size, cos; 834 u32 *sb_data_p; 835 struct bnx2x_fp_txdata txdata; 836 837 /* Rx */ 838 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)" 839 " rx_comp_prod(0x%x)" 840 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 841 i, fp->rx_bd_prod, fp->rx_bd_cons, 842 fp->rx_comp_prod, 843 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 844 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)" 845 " fp_hc_idx(0x%x)\n", 846 fp->rx_sge_prod, fp->last_max_sge, 847 le16_to_cpu(fp->fp_hc_idx)); 848 849 /* Tx */ 850 for_each_cos_in_tx_queue(fp, cos) 851 { 852 txdata = fp->txdata[cos]; 853 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)" 854 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)" 855 " *tx_cons_sb(0x%x)\n", 856 i, txdata.tx_pkt_prod, 857 txdata.tx_pkt_cons, txdata.tx_bd_prod, 858 txdata.tx_bd_cons, 859 le16_to_cpu(*txdata.tx_cons_sb)); 860 } 861 862 loop = CHIP_IS_E1x(bp) ? 863 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 864 865 /* host sb data */ 866 867#ifdef BCM_CNIC 868 if (IS_FCOE_FP(fp)) 869 continue; 870#endif 871 BNX2X_ERR(" run indexes ("); 872 for (j = 0; j < HC_SB_MAX_SM; j++) 873 pr_cont("0x%x%s", 874 fp->sb_running_index[j], 875 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 876 877 BNX2X_ERR(" indexes ("); 878 for (j = 0; j < loop; j++) 879 pr_cont("0x%x%s", 880 fp->sb_index_values[j], 881 (j == loop - 1) ? ")" : " "); 882 /* fw sb data */ 883 data_size = CHIP_IS_E1x(bp) ? 884 sizeof(struct hc_status_block_data_e1x) : 885 sizeof(struct hc_status_block_data_e2); 886 data_size /= sizeof(u32); 887 sb_data_p = CHIP_IS_E1x(bp) ? 888 (u32 *)&sb_data_e1x : 889 (u32 *)&sb_data_e2; 890 /* copy sb data in here */ 891 for (j = 0; j < data_size; j++) 892 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 893 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 894 j * sizeof(u32)); 895 896 if (!CHIP_IS_E1x(bp)) { 897 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 898 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 899 "state(0x%x)\n", 900 sb_data_e2.common.p_func.pf_id, 901 sb_data_e2.common.p_func.vf_id, 902 sb_data_e2.common.p_func.vf_valid, 903 sb_data_e2.common.p_func.vnic_id, 904 sb_data_e2.common.same_igu_sb_1b, 905 sb_data_e2.common.state); 906 } else { 907 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 908 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 909 "state(0x%x)\n", 910 sb_data_e1x.common.p_func.pf_id, 911 sb_data_e1x.common.p_func.vf_id, 912 sb_data_e1x.common.p_func.vf_valid, 913 sb_data_e1x.common.p_func.vnic_id, 914 sb_data_e1x.common.same_igu_sb_1b, 915 sb_data_e1x.common.state); 916 } 917 918 /* SB_SMs data */ 919 for (j = 0; j < HC_SB_MAX_SM; j++) { 920 pr_cont("SM[%d] __flags (0x%x) " 921 "igu_sb_id (0x%x) igu_seg_id(0x%x) " 922 "time_to_expire (0x%x) " 923 "timer_value(0x%x)\n", j, 924 hc_sm_p[j].__flags, 925 hc_sm_p[j].igu_sb_id, 926 hc_sm_p[j].igu_seg_id, 927 hc_sm_p[j].time_to_expire, 928 hc_sm_p[j].timer_value); 929 } 930 931 /* Indecies data */ 932 for (j = 0; j < loop; j++) { 933 pr_cont("INDEX[%d] flags (0x%x) " 934 "timeout (0x%x)\n", j, 935 hc_index_p[j].flags, 936 hc_index_p[j].timeout); 937 } 938 } 939 940#ifdef BNX2X_STOP_ON_ERROR 941 /* Rings */ 942 /* Rx */ 943 for_each_rx_queue(bp, i) { 944 struct bnx2x_fastpath *fp = &bp->fp[i]; 945 946 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 947 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 948 for (j = start; j != end; j = RX_BD(j + 1)) { 949 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 950 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 951 952 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 953 i, j, rx_bd[1], rx_bd[0], sw_bd->data); 954 } 955 956 start = RX_SGE(fp->rx_sge_prod); 957 end = RX_SGE(fp->last_max_sge); 958 for (j = start; j != end; j = RX_SGE(j + 1)) { 959 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 960 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 961 962 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 963 i, j, rx_sge[1], rx_sge[0], sw_page->page); 964 } 965 966 start = RCQ_BD(fp->rx_comp_cons - 10); 967 end = RCQ_BD(fp->rx_comp_cons + 503); 968 for (j = start; j != end; j = RCQ_BD(j + 1)) { 969 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 970 971 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 972 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 973 } 974 } 975 976 /* Tx */ 977 for_each_tx_queue(bp, i) { 978 struct bnx2x_fastpath *fp = &bp->fp[i]; 979 for_each_cos_in_tx_queue(fp, cos) { 980 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; 981 982 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 983 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 984 for (j = start; j != end; j = TX_BD(j + 1)) { 985 struct sw_tx_bd *sw_bd = 986 &txdata->tx_buf_ring[j]; 987 988 BNX2X_ERR("fp%d: txdata %d, " 989 "packet[%x]=[%p,%x]\n", 990 i, cos, j, sw_bd->skb, 991 sw_bd->first_bd); 992 } 993 994 start = TX_BD(txdata->tx_bd_cons - 10); 995 end = TX_BD(txdata->tx_bd_cons + 254); 996 for (j = start; j != end; j = TX_BD(j + 1)) { 997 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 998 999 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=" 1000 "[%x:%x:%x:%x]\n", 1001 i, cos, j, tx_bd[0], tx_bd[1], 1002 tx_bd[2], tx_bd[3]); 1003 } 1004 } 1005 } 1006#endif 1007 bnx2x_fw_dump(bp); 1008 bnx2x_mc_assert(bp); 1009 BNX2X_ERR("end crash dump -----------------\n"); 1010} 1011 1012/* 1013 * FLR Support for E2 1014 * 1015 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 1016 * initialization. 1017 */ 1018#define FLR_WAIT_USEC 10000 /* 10 miliseconds */ 1019#define FLR_WAIT_INTERVAL 50 /* usec */ 1020#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ 1021 1022struct pbf_pN_buf_regs { 1023 int pN; 1024 u32 init_crd; 1025 u32 crd; 1026 u32 crd_freed; 1027}; 1028 1029struct pbf_pN_cmd_regs { 1030 int pN; 1031 u32 lines_occup; 1032 u32 lines_freed; 1033}; 1034 1035static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1036 struct pbf_pN_buf_regs *regs, 1037 u32 poll_count) 1038{ 1039 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1040 u32 cur_cnt = poll_count; 1041 1042 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1043 crd = crd_start = REG_RD(bp, regs->crd); 1044 init_crd = REG_RD(bp, regs->init_crd); 1045 1046 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1047 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1048 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1049 1050 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1051 (init_crd - crd_start))) { 1052 if (cur_cnt--) { 1053 udelay(FLR_WAIT_INTERVAL); 1054 crd = REG_RD(bp, regs->crd); 1055 crd_freed = REG_RD(bp, regs->crd_freed); 1056 } else { 1057 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1058 regs->pN); 1059 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1060 regs->pN, crd); 1061 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1062 regs->pN, crd_freed); 1063 break; 1064 } 1065 } 1066 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1067 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1068} 1069 1070static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1071 struct pbf_pN_cmd_regs *regs, 1072 u32 poll_count) 1073{ 1074 u32 occup, to_free, freed, freed_start; 1075 u32 cur_cnt = poll_count; 1076 1077 occup = to_free = REG_RD(bp, regs->lines_occup); 1078 freed = freed_start = REG_RD(bp, regs->lines_freed); 1079 1080 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1081 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1082 1083 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1084 if (cur_cnt--) { 1085 udelay(FLR_WAIT_INTERVAL); 1086 occup = REG_RD(bp, regs->lines_occup); 1087 freed = REG_RD(bp, regs->lines_freed); 1088 } else { 1089 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1090 regs->pN); 1091 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1092 regs->pN, occup); 1093 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1094 regs->pN, freed); 1095 break; 1096 } 1097 } 1098 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1099 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1100} 1101 1102static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1103 u32 expected, u32 poll_count) 1104{ 1105 u32 cur_cnt = poll_count; 1106 u32 val; 1107 1108 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1109 udelay(FLR_WAIT_INTERVAL); 1110 1111 return val; 1112} 1113 1114static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1115 char *msg, u32 poll_cnt) 1116{ 1117 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1118 if (val != 0) { 1119 BNX2X_ERR("%s usage count=%d\n", msg, val); 1120 return 1; 1121 } 1122 return 0; 1123} 1124 1125static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1126{ 1127 /* adjust polling timeout */ 1128 if (CHIP_REV_IS_EMUL(bp)) 1129 return FLR_POLL_CNT * 2000; 1130 1131 if (CHIP_REV_IS_FPGA(bp)) 1132 return FLR_POLL_CNT * 120; 1133 1134 return FLR_POLL_CNT; 1135} 1136 1137static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1138{ 1139 struct pbf_pN_cmd_regs cmd_regs[] = { 1140 {0, (CHIP_IS_E3B0(bp)) ? 1141 PBF_REG_TQ_OCCUPANCY_Q0 : 1142 PBF_REG_P0_TQ_OCCUPANCY, 1143 (CHIP_IS_E3B0(bp)) ? 1144 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1145 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1146 {1, (CHIP_IS_E3B0(bp)) ? 1147 PBF_REG_TQ_OCCUPANCY_Q1 : 1148 PBF_REG_P1_TQ_OCCUPANCY, 1149 (CHIP_IS_E3B0(bp)) ? 1150 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1151 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1152 {4, (CHIP_IS_E3B0(bp)) ? 1153 PBF_REG_TQ_OCCUPANCY_LB_Q : 1154 PBF_REG_P4_TQ_OCCUPANCY, 1155 (CHIP_IS_E3B0(bp)) ? 1156 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1157 PBF_REG_P4_TQ_LINES_FREED_CNT} 1158 }; 1159 1160 struct pbf_pN_buf_regs buf_regs[] = { 1161 {0, (CHIP_IS_E3B0(bp)) ? 1162 PBF_REG_INIT_CRD_Q0 : 1163 PBF_REG_P0_INIT_CRD , 1164 (CHIP_IS_E3B0(bp)) ? 1165 PBF_REG_CREDIT_Q0 : 1166 PBF_REG_P0_CREDIT, 1167 (CHIP_IS_E3B0(bp)) ? 1168 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1169 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1170 {1, (CHIP_IS_E3B0(bp)) ? 1171 PBF_REG_INIT_CRD_Q1 : 1172 PBF_REG_P1_INIT_CRD, 1173 (CHIP_IS_E3B0(bp)) ? 1174 PBF_REG_CREDIT_Q1 : 1175 PBF_REG_P1_CREDIT, 1176 (CHIP_IS_E3B0(bp)) ? 1177 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1178 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1179 {4, (CHIP_IS_E3B0(bp)) ? 1180 PBF_REG_INIT_CRD_LB_Q : 1181 PBF_REG_P4_INIT_CRD, 1182 (CHIP_IS_E3B0(bp)) ? 1183 PBF_REG_CREDIT_LB_Q : 1184 PBF_REG_P4_CREDIT, 1185 (CHIP_IS_E3B0(bp)) ? 1186 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1187 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1188 }; 1189 1190 int i; 1191 1192 /* Verify the command queues are flushed P0, P1, P4 */ 1193 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1194 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1195 1196 1197 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1198 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1199 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1200} 1201 1202#define OP_GEN_PARAM(param) \ 1203 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1204 1205#define OP_GEN_TYPE(type) \ 1206 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1207 1208#define OP_GEN_AGG_VECT(index) \ 1209 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1210 1211 1212static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, 1213 u32 poll_cnt) 1214{ 1215 struct sdm_op_gen op_gen = {0}; 1216 1217 u32 comp_addr = BAR_CSTRORM_INTMEM + 1218 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1219 int ret = 0; 1220 1221 if (REG_RD(bp, comp_addr)) { 1222 BNX2X_ERR("Cleanup complete was not 0 before sending\n"); 1223 return 1; 1224 } 1225 1226 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1227 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1228 op_gen.command |= OP_GEN_AGG_VECT(clnup_func); 1229 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1230 1231 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); 1232 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); 1233 1234 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1235 BNX2X_ERR("FW final cleanup did not succeed\n"); 1236 ret = 1; 1237 } 1238 /* Zero completion for nxt FLR */ 1239 REG_WR(bp, comp_addr, 0); 1240 1241 return ret; 1242} 1243 1244static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1245{ 1246 int pos; 1247 u16 status; 1248 1249 pos = pci_pcie_cap(dev); 1250 if (!pos) 1251 return false; 1252 1253 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 1254 return status & PCI_EXP_DEVSTA_TRPND; 1255} 1256 1257/* PF FLR specific routines 1258*/ 1259static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1260{ 1261 1262 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1263 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1264 CFC_REG_NUM_LCIDS_INSIDE_PF, 1265 "CFC PF usage counter timed out", 1266 poll_cnt)) 1267 return 1; 1268 1269 1270 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1271 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1272 DORQ_REG_PF_USAGE_CNT, 1273 "DQ PF usage counter timed out", 1274 poll_cnt)) 1275 return 1; 1276 1277 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1278 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1279 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1280 "QM PF usage counter timed out", 1281 poll_cnt)) 1282 return 1; 1283 1284 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1285 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1286 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1287 "Timers VNIC usage counter timed out", 1288 poll_cnt)) 1289 return 1; 1290 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1291 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1292 "Timers NUM_SCANS usage counter timed out", 1293 poll_cnt)) 1294 return 1; 1295 1296 /* Wait DMAE PF usage counter to zero */ 1297 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1298 dmae_reg_go_c[INIT_DMAE_C(bp)], 1299 "DMAE dommand register timed out", 1300 poll_cnt)) 1301 return 1; 1302 1303 return 0; 1304} 1305 1306static void bnx2x_hw_enable_status(struct bnx2x *bp) 1307{ 1308 u32 val; 1309 1310 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1311 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1312 1313 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1314 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1315 1316 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1317 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1318 1319 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1320 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1321 1322 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1323 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1324 1325 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1326 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1327 1328 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1329 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1330 1331 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1332 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1333 val); 1334} 1335 1336static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1337{ 1338 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1339 1340 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1341 1342 /* Re-enable PF target read access */ 1343 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1344 1345 /* Poll HW usage counters */ 1346 DP(BNX2X_MSG_SP, "Polling usage counters\n"); 1347 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1348 return -EBUSY; 1349 1350 /* Zero the igu 'trailing edge' and 'leading edge' */ 1351 1352 /* Send the FW cleanup command */ 1353 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1354 return -EBUSY; 1355 1356 /* ATC cleanup */ 1357 1358 /* Verify TX hw is flushed */ 1359 bnx2x_tx_hw_flushed(bp, poll_cnt); 1360 1361 /* Wait 100ms (not adjusted according to platform) */ 1362 msleep(100); 1363 1364 /* Verify no pending pci transactions */ 1365 if (bnx2x_is_pcie_pending(bp->pdev)) 1366 BNX2X_ERR("PCIE Transactions still pending\n"); 1367 1368 /* Debug */ 1369 bnx2x_hw_enable_status(bp); 1370 1371 /* 1372 * Master enable - Due to WB DMAE writes performed before this 1373 * register is re-initialized as part of the regular function init 1374 */ 1375 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1376 1377 return 0; 1378} 1379 1380static void bnx2x_hc_int_enable(struct bnx2x *bp) 1381{ 1382 int port = BP_PORT(bp); 1383 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1384 u32 val = REG_RD(bp, addr); 1385 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1386 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1387 1388 if (msix) { 1389 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1390 HC_CONFIG_0_REG_INT_LINE_EN_0); 1391 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1392 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1393 } else if (msi) { 1394 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1395 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1396 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1397 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1398 } else { 1399 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1400 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1401 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1402 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1403 1404 if (!CHIP_IS_E1(bp)) { 1405 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1406 val, port, addr); 1407 1408 REG_WR(bp, addr, val); 1409 1410 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1411 } 1412 } 1413 1414 if (CHIP_IS_E1(bp)) 1415 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1416 1417 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", 1418 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1419 1420 REG_WR(bp, addr, val); 1421 /* 1422 * Ensure that HC_CONFIG is written before leading/trailing edge config 1423 */ 1424 mmiowb(); 1425 barrier(); 1426 1427 if (!CHIP_IS_E1(bp)) { 1428 /* init leading/trailing edge */ 1429 if (IS_MF(bp)) { 1430 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1431 if (bp->port.pmf) 1432 /* enable nig and gpio3 attention */ 1433 val |= 0x1100; 1434 } else 1435 val = 0xffff; 1436 1437 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1438 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1439 } 1440 1441 /* Make sure that interrupts are indeed enabled from here on */ 1442 mmiowb(); 1443} 1444 1445static void bnx2x_igu_int_enable(struct bnx2x *bp) 1446{ 1447 u32 val; 1448 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1449 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1450 1451 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1452 1453 if (msix) { 1454 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1455 IGU_PF_CONF_SINGLE_ISR_EN); 1456 val |= (IGU_PF_CONF_FUNC_EN | 1457 IGU_PF_CONF_MSI_MSIX_EN | 1458 IGU_PF_CONF_ATTN_BIT_EN); 1459 } else if (msi) { 1460 val &= ~IGU_PF_CONF_INT_LINE_EN; 1461 val |= (IGU_PF_CONF_FUNC_EN | 1462 IGU_PF_CONF_MSI_MSIX_EN | 1463 IGU_PF_CONF_ATTN_BIT_EN | 1464 IGU_PF_CONF_SINGLE_ISR_EN); 1465 } else { 1466 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1467 val |= (IGU_PF_CONF_FUNC_EN | 1468 IGU_PF_CONF_INT_LINE_EN | 1469 IGU_PF_CONF_ATTN_BIT_EN | 1470 IGU_PF_CONF_SINGLE_ISR_EN); 1471 } 1472 1473 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n", 1474 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1475 1476 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1477 1478 barrier(); 1479 1480 /* init leading/trailing edge */ 1481 if (IS_MF(bp)) { 1482 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1483 if (bp->port.pmf) 1484 /* enable nig and gpio3 attention */ 1485 val |= 0x1100; 1486 } else 1487 val = 0xffff; 1488 1489 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1490 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1491 1492 /* Make sure that interrupts are indeed enabled from here on */ 1493 mmiowb(); 1494} 1495 1496void bnx2x_int_enable(struct bnx2x *bp) 1497{ 1498 if (bp->common.int_block == INT_BLOCK_HC) 1499 bnx2x_hc_int_enable(bp); 1500 else 1501 bnx2x_igu_int_enable(bp); 1502} 1503 1504static void bnx2x_hc_int_disable(struct bnx2x *bp) 1505{ 1506 int port = BP_PORT(bp); 1507 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1508 u32 val = REG_RD(bp, addr); 1509 1510 /* 1511 * in E1 we must use only PCI configuration space to disable 1512 * MSI/MSIX capablility 1513 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 1514 */ 1515 if (CHIP_IS_E1(bp)) { 1516 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 1517 * Use mask register to prevent from HC sending interrupts 1518 * after we exit the function 1519 */ 1520 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 1521 1522 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1523 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1524 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1525 } else 1526 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1527 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1528 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1529 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1530 1531 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1532 val, port, addr); 1533 1534 /* flush all outstanding writes */ 1535 mmiowb(); 1536 1537 REG_WR(bp, addr, val); 1538 if (REG_RD(bp, addr) != val) 1539 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1540} 1541 1542static void bnx2x_igu_int_disable(struct bnx2x *bp) 1543{ 1544 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1545 1546 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 1547 IGU_PF_CONF_INT_LINE_EN | 1548 IGU_PF_CONF_ATTN_BIT_EN); 1549 1550 DP(NETIF_MSG_INTR, "write %x to IGU\n", val); 1551 1552 /* flush all outstanding writes */ 1553 mmiowb(); 1554 1555 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1556 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 1557 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1558} 1559 1560void bnx2x_int_disable(struct bnx2x *bp) 1561{ 1562 if (bp->common.int_block == INT_BLOCK_HC) 1563 bnx2x_hc_int_disable(bp); 1564 else 1565 bnx2x_igu_int_disable(bp); 1566} 1567 1568void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1569{ 1570 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1571 int i, offset; 1572 1573 if (disable_hw) 1574 /* prevent the HW from sending interrupts */ 1575 bnx2x_int_disable(bp); 1576 1577 /* make sure all ISRs are done */ 1578 if (msix) { 1579 synchronize_irq(bp->msix_table[0].vector); 1580 offset = 1; 1581#ifdef BCM_CNIC 1582 offset++; 1583#endif 1584 for_each_eth_queue(bp, i) 1585 synchronize_irq(bp->msix_table[offset++].vector); 1586 } else 1587 synchronize_irq(bp->pdev->irq); 1588 1589 /* make sure sp_task is not running */ 1590 cancel_delayed_work(&bp->sp_task); 1591 cancel_delayed_work(&bp->period_task); 1592 flush_workqueue(bnx2x_wq); 1593} 1594 1595/* fast path */ 1596 1597/* 1598 * General service functions 1599 */ 1600 1601/* Return true if succeeded to acquire the lock */ 1602static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1603{ 1604 u32 lock_status; 1605 u32 resource_bit = (1 << resource); 1606 int func = BP_FUNC(bp); 1607 u32 hw_lock_control_reg; 1608 1609 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource); 1610 1611 /* Validating that the resource is within range */ 1612 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1613 DP(NETIF_MSG_HW, 1614 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1615 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1616 return false; 1617 } 1618 1619 if (func <= 5) 1620 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1621 else 1622 hw_lock_control_reg = 1623 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1624 1625 /* Try to acquire the lock */ 1626 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1627 lock_status = REG_RD(bp, hw_lock_control_reg); 1628 if (lock_status & resource_bit) 1629 return true; 1630 1631 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource); 1632 return false; 1633} 1634 1635/** 1636 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1637 * 1638 * @bp: driver handle 1639 * 1640 * Returns the recovery leader resource id according to the engine this function 1641 * belongs to. Currently only only 2 engines is supported. 1642 */ 1643static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1644{ 1645 if (BP_PATH(bp)) 1646 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1647 else 1648 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1649} 1650 1651/** 1652 * bnx2x_trylock_leader_lock- try to aquire a leader lock. 1653 * 1654 * @bp: driver handle 1655 * 1656 * Tries to aquire a leader lock for cuurent engine. 1657 */ 1658static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1659{ 1660 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1661} 1662 1663#ifdef BCM_CNIC 1664static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1665#endif 1666 1667void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1668{ 1669 struct bnx2x *bp = fp->bp; 1670 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1671 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1672 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1673 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj; 1674 1675 DP(BNX2X_MSG_SP, 1676 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1677 fp->index, cid, command, bp->state, 1678 rr_cqe->ramrod_cqe.ramrod_type); 1679 1680 switch (command) { 1681 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1682 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1683 drv_cmd = BNX2X_Q_CMD_UPDATE; 1684 break; 1685 1686 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1687 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1688 drv_cmd = BNX2X_Q_CMD_SETUP; 1689 break; 1690 1691 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1692 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1693 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1694 break; 1695 1696 case (RAMROD_CMD_ID_ETH_HALT): 1697 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1698 drv_cmd = BNX2X_Q_CMD_HALT; 1699 break; 1700 1701 case (RAMROD_CMD_ID_ETH_TERMINATE): 1702 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); 1703 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1704 break; 1705 1706 case (RAMROD_CMD_ID_ETH_EMPTY): 1707 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1708 drv_cmd = BNX2X_Q_CMD_EMPTY; 1709 break; 1710 1711 default: 1712 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1713 command, fp->index); 1714 return; 1715 } 1716 1717 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1718 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1719 /* q_obj->complete_cmd() failure means that this was 1720 * an unexpected completion. 1721 * 1722 * In this case we don't want to increase the bp->spq_left 1723 * because apparently we haven't sent this command the first 1724 * place. 1725 */ 1726#ifdef BNX2X_STOP_ON_ERROR 1727 bnx2x_panic(); 1728#else 1729 return; 1730#endif 1731 1732 smp_mb__before_atomic_inc(); 1733 atomic_inc(&bp->cq_spq_left); 1734 /* push the change in bp->spq_left and towards the memory */ 1735 smp_mb__after_atomic_inc(); 1736 1737 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1738 1739 return; 1740} 1741 1742void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 1743 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) 1744{ 1745 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; 1746 1747 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, 1748 start); 1749} 1750 1751irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1752{ 1753 struct bnx2x *bp = netdev_priv(dev_instance); 1754 u16 status = bnx2x_ack_int(bp); 1755 u16 mask; 1756 int i; 1757 u8 cos; 1758 1759 /* Return here if interrupt is shared and it's not for us */ 1760 if (unlikely(status == 0)) { 1761 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1762 return IRQ_NONE; 1763 } 1764 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1765 1766#ifdef BNX2X_STOP_ON_ERROR 1767 if (unlikely(bp->panic)) 1768 return IRQ_HANDLED; 1769#endif 1770 1771 for_each_eth_queue(bp, i) { 1772 struct bnx2x_fastpath *fp = &bp->fp[i]; 1773 1774 mask = 0x2 << (fp->index + CNIC_PRESENT); 1775 if (status & mask) { 1776 /* Handle Rx or Tx according to SB id */ 1777 prefetch(fp->rx_cons_sb); 1778 for_each_cos_in_tx_queue(fp, cos) 1779 prefetch(fp->txdata[cos].tx_cons_sb); 1780 prefetch(&fp->sb_running_index[SM_RX_ID]); 1781 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 1782 status &= ~mask; 1783 } 1784 } 1785 1786#ifdef BCM_CNIC 1787 mask = 0x2; 1788 if (status & (mask | 0x1)) { 1789 struct cnic_ops *c_ops = NULL; 1790 1791 if (likely(bp->state == BNX2X_STATE_OPEN)) { 1792 rcu_read_lock(); 1793 c_ops = rcu_dereference(bp->cnic_ops); 1794 if (c_ops) 1795 c_ops->cnic_handler(bp->cnic_data, NULL); 1796 rcu_read_unlock(); 1797 } 1798 1799 status &= ~mask; 1800 } 1801#endif 1802 1803 if (unlikely(status & 0x1)) { 1804 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1805 1806 status &= ~0x1; 1807 if (!status) 1808 return IRQ_HANDLED; 1809 } 1810 1811 if (unlikely(status)) 1812 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1813 status); 1814 1815 return IRQ_HANDLED; 1816} 1817 1818/* Link */ 1819 1820/* 1821 * General service functions 1822 */ 1823 1824int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 1825{ 1826 u32 lock_status; 1827 u32 resource_bit = (1 << resource); 1828 int func = BP_FUNC(bp); 1829 u32 hw_lock_control_reg; 1830 int cnt; 1831 1832 /* Validating that the resource is within range */ 1833 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1834 DP(NETIF_MSG_HW, 1835 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1836 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1837 return -EINVAL; 1838 } 1839 1840 if (func <= 5) { 1841 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1842 } else { 1843 hw_lock_control_reg = 1844 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1845 } 1846 1847 /* Validating that the resource is not already taken */ 1848 lock_status = REG_RD(bp, hw_lock_control_reg); 1849 if (lock_status & resource_bit) { 1850 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1851 lock_status, resource_bit); 1852 return -EEXIST; 1853 } 1854 1855 /* Try for 5 second every 5ms */ 1856 for (cnt = 0; cnt < 1000; cnt++) { 1857 /* Try to acquire the lock */ 1858 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1859 lock_status = REG_RD(bp, hw_lock_control_reg); 1860 if (lock_status & resource_bit) 1861 return 0; 1862 1863 msleep(5); 1864 } 1865 DP(NETIF_MSG_HW, "Timeout\n"); 1866 return -EAGAIN; 1867} 1868 1869int bnx2x_release_leader_lock(struct bnx2x *bp) 1870{ 1871 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1872} 1873 1874int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 1875{ 1876 u32 lock_status; 1877 u32 resource_bit = (1 << resource); 1878 int func = BP_FUNC(bp); 1879 u32 hw_lock_control_reg; 1880 1881 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource); 1882 1883 /* Validating that the resource is within range */ 1884 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1885 DP(NETIF_MSG_HW, 1886 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1887 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1888 return -EINVAL; 1889 } 1890 1891 if (func <= 5) { 1892 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1893 } else { 1894 hw_lock_control_reg = 1895 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1896 } 1897 1898 /* Validating that the resource is currently taken */ 1899 lock_status = REG_RD(bp, hw_lock_control_reg); 1900 if (!(lock_status & resource_bit)) { 1901 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1902 lock_status, resource_bit); 1903 return -EFAULT; 1904 } 1905 1906 REG_WR(bp, hw_lock_control_reg, resource_bit); 1907 return 0; 1908} 1909 1910 1911int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 1912{ 1913 /* The GPIO should be swapped if swap register is set and active */ 1914 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1915 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1916 int gpio_shift = gpio_num + 1917 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1918 u32 gpio_mask = (1 << gpio_shift); 1919 u32 gpio_reg; 1920 int value; 1921 1922 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1923 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1924 return -EINVAL; 1925 } 1926 1927 /* read GPIO value */ 1928 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1929 1930 /* get the requested pin value */ 1931 if ((gpio_reg & gpio_mask) == gpio_mask) 1932 value = 1; 1933 else 1934 value = 0; 1935 1936 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); 1937 1938 return value; 1939} 1940 1941int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 1942{ 1943 /* The GPIO should be swapped if swap register is set and active */ 1944 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1945 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1946 int gpio_shift = gpio_num + 1947 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1948 u32 gpio_mask = (1 << gpio_shift); 1949 u32 gpio_reg; 1950 1951 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1952 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1953 return -EINVAL; 1954 } 1955 1956 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1957 /* read GPIO and mask except the float bits */ 1958 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 1959 1960 switch (mode) { 1961 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1962 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n", 1963 gpio_num, gpio_shift); 1964 /* clear FLOAT and set CLR */ 1965 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1966 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 1967 break; 1968 1969 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 1970 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n", 1971 gpio_num, gpio_shift); 1972 /* clear FLOAT and set SET */ 1973 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1974 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 1975 break; 1976 1977 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 1978 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", 1979 gpio_num, gpio_shift); 1980 /* set FLOAT */ 1981 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1982 break; 1983 1984 default: 1985 break; 1986 } 1987 1988 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 1989 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1990 1991 return 0; 1992} 1993 1994int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 1995{ 1996 u32 gpio_reg = 0; 1997 int rc = 0; 1998 1999 /* Any port swapping should be handled by caller. */ 2000 2001 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2002 /* read GPIO and mask except the float bits */ 2003 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 2004 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2005 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 2006 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 2007 2008 switch (mode) { 2009 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2010 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 2011 /* set CLR */ 2012 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2013 break; 2014 2015 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2016 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 2017 /* set SET */ 2018 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2019 break; 2020 2021 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2022 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2023 /* set FLOAT */ 2024 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2025 break; 2026 2027 default: 2028 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2029 rc = -EINVAL; 2030 break; 2031 } 2032 2033 if (rc == 0) 2034 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2035 2036 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2037 2038 return rc; 2039} 2040 2041int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2042{ 2043 /* The GPIO should be swapped if swap register is set and active */ 2044 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2045 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2046 int gpio_shift = gpio_num + 2047 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2048 u32 gpio_mask = (1 << gpio_shift); 2049 u32 gpio_reg; 2050 2051 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2052 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2053 return -EINVAL; 2054 } 2055 2056 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2057 /* read GPIO int */ 2058 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2059 2060 switch (mode) { 2061 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2062 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> " 2063 "output low\n", gpio_num, gpio_shift); 2064 /* clear SET and set CLR */ 2065 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2066 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2067 break; 2068 2069 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2070 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> " 2071 "output high\n", gpio_num, gpio_shift); 2072 /* clear CLR and set SET */ 2073 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2074 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2075 break; 2076 2077 default: 2078 break; 2079 } 2080 2081 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2082 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2083 2084 return 0; 2085} 2086 2087static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) 2088{ 2089 u32 spio_mask = (1 << spio_num); 2090 u32 spio_reg; 2091 2092 if ((spio_num < MISC_REGISTERS_SPIO_4) || 2093 (spio_num > MISC_REGISTERS_SPIO_7)) { 2094 BNX2X_ERR("Invalid SPIO %d\n", spio_num); 2095 return -EINVAL; 2096 } 2097 2098 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2099 /* read SPIO and mask except the float bits */ 2100 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); 2101 2102 switch (mode) { 2103 case MISC_REGISTERS_SPIO_OUTPUT_LOW: 2104 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); 2105 /* clear FLOAT and set CLR */ 2106 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2107 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); 2108 break; 2109 2110 case MISC_REGISTERS_SPIO_OUTPUT_HIGH: 2111 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); 2112 /* clear FLOAT and set SET */ 2113 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2114 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); 2115 break; 2116 2117 case MISC_REGISTERS_SPIO_INPUT_HI_Z: 2118 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num); 2119 /* set FLOAT */ 2120 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2121 break; 2122 2123 default: 2124 break; 2125 } 2126 2127 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2128 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2129 2130 return 0; 2131} 2132 2133void bnx2x_calc_fc_adv(struct bnx2x *bp) 2134{ 2135 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2136 switch (bp->link_vars.ieee_fc & 2137 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2138 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 2139 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2140 ADVERTISED_Pause); 2141 break; 2142 2143 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2144 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2145 ADVERTISED_Pause); 2146 break; 2147 2148 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2149 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2150 break; 2151 2152 default: 2153 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2154 ADVERTISED_Pause); 2155 break; 2156 } 2157} 2158 2159u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2160{ 2161 if (!BP_NOMCP(bp)) { 2162 u8 rc; 2163 int cfx_idx = bnx2x_get_link_cfg_idx(bp); 2164 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2165 /* 2166 * Initialize link parameters structure variables 2167 * It is recommended to turn off RX FC for jumbo frames 2168 * for better performance 2169 */ 2170 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2171 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2172 else 2173 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2174 2175 bnx2x_acquire_phy_lock(bp); 2176 2177 if (load_mode == LOAD_DIAG) { 2178 struct link_params *lp = &bp->link_params; 2179 lp->loopback_mode = LOOPBACK_XGXS; 2180 /* do PHY loopback at 10G speed, if possible */ 2181 if (lp->req_line_speed[cfx_idx] < SPEED_10000) { 2182 if (lp->speed_cap_mask[cfx_idx] & 2183 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2184 lp->req_line_speed[cfx_idx] = 2185 SPEED_10000; 2186 else 2187 lp->req_line_speed[cfx_idx] = 2188 SPEED_1000; 2189 } 2190 } 2191 2192 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2193 2194 bnx2x_release_phy_lock(bp); 2195 2196 bnx2x_calc_fc_adv(bp); 2197 2198 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { 2199 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2200 bnx2x_link_report(bp); 2201 } else 2202 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2203 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2204 return rc; 2205 } 2206 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2207 return -EINVAL; 2208} 2209 2210void bnx2x_link_set(struct bnx2x *bp) 2211{ 2212 if (!BP_NOMCP(bp)) { 2213 bnx2x_acquire_phy_lock(bp); 2214 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2215 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2216 bnx2x_release_phy_lock(bp); 2217 2218 bnx2x_calc_fc_adv(bp); 2219 } else 2220 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2221} 2222 2223static void bnx2x__link_reset(struct bnx2x *bp) 2224{ 2225 if (!BP_NOMCP(bp)) { 2226 bnx2x_acquire_phy_lock(bp); 2227 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2228 bnx2x_release_phy_lock(bp); 2229 } else 2230 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2231} 2232 2233u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2234{ 2235 u8 rc = 0; 2236 2237 if (!BP_NOMCP(bp)) { 2238 bnx2x_acquire_phy_lock(bp); 2239 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2240 is_serdes); 2241 bnx2x_release_phy_lock(bp); 2242 } else 2243 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2244 2245 return rc; 2246} 2247 2248static void bnx2x_init_port_minmax(struct bnx2x *bp) 2249{ 2250 u32 r_param = bp->link_vars.line_speed / 8; 2251 u32 fair_periodic_timeout_usec; 2252 u32 t_fair; 2253 2254 memset(&(bp->cmng.rs_vars), 0, 2255 sizeof(struct rate_shaping_vars_per_port)); 2256 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port)); 2257 2258 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ 2259 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4; 2260 2261 /* this is the threshold below which no timer arming will occur 2262 1.25 coefficient is for the threshold to be a little bigger 2263 than the real time, to compensate for timer in-accuracy */ 2264 bp->cmng.rs_vars.rs_threshold = 2265 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; 2266 2267 /* resolution of fairness timer */ 2268 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; 2269 /* for 10G it is 1000usec. for 1G it is 10000usec. */ 2270 t_fair = T_FAIR_COEF / bp->link_vars.line_speed; 2271 2272 /* this is the threshold below which we won't arm the timer anymore */ 2273 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES; 2274 2275 /* we multiply by 1e3/8 to get bytes/msec. 2276 We don't want the credits to pass a credit 2277 of the t_fair*FAIR_MEM (algorithm resolution) */ 2278 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM; 2279 /* since each tick is 4 usec */ 2280 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4; 2281} 2282 2283/* Calculates the sum of vn_min_rates. 2284 It's needed for further normalizing of the min_rates. 2285 Returns: 2286 sum of vn_min_rates. 2287 or 2288 0 - if all the min_rates are 0. 2289 In the later case fainess algorithm should be deactivated. 2290 If not all min_rates are zero then those that are zeroes will be set to 1. 2291 */ 2292static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) 2293{ 2294 int all_zero = 1; 2295 int vn; 2296 2297 bp->vn_weight_sum = 0; 2298 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2299 u32 vn_cfg = bp->mf_config[vn]; 2300 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2301 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2302 2303 /* Skip hidden vns */ 2304 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2305 continue; 2306 2307 /* If min rate is zero - set it to 1 */ 2308 if (!vn_min_rate) 2309 vn_min_rate = DEF_MIN_RATE; 2310 else 2311 all_zero = 0; 2312 2313 bp->vn_weight_sum += vn_min_rate; 2314 } 2315 2316 /* if ETS or all min rates are zeros - disable fairness */ 2317 if (BNX2X_IS_ETS_ENABLED(bp)) { 2318 bp->cmng.flags.cmng_enables &= 2319 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2320 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2321 } else if (all_zero) { 2322 bp->cmng.flags.cmng_enables &= 2323 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2324 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2325 " fairness will be disabled\n"); 2326 } else 2327 bp->cmng.flags.cmng_enables |= 2328 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2329} 2330 2331static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) 2332{ 2333 struct rate_shaping_vars_per_vn m_rs_vn; 2334 struct fairness_vars_per_vn m_fair_vn; 2335 u32 vn_cfg = bp->mf_config[vn]; 2336 int func = func_by_vn(bp, vn); 2337 u16 vn_min_rate, vn_max_rate; 2338 int i; 2339 2340 /* If function is hidden - set min and max to zeroes */ 2341 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 2342 vn_min_rate = 0; 2343 vn_max_rate = 0; 2344 2345 } else { 2346 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2347 2348 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2349 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2350 /* If fairness is enabled (not all min rates are zeroes) and 2351 if current min rate is zero - set it to 1. 2352 This is a requirement of the algorithm. */ 2353 if (bp->vn_weight_sum && (vn_min_rate == 0)) 2354 vn_min_rate = DEF_MIN_RATE; 2355 2356 if (IS_MF_SI(bp)) 2357 /* maxCfg in percents of linkspeed */ 2358 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2359 else 2360 /* maxCfg is absolute in 100Mb units */ 2361 vn_max_rate = maxCfg * 100; 2362 } 2363 2364 DP(NETIF_MSG_IFUP, 2365 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n", 2366 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); 2367 2368 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn)); 2369 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); 2370 2371 /* global vn counter - maximal Mbps for this vn */ 2372 m_rs_vn.vn_counter.rate = vn_max_rate; 2373 2374 /* quota - number of bytes transmitted in this period */ 2375 m_rs_vn.vn_counter.quota = 2376 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8; 2377 2378 if (bp->vn_weight_sum) { 2379 /* credit for each period of the fairness algorithm: 2380 number of bytes in T_FAIR (the vn share the port rate). 2381 vn_weight_sum should not be larger than 10000, thus 2382 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater 2383 than zero */ 2384 m_fair_vn.vn_credit_delta = 2385 max_t(u32, (vn_min_rate * (T_FAIR_COEF / 2386 (8 * bp->vn_weight_sum))), 2387 (bp->cmng.fair_vars.fair_threshold + 2388 MIN_ABOVE_THRESH)); 2389 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n", 2390 m_fair_vn.vn_credit_delta); 2391 } 2392 2393 /* Store it to internal memory */ 2394 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++) 2395 REG_WR(bp, BAR_XSTRORM_INTMEM + 2396 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4, 2397 ((u32 *)(&m_rs_vn))[i]); 2398 2399 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++) 2400 REG_WR(bp, BAR_XSTRORM_INTMEM + 2401 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4, 2402 ((u32 *)(&m_fair_vn))[i]); 2403} 2404 2405static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2406{ 2407 if (CHIP_REV_IS_SLOW(bp)) 2408 return CMNG_FNS_NONE; 2409 if (IS_MF(bp)) 2410 return CMNG_FNS_MINMAX; 2411 2412 return CMNG_FNS_NONE; 2413} 2414 2415void bnx2x_read_mf_cfg(struct bnx2x *bp) 2416{ 2417 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2418 2419 if (BP_NOMCP(bp)) 2420 return; /* what should be the default bvalue in this case */ 2421 2422 /* For 2 port configuration the absolute function number formula 2423 * is: 2424 * abs_func = 2 * vn + BP_PORT + BP_PATH 2425 * 2426 * and there are 4 functions per port 2427 * 2428 * For 4 port configuration it is 2429 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2430 * 2431 * and there are 2 functions per port 2432 */ 2433 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2434 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2435 2436 if (func >= E1H_FUNC_MAX) 2437 break; 2438 2439 bp->mf_config[vn] = 2440 MF_CFG_RD(bp, func_mf_config[func].config); 2441 } 2442} 2443 2444static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2445{ 2446 2447 if (cmng_type == CMNG_FNS_MINMAX) { 2448 int vn; 2449 2450 /* clear cmng_enables */ 2451 bp->cmng.flags.cmng_enables = 0; 2452 2453 /* read mf conf from shmem */ 2454 if (read_cfg) 2455 bnx2x_read_mf_cfg(bp); 2456 2457 /* Init rate shaping and fairness contexts */ 2458 bnx2x_init_port_minmax(bp); 2459 2460 /* vn_weight_sum and enable fairness if not 0 */ 2461 bnx2x_calc_vn_weight_sum(bp); 2462 2463 /* calculate and set min-max rate for each vn */ 2464 if (bp->port.pmf) 2465 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) 2466 bnx2x_init_vn_minmax(bp, vn); 2467 2468 /* always enable rate shaping and fairness */ 2469 bp->cmng.flags.cmng_enables |= 2470 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2471 if (!bp->vn_weight_sum) 2472 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2473 " fairness will be disabled\n"); 2474 return; 2475 } 2476 2477 /* rate shaping and fairness are disabled */ 2478 DP(NETIF_MSG_IFUP, 2479 "rate shaping and fairness are disabled\n"); 2480} 2481 2482/* This function is called upon link interrupt */ 2483static void bnx2x_link_attn(struct bnx2x *bp) 2484{ 2485 /* Make sure that we are synced with the current statistics */ 2486 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2487 2488 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2489 2490 if (bp->link_vars.link_up) { 2491 2492 /* dropless flow control */ 2493 if (!CHIP_IS_E1(bp) && bp->dropless_fc) { 2494 int port = BP_PORT(bp); 2495 u32 pause_enabled = 0; 2496 2497 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2498 pause_enabled = 1; 2499 2500 REG_WR(bp, BAR_USTRORM_INTMEM + 2501 USTORM_ETH_PAUSE_ENABLED_OFFSET(port), 2502 pause_enabled); 2503 } 2504 2505 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2506 struct host_port_stats *pstats; 2507 2508 pstats = bnx2x_sp(bp, port_stats); 2509 /* reset old mac stats */ 2510 memset(&(pstats->mac_stx[0]), 0, 2511 sizeof(struct mac_stx)); 2512 } 2513 if (bp->state == BNX2X_STATE_OPEN) 2514 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2515 } 2516 2517 if (bp->link_vars.link_up && bp->link_vars.line_speed) { 2518 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2519 2520 if (cmng_fns != CMNG_FNS_NONE) { 2521 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2522 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2523 } else 2524 /* rate shaping and fairness are disabled */ 2525 DP(NETIF_MSG_IFUP, 2526 "single function mode without fairness\n"); 2527 } 2528 2529 __bnx2x_link_report(bp); 2530 2531 if (IS_MF(bp)) 2532 bnx2x_link_sync_notify(bp); 2533} 2534 2535void bnx2x__link_status_update(struct bnx2x *bp) 2536{ 2537 if (bp->state != BNX2X_STATE_OPEN) 2538 return; 2539 2540 /* read updated dcb configuration */ 2541 bnx2x_dcbx_pmf_update(bp); 2542 2543 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2544 2545 if (bp->link_vars.link_up) 2546 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2547 else 2548 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2549 2550 /* indicate link status */ 2551 bnx2x_link_report(bp); 2552} 2553 2554static void bnx2x_pmf_update(struct bnx2x *bp) 2555{ 2556 int port = BP_PORT(bp); 2557 u32 val; 2558 2559 bp->port.pmf = 1; 2560 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf); 2561 2562 /* 2563 * We need the mb() to ensure the ordering between the writing to 2564 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2565 */ 2566 smp_mb(); 2567 2568 /* queue a periodic task */ 2569 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2570 2571 bnx2x_dcbx_pmf_update(bp); 2572 2573 /* enable nig attention */ 2574 val = (0xff0f | (1 << (BP_VN(bp) + 4))); 2575 if (bp->common.int_block == INT_BLOCK_HC) { 2576 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 2577 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 2578 } else if (!CHIP_IS_E1x(bp)) { 2579 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 2580 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 2581 } 2582 2583 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 2584} 2585 2586/* end of Link */ 2587 2588/* slow path */ 2589 2590/* 2591 * General service functions 2592 */ 2593 2594/* send the MCP a request, block until there is a reply */ 2595u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 2596{ 2597 int mb_idx = BP_FW_MB_IDX(bp); 2598 u32 seq; 2599 u32 rc = 0; 2600 u32 cnt = 1; 2601 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 2602 2603 mutex_lock(&bp->fw_mb_mutex); 2604 seq = ++bp->fw_seq; 2605 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 2606 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 2607 2608 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 2609 (command | seq), param); 2610 2611 do { 2612 /* let the FW do it's magic ... */ 2613 msleep(delay); 2614 2615 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 2616 2617 /* Give the FW up to 5 second (500*10ms) */ 2618 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2619 2620 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 2621 cnt*delay, rc, seq); 2622 2623 /* is this a reply to our command? */ 2624 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 2625 rc &= FW_MSG_CODE_MASK; 2626 else { 2627 /* FW BUG! */ 2628 BNX2X_ERR("FW failed to respond!\n"); 2629 bnx2x_fw_dump(bp); 2630 rc = 0; 2631 } 2632 mutex_unlock(&bp->fw_mb_mutex); 2633 2634 return rc; 2635} 2636 2637 2638void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 2639{ 2640 if (CHIP_IS_E1x(bp)) { 2641 struct tstorm_eth_function_common_config tcfg = {0}; 2642 2643 storm_memset_func_cfg(bp, &tcfg, p->func_id); 2644 } 2645 2646 /* Enable the function in the FW */ 2647 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 2648 storm_memset_func_en(bp, p->func_id, 1); 2649 2650 /* spq */ 2651 if (p->func_flgs & FUNC_FLG_SPQ) { 2652 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 2653 REG_WR(bp, XSEM_REG_FAST_MEMORY + 2654 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 2655 } 2656} 2657 2658/** 2659 * bnx2x_get_tx_only_flags - Return common flags 2660 * 2661 * @bp device handle 2662 * @fp queue handle 2663 * @zero_stats TRUE if statistics zeroing is needed 2664 * 2665 * Return the flags that are common for the Tx-only and not normal connections. 2666 */ 2667static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 2668 struct bnx2x_fastpath *fp, 2669 bool zero_stats) 2670{ 2671 unsigned long flags = 0; 2672 2673 /* PF driver will always initialize the Queue to an ACTIVE state */ 2674 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 2675 2676 /* tx only connections collect statistics (on the same index as the 2677 * parent connection). The statistics are zeroed when the parent 2678 * connection is initialized. 2679 */ 2680 2681 __set_bit(BNX2X_Q_FLG_STATS, &flags); 2682 if (zero_stats) 2683 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 2684 2685 2686 return flags; 2687} 2688 2689static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 2690 struct bnx2x_fastpath *fp, 2691 bool leading) 2692{ 2693 unsigned long flags = 0; 2694 2695 /* calculate other queue flags */ 2696 if (IS_MF_SD(bp)) 2697 __set_bit(BNX2X_Q_FLG_OV, &flags); 2698 2699 if (IS_FCOE_FP(fp)) 2700 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 2701 2702 if (!fp->disable_tpa) { 2703 __set_bit(BNX2X_Q_FLG_TPA, &flags); 2704 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 2705 if (fp->mode == TPA_MODE_GRO) 2706 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); 2707 } 2708 2709 if (leading) { 2710 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 2711 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 2712 } 2713 2714 /* Always set HW VLAN stripping */ 2715 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 2716 2717 2718 return flags | bnx2x_get_common_flags(bp, fp, true); 2719} 2720 2721static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 2722 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 2723 u8 cos) 2724{ 2725 gen_init->stat_id = bnx2x_stats_id(fp); 2726 gen_init->spcl_id = fp->cl_id; 2727 2728 /* Always use mini-jumbo MTU for FCoE L2 ring */ 2729 if (IS_FCOE_FP(fp)) 2730 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 2731 else 2732 gen_init->mtu = bp->dev->mtu; 2733 2734 gen_init->cos = cos; 2735} 2736 2737static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 2738 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 2739 struct bnx2x_rxq_setup_params *rxq_init) 2740{ 2741 u8 max_sge = 0; 2742 u16 sge_sz = 0; 2743 u16 tpa_agg_size = 0; 2744 2745 if (!fp->disable_tpa) { 2746 pause->sge_th_lo = SGE_TH_LO(bp); 2747 pause->sge_th_hi = SGE_TH_HI(bp); 2748 2749 /* validate SGE ring has enough to cross high threshold */ 2750 WARN_ON(bp->dropless_fc && 2751 pause->sge_th_hi + FW_PREFETCH_CNT > 2752 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); 2753 2754 tpa_agg_size = min_t(u32, 2755 (min_t(u32, 8, MAX_SKB_FRAGS) * 2756 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); 2757 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 2758 SGE_PAGE_SHIFT; 2759 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 2760 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 2761 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, 2762 0xffff); 2763 } 2764 2765 /* pause - not for e1 */ 2766 if (!CHIP_IS_E1(bp)) { 2767 pause->bd_th_lo = BD_TH_LO(bp); 2768 pause->bd_th_hi = BD_TH_HI(bp); 2769 2770 pause->rcq_th_lo = RCQ_TH_LO(bp); 2771 pause->rcq_th_hi = RCQ_TH_HI(bp); 2772 /* 2773 * validate that rings have enough entries to cross 2774 * high thresholds 2775 */ 2776 WARN_ON(bp->dropless_fc && 2777 pause->bd_th_hi + FW_PREFETCH_CNT > 2778 bp->rx_ring_size); 2779 WARN_ON(bp->dropless_fc && 2780 pause->rcq_th_hi + FW_PREFETCH_CNT > 2781 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); 2782 2783 pause->pri_map = 1; 2784 } 2785 2786 /* rxq setup */ 2787 rxq_init->dscr_map = fp->rx_desc_mapping; 2788 rxq_init->sge_map = fp->rx_sge_mapping; 2789 rxq_init->rcq_map = fp->rx_comp_mapping; 2790 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 2791 2792 /* This should be a maximum number of data bytes that may be 2793 * placed on the BD (not including paddings). 2794 */ 2795 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - 2796 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; 2797 2798 rxq_init->cl_qzone_id = fp->cl_qzone_id; 2799 rxq_init->tpa_agg_sz = tpa_agg_size; 2800 rxq_init->sge_buf_sz = sge_sz; 2801 rxq_init->max_sges_pkt = max_sge; 2802 rxq_init->rss_engine_id = BP_FUNC(bp); 2803 2804 /* Maximum number or simultaneous TPA aggregation for this Queue. 2805 * 2806 * For PF Clients it should be the maximum avaliable number. 2807 * VF driver(s) may want to define it to a smaller value. 2808 */ 2809 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); 2810 2811 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 2812 rxq_init->fw_sb_id = fp->fw_sb_id; 2813 2814 if (IS_FCOE_FP(fp)) 2815 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 2816 else 2817 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 2818} 2819 2820static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 2821 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 2822 u8 cos) 2823{ 2824 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping; 2825 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 2826 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 2827 txq_init->fw_sb_id = fp->fw_sb_id; 2828 2829 /* 2830 * set the tss leading client id for TX classfication == 2831 * leading RSS client id 2832 */ 2833 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 2834 2835 if (IS_FCOE_FP(fp)) { 2836 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 2837 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 2838 } 2839} 2840 2841static void bnx2x_pf_init(struct bnx2x *bp) 2842{ 2843 struct bnx2x_func_init_params func_init = {0}; 2844 struct event_ring_data eq_data = { {0} }; 2845 u16 flags; 2846 2847 if (!CHIP_IS_E1x(bp)) { 2848 /* reset IGU PF statistics: MSIX + ATTN */ 2849 /* PF */ 2850 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2851 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2852 (CHIP_MODE_IS_4_PORT(bp) ? 2853 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2854 /* ATTN */ 2855 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2856 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2857 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 2858 (CHIP_MODE_IS_4_PORT(bp) ? 2859 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2860 } 2861 2862 /* function setup flags */ 2863 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 2864 2865 /* This flag is relevant for E1x only. 2866 * E2 doesn't have a TPA configuration in a function level. 2867 */ 2868 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; 2869 2870 func_init.func_flgs = flags; 2871 func_init.pf_id = BP_FUNC(bp); 2872 func_init.func_id = BP_FUNC(bp); 2873 func_init.spq_map = bp->spq_mapping; 2874 func_init.spq_prod = bp->spq_prod_idx; 2875 2876 bnx2x_func_init(bp, &func_init); 2877 2878 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 2879 2880 /* 2881 * Congestion management values depend on the link rate 2882 * There is no active link so initial link rate is set to 10 Gbps. 2883 * When the link comes up The congestion management values are 2884 * re-calculated according to the actual link rate. 2885 */ 2886 bp->link_vars.line_speed = SPEED_10000; 2887 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 2888 2889 /* Only the PMF sets the HW */ 2890 if (bp->port.pmf) 2891 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2892 2893 /* init Event Queue */ 2894 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 2895 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 2896 eq_data.producer = bp->eq_prod; 2897 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 2898 eq_data.sb_id = DEF_SB_ID; 2899 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 2900} 2901 2902 2903static void bnx2x_e1h_disable(struct bnx2x *bp) 2904{ 2905 int port = BP_PORT(bp); 2906 2907 bnx2x_tx_disable(bp); 2908 2909 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 2910} 2911 2912static void bnx2x_e1h_enable(struct bnx2x *bp) 2913{ 2914 int port = BP_PORT(bp); 2915 2916 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 2917 2918 /* Tx queue should be only reenabled */ 2919 netif_tx_wake_all_queues(bp->dev); 2920 2921 /* 2922 * Should not call netif_carrier_on since it will be called if the link 2923 * is up when checking for link state 2924 */ 2925} 2926 2927#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 2928 2929static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) 2930{ 2931 struct eth_stats_info *ether_stat = 2932 &bp->slowpath->drv_info_to_mcp.ether_stat; 2933 2934 /* leave last char as NULL */ 2935 memcpy(ether_stat->version, DRV_MODULE_VERSION, 2936 ETH_STAT_INFO_VERSION_LEN - 1); 2937 2938 bp->fp[0].mac_obj.get_n_elements(bp, &bp->fp[0].mac_obj, 2939 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 2940 ether_stat->mac_local); 2941 2942 ether_stat->mtu_size = bp->dev->mtu; 2943 2944 if (bp->dev->features & NETIF_F_RXCSUM) 2945 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 2946 if (bp->dev->features & NETIF_F_TSO) 2947 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 2948 ether_stat->feature_flags |= bp->common.boot_mode; 2949 2950 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; 2951 2952 ether_stat->txq_size = bp->tx_ring_size; 2953 ether_stat->rxq_size = bp->rx_ring_size; 2954} 2955 2956static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) 2957{ 2958#ifdef BCM_CNIC 2959 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 2960 struct fcoe_stats_info *fcoe_stat = 2961 &bp->slowpath->drv_info_to_mcp.fcoe_stat; 2962 2963 memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN); 2964 2965 fcoe_stat->qos_priority = 2966 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; 2967 2968 /* insert FCoE stats from ramrod response */ 2969 if (!NO_FCOE(bp)) { 2970 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = 2971 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2972 tstorm_queue_statistics; 2973 2974 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = 2975 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2976 xstorm_queue_statistics; 2977 2978 struct fcoe_statistics_params *fw_fcoe_stat = 2979 &bp->fw_stats_data->fcoe; 2980 2981 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo, 2982 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); 2983 2984 ADD_64(fcoe_stat->rx_bytes_hi, 2985 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, 2986 fcoe_stat->rx_bytes_lo, 2987 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); 2988 2989 ADD_64(fcoe_stat->rx_bytes_hi, 2990 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, 2991 fcoe_stat->rx_bytes_lo, 2992 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); 2993 2994 ADD_64(fcoe_stat->rx_bytes_hi, 2995 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, 2996 fcoe_stat->rx_bytes_lo, 2997 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); 2998 2999 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3000 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); 3001 3002 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3003 fcoe_q_tstorm_stats->rcv_ucast_pkts); 3004 3005 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3006 fcoe_q_tstorm_stats->rcv_bcast_pkts); 3007 3008 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 3009 fcoe_q_tstorm_stats->rcv_mcast_pkts); 3010 3011 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo, 3012 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); 3013 3014 ADD_64(fcoe_stat->tx_bytes_hi, 3015 fcoe_q_xstorm_stats->ucast_bytes_sent.hi, 3016 fcoe_stat->tx_bytes_lo, 3017 fcoe_q_xstorm_stats->ucast_bytes_sent.lo); 3018 3019 ADD_64(fcoe_stat->tx_bytes_hi, 3020 fcoe_q_xstorm_stats->bcast_bytes_sent.hi, 3021 fcoe_stat->tx_bytes_lo, 3022 fcoe_q_xstorm_stats->bcast_bytes_sent.lo); 3023 3024 ADD_64(fcoe_stat->tx_bytes_hi, 3025 fcoe_q_xstorm_stats->mcast_bytes_sent.hi, 3026 fcoe_stat->tx_bytes_lo, 3027 fcoe_q_xstorm_stats->mcast_bytes_sent.lo); 3028 3029 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3030 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); 3031 3032 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3033 fcoe_q_xstorm_stats->ucast_pkts_sent); 3034 3035 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3036 fcoe_q_xstorm_stats->bcast_pkts_sent); 3037 3038 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3039 fcoe_q_xstorm_stats->mcast_pkts_sent); 3040 } 3041 3042 /* ask L5 driver to add data to the struct */ 3043 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); 3044#endif 3045} 3046 3047static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) 3048{ 3049#ifdef BCM_CNIC 3050 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3051 struct iscsi_stats_info *iscsi_stat = 3052 &bp->slowpath->drv_info_to_mcp.iscsi_stat; 3053 3054 memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); 3055 3056 iscsi_stat->qos_priority = 3057 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; 3058 3059 /* ask L5 driver to add data to the struct */ 3060 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); 3061#endif 3062} 3063 3064/* called due to MCP event (on pmf): 3065 * reread new bandwidth configuration 3066 * configure FW 3067 * notify others function about the change 3068 */ 3069static inline void bnx2x_config_mf_bw(struct bnx2x *bp) 3070{ 3071 if (bp->link_vars.link_up) { 3072 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 3073 bnx2x_link_sync_notify(bp); 3074 } 3075 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3076} 3077 3078static inline void bnx2x_set_mf_bw(struct bnx2x *bp) 3079{ 3080 bnx2x_config_mf_bw(bp); 3081 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 3082} 3083 3084static void bnx2x_handle_drv_info_req(struct bnx2x *bp) 3085{ 3086 enum drv_info_opcode op_code; 3087 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); 3088 3089 /* if drv_info version supported by MFW doesn't match - send NACK */ 3090 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 3091 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3092 return; 3093 } 3094 3095 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 3096 DRV_INFO_CONTROL_OP_CODE_SHIFT; 3097 3098 memset(&bp->slowpath->drv_info_to_mcp, 0, 3099 sizeof(union drv_info_to_mcp)); 3100 3101 switch (op_code) { 3102 case ETH_STATS_OPCODE: 3103 bnx2x_drv_info_ether_stat(bp); 3104 break; 3105 case FCOE_STATS_OPCODE: 3106 bnx2x_drv_info_fcoe_stat(bp); 3107 break; 3108 case ISCSI_STATS_OPCODE: 3109 bnx2x_drv_info_iscsi_stat(bp); 3110 break; 3111 default: 3112 /* if op code isn't supported - send NACK */ 3113 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3114 return; 3115 } 3116 3117 /* if we got drv_info attn from MFW then these fields are defined in 3118 * shmem2 for sure 3119 */ 3120 SHMEM2_WR(bp, drv_info_host_addr_lo, 3121 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3122 SHMEM2_WR(bp, drv_info_host_addr_hi, 3123 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3124 3125 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); 3126} 3127 3128static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) 3129{ 3130 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); 3131 3132 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 3133 3134 /* 3135 * This is the only place besides the function initialization 3136 * where the bp->flags can change so it is done without any 3137 * locks 3138 */ 3139 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 3140 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n"); 3141 bp->flags |= MF_FUNC_DIS; 3142 3143 bnx2x_e1h_disable(bp); 3144 } else { 3145 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); 3146 bp->flags &= ~MF_FUNC_DIS; 3147 3148 bnx2x_e1h_enable(bp); 3149 } 3150 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 3151 } 3152 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 3153 bnx2x_config_mf_bw(bp); 3154 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 3155 } 3156 3157 /* Report results to MCP */ 3158 if (dcc_event) 3159 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); 3160 else 3161 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); 3162} 3163 3164/* must be called under the spq lock */ 3165static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 3166{ 3167 struct eth_spe *next_spe = bp->spq_prod_bd; 3168 3169 if (bp->spq_prod_bd == bp->spq_last_bd) { 3170 bp->spq_prod_bd = bp->spq; 3171 bp->spq_prod_idx = 0; 3172 DP(NETIF_MSG_TIMER, "end of spq\n"); 3173 } else { 3174 bp->spq_prod_bd++; 3175 bp->spq_prod_idx++; 3176 } 3177 return next_spe; 3178} 3179 3180/* must be called under the spq lock */ 3181static inline void bnx2x_sp_prod_update(struct bnx2x *bp) 3182{ 3183 int func = BP_FUNC(bp); 3184 3185 /* 3186 * Make sure that BD data is updated before writing the producer: 3187 * BD data is written to the memory, the producer is read from the 3188 * memory, thus we need a full memory barrier to ensure the ordering. 3189 */ 3190 mb(); 3191 3192 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3193 bp->spq_prod_idx); 3194 mmiowb(); 3195} 3196 3197/** 3198 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3199 * 3200 * @cmd: command to check 3201 * @cmd_type: command type 3202 */ 3203static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3204{ 3205 if ((cmd_type == NONE_CONNECTION_TYPE) || 3206 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3207 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3208 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3209 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3210 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3211 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3212 return true; 3213 else 3214 return false; 3215 3216} 3217 3218 3219/** 3220 * bnx2x_sp_post - place a single command on an SP ring 3221 * 3222 * @bp: driver handle 3223 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3224 * @cid: SW CID the command is related to 3225 * @data_hi: command private data address (high 32 bits) 3226 * @data_lo: command private data address (low 32 bits) 3227 * @cmd_type: command type (e.g. NONE, ETH) 3228 * 3229 * SP data is handled as if it's always an address pair, thus data fields are 3230 * not swapped to little endian in upper functions. Instead this function swaps 3231 * data as if it's two u32 fields. 3232 */ 3233int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3234 u32 data_hi, u32 data_lo, int cmd_type) 3235{ 3236 struct eth_spe *spe; 3237 u16 type; 3238 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3239 3240#ifdef BNX2X_STOP_ON_ERROR 3241 if (unlikely(bp->panic)) 3242 return -EIO; 3243#endif 3244 3245 spin_lock_bh(&bp->spq_lock); 3246 3247 if (common) { 3248 if (!atomic_read(&bp->eq_spq_left)) { 3249 BNX2X_ERR("BUG! EQ ring full!\n"); 3250 spin_unlock_bh(&bp->spq_lock); 3251 bnx2x_panic(); 3252 return -EBUSY; 3253 } 3254 } else if (!atomic_read(&bp->cq_spq_left)) { 3255 BNX2X_ERR("BUG! SPQ ring full!\n"); 3256 spin_unlock_bh(&bp->spq_lock); 3257 bnx2x_panic(); 3258 return -EBUSY; 3259 } 3260 3261 spe = bnx2x_sp_get_next(bp); 3262 3263 /* CID needs port number to be encoded int it */ 3264 spe->hdr.conn_and_cmd_data = 3265 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3266 HW_CID(bp, cid)); 3267 3268 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; 3269 3270 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3271 SPE_HDR_FUNCTION_ID); 3272 3273 spe->hdr.type = cpu_to_le16(type); 3274 3275 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3276 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3277 3278 /* 3279 * It's ok if the actual decrement is issued towards the memory 3280 * somewhere between the spin_lock and spin_unlock. Thus no 3281 * more explict memory barrier is needed. 3282 */ 3283 if (common) 3284 atomic_dec(&bp->eq_spq_left); 3285 else 3286 atomic_dec(&bp->cq_spq_left); 3287 3288 3289 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/, 3290 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) " 3291 "type(0x%x) left (CQ, EQ) (%x,%x)\n", 3292 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3293 (u32)(U64_LO(bp->spq_mapping) + 3294 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3295 HW_CID(bp, cid), data_hi, data_lo, type, 3296 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3297 3298 bnx2x_sp_prod_update(bp); 3299 spin_unlock_bh(&bp->spq_lock); 3300 return 0; 3301} 3302 3303/* acquire split MCP access lock register */ 3304static int bnx2x_acquire_alr(struct bnx2x *bp) 3305{ 3306 u32 j, val; 3307 int rc = 0; 3308 3309 might_sleep(); 3310 for (j = 0; j < 1000; j++) { 3311 val = (1UL << 31); 3312 REG_WR(bp, GRCBASE_MCP + 0x9c, val); 3313 val = REG_RD(bp, GRCBASE_MCP + 0x9c); 3314 if (val & (1L << 31)) 3315 break; 3316 3317 msleep(5); 3318 } 3319 if (!(val & (1L << 31))) { 3320 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3321 rc = -EBUSY; 3322 } 3323 3324 return rc; 3325} 3326 3327/* release split MCP access lock register */ 3328static void bnx2x_release_alr(struct bnx2x *bp) 3329{ 3330 REG_WR(bp, GRCBASE_MCP + 0x9c, 0); 3331} 3332 3333#define BNX2X_DEF_SB_ATT_IDX 0x0001 3334#define BNX2X_DEF_SB_IDX 0x0002 3335 3336static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3337{ 3338 struct host_sp_status_block *def_sb = bp->def_status_blk; 3339 u16 rc = 0; 3340 3341 barrier(); /* status block is written to by the chip */ 3342 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3343 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 3344 rc |= BNX2X_DEF_SB_ATT_IDX; 3345 } 3346 3347 if (bp->def_idx != def_sb->sp_sb.running_index) { 3348 bp->def_idx = def_sb->sp_sb.running_index; 3349 rc |= BNX2X_DEF_SB_IDX; 3350 } 3351 3352 /* Do not reorder: indecies reading should complete before handling */ 3353 barrier(); 3354 return rc; 3355} 3356 3357/* 3358 * slow path service functions 3359 */ 3360 3361static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 3362{ 3363 int port = BP_PORT(bp); 3364 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 3365 MISC_REG_AEU_MASK_ATTN_FUNC_0; 3366 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 3367 NIG_REG_MASK_INTERRUPT_PORT0; 3368 u32 aeu_mask; 3369 u32 nig_mask = 0; 3370 u32 reg_addr; 3371 3372 if (bp->attn_state & asserted) 3373 BNX2X_ERR("IGU ERROR\n"); 3374 3375 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3376 aeu_mask = REG_RD(bp, aeu_addr); 3377 3378 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 3379 aeu_mask, asserted); 3380 aeu_mask &= ~(asserted & 0x3ff); 3381 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 3382 3383 REG_WR(bp, aeu_addr, aeu_mask); 3384 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3385 3386 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 3387 bp->attn_state |= asserted; 3388 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 3389 3390 if (asserted & ATTN_HARD_WIRED_MASK) { 3391 if (asserted & ATTN_NIG_FOR_FUNC) { 3392 3393 bnx2x_acquire_phy_lock(bp); 3394 3395 /* save nig interrupt mask */ 3396 nig_mask = REG_RD(bp, nig_int_mask_addr); 3397 3398 /* If nig_mask is not set, no need to call the update 3399 * function. 3400 */ 3401 if (nig_mask) { 3402 REG_WR(bp, nig_int_mask_addr, 0); 3403 3404 bnx2x_link_attn(bp); 3405 } 3406 3407 /* handle unicore attn? */ 3408 } 3409 if (asserted & ATTN_SW_TIMER_4_FUNC) 3410 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 3411 3412 if (asserted & GPIO_2_FUNC) 3413 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 3414 3415 if (asserted & GPIO_3_FUNC) 3416 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 3417 3418 if (asserted & GPIO_4_FUNC) 3419 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 3420 3421 if (port == 0) { 3422 if (asserted & ATTN_GENERAL_ATTN_1) { 3423 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 3424 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 3425 } 3426 if (asserted & ATTN_GENERAL_ATTN_2) { 3427 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 3428 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 3429 } 3430 if (asserted & ATTN_GENERAL_ATTN_3) { 3431 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 3432 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 3433 } 3434 } else { 3435 if (asserted & ATTN_GENERAL_ATTN_4) { 3436 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 3437 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 3438 } 3439 if (asserted & ATTN_GENERAL_ATTN_5) { 3440 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 3441 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 3442 } 3443 if (asserted & ATTN_GENERAL_ATTN_6) { 3444 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 3445 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 3446 } 3447 } 3448 3449 } /* if hardwired */ 3450 3451 if (bp->common.int_block == INT_BLOCK_HC) 3452 reg_addr = (HC_REG_COMMAND_REG + port*32 + 3453 COMMAND_REG_ATTN_BITS_SET); 3454 else 3455 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 3456 3457 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 3458 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 3459 REG_WR(bp, reg_addr, asserted); 3460 3461 /* now set back the mask */ 3462 if (asserted & ATTN_NIG_FOR_FUNC) { 3463 REG_WR(bp, nig_int_mask_addr, nig_mask); 3464 bnx2x_release_phy_lock(bp); 3465 } 3466} 3467 3468static inline void bnx2x_fan_failure(struct bnx2x *bp) 3469{ 3470 int port = BP_PORT(bp); 3471 u32 ext_phy_config; 3472 /* mark the failure */ 3473 ext_phy_config = 3474 SHMEM_RD(bp, 3475 dev_info.port_hw_config[port].external_phy_config); 3476 3477 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 3478 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 3479 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 3480 ext_phy_config); 3481 3482 /* log the failure */ 3483 netdev_err(bp->dev, "Fan Failure on Network Controller has caused" 3484 " the driver to shutdown the card to prevent permanent" 3485 " damage. Please contact OEM Support for assistance\n"); 3486 3487 /* 3488 * Scheudle device reset (unload) 3489 * This is due to some boards consuming sufficient power when driver is 3490 * up to overheat if fan fails. 3491 */ 3492 smp_mb__before_clear_bit(); 3493 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); 3494 smp_mb__after_clear_bit(); 3495 schedule_delayed_work(&bp->sp_rtnl_task, 0); 3496 3497} 3498 3499static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 3500{ 3501 int port = BP_PORT(bp); 3502 int reg_offset; 3503 u32 val; 3504 3505 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 3506 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 3507 3508 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 3509 3510 val = REG_RD(bp, reg_offset); 3511 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 3512 REG_WR(bp, reg_offset, val); 3513 3514 BNX2X_ERR("SPIO5 hw attention\n"); 3515 3516 /* Fan failure attention */ 3517 bnx2x_hw_reset_phy(&bp->link_params); 3518 bnx2x_fan_failure(bp); 3519 } 3520 3521 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 3522 bnx2x_acquire_phy_lock(bp); 3523 bnx2x_handle_module_detect_int(&bp->link_params); 3524 bnx2x_release_phy_lock(bp); 3525 } 3526 3527 if (attn & HW_INTERRUT_ASSERT_SET_0) { 3528 3529 val = REG_RD(bp, reg_offset); 3530 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 3531 REG_WR(bp, reg_offset, val); 3532 3533 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 3534 (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); 3535 bnx2x_panic(); 3536 } 3537} 3538 3539static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 3540{ 3541 u32 val; 3542 3543 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 3544 3545 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 3546 BNX2X_ERR("DB hw attention 0x%x\n", val); 3547 /* DORQ discard attention */ 3548 if (val & 0x2) 3549 BNX2X_ERR("FATAL error from DORQ\n"); 3550 } 3551 3552 if (attn & HW_INTERRUT_ASSERT_SET_1) { 3553 3554 int port = BP_PORT(bp); 3555 int reg_offset; 3556 3557 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 3558 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 3559 3560 val = REG_RD(bp, reg_offset); 3561 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 3562 REG_WR(bp, reg_offset, val); 3563 3564 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 3565 (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); 3566 bnx2x_panic(); 3567 } 3568} 3569 3570static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 3571{ 3572 u32 val; 3573 3574 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 3575 3576 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 3577 BNX2X_ERR("CFC hw attention 0x%x\n", val); 3578 /* CFC error attention */ 3579 if (val & 0x2) 3580 BNX2X_ERR("FATAL error from CFC\n"); 3581 } 3582 3583 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 3584 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 3585 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 3586 /* RQ_USDMDP_FIFO_OVERFLOW */ 3587 if (val & 0x18000) 3588 BNX2X_ERR("FATAL error from PXP\n"); 3589 3590 if (!CHIP_IS_E1x(bp)) { 3591 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 3592 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 3593 } 3594 } 3595 3596 if (attn & HW_INTERRUT_ASSERT_SET_2) { 3597 3598 int port = BP_PORT(bp); 3599 int reg_offset; 3600 3601 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 3602 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 3603 3604 val = REG_RD(bp, reg_offset); 3605 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 3606 REG_WR(bp, reg_offset, val); 3607 3608 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 3609 (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); 3610 bnx2x_panic(); 3611 } 3612} 3613 3614static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 3615{ 3616 u32 val; 3617 3618 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 3619 3620 if (attn & BNX2X_PMF_LINK_ASSERT) { 3621 int func = BP_FUNC(bp); 3622 3623 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 3624 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 3625 func_mf_config[BP_ABS_FUNC(bp)].config); 3626 val = SHMEM_RD(bp, 3627 func_mb[BP_FW_MB_IDX(bp)].drv_status); 3628 if (val & DRV_STATUS_DCC_EVENT_MASK) 3629 bnx2x_dcc_event(bp, 3630 (val & DRV_STATUS_DCC_EVENT_MASK)); 3631 3632 if (val & DRV_STATUS_SET_MF_BW) 3633 bnx2x_set_mf_bw(bp); 3634 3635 if (val & DRV_STATUS_DRV_INFO_REQ) 3636 bnx2x_handle_drv_info_req(bp); 3637 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 3638 bnx2x_pmf_update(bp); 3639 3640 if (bp->port.pmf && 3641 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 3642 bp->dcbx_enabled > 0) 3643 /* start dcbx state machine */ 3644 bnx2x_dcbx_set_params(bp, 3645 BNX2X_DCBX_STATE_NEG_RECEIVED); 3646 if (bp->link_vars.periodic_flags & 3647 PERIODIC_FLAGS_LINK_EVENT) { 3648 /* sync with link */ 3649 bnx2x_acquire_phy_lock(bp); 3650 bp->link_vars.periodic_flags &= 3651 ~PERIODIC_FLAGS_LINK_EVENT; 3652 bnx2x_release_phy_lock(bp); 3653 if (IS_MF(bp)) 3654 bnx2x_link_sync_notify(bp); 3655 bnx2x_link_report(bp); 3656 } 3657 /* Always call it here: bnx2x_link_report() will 3658 * prevent the link indication duplication. 3659 */ 3660 bnx2x__link_status_update(bp); 3661 } else if (attn & BNX2X_MC_ASSERT_BITS) { 3662 3663 BNX2X_ERR("MC assert!\n"); 3664 bnx2x_mc_assert(bp); 3665 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 3666 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 3667 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 3668 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 3669 bnx2x_panic(); 3670 3671 } else if (attn & BNX2X_MCP_ASSERT) { 3672 3673 BNX2X_ERR("MCP assert!\n"); 3674 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 3675 bnx2x_fw_dump(bp); 3676 3677 } else 3678 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 3679 } 3680 3681 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 3682 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 3683 if (attn & BNX2X_GRC_TIMEOUT) { 3684 val = CHIP_IS_E1(bp) ? 0 : 3685 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 3686 BNX2X_ERR("GRC time-out 0x%08x\n", val); 3687 } 3688 if (attn & BNX2X_GRC_RSV) { 3689 val = CHIP_IS_E1(bp) ? 0 : 3690 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 3691 BNX2X_ERR("GRC reserved 0x%08x\n", val); 3692 } 3693 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 3694 } 3695} 3696 3697/* 3698 * Bits map: 3699 * 0-7 - Engine0 load counter. 3700 * 8-15 - Engine1 load counter. 3701 * 16 - Engine0 RESET_IN_PROGRESS bit. 3702 * 17 - Engine1 RESET_IN_PROGRESS bit. 3703 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 3704 * on the engine 3705 * 19 - Engine1 ONE_IS_LOADED. 3706 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 3707 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 3708 * just the one belonging to its engine). 3709 * 3710 */ 3711#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 3712 3713#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 3714#define BNX2X_PATH0_LOAD_CNT_SHIFT 0 3715#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 3716#define BNX2X_PATH1_LOAD_CNT_SHIFT 8 3717#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 3718#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 3719#define BNX2X_GLOBAL_RESET_BIT 0x00040000 3720 3721/* 3722 * Set the GLOBAL_RESET bit. 3723 * 3724 * Should be run under rtnl lock 3725 */ 3726void bnx2x_set_reset_global(struct bnx2x *bp) 3727{ 3728 u32 val; 3729 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3730 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3731 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 3732 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3733} 3734 3735/* 3736 * Clear the GLOBAL_RESET bit. 3737 * 3738 * Should be run under rtnl lock 3739 */ 3740static inline void bnx2x_clear_reset_global(struct bnx2x *bp) 3741{ 3742 u32 val; 3743 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3744 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3745 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 3746 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3747} 3748 3749/* 3750 * Checks the GLOBAL_RESET bit. 3751 * 3752 * should be run under rtnl lock 3753 */ 3754static inline bool bnx2x_reset_is_global(struct bnx2x *bp) 3755{ 3756 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3757 3758 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 3759 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 3760} 3761 3762/* 3763 * Clear RESET_IN_PROGRESS bit for the current engine. 3764 * 3765 * Should be run under rtnl lock 3766 */ 3767static inline void bnx2x_set_reset_done(struct bnx2x *bp) 3768{ 3769 u32 val; 3770 u32 bit = BP_PATH(bp) ? 3771 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3772 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3773 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3774 3775 /* Clear the bit */ 3776 val &= ~bit; 3777 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3778 3779 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3780} 3781 3782/* 3783 * Set RESET_IN_PROGRESS for the current engine. 3784 * 3785 * should be run under rtnl lock 3786 */ 3787void bnx2x_set_reset_in_progress(struct bnx2x *bp) 3788{ 3789 u32 val; 3790 u32 bit = BP_PATH(bp) ? 3791 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3792 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3793 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3794 3795 /* Set the bit */ 3796 val |= bit; 3797 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3798 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3799} 3800 3801/* 3802 * Checks the RESET_IN_PROGRESS bit for the given engine. 3803 * should be run under rtnl lock 3804 */ 3805bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 3806{ 3807 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3808 u32 bit = engine ? 3809 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3810 3811 /* return false if bit is set */ 3812 return (val & bit) ? false : true; 3813} 3814 3815/* 3816 * set pf load for the current pf. 3817 * 3818 * should be run under rtnl lock 3819 */ 3820void bnx2x_set_pf_load(struct bnx2x *bp) 3821{ 3822 u32 val1, val; 3823 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3824 BNX2X_PATH0_LOAD_CNT_MASK; 3825 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3826 BNX2X_PATH0_LOAD_CNT_SHIFT; 3827 3828 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3829 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3830 3831 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3832 3833 /* get the current counter value */ 3834 val1 = (val & mask) >> shift; 3835 3836 /* set bit of that PF */ 3837 val1 |= (1 << bp->pf_num); 3838 3839 /* clear the old value */ 3840 val &= ~mask; 3841 3842 /* set the new one */ 3843 val |= ((val1 << shift) & mask); 3844 3845 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3846 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3847} 3848 3849/** 3850 * bnx2x_clear_pf_load - clear pf load mark 3851 * 3852 * @bp: driver handle 3853 * 3854 * Should be run under rtnl lock. 3855 * Decrements the load counter for the current engine. Returns 3856 * whether other functions are still loaded 3857 */ 3858bool bnx2x_clear_pf_load(struct bnx2x *bp) 3859{ 3860 u32 val1, val; 3861 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3862 BNX2X_PATH0_LOAD_CNT_MASK; 3863 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3864 BNX2X_PATH0_LOAD_CNT_SHIFT; 3865 3866 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3867 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3868 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3869 3870 /* get the current counter value */ 3871 val1 = (val & mask) >> shift; 3872 3873 /* clear bit of that PF */ 3874 val1 &= ~(1 << bp->pf_num); 3875 3876 /* clear the old value */ 3877 val &= ~mask; 3878 3879 /* set the new one */ 3880 val |= ((val1 << shift) & mask); 3881 3882 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3883 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3884 return val1 != 0; 3885} 3886 3887/* 3888 * Read the load status for the current engine. 3889 * 3890 * should be run under rtnl lock 3891 */ 3892static inline bool bnx2x_get_load_status(struct bnx2x *bp, int engine) 3893{ 3894 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 3895 BNX2X_PATH0_LOAD_CNT_MASK); 3896 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3897 BNX2X_PATH0_LOAD_CNT_SHIFT); 3898 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3899 3900 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val); 3901 3902 val = (val & mask) >> shift; 3903 3904 DP(NETIF_MSG_HW, "load mask for engine %d = 0x%x\n", engine, val); 3905 3906 return val != 0; 3907} 3908 3909/* 3910 * Reset the load status for the current engine. 3911 */ 3912static inline void bnx2x_clear_load_status(struct bnx2x *bp) 3913{ 3914 u32 val; 3915 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3916 BNX2X_PATH0_LOAD_CNT_MASK); 3917 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3918 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3919 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); 3920 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3921} 3922 3923static inline void _print_next_block(int idx, const char *blk) 3924{ 3925 pr_cont("%s%s", idx ? ", " : "", blk); 3926} 3927 3928static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, 3929 bool print) 3930{ 3931 int i = 0; 3932 u32 cur_bit = 0; 3933 for (i = 0; sig; i++) { 3934 cur_bit = ((u32)0x1 << i); 3935 if (sig & cur_bit) { 3936 switch (cur_bit) { 3937 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 3938 if (print) 3939 _print_next_block(par_num++, "BRB"); 3940 break; 3941 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 3942 if (print) 3943 _print_next_block(par_num++, "PARSER"); 3944 break; 3945 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 3946 if (print) 3947 _print_next_block(par_num++, "TSDM"); 3948 break; 3949 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 3950 if (print) 3951 _print_next_block(par_num++, 3952 "SEARCHER"); 3953 break; 3954 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 3955 if (print) 3956 _print_next_block(par_num++, "TCM"); 3957 break; 3958 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 3959 if (print) 3960 _print_next_block(par_num++, "TSEMI"); 3961 break; 3962 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 3963 if (print) 3964 _print_next_block(par_num++, "XPB"); 3965 break; 3966 } 3967 3968 /* Clear the bit */ 3969 sig &= ~cur_bit; 3970 } 3971 } 3972 3973 return par_num; 3974} 3975 3976static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, 3977 bool *global, bool print) 3978{ 3979 int i = 0; 3980 u32 cur_bit = 0; 3981 for (i = 0; sig; i++) { 3982 cur_bit = ((u32)0x1 << i); 3983 if (sig & cur_bit) { 3984 switch (cur_bit) { 3985 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 3986 if (print) 3987 _print_next_block(par_num++, "PBF"); 3988 break; 3989 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 3990 if (print) 3991 _print_next_block(par_num++, "QM"); 3992 break; 3993 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 3994 if (print) 3995 _print_next_block(par_num++, "TM"); 3996 break; 3997 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 3998 if (print) 3999 _print_next_block(par_num++, "XSDM"); 4000 break; 4001 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 4002 if (print) 4003 _print_next_block(par_num++, "XCM"); 4004 break; 4005 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 4006 if (print) 4007 _print_next_block(par_num++, "XSEMI"); 4008 break; 4009 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 4010 if (print) 4011 _print_next_block(par_num++, 4012 "DOORBELLQ"); 4013 break; 4014 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 4015 if (print) 4016 _print_next_block(par_num++, "NIG"); 4017 break; 4018 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 4019 if (print) 4020 _print_next_block(par_num++, 4021 "VAUX PCI CORE"); 4022 *global = true; 4023 break; 4024 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 4025 if (print) 4026 _print_next_block(par_num++, "DEBUG"); 4027 break; 4028 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 4029 if (print) 4030 _print_next_block(par_num++, "USDM"); 4031 break; 4032 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 4033 if (print) 4034 _print_next_block(par_num++, "UCM"); 4035 break; 4036 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 4037 if (print) 4038 _print_next_block(par_num++, "USEMI"); 4039 break; 4040 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 4041 if (print) 4042 _print_next_block(par_num++, "UPB"); 4043 break; 4044 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 4045 if (print) 4046 _print_next_block(par_num++, "CSDM"); 4047 break; 4048 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 4049 if (print) 4050 _print_next_block(par_num++, "CCM"); 4051 break; 4052 } 4053 4054 /* Clear the bit */ 4055 sig &= ~cur_bit; 4056 } 4057 } 4058 4059 return par_num; 4060} 4061 4062static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, 4063 bool print) 4064{ 4065 int i = 0; 4066 u32 cur_bit = 0; 4067 for (i = 0; sig; i++) { 4068 cur_bit = ((u32)0x1 << i); 4069 if (sig & cur_bit) { 4070 switch (cur_bit) { 4071 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 4072 if (print) 4073 _print_next_block(par_num++, "CSEMI"); 4074 break; 4075 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 4076 if (print) 4077 _print_next_block(par_num++, "PXP"); 4078 break; 4079 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 4080 if (print) 4081 _print_next_block(par_num++, 4082 "PXPPCICLOCKCLIENT"); 4083 break; 4084 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 4085 if (print) 4086 _print_next_block(par_num++, "CFC"); 4087 break; 4088 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 4089 if (print) 4090 _print_next_block(par_num++, "CDU"); 4091 break; 4092 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 4093 if (print) 4094 _print_next_block(par_num++, "DMAE"); 4095 break; 4096 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 4097 if (print) 4098 _print_next_block(par_num++, "IGU"); 4099 break; 4100 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 4101 if (print) 4102 _print_next_block(par_num++, "MISC"); 4103 break; 4104 } 4105 4106 /* Clear the bit */ 4107 sig &= ~cur_bit; 4108 } 4109 } 4110 4111 return par_num; 4112} 4113 4114static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, 4115 bool *global, bool print) 4116{ 4117 int i = 0; 4118 u32 cur_bit = 0; 4119 for (i = 0; sig; i++) { 4120 cur_bit = ((u32)0x1 << i); 4121 if (sig & cur_bit) { 4122 switch (cur_bit) { 4123 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 4124 if (print) 4125 _print_next_block(par_num++, "MCP ROM"); 4126 *global = true; 4127 break; 4128 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 4129 if (print) 4130 _print_next_block(par_num++, 4131 "MCP UMP RX"); 4132 *global = true; 4133 break; 4134 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 4135 if (print) 4136 _print_next_block(par_num++, 4137 "MCP UMP TX"); 4138 *global = true; 4139 break; 4140 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 4141 if (print) 4142 _print_next_block(par_num++, 4143 "MCP SCPAD"); 4144 *global = true; 4145 break; 4146 } 4147 4148 /* Clear the bit */ 4149 sig &= ~cur_bit; 4150 } 4151 } 4152 4153 return par_num; 4154} 4155 4156static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, 4157 bool print) 4158{ 4159 int i = 0; 4160 u32 cur_bit = 0; 4161 for (i = 0; sig; i++) { 4162 cur_bit = ((u32)0x1 << i); 4163 if (sig & cur_bit) { 4164 switch (cur_bit) { 4165 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 4166 if (print) 4167 _print_next_block(par_num++, "PGLUE_B"); 4168 break; 4169 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 4170 if (print) 4171 _print_next_block(par_num++, "ATC"); 4172 break; 4173 } 4174 4175 /* Clear the bit */ 4176 sig &= ~cur_bit; 4177 } 4178 } 4179 4180 return par_num; 4181} 4182 4183static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4184 u32 *sig) 4185{ 4186 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4187 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4188 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4189 (sig[3] & HW_PRTY_ASSERT_SET_3) || 4190 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4191 int par_num = 0; 4192 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: " 4193 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x " 4194 "[4]:0x%08x\n", 4195 sig[0] & HW_PRTY_ASSERT_SET_0, 4196 sig[1] & HW_PRTY_ASSERT_SET_1, 4197 sig[2] & HW_PRTY_ASSERT_SET_2, 4198 sig[3] & HW_PRTY_ASSERT_SET_3, 4199 sig[4] & HW_PRTY_ASSERT_SET_4); 4200 if (print) 4201 netdev_err(bp->dev, 4202 "Parity errors detected in blocks: "); 4203 par_num = bnx2x_check_blocks_with_parity0( 4204 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); 4205 par_num = bnx2x_check_blocks_with_parity1( 4206 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); 4207 par_num = bnx2x_check_blocks_with_parity2( 4208 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); 4209 par_num = bnx2x_check_blocks_with_parity3( 4210 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); 4211 par_num = bnx2x_check_blocks_with_parity4( 4212 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); 4213 4214 if (print) 4215 pr_cont("\n"); 4216 4217 return true; 4218 } else 4219 return false; 4220} 4221 4222/** 4223 * bnx2x_chk_parity_attn - checks for parity attentions. 4224 * 4225 * @bp: driver handle 4226 * @global: true if there was a global attention 4227 * @print: show parity attention in syslog 4228 */ 4229bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 4230{ 4231 struct attn_route attn = { {0} }; 4232 int port = BP_PORT(bp); 4233 4234 attn.sig[0] = REG_RD(bp, 4235 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 4236 port*4); 4237 attn.sig[1] = REG_RD(bp, 4238 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 4239 port*4); 4240 attn.sig[2] = REG_RD(bp, 4241 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 4242 port*4); 4243 attn.sig[3] = REG_RD(bp, 4244 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 4245 port*4); 4246 4247 if (!CHIP_IS_E1x(bp)) 4248 attn.sig[4] = REG_RD(bp, 4249 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 4250 port*4); 4251 4252 return bnx2x_parity_attn(bp, global, print, attn.sig); 4253} 4254 4255 4256static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 4257{ 4258 u32 val; 4259 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 4260 4261 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 4262 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 4263 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 4264 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4265 "ADDRESS_ERROR\n"); 4266 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 4267 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4268 "INCORRECT_RCV_BEHAVIOR\n"); 4269 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 4270 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4271 "WAS_ERROR_ATTN\n"); 4272 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 4273 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4274 "VF_LENGTH_VIOLATION_ATTN\n"); 4275 if (val & 4276 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 4277 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4278 "VF_GRC_SPACE_VIOLATION_ATTN\n"); 4279 if (val & 4280 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 4281 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4282 "VF_MSIX_BAR_VIOLATION_ATTN\n"); 4283 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 4284 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4285 "TCPL_ERROR_ATTN\n"); 4286 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 4287 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4288 "TCPL_IN_TWO_RCBS_ATTN\n"); 4289 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 4290 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4291 "CSSNOOP_FIFO_OVERFLOW\n"); 4292 } 4293 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 4294 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 4295 BNX2X_ERR("ATC hw attention 0x%x\n", val); 4296 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 4297 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 4298 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 4299 BNX2X_ERR("ATC_ATC_INT_STS_REG" 4300 "_ATC_TCPL_TO_NOT_PEND\n"); 4301 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 4302 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4303 "ATC_GPA_MULTIPLE_HITS\n"); 4304 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 4305 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4306 "ATC_RCPL_TO_EMPTY_CNT\n"); 4307 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 4308 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 4309 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 4310 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4311 "ATC_IREQ_LESS_THAN_STU\n"); 4312 } 4313 4314 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4315 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 4316 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 4317 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4318 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 4319 } 4320 4321} 4322 4323static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 4324{ 4325 struct attn_route attn, *group_mask; 4326 int port = BP_PORT(bp); 4327 int index; 4328 u32 reg_addr; 4329 u32 val; 4330 u32 aeu_mask; 4331 bool global = false; 4332 4333 /* need to take HW lock because MCP or other port might also 4334 try to handle this event */ 4335 bnx2x_acquire_alr(bp); 4336 4337 if (bnx2x_chk_parity_attn(bp, &global, true)) { 4338#ifndef BNX2X_STOP_ON_ERROR 4339 bp->recovery_state = BNX2X_RECOVERY_INIT; 4340 schedule_delayed_work(&bp->sp_rtnl_task, 0); 4341 /* Disable HW interrupts */ 4342 bnx2x_int_disable(bp); 4343 /* In case of parity errors don't handle attentions so that 4344 * other function would "see" parity errors. 4345 */ 4346#else 4347 bnx2x_panic(); 4348#endif 4349 bnx2x_release_alr(bp); 4350 return; 4351 } 4352 4353 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 4354 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 4355 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 4356 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 4357 if (!CHIP_IS_E1x(bp)) 4358 attn.sig[4] = 4359 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 4360 else 4361 attn.sig[4] = 0; 4362 4363 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 4364 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 4365 4366 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4367 if (deasserted & (1 << index)) { 4368 group_mask = &bp->attn_group[index]; 4369 4370 DP(NETIF_MSG_HW, "group[%d]: %08x %08x " 4371 "%08x %08x %08x\n", 4372 index, 4373 group_mask->sig[0], group_mask->sig[1], 4374 group_mask->sig[2], group_mask->sig[3], 4375 group_mask->sig[4]); 4376 4377 bnx2x_attn_int_deasserted4(bp, 4378 attn.sig[4] & group_mask->sig[4]); 4379 bnx2x_attn_int_deasserted3(bp, 4380 attn.sig[3] & group_mask->sig[3]); 4381 bnx2x_attn_int_deasserted1(bp, 4382 attn.sig[1] & group_mask->sig[1]); 4383 bnx2x_attn_int_deasserted2(bp, 4384 attn.sig[2] & group_mask->sig[2]); 4385 bnx2x_attn_int_deasserted0(bp, 4386 attn.sig[0] & group_mask->sig[0]); 4387 } 4388 } 4389 4390 bnx2x_release_alr(bp); 4391 4392 if (bp->common.int_block == INT_BLOCK_HC) 4393 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4394 COMMAND_REG_ATTN_BITS_CLR); 4395 else 4396 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 4397 4398 val = ~deasserted; 4399 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 4400 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4401 REG_WR(bp, reg_addr, val); 4402 4403 if (~bp->attn_state & deasserted) 4404 BNX2X_ERR("IGU ERROR\n"); 4405 4406 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4407 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4408 4409 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4410 aeu_mask = REG_RD(bp, reg_addr); 4411 4412 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 4413 aeu_mask, deasserted); 4414 aeu_mask |= (deasserted & 0x3ff); 4415 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4416 4417 REG_WR(bp, reg_addr, aeu_mask); 4418 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4419 4420 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4421 bp->attn_state &= ~deasserted; 4422 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4423} 4424 4425static void bnx2x_attn_int(struct bnx2x *bp) 4426{ 4427 /* read local copy of bits */ 4428 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 4429 attn_bits); 4430 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 4431 attn_bits_ack); 4432 u32 attn_state = bp->attn_state; 4433 4434 /* look for changed bits */ 4435 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 4436 u32 deasserted = ~attn_bits & attn_ack & attn_state; 4437 4438 DP(NETIF_MSG_HW, 4439 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 4440 attn_bits, attn_ack, asserted, deasserted); 4441 4442 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 4443 BNX2X_ERR("BAD attention state\n"); 4444 4445 /* handle bits that were raised */ 4446 if (asserted) 4447 bnx2x_attn_int_asserted(bp, asserted); 4448 4449 if (deasserted) 4450 bnx2x_attn_int_deasserted(bp, deasserted); 4451} 4452 4453void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 4454 u16 index, u8 op, u8 update) 4455{ 4456 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 4457 4458 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 4459 igu_addr); 4460} 4461 4462static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 4463{ 4464 /* No memory barriers */ 4465 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 4466 mmiowb(); /* keep prod updates ordered */ 4467} 4468 4469#ifdef BCM_CNIC 4470static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 4471 union event_ring_elem *elem) 4472{ 4473 u8 err = elem->message.error; 4474 4475 if (!bp->cnic_eth_dev.starting_cid || 4476 (cid < bp->cnic_eth_dev.starting_cid && 4477 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 4478 return 1; 4479 4480 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 4481 4482 if (unlikely(err)) { 4483 4484 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 4485 cid); 4486 bnx2x_panic_dump(bp); 4487 } 4488 bnx2x_cnic_cfc_comp(bp, cid, err); 4489 return 0; 4490} 4491#endif 4492 4493static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 4494{ 4495 struct bnx2x_mcast_ramrod_params rparam; 4496 int rc; 4497 4498 memset(&rparam, 0, sizeof(rparam)); 4499 4500 rparam.mcast_obj = &bp->mcast_obj; 4501 4502 netif_addr_lock_bh(bp->dev); 4503 4504 /* Clear pending state for the last command */ 4505 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 4506 4507 /* If there are pending mcast commands - send them */ 4508 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 4509 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 4510 if (rc < 0) 4511 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 4512 rc); 4513 } 4514 4515 netif_addr_unlock_bh(bp->dev); 4516} 4517 4518static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp, 4519 union event_ring_elem *elem) 4520{ 4521 unsigned long ramrod_flags = 0; 4522 int rc = 0; 4523 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; 4524 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 4525 4526 /* Always push next commands out, don't wait here */ 4527 __set_bit(RAMROD_CONT, &ramrod_flags); 4528 4529 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 4530 case BNX2X_FILTER_MAC_PENDING: 4531#ifdef BCM_CNIC 4532 if (cid == BNX2X_ISCSI_ETH_CID) 4533 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 4534 else 4535#endif 4536 vlan_mac_obj = &bp->fp[cid].mac_obj; 4537 4538 break; 4539 case BNX2X_FILTER_MCAST_PENDING: 4540 /* This is only relevant for 57710 where multicast MACs are 4541 * configured as unicast MACs using the same ramrod. 4542 */ 4543 bnx2x_handle_mcast_eqe(bp); 4544 return; 4545 default: 4546 BNX2X_ERR("Unsupported classification command: %d\n", 4547 elem->message.data.eth_event.echo); 4548 return; 4549 } 4550 4551 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 4552 4553 if (rc < 0) 4554 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 4555 else if (rc > 0) 4556 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 4557 4558} 4559 4560#ifdef BCM_CNIC 4561static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 4562#endif 4563 4564static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 4565{ 4566 netif_addr_lock_bh(bp->dev); 4567 4568 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 4569 4570 /* Send rx_mode command again if was requested */ 4571 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 4572 bnx2x_set_storm_rx_mode(bp); 4573#ifdef BCM_CNIC 4574 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 4575 &bp->sp_state)) 4576 bnx2x_set_iscsi_eth_rx_mode(bp, true); 4577 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 4578 &bp->sp_state)) 4579 bnx2x_set_iscsi_eth_rx_mode(bp, false); 4580#endif 4581 4582 netif_addr_unlock_bh(bp->dev); 4583} 4584 4585static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 4586 struct bnx2x *bp, u32 cid) 4587{ 4588 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 4589#ifdef BCM_CNIC 4590 if (cid == BNX2X_FCOE_ETH_CID) 4591 return &bnx2x_fcoe(bp, q_obj); 4592 else 4593#endif 4594 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj); 4595} 4596 4597static void bnx2x_eq_int(struct bnx2x *bp) 4598{ 4599 u16 hw_cons, sw_cons, sw_prod; 4600 union event_ring_elem *elem; 4601 u32 cid; 4602 u8 opcode; 4603 int spqe_cnt = 0; 4604 struct bnx2x_queue_sp_obj *q_obj; 4605 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 4606 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 4607 4608 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 4609 4610 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 4611 * when we get the the next-page we nned to adjust so the loop 4612 * condition below will be met. The next element is the size of a 4613 * regular element and hence incrementing by 1 4614 */ 4615 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 4616 hw_cons++; 4617 4618 /* This function may never run in parallel with itself for a 4619 * specific bp, thus there is no need in "paired" read memory 4620 * barrier here. 4621 */ 4622 sw_cons = bp->eq_cons; 4623 sw_prod = bp->eq_prod; 4624 4625 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 4626 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 4627 4628 for (; sw_cons != hw_cons; 4629 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 4630 4631 4632 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 4633 4634 cid = SW_CID(elem->message.data.cfc_del_event.cid); 4635 opcode = elem->message.opcode; 4636 4637 4638 /* handle eq element */ 4639 switch (opcode) { 4640 case EVENT_RING_OPCODE_STAT_QUERY: 4641 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n", 4642 bp->stats_comp++); 4643 /* nothing to do with stats comp */ 4644 goto next_spqe; 4645 4646 case EVENT_RING_OPCODE_CFC_DEL: 4647 /* handle according to cid range */ 4648 /* 4649 * we may want to verify here that the bp state is 4650 * HALTING 4651 */ 4652 DP(BNX2X_MSG_SP, 4653 "got delete ramrod for MULTI[%d]\n", cid); 4654#ifdef BCM_CNIC 4655 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 4656 goto next_spqe; 4657#endif 4658 q_obj = bnx2x_cid_to_q_obj(bp, cid); 4659 4660 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 4661 break; 4662 4663 4664 4665 goto next_spqe; 4666 4667 case EVENT_RING_OPCODE_STOP_TRAFFIC: 4668 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n"); 4669 if (f_obj->complete_cmd(bp, f_obj, 4670 BNX2X_F_CMD_TX_STOP)) 4671 break; 4672 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 4673 goto next_spqe; 4674 4675 case EVENT_RING_OPCODE_START_TRAFFIC: 4676 DP(BNX2X_MSG_SP, "got START TRAFFIC\n"); 4677 if (f_obj->complete_cmd(bp, f_obj, 4678 BNX2X_F_CMD_TX_START)) 4679 break; 4680 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 4681 goto next_spqe; 4682 case EVENT_RING_OPCODE_FUNCTION_START: 4683 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n"); 4684 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 4685 break; 4686 4687 goto next_spqe; 4688 4689 case EVENT_RING_OPCODE_FUNCTION_STOP: 4690 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n"); 4691 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 4692 break; 4693 4694 goto next_spqe; 4695 } 4696 4697 switch (opcode | bp->state) { 4698 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4699 BNX2X_STATE_OPEN): 4700 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4701 BNX2X_STATE_OPENING_WAIT4_PORT): 4702 cid = elem->message.data.eth_event.echo & 4703 BNX2X_SWCID_MASK; 4704 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 4705 cid); 4706 rss_raw->clear_pending(rss_raw); 4707 break; 4708 4709 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 4710 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 4711 case (EVENT_RING_OPCODE_SET_MAC | 4712 BNX2X_STATE_CLOSING_WAIT4_HALT): 4713 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4714 BNX2X_STATE_OPEN): 4715 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4716 BNX2X_STATE_DIAG): 4717 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4718 BNX2X_STATE_CLOSING_WAIT4_HALT): 4719 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); 4720 bnx2x_handle_classification_eqe(bp, elem); 4721 break; 4722 4723 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4724 BNX2X_STATE_OPEN): 4725 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4726 BNX2X_STATE_DIAG): 4727 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4728 BNX2X_STATE_CLOSING_WAIT4_HALT): 4729 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 4730 bnx2x_handle_mcast_eqe(bp); 4731 break; 4732 4733 case (EVENT_RING_OPCODE_FILTERS_RULES | 4734 BNX2X_STATE_OPEN): 4735 case (EVENT_RING_OPCODE_FILTERS_RULES | 4736 BNX2X_STATE_DIAG): 4737 case (EVENT_RING_OPCODE_FILTERS_RULES | 4738 BNX2X_STATE_CLOSING_WAIT4_HALT): 4739 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 4740 bnx2x_handle_rx_mode_eqe(bp); 4741 break; 4742 default: 4743 /* unknown event log error and continue */ 4744 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 4745 elem->message.opcode, bp->state); 4746 } 4747next_spqe: 4748 spqe_cnt++; 4749 } /* for */ 4750 4751 smp_mb__before_atomic_inc(); 4752 atomic_add(spqe_cnt, &bp->eq_spq_left); 4753 4754 bp->eq_cons = sw_cons; 4755 bp->eq_prod = sw_prod; 4756 /* Make sure that above mem writes were issued towards the memory */ 4757 smp_wmb(); 4758 4759 /* update producer */ 4760 bnx2x_update_eq_prod(bp, bp->eq_prod); 4761} 4762 4763static void bnx2x_sp_task(struct work_struct *work) 4764{ 4765 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 4766 u16 status; 4767 4768 status = bnx2x_update_dsb_idx(bp); 4769/* if (status == 0) */ 4770/* BNX2X_ERR("spurious slowpath interrupt!\n"); */ 4771 4772 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status); 4773 4774 /* HW attentions */ 4775 if (status & BNX2X_DEF_SB_ATT_IDX) { 4776 bnx2x_attn_int(bp); 4777 status &= ~BNX2X_DEF_SB_ATT_IDX; 4778 } 4779 4780 /* SP events: STAT_QUERY and others */ 4781 if (status & BNX2X_DEF_SB_IDX) { 4782#ifdef BCM_CNIC 4783 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 4784 4785 if ((!NO_FCOE(bp)) && 4786 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 4787 /* 4788 * Prevent local bottom-halves from running as 4789 * we are going to change the local NAPI list. 4790 */ 4791 local_bh_disable(); 4792 napi_schedule(&bnx2x_fcoe(bp, napi)); 4793 local_bh_enable(); 4794 } 4795#endif 4796 /* Handle EQ completions */ 4797 bnx2x_eq_int(bp); 4798 4799 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 4800 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 4801 4802 status &= ~BNX2X_DEF_SB_IDX; 4803 } 4804 4805 if (unlikely(status)) 4806 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 4807 status); 4808 4809 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 4810 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 4811} 4812 4813irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 4814{ 4815 struct net_device *dev = dev_instance; 4816 struct bnx2x *bp = netdev_priv(dev); 4817 4818 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 4819 IGU_INT_DISABLE, 0); 4820 4821#ifdef BNX2X_STOP_ON_ERROR 4822 if (unlikely(bp->panic)) 4823 return IRQ_HANDLED; 4824#endif 4825 4826#ifdef BCM_CNIC 4827 { 4828 struct cnic_ops *c_ops; 4829 4830 rcu_read_lock(); 4831 c_ops = rcu_dereference(bp->cnic_ops); 4832 if (c_ops) 4833 c_ops->cnic_handler(bp->cnic_data, NULL); 4834 rcu_read_unlock(); 4835 } 4836#endif 4837 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 4838 4839 return IRQ_HANDLED; 4840} 4841 4842/* end of slow path */ 4843 4844 4845void bnx2x_drv_pulse(struct bnx2x *bp) 4846{ 4847 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 4848 bp->fw_drv_pulse_wr_seq); 4849} 4850 4851 4852static void bnx2x_timer(unsigned long data) 4853{ 4854 struct bnx2x *bp = (struct bnx2x *) data; 4855 4856 if (!netif_running(bp->dev)) 4857 return; 4858 4859 if (!BP_NOMCP(bp)) { 4860 int mb_idx = BP_FW_MB_IDX(bp); 4861 u32 drv_pulse; 4862 u32 mcp_pulse; 4863 4864 ++bp->fw_drv_pulse_wr_seq; 4865 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 4866 /* TBD - add SYSTEM_TIME */ 4867 drv_pulse = bp->fw_drv_pulse_wr_seq; 4868 bnx2x_drv_pulse(bp); 4869 4870 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 4871 MCP_PULSE_SEQ_MASK); 4872 /* The delta between driver pulse and mcp response 4873 * should be 1 (before mcp response) or 0 (after mcp response) 4874 */ 4875 if ((drv_pulse != mcp_pulse) && 4876 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 4877 /* someone lost a heartbeat... */ 4878 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 4879 drv_pulse, mcp_pulse); 4880 } 4881 } 4882 4883 if (bp->state == BNX2X_STATE_OPEN) 4884 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 4885 4886 mod_timer(&bp->timer, jiffies + bp->current_interval); 4887} 4888 4889/* end of Statistics */ 4890 4891/* nic init */ 4892 4893/* 4894 * nic init service functions 4895 */ 4896 4897static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 4898{ 4899 u32 i; 4900 if (!(len%4) && !(addr%4)) 4901 for (i = 0; i < len; i += 4) 4902 REG_WR(bp, addr + i, fill); 4903 else 4904 for (i = 0; i < len; i++) 4905 REG_WR8(bp, addr + i, fill); 4906 4907} 4908 4909/* helper: writes FP SP data to FW - data_size in dwords */ 4910static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 4911 int fw_sb_id, 4912 u32 *sb_data_p, 4913 u32 data_size) 4914{ 4915 int index; 4916 for (index = 0; index < data_size; index++) 4917 REG_WR(bp, BAR_CSTRORM_INTMEM + 4918 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 4919 sizeof(u32)*index, 4920 *(sb_data_p + index)); 4921} 4922 4923static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 4924{ 4925 u32 *sb_data_p; 4926 u32 data_size = 0; 4927 struct hc_status_block_data_e2 sb_data_e2; 4928 struct hc_status_block_data_e1x sb_data_e1x; 4929 4930 /* disable the function first */ 4931 if (!CHIP_IS_E1x(bp)) { 4932 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 4933 sb_data_e2.common.state = SB_DISABLED; 4934 sb_data_e2.common.p_func.vf_valid = false; 4935 sb_data_p = (u32 *)&sb_data_e2; 4936 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 4937 } else { 4938 memset(&sb_data_e1x, 0, 4939 sizeof(struct hc_status_block_data_e1x)); 4940 sb_data_e1x.common.state = SB_DISABLED; 4941 sb_data_e1x.common.p_func.vf_valid = false; 4942 sb_data_p = (u32 *)&sb_data_e1x; 4943 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 4944 } 4945 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 4946 4947 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4948 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 4949 CSTORM_STATUS_BLOCK_SIZE); 4950 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4951 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 4952 CSTORM_SYNC_BLOCK_SIZE); 4953} 4954 4955/* helper: writes SP SB data to FW */ 4956static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 4957 struct hc_sp_status_block_data *sp_sb_data) 4958{ 4959 int func = BP_FUNC(bp); 4960 int i; 4961 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 4962 REG_WR(bp, BAR_CSTRORM_INTMEM + 4963 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 4964 i*sizeof(u32), 4965 *((u32 *)sp_sb_data + i)); 4966} 4967 4968static inline void bnx2x_zero_sp_sb(struct bnx2x *bp) 4969{ 4970 int func = BP_FUNC(bp); 4971 struct hc_sp_status_block_data sp_sb_data; 4972 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 4973 4974 sp_sb_data.state = SB_DISABLED; 4975 sp_sb_data.p_func.vf_valid = false; 4976 4977 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 4978 4979 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4980 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 4981 CSTORM_SP_STATUS_BLOCK_SIZE); 4982 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4983 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 4984 CSTORM_SP_SYNC_BLOCK_SIZE); 4985 4986} 4987 4988 4989static inline 4990void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 4991 int igu_sb_id, int igu_seg_id) 4992{ 4993 hc_sm->igu_sb_id = igu_sb_id; 4994 hc_sm->igu_seg_id = igu_seg_id; 4995 hc_sm->timer_value = 0xFF; 4996 hc_sm->time_to_expire = 0xFFFFFFFF; 4997} 4998 4999 5000/* allocates state machine ids. */ 5001static inline 5002void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) 5003{ 5004 /* zero out state machine indices */ 5005 /* rx indices */ 5006 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5007 5008 /* tx indices */ 5009 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5010 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 5011 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 5012 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 5013 5014 /* map indices */ 5015 /* rx indices */ 5016 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 5017 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5018 5019 /* tx indices */ 5020 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 5021 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5022 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 5023 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5024 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 5025 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5026 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 5027 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5028} 5029 5030static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 5031 u8 vf_valid, int fw_sb_id, int igu_sb_id) 5032{ 5033 int igu_seg_id; 5034 5035 struct hc_status_block_data_e2 sb_data_e2; 5036 struct hc_status_block_data_e1x sb_data_e1x; 5037 struct hc_status_block_sm *hc_sm_p; 5038 int data_size; 5039 u32 *sb_data_p; 5040 5041 if (CHIP_INT_MODE_IS_BC(bp)) 5042 igu_seg_id = HC_SEG_ACCESS_NORM; 5043 else 5044 igu_seg_id = IGU_SEG_ACCESS_NORM; 5045 5046 bnx2x_zero_fp_sb(bp, fw_sb_id); 5047 5048 if (!CHIP_IS_E1x(bp)) { 5049 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5050 sb_data_e2.common.state = SB_ENABLED; 5051 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 5052 sb_data_e2.common.p_func.vf_id = vfid; 5053 sb_data_e2.common.p_func.vf_valid = vf_valid; 5054 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 5055 sb_data_e2.common.same_igu_sb_1b = true; 5056 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 5057 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 5058 hc_sm_p = sb_data_e2.common.state_machine; 5059 sb_data_p = (u32 *)&sb_data_e2; 5060 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5061 bnx2x_map_sb_state_machines(sb_data_e2.index_data); 5062 } else { 5063 memset(&sb_data_e1x, 0, 5064 sizeof(struct hc_status_block_data_e1x)); 5065 sb_data_e1x.common.state = SB_ENABLED; 5066 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 5067 sb_data_e1x.common.p_func.vf_id = 0xff; 5068 sb_data_e1x.common.p_func.vf_valid = false; 5069 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 5070 sb_data_e1x.common.same_igu_sb_1b = true; 5071 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 5072 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 5073 hc_sm_p = sb_data_e1x.common.state_machine; 5074 sb_data_p = (u32 *)&sb_data_e1x; 5075 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5076 bnx2x_map_sb_state_machines(sb_data_e1x.index_data); 5077 } 5078 5079 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 5080 igu_sb_id, igu_seg_id); 5081 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 5082 igu_sb_id, igu_seg_id); 5083 5084 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id); 5085 5086 /* write indecies to HW */ 5087 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5088} 5089 5090static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 5091 u16 tx_usec, u16 rx_usec) 5092{ 5093 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 5094 false, rx_usec); 5095 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5096 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 5097 tx_usec); 5098 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5099 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 5100 tx_usec); 5101 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5102 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 5103 tx_usec); 5104} 5105 5106static void bnx2x_init_def_sb(struct bnx2x *bp) 5107{ 5108 struct host_sp_status_block *def_sb = bp->def_status_blk; 5109 dma_addr_t mapping = bp->def_status_blk_mapping; 5110 int igu_sp_sb_index; 5111 int igu_seg_id; 5112 int port = BP_PORT(bp); 5113 int func = BP_FUNC(bp); 5114 int reg_offset, reg_offset_en5; 5115 u64 section; 5116 int index; 5117 struct hc_sp_status_block_data sp_sb_data; 5118 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5119 5120 if (CHIP_INT_MODE_IS_BC(bp)) { 5121 igu_sp_sb_index = DEF_SB_IGU_ID; 5122 igu_seg_id = HC_SEG_ACCESS_DEF; 5123 } else { 5124 igu_sp_sb_index = bp->igu_dsb_id; 5125 igu_seg_id = IGU_SEG_ACCESS_DEF; 5126 } 5127 5128 /* ATTN */ 5129 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5130 atten_status_block); 5131 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 5132 5133 bp->attn_state = 0; 5134 5135 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 5136 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 5137 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 5138 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); 5139 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 5140 int sindex; 5141 /* take care of sig[0]..sig[4] */ 5142 for (sindex = 0; sindex < 4; sindex++) 5143 bp->attn_group[index].sig[sindex] = 5144 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 5145 5146 if (!CHIP_IS_E1x(bp)) 5147 /* 5148 * enable5 is separate from the rest of the registers, 5149 * and therefore the address skip is 4 5150 * and not 16 between the different groups 5151 */ 5152 bp->attn_group[index].sig[4] = REG_RD(bp, 5153 reg_offset_en5 + 0x4*index); 5154 else 5155 bp->attn_group[index].sig[4] = 0; 5156 } 5157 5158 if (bp->common.int_block == INT_BLOCK_HC) { 5159 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 5160 HC_REG_ATTN_MSG0_ADDR_L); 5161 5162 REG_WR(bp, reg_offset, U64_LO(section)); 5163 REG_WR(bp, reg_offset + 4, U64_HI(section)); 5164 } else if (!CHIP_IS_E1x(bp)) { 5165 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 5166 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 5167 } 5168 5169 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5170 sp_sb); 5171 5172 bnx2x_zero_sp_sb(bp); 5173 5174 sp_sb_data.state = SB_ENABLED; 5175 sp_sb_data.host_sb_addr.lo = U64_LO(section); 5176 sp_sb_data.host_sb_addr.hi = U64_HI(section); 5177 sp_sb_data.igu_sb_id = igu_sp_sb_index; 5178 sp_sb_data.igu_seg_id = igu_seg_id; 5179 sp_sb_data.p_func.pf_id = func; 5180 sp_sb_data.p_func.vnic_id = BP_VN(bp); 5181 sp_sb_data.p_func.vf_id = 0xff; 5182 5183 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5184 5185 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 5186} 5187 5188void bnx2x_update_coalesce(struct bnx2x *bp) 5189{ 5190 int i; 5191 5192 for_each_eth_queue(bp, i) 5193 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 5194 bp->tx_ticks, bp->rx_ticks); 5195} 5196 5197static void bnx2x_init_sp_ring(struct bnx2x *bp) 5198{ 5199 spin_lock_init(&bp->spq_lock); 5200 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 5201 5202 bp->spq_prod_idx = 0; 5203 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 5204 bp->spq_prod_bd = bp->spq; 5205 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 5206} 5207 5208static void bnx2x_init_eq_ring(struct bnx2x *bp) 5209{ 5210 int i; 5211 for (i = 1; i <= NUM_EQ_PAGES; i++) { 5212 union event_ring_elem *elem = 5213 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 5214 5215 elem->next_page.addr.hi = 5216 cpu_to_le32(U64_HI(bp->eq_mapping + 5217 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 5218 elem->next_page.addr.lo = 5219 cpu_to_le32(U64_LO(bp->eq_mapping + 5220 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 5221 } 5222 bp->eq_cons = 0; 5223 bp->eq_prod = NUM_EQ_DESC; 5224 bp->eq_cons_sb = BNX2X_EQ_INDEX; 5225 /* we want a warning message before it gets rought... */ 5226 atomic_set(&bp->eq_spq_left, 5227 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 5228} 5229 5230 5231/* called with netif_addr_lock_bh() */ 5232void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 5233 unsigned long rx_mode_flags, 5234 unsigned long rx_accept_flags, 5235 unsigned long tx_accept_flags, 5236 unsigned long ramrod_flags) 5237{ 5238 struct bnx2x_rx_mode_ramrod_params ramrod_param; 5239 int rc; 5240 5241 memset(&ramrod_param, 0, sizeof(ramrod_param)); 5242 5243 /* Prepare ramrod parameters */ 5244 ramrod_param.cid = 0; 5245 ramrod_param.cl_id = cl_id; 5246 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 5247 ramrod_param.func_id = BP_FUNC(bp); 5248 5249 ramrod_param.pstate = &bp->sp_state; 5250 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 5251 5252 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 5253 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 5254 5255 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5256 5257 ramrod_param.ramrod_flags = ramrod_flags; 5258 ramrod_param.rx_mode_flags = rx_mode_flags; 5259 5260 ramrod_param.rx_accept_flags = rx_accept_flags; 5261 ramrod_param.tx_accept_flags = tx_accept_flags; 5262 5263 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 5264 if (rc < 0) { 5265 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 5266 return; 5267 } 5268} 5269 5270/* called with netif_addr_lock_bh() */ 5271void bnx2x_set_storm_rx_mode(struct bnx2x *bp) 5272{ 5273 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 5274 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 5275 5276#ifdef BCM_CNIC 5277 if (!NO_FCOE(bp)) 5278 5279 /* Configure rx_mode of FCoE Queue */ 5280 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 5281#endif 5282 5283 switch (bp->rx_mode) { 5284 case BNX2X_RX_MODE_NONE: 5285 /* 5286 * 'drop all' supersedes any accept flags that may have been 5287 * passed to the function. 5288 */ 5289 break; 5290 case BNX2X_RX_MODE_NORMAL: 5291 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5292 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); 5293 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5294 5295 /* internal switching mode */ 5296 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5297 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); 5298 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5299 5300 break; 5301 case BNX2X_RX_MODE_ALLMULTI: 5302 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5303 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5304 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5305 5306 /* internal switching mode */ 5307 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5308 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5309 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5310 5311 break; 5312 case BNX2X_RX_MODE_PROMISC: 5313 /* According to deffinition of SI mode, iface in promisc mode 5314 * should receive matched and unmatched (in resolution of port) 5315 * unicast packets. 5316 */ 5317 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); 5318 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5319 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5320 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5321 5322 /* internal switching mode */ 5323 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5324 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5325 5326 if (IS_MF_SI(bp)) 5327 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); 5328 else 5329 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5330 5331 break; 5332 default: 5333 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); 5334 return; 5335 } 5336 5337 if (bp->rx_mode != BNX2X_RX_MODE_NONE) { 5338 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); 5339 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); 5340 } 5341 5342 __set_bit(RAMROD_RX, &ramrod_flags); 5343 __set_bit(RAMROD_TX, &ramrod_flags); 5344 5345 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, 5346 tx_accept_flags, ramrod_flags); 5347} 5348 5349static void bnx2x_init_internal_common(struct bnx2x *bp) 5350{ 5351 int i; 5352 5353 if (IS_MF_SI(bp)) 5354 /* 5355 * In switch independent mode, the TSTORM needs to accept 5356 * packets that failed classification, since approximate match 5357 * mac addresses aren't written to NIG LLH 5358 */ 5359 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5360 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); 5361 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ 5362 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5363 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); 5364 5365 /* Zero this manually as its initialization is 5366 currently missing in the initTool */ 5367 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 5368 REG_WR(bp, BAR_USTRORM_INTMEM + 5369 USTORM_AGG_DATA_OFFSET + i * 4, 0); 5370 if (!CHIP_IS_E1x(bp)) { 5371 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 5372 CHIP_INT_MODE_IS_BC(bp) ? 5373 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 5374 } 5375} 5376 5377static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 5378{ 5379 switch (load_code) { 5380 case FW_MSG_CODE_DRV_LOAD_COMMON: 5381 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5382 bnx2x_init_internal_common(bp); 5383 /* no break */ 5384 5385 case FW_MSG_CODE_DRV_LOAD_PORT: 5386 /* nothing to do */ 5387 /* no break */ 5388 5389 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5390 /* internal memory per function is 5391 initialized inside bnx2x_pf_init */ 5392 break; 5393 5394 default: 5395 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5396 break; 5397 } 5398} 5399 5400static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 5401{ 5402 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; 5403} 5404 5405static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 5406{ 5407 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; 5408} 5409 5410static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 5411{ 5412 if (CHIP_IS_E1x(fp->bp)) 5413 return BP_L_ID(fp->bp) + fp->index; 5414 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 5415 return bnx2x_fp_igu_sb_id(fp); 5416} 5417 5418static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 5419{ 5420 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 5421 u8 cos; 5422 unsigned long q_type = 0; 5423 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 5424 fp->rx_queue = fp_idx; 5425 fp->cid = fp_idx; 5426 fp->cl_id = bnx2x_fp_cl_id(fp); 5427 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 5428 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 5429 /* qZone id equals to FW (per path) client id */ 5430 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 5431 5432 /* init shortcut */ 5433 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 5434 5435 /* Setup SB indicies */ 5436 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 5437 5438 /* Configure Queue State object */ 5439 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 5440 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 5441 5442 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 5443 5444 /* init tx data */ 5445 for_each_cos_in_tx_queue(fp, cos) { 5446 bnx2x_init_txdata(bp, &fp->txdata[cos], 5447 CID_COS_TO_TX_ONLY_CID(fp->cid, cos), 5448 FP_COS_TO_TXQ(fp, cos), 5449 BNX2X_TX_SB_INDEX_BASE + cos); 5450 cids[cos] = fp->txdata[cos].cid; 5451 } 5452 5453 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos, 5454 BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 5455 bnx2x_sp_mapping(bp, q_rdata), q_type); 5456 5457 /** 5458 * Configure classification DBs: Always enable Tx switching 5459 */ 5460 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 5461 5462 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) " 5463 "cl_id %d fw_sb %d igu_sb %d\n", 5464 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 5465 fp->igu_sb_id); 5466 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 5467 fp->fw_sb_id, fp->igu_sb_id); 5468 5469 bnx2x_update_fpsb_idx(fp); 5470} 5471 5472void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) 5473{ 5474 int i; 5475 5476 for_each_eth_queue(bp, i) 5477 bnx2x_init_eth_fp(bp, i); 5478#ifdef BCM_CNIC 5479 if (!NO_FCOE(bp)) 5480 bnx2x_init_fcoe_fp(bp); 5481 5482 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 5483 BNX2X_VF_ID_INVALID, false, 5484 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 5485 5486#endif 5487 5488 /* Initialize MOD_ABS interrupts */ 5489 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 5490 bp->common.shmem_base, bp->common.shmem2_base, 5491 BP_PORT(bp)); 5492 /* ensure status block indices were read */ 5493 rmb(); 5494 5495 bnx2x_init_def_sb(bp); 5496 bnx2x_update_dsb_idx(bp); 5497 bnx2x_init_rx_rings(bp); 5498 bnx2x_init_tx_rings(bp); 5499 bnx2x_init_sp_ring(bp); 5500 bnx2x_init_eq_ring(bp); 5501 bnx2x_init_internal(bp, load_code); 5502 bnx2x_pf_init(bp); 5503 bnx2x_stats_init(bp); 5504 5505 /* flush all before enabling interrupts */ 5506 mb(); 5507 mmiowb(); 5508 5509 bnx2x_int_enable(bp); 5510 5511 /* Check for SPIO5 */ 5512 bnx2x_attn_int_deasserted0(bp, 5513 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 5514 AEU_INPUTS_ATTN_BITS_SPIO5); 5515} 5516 5517/* end of nic init */ 5518 5519/* 5520 * gzip service functions 5521 */ 5522 5523static int bnx2x_gunzip_init(struct bnx2x *bp) 5524{ 5525 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 5526 &bp->gunzip_mapping, GFP_KERNEL); 5527 if (bp->gunzip_buf == NULL) 5528 goto gunzip_nomem1; 5529 5530 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 5531 if (bp->strm == NULL) 5532 goto gunzip_nomem2; 5533 5534 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 5535 if (bp->strm->workspace == NULL) 5536 goto gunzip_nomem3; 5537 5538 return 0; 5539 5540gunzip_nomem3: 5541 kfree(bp->strm); 5542 bp->strm = NULL; 5543 5544gunzip_nomem2: 5545 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5546 bp->gunzip_mapping); 5547 bp->gunzip_buf = NULL; 5548 5549gunzip_nomem1: 5550 netdev_err(bp->dev, "Cannot allocate firmware buffer for" 5551 " un-compression\n"); 5552 return -ENOMEM; 5553} 5554 5555static void bnx2x_gunzip_end(struct bnx2x *bp) 5556{ 5557 if (bp->strm) { 5558 vfree(bp->strm->workspace); 5559 kfree(bp->strm); 5560 bp->strm = NULL; 5561 } 5562 5563 if (bp->gunzip_buf) { 5564 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5565 bp->gunzip_mapping); 5566 bp->gunzip_buf = NULL; 5567 } 5568} 5569 5570static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 5571{ 5572 int n, rc; 5573 5574 /* check gzip header */ 5575 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 5576 BNX2X_ERR("Bad gzip header\n"); 5577 return -EINVAL; 5578 } 5579 5580 n = 10; 5581 5582#define FNAME 0x8 5583 5584 if (zbuf[3] & FNAME) 5585 while ((zbuf[n++] != 0) && (n < len)); 5586 5587 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 5588 bp->strm->avail_in = len - n; 5589 bp->strm->next_out = bp->gunzip_buf; 5590 bp->strm->avail_out = FW_BUF_SIZE; 5591 5592 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 5593 if (rc != Z_OK) 5594 return rc; 5595 5596 rc = zlib_inflate(bp->strm, Z_FINISH); 5597 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 5598 netdev_err(bp->dev, "Firmware decompression error: %s\n", 5599 bp->strm->msg); 5600 5601 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 5602 if (bp->gunzip_outlen & 0x3) 5603 netdev_err(bp->dev, "Firmware decompression error:" 5604 " gunzip_outlen (%d) not aligned\n", 5605 bp->gunzip_outlen); 5606 bp->gunzip_outlen >>= 2; 5607 5608 zlib_inflateEnd(bp->strm); 5609 5610 if (rc == Z_STREAM_END) 5611 return 0; 5612 5613 return rc; 5614} 5615 5616/* nic load/unload */ 5617 5618/* 5619 * General service functions 5620 */ 5621 5622/* send a NIG loopback debug packet */ 5623static void bnx2x_lb_pckt(struct bnx2x *bp) 5624{ 5625 u32 wb_write[3]; 5626 5627 /* Ethernet source and destination addresses */ 5628 wb_write[0] = 0x55555555; 5629 wb_write[1] = 0x55555555; 5630 wb_write[2] = 0x20; /* SOP */ 5631 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5632 5633 /* NON-IP protocol */ 5634 wb_write[0] = 0x09000000; 5635 wb_write[1] = 0x55555555; 5636 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 5637 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5638} 5639 5640/* some of the internal memories 5641 * are not directly readable from the driver 5642 * to test them we send debug packets 5643 */ 5644static int bnx2x_int_mem_test(struct bnx2x *bp) 5645{ 5646 int factor; 5647 int count, i; 5648 u32 val = 0; 5649 5650 if (CHIP_REV_IS_FPGA(bp)) 5651 factor = 120; 5652 else if (CHIP_REV_IS_EMUL(bp)) 5653 factor = 200; 5654 else 5655 factor = 1; 5656 5657 /* Disable inputs of parser neighbor blocks */ 5658 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5659 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5660 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5661 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5662 5663 /* Write 0 to parser credits for CFC search request */ 5664 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5665 5666 /* send Ethernet packet */ 5667 bnx2x_lb_pckt(bp); 5668 5669 /* TODO do i reset NIG statistic? */ 5670 /* Wait until NIG register shows 1 packet of size 0x10 */ 5671 count = 1000 * factor; 5672 while (count) { 5673 5674 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5675 val = *bnx2x_sp(bp, wb_data[0]); 5676 if (val == 0x10) 5677 break; 5678 5679 msleep(10); 5680 count--; 5681 } 5682 if (val != 0x10) { 5683 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5684 return -1; 5685 } 5686 5687 /* Wait until PRS register shows 1 packet */ 5688 count = 1000 * factor; 5689 while (count) { 5690 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5691 if (val == 1) 5692 break; 5693 5694 msleep(10); 5695 count--; 5696 } 5697 if (val != 0x1) { 5698 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5699 return -2; 5700 } 5701 5702 /* Reset and init BRB, PRS */ 5703 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5704 msleep(50); 5705 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5706 msleep(50); 5707 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5708 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5709 5710 DP(NETIF_MSG_HW, "part2\n"); 5711 5712 /* Disable inputs of parser neighbor blocks */ 5713 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5714 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5715 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5716 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5717 5718 /* Write 0 to parser credits for CFC search request */ 5719 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5720 5721 /* send 10 Ethernet packets */ 5722 for (i = 0; i < 10; i++) 5723 bnx2x_lb_pckt(bp); 5724 5725 /* Wait until NIG register shows 10 + 1 5726 packets of size 11*0x10 = 0xb0 */ 5727 count = 1000 * factor; 5728 while (count) { 5729 5730 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5731 val = *bnx2x_sp(bp, wb_data[0]); 5732 if (val == 0xb0) 5733 break; 5734 5735 msleep(10); 5736 count--; 5737 } 5738 if (val != 0xb0) { 5739 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5740 return -3; 5741 } 5742 5743 /* Wait until PRS register shows 2 packets */ 5744 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5745 if (val != 2) 5746 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5747 5748 /* Write 1 to parser credits for CFC search request */ 5749 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 5750 5751 /* Wait until PRS register shows 3 packets */ 5752 msleep(10 * factor); 5753 /* Wait until NIG register shows 1 packet of size 0x10 */ 5754 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5755 if (val != 3) 5756 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5757 5758 /* clear NIG EOP FIFO */ 5759 for (i = 0; i < 11; i++) 5760 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 5761 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 5762 if (val != 1) { 5763 BNX2X_ERR("clear of NIG failed\n"); 5764 return -4; 5765 } 5766 5767 /* Reset and init BRB, PRS, NIG */ 5768 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5769 msleep(50); 5770 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5771 msleep(50); 5772 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5773 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5774#ifndef BCM_CNIC 5775 /* set NIC mode */ 5776 REG_WR(bp, PRS_REG_NIC_MODE, 1); 5777#endif 5778 5779 /* Enable inputs of parser neighbor blocks */ 5780 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 5781 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 5782 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 5783 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 5784 5785 DP(NETIF_MSG_HW, "done\n"); 5786 5787 return 0; /* OK */ 5788} 5789 5790static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 5791{ 5792 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 5793 if (!CHIP_IS_E1x(bp)) 5794 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 5795 else 5796 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 5797 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 5798 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 5799 /* 5800 * mask read length error interrupts in brb for parser 5801 * (parsing unit and 'checksum and crc' unit) 5802 * these errors are legal (PU reads fixed length and CAC can cause 5803 * read length error on truncated packets) 5804 */ 5805 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 5806 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 5807 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 5808 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 5809 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 5810 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 5811/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 5812/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 5813 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 5814 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 5815 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 5816/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 5817/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 5818 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 5819 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 5820 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 5821 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 5822/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 5823/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 5824 5825 if (CHIP_REV_IS_FPGA(bp)) 5826 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); 5827 else if (!CHIP_IS_E1x(bp)) 5828 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 5829 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF 5830 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT 5831 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN 5832 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED 5833 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); 5834 else 5835 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); 5836 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 5837 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 5838 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 5839/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 5840 5841 if (!CHIP_IS_E1x(bp)) 5842 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 5843 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 5844 5845 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 5846 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 5847/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 5848 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 5849} 5850 5851static void bnx2x_reset_common(struct bnx2x *bp) 5852{ 5853 u32 val = 0x1400; 5854 5855 /* reset_common */ 5856 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 5857 0xd3ffff7f); 5858 5859 if (CHIP_IS_E3(bp)) { 5860 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 5861 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 5862 } 5863 5864 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); 5865} 5866 5867static void bnx2x_setup_dmae(struct bnx2x *bp) 5868{ 5869 bp->dmae_ready = 0; 5870 spin_lock_init(&bp->dmae_lock); 5871} 5872 5873static void bnx2x_init_pxp(struct bnx2x *bp) 5874{ 5875 u16 devctl; 5876 int r_order, w_order; 5877 5878 pci_read_config_word(bp->pdev, 5879 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); 5880 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); 5881 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 5882 if (bp->mrrs == -1) 5883 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); 5884 else { 5885 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); 5886 r_order = bp->mrrs; 5887 } 5888 5889 bnx2x_init_pxp_arb(bp, r_order, w_order); 5890} 5891 5892static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 5893{ 5894 int is_required; 5895 u32 val; 5896 int port; 5897 5898 if (BP_NOMCP(bp)) 5899 return; 5900 5901 is_required = 0; 5902 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 5903 SHARED_HW_CFG_FAN_FAILURE_MASK; 5904 5905 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) 5906 is_required = 1; 5907 5908 /* 5909 * The fan failure mechanism is usually related to the PHY type since 5910 * the power consumption of the board is affected by the PHY. Currently, 5911 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 5912 */ 5913 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 5914 for (port = PORT_0; port < PORT_MAX; port++) { 5915 is_required |= 5916 bnx2x_fan_failure_det_req( 5917 bp, 5918 bp->common.shmem_base, 5919 bp->common.shmem2_base, 5920 port); 5921 } 5922 5923 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 5924 5925 if (is_required == 0) 5926 return; 5927 5928 /* Fan failure is indicated by SPIO 5 */ 5929 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, 5930 MISC_REGISTERS_SPIO_INPUT_HI_Z); 5931 5932 /* set to active low mode */ 5933 val = REG_RD(bp, MISC_REG_SPIO_INT); 5934 val |= ((1 << MISC_REGISTERS_SPIO_5) << 5935 MISC_REGISTERS_SPIO_INT_OLD_SET_POS); 5936 REG_WR(bp, MISC_REG_SPIO_INT, val); 5937 5938 /* enable interrupt to signal the IGU */ 5939 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 5940 val |= (1 << MISC_REGISTERS_SPIO_5); 5941 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 5942} 5943 5944static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) 5945{ 5946 u32 offset = 0; 5947 5948 if (CHIP_IS_E1(bp)) 5949 return; 5950 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) 5951 return; 5952 5953 switch (BP_ABS_FUNC(bp)) { 5954 case 0: 5955 offset = PXP2_REG_PGL_PRETEND_FUNC_F0; 5956 break; 5957 case 1: 5958 offset = PXP2_REG_PGL_PRETEND_FUNC_F1; 5959 break; 5960 case 2: 5961 offset = PXP2_REG_PGL_PRETEND_FUNC_F2; 5962 break; 5963 case 3: 5964 offset = PXP2_REG_PGL_PRETEND_FUNC_F3; 5965 break; 5966 case 4: 5967 offset = PXP2_REG_PGL_PRETEND_FUNC_F4; 5968 break; 5969 case 5: 5970 offset = PXP2_REG_PGL_PRETEND_FUNC_F5; 5971 break; 5972 case 6: 5973 offset = PXP2_REG_PGL_PRETEND_FUNC_F6; 5974 break; 5975 case 7: 5976 offset = PXP2_REG_PGL_PRETEND_FUNC_F7; 5977 break; 5978 default: 5979 return; 5980 } 5981 5982 REG_WR(bp, offset, pretend_func_num); 5983 REG_RD(bp, offset); 5984 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); 5985} 5986 5987void bnx2x_pf_disable(struct bnx2x *bp) 5988{ 5989 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 5990 val &= ~IGU_PF_CONF_FUNC_EN; 5991 5992 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 5993 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 5994 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); 5995} 5996 5997static inline void bnx2x__common_init_phy(struct bnx2x *bp) 5998{ 5999 u32 shmem_base[2], shmem2_base[2]; 6000 shmem_base[0] = bp->common.shmem_base; 6001 shmem2_base[0] = bp->common.shmem2_base; 6002 if (!CHIP_IS_E1x(bp)) { 6003 shmem_base[1] = 6004 SHMEM2_RD(bp, other_shmem_base_addr); 6005 shmem2_base[1] = 6006 SHMEM2_RD(bp, other_shmem2_base_addr); 6007 } 6008 bnx2x_acquire_phy_lock(bp); 6009 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, 6010 bp->common.chip_id); 6011 bnx2x_release_phy_lock(bp); 6012} 6013 6014/** 6015 * bnx2x_init_hw_common - initialize the HW at the COMMON phase. 6016 * 6017 * @bp: driver handle 6018 */ 6019static int bnx2x_init_hw_common(struct bnx2x *bp) 6020{ 6021 u32 val; 6022 6023 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp)); 6024 6025 /* 6026 * take the UNDI lock to protect undi_unload flow from accessing 6027 * registers while we're resetting the chip 6028 */ 6029 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6030 6031 bnx2x_reset_common(bp); 6032 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 6033 6034 val = 0xfffc; 6035 if (CHIP_IS_E3(bp)) { 6036 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 6037 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 6038 } 6039 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 6040 6041 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6042 6043 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 6044 6045 if (!CHIP_IS_E1x(bp)) { 6046 u8 abs_func_id; 6047 6048 /** 6049 * 4-port mode or 2-port mode we need to turn of master-enable 6050 * for everyone, after that, turn it back on for self. 6051 * so, we disregard multi-function or not, and always disable 6052 * for all functions on the given path, this means 0,2,4,6 for 6053 * path 0 and 1,3,5,7 for path 1 6054 */ 6055 for (abs_func_id = BP_PATH(bp); 6056 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { 6057 if (abs_func_id == BP_ABS_FUNC(bp)) { 6058 REG_WR(bp, 6059 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 6060 1); 6061 continue; 6062 } 6063 6064 bnx2x_pretend_func(bp, abs_func_id); 6065 /* clear pf enable */ 6066 bnx2x_pf_disable(bp); 6067 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6068 } 6069 } 6070 6071 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); 6072 if (CHIP_IS_E1(bp)) { 6073 /* enable HW interrupt from PXP on USDM overflow 6074 bit 16 on INT_MASK_0 */ 6075 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 6076 } 6077 6078 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); 6079 bnx2x_init_pxp(bp); 6080 6081#ifdef __BIG_ENDIAN 6082 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); 6083 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); 6084 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 6085 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 6086 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 6087 /* make sure this value is 0 */ 6088 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); 6089 6090/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ 6091 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); 6092 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); 6093 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); 6094 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 6095#endif 6096 6097 bnx2x_ilt_init_page_size(bp, INITOP_SET); 6098 6099 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 6100 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 6101 6102 /* let the HW do it's magic ... */ 6103 msleep(100); 6104 /* finish PXP init */ 6105 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); 6106 if (val != 1) { 6107 BNX2X_ERR("PXP2 CFG failed\n"); 6108 return -EBUSY; 6109 } 6110 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); 6111 if (val != 1) { 6112 BNX2X_ERR("PXP2 RD_INIT failed\n"); 6113 return -EBUSY; 6114 } 6115 6116 /* Timers bug workaround E2 only. We need to set the entire ILT to 6117 * have entries with value "0" and valid bit on. 6118 * This needs to be done by the first PF that is loaded in a path 6119 * (i.e. common phase) 6120 */ 6121 if (!CHIP_IS_E1x(bp)) { 6122/* In E2 there is a bug in the timers block that can cause function 6 / 7 6123 * (i.e. vnic3) to start even if it is marked as "scan-off". 6124 * This occurs when a different function (func2,3) is being marked 6125 * as "scan-off". Real-life scenario for example: if a driver is being 6126 * load-unloaded while func6,7 are down. This will cause the timer to access 6127 * the ilt, translate to a logical address and send a request to read/write. 6128 * Since the ilt for the function that is down is not valid, this will cause 6129 * a translation error which is unrecoverable. 6130 * The Workaround is intended to make sure that when this happens nothing fatal 6131 * will occur. The workaround: 6132 * 1. First PF driver which loads on a path will: 6133 * a. After taking the chip out of reset, by using pretend, 6134 * it will write "0" to the following registers of 6135 * the other vnics. 6136 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6137 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 6138 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 6139 * And for itself it will write '1' to 6140 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 6141 * dmae-operations (writing to pram for example.) 6142 * note: can be done for only function 6,7 but cleaner this 6143 * way. 6144 * b. Write zero+valid to the entire ILT. 6145 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 6146 * VNIC3 (of that port). The range allocated will be the 6147 * entire ILT. This is needed to prevent ILT range error. 6148 * 2. Any PF driver load flow: 6149 * a. ILT update with the physical addresses of the allocated 6150 * logical pages. 6151 * b. Wait 20msec. - note that this timeout is needed to make 6152 * sure there are no requests in one of the PXP internal 6153 * queues with "old" ILT addresses. 6154 * c. PF enable in the PGLC. 6155 * d. Clear the was_error of the PF in the PGLC. (could have 6156 * occured while driver was down) 6157 * e. PF enable in the CFC (WEAK + STRONG) 6158 * f. Timers scan enable 6159 * 3. PF driver unload flow: 6160 * a. Clear the Timers scan_en. 6161 * b. Polling for scan_on=0 for that PF. 6162 * c. Clear the PF enable bit in the PXP. 6163 * d. Clear the PF enable in the CFC (WEAK + STRONG) 6164 * e. Write zero+valid to all ILT entries (The valid bit must 6165 * stay set) 6166 * f. If this is VNIC 3 of a port then also init 6167 * first_timers_ilt_entry to zero and last_timers_ilt_entry 6168 * to the last enrty in the ILT. 6169 * 6170 * Notes: 6171 * Currently the PF error in the PGLC is non recoverable. 6172 * In the future the there will be a recovery routine for this error. 6173 * Currently attention is masked. 6174 * Having an MCP lock on the load/unload process does not guarantee that 6175 * there is no Timer disable during Func6/7 enable. This is because the 6176 * Timers scan is currently being cleared by the MCP on FLR. 6177 * Step 2.d can be done only for PF6/7 and the driver can also check if 6178 * there is error before clearing it. But the flow above is simpler and 6179 * more general. 6180 * All ILT entries are written by zero+valid and not just PF6/7 6181 * ILT entries since in the future the ILT entries allocation for 6182 * PF-s might be dynamic. 6183 */ 6184 struct ilt_client_info ilt_cli; 6185 struct bnx2x_ilt ilt; 6186 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 6187 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); 6188 6189 /* initialize dummy TM client */ 6190 ilt_cli.start = 0; 6191 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 6192 ilt_cli.client_num = ILT_CLIENT_TM; 6193 6194 /* Step 1: set zeroes to all ilt page entries with valid bit on 6195 * Step 2: set the timers first/last ilt entry to point 6196 * to the entire range to prevent ILT range error for 3rd/4th 6197 * vnic (this code assumes existance of the vnic) 6198 * 6199 * both steps performed by call to bnx2x_ilt_client_init_op() 6200 * with dummy TM client 6201 * 6202 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 6203 * and his brother are split registers 6204 */ 6205 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); 6206 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); 6207 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6208 6209 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); 6210 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); 6211 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 6212 } 6213 6214 6215 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 6216 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 6217 6218 if (!CHIP_IS_E1x(bp)) { 6219 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : 6220 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); 6221 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); 6222 6223 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); 6224 6225 /* let the HW do it's magic ... */ 6226 do { 6227 msleep(200); 6228 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); 6229 } while (factor-- && (val != 1)); 6230 6231 if (val != 1) { 6232 BNX2X_ERR("ATC_INIT failed\n"); 6233 return -EBUSY; 6234 } 6235 } 6236 6237 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); 6238 6239 /* clean the DMAE memory */ 6240 bp->dmae_ready = 1; 6241 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); 6242 6243 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); 6244 6245 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); 6246 6247 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); 6248 6249 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); 6250 6251 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); 6252 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); 6253 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); 6254 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); 6255 6256 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); 6257 6258 6259 /* QM queues pointers table */ 6260 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); 6261 6262 /* soft reset pulse */ 6263 REG_WR(bp, QM_REG_SOFT_RESET, 1); 6264 REG_WR(bp, QM_REG_SOFT_RESET, 0); 6265 6266#ifdef BCM_CNIC 6267 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); 6268#endif 6269 6270 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); 6271 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); 6272 if (!CHIP_REV_IS_SLOW(bp)) 6273 /* enable hw interrupt from doorbell Q */ 6274 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6275 6276 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6277 6278 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6279 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 6280 6281 if (!CHIP_IS_E1(bp)) 6282 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); 6283 6284 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) 6285 /* Bit-map indicating which L2 hdrs may appear 6286 * after the basic Ethernet header 6287 */ 6288 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 6289 bp->path_has_ovlan ? 7 : 6); 6290 6291 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); 6292 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); 6293 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); 6294 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); 6295 6296 if (!CHIP_IS_E1x(bp)) { 6297 /* reset VFC memories */ 6298 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6299 VFC_MEMORIES_RST_REG_CAM_RST | 6300 VFC_MEMORIES_RST_REG_RAM_RST); 6301 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6302 VFC_MEMORIES_RST_REG_CAM_RST | 6303 VFC_MEMORIES_RST_REG_RAM_RST); 6304 6305 msleep(20); 6306 } 6307 6308 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); 6309 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); 6310 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); 6311 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); 6312 6313 /* sync semi rtc */ 6314 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6315 0x80000000); 6316 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 6317 0x80000000); 6318 6319 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); 6320 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); 6321 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); 6322 6323 if (!CHIP_IS_E1x(bp)) 6324 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 6325 bp->path_has_ovlan ? 7 : 6); 6326 6327 REG_WR(bp, SRC_REG_SOFT_RST, 1); 6328 6329 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); 6330 6331#ifdef BCM_CNIC 6332 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 6333 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 6334 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); 6335 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); 6336 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); 6337 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 6338 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); 6339 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 6340 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); 6341 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); 6342#endif 6343 REG_WR(bp, SRC_REG_SOFT_RST, 0); 6344 6345 if (sizeof(union cdu_context) != 1024) 6346 /* we currently assume that a context is 1024 bytes */ 6347 dev_alert(&bp->pdev->dev, "please adjust the size " 6348 "of cdu_context(%ld)\n", 6349 (long)sizeof(union cdu_context)); 6350 6351 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 6352 val = (4 << 24) + (0 << 12) + 1024; 6353 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); 6354 6355 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); 6356 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); 6357 /* enable context validation interrupt from CFC */ 6358 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6359 6360 /* set the thresholds to prevent CFC/CDU race */ 6361 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 6362 6363 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); 6364 6365 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) 6366 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); 6367 6368 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); 6369 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); 6370 6371 /* Reset PCIE errors for debug */ 6372 REG_WR(bp, 0x2814, 0xffffffff); 6373 REG_WR(bp, 0x3820, 0xffffffff); 6374 6375 if (!CHIP_IS_E1x(bp)) { 6376 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 6377 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 6378 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 6379 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 6380 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 6381 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 6382 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 6383 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 6384 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 6385 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 6386 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 6387 } 6388 6389 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); 6390 if (!CHIP_IS_E1(bp)) { 6391 /* in E3 this done in per-port section */ 6392 if (!CHIP_IS_E3(bp)) 6393 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6394 } 6395 if (CHIP_IS_E1H(bp)) 6396 /* not applicable for E2 (and above ...) */ 6397 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); 6398 6399 if (CHIP_REV_IS_SLOW(bp)) 6400 msleep(200); 6401 6402 /* finish CFC init */ 6403 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); 6404 if (val != 1) { 6405 BNX2X_ERR("CFC LL_INIT failed\n"); 6406 return -EBUSY; 6407 } 6408 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); 6409 if (val != 1) { 6410 BNX2X_ERR("CFC AC_INIT failed\n"); 6411 return -EBUSY; 6412 } 6413 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 6414 if (val != 1) { 6415 BNX2X_ERR("CFC CAM_INIT failed\n"); 6416 return -EBUSY; 6417 } 6418 REG_WR(bp, CFC_REG_DEBUG0, 0); 6419 6420 if (CHIP_IS_E1(bp)) { 6421 /* read NIG statistic 6422 to see if this is our first up since powerup */ 6423 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6424 val = *bnx2x_sp(bp, wb_data[0]); 6425 6426 /* do internal memory self test */ 6427 if ((val == 0) && bnx2x_int_mem_test(bp)) { 6428 BNX2X_ERR("internal mem self test failed\n"); 6429 return -EBUSY; 6430 } 6431 } 6432 6433 bnx2x_setup_fan_failure_detection(bp); 6434 6435 /* clear PXP2 attentions */ 6436 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 6437 6438 bnx2x_enable_blocks_attention(bp); 6439 bnx2x_enable_blocks_parity(bp); 6440 6441 if (!BP_NOMCP(bp)) { 6442 if (CHIP_IS_E1x(bp)) 6443 bnx2x__common_init_phy(bp); 6444 } else 6445 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 6446 6447 return 0; 6448} 6449 6450/** 6451 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. 6452 * 6453 * @bp: driver handle 6454 */ 6455static int bnx2x_init_hw_common_chip(struct bnx2x *bp) 6456{ 6457 int rc = bnx2x_init_hw_common(bp); 6458 6459 if (rc) 6460 return rc; 6461 6462 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 6463 if (!BP_NOMCP(bp)) 6464 bnx2x__common_init_phy(bp); 6465 6466 return 0; 6467} 6468 6469static int bnx2x_init_hw_port(struct bnx2x *bp) 6470{ 6471 int port = BP_PORT(bp); 6472 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 6473 u32 low, high; 6474 u32 val; 6475 6476 bnx2x__link_reset(bp); 6477 6478 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port); 6479 6480 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 6481 6482 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6483 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6484 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6485 6486 /* Timers bug workaround: disables the pf_master bit in pglue at 6487 * common phase, we need to enable it here before any dmae access are 6488 * attempted. Therefore we manually added the enable-master to the 6489 * port phase (it also happens in the function phase) 6490 */ 6491 if (!CHIP_IS_E1x(bp)) 6492 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6493 6494 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6495 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6496 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6497 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6498 6499 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6500 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6501 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6502 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6503 6504 /* QM cid (connection) count */ 6505 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); 6506 6507#ifdef BCM_CNIC 6508 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6509 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 6510 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 6511#endif 6512 6513 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6514 6515 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { 6516 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6517 6518 if (IS_MF(bp)) 6519 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 6520 else if (bp->dev->mtu > 4096) { 6521 if (bp->flags & ONE_PORT_FLAG) 6522 low = 160; 6523 else { 6524 val = bp->dev->mtu; 6525 /* (24*1024 + val*4)/256 */ 6526 low = 96 + (val/64) + 6527 ((val % 64) ? 1 : 0); 6528 } 6529 } else 6530 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 6531 high = low + 56; /* 14*1024/256 */ 6532 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 6533 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 6534 } 6535 6536 if (CHIP_MODE_IS_4_PORT(bp)) 6537 REG_WR(bp, (BP_PORT(bp) ? 6538 BRB1_REG_MAC_GUARANTIED_1 : 6539 BRB1_REG_MAC_GUARANTIED_0), 40); 6540 6541 6542 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6543 if (CHIP_IS_E3B0(bp)) 6544 /* Ovlan exists only if we are in multi-function + 6545 * switch-dependent mode, in switch-independent there 6546 * is no ovlan headers 6547 */ 6548 REG_WR(bp, BP_PORT(bp) ? 6549 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 6550 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 6551 (bp->path_has_ovlan ? 7 : 6)); 6552 6553 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6554 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6555 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6556 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6557 6558 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6559 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6560 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6561 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6562 6563 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6564 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6565 6566 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6567 6568 if (CHIP_IS_E1x(bp)) { 6569 /* configure PBF to work without PAUSE mtu 9000 */ 6570 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 6571 6572 /* update threshold */ 6573 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 6574 /* update init credit */ 6575 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 6576 6577 /* probe changes */ 6578 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 6579 udelay(50); 6580 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 6581 } 6582 6583#ifdef BCM_CNIC 6584 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6585#endif 6586 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6587 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6588 6589 if (CHIP_IS_E1(bp)) { 6590 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6591 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6592 } 6593 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6594 6595 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6596 6597 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6598 /* init aeu_mask_attn_func_0/1: 6599 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 6600 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 6601 * bits 4-7 are used for "per vn group attention" */ 6602 val = IS_MF(bp) ? 0xF7 : 0x7; 6603 /* Enable DCBX attention for all but E1 */ 6604 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 6605 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 6606 6607 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6608 6609 if (!CHIP_IS_E1x(bp)) { 6610 /* Bit-map indicating which L2 hdrs may appear after the 6611 * basic Ethernet header 6612 */ 6613 REG_WR(bp, BP_PORT(bp) ? 6614 NIG_REG_P1_HDRS_AFTER_BASIC : 6615 NIG_REG_P0_HDRS_AFTER_BASIC, 6616 IS_MF_SD(bp) ? 7 : 6); 6617 6618 if (CHIP_IS_E3(bp)) 6619 REG_WR(bp, BP_PORT(bp) ? 6620 NIG_REG_LLH1_MF_MODE : 6621 NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6622 } 6623 if (!CHIP_IS_E3(bp)) 6624 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 6625 6626 if (!CHIP_IS_E1(bp)) { 6627 /* 0x2 disable mf_ov, 0x1 enable */ 6628 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 6629 (IS_MF_SD(bp) ? 0x1 : 0x2)); 6630 6631 if (!CHIP_IS_E1x(bp)) { 6632 val = 0; 6633 switch (bp->mf_mode) { 6634 case MULTI_FUNCTION_SD: 6635 val = 1; 6636 break; 6637 case MULTI_FUNCTION_SI: 6638 val = 2; 6639 break; 6640 } 6641 6642 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : 6643 NIG_REG_LLH0_CLS_TYPE), val); 6644 } 6645 { 6646 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 6647 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 6648 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 6649 } 6650 } 6651 6652 6653 /* If SPIO5 is set to generate interrupts, enable it for this port */ 6654 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6655 if (val & (1 << MISC_REGISTERS_SPIO_5)) { 6656 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 6657 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 6658 val = REG_RD(bp, reg_addr); 6659 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 6660 REG_WR(bp, reg_addr, val); 6661 } 6662 6663 return 0; 6664} 6665 6666static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 6667{ 6668 int reg; 6669 6670 if (CHIP_IS_E1(bp)) 6671 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 6672 else 6673 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 6674 6675 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr)); 6676} 6677 6678static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) 6679{ 6680 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); 6681} 6682 6683static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) 6684{ 6685 u32 i, base = FUNC_ILT_BASE(func); 6686 for (i = base; i < base + ILT_PER_FUNC; i++) 6687 bnx2x_ilt_wr(bp, i, 0); 6688} 6689 6690static int bnx2x_init_hw_func(struct bnx2x *bp) 6691{ 6692 int port = BP_PORT(bp); 6693 int func = BP_FUNC(bp); 6694 int init_phase = PHASE_PF0 + func; 6695 struct bnx2x_ilt *ilt = BP_ILT(bp); 6696 u16 cdu_ilt_start; 6697 u32 addr, val; 6698 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 6699 int i, main_mem_width, rc; 6700 6701 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func); 6702 6703 /* FLR cleanup - hmmm */ 6704 if (!CHIP_IS_E1x(bp)) { 6705 rc = bnx2x_pf_flr_clnup(bp); 6706 if (rc) 6707 return rc; 6708 } 6709 6710 /* set MSI reconfigure capability */ 6711 if (bp->common.int_block == INT_BLOCK_HC) { 6712 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 6713 val = REG_RD(bp, addr); 6714 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 6715 REG_WR(bp, addr, val); 6716 } 6717 6718 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6719 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6720 6721 ilt = BP_ILT(bp); 6722 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 6723 6724 for (i = 0; i < L2_ILT_LINES(bp); i++) { 6725 ilt->lines[cdu_ilt_start + i].page = 6726 bp->context.vcxt + (ILT_PAGE_CIDS * i); 6727 ilt->lines[cdu_ilt_start + i].page_mapping = 6728 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i); 6729 /* cdu ilt pages are allocated manually so there's no need to 6730 set the size */ 6731 } 6732 bnx2x_ilt_init_op(bp, INITOP_SET); 6733 6734#ifdef BCM_CNIC 6735 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); 6736 6737 /* T1 hash bits value determines the T1 number of entries */ 6738 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 6739#endif 6740 6741#ifndef BCM_CNIC 6742 /* set NIC mode */ 6743 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6744#endif /* BCM_CNIC */ 6745 6746 if (!CHIP_IS_E1x(bp)) { 6747 u32 pf_conf = IGU_PF_CONF_FUNC_EN; 6748 6749 /* Turn on a single ISR mode in IGU if driver is going to use 6750 * INT#x or MSI 6751 */ 6752 if (!(bp->flags & USING_MSIX_FLAG)) 6753 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 6754 /* 6755 * Timers workaround bug: function init part. 6756 * Need to wait 20msec after initializing ILT, 6757 * needed to make sure there are no requests in 6758 * one of the PXP internal queues with "old" ILT addresses 6759 */ 6760 msleep(20); 6761 /* 6762 * Master enable - Due to WB DMAE writes performed before this 6763 * register is re-initialized as part of the regular function 6764 * init 6765 */ 6766 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6767 /* Enable the function in IGU */ 6768 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); 6769 } 6770 6771 bp->dmae_ready = 1; 6772 6773 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6774 6775 if (!CHIP_IS_E1x(bp)) 6776 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); 6777 6778 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6779 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6780 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6781 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6782 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6783 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6784 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6785 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6786 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6787 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6788 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6789 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6790 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6791 6792 if (!CHIP_IS_E1x(bp)) 6793 REG_WR(bp, QM_REG_PF_EN, 1); 6794 6795 if (!CHIP_IS_E1x(bp)) { 6796 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6797 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6798 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6799 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6800 } 6801 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6802 6803 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6804 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6805 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6806 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6807 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6808 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6809 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6810 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6811 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6812 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6813 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6814 if (!CHIP_IS_E1x(bp)) 6815 REG_WR(bp, PBF_REG_DISABLE_PF, 0); 6816 6817 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6818 6819 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6820 6821 if (!CHIP_IS_E1x(bp)) 6822 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); 6823 6824 if (IS_MF(bp)) { 6825 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 6826 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); 6827 } 6828 6829 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6830 6831 /* HC init per function */ 6832 if (bp->common.int_block == INT_BLOCK_HC) { 6833 if (CHIP_IS_E1H(bp)) { 6834 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6835 6836 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6837 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6838 } 6839 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6840 6841 } else { 6842 int num_segs, sb_idx, prod_offset; 6843 6844 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6845 6846 if (!CHIP_IS_E1x(bp)) { 6847 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 6848 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 6849 } 6850 6851 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6852 6853 if (!CHIP_IS_E1x(bp)) { 6854 int dsb_idx = 0; 6855 /** 6856 * Producer memory: 6857 * E2 mode: address 0-135 match to the mapping memory; 6858 * 136 - PF0 default prod; 137 - PF1 default prod; 6859 * 138 - PF2 default prod; 139 - PF3 default prod; 6860 * 140 - PF0 attn prod; 141 - PF1 attn prod; 6861 * 142 - PF2 attn prod; 143 - PF3 attn prod; 6862 * 144-147 reserved. 6863 * 6864 * E1.5 mode - In backward compatible mode; 6865 * for non default SB; each even line in the memory 6866 * holds the U producer and each odd line hold 6867 * the C producer. The first 128 producers are for 6868 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 6869 * producers are for the DSB for each PF. 6870 * Each PF has five segments: (the order inside each 6871 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 6872 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 6873 * 144-147 attn prods; 6874 */ 6875 /* non-default-status-blocks */ 6876 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6877 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 6878 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { 6879 prod_offset = (bp->igu_base_sb + sb_idx) * 6880 num_segs; 6881 6882 for (i = 0; i < num_segs; i++) { 6883 addr = IGU_REG_PROD_CONS_MEMORY + 6884 (prod_offset + i) * 4; 6885 REG_WR(bp, addr, 0); 6886 } 6887 /* send consumer update with value 0 */ 6888 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, 6889 USTORM_ID, 0, IGU_INT_NOP, 1); 6890 bnx2x_igu_clear_sb(bp, 6891 bp->igu_base_sb + sb_idx); 6892 } 6893 6894 /* default-status-blocks */ 6895 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6896 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 6897 6898 if (CHIP_MODE_IS_4_PORT(bp)) 6899 dsb_idx = BP_FUNC(bp); 6900 else 6901 dsb_idx = BP_VN(bp); 6902 6903 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 6904 IGU_BC_BASE_DSB_PROD + dsb_idx : 6905 IGU_NORM_BASE_DSB_PROD + dsb_idx); 6906 6907 /* 6908 * igu prods come in chunks of E1HVN_MAX (4) - 6909 * does not matters what is the current chip mode 6910 */ 6911 for (i = 0; i < (num_segs * E1HVN_MAX); 6912 i += E1HVN_MAX) { 6913 addr = IGU_REG_PROD_CONS_MEMORY + 6914 (prod_offset + i)*4; 6915 REG_WR(bp, addr, 0); 6916 } 6917 /* send consumer update with 0 */ 6918 if (CHIP_INT_MODE_IS_BC(bp)) { 6919 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6920 USTORM_ID, 0, IGU_INT_NOP, 1); 6921 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6922 CSTORM_ID, 0, IGU_INT_NOP, 1); 6923 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6924 XSTORM_ID, 0, IGU_INT_NOP, 1); 6925 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6926 TSTORM_ID, 0, IGU_INT_NOP, 1); 6927 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6928 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6929 } else { 6930 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6931 USTORM_ID, 0, IGU_INT_NOP, 1); 6932 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6933 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6934 } 6935 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); 6936 6937 /* !!! these should become driver const once 6938 rf-tool supports split-68 const */ 6939 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 6940 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 6941 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 6942 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 6943 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 6944 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 6945 } 6946 } 6947 6948 /* Reset PCIE errors for debug */ 6949 REG_WR(bp, 0x2114, 0xffffffff); 6950 REG_WR(bp, 0x2120, 0xffffffff); 6951 6952 if (CHIP_IS_E1x(bp)) { 6953 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 6954 main_mem_base = HC_REG_MAIN_MEMORY + 6955 BP_PORT(bp) * (main_mem_size * 4); 6956 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 6957 main_mem_width = 8; 6958 6959 val = REG_RD(bp, main_mem_prty_clr); 6960 if (val) 6961 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC " 6962 "block during " 6963 "function init (0x%x)!\n", val); 6964 6965 /* Clear "false" parity errors in MSI-X table */ 6966 for (i = main_mem_base; 6967 i < main_mem_base + main_mem_size * 4; 6968 i += main_mem_width) { 6969 bnx2x_read_dmae(bp, i, main_mem_width / 4); 6970 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), 6971 i, main_mem_width / 4); 6972 } 6973 /* Clear HC parity attention */ 6974 REG_RD(bp, main_mem_prty_clr); 6975 } 6976 6977#ifdef BNX2X_STOP_ON_ERROR 6978 /* Enable STORMs SP logging */ 6979 REG_WR8(bp, BAR_USTRORM_INTMEM + 6980 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6981 REG_WR8(bp, BAR_TSTRORM_INTMEM + 6982 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6983 REG_WR8(bp, BAR_CSTRORM_INTMEM + 6984 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6985 REG_WR8(bp, BAR_XSTRORM_INTMEM + 6986 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6987#endif 6988 6989 bnx2x_phy_probe(&bp->link_params); 6990 6991 return 0; 6992} 6993 6994 6995void bnx2x_free_mem(struct bnx2x *bp) 6996{ 6997 /* fastpath */ 6998 bnx2x_free_fp_mem(bp); 6999 /* end of fastpath */ 7000 7001 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 7002 sizeof(struct host_sp_status_block)); 7003 7004 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 7005 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7006 7007 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 7008 sizeof(struct bnx2x_slowpath)); 7009 7010 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping, 7011 bp->context.size); 7012 7013 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); 7014 7015 BNX2X_FREE(bp->ilt->lines); 7016 7017#ifdef BCM_CNIC 7018 if (!CHIP_IS_E1x(bp)) 7019 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, 7020 sizeof(struct host_hc_status_block_e2)); 7021 else 7022 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, 7023 sizeof(struct host_hc_status_block_e1x)); 7024 7025 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 7026#endif 7027 7028 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 7029 7030 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, 7031 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7032} 7033 7034static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) 7035{ 7036 int num_groups; 7037 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1; 7038 7039 /* number of queues for statistics is number of eth queues + FCoE */ 7040 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats; 7041 7042 /* Total number of FW statistics requests = 7043 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats + 7044 * num of queues 7045 */ 7046 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats; 7047 7048 7049 /* Request is built from stats_query_header and an array of 7050 * stats_query_cmd_group each of which contains 7051 * STATS_QUERY_CMD_COUNT rules. The real number or requests is 7052 * configured in the stats_query_header. 7053 */ 7054 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) + 7055 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0); 7056 7057 bp->fw_stats_req_sz = sizeof(struct stats_query_header) + 7058 num_groups * sizeof(struct stats_query_cmd_group); 7059 7060 /* Data for statistics requests + stats_conter 7061 * 7062 * stats_counter holds per-STORM counters that are incremented 7063 * when STORM has finished with the current request. 7064 * 7065 * memory for FCoE offloaded statistics are counted anyway, 7066 * even if they will not be sent. 7067 */ 7068 bp->fw_stats_data_sz = sizeof(struct per_port_stats) + 7069 sizeof(struct per_pf_stats) + 7070 sizeof(struct fcoe_statistics_params) + 7071 sizeof(struct per_queue_stats) * num_queue_stats + 7072 sizeof(struct stats_counter); 7073 7074 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, 7075 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7076 7077 /* Set shortcuts */ 7078 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; 7079 bp->fw_stats_req_mapping = bp->fw_stats_mapping; 7080 7081 bp->fw_stats_data = (struct bnx2x_fw_stats_data *) 7082 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); 7083 7084 bp->fw_stats_data_mapping = bp->fw_stats_mapping + 7085 bp->fw_stats_req_sz; 7086 return 0; 7087 7088alloc_mem_err: 7089 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 7090 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7091 return -ENOMEM; 7092} 7093 7094 7095int bnx2x_alloc_mem(struct bnx2x *bp) 7096{ 7097#ifdef BCM_CNIC 7098 if (!CHIP_IS_E1x(bp)) 7099 /* size = the status block + ramrod buffers */ 7100 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, 7101 sizeof(struct host_hc_status_block_e2)); 7102 else 7103 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, 7104 sizeof(struct host_hc_status_block_e1x)); 7105 7106 /* allocate searcher T2 table */ 7107 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); 7108#endif 7109 7110 7111 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, 7112 sizeof(struct host_sp_status_block)); 7113 7114 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, 7115 sizeof(struct bnx2x_slowpath)); 7116 7117#ifdef BCM_CNIC 7118 /* write address to which L5 should insert its values */ 7119 bp->cnic_eth_dev.addr_drv_info_to_mcp = &bp->slowpath->drv_info_to_mcp; 7120#endif 7121 7122 /* Allocated memory for FW statistics */ 7123 if (bnx2x_alloc_fw_stats_mem(bp)) 7124 goto alloc_mem_err; 7125 7126 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); 7127 7128 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping, 7129 bp->context.size); 7130 7131 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); 7132 7133 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) 7134 goto alloc_mem_err; 7135 7136 /* Slow path ring */ 7137 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); 7138 7139 /* EQ */ 7140 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, 7141 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7142 7143 7144 /* fastpath */ 7145 /* need to be done at the end, since it's self adjusting to amount 7146 * of memory available for RSS queues 7147 */ 7148 if (bnx2x_alloc_fp_mem(bp)) 7149 goto alloc_mem_err; 7150 return 0; 7151 7152alloc_mem_err: 7153 bnx2x_free_mem(bp); 7154 return -ENOMEM; 7155} 7156 7157/* 7158 * Init service functions 7159 */ 7160 7161int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 7162 struct bnx2x_vlan_mac_obj *obj, bool set, 7163 int mac_type, unsigned long *ramrod_flags) 7164{ 7165 int rc; 7166 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 7167 7168 memset(&ramrod_param, 0, sizeof(ramrod_param)); 7169 7170 /* Fill general parameters */ 7171 ramrod_param.vlan_mac_obj = obj; 7172 ramrod_param.ramrod_flags = *ramrod_flags; 7173 7174 /* Fill a user request section if needed */ 7175 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 7176 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 7177 7178 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 7179 7180 /* Set the command: ADD or DEL */ 7181 if (set) 7182 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 7183 else 7184 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 7185 } 7186 7187 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 7188 if (rc < 0) 7189 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); 7190 return rc; 7191} 7192 7193int bnx2x_del_all_macs(struct bnx2x *bp, 7194 struct bnx2x_vlan_mac_obj *mac_obj, 7195 int mac_type, bool wait_for_comp) 7196{ 7197 int rc; 7198 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 7199 7200 /* Wait for completion of requested */ 7201 if (wait_for_comp) 7202 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7203 7204 /* Set the mac type of addresses we want to clear */ 7205 __set_bit(mac_type, &vlan_mac_flags); 7206 7207 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); 7208 if (rc < 0) 7209 BNX2X_ERR("Failed to delete MACs: %d\n", rc); 7210 7211 return rc; 7212} 7213 7214int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) 7215{ 7216 unsigned long ramrod_flags = 0; 7217 7218#ifdef BCM_CNIC 7219 if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_ISCSI_SD(bp)) { 7220 DP(NETIF_MSG_IFUP, "Ignoring Zero MAC for iSCSI SD mode\n"); 7221 return 0; 7222 } 7223#endif 7224 7225 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); 7226 7227 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7228 /* Eth MAC is set on RSS leading client (fp[0]) */ 7229 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set, 7230 BNX2X_ETH_MAC, &ramrod_flags); 7231} 7232 7233int bnx2x_setup_leading(struct bnx2x *bp) 7234{ 7235 return bnx2x_setup_queue(bp, &bp->fp[0], 1); 7236} 7237 7238/** 7239 * bnx2x_set_int_mode - configure interrupt mode 7240 * 7241 * @bp: driver handle 7242 * 7243 * In case of MSI-X it will also try to enable MSI-X. 7244 */ 7245static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) 7246{ 7247 switch (int_mode) { 7248 case INT_MODE_MSI: 7249 bnx2x_enable_msi(bp); 7250 /* falling through... */ 7251 case INT_MODE_INTx: 7252 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7253 DP(NETIF_MSG_IFUP, "set number of queues to 1\n"); 7254 break; 7255 default: 7256 /* Set number of queues according to bp->multi_mode value */ 7257 bnx2x_set_num_queues(bp); 7258 7259 DP(NETIF_MSG_IFUP, "set number of queues to %d\n", 7260 bp->num_queues); 7261 7262 /* if we can't use MSI-X we only need one fp, 7263 * so try to enable MSI-X with the requested number of fp's 7264 * and fallback to MSI or legacy INTx with one fp 7265 */ 7266 if (bnx2x_enable_msix(bp)) { 7267 /* failed to enable MSI-X */ 7268 if (bp->multi_mode) 7269 DP(NETIF_MSG_IFUP, 7270 "Multi requested but failed to " 7271 "enable MSI-X (%d), " 7272 "set number of queues to %d\n", 7273 bp->num_queues, 7274 1 + NON_ETH_CONTEXT_USE); 7275 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7276 7277 /* Try to enable MSI */ 7278 if (!(bp->flags & DISABLE_MSI_FLAG)) 7279 bnx2x_enable_msi(bp); 7280 } 7281 break; 7282 } 7283} 7284 7285/* must be called prioir to any HW initializations */ 7286static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) 7287{ 7288 return L2_ILT_LINES(bp); 7289} 7290 7291void bnx2x_ilt_set_info(struct bnx2x *bp) 7292{ 7293 struct ilt_client_info *ilt_client; 7294 struct bnx2x_ilt *ilt = BP_ILT(bp); 7295 u16 line = 0; 7296 7297 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); 7298 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); 7299 7300 /* CDU */ 7301 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 7302 ilt_client->client_num = ILT_CLIENT_CDU; 7303 ilt_client->page_size = CDU_ILT_PAGE_SZ; 7304 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 7305 ilt_client->start = line; 7306 line += bnx2x_cid_ilt_lines(bp); 7307#ifdef BCM_CNIC 7308 line += CNIC_ILT_LINES; 7309#endif 7310 ilt_client->end = line - 1; 7311 7312 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, " 7313 "flags 0x%x, hw psz %d\n", 7314 ilt_client->start, 7315 ilt_client->end, 7316 ilt_client->page_size, 7317 ilt_client->flags, 7318 ilog2(ilt_client->page_size >> 12)); 7319 7320 /* QM */ 7321 if (QM_INIT(bp->qm_cid_count)) { 7322 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 7323 ilt_client->client_num = ILT_CLIENT_QM; 7324 ilt_client->page_size = QM_ILT_PAGE_SZ; 7325 ilt_client->flags = 0; 7326 ilt_client->start = line; 7327 7328 /* 4 bytes for each cid */ 7329 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 7330 QM_ILT_PAGE_SZ); 7331 7332 ilt_client->end = line - 1; 7333 7334 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, " 7335 "flags 0x%x, hw psz %d\n", 7336 ilt_client->start, 7337 ilt_client->end, 7338 ilt_client->page_size, 7339 ilt_client->flags, 7340 ilog2(ilt_client->page_size >> 12)); 7341 7342 } 7343 /* SRC */ 7344 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 7345#ifdef BCM_CNIC 7346 ilt_client->client_num = ILT_CLIENT_SRC; 7347 ilt_client->page_size = SRC_ILT_PAGE_SZ; 7348 ilt_client->flags = 0; 7349 ilt_client->start = line; 7350 line += SRC_ILT_LINES; 7351 ilt_client->end = line - 1; 7352 7353 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, " 7354 "flags 0x%x, hw psz %d\n", 7355 ilt_client->start, 7356 ilt_client->end, 7357 ilt_client->page_size, 7358 ilt_client->flags, 7359 ilog2(ilt_client->page_size >> 12)); 7360 7361#else 7362 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7363#endif 7364 7365 /* TM */ 7366 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 7367#ifdef BCM_CNIC 7368 ilt_client->client_num = ILT_CLIENT_TM; 7369 ilt_client->page_size = TM_ILT_PAGE_SZ; 7370 ilt_client->flags = 0; 7371 ilt_client->start = line; 7372 line += TM_ILT_LINES; 7373 ilt_client->end = line - 1; 7374 7375 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, " 7376 "flags 0x%x, hw psz %d\n", 7377 ilt_client->start, 7378 ilt_client->end, 7379 ilt_client->page_size, 7380 ilt_client->flags, 7381 ilog2(ilt_client->page_size >> 12)); 7382 7383#else 7384 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7385#endif 7386 BUG_ON(line > ILT_MAX_LINES); 7387} 7388 7389/** 7390 * bnx2x_pf_q_prep_init - prepare INIT transition parameters 7391 * 7392 * @bp: driver handle 7393 * @fp: pointer to fastpath 7394 * @init_params: pointer to parameters structure 7395 * 7396 * parameters configured: 7397 * - HC configuration 7398 * - Queue's CDU context 7399 */ 7400static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp, 7401 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) 7402{ 7403 7404 u8 cos; 7405 /* FCoE Queue uses Default SB, thus has no HC capabilities */ 7406 if (!IS_FCOE_FP(fp)) { 7407 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); 7408 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); 7409 7410 /* If HC is supporterd, enable host coalescing in the transition 7411 * to INIT state. 7412 */ 7413 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); 7414 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); 7415 7416 /* HC rate */ 7417 init_params->rx.hc_rate = bp->rx_ticks ? 7418 (1000000 / bp->rx_ticks) : 0; 7419 init_params->tx.hc_rate = bp->tx_ticks ? 7420 (1000000 / bp->tx_ticks) : 0; 7421 7422 /* FW SB ID */ 7423 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = 7424 fp->fw_sb_id; 7425 7426 /* 7427 * CQ index among the SB indices: FCoE clients uses the default 7428 * SB, therefore it's different. 7429 */ 7430 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 7431 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 7432 } 7433 7434 /* set maximum number of COSs supported by this queue */ 7435 init_params->max_cos = fp->max_cos; 7436 7437 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n", 7438 fp->index, init_params->max_cos); 7439 7440 /* set the context pointers queue object */ 7441 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) 7442 init_params->cxts[cos] = 7443 &bp->context.vcxt[fp->txdata[cos].cid].eth; 7444} 7445 7446int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7447 struct bnx2x_queue_state_params *q_params, 7448 struct bnx2x_queue_setup_tx_only_params *tx_only_params, 7449 int tx_index, bool leading) 7450{ 7451 memset(tx_only_params, 0, sizeof(*tx_only_params)); 7452 7453 /* Set the command */ 7454 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 7455 7456 /* Set tx-only QUEUE flags: don't zero statistics */ 7457 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); 7458 7459 /* choose the index of the cid to send the slow path on */ 7460 tx_only_params->cid_index = tx_index; 7461 7462 /* Set general TX_ONLY_SETUP parameters */ 7463 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); 7464 7465 /* Set Tx TX_ONLY_SETUP parameters */ 7466 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 7467 7468 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:" 7469 "cos %d, primary cid %d, cid %d, " 7470 "client id %d, sp-client id %d, flags %lx\n", 7471 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 7472 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 7473 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 7474 7475 /* send the ramrod */ 7476 return bnx2x_queue_state_change(bp, q_params); 7477} 7478 7479 7480/** 7481 * bnx2x_setup_queue - setup queue 7482 * 7483 * @bp: driver handle 7484 * @fp: pointer to fastpath 7485 * @leading: is leading 7486 * 7487 * This function performs 2 steps in a Queue state machine 7488 * actually: 1) RESET->INIT 2) INIT->SETUP 7489 */ 7490 7491int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7492 bool leading) 7493{ 7494 struct bnx2x_queue_state_params q_params = {0}; 7495 struct bnx2x_queue_setup_params *setup_params = 7496 &q_params.params.setup; 7497 struct bnx2x_queue_setup_tx_only_params *tx_only_params = 7498 &q_params.params.tx_only; 7499 int rc; 7500 u8 tx_index; 7501 7502 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index); 7503 7504 /* reset IGU state skip FCoE L2 queue */ 7505 if (!IS_FCOE_FP(fp)) 7506 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, 7507 IGU_INT_ENABLE, 0); 7508 7509 q_params.q_obj = &fp->q_obj; 7510 /* We want to wait for completion in this context */ 7511 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7512 7513 /* Prepare the INIT parameters */ 7514 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); 7515 7516 /* Set the command */ 7517 q_params.cmd = BNX2X_Q_CMD_INIT; 7518 7519 /* Change the state to INIT */ 7520 rc = bnx2x_queue_state_change(bp, &q_params); 7521 if (rc) { 7522 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); 7523 return rc; 7524 } 7525 7526 DP(BNX2X_MSG_SP, "init complete\n"); 7527 7528 7529 /* Now move the Queue to the SETUP state... */ 7530 memset(setup_params, 0, sizeof(*setup_params)); 7531 7532 /* Set QUEUE flags */ 7533 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); 7534 7535 /* Set general SETUP parameters */ 7536 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, 7537 FIRST_TX_COS_INDEX); 7538 7539 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, 7540 &setup_params->rxq_params); 7541 7542 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, 7543 FIRST_TX_COS_INDEX); 7544 7545 /* Set the command */ 7546 q_params.cmd = BNX2X_Q_CMD_SETUP; 7547 7548 /* Change the state to SETUP */ 7549 rc = bnx2x_queue_state_change(bp, &q_params); 7550 if (rc) { 7551 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); 7552 return rc; 7553 } 7554 7555 /* loop through the relevant tx-only indices */ 7556 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7557 tx_index < fp->max_cos; 7558 tx_index++) { 7559 7560 /* prepare and send tx-only ramrod*/ 7561 rc = bnx2x_setup_tx_only(bp, fp, &q_params, 7562 tx_only_params, tx_index, leading); 7563 if (rc) { 7564 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", 7565 fp->index, tx_index); 7566 return rc; 7567 } 7568 } 7569 7570 return rc; 7571} 7572 7573static int bnx2x_stop_queue(struct bnx2x *bp, int index) 7574{ 7575 struct bnx2x_fastpath *fp = &bp->fp[index]; 7576 struct bnx2x_fp_txdata *txdata; 7577 struct bnx2x_queue_state_params q_params = {0}; 7578 int rc, tx_index; 7579 7580 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid); 7581 7582 q_params.q_obj = &fp->q_obj; 7583 /* We want to wait for completion in this context */ 7584 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7585 7586 7587 /* close tx-only connections */ 7588 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7589 tx_index < fp->max_cos; 7590 tx_index++){ 7591 7592 /* ascertain this is a normal queue*/ 7593 txdata = &fp->txdata[tx_index]; 7594 7595 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n", 7596 txdata->txq_index); 7597 7598 /* send halt terminate on tx-only connection */ 7599 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7600 memset(&q_params.params.terminate, 0, 7601 sizeof(q_params.params.terminate)); 7602 q_params.params.terminate.cid_index = tx_index; 7603 7604 rc = bnx2x_queue_state_change(bp, &q_params); 7605 if (rc) 7606 return rc; 7607 7608 /* send halt terminate on tx-only connection */ 7609 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7610 memset(&q_params.params.cfc_del, 0, 7611 sizeof(q_params.params.cfc_del)); 7612 q_params.params.cfc_del.cid_index = tx_index; 7613 rc = bnx2x_queue_state_change(bp, &q_params); 7614 if (rc) 7615 return rc; 7616 } 7617 /* Stop the primary connection: */ 7618 /* ...halt the connection */ 7619 q_params.cmd = BNX2X_Q_CMD_HALT; 7620 rc = bnx2x_queue_state_change(bp, &q_params); 7621 if (rc) 7622 return rc; 7623 7624 /* ...terminate the connection */ 7625 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7626 memset(&q_params.params.terminate, 0, 7627 sizeof(q_params.params.terminate)); 7628 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 7629 rc = bnx2x_queue_state_change(bp, &q_params); 7630 if (rc) 7631 return rc; 7632 /* ...delete cfc entry */ 7633 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7634 memset(&q_params.params.cfc_del, 0, 7635 sizeof(q_params.params.cfc_del)); 7636 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 7637 return bnx2x_queue_state_change(bp, &q_params); 7638} 7639 7640 7641static void bnx2x_reset_func(struct bnx2x *bp) 7642{ 7643 int port = BP_PORT(bp); 7644 int func = BP_FUNC(bp); 7645 int i; 7646 7647 /* Disable the function in the FW */ 7648 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 7649 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 7650 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 7651 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 7652 7653 /* FP SBs */ 7654 for_each_eth_queue(bp, i) { 7655 struct bnx2x_fastpath *fp = &bp->fp[i]; 7656 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7657 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 7658 SB_DISABLED); 7659 } 7660 7661#ifdef BCM_CNIC 7662 /* CNIC SB */ 7663 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7664 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), 7665 SB_DISABLED); 7666#endif 7667 /* SP SB */ 7668 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7669 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 7670 SB_DISABLED); 7671 7672 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) 7673 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 7674 0); 7675 7676 /* Configure IGU */ 7677 if (bp->common.int_block == INT_BLOCK_HC) { 7678 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7679 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7680 } else { 7681 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 7682 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 7683 } 7684 7685#ifdef BCM_CNIC 7686 /* Disable Timer scan */ 7687 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 7688 /* 7689 * Wait for at least 10ms and up to 2 second for the timers scan to 7690 * complete 7691 */ 7692 for (i = 0; i < 200; i++) { 7693 msleep(10); 7694 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) 7695 break; 7696 } 7697#endif 7698 /* Clear ILT */ 7699 bnx2x_clear_func_ilt(bp, func); 7700 7701 /* Timers workaround bug for E2: if this is vnic-3, 7702 * we need to set the entire ilt range for this timers. 7703 */ 7704 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { 7705 struct ilt_client_info ilt_cli; 7706 /* use dummy TM client */ 7707 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 7708 ilt_cli.start = 0; 7709 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 7710 ilt_cli.client_num = ILT_CLIENT_TM; 7711 7712 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); 7713 } 7714 7715 /* this assumes that reset_port() called before reset_func()*/ 7716 if (!CHIP_IS_E1x(bp)) 7717 bnx2x_pf_disable(bp); 7718 7719 bp->dmae_ready = 0; 7720} 7721 7722static void bnx2x_reset_port(struct bnx2x *bp) 7723{ 7724 int port = BP_PORT(bp); 7725 u32 val; 7726 7727 /* Reset physical Link */ 7728 bnx2x__link_reset(bp); 7729 7730 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 7731 7732 /* Do not rcv packets to BRB */ 7733 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 7734 /* Do not direct rcv packets that are not for MCP to the BRB */ 7735 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 7736 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 7737 7738 /* Configure AEU */ 7739 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 7740 7741 msleep(100); 7742 /* Check for BRB port occupancy */ 7743 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 7744 if (val) 7745 DP(NETIF_MSG_IFDOWN, 7746 "BRB1 is not empty %d blocks are occupied\n", val); 7747 7748 /* TODO: Close Doorbell port? */ 7749} 7750 7751static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) 7752{ 7753 struct bnx2x_func_state_params func_params = {0}; 7754 7755 /* Prepare parameters for function state transitions */ 7756 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7757 7758 func_params.f_obj = &bp->func_obj; 7759 func_params.cmd = BNX2X_F_CMD_HW_RESET; 7760 7761 func_params.params.hw_init.load_phase = load_code; 7762 7763 return bnx2x_func_state_change(bp, &func_params); 7764} 7765 7766static inline int bnx2x_func_stop(struct bnx2x *bp) 7767{ 7768 struct bnx2x_func_state_params func_params = {0}; 7769 int rc; 7770 7771 /* Prepare parameters for function state transitions */ 7772 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7773 func_params.f_obj = &bp->func_obj; 7774 func_params.cmd = BNX2X_F_CMD_STOP; 7775 7776 /* 7777 * Try to stop the function the 'good way'. If fails (in case 7778 * of a parity error during bnx2x_chip_cleanup()) and we are 7779 * not in a debug mode, perform a state transaction in order to 7780 * enable further HW_RESET transaction. 7781 */ 7782 rc = bnx2x_func_state_change(bp, &func_params); 7783 if (rc) { 7784#ifdef BNX2X_STOP_ON_ERROR 7785 return rc; 7786#else 7787 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry " 7788 "transaction\n"); 7789 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 7790 return bnx2x_func_state_change(bp, &func_params); 7791#endif 7792 } 7793 7794 return 0; 7795} 7796 7797/** 7798 * bnx2x_send_unload_req - request unload mode from the MCP. 7799 * 7800 * @bp: driver handle 7801 * @unload_mode: requested function's unload mode 7802 * 7803 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 7804 */ 7805u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 7806{ 7807 u32 reset_code = 0; 7808 int port = BP_PORT(bp); 7809 7810 /* Select the UNLOAD request mode */ 7811 if (unload_mode == UNLOAD_NORMAL) 7812 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7813 7814 else if (bp->flags & NO_WOL_FLAG) 7815 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 7816 7817 else if (bp->wol) { 7818 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 7819 u8 *mac_addr = bp->dev->dev_addr; 7820 u32 val; 7821 u16 pmc; 7822 7823 /* The mac address is written to entries 1-4 to 7824 * preserve entry 0 which is used by the PMF 7825 */ 7826 u8 entry = (BP_VN(bp) + 1)*8; 7827 7828 val = (mac_addr[0] << 8) | mac_addr[1]; 7829 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 7830 7831 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 7832 (mac_addr[4] << 8) | mac_addr[5]; 7833 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 7834 7835 /* Enable the PME and clear the status */ 7836 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); 7837 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; 7838 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); 7839 7840 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 7841 7842 } else 7843 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7844 7845 /* Send the request to the MCP */ 7846 if (!BP_NOMCP(bp)) 7847 reset_code = bnx2x_fw_command(bp, reset_code, 0); 7848 else { 7849 int path = BP_PATH(bp); 7850 7851 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] " 7852 "%d, %d, %d\n", 7853 path, load_count[path][0], load_count[path][1], 7854 load_count[path][2]); 7855 load_count[path][0]--; 7856 load_count[path][1 + port]--; 7857 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] " 7858 "%d, %d, %d\n", 7859 path, load_count[path][0], load_count[path][1], 7860 load_count[path][2]); 7861 if (load_count[path][0] == 0) 7862 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 7863 else if (load_count[path][1 + port] == 0) 7864 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 7865 else 7866 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 7867 } 7868 7869 return reset_code; 7870} 7871 7872/** 7873 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 7874 * 7875 * @bp: driver handle 7876 */ 7877void bnx2x_send_unload_done(struct bnx2x *bp) 7878{ 7879 /* Report UNLOAD_DONE to MCP */ 7880 if (!BP_NOMCP(bp)) 7881 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 7882} 7883 7884static inline int bnx2x_func_wait_started(struct bnx2x *bp) 7885{ 7886 int tout = 50; 7887 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 7888 7889 if (!bp->port.pmf) 7890 return 0; 7891 7892 /* 7893 * (assumption: No Attention from MCP at this stage) 7894 * PMF probably in the middle of TXdisable/enable transaction 7895 * 1. Sync IRS for default SB 7896 * 2. Sync SP queue - this guarantes us that attention handling started 7897 * 3. Wait, that TXdisable/enable transaction completes 7898 * 7899 * 1+2 guranty that if DCBx attention was scheduled it already changed 7900 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy 7901 * received complettion for the transaction the state is TX_STOPPED. 7902 * State will return to STARTED after completion of TX_STOPPED-->STARTED 7903 * transaction. 7904 */ 7905 7906 /* make sure default SB ISR is done */ 7907 if (msix) 7908 synchronize_irq(bp->msix_table[0].vector); 7909 else 7910 synchronize_irq(bp->pdev->irq); 7911 7912 flush_workqueue(bnx2x_wq); 7913 7914 while (bnx2x_func_get_state(bp, &bp->func_obj) != 7915 BNX2X_F_STATE_STARTED && tout--) 7916 msleep(20); 7917 7918 if (bnx2x_func_get_state(bp, &bp->func_obj) != 7919 BNX2X_F_STATE_STARTED) { 7920#ifdef BNX2X_STOP_ON_ERROR 7921 return -EBUSY; 7922#else 7923 /* 7924 * Failed to complete the transaction in a "good way" 7925 * Force both transactions with CLR bit 7926 */ 7927 struct bnx2x_func_state_params func_params = {0}; 7928 7929 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! " 7930 "Forcing STARTED-->TX_ST0PPED-->STARTED\n"); 7931 7932 func_params.f_obj = &bp->func_obj; 7933 __set_bit(RAMROD_DRV_CLR_ONLY, 7934 &func_params.ramrod_flags); 7935 7936 /* STARTED-->TX_ST0PPED */ 7937 func_params.cmd = BNX2X_F_CMD_TX_STOP; 7938 bnx2x_func_state_change(bp, &func_params); 7939 7940 /* TX_ST0PPED-->STARTED */ 7941 func_params.cmd = BNX2X_F_CMD_TX_START; 7942 return bnx2x_func_state_change(bp, &func_params); 7943#endif 7944 } 7945 7946 return 0; 7947} 7948 7949void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) 7950{ 7951 int port = BP_PORT(bp); 7952 int i, rc = 0; 7953 u8 cos; 7954 struct bnx2x_mcast_ramrod_params rparam = {0}; 7955 u32 reset_code; 7956 7957 /* Wait until tx fastpath tasks complete */ 7958 for_each_tx_queue(bp, i) { 7959 struct bnx2x_fastpath *fp = &bp->fp[i]; 7960 7961 for_each_cos_in_tx_queue(fp, cos) 7962 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]); 7963#ifdef BNX2X_STOP_ON_ERROR 7964 if (rc) 7965 return; 7966#endif 7967 } 7968 7969 /* Give HW time to discard old tx messages */ 7970 usleep_range(1000, 1000); 7971 7972 /* Clean all ETH MACs */ 7973 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false); 7974 if (rc < 0) 7975 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); 7976 7977 /* Clean up UC list */ 7978 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, 7979 true); 7980 if (rc < 0) 7981 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: " 7982 "%d\n", rc); 7983 7984 /* Disable LLH */ 7985 if (!CHIP_IS_E1(bp)) 7986 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 7987 7988 /* Set "drop all" (stop Rx). 7989 * We need to take a netif_addr_lock() here in order to prevent 7990 * a race between the completion code and this code. 7991 */ 7992 netif_addr_lock_bh(bp->dev); 7993 /* Schedule the rx_mode command */ 7994 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 7995 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 7996 else 7997 bnx2x_set_storm_rx_mode(bp); 7998 7999 /* Cleanup multicast configuration */ 8000 rparam.mcast_obj = &bp->mcast_obj; 8001 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 8002 if (rc < 0) 8003 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); 8004 8005 netif_addr_unlock_bh(bp->dev); 8006 8007 8008 8009 /* 8010 * Send the UNLOAD_REQUEST to the MCP. This will return if 8011 * this function should perform FUNC, PORT or COMMON HW 8012 * reset. 8013 */ 8014 reset_code = bnx2x_send_unload_req(bp, unload_mode); 8015 8016 /* 8017 * (assumption: No Attention from MCP at this stage) 8018 * PMF probably in the middle of TXdisable/enable transaction 8019 */ 8020 rc = bnx2x_func_wait_started(bp); 8021 if (rc) { 8022 BNX2X_ERR("bnx2x_func_wait_started failed\n"); 8023#ifdef BNX2X_STOP_ON_ERROR 8024 return; 8025#endif 8026 } 8027 8028 /* Close multi and leading connections 8029 * Completions for ramrods are collected in a synchronous way 8030 */ 8031 for_each_queue(bp, i) 8032 if (bnx2x_stop_queue(bp, i)) 8033#ifdef BNX2X_STOP_ON_ERROR 8034 return; 8035#else 8036 goto unload_error; 8037#endif 8038 /* If SP settings didn't get completed so far - something 8039 * very wrong has happen. 8040 */ 8041 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) 8042 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); 8043 8044#ifndef BNX2X_STOP_ON_ERROR 8045unload_error: 8046#endif 8047 rc = bnx2x_func_stop(bp); 8048 if (rc) { 8049 BNX2X_ERR("Function stop failed!\n"); 8050#ifdef BNX2X_STOP_ON_ERROR 8051 return; 8052#endif 8053 } 8054 8055 /* Disable HW interrupts, NAPI */ 8056 bnx2x_netif_stop(bp, 1); 8057 8058 /* Release IRQs */ 8059 bnx2x_free_irq(bp); 8060 8061 /* Reset the chip */ 8062 rc = bnx2x_reset_hw(bp, reset_code); 8063 if (rc) 8064 BNX2X_ERR("HW_RESET failed\n"); 8065 8066 8067 /* Report UNLOAD_DONE to MCP */ 8068 bnx2x_send_unload_done(bp); 8069} 8070 8071void bnx2x_disable_close_the_gate(struct bnx2x *bp) 8072{ 8073 u32 val; 8074 8075 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n"); 8076 8077 if (CHIP_IS_E1(bp)) { 8078 int port = BP_PORT(bp); 8079 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8080 MISC_REG_AEU_MASK_ATTN_FUNC_0; 8081 8082 val = REG_RD(bp, addr); 8083 val &= ~(0x300); 8084 REG_WR(bp, addr, val); 8085 } else { 8086 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); 8087 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 8088 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 8089 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); 8090 } 8091} 8092 8093/* Close gates #2, #3 and #4: */ 8094static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 8095{ 8096 u32 val; 8097 8098 /* Gates #2 and #4a are closed/opened for "not E1" only */ 8099 if (!CHIP_IS_E1(bp)) { 8100 /* #4 */ 8101 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 8102 /* #2 */ 8103 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 8104 } 8105 8106 /* #3 */ 8107 if (CHIP_IS_E1x(bp)) { 8108 /* Prevent interrupts from HC on both ports */ 8109 val = REG_RD(bp, HC_REG_CONFIG_1); 8110 REG_WR(bp, HC_REG_CONFIG_1, 8111 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 8112 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 8113 8114 val = REG_RD(bp, HC_REG_CONFIG_0); 8115 REG_WR(bp, HC_REG_CONFIG_0, 8116 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 8117 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 8118 } else { 8119 /* Prevent incomming interrupts in IGU */ 8120 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 8121 8122 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, 8123 (!close) ? 8124 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 8125 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 8126 } 8127 8128 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n", 8129 close ? "closing" : "opening"); 8130 mmiowb(); 8131} 8132 8133#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ 8134 8135static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) 8136{ 8137 /* Do some magic... */ 8138 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8139 *magic_val = val & SHARED_MF_CLP_MAGIC; 8140 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 8141} 8142 8143/** 8144 * bnx2x_clp_reset_done - restore the value of the `magic' bit. 8145 * 8146 * @bp: driver handle 8147 * @magic_val: old value of the `magic' bit. 8148 */ 8149static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 8150{ 8151 /* Restore the `magic' bit value... */ 8152 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8153 MF_CFG_WR(bp, shared_mf_config.clp_mb, 8154 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 8155} 8156 8157/** 8158 * bnx2x_reset_mcp_prep - prepare for MCP reset. 8159 * 8160 * @bp: driver handle 8161 * @magic_val: old value of 'magic' bit. 8162 * 8163 * Takes care of CLP configurations. 8164 */ 8165static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 8166{ 8167 u32 shmem; 8168 u32 validity_offset; 8169 8170 DP(NETIF_MSG_HW, "Starting\n"); 8171 8172 /* Set `magic' bit in order to save MF config */ 8173 if (!CHIP_IS_E1(bp)) 8174 bnx2x_clp_reset_prep(bp, magic_val); 8175 8176 /* Get shmem offset */ 8177 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8178 validity_offset = offsetof(struct shmem_region, validity_map[0]); 8179 8180 /* Clear validity map flags */ 8181 if (shmem > 0) 8182 REG_WR(bp, shmem + validity_offset, 0); 8183} 8184 8185#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 8186#define MCP_ONE_TIMEOUT 100 /* 100 ms */ 8187 8188/** 8189 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT 8190 * 8191 * @bp: driver handle 8192 */ 8193static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) 8194{ 8195 /* special handling for emulation and FPGA, 8196 wait 10 times longer */ 8197 if (CHIP_REV_IS_SLOW(bp)) 8198 msleep(MCP_ONE_TIMEOUT*10); 8199 else 8200 msleep(MCP_ONE_TIMEOUT); 8201} 8202 8203/* 8204 * initializes bp->common.shmem_base and waits for validity signature to appear 8205 */ 8206static int bnx2x_init_shmem(struct bnx2x *bp) 8207{ 8208 int cnt = 0; 8209 u32 val = 0; 8210 8211 do { 8212 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8213 if (bp->common.shmem_base) { 8214 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 8215 if (val & SHR_MEM_VALIDITY_MB) 8216 return 0; 8217 } 8218 8219 bnx2x_mcp_wait_one(bp); 8220 8221 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 8222 8223 BNX2X_ERR("BAD MCP validity signature\n"); 8224 8225 return -ENODEV; 8226} 8227 8228static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 8229{ 8230 int rc = bnx2x_init_shmem(bp); 8231 8232 /* Restore the `magic' bit value */ 8233 if (!CHIP_IS_E1(bp)) 8234 bnx2x_clp_reset_done(bp, magic_val); 8235 8236 return rc; 8237} 8238 8239static void bnx2x_pxp_prep(struct bnx2x *bp) 8240{ 8241 if (!CHIP_IS_E1(bp)) { 8242 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 8243 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 8244 mmiowb(); 8245 } 8246} 8247 8248/* 8249 * Reset the whole chip except for: 8250 * - PCIE core 8251 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by 8252 * one reset bit) 8253 * - IGU 8254 * - MISC (including AEU) 8255 * - GRC 8256 * - RBCN, RBCP 8257 */ 8258static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) 8259{ 8260 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 8261 u32 global_bits2, stay_reset2; 8262 8263 /* 8264 * Bits that have to be set in reset_mask2 if we want to reset 'global' 8265 * (per chip) blocks. 8266 */ 8267 global_bits2 = 8268 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 8269 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 8270 8271 /* Don't reset the following blocks */ 8272 not_reset_mask1 = 8273 MISC_REGISTERS_RESET_REG_1_RST_HC | 8274 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 8275 MISC_REGISTERS_RESET_REG_1_RST_PXP; 8276 8277 not_reset_mask2 = 8278 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 8279 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 8280 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 8281 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 8282 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 8283 MISC_REGISTERS_RESET_REG_2_RST_GRC | 8284 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 8285 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 8286 MISC_REGISTERS_RESET_REG_2_RST_ATC | 8287 MISC_REGISTERS_RESET_REG_2_PGLC; 8288 8289 /* 8290 * Keep the following blocks in reset: 8291 * - all xxMACs are handled by the bnx2x_link code. 8292 */ 8293 stay_reset2 = 8294 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 8295 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 8296 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 8297 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 8298 MISC_REGISTERS_RESET_REG_2_UMAC0 | 8299 MISC_REGISTERS_RESET_REG_2_UMAC1 | 8300 MISC_REGISTERS_RESET_REG_2_XMAC | 8301 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 8302 8303 /* Full reset masks according to the chip */ 8304 reset_mask1 = 0xffffffff; 8305 8306 if (CHIP_IS_E1(bp)) 8307 reset_mask2 = 0xffff; 8308 else if (CHIP_IS_E1H(bp)) 8309 reset_mask2 = 0x1ffff; 8310 else if (CHIP_IS_E2(bp)) 8311 reset_mask2 = 0xfffff; 8312 else /* CHIP_IS_E3 */ 8313 reset_mask2 = 0x3ffffff; 8314 8315 /* Don't reset global blocks unless we need to */ 8316 if (!global) 8317 reset_mask2 &= ~global_bits2; 8318 8319 /* 8320 * In case of attention in the QM, we need to reset PXP 8321 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 8322 * because otherwise QM reset would release 'close the gates' shortly 8323 * before resetting the PXP, then the PSWRQ would send a write 8324 * request to PGLUE. Then when PXP is reset, PGLUE would try to 8325 * read the payload data from PSWWR, but PSWWR would not 8326 * respond. The write queue in PGLUE would stuck, dmae commands 8327 * would not return. Therefore it's important to reset the second 8328 * reset register (containing the 8329 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 8330 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 8331 * bit). 8332 */ 8333 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8334 reset_mask2 & (~not_reset_mask2)); 8335 8336 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8337 reset_mask1 & (~not_reset_mask1)); 8338 8339 barrier(); 8340 mmiowb(); 8341 8342 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 8343 reset_mask2 & (~stay_reset2)); 8344 8345 barrier(); 8346 mmiowb(); 8347 8348 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 8349 mmiowb(); 8350} 8351 8352/** 8353 * bnx2x_er_poll_igu_vq - poll for pending writes bit. 8354 * It should get cleared in no more than 1s. 8355 * 8356 * @bp: driver handle 8357 * 8358 * It should get cleared in no more than 1s. Returns 0 if 8359 * pending writes bit gets cleared. 8360 */ 8361static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) 8362{ 8363 u32 cnt = 1000; 8364 u32 pend_bits = 0; 8365 8366 do { 8367 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); 8368 8369 if (pend_bits == 0) 8370 break; 8371 8372 usleep_range(1000, 1000); 8373 } while (cnt-- > 0); 8374 8375 if (cnt <= 0) { 8376 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", 8377 pend_bits); 8378 return -EBUSY; 8379 } 8380 8381 return 0; 8382} 8383 8384static int bnx2x_process_kill(struct bnx2x *bp, bool global) 8385{ 8386 int cnt = 1000; 8387 u32 val = 0; 8388 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 8389 8390 8391 /* Empty the Tetris buffer, wait for 1s */ 8392 do { 8393 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); 8394 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); 8395 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); 8396 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); 8397 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); 8398 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 8399 ((port_is_idle_0 & 0x1) == 0x1) && 8400 ((port_is_idle_1 & 0x1) == 0x1) && 8401 (pgl_exp_rom2 == 0xffffffff)) 8402 break; 8403 usleep_range(1000, 1000); 8404 } while (cnt-- > 0); 8405 8406 if (cnt <= 0) { 8407 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there" 8408 " are still" 8409 " outstanding read requests after 1s!\n"); 8410 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x," 8411 " port_is_idle_0=0x%08x," 8412 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 8413 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 8414 pgl_exp_rom2); 8415 return -EAGAIN; 8416 } 8417 8418 barrier(); 8419 8420 /* Close gates #2, #3 and #4 */ 8421 bnx2x_set_234_gates(bp, true); 8422 8423 /* Poll for IGU VQs for 57712 and newer chips */ 8424 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) 8425 return -EAGAIN; 8426 8427 8428 /* TBD: Indicate that "process kill" is in progress to MCP */ 8429 8430 /* Clear "unprepared" bit */ 8431 REG_WR(bp, MISC_REG_UNPREPARED, 0); 8432 barrier(); 8433 8434 /* Make sure all is written to the chip before the reset */ 8435 mmiowb(); 8436 8437 /* Wait for 1ms to empty GLUE and PCI-E core queues, 8438 * PSWHST, GRC and PSWRD Tetris buffer. 8439 */ 8440 usleep_range(1000, 1000); 8441 8442 /* Prepare to chip reset: */ 8443 /* MCP */ 8444 if (global) 8445 bnx2x_reset_mcp_prep(bp, &val); 8446 8447 /* PXP */ 8448 bnx2x_pxp_prep(bp); 8449 barrier(); 8450 8451 /* reset the chip */ 8452 bnx2x_process_kill_chip_reset(bp, global); 8453 barrier(); 8454 8455 /* Recover after reset: */ 8456 /* MCP */ 8457 if (global && bnx2x_reset_mcp_comp(bp, val)) 8458 return -EAGAIN; 8459 8460 /* TBD: Add resetting the NO_MCP mode DB here */ 8461 8462 /* PXP */ 8463 bnx2x_pxp_prep(bp); 8464 8465 /* Open the gates #2, #3 and #4 */ 8466 bnx2x_set_234_gates(bp, false); 8467 8468 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a 8469 * reset state, re-enable attentions. */ 8470 8471 return 0; 8472} 8473 8474int bnx2x_leader_reset(struct bnx2x *bp) 8475{ 8476 int rc = 0; 8477 bool global = bnx2x_reset_is_global(bp); 8478 u32 load_code; 8479 8480 /* if not going to reset MCP - load "fake" driver to reset HW while 8481 * driver is owner of the HW 8482 */ 8483 if (!global && !BP_NOMCP(bp)) { 8484 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 0); 8485 if (!load_code) { 8486 BNX2X_ERR("MCP response failure, aborting\n"); 8487 rc = -EAGAIN; 8488 goto exit_leader_reset; 8489 } 8490 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && 8491 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { 8492 BNX2X_ERR("MCP unexpected resp, aborting\n"); 8493 rc = -EAGAIN; 8494 goto exit_leader_reset2; 8495 } 8496 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); 8497 if (!load_code) { 8498 BNX2X_ERR("MCP response failure, aborting\n"); 8499 rc = -EAGAIN; 8500 goto exit_leader_reset2; 8501 } 8502 } 8503 8504 /* Try to recover after the failure */ 8505 if (bnx2x_process_kill(bp, global)) { 8506 netdev_err(bp->dev, "Something bad had happen on engine %d! " 8507 "Aii!\n", BP_PATH(bp)); 8508 rc = -EAGAIN; 8509 goto exit_leader_reset2; 8510 } 8511 8512 /* 8513 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver 8514 * state. 8515 */ 8516 bnx2x_set_reset_done(bp); 8517 if (global) 8518 bnx2x_clear_reset_global(bp); 8519 8520exit_leader_reset2: 8521 /* unload "fake driver" if it was loaded */ 8522 if (!global && !BP_NOMCP(bp)) { 8523 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); 8524 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 8525 } 8526exit_leader_reset: 8527 bp->is_leader = 0; 8528 bnx2x_release_leader_lock(bp); 8529 smp_mb(); 8530 return rc; 8531} 8532 8533static inline void bnx2x_recovery_failed(struct bnx2x *bp) 8534{ 8535 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); 8536 8537 /* Disconnect this device */ 8538 netif_device_detach(bp->dev); 8539 8540 /* 8541 * Block ifup for all function on this engine until "process kill" 8542 * or power cycle. 8543 */ 8544 bnx2x_set_reset_in_progress(bp); 8545 8546 /* Shut down the power */ 8547 bnx2x_set_power_state(bp, PCI_D3hot); 8548 8549 bp->recovery_state = BNX2X_RECOVERY_FAILED; 8550 8551 smp_mb(); 8552} 8553 8554/* 8555 * Assumption: runs under rtnl lock. This together with the fact 8556 * that it's called only from bnx2x_sp_rtnl() ensure that it 8557 * will never be called when netif_running(bp->dev) is false. 8558 */ 8559static void bnx2x_parity_recover(struct bnx2x *bp) 8560{ 8561 bool global = false; 8562 u32 error_recovered, error_unrecovered; 8563 bool is_parity; 8564 8565 DP(NETIF_MSG_HW, "Handling parity\n"); 8566 while (1) { 8567 switch (bp->recovery_state) { 8568 case BNX2X_RECOVERY_INIT: 8569 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 8570 is_parity = bnx2x_chk_parity_attn(bp, &global, false); 8571 WARN_ON(!is_parity); 8572 8573 /* Try to get a LEADER_LOCK HW lock */ 8574 if (bnx2x_trylock_leader_lock(bp)) { 8575 bnx2x_set_reset_in_progress(bp); 8576 /* 8577 * Check if there is a global attention and if 8578 * there was a global attention, set the global 8579 * reset bit. 8580 */ 8581 8582 if (global) 8583 bnx2x_set_reset_global(bp); 8584 8585 bp->is_leader = 1; 8586 } 8587 8588 /* Stop the driver */ 8589 /* If interface has been removed - break */ 8590 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) 8591 return; 8592 8593 bp->recovery_state = BNX2X_RECOVERY_WAIT; 8594 8595 /* Ensure "is_leader", MCP command sequence and 8596 * "recovery_state" update values are seen on other 8597 * CPUs. 8598 */ 8599 smp_mb(); 8600 break; 8601 8602 case BNX2X_RECOVERY_WAIT: 8603 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 8604 if (bp->is_leader) { 8605 int other_engine = BP_PATH(bp) ? 0 : 1; 8606 bool other_load_status = 8607 bnx2x_get_load_status(bp, other_engine); 8608 bool load_status = 8609 bnx2x_get_load_status(bp, BP_PATH(bp)); 8610 global = bnx2x_reset_is_global(bp); 8611 8612 /* 8613 * In case of a parity in a global block, let 8614 * the first leader that performs a 8615 * leader_reset() reset the global blocks in 8616 * order to clear global attentions. Otherwise 8617 * the the gates will remain closed for that 8618 * engine. 8619 */ 8620 if (load_status || 8621 (global && other_load_status)) { 8622 /* Wait until all other functions get 8623 * down. 8624 */ 8625 schedule_delayed_work(&bp->sp_rtnl_task, 8626 HZ/10); 8627 return; 8628 } else { 8629 /* If all other functions got down - 8630 * try to bring the chip back to 8631 * normal. In any case it's an exit 8632 * point for a leader. 8633 */ 8634 if (bnx2x_leader_reset(bp)) { 8635 bnx2x_recovery_failed(bp); 8636 return; 8637 } 8638 8639 /* If we are here, means that the 8640 * leader has succeeded and doesn't 8641 * want to be a leader any more. Try 8642 * to continue as a none-leader. 8643 */ 8644 break; 8645 } 8646 } else { /* non-leader */ 8647 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { 8648 /* Try to get a LEADER_LOCK HW lock as 8649 * long as a former leader may have 8650 * been unloaded by the user or 8651 * released a leadership by another 8652 * reason. 8653 */ 8654 if (bnx2x_trylock_leader_lock(bp)) { 8655 /* I'm a leader now! Restart a 8656 * switch case. 8657 */ 8658 bp->is_leader = 1; 8659 break; 8660 } 8661 8662 schedule_delayed_work(&bp->sp_rtnl_task, 8663 HZ/10); 8664 return; 8665 8666 } else { 8667 /* 8668 * If there was a global attention, wait 8669 * for it to be cleared. 8670 */ 8671 if (bnx2x_reset_is_global(bp)) { 8672 schedule_delayed_work( 8673 &bp->sp_rtnl_task, 8674 HZ/10); 8675 return; 8676 } 8677 8678 error_recovered = 8679 bp->eth_stats.recoverable_error; 8680 error_unrecovered = 8681 bp->eth_stats.unrecoverable_error; 8682 bp->recovery_state = 8683 BNX2X_RECOVERY_NIC_LOADING; 8684 if (bnx2x_nic_load(bp, LOAD_NORMAL)) { 8685 error_unrecovered++; 8686 netdev_err(bp->dev, 8687 "Recovery failed. " 8688 "Power cycle " 8689 "needed\n"); 8690 /* Disconnect this device */ 8691 netif_device_detach(bp->dev); 8692 /* Shut down the power */ 8693 bnx2x_set_power_state( 8694 bp, PCI_D3hot); 8695 smp_mb(); 8696 } else { 8697 bp->recovery_state = 8698 BNX2X_RECOVERY_DONE; 8699 error_recovered++; 8700 smp_mb(); 8701 } 8702 bp->eth_stats.recoverable_error = 8703 error_recovered; 8704 bp->eth_stats.unrecoverable_error = 8705 error_unrecovered; 8706 8707 return; 8708 } 8709 } 8710 default: 8711 return; 8712 } 8713 } 8714} 8715 8716static int bnx2x_close(struct net_device *dev); 8717 8718/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is 8719 * scheduled on a general queue in order to prevent a dead lock. 8720 */ 8721static void bnx2x_sp_rtnl_task(struct work_struct *work) 8722{ 8723 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); 8724 8725 rtnl_lock(); 8726 8727 if (!netif_running(bp->dev)) 8728 goto sp_rtnl_exit; 8729 8730 /* if stop on error is defined no recovery flows should be executed */ 8731#ifdef BNX2X_STOP_ON_ERROR 8732 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined " 8733 "so reset not done to allow debug dump,\n" 8734 "you will need to reboot when done\n"); 8735 goto sp_rtnl_not_reset; 8736#endif 8737 8738 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { 8739 /* 8740 * Clear all pending SP commands as we are going to reset the 8741 * function anyway. 8742 */ 8743 bp->sp_rtnl_state = 0; 8744 smp_mb(); 8745 8746 bnx2x_parity_recover(bp); 8747 8748 goto sp_rtnl_exit; 8749 } 8750 8751 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { 8752 /* 8753 * Clear all pending SP commands as we are going to reset the 8754 * function anyway. 8755 */ 8756 bp->sp_rtnl_state = 0; 8757 smp_mb(); 8758 8759 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 8760 bnx2x_nic_load(bp, LOAD_NORMAL); 8761 8762 goto sp_rtnl_exit; 8763 } 8764#ifdef BNX2X_STOP_ON_ERROR 8765sp_rtnl_not_reset: 8766#endif 8767 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) 8768 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); 8769 8770 /* 8771 * in case of fan failure we need to reset id if the "stop on error" 8772 * debug flag is set, since we trying to prevent permanent overheating 8773 * damage 8774 */ 8775 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { 8776 DP(BNX2X_MSG_SP, "fan failure detected. Unloading driver\n"); 8777 netif_device_detach(bp->dev); 8778 bnx2x_close(bp->dev); 8779 } 8780 8781sp_rtnl_exit: 8782 rtnl_unlock(); 8783} 8784 8785/* end of nic load/unload */ 8786 8787static void bnx2x_period_task(struct work_struct *work) 8788{ 8789 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); 8790 8791 if (!netif_running(bp->dev)) 8792 goto period_task_exit; 8793 8794 if (CHIP_REV_IS_SLOW(bp)) { 8795 BNX2X_ERR("period task called on emulation, ignoring\n"); 8796 goto period_task_exit; 8797 } 8798 8799 bnx2x_acquire_phy_lock(bp); 8800 /* 8801 * The barrier is needed to ensure the ordering between the writing to 8802 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and 8803 * the reading here. 8804 */ 8805 smp_mb(); 8806 if (bp->port.pmf) { 8807 bnx2x_period_func(&bp->link_params, &bp->link_vars); 8808 8809 /* Re-queue task in 1 sec */ 8810 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); 8811 } 8812 8813 bnx2x_release_phy_lock(bp); 8814period_task_exit: 8815 return; 8816} 8817 8818/* 8819 * Init service functions 8820 */ 8821 8822static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) 8823{ 8824 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; 8825 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; 8826 return base + (BP_ABS_FUNC(bp)) * stride; 8827} 8828 8829static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) 8830{ 8831 u32 reg = bnx2x_get_pretend_reg(bp); 8832 8833 /* Flush all outstanding writes */ 8834 mmiowb(); 8835 8836 /* Pretend to be function 0 */ 8837 REG_WR(bp, reg, 0); 8838 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ 8839 8840 /* From now we are in the "like-E1" mode */ 8841 bnx2x_int_disable(bp); 8842 8843 /* Flush all outstanding writes */ 8844 mmiowb(); 8845 8846 /* Restore the original function */ 8847 REG_WR(bp, reg, BP_ABS_FUNC(bp)); 8848 REG_RD(bp, reg); 8849} 8850 8851static inline void bnx2x_undi_int_disable(struct bnx2x *bp) 8852{ 8853 if (CHIP_IS_E1(bp)) 8854 bnx2x_int_disable(bp); 8855 else 8856 bnx2x_undi_int_disable_e1h(bp); 8857} 8858 8859static void __devinit bnx2x_undi_unload(struct bnx2x *bp) 8860{ 8861 u32 val; 8862 8863 /* possibly another driver is trying to reset the chip */ 8864 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8865 8866 /* check if doorbell queue is reset */ 8867 if (REG_RD(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET) 8868 & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { 8869 8870 /* 8871 * Check if it is the UNDI driver 8872 * UNDI driver initializes CID offset for normal bell to 0x7 8873 */ 8874 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 8875 if (val == 0x7) { 8876 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8877 /* save our pf_num */ 8878 int orig_pf_num = bp->pf_num; 8879 int port; 8880 u32 swap_en, swap_val, value; 8881 8882 /* clear the UNDI indication */ 8883 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 8884 8885 BNX2X_DEV_INFO("UNDI is active! reset device\n"); 8886 8887 /* try unload UNDI on port 0 */ 8888 bp->pf_num = 0; 8889 bp->fw_seq = 8890 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8891 DRV_MSG_SEQ_NUMBER_MASK); 8892 reset_code = bnx2x_fw_command(bp, reset_code, 0); 8893 8894 /* if UNDI is loaded on the other port */ 8895 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { 8896 8897 /* send "DONE" for previous unload */ 8898 bnx2x_fw_command(bp, 8899 DRV_MSG_CODE_UNLOAD_DONE, 0); 8900 8901 /* unload UNDI on port 1 */ 8902 bp->pf_num = 1; 8903 bp->fw_seq = 8904 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8905 DRV_MSG_SEQ_NUMBER_MASK); 8906 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8907 8908 bnx2x_fw_command(bp, reset_code, 0); 8909 } 8910 8911 bnx2x_undi_int_disable(bp); 8912 port = BP_PORT(bp); 8913 8914 /* close input traffic and wait for it */ 8915 /* Do not rcv packets to BRB */ 8916 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK : 8917 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0); 8918 /* Do not direct rcv packets that are not for MCP to 8919 * the BRB */ 8920 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 8921 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 8922 /* clear AEU */ 8923 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8924 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0); 8925 msleep(10); 8926 8927 /* save NIG port swap info */ 8928 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 8929 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 8930 /* reset device */ 8931 REG_WR(bp, 8932 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8933 0xd3ffffff); 8934 8935 value = 0x1400; 8936 if (CHIP_IS_E3(bp)) { 8937 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 8938 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 8939 } 8940 8941 REG_WR(bp, 8942 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8943 value); 8944 8945 /* take the NIG out of reset and restore swap values */ 8946 REG_WR(bp, 8947 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 8948 MISC_REGISTERS_RESET_REG_1_RST_NIG); 8949 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val); 8950 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en); 8951 8952 /* send unload done to the MCP */ 8953 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 8954 8955 /* restore our func and fw_seq */ 8956 bp->pf_num = orig_pf_num; 8957 } 8958 } 8959 8960 /* now it's safe to release the lock */ 8961 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8962} 8963 8964static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) 8965{ 8966 u32 val, val2, val3, val4, id, boot_mode; 8967 u16 pmc; 8968 8969 /* Get the chip revision id and number. */ 8970 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 8971 val = REG_RD(bp, MISC_REG_CHIP_NUM); 8972 id = ((val & 0xffff) << 16); 8973 val = REG_RD(bp, MISC_REG_CHIP_REV); 8974 id |= ((val & 0xf) << 12); 8975 val = REG_RD(bp, MISC_REG_CHIP_METAL); 8976 id |= ((val & 0xff) << 4); 8977 val = REG_RD(bp, MISC_REG_BOND_ID); 8978 id |= (val & 0xf); 8979 bp->common.chip_id = id; 8980 8981 /* Set doorbell size */ 8982 bp->db_size = (1 << BNX2X_DB_SHIFT); 8983 8984 if (!CHIP_IS_E1x(bp)) { 8985 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 8986 if ((val & 1) == 0) 8987 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); 8988 else 8989 val = (val >> 1) & 1; 8990 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : 8991 "2_PORT_MODE"); 8992 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : 8993 CHIP_2_PORT_MODE; 8994 8995 if (CHIP_MODE_IS_4_PORT(bp)) 8996 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ 8997 else 8998 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ 8999 } else { 9000 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ 9001 bp->pfid = bp->pf_num; /* 0..7 */ 9002 } 9003 9004 bp->link_params.chip_id = bp->common.chip_id; 9005 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 9006 9007 val = (REG_RD(bp, 0x2874) & 0x55); 9008 if ((bp->common.chip_id & 0x1) || 9009 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { 9010 bp->flags |= ONE_PORT_FLAG; 9011 BNX2X_DEV_INFO("single port device\n"); 9012 } 9013 9014 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); 9015 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << 9016 (val & MCPR_NVM_CFG4_FLASH_SIZE)); 9017 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 9018 bp->common.flash_size, bp->common.flash_size); 9019 9020 bnx2x_init_shmem(bp); 9021 9022 9023 9024 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? 9025 MISC_REG_GENERIC_CR_1 : 9026 MISC_REG_GENERIC_CR_0)); 9027 9028 bp->link_params.shmem_base = bp->common.shmem_base; 9029 bp->link_params.shmem2_base = bp->common.shmem2_base; 9030 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 9031 bp->common.shmem_base, bp->common.shmem2_base); 9032 9033 if (!bp->common.shmem_base) { 9034 BNX2X_DEV_INFO("MCP not active\n"); 9035 bp->flags |= NO_MCP_FLAG; 9036 return; 9037 } 9038 9039 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 9040 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 9041 9042 bp->link_params.hw_led_mode = ((bp->common.hw_config & 9043 SHARED_HW_CFG_LED_MODE_MASK) >> 9044 SHARED_HW_CFG_LED_MODE_SHIFT); 9045 9046 bp->link_params.feature_config_flags = 0; 9047 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); 9048 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) 9049 bp->link_params.feature_config_flags |= 9050 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 9051 else 9052 bp->link_params.feature_config_flags &= 9053 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 9054 9055 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 9056 bp->common.bc_ver = val; 9057 BNX2X_DEV_INFO("bc_ver %X\n", val); 9058 if (val < BNX2X_BC_VER) { 9059 /* for now only warn 9060 * later we might need to enforce this */ 9061 BNX2X_ERR("This driver needs bc_ver %X but found %X, " 9062 "please upgrade BC\n", BNX2X_BC_VER, val); 9063 } 9064 bp->link_params.feature_config_flags |= 9065 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 9066 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 9067 9068 bp->link_params.feature_config_flags |= 9069 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? 9070 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; 9071 9072 bp->link_params.feature_config_flags |= 9073 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? 9074 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; 9075 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? 9076 BC_SUPPORTS_PFC_STATS : 0; 9077 9078 boot_mode = SHMEM_RD(bp, 9079 dev_info.port_feature_config[BP_PORT(bp)].mba_config) & 9080 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; 9081 switch (boot_mode) { 9082 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: 9083 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; 9084 break; 9085 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: 9086 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; 9087 break; 9088 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: 9089 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; 9090 break; 9091 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: 9092 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; 9093 break; 9094 } 9095 9096 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); 9097 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; 9098 9099 BNX2X_DEV_INFO("%sWoL capable\n", 9100 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 9101 9102 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 9103 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 9104 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); 9105 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); 9106 9107 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", 9108 val, val2, val3, val4); 9109} 9110 9111#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 9112#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 9113 9114static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) 9115{ 9116 int pfid = BP_FUNC(bp); 9117 int igu_sb_id; 9118 u32 val; 9119 u8 fid, igu_sb_cnt = 0; 9120 9121 bp->igu_base_sb = 0xff; 9122 if (CHIP_INT_MODE_IS_BC(bp)) { 9123 int vn = BP_VN(bp); 9124 igu_sb_cnt = bp->igu_sb_cnt; 9125 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 9126 FP_SB_MAX_E1x; 9127 9128 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + 9129 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); 9130 9131 return; 9132 } 9133 9134 /* IGU in normal mode - read CAM */ 9135 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 9136 igu_sb_id++) { 9137 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 9138 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 9139 continue; 9140 fid = IGU_FID(val); 9141 if ((fid & IGU_FID_ENCODE_IS_PF)) { 9142 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) 9143 continue; 9144 if (IGU_VEC(val) == 0) 9145 /* default status block */ 9146 bp->igu_dsb_id = igu_sb_id; 9147 else { 9148 if (bp->igu_base_sb == 0xff) 9149 bp->igu_base_sb = igu_sb_id; 9150 igu_sb_cnt++; 9151 } 9152 } 9153 } 9154 9155#ifdef CONFIG_PCI_MSI 9156 /* 9157 * It's expected that number of CAM entries for this functions is equal 9158 * to the number evaluated based on the MSI-X table size. We want a 9159 * harsh warning if these values are different! 9160 */ 9161 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); 9162#endif 9163 9164 if (igu_sb_cnt == 0) 9165 BNX2X_ERR("CAM configuration error\n"); 9166} 9167 9168static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, 9169 u32 switch_cfg) 9170{ 9171 int cfg_size = 0, idx, port = BP_PORT(bp); 9172 9173 /* Aggregation of supported attributes of all external phys */ 9174 bp->port.supported[0] = 0; 9175 bp->port.supported[1] = 0; 9176 switch (bp->link_params.num_phys) { 9177 case 1: 9178 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; 9179 cfg_size = 1; 9180 break; 9181 case 2: 9182 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; 9183 cfg_size = 1; 9184 break; 9185 case 3: 9186 if (bp->link_params.multi_phy_config & 9187 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 9188 bp->port.supported[1] = 9189 bp->link_params.phy[EXT_PHY1].supported; 9190 bp->port.supported[0] = 9191 bp->link_params.phy[EXT_PHY2].supported; 9192 } else { 9193 bp->port.supported[0] = 9194 bp->link_params.phy[EXT_PHY1].supported; 9195 bp->port.supported[1] = 9196 bp->link_params.phy[EXT_PHY2].supported; 9197 } 9198 cfg_size = 2; 9199 break; 9200 } 9201 9202 if (!(bp->port.supported[0] || bp->port.supported[1])) { 9203 BNX2X_ERR("NVRAM config error. BAD phy config." 9204 "PHY1 config 0x%x, PHY2 config 0x%x\n", 9205 SHMEM_RD(bp, 9206 dev_info.port_hw_config[port].external_phy_config), 9207 SHMEM_RD(bp, 9208 dev_info.port_hw_config[port].external_phy_config2)); 9209 return; 9210 } 9211 9212 if (CHIP_IS_E3(bp)) 9213 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); 9214 else { 9215 switch (switch_cfg) { 9216 case SWITCH_CFG_1G: 9217 bp->port.phy_addr = REG_RD( 9218 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 9219 break; 9220 case SWITCH_CFG_10G: 9221 bp->port.phy_addr = REG_RD( 9222 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 9223 break; 9224 default: 9225 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 9226 bp->port.link_config[0]); 9227 return; 9228 } 9229 } 9230 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 9231 /* mask what we support according to speed_cap_mask per configuration */ 9232 for (idx = 0; idx < cfg_size; idx++) { 9233 if (!(bp->link_params.speed_cap_mask[idx] & 9234 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 9235 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; 9236 9237 if (!(bp->link_params.speed_cap_mask[idx] & 9238 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 9239 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; 9240 9241 if (!(bp->link_params.speed_cap_mask[idx] & 9242 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 9243 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; 9244 9245 if (!(bp->link_params.speed_cap_mask[idx] & 9246 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 9247 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; 9248 9249 if (!(bp->link_params.speed_cap_mask[idx] & 9250 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 9251 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | 9252 SUPPORTED_1000baseT_Full); 9253 9254 if (!(bp->link_params.speed_cap_mask[idx] & 9255 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 9256 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; 9257 9258 if (!(bp->link_params.speed_cap_mask[idx] & 9259 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 9260 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; 9261 9262 } 9263 9264 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], 9265 bp->port.supported[1]); 9266} 9267 9268static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) 9269{ 9270 u32 link_config, idx, cfg_size = 0; 9271 bp->port.advertising[0] = 0; 9272 bp->port.advertising[1] = 0; 9273 switch (bp->link_params.num_phys) { 9274 case 1: 9275 case 2: 9276 cfg_size = 1; 9277 break; 9278 case 3: 9279 cfg_size = 2; 9280 break; 9281 } 9282 for (idx = 0; idx < cfg_size; idx++) { 9283 bp->link_params.req_duplex[idx] = DUPLEX_FULL; 9284 link_config = bp->port.link_config[idx]; 9285 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 9286 case PORT_FEATURE_LINK_SPEED_AUTO: 9287 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { 9288 bp->link_params.req_line_speed[idx] = 9289 SPEED_AUTO_NEG; 9290 bp->port.advertising[idx] |= 9291 bp->port.supported[idx]; 9292 if (bp->link_params.phy[EXT_PHY1].type == 9293 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 9294 bp->port.advertising[idx] |= 9295 (SUPPORTED_100baseT_Half | 9296 SUPPORTED_100baseT_Full); 9297 } else { 9298 /* force 10G, no AN */ 9299 bp->link_params.req_line_speed[idx] = 9300 SPEED_10000; 9301 bp->port.advertising[idx] |= 9302 (ADVERTISED_10000baseT_Full | 9303 ADVERTISED_FIBRE); 9304 continue; 9305 } 9306 break; 9307 9308 case PORT_FEATURE_LINK_SPEED_10M_FULL: 9309 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { 9310 bp->link_params.req_line_speed[idx] = 9311 SPEED_10; 9312 bp->port.advertising[idx] |= 9313 (ADVERTISED_10baseT_Full | 9314 ADVERTISED_TP); 9315 } else { 9316 BNX2X_ERR("NVRAM config error. " 9317 "Invalid link_config 0x%x" 9318 " speed_cap_mask 0x%x\n", 9319 link_config, 9320 bp->link_params.speed_cap_mask[idx]); 9321 return; 9322 } 9323 break; 9324 9325 case PORT_FEATURE_LINK_SPEED_10M_HALF: 9326 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { 9327 bp->link_params.req_line_speed[idx] = 9328 SPEED_10; 9329 bp->link_params.req_duplex[idx] = 9330 DUPLEX_HALF; 9331 bp->port.advertising[idx] |= 9332 (ADVERTISED_10baseT_Half | 9333 ADVERTISED_TP); 9334 } else { 9335 BNX2X_ERR("NVRAM config error. " 9336 "Invalid link_config 0x%x" 9337 " speed_cap_mask 0x%x\n", 9338 link_config, 9339 bp->link_params.speed_cap_mask[idx]); 9340 return; 9341 } 9342 break; 9343 9344 case PORT_FEATURE_LINK_SPEED_100M_FULL: 9345 if (bp->port.supported[idx] & 9346 SUPPORTED_100baseT_Full) { 9347 bp->link_params.req_line_speed[idx] = 9348 SPEED_100; 9349 bp->port.advertising[idx] |= 9350 (ADVERTISED_100baseT_Full | 9351 ADVERTISED_TP); 9352 } else { 9353 BNX2X_ERR("NVRAM config error. " 9354 "Invalid link_config 0x%x" 9355 " speed_cap_mask 0x%x\n", 9356 link_config, 9357 bp->link_params.speed_cap_mask[idx]); 9358 return; 9359 } 9360 break; 9361 9362 case PORT_FEATURE_LINK_SPEED_100M_HALF: 9363 if (bp->port.supported[idx] & 9364 SUPPORTED_100baseT_Half) { 9365 bp->link_params.req_line_speed[idx] = 9366 SPEED_100; 9367 bp->link_params.req_duplex[idx] = 9368 DUPLEX_HALF; 9369 bp->port.advertising[idx] |= 9370 (ADVERTISED_100baseT_Half | 9371 ADVERTISED_TP); 9372 } else { 9373 BNX2X_ERR("NVRAM config error. " 9374 "Invalid link_config 0x%x" 9375 " speed_cap_mask 0x%x\n", 9376 link_config, 9377 bp->link_params.speed_cap_mask[idx]); 9378 return; 9379 } 9380 break; 9381 9382 case PORT_FEATURE_LINK_SPEED_1G: 9383 if (bp->port.supported[idx] & 9384 SUPPORTED_1000baseT_Full) { 9385 bp->link_params.req_line_speed[idx] = 9386 SPEED_1000; 9387 bp->port.advertising[idx] |= 9388 (ADVERTISED_1000baseT_Full | 9389 ADVERTISED_TP); 9390 } else { 9391 BNX2X_ERR("NVRAM config error. " 9392 "Invalid link_config 0x%x" 9393 " speed_cap_mask 0x%x\n", 9394 link_config, 9395 bp->link_params.speed_cap_mask[idx]); 9396 return; 9397 } 9398 break; 9399 9400 case PORT_FEATURE_LINK_SPEED_2_5G: 9401 if (bp->port.supported[idx] & 9402 SUPPORTED_2500baseX_Full) { 9403 bp->link_params.req_line_speed[idx] = 9404 SPEED_2500; 9405 bp->port.advertising[idx] |= 9406 (ADVERTISED_2500baseX_Full | 9407 ADVERTISED_TP); 9408 } else { 9409 BNX2X_ERR("NVRAM config error. " 9410 "Invalid link_config 0x%x" 9411 " speed_cap_mask 0x%x\n", 9412 link_config, 9413 bp->link_params.speed_cap_mask[idx]); 9414 return; 9415 } 9416 break; 9417 9418 case PORT_FEATURE_LINK_SPEED_10G_CX4: 9419 if (bp->port.supported[idx] & 9420 SUPPORTED_10000baseT_Full) { 9421 bp->link_params.req_line_speed[idx] = 9422 SPEED_10000; 9423 bp->port.advertising[idx] |= 9424 (ADVERTISED_10000baseT_Full | 9425 ADVERTISED_FIBRE); 9426 } else { 9427 BNX2X_ERR("NVRAM config error. " 9428 "Invalid link_config 0x%x" 9429 " speed_cap_mask 0x%x\n", 9430 link_config, 9431 bp->link_params.speed_cap_mask[idx]); 9432 return; 9433 } 9434 break; 9435 case PORT_FEATURE_LINK_SPEED_20G: 9436 bp->link_params.req_line_speed[idx] = SPEED_20000; 9437 9438 break; 9439 default: 9440 BNX2X_ERR("NVRAM config error. " 9441 "BAD link speed link_config 0x%x\n", 9442 link_config); 9443 bp->link_params.req_line_speed[idx] = 9444 SPEED_AUTO_NEG; 9445 bp->port.advertising[idx] = 9446 bp->port.supported[idx]; 9447 break; 9448 } 9449 9450 bp->link_params.req_flow_ctrl[idx] = (link_config & 9451 PORT_FEATURE_FLOW_CONTROL_MASK); 9452 if ((bp->link_params.req_flow_ctrl[idx] == 9453 BNX2X_FLOW_CTRL_AUTO) && 9454 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { 9455 bp->link_params.req_flow_ctrl[idx] = 9456 BNX2X_FLOW_CTRL_NONE; 9457 } 9458 9459 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl" 9460 " 0x%x advertising 0x%x\n", 9461 bp->link_params.req_line_speed[idx], 9462 bp->link_params.req_duplex[idx], 9463 bp->link_params.req_flow_ctrl[idx], 9464 bp->port.advertising[idx]); 9465 } 9466} 9467 9468static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 9469{ 9470 mac_hi = cpu_to_be16(mac_hi); 9471 mac_lo = cpu_to_be32(mac_lo); 9472 memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); 9473 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); 9474} 9475 9476static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) 9477{ 9478 int port = BP_PORT(bp); 9479 u32 config; 9480 u32 ext_phy_type, ext_phy_config; 9481 9482 bp->link_params.bp = bp; 9483 bp->link_params.port = port; 9484 9485 bp->link_params.lane_config = 9486 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 9487 9488 bp->link_params.speed_cap_mask[0] = 9489 SHMEM_RD(bp, 9490 dev_info.port_hw_config[port].speed_capability_mask); 9491 bp->link_params.speed_cap_mask[1] = 9492 SHMEM_RD(bp, 9493 dev_info.port_hw_config[port].speed_capability_mask2); 9494 bp->port.link_config[0] = 9495 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 9496 9497 bp->port.link_config[1] = 9498 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); 9499 9500 bp->link_params.multi_phy_config = 9501 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); 9502 /* If the device is capable of WoL, set the default state according 9503 * to the HW 9504 */ 9505 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 9506 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 9507 (config & PORT_FEATURE_WOL_ENABLED)); 9508 9509 BNX2X_DEV_INFO("lane_config 0x%08x " 9510 "speed_cap_mask0 0x%08x link_config0 0x%08x\n", 9511 bp->link_params.lane_config, 9512 bp->link_params.speed_cap_mask[0], 9513 bp->port.link_config[0]); 9514 9515 bp->link_params.switch_cfg = (bp->port.link_config[0] & 9516 PORT_FEATURE_CONNECTED_SWITCH_MASK); 9517 bnx2x_phy_probe(&bp->link_params); 9518 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 9519 9520 bnx2x_link_settings_requested(bp); 9521 9522 /* 9523 * If connected directly, work with the internal PHY, otherwise, work 9524 * with the external PHY 9525 */ 9526 ext_phy_config = 9527 SHMEM_RD(bp, 9528 dev_info.port_hw_config[port].external_phy_config); 9529 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 9530 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 9531 bp->mdio.prtad = bp->port.phy_addr; 9532 9533 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 9534 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 9535 bp->mdio.prtad = 9536 XGXS_EXT_PHY_ADDR(ext_phy_config); 9537 9538 /* 9539 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) 9540 * In MF mode, it is set to cover self test cases 9541 */ 9542 if (IS_MF(bp)) 9543 bp->port.need_hw_lock = 1; 9544 else 9545 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, 9546 bp->common.shmem_base, 9547 bp->common.shmem2_base); 9548} 9549 9550void bnx2x_get_iscsi_info(struct bnx2x *bp) 9551{ 9552#ifdef BCM_CNIC 9553 int port = BP_PORT(bp); 9554 9555 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9556 drv_lic_key[port].max_iscsi_conn); 9557 9558 /* Get the number of maximum allowed iSCSI connections */ 9559 bp->cnic_eth_dev.max_iscsi_conn = 9560 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> 9561 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; 9562 9563 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", 9564 bp->cnic_eth_dev.max_iscsi_conn); 9565 9566 /* 9567 * If maximum allowed number of connections is zero - 9568 * disable the feature. 9569 */ 9570 if (!bp->cnic_eth_dev.max_iscsi_conn) 9571 bp->flags |= NO_ISCSI_FLAG; 9572#else 9573 bp->flags |= NO_ISCSI_FLAG; 9574#endif 9575} 9576 9577static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp) 9578{ 9579#ifdef BCM_CNIC 9580 int port = BP_PORT(bp); 9581 int func = BP_ABS_FUNC(bp); 9582 9583 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9584 drv_lic_key[port].max_fcoe_conn); 9585 9586 /* Get the number of maximum allowed FCoE connections */ 9587 bp->cnic_eth_dev.max_fcoe_conn = 9588 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> 9589 BNX2X_MAX_FCOE_INIT_CONN_SHIFT; 9590 9591 /* Read the WWN: */ 9592 if (!IS_MF(bp)) { 9593 /* Port info */ 9594 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9595 SHMEM_RD(bp, 9596 dev_info.port_hw_config[port]. 9597 fcoe_wwn_port_name_upper); 9598 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9599 SHMEM_RD(bp, 9600 dev_info.port_hw_config[port]. 9601 fcoe_wwn_port_name_lower); 9602 9603 /* Node info */ 9604 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9605 SHMEM_RD(bp, 9606 dev_info.port_hw_config[port]. 9607 fcoe_wwn_node_name_upper); 9608 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9609 SHMEM_RD(bp, 9610 dev_info.port_hw_config[port]. 9611 fcoe_wwn_node_name_lower); 9612 } else if (!IS_MF_SD(bp)) { 9613 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9614 9615 /* 9616 * Read the WWN info only if the FCoE feature is enabled for 9617 * this function. 9618 */ 9619 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9620 /* Port info */ 9621 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9622 MF_CFG_RD(bp, func_ext_config[func]. 9623 fcoe_wwn_port_name_upper); 9624 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9625 MF_CFG_RD(bp, func_ext_config[func]. 9626 fcoe_wwn_port_name_lower); 9627 9628 /* Node info */ 9629 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9630 MF_CFG_RD(bp, func_ext_config[func]. 9631 fcoe_wwn_node_name_upper); 9632 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9633 MF_CFG_RD(bp, func_ext_config[func]. 9634 fcoe_wwn_node_name_lower); 9635 } 9636 } 9637 9638 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); 9639 9640 /* 9641 * If maximum allowed number of connections is zero - 9642 * disable the feature. 9643 */ 9644 if (!bp->cnic_eth_dev.max_fcoe_conn) 9645 bp->flags |= NO_FCOE_FLAG; 9646#else 9647 bp->flags |= NO_FCOE_FLAG; 9648#endif 9649} 9650 9651static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) 9652{ 9653 /* 9654 * iSCSI may be dynamically disabled but reading 9655 * info here we will decrease memory usage by driver 9656 * if the feature is disabled for good 9657 */ 9658 bnx2x_get_iscsi_info(bp); 9659 bnx2x_get_fcoe_info(bp); 9660} 9661 9662static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) 9663{ 9664 u32 val, val2; 9665 int func = BP_ABS_FUNC(bp); 9666 int port = BP_PORT(bp); 9667#ifdef BCM_CNIC 9668 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; 9669 u8 *fip_mac = bp->fip_mac; 9670#endif 9671 9672 /* Zero primary MAC configuration */ 9673 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9674 9675 if (BP_NOMCP(bp)) { 9676 BNX2X_ERROR("warning: random MAC workaround active\n"); 9677 eth_hw_addr_random(bp->dev); 9678 } else if (IS_MF(bp)) { 9679 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 9680 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); 9681 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && 9682 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) 9683 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9684 9685#ifdef BCM_CNIC 9686 /* 9687 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or 9688 * FCoE MAC then the appropriate feature should be disabled. 9689 */ 9690 if (IS_MF_SI(bp)) { 9691 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9692 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 9693 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9694 iscsi_mac_addr_upper); 9695 val = MF_CFG_RD(bp, func_ext_config[func]. 9696 iscsi_mac_addr_lower); 9697 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9698 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9699 iscsi_mac); 9700 } else 9701 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 9702 9703 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9704 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9705 fcoe_mac_addr_upper); 9706 val = MF_CFG_RD(bp, func_ext_config[func]. 9707 fcoe_mac_addr_lower); 9708 bnx2x_set_mac_buf(fip_mac, val, val2); 9709 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n", 9710 fip_mac); 9711 9712 } else 9713 bp->flags |= NO_FCOE_FLAG; 9714 } else { /* SD mode */ 9715 if (BNX2X_IS_MF_PROTOCOL_ISCSI(bp)) { 9716 /* use primary mac as iscsi mac */ 9717 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); 9718 /* Zero primary MAC configuration */ 9719 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9720 9721 BNX2X_DEV_INFO("SD ISCSI MODE\n"); 9722 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9723 iscsi_mac); 9724 } 9725 } 9726#endif 9727 } else { 9728 /* in SF read MACs from port configuration */ 9729 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 9730 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 9731 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9732 9733#ifdef BCM_CNIC 9734 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9735 iscsi_mac_upper); 9736 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9737 iscsi_mac_lower); 9738 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9739 9740 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9741 fcoe_fip_mac_upper); 9742 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9743 fcoe_fip_mac_lower); 9744 bnx2x_set_mac_buf(fip_mac, val, val2); 9745#endif 9746 } 9747 9748 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 9749 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); 9750 9751#ifdef BCM_CNIC 9752 /* Set the FCoE MAC in MF_SD mode */ 9753 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp)) 9754 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); 9755 9756 /* Disable iSCSI if MAC configuration is 9757 * invalid. 9758 */ 9759 if (!is_valid_ether_addr(iscsi_mac)) { 9760 bp->flags |= NO_ISCSI_FLAG; 9761 memset(iscsi_mac, 0, ETH_ALEN); 9762 } 9763 9764 /* Disable FCoE if MAC configuration is 9765 * invalid. 9766 */ 9767 if (!is_valid_ether_addr(fip_mac)) { 9768 bp->flags |= NO_FCOE_FLAG; 9769 memset(bp->fip_mac, 0, ETH_ALEN); 9770 } 9771#endif 9772 9773 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) 9774 dev_err(&bp->pdev->dev, 9775 "bad Ethernet MAC address configuration: " 9776 "%pM, change it manually before bringing up " 9777 "the appropriate network interface\n", 9778 bp->dev->dev_addr); 9779} 9780 9781static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) 9782{ 9783 int /*abs*/func = BP_ABS_FUNC(bp); 9784 int vn; 9785 u32 val = 0; 9786 int rc = 0; 9787 9788 bnx2x_get_common_hwinfo(bp); 9789 9790 /* 9791 * initialize IGU parameters 9792 */ 9793 if (CHIP_IS_E1x(bp)) { 9794 bp->common.int_block = INT_BLOCK_HC; 9795 9796 bp->igu_dsb_id = DEF_SB_IGU_ID; 9797 bp->igu_base_sb = 0; 9798 } else { 9799 bp->common.int_block = INT_BLOCK_IGU; 9800 9801 /* do not allow device reset during IGU info preocessing */ 9802 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9803 9804 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 9805 9806 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9807 int tout = 5000; 9808 9809 BNX2X_DEV_INFO("FORCING Normal Mode\n"); 9810 9811 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 9812 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); 9813 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); 9814 9815 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9816 tout--; 9817 usleep_range(1000, 1000); 9818 } 9819 9820 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9821 dev_err(&bp->pdev->dev, 9822 "FORCING Normal Mode failed!!!\n"); 9823 return -EPERM; 9824 } 9825 } 9826 9827 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9828 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); 9829 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; 9830 } else 9831 BNX2X_DEV_INFO("IGU Normal Mode\n"); 9832 9833 bnx2x_get_igu_cam_info(bp); 9834 9835 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9836 } 9837 9838 /* 9839 * set base FW non-default (fast path) status block id, this value is 9840 * used to initialize the fw_sb_id saved on the fp/queue structure to 9841 * determine the id used by the FW. 9842 */ 9843 if (CHIP_IS_E1x(bp)) 9844 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); 9845 else /* 9846 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of 9847 * the same queue are indicated on the same IGU SB). So we prefer 9848 * FW and IGU SBs to be the same value. 9849 */ 9850 bp->base_fw_ndsb = bp->igu_base_sb; 9851 9852 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" 9853 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, 9854 bp->igu_sb_cnt, bp->base_fw_ndsb); 9855 9856 /* 9857 * Initialize MF configuration 9858 */ 9859 9860 bp->mf_ov = 0; 9861 bp->mf_mode = 0; 9862 vn = BP_VN(bp); 9863 9864 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 9865 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 9866 bp->common.shmem2_base, SHMEM2_RD(bp, size), 9867 (u32)offsetof(struct shmem2_region, mf_cfg_addr)); 9868 9869 if (SHMEM2_HAS(bp, mf_cfg_addr)) 9870 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); 9871 else 9872 bp->common.mf_cfg_base = bp->common.shmem_base + 9873 offsetof(struct shmem_region, func_mb) + 9874 E1H_FUNC_MAX * sizeof(struct drv_func_mb); 9875 /* 9876 * get mf configuration: 9877 * 1. existence of MF configuration 9878 * 2. MAC address must be legal (check only upper bytes) 9879 * for Switch-Independent mode; 9880 * OVLAN must be legal for Switch-Dependent mode 9881 * 3. SF_MODE configures specific MF mode 9882 */ 9883 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9884 /* get mf configuration */ 9885 val = SHMEM_RD(bp, 9886 dev_info.shared_feature_config.config); 9887 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; 9888 9889 switch (val) { 9890 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 9891 val = MF_CFG_RD(bp, func_mf_config[func]. 9892 mac_upper); 9893 /* check for legal mac (upper bytes)*/ 9894 if (val != 0xffff) { 9895 bp->mf_mode = MULTI_FUNCTION_SI; 9896 bp->mf_config[vn] = MF_CFG_RD(bp, 9897 func_mf_config[func].config); 9898 } else 9899 BNX2X_DEV_INFO("illegal MAC address " 9900 "for SI\n"); 9901 break; 9902 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 9903 /* get OV configuration */ 9904 val = MF_CFG_RD(bp, 9905 func_mf_config[FUNC_0].e1hov_tag); 9906 val &= FUNC_MF_CFG_E1HOV_TAG_MASK; 9907 9908 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9909 bp->mf_mode = MULTI_FUNCTION_SD; 9910 bp->mf_config[vn] = MF_CFG_RD(bp, 9911 func_mf_config[func].config); 9912 } else 9913 BNX2X_DEV_INFO("illegal OV for SD\n"); 9914 break; 9915 default: 9916 /* Unknown configuration: reset mf_config */ 9917 bp->mf_config[vn] = 0; 9918 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val); 9919 } 9920 } 9921 9922 BNX2X_DEV_INFO("%s function mode\n", 9923 IS_MF(bp) ? "multi" : "single"); 9924 9925 switch (bp->mf_mode) { 9926 case MULTI_FUNCTION_SD: 9927 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 9928 FUNC_MF_CFG_E1HOV_TAG_MASK; 9929 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9930 bp->mf_ov = val; 9931 bp->path_has_ovlan = true; 9932 9933 BNX2X_DEV_INFO("MF OV for func %d is %d " 9934 "(0x%04x)\n", func, bp->mf_ov, 9935 bp->mf_ov); 9936 } else { 9937 dev_err(&bp->pdev->dev, 9938 "No valid MF OV for func %d, " 9939 "aborting\n", func); 9940 return -EPERM; 9941 } 9942 break; 9943 case MULTI_FUNCTION_SI: 9944 BNX2X_DEV_INFO("func %d is in MF " 9945 "switch-independent mode\n", func); 9946 break; 9947 default: 9948 if (vn) { 9949 dev_err(&bp->pdev->dev, 9950 "VN %d is in a single function mode, " 9951 "aborting\n", vn); 9952 return -EPERM; 9953 } 9954 break; 9955 } 9956 9957 /* check if other port on the path needs ovlan: 9958 * Since MF configuration is shared between ports 9959 * Possible mixed modes are only 9960 * {SF, SI} {SF, SD} {SD, SF} {SI, SF} 9961 */ 9962 if (CHIP_MODE_IS_4_PORT(bp) && 9963 !bp->path_has_ovlan && 9964 !IS_MF(bp) && 9965 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9966 u8 other_port = !BP_PORT(bp); 9967 u8 other_func = BP_PATH(bp) + 2*other_port; 9968 val = MF_CFG_RD(bp, 9969 func_mf_config[other_func].e1hov_tag); 9970 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) 9971 bp->path_has_ovlan = true; 9972 } 9973 } 9974 9975 /* adjust igu_sb_cnt to MF for E1x */ 9976 if (CHIP_IS_E1x(bp) && IS_MF(bp)) 9977 bp->igu_sb_cnt /= E1HVN_MAX; 9978 9979 /* port info */ 9980 bnx2x_get_port_hwinfo(bp); 9981 9982 /* Get MAC addresses */ 9983 bnx2x_get_mac_hwinfo(bp); 9984 9985 bnx2x_get_cnic_info(bp); 9986 9987 return rc; 9988} 9989 9990static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) 9991{ 9992 int cnt, i, block_end, rodi; 9993 char vpd_start[BNX2X_VPD_LEN+1]; 9994 char str_id_reg[VENDOR_ID_LEN+1]; 9995 char str_id_cap[VENDOR_ID_LEN+1]; 9996 char *vpd_data; 9997 char *vpd_extended_data = NULL; 9998 u8 len; 9999 10000 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); 10001 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); 10002 10003 if (cnt < BNX2X_VPD_LEN) 10004 goto out_not_found; 10005 10006 /* VPD RO tag should be first tag after identifier string, hence 10007 * we should be able to find it in first BNX2X_VPD_LEN chars 10008 */ 10009 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, 10010 PCI_VPD_LRDT_RO_DATA); 10011 if (i < 0) 10012 goto out_not_found; 10013 10014 block_end = i + PCI_VPD_LRDT_TAG_SIZE + 10015 pci_vpd_lrdt_size(&vpd_start[i]); 10016 10017 i += PCI_VPD_LRDT_TAG_SIZE; 10018 10019 if (block_end > BNX2X_VPD_LEN) { 10020 vpd_extended_data = kmalloc(block_end, GFP_KERNEL); 10021 if (vpd_extended_data == NULL) 10022 goto out_not_found; 10023 10024 /* read rest of vpd image into vpd_extended_data */ 10025 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); 10026 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, 10027 block_end - BNX2X_VPD_LEN, 10028 vpd_extended_data + BNX2X_VPD_LEN); 10029 if (cnt < (block_end - BNX2X_VPD_LEN)) 10030 goto out_not_found; 10031 vpd_data = vpd_extended_data; 10032 } else 10033 vpd_data = vpd_start; 10034 10035 /* now vpd_data holds full vpd content in both cases */ 10036 10037 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 10038 PCI_VPD_RO_KEYWORD_MFR_ID); 10039 if (rodi < 0) 10040 goto out_not_found; 10041 10042 len = pci_vpd_info_field_size(&vpd_data[rodi]); 10043 10044 if (len != VENDOR_ID_LEN) 10045 goto out_not_found; 10046 10047 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 10048 10049 /* vendor specific info */ 10050 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); 10051 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); 10052 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || 10053 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { 10054 10055 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 10056 PCI_VPD_RO_KEYWORD_VENDOR0); 10057 if (rodi >= 0) { 10058 len = pci_vpd_info_field_size(&vpd_data[rodi]); 10059 10060 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 10061 10062 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { 10063 memcpy(bp->fw_ver, &vpd_data[rodi], len); 10064 bp->fw_ver[len] = ' '; 10065 } 10066 } 10067 kfree(vpd_extended_data); 10068 return; 10069 } 10070out_not_found: 10071 kfree(vpd_extended_data); 10072 return; 10073} 10074 10075static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) 10076{ 10077 u32 flags = 0; 10078 10079 if (CHIP_REV_IS_FPGA(bp)) 10080 SET_FLAGS(flags, MODE_FPGA); 10081 else if (CHIP_REV_IS_EMUL(bp)) 10082 SET_FLAGS(flags, MODE_EMUL); 10083 else 10084 SET_FLAGS(flags, MODE_ASIC); 10085 10086 if (CHIP_MODE_IS_4_PORT(bp)) 10087 SET_FLAGS(flags, MODE_PORT4); 10088 else 10089 SET_FLAGS(flags, MODE_PORT2); 10090 10091 if (CHIP_IS_E2(bp)) 10092 SET_FLAGS(flags, MODE_E2); 10093 else if (CHIP_IS_E3(bp)) { 10094 SET_FLAGS(flags, MODE_E3); 10095 if (CHIP_REV(bp) == CHIP_REV_Ax) 10096 SET_FLAGS(flags, MODE_E3_A0); 10097 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ 10098 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 10099 } 10100 10101 if (IS_MF(bp)) { 10102 SET_FLAGS(flags, MODE_MF); 10103 switch (bp->mf_mode) { 10104 case MULTI_FUNCTION_SD: 10105 SET_FLAGS(flags, MODE_MF_SD); 10106 break; 10107 case MULTI_FUNCTION_SI: 10108 SET_FLAGS(flags, MODE_MF_SI); 10109 break; 10110 } 10111 } else 10112 SET_FLAGS(flags, MODE_SF); 10113 10114#if defined(__LITTLE_ENDIAN) 10115 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 10116#else /*(__BIG_ENDIAN)*/ 10117 SET_FLAGS(flags, MODE_BIG_ENDIAN); 10118#endif 10119 INIT_MODE_FLAGS(bp) = flags; 10120} 10121 10122static int __devinit bnx2x_init_bp(struct bnx2x *bp) 10123{ 10124 int func; 10125 int rc; 10126 10127 mutex_init(&bp->port.phy_mutex); 10128 mutex_init(&bp->fw_mb_mutex); 10129 spin_lock_init(&bp->stats_lock); 10130#ifdef BCM_CNIC 10131 mutex_init(&bp->cnic_mutex); 10132#endif 10133 10134 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); 10135 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); 10136 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); 10137 rc = bnx2x_get_hwinfo(bp); 10138 if (rc) 10139 return rc; 10140 10141 bnx2x_set_modes_bitmap(bp); 10142 10143 rc = bnx2x_alloc_mem_bp(bp); 10144 if (rc) 10145 return rc; 10146 10147 bnx2x_read_fwinfo(bp); 10148 10149 func = BP_FUNC(bp); 10150 10151 /* need to reset chip if undi was active */ 10152 if (!BP_NOMCP(bp)) 10153 bnx2x_undi_unload(bp); 10154 10155 if (CHIP_REV_IS_FPGA(bp)) 10156 dev_err(&bp->pdev->dev, "FPGA detected\n"); 10157 10158 if (BP_NOMCP(bp) && (func == 0)) 10159 dev_err(&bp->pdev->dev, "MCP disabled, " 10160 "must load devices in order!\n"); 10161 10162 bp->multi_mode = multi_mode; 10163 10164 bp->disable_tpa = disable_tpa; 10165 10166#ifdef BCM_CNIC 10167 bp->disable_tpa |= IS_MF_ISCSI_SD(bp); 10168#endif 10169 10170 /* Set TPA flags */ 10171 if (bp->disable_tpa) { 10172 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); 10173 bp->dev->features &= ~NETIF_F_LRO; 10174 } else { 10175 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); 10176 bp->dev->features |= NETIF_F_LRO; 10177 } 10178 10179 if (CHIP_IS_E1(bp)) 10180 bp->dropless_fc = 0; 10181 else 10182 bp->dropless_fc = dropless_fc; 10183 10184 bp->mrrs = mrrs; 10185 10186 bp->tx_ring_size = MAX_TX_AVAIL; 10187 10188 /* make sure that the numbers are in the right granularity */ 10189 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; 10190 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; 10191 10192 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; 10193 10194 init_timer(&bp->timer); 10195 bp->timer.expires = jiffies + bp->current_interval; 10196 bp->timer.data = (unsigned long) bp; 10197 bp->timer.function = bnx2x_timer; 10198 10199 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); 10200 bnx2x_dcbx_init_params(bp); 10201 10202#ifdef BCM_CNIC 10203 if (CHIP_IS_E1x(bp)) 10204 bp->cnic_base_cl_id = FP_SB_MAX_E1x; 10205 else 10206 bp->cnic_base_cl_id = FP_SB_MAX_E2; 10207#endif 10208 10209 /* multiple tx priority */ 10210 if (CHIP_IS_E1x(bp)) 10211 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; 10212 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) 10213 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; 10214 if (CHIP_IS_E3B0(bp)) 10215 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; 10216 10217 bp->gro_check = bnx2x_need_gro_check(bp->dev->mtu); 10218 10219 return rc; 10220} 10221 10222 10223/**************************************************************************** 10224* General service functions 10225****************************************************************************/ 10226 10227/* 10228 * net_device service functions 10229 */ 10230 10231/* called with rtnl_lock */ 10232static int bnx2x_open(struct net_device *dev) 10233{ 10234 struct bnx2x *bp = netdev_priv(dev); 10235 bool global = false; 10236 int other_engine = BP_PATH(bp) ? 0 : 1; 10237 bool other_load_status, load_status; 10238 10239 bp->stats_init = true; 10240 10241 netif_carrier_off(dev); 10242 10243 bnx2x_set_power_state(bp, PCI_D0); 10244 10245 other_load_status = bnx2x_get_load_status(bp, other_engine); 10246 load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); 10247 10248 /* 10249 * If parity had happen during the unload, then attentions 10250 * and/or RECOVERY_IN_PROGRES may still be set. In this case we 10251 * want the first function loaded on the current engine to 10252 * complete the recovery. 10253 */ 10254 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 10255 bnx2x_chk_parity_attn(bp, &global, true)) 10256 do { 10257 /* 10258 * If there are attentions and they are in a global 10259 * blocks, set the GLOBAL_RESET bit regardless whether 10260 * it will be this function that will complete the 10261 * recovery or not. 10262 */ 10263 if (global) 10264 bnx2x_set_reset_global(bp); 10265 10266 /* 10267 * Only the first function on the current engine should 10268 * try to recover in open. In case of attentions in 10269 * global blocks only the first in the chip should try 10270 * to recover. 10271 */ 10272 if ((!load_status && 10273 (!global || !other_load_status)) && 10274 bnx2x_trylock_leader_lock(bp) && 10275 !bnx2x_leader_reset(bp)) { 10276 netdev_info(bp->dev, "Recovered in open\n"); 10277 break; 10278 } 10279 10280 /* recovery has failed... */ 10281 bnx2x_set_power_state(bp, PCI_D3hot); 10282 bp->recovery_state = BNX2X_RECOVERY_FAILED; 10283 10284 netdev_err(bp->dev, "Recovery flow hasn't been properly" 10285 " completed yet. Try again later. If u still see this" 10286 " message after a few retries then power cycle is" 10287 " required.\n"); 10288 10289 return -EAGAIN; 10290 } while (0); 10291 10292 bp->recovery_state = BNX2X_RECOVERY_DONE; 10293 return bnx2x_nic_load(bp, LOAD_OPEN); 10294} 10295 10296/* called with rtnl_lock */ 10297static int bnx2x_close(struct net_device *dev) 10298{ 10299 struct bnx2x *bp = netdev_priv(dev); 10300 10301 /* Unload the driver, release IRQs */ 10302 bnx2x_nic_unload(bp, UNLOAD_CLOSE); 10303 10304 /* Power off */ 10305 bnx2x_set_power_state(bp, PCI_D3hot); 10306 10307 return 0; 10308} 10309 10310static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp, 10311 struct bnx2x_mcast_ramrod_params *p) 10312{ 10313 int mc_count = netdev_mc_count(bp->dev); 10314 struct bnx2x_mcast_list_elem *mc_mac = 10315 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); 10316 struct netdev_hw_addr *ha; 10317 10318 if (!mc_mac) 10319 return -ENOMEM; 10320 10321 INIT_LIST_HEAD(&p->mcast_list); 10322 10323 netdev_for_each_mc_addr(ha, bp->dev) { 10324 mc_mac->mac = bnx2x_mc_addr(ha); 10325 list_add_tail(&mc_mac->link, &p->mcast_list); 10326 mc_mac++; 10327 } 10328 10329 p->mcast_list_len = mc_count; 10330 10331 return 0; 10332} 10333 10334static inline void bnx2x_free_mcast_macs_list( 10335 struct bnx2x_mcast_ramrod_params *p) 10336{ 10337 struct bnx2x_mcast_list_elem *mc_mac = 10338 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, 10339 link); 10340 10341 WARN_ON(!mc_mac); 10342 kfree(mc_mac); 10343} 10344 10345/** 10346 * bnx2x_set_uc_list - configure a new unicast MACs list. 10347 * 10348 * @bp: driver handle 10349 * 10350 * We will use zero (0) as a MAC type for these MACs. 10351 */ 10352static inline int bnx2x_set_uc_list(struct bnx2x *bp) 10353{ 10354 int rc; 10355 struct net_device *dev = bp->dev; 10356 struct netdev_hw_addr *ha; 10357 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj; 10358 unsigned long ramrod_flags = 0; 10359 10360 /* First schedule a cleanup up of old configuration */ 10361 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); 10362 if (rc < 0) { 10363 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); 10364 return rc; 10365 } 10366 10367 netdev_for_each_uc_addr(ha, dev) { 10368 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, 10369 BNX2X_UC_LIST_MAC, &ramrod_flags); 10370 if (rc < 0) { 10371 BNX2X_ERR("Failed to schedule ADD operations: %d\n", 10372 rc); 10373 return rc; 10374 } 10375 } 10376 10377 /* Execute the pending commands */ 10378 __set_bit(RAMROD_CONT, &ramrod_flags); 10379 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, 10380 BNX2X_UC_LIST_MAC, &ramrod_flags); 10381} 10382 10383static inline int bnx2x_set_mc_list(struct bnx2x *bp) 10384{ 10385 struct net_device *dev = bp->dev; 10386 struct bnx2x_mcast_ramrod_params rparam = {0}; 10387 int rc = 0; 10388 10389 rparam.mcast_obj = &bp->mcast_obj; 10390 10391 /* first, clear all configured multicast MACs */ 10392 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 10393 if (rc < 0) { 10394 BNX2X_ERR("Failed to clear multicast " 10395 "configuration: %d\n", rc); 10396 return rc; 10397 } 10398 10399 /* then, configure a new MACs list */ 10400 if (netdev_mc_count(dev)) { 10401 rc = bnx2x_init_mcast_macs_list(bp, &rparam); 10402 if (rc) { 10403 BNX2X_ERR("Failed to create multicast MACs " 10404 "list: %d\n", rc); 10405 return rc; 10406 } 10407 10408 /* Now add the new MACs */ 10409 rc = bnx2x_config_mcast(bp, &rparam, 10410 BNX2X_MCAST_CMD_ADD); 10411 if (rc < 0) 10412 BNX2X_ERR("Failed to set a new multicast " 10413 "configuration: %d\n", rc); 10414 10415 bnx2x_free_mcast_macs_list(&rparam); 10416 } 10417 10418 return rc; 10419} 10420 10421 10422/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ 10423void bnx2x_set_rx_mode(struct net_device *dev) 10424{ 10425 struct bnx2x *bp = netdev_priv(dev); 10426 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 10427 10428 if (bp->state != BNX2X_STATE_OPEN) { 10429 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 10430 return; 10431 } 10432 10433 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); 10434 10435 if (dev->flags & IFF_PROMISC) 10436 rx_mode = BNX2X_RX_MODE_PROMISC; 10437 else if ((dev->flags & IFF_ALLMULTI) || 10438 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && 10439 CHIP_IS_E1(bp))) 10440 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10441 else { 10442 /* some multicasts */ 10443 if (bnx2x_set_mc_list(bp) < 0) 10444 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10445 10446 if (bnx2x_set_uc_list(bp) < 0) 10447 rx_mode = BNX2X_RX_MODE_PROMISC; 10448 } 10449 10450 bp->rx_mode = rx_mode; 10451#ifdef BCM_CNIC 10452 /* handle ISCSI SD mode */ 10453 if (IS_MF_ISCSI_SD(bp)) 10454 bp->rx_mode = BNX2X_RX_MODE_NONE; 10455#endif 10456 10457 /* Schedule the rx_mode command */ 10458 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { 10459 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 10460 return; 10461 } 10462 10463 bnx2x_set_storm_rx_mode(bp); 10464} 10465 10466/* called with rtnl_lock */ 10467static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 10468 int devad, u16 addr) 10469{ 10470 struct bnx2x *bp = netdev_priv(netdev); 10471 u16 value; 10472 int rc; 10473 10474 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 10475 prtad, devad, addr); 10476 10477 /* The HW expects different devad if CL22 is used */ 10478 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10479 10480 bnx2x_acquire_phy_lock(bp); 10481 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); 10482 bnx2x_release_phy_lock(bp); 10483 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 10484 10485 if (!rc) 10486 rc = value; 10487 return rc; 10488} 10489 10490/* called with rtnl_lock */ 10491static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, 10492 u16 addr, u16 value) 10493{ 10494 struct bnx2x *bp = netdev_priv(netdev); 10495 int rc; 10496 10497 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x," 10498 " value 0x%x\n", prtad, devad, addr, value); 10499 10500 /* The HW expects different devad if CL22 is used */ 10501 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10502 10503 bnx2x_acquire_phy_lock(bp); 10504 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); 10505 bnx2x_release_phy_lock(bp); 10506 return rc; 10507} 10508 10509/* called with rtnl_lock */ 10510static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 10511{ 10512 struct bnx2x *bp = netdev_priv(dev); 10513 struct mii_ioctl_data *mdio = if_mii(ifr); 10514 10515 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", 10516 mdio->phy_id, mdio->reg_num, mdio->val_in); 10517 10518 if (!netif_running(dev)) 10519 return -EAGAIN; 10520 10521 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); 10522} 10523 10524#ifdef CONFIG_NET_POLL_CONTROLLER 10525static void poll_bnx2x(struct net_device *dev) 10526{ 10527 struct bnx2x *bp = netdev_priv(dev); 10528 10529 disable_irq(bp->pdev->irq); 10530 bnx2x_interrupt(bp->pdev->irq, dev); 10531 enable_irq(bp->pdev->irq); 10532} 10533#endif 10534 10535static int bnx2x_validate_addr(struct net_device *dev) 10536{ 10537 struct bnx2x *bp = netdev_priv(dev); 10538 10539 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) 10540 return -EADDRNOTAVAIL; 10541 return 0; 10542} 10543 10544static const struct net_device_ops bnx2x_netdev_ops = { 10545 .ndo_open = bnx2x_open, 10546 .ndo_stop = bnx2x_close, 10547 .ndo_start_xmit = bnx2x_start_xmit, 10548 .ndo_select_queue = bnx2x_select_queue, 10549 .ndo_set_rx_mode = bnx2x_set_rx_mode, 10550 .ndo_set_mac_address = bnx2x_change_mac_addr, 10551 .ndo_validate_addr = bnx2x_validate_addr, 10552 .ndo_do_ioctl = bnx2x_ioctl, 10553 .ndo_change_mtu = bnx2x_change_mtu, 10554 .ndo_fix_features = bnx2x_fix_features, 10555 .ndo_set_features = bnx2x_set_features, 10556 .ndo_tx_timeout = bnx2x_tx_timeout, 10557#ifdef CONFIG_NET_POLL_CONTROLLER 10558 .ndo_poll_controller = poll_bnx2x, 10559#endif 10560 .ndo_setup_tc = bnx2x_setup_tc, 10561 10562#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) 10563 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, 10564#endif 10565}; 10566 10567static inline int bnx2x_set_coherency_mask(struct bnx2x *bp) 10568{ 10569 struct device *dev = &bp->pdev->dev; 10570 10571 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 10572 bp->flags |= USING_DAC_FLAG; 10573 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 10574 dev_err(dev, "dma_set_coherent_mask failed, " 10575 "aborting\n"); 10576 return -EIO; 10577 } 10578 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 10579 dev_err(dev, "System does not support DMA, aborting\n"); 10580 return -EIO; 10581 } 10582 10583 return 0; 10584} 10585 10586static int __devinit bnx2x_init_dev(struct pci_dev *pdev, 10587 struct net_device *dev, 10588 unsigned long board_type) 10589{ 10590 struct bnx2x *bp; 10591 int rc; 10592 u32 pci_cfg_dword; 10593 bool chip_is_e1x = (board_type == BCM57710 || 10594 board_type == BCM57711 || 10595 board_type == BCM57711E); 10596 10597 SET_NETDEV_DEV(dev, &pdev->dev); 10598 bp = netdev_priv(dev); 10599 10600 bp->dev = dev; 10601 bp->pdev = pdev; 10602 bp->flags = 0; 10603 10604 rc = pci_enable_device(pdev); 10605 if (rc) { 10606 dev_err(&bp->pdev->dev, 10607 "Cannot enable PCI device, aborting\n"); 10608 goto err_out; 10609 } 10610 10611 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 10612 dev_err(&bp->pdev->dev, 10613 "Cannot find PCI device base address, aborting\n"); 10614 rc = -ENODEV; 10615 goto err_out_disable; 10616 } 10617 10618 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 10619 dev_err(&bp->pdev->dev, "Cannot find second PCI device" 10620 " base address, aborting\n"); 10621 rc = -ENODEV; 10622 goto err_out_disable; 10623 } 10624 10625 if (atomic_read(&pdev->enable_cnt) == 1) { 10626 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 10627 if (rc) { 10628 dev_err(&bp->pdev->dev, 10629 "Cannot obtain PCI resources, aborting\n"); 10630 goto err_out_disable; 10631 } 10632 10633 pci_set_master(pdev); 10634 pci_save_state(pdev); 10635 } 10636 10637 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 10638 if (bp->pm_cap == 0) { 10639 dev_err(&bp->pdev->dev, 10640 "Cannot find power management capability, aborting\n"); 10641 rc = -EIO; 10642 goto err_out_release; 10643 } 10644 10645 if (!pci_is_pcie(pdev)) { 10646 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 10647 rc = -EIO; 10648 goto err_out_release; 10649 } 10650 10651 rc = bnx2x_set_coherency_mask(bp); 10652 if (rc) 10653 goto err_out_release; 10654 10655 dev->mem_start = pci_resource_start(pdev, 0); 10656 dev->base_addr = dev->mem_start; 10657 dev->mem_end = pci_resource_end(pdev, 0); 10658 10659 dev->irq = pdev->irq; 10660 10661 bp->regview = pci_ioremap_bar(pdev, 0); 10662 if (!bp->regview) { 10663 dev_err(&bp->pdev->dev, 10664 "Cannot map register space, aborting\n"); 10665 rc = -ENOMEM; 10666 goto err_out_release; 10667 } 10668 10669 /* In E1/E1H use pci device function given by kernel. 10670 * In E2/E3 read physical function from ME register since these chips 10671 * support Physical Device Assignment where kernel BDF maybe arbitrary 10672 * (depending on hypervisor). 10673 */ 10674 if (chip_is_e1x) 10675 bp->pf_num = PCI_FUNC(pdev->devfn); 10676 else {/* chip is E2/3*/ 10677 pci_read_config_dword(bp->pdev, 10678 PCICFG_ME_REGISTER, &pci_cfg_dword); 10679 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> 10680 ME_REG_ABS_PF_NUM_SHIFT); 10681 } 10682 DP(BNX2X_MSG_SP, "me reg PF num: %d\n", bp->pf_num); 10683 10684 bnx2x_set_power_state(bp, PCI_D0); 10685 10686 /* clean indirect addresses */ 10687 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 10688 PCICFG_VENDOR_ID_OFFSET); 10689 /* 10690 * Clean the following indirect addresses for all functions since it 10691 * is not used by the driver. 10692 */ 10693 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); 10694 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); 10695 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 10696 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 10697 10698 if (chip_is_e1x) { 10699 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 10700 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 10701 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 10702 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); 10703 } 10704 10705 /* 10706 * Enable internal target-read (in case we are probed after PF FLR). 10707 * Must be done prior to any BAR read access. Only for 57712 and up 10708 */ 10709 if (!chip_is_e1x) 10710 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 10711 10712 /* Reset the load counter */ 10713 bnx2x_clear_load_status(bp); 10714 10715 dev->watchdog_timeo = TX_TIMEOUT; 10716 10717 dev->netdev_ops = &bnx2x_netdev_ops; 10718 bnx2x_set_ethtool_ops(dev); 10719 10720 dev->priv_flags |= IFF_UNICAST_FLT; 10721 10722 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10723 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | 10724 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | 10725 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; 10726 10727 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10728 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 10729 10730 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; 10731 if (bp->flags & USING_DAC_FLAG) 10732 dev->features |= NETIF_F_HIGHDMA; 10733 10734 /* Add Loopback capability to the device */ 10735 dev->hw_features |= NETIF_F_LOOPBACK; 10736 10737#ifdef BCM_DCBNL 10738 dev->dcbnl_ops = &bnx2x_dcbnl_ops; 10739#endif 10740 10741 /* get_port_hwinfo() will set prtad and mmds properly */ 10742 bp->mdio.prtad = MDIO_PRTAD_NONE; 10743 bp->mdio.mmds = 0; 10744 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10745 bp->mdio.dev = dev; 10746 bp->mdio.mdio_read = bnx2x_mdio_read; 10747 bp->mdio.mdio_write = bnx2x_mdio_write; 10748 10749 return 0; 10750 10751err_out_release: 10752 if (atomic_read(&pdev->enable_cnt) == 1) 10753 pci_release_regions(pdev); 10754 10755err_out_disable: 10756 pci_disable_device(pdev); 10757 pci_set_drvdata(pdev, NULL); 10758 10759err_out: 10760 return rc; 10761} 10762 10763static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, 10764 int *width, int *speed) 10765{ 10766 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); 10767 10768 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; 10769 10770 /* return value of 1=2.5GHz 2=5GHz */ 10771 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; 10772} 10773 10774static int bnx2x_check_firmware(struct bnx2x *bp) 10775{ 10776 const struct firmware *firmware = bp->firmware; 10777 struct bnx2x_fw_file_hdr *fw_hdr; 10778 struct bnx2x_fw_file_section *sections; 10779 u32 offset, len, num_ops; 10780 u16 *ops_offsets; 10781 int i; 10782 const u8 *fw_ver; 10783 10784 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) 10785 return -EINVAL; 10786 10787 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 10788 sections = (struct bnx2x_fw_file_section *)fw_hdr; 10789 10790 /* Make sure none of the offsets and sizes make us read beyond 10791 * the end of the firmware data */ 10792 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { 10793 offset = be32_to_cpu(sections[i].offset); 10794 len = be32_to_cpu(sections[i].len); 10795 if (offset + len > firmware->size) { 10796 dev_err(&bp->pdev->dev, 10797 "Section %d length is out of bounds\n", i); 10798 return -EINVAL; 10799 } 10800 } 10801 10802 /* Likewise for the init_ops offsets */ 10803 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); 10804 ops_offsets = (u16 *)(firmware->data + offset); 10805 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); 10806 10807 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 10808 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 10809 dev_err(&bp->pdev->dev, 10810 "Section offset %d is out of bounds\n", i); 10811 return -EINVAL; 10812 } 10813 } 10814 10815 /* Check FW version */ 10816 offset = be32_to_cpu(fw_hdr->fw_version.offset); 10817 fw_ver = firmware->data + offset; 10818 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || 10819 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || 10820 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || 10821 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { 10822 dev_err(&bp->pdev->dev, 10823 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 10824 fw_ver[0], fw_ver[1], fw_ver[2], 10825 fw_ver[3], BCM_5710_FW_MAJOR_VERSION, 10826 BCM_5710_FW_MINOR_VERSION, 10827 BCM_5710_FW_REVISION_VERSION, 10828 BCM_5710_FW_ENGINEERING_VERSION); 10829 return -EINVAL; 10830 } 10831 10832 return 0; 10833} 10834 10835static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10836{ 10837 const __be32 *source = (const __be32 *)_source; 10838 u32 *target = (u32 *)_target; 10839 u32 i; 10840 10841 for (i = 0; i < n/4; i++) 10842 target[i] = be32_to_cpu(source[i]); 10843} 10844 10845/* 10846 Ops array is stored in the following format: 10847 {op(8bit), offset(24bit, big endian), data(32bit, big endian)} 10848 */ 10849static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) 10850{ 10851 const __be32 *source = (const __be32 *)_source; 10852 struct raw_op *target = (struct raw_op *)_target; 10853 u32 i, j, tmp; 10854 10855 for (i = 0, j = 0; i < n/8; i++, j += 2) { 10856 tmp = be32_to_cpu(source[j]); 10857 target[i].op = (tmp >> 24) & 0xff; 10858 target[i].offset = tmp & 0xffffff; 10859 target[i].raw_data = be32_to_cpu(source[j + 1]); 10860 } 10861} 10862 10863/** 10864 * IRO array is stored in the following format: 10865 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } 10866 */ 10867static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) 10868{ 10869 const __be32 *source = (const __be32 *)_source; 10870 struct iro *target = (struct iro *)_target; 10871 u32 i, j, tmp; 10872 10873 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { 10874 target[i].base = be32_to_cpu(source[j]); 10875 j++; 10876 tmp = be32_to_cpu(source[j]); 10877 target[i].m1 = (tmp >> 16) & 0xffff; 10878 target[i].m2 = tmp & 0xffff; 10879 j++; 10880 tmp = be32_to_cpu(source[j]); 10881 target[i].m3 = (tmp >> 16) & 0xffff; 10882 target[i].size = tmp & 0xffff; 10883 j++; 10884 } 10885} 10886 10887static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10888{ 10889 const __be16 *source = (const __be16 *)_source; 10890 u16 *target = (u16 *)_target; 10891 u32 i; 10892 10893 for (i = 0; i < n/2; i++) 10894 target[i] = be16_to_cpu(source[i]); 10895} 10896 10897#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ 10898do { \ 10899 u32 len = be32_to_cpu(fw_hdr->arr.len); \ 10900 bp->arr = kmalloc(len, GFP_KERNEL); \ 10901 if (!bp->arr) \ 10902 goto lbl; \ 10903 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ 10904 (u8 *)bp->arr, len); \ 10905} while (0) 10906 10907int bnx2x_init_firmware(struct bnx2x *bp) 10908{ 10909 struct bnx2x_fw_file_hdr *fw_hdr; 10910 int rc; 10911 10912 10913 if (!bp->firmware) { 10914 const char *fw_file_name; 10915 10916 if (CHIP_IS_E1(bp)) 10917 fw_file_name = FW_FILE_NAME_E1; 10918 else if (CHIP_IS_E1H(bp)) 10919 fw_file_name = FW_FILE_NAME_E1H; 10920 else if (!CHIP_IS_E1x(bp)) 10921 fw_file_name = FW_FILE_NAME_E2; 10922 else { 10923 BNX2X_ERR("Unsupported chip revision\n"); 10924 return -EINVAL; 10925 } 10926 BNX2X_DEV_INFO("Loading %s\n", fw_file_name); 10927 10928 rc = request_firmware(&bp->firmware, fw_file_name, 10929 &bp->pdev->dev); 10930 if (rc) { 10931 BNX2X_ERR("Can't load firmware file %s\n", 10932 fw_file_name); 10933 goto request_firmware_exit; 10934 } 10935 10936 rc = bnx2x_check_firmware(bp); 10937 if (rc) { 10938 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); 10939 goto request_firmware_exit; 10940 } 10941 } 10942 10943 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; 10944 10945 /* Initialize the pointers to the init arrays */ 10946 /* Blob */ 10947 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); 10948 10949 /* Opcodes */ 10950 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); 10951 10952 /* Offsets */ 10953 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, 10954 be16_to_cpu_n); 10955 10956 /* STORMs firmware */ 10957 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10958 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); 10959 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + 10960 be32_to_cpu(fw_hdr->tsem_pram_data.offset); 10961 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10962 be32_to_cpu(fw_hdr->usem_int_table_data.offset); 10963 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + 10964 be32_to_cpu(fw_hdr->usem_pram_data.offset); 10965 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10966 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); 10967 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + 10968 be32_to_cpu(fw_hdr->xsem_pram_data.offset); 10969 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10970 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 10971 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 10972 be32_to_cpu(fw_hdr->csem_pram_data.offset); 10973 /* IRO */ 10974 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); 10975 10976 return 0; 10977 10978iro_alloc_err: 10979 kfree(bp->init_ops_offsets); 10980init_offsets_alloc_err: 10981 kfree(bp->init_ops); 10982init_ops_alloc_err: 10983 kfree(bp->init_data); 10984request_firmware_exit: 10985 release_firmware(bp->firmware); 10986 10987 return rc; 10988} 10989 10990static void bnx2x_release_firmware(struct bnx2x *bp) 10991{ 10992 kfree(bp->init_ops_offsets); 10993 kfree(bp->init_ops); 10994 kfree(bp->init_data); 10995 release_firmware(bp->firmware); 10996 bp->firmware = NULL; 10997} 10998 10999 11000static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { 11001 .init_hw_cmn_chip = bnx2x_init_hw_common_chip, 11002 .init_hw_cmn = bnx2x_init_hw_common, 11003 .init_hw_port = bnx2x_init_hw_port, 11004 .init_hw_func = bnx2x_init_hw_func, 11005 11006 .reset_hw_cmn = bnx2x_reset_common, 11007 .reset_hw_port = bnx2x_reset_port, 11008 .reset_hw_func = bnx2x_reset_func, 11009 11010 .gunzip_init = bnx2x_gunzip_init, 11011 .gunzip_end = bnx2x_gunzip_end, 11012 11013 .init_fw = bnx2x_init_firmware, 11014 .release_fw = bnx2x_release_firmware, 11015}; 11016 11017void bnx2x__init_func_obj(struct bnx2x *bp) 11018{ 11019 /* Prepare DMAE related driver resources */ 11020 bnx2x_setup_dmae(bp); 11021 11022 bnx2x_init_func_obj(bp, &bp->func_obj, 11023 bnx2x_sp(bp, func_rdata), 11024 bnx2x_sp_mapping(bp, func_rdata), 11025 &bnx2x_func_sp_drv); 11026} 11027 11028/* must be called after sriov-enable */ 11029static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp) 11030{ 11031 int cid_count = BNX2X_L2_CID_COUNT(bp); 11032 11033#ifdef BCM_CNIC 11034 cid_count += CNIC_CID_MAX; 11035#endif 11036 return roundup(cid_count, QM_CID_ROUND); 11037} 11038 11039/** 11040 * bnx2x_get_num_none_def_sbs - return the number of none default SBs 11041 * 11042 * @dev: pci device 11043 * 11044 */ 11045static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) 11046{ 11047 int pos; 11048 u16 control; 11049 11050 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 11051 11052 /* 11053 * If MSI-X is not supported - return number of SBs needed to support 11054 * one fast path queue: one FP queue + SB for CNIC 11055 */ 11056 if (!pos) 11057 return 1 + CNIC_PRESENT; 11058 11059 /* 11060 * The value in the PCI configuration space is the index of the last 11061 * entry, namely one less than the actual size of the table, which is 11062 * exactly what we want to return from this function: number of all SBs 11063 * without the default SB. 11064 */ 11065 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 11066 return control & PCI_MSIX_FLAGS_QSIZE; 11067} 11068 11069static int __devinit bnx2x_init_one(struct pci_dev *pdev, 11070 const struct pci_device_id *ent) 11071{ 11072 struct net_device *dev = NULL; 11073 struct bnx2x *bp; 11074 int pcie_width, pcie_speed; 11075 int rc, max_non_def_sbs; 11076 int rx_count, tx_count, rss_count; 11077 /* 11078 * An estimated maximum supported CoS number according to the chip 11079 * version. 11080 * We will try to roughly estimate the maximum number of CoSes this chip 11081 * may support in order to minimize the memory allocated for Tx 11082 * netdev_queue's. This number will be accurately calculated during the 11083 * initialization of bp->max_cos based on the chip versions AND chip 11084 * revision in the bnx2x_init_bp(). 11085 */ 11086 u8 max_cos_est = 0; 11087 11088 switch (ent->driver_data) { 11089 case BCM57710: 11090 case BCM57711: 11091 case BCM57711E: 11092 max_cos_est = BNX2X_MULTI_TX_COS_E1X; 11093 break; 11094 11095 case BCM57712: 11096 case BCM57712_MF: 11097 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; 11098 break; 11099 11100 case BCM57800: 11101 case BCM57800_MF: 11102 case BCM57810: 11103 case BCM57810_MF: 11104 case BCM57840: 11105 case BCM57840_MF: 11106 max_cos_est = BNX2X_MULTI_TX_COS_E3B0; 11107 break; 11108 11109 default: 11110 pr_err("Unknown board_type (%ld), aborting\n", 11111 ent->driver_data); 11112 return -ENODEV; 11113 } 11114 11115 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); 11116 11117 /* !!! FIXME !!! 11118 * Do not allow the maximum SB count to grow above 16 11119 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48. 11120 * We will use the FP_SB_MAX_E1x macro for this matter. 11121 */ 11122 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs); 11123 11124 WARN_ON(!max_non_def_sbs); 11125 11126 /* Maximum number of RSS queues: one IGU SB goes to CNIC */ 11127 rss_count = max_non_def_sbs - CNIC_PRESENT; 11128 11129 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ 11130 rx_count = rss_count + FCOE_PRESENT; 11131 11132 /* 11133 * Maximum number of netdev Tx queues: 11134 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 11135 */ 11136 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT; 11137 11138 /* dev zeroed in init_etherdev */ 11139 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); 11140 if (!dev) 11141 return -ENOMEM; 11142 11143 bp = netdev_priv(dev); 11144 11145 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n", 11146 tx_count, rx_count); 11147 11148 bp->igu_sb_cnt = max_non_def_sbs; 11149 bp->msg_enable = debug; 11150 pci_set_drvdata(pdev, dev); 11151 11152 rc = bnx2x_init_dev(pdev, dev, ent->driver_data); 11153 if (rc < 0) { 11154 free_netdev(dev); 11155 return rc; 11156 } 11157 11158 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs); 11159 11160 rc = bnx2x_init_bp(bp); 11161 if (rc) 11162 goto init_one_exit; 11163 11164 /* 11165 * Map doorbels here as we need the real value of bp->max_cos which 11166 * is initialized in bnx2x_init_bp(). 11167 */ 11168 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), 11169 min_t(u64, BNX2X_DB_SIZE(bp), 11170 pci_resource_len(pdev, 2))); 11171 if (!bp->doorbells) { 11172 dev_err(&bp->pdev->dev, 11173 "Cannot map doorbell space, aborting\n"); 11174 rc = -ENOMEM; 11175 goto init_one_exit; 11176 } 11177 11178 /* calc qm_cid_count */ 11179 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); 11180 11181#ifdef BCM_CNIC 11182 /* disable FCOE L2 queue for E1x */ 11183 if (CHIP_IS_E1x(bp)) 11184 bp->flags |= NO_FCOE_FLAG; 11185 11186#endif 11187 11188 /* Configure interrupt mode: try to enable MSI-X/MSI if 11189 * needed, set bp->num_queues appropriately. 11190 */ 11191 bnx2x_set_int_mode(bp); 11192 11193 /* Add all NAPI objects */ 11194 bnx2x_add_all_napi(bp); 11195 11196 rc = register_netdev(dev); 11197 if (rc) { 11198 dev_err(&pdev->dev, "Cannot register net device\n"); 11199 goto init_one_exit; 11200 } 11201 11202#ifdef BCM_CNIC 11203 if (!NO_FCOE(bp)) { 11204 /* Add storage MAC address */ 11205 rtnl_lock(); 11206 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11207 rtnl_unlock(); 11208 } 11209#endif 11210 11211 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); 11212 11213 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", 11214 board_info[ent->driver_data].name, 11215 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 11216 pcie_width, 11217 ((!CHIP_IS_E2(bp) && pcie_speed == 2) || 11218 (CHIP_IS_E2(bp) && pcie_speed == 1)) ? 11219 "5GHz (Gen2)" : "2.5GHz", 11220 dev->base_addr, bp->pdev->irq, dev->dev_addr); 11221 11222 return 0; 11223 11224init_one_exit: 11225 if (bp->regview) 11226 iounmap(bp->regview); 11227 11228 if (bp->doorbells) 11229 iounmap(bp->doorbells); 11230 11231 free_netdev(dev); 11232 11233 if (atomic_read(&pdev->enable_cnt) == 1) 11234 pci_release_regions(pdev); 11235 11236 pci_disable_device(pdev); 11237 pci_set_drvdata(pdev, NULL); 11238 11239 return rc; 11240} 11241 11242static void __devexit bnx2x_remove_one(struct pci_dev *pdev) 11243{ 11244 struct net_device *dev = pci_get_drvdata(pdev); 11245 struct bnx2x *bp; 11246 11247 if (!dev) { 11248 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); 11249 return; 11250 } 11251 bp = netdev_priv(dev); 11252 11253#ifdef BCM_CNIC 11254 /* Delete storage MAC address */ 11255 if (!NO_FCOE(bp)) { 11256 rtnl_lock(); 11257 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11258 rtnl_unlock(); 11259 } 11260#endif 11261 11262#ifdef BCM_DCBNL 11263 /* Delete app tlvs from dcbnl */ 11264 bnx2x_dcbnl_update_applist(bp, true); 11265#endif 11266 11267 unregister_netdev(dev); 11268 11269 /* Delete all NAPI objects */ 11270 bnx2x_del_all_napi(bp); 11271 11272 /* Power on: we can't let PCI layer write to us while we are in D3 */ 11273 bnx2x_set_power_state(bp, PCI_D0); 11274 11275 /* Disable MSI/MSI-X */ 11276 bnx2x_disable_msi(bp); 11277 11278 /* Power off */ 11279 bnx2x_set_power_state(bp, PCI_D3hot); 11280 11281 /* Make sure RESET task is not scheduled before continuing */ 11282 cancel_delayed_work_sync(&bp->sp_rtnl_task); 11283 11284 if (bp->regview) 11285 iounmap(bp->regview); 11286 11287 if (bp->doorbells) 11288 iounmap(bp->doorbells); 11289 11290 bnx2x_release_firmware(bp); 11291 11292 bnx2x_free_mem_bp(bp); 11293 11294 free_netdev(dev); 11295 11296 if (atomic_read(&pdev->enable_cnt) == 1) 11297 pci_release_regions(pdev); 11298 11299 pci_disable_device(pdev); 11300 pci_set_drvdata(pdev, NULL); 11301} 11302 11303static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 11304{ 11305 int i; 11306 11307 bp->state = BNX2X_STATE_ERROR; 11308 11309 bp->rx_mode = BNX2X_RX_MODE_NONE; 11310 11311#ifdef BCM_CNIC 11312 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); 11313#endif 11314 /* Stop Tx */ 11315 bnx2x_tx_disable(bp); 11316 11317 bnx2x_netif_stop(bp, 0); 11318 11319 del_timer_sync(&bp->timer); 11320 11321 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 11322 11323 /* Release IRQs */ 11324 bnx2x_free_irq(bp); 11325 11326 /* Free SKBs, SGEs, TPA pool and driver internals */ 11327 bnx2x_free_skbs(bp); 11328 11329 for_each_rx_queue(bp, i) 11330 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 11331 11332 bnx2x_free_mem(bp); 11333 11334 bp->state = BNX2X_STATE_CLOSED; 11335 11336 netif_carrier_off(bp->dev); 11337 11338 return 0; 11339} 11340 11341static void bnx2x_eeh_recover(struct bnx2x *bp) 11342{ 11343 u32 val; 11344 11345 mutex_init(&bp->port.phy_mutex); 11346 11347 11348 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 11349 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11350 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11351 BNX2X_ERR("BAD MCP validity signature\n"); 11352} 11353 11354/** 11355 * bnx2x_io_error_detected - called when PCI error is detected 11356 * @pdev: Pointer to PCI device 11357 * @state: The current pci connection state 11358 * 11359 * This function is called after a PCI bus error affecting 11360 * this device has been detected. 11361 */ 11362static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, 11363 pci_channel_state_t state) 11364{ 11365 struct net_device *dev = pci_get_drvdata(pdev); 11366 struct bnx2x *bp = netdev_priv(dev); 11367 11368 rtnl_lock(); 11369 11370 netif_device_detach(dev); 11371 11372 if (state == pci_channel_io_perm_failure) { 11373 rtnl_unlock(); 11374 return PCI_ERS_RESULT_DISCONNECT; 11375 } 11376 11377 if (netif_running(dev)) 11378 bnx2x_eeh_nic_unload(bp); 11379 11380 pci_disable_device(pdev); 11381 11382 rtnl_unlock(); 11383 11384 /* Request a slot reset */ 11385 return PCI_ERS_RESULT_NEED_RESET; 11386} 11387 11388/** 11389 * bnx2x_io_slot_reset - called after the PCI bus has been reset 11390 * @pdev: Pointer to PCI device 11391 * 11392 * Restart the card from scratch, as if from a cold-boot. 11393 */ 11394static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) 11395{ 11396 struct net_device *dev = pci_get_drvdata(pdev); 11397 struct bnx2x *bp = netdev_priv(dev); 11398 11399 rtnl_lock(); 11400 11401 if (pci_enable_device(pdev)) { 11402 dev_err(&pdev->dev, 11403 "Cannot re-enable PCI device after reset\n"); 11404 rtnl_unlock(); 11405 return PCI_ERS_RESULT_DISCONNECT; 11406 } 11407 11408 pci_set_master(pdev); 11409 pci_restore_state(pdev); 11410 11411 if (netif_running(dev)) 11412 bnx2x_set_power_state(bp, PCI_D0); 11413 11414 rtnl_unlock(); 11415 11416 return PCI_ERS_RESULT_RECOVERED; 11417} 11418 11419/** 11420 * bnx2x_io_resume - called when traffic can start flowing again 11421 * @pdev: Pointer to PCI device 11422 * 11423 * This callback is called when the error recovery driver tells us that 11424 * its OK to resume normal operation. 11425 */ 11426static void bnx2x_io_resume(struct pci_dev *pdev) 11427{ 11428 struct net_device *dev = pci_get_drvdata(pdev); 11429 struct bnx2x *bp = netdev_priv(dev); 11430 11431 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 11432 netdev_err(bp->dev, "Handling parity error recovery. " 11433 "Try again later\n"); 11434 return; 11435 } 11436 11437 rtnl_lock(); 11438 11439 bnx2x_eeh_recover(bp); 11440 11441 if (netif_running(dev)) 11442 bnx2x_nic_load(bp, LOAD_NORMAL); 11443 11444 netif_device_attach(dev); 11445 11446 rtnl_unlock(); 11447} 11448 11449static struct pci_error_handlers bnx2x_err_handler = { 11450 .error_detected = bnx2x_io_error_detected, 11451 .slot_reset = bnx2x_io_slot_reset, 11452 .resume = bnx2x_io_resume, 11453}; 11454 11455static struct pci_driver bnx2x_pci_driver = { 11456 .name = DRV_MODULE_NAME, 11457 .id_table = bnx2x_pci_tbl, 11458 .probe = bnx2x_init_one, 11459 .remove = __devexit_p(bnx2x_remove_one), 11460 .suspend = bnx2x_suspend, 11461 .resume = bnx2x_resume, 11462 .err_handler = &bnx2x_err_handler, 11463}; 11464 11465static int __init bnx2x_init(void) 11466{ 11467 int ret; 11468 11469 pr_info("%s", version); 11470 11471 bnx2x_wq = create_singlethread_workqueue("bnx2x"); 11472 if (bnx2x_wq == NULL) { 11473 pr_err("Cannot create workqueue\n"); 11474 return -ENOMEM; 11475 } 11476 11477 ret = pci_register_driver(&bnx2x_pci_driver); 11478 if (ret) { 11479 pr_err("Cannot register driver\n"); 11480 destroy_workqueue(bnx2x_wq); 11481 } 11482 return ret; 11483} 11484 11485static void __exit bnx2x_cleanup(void) 11486{ 11487 pci_unregister_driver(&bnx2x_pci_driver); 11488 11489 destroy_workqueue(bnx2x_wq); 11490} 11491 11492void bnx2x_notify_link_changed(struct bnx2x *bp) 11493{ 11494 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); 11495} 11496 11497module_init(bnx2x_init); 11498module_exit(bnx2x_cleanup); 11499 11500#ifdef BCM_CNIC 11501/** 11502 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). 11503 * 11504 * @bp: driver handle 11505 * @set: set or clear the CAM entry 11506 * 11507 * This function will wait until the ramdord completion returns. 11508 * Return 0 if success, -ENODEV if ramrod doesn't return. 11509 */ 11510static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) 11511{ 11512 unsigned long ramrod_flags = 0; 11513 11514 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 11515 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, 11516 &bp->iscsi_l2_mac_obj, true, 11517 BNX2X_ISCSI_ETH_MAC, &ramrod_flags); 11518} 11519 11520/* count denotes the number of new completions we have seen */ 11521static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) 11522{ 11523 struct eth_spe *spe; 11524 11525#ifdef BNX2X_STOP_ON_ERROR 11526 if (unlikely(bp->panic)) 11527 return; 11528#endif 11529 11530 spin_lock_bh(&bp->spq_lock); 11531 BUG_ON(bp->cnic_spq_pending < count); 11532 bp->cnic_spq_pending -= count; 11533 11534 11535 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { 11536 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) 11537 & SPE_HDR_CONN_TYPE) >> 11538 SPE_HDR_CONN_TYPE_SHIFT; 11539 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) 11540 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; 11541 11542 /* Set validation for iSCSI L2 client before sending SETUP 11543 * ramrod 11544 */ 11545 if (type == ETH_CONNECTION_TYPE) { 11546 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) 11547 bnx2x_set_ctx_validation(bp, &bp->context. 11548 vcxt[BNX2X_ISCSI_ETH_CID].eth, 11549 BNX2X_ISCSI_ETH_CID); 11550 } 11551 11552 /* 11553 * There may be not more than 8 L2, not more than 8 L5 SPEs 11554 * and in the air. We also check that number of outstanding 11555 * COMMON ramrods is not more than the EQ and SPQ can 11556 * accommodate. 11557 */ 11558 if (type == ETH_CONNECTION_TYPE) { 11559 if (!atomic_read(&bp->cq_spq_left)) 11560 break; 11561 else 11562 atomic_dec(&bp->cq_spq_left); 11563 } else if (type == NONE_CONNECTION_TYPE) { 11564 if (!atomic_read(&bp->eq_spq_left)) 11565 break; 11566 else 11567 atomic_dec(&bp->eq_spq_left); 11568 } else if ((type == ISCSI_CONNECTION_TYPE) || 11569 (type == FCOE_CONNECTION_TYPE)) { 11570 if (bp->cnic_spq_pending >= 11571 bp->cnic_eth_dev.max_kwqe_pending) 11572 break; 11573 else 11574 bp->cnic_spq_pending++; 11575 } else { 11576 BNX2X_ERR("Unknown SPE type: %d\n", type); 11577 bnx2x_panic(); 11578 break; 11579 } 11580 11581 spe = bnx2x_sp_get_next(bp); 11582 *spe = *bp->cnic_kwq_cons; 11583 11584 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n", 11585 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 11586 11587 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 11588 bp->cnic_kwq_cons = bp->cnic_kwq; 11589 else 11590 bp->cnic_kwq_cons++; 11591 } 11592 bnx2x_sp_prod_update(bp); 11593 spin_unlock_bh(&bp->spq_lock); 11594} 11595 11596static int bnx2x_cnic_sp_queue(struct net_device *dev, 11597 struct kwqe_16 *kwqes[], u32 count) 11598{ 11599 struct bnx2x *bp = netdev_priv(dev); 11600 int i; 11601 11602#ifdef BNX2X_STOP_ON_ERROR 11603 if (unlikely(bp->panic)) 11604 return -EIO; 11605#endif 11606 11607 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && 11608 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 11609 netdev_err(dev, "Handling parity error recovery. Try again " 11610 "later\n"); 11611 return -EAGAIN; 11612 } 11613 11614 spin_lock_bh(&bp->spq_lock); 11615 11616 for (i = 0; i < count; i++) { 11617 struct eth_spe *spe = (struct eth_spe *)kwqes[i]; 11618 11619 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) 11620 break; 11621 11622 *bp->cnic_kwq_prod = *spe; 11623 11624 bp->cnic_kwq_pending++; 11625 11626 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n", 11627 spe->hdr.conn_and_cmd_data, spe->hdr.type, 11628 spe->data.update_data_addr.hi, 11629 spe->data.update_data_addr.lo, 11630 bp->cnic_kwq_pending); 11631 11632 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 11633 bp->cnic_kwq_prod = bp->cnic_kwq; 11634 else 11635 bp->cnic_kwq_prod++; 11636 } 11637 11638 spin_unlock_bh(&bp->spq_lock); 11639 11640 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) 11641 bnx2x_cnic_sp_post(bp, 0); 11642 11643 return i; 11644} 11645 11646static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11647{ 11648 struct cnic_ops *c_ops; 11649 int rc = 0; 11650 11651 mutex_lock(&bp->cnic_mutex); 11652 c_ops = rcu_dereference_protected(bp->cnic_ops, 11653 lockdep_is_held(&bp->cnic_mutex)); 11654 if (c_ops) 11655 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11656 mutex_unlock(&bp->cnic_mutex); 11657 11658 return rc; 11659} 11660 11661static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11662{ 11663 struct cnic_ops *c_ops; 11664 int rc = 0; 11665 11666 rcu_read_lock(); 11667 c_ops = rcu_dereference(bp->cnic_ops); 11668 if (c_ops) 11669 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11670 rcu_read_unlock(); 11671 11672 return rc; 11673} 11674 11675/* 11676 * for commands that have no data 11677 */ 11678int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) 11679{ 11680 struct cnic_ctl_info ctl = {0}; 11681 11682 ctl.cmd = cmd; 11683 11684 return bnx2x_cnic_ctl_send(bp, &ctl); 11685} 11686 11687static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) 11688{ 11689 struct cnic_ctl_info ctl = {0}; 11690 11691 /* first we tell CNIC and only then we count this as a completion */ 11692 ctl.cmd = CNIC_CTL_COMPLETION_CMD; 11693 ctl.data.comp.cid = cid; 11694 ctl.data.comp.error = err; 11695 11696 bnx2x_cnic_ctl_send_bh(bp, &ctl); 11697 bnx2x_cnic_sp_post(bp, 0); 11698} 11699 11700 11701/* Called with netif_addr_lock_bh() taken. 11702 * Sets an rx_mode config for an iSCSI ETH client. 11703 * Doesn't block. 11704 * Completion should be checked outside. 11705 */ 11706static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) 11707{ 11708 unsigned long accept_flags = 0, ramrod_flags = 0; 11709 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11710 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; 11711 11712 if (start) { 11713 /* Start accepting on iSCSI L2 ring. Accept all multicasts 11714 * because it's the only way for UIO Queue to accept 11715 * multicasts (in non-promiscuous mode only one Queue per 11716 * function will receive multicast packets (leading in our 11717 * case). 11718 */ 11719 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); 11720 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); 11721 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); 11722 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 11723 11724 /* Clear STOP_PENDING bit if START is requested */ 11725 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); 11726 11727 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; 11728 } else 11729 /* Clear START_PENDING bit if STOP is requested */ 11730 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); 11731 11732 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 11733 set_bit(sched_state, &bp->sp_state); 11734 else { 11735 __set_bit(RAMROD_RX, &ramrod_flags); 11736 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, 11737 ramrod_flags); 11738 } 11739} 11740 11741 11742static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 11743{ 11744 struct bnx2x *bp = netdev_priv(dev); 11745 int rc = 0; 11746 11747 switch (ctl->cmd) { 11748 case DRV_CTL_CTXTBL_WR_CMD: { 11749 u32 index = ctl->data.io.offset; 11750 dma_addr_t addr = ctl->data.io.dma_addr; 11751 11752 bnx2x_ilt_wr(bp, index, addr); 11753 break; 11754 } 11755 11756 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { 11757 int count = ctl->data.credit.credit_count; 11758 11759 bnx2x_cnic_sp_post(bp, count); 11760 break; 11761 } 11762 11763 /* rtnl_lock is held. */ 11764 case DRV_CTL_START_L2_CMD: { 11765 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11766 unsigned long sp_bits = 0; 11767 11768 /* Configure the iSCSI classification object */ 11769 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, 11770 cp->iscsi_l2_client_id, 11771 cp->iscsi_l2_cid, BP_FUNC(bp), 11772 bnx2x_sp(bp, mac_rdata), 11773 bnx2x_sp_mapping(bp, mac_rdata), 11774 BNX2X_FILTER_MAC_PENDING, 11775 &bp->sp_state, BNX2X_OBJ_TYPE_RX, 11776 &bp->macs_pool); 11777 11778 /* Set iSCSI MAC address */ 11779 rc = bnx2x_set_iscsi_eth_mac_addr(bp); 11780 if (rc) 11781 break; 11782 11783 mmiowb(); 11784 barrier(); 11785 11786 /* Start accepting on iSCSI L2 ring */ 11787 11788 netif_addr_lock_bh(dev); 11789 bnx2x_set_iscsi_eth_rx_mode(bp, true); 11790 netif_addr_unlock_bh(dev); 11791 11792 /* bits to wait on */ 11793 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11794 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); 11795 11796 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11797 BNX2X_ERR("rx_mode completion timed out!\n"); 11798 11799 break; 11800 } 11801 11802 /* rtnl_lock is held. */ 11803 case DRV_CTL_STOP_L2_CMD: { 11804 unsigned long sp_bits = 0; 11805 11806 /* Stop accepting on iSCSI L2 ring */ 11807 netif_addr_lock_bh(dev); 11808 bnx2x_set_iscsi_eth_rx_mode(bp, false); 11809 netif_addr_unlock_bh(dev); 11810 11811 /* bits to wait on */ 11812 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11813 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); 11814 11815 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11816 BNX2X_ERR("rx_mode completion timed out!\n"); 11817 11818 mmiowb(); 11819 barrier(); 11820 11821 /* Unset iSCSI L2 MAC */ 11822 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, 11823 BNX2X_ISCSI_ETH_MAC, true); 11824 break; 11825 } 11826 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { 11827 int count = ctl->data.credit.credit_count; 11828 11829 smp_mb__before_atomic_inc(); 11830 atomic_add(count, &bp->cq_spq_left); 11831 smp_mb__after_atomic_inc(); 11832 break; 11833 } 11834 case DRV_CTL_ULP_REGISTER_CMD: { 11835 int ulp_type = ctl->data.ulp_type; 11836 11837 if (CHIP_IS_E3(bp)) { 11838 int idx = BP_FW_MB_IDX(bp); 11839 u32 cap; 11840 11841 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 11842 if (ulp_type == CNIC_ULP_ISCSI) 11843 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 11844 else if (ulp_type == CNIC_ULP_FCOE) 11845 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 11846 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 11847 } 11848 break; 11849 } 11850 case DRV_CTL_ULP_UNREGISTER_CMD: { 11851 int ulp_type = ctl->data.ulp_type; 11852 11853 if (CHIP_IS_E3(bp)) { 11854 int idx = BP_FW_MB_IDX(bp); 11855 u32 cap; 11856 11857 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 11858 if (ulp_type == CNIC_ULP_ISCSI) 11859 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 11860 else if (ulp_type == CNIC_ULP_FCOE) 11861 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 11862 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 11863 } 11864 break; 11865 } 11866 11867 default: 11868 BNX2X_ERR("unknown command %x\n", ctl->cmd); 11869 rc = -EINVAL; 11870 } 11871 11872 return rc; 11873} 11874 11875void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) 11876{ 11877 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11878 11879 if (bp->flags & USING_MSIX_FLAG) { 11880 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 11881 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 11882 cp->irq_arr[0].vector = bp->msix_table[1].vector; 11883 } else { 11884 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 11885 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 11886 } 11887 if (!CHIP_IS_E1x(bp)) 11888 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; 11889 else 11890 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; 11891 11892 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); 11893 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); 11894 cp->irq_arr[1].status_blk = bp->def_status_blk; 11895 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 11896 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; 11897 11898 cp->num_irq = 2; 11899} 11900 11901static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, 11902 void *data) 11903{ 11904 struct bnx2x *bp = netdev_priv(dev); 11905 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11906 11907 if (ops == NULL) 11908 return -EINVAL; 11909 11910 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 11911 if (!bp->cnic_kwq) 11912 return -ENOMEM; 11913 11914 bp->cnic_kwq_cons = bp->cnic_kwq; 11915 bp->cnic_kwq_prod = bp->cnic_kwq; 11916 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; 11917 11918 bp->cnic_spq_pending = 0; 11919 bp->cnic_kwq_pending = 0; 11920 11921 bp->cnic_data = data; 11922 11923 cp->num_irq = 0; 11924 cp->drv_state |= CNIC_DRV_STATE_REGD; 11925 cp->iro_arr = bp->iro_arr; 11926 11927 bnx2x_setup_cnic_irq_info(bp); 11928 11929 rcu_assign_pointer(bp->cnic_ops, ops); 11930 11931 return 0; 11932} 11933 11934static int bnx2x_unregister_cnic(struct net_device *dev) 11935{ 11936 struct bnx2x *bp = netdev_priv(dev); 11937 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11938 11939 mutex_lock(&bp->cnic_mutex); 11940 cp->drv_state = 0; 11941 RCU_INIT_POINTER(bp->cnic_ops, NULL); 11942 mutex_unlock(&bp->cnic_mutex); 11943 synchronize_rcu(); 11944 kfree(bp->cnic_kwq); 11945 bp->cnic_kwq = NULL; 11946 11947 return 0; 11948} 11949 11950struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) 11951{ 11952 struct bnx2x *bp = netdev_priv(dev); 11953 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11954 11955 /* If both iSCSI and FCoE are disabled - return NULL in 11956 * order to indicate CNIC that it should not try to work 11957 * with this device. 11958 */ 11959 if (NO_ISCSI(bp) && NO_FCOE(bp)) 11960 return NULL; 11961 11962 cp->drv_owner = THIS_MODULE; 11963 cp->chip_id = CHIP_ID(bp); 11964 cp->pdev = bp->pdev; 11965 cp->io_base = bp->regview; 11966 cp->io_base2 = bp->doorbells; 11967 cp->max_kwqe_pending = 8; 11968 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; 11969 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 11970 bnx2x_cid_ilt_lines(bp); 11971 cp->ctx_tbl_len = CNIC_ILT_LINES; 11972 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 11973 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 11974 cp->drv_ctl = bnx2x_drv_ctl; 11975 cp->drv_register_cnic = bnx2x_register_cnic; 11976 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 11977 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID; 11978 cp->iscsi_l2_client_id = 11979 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11980 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID; 11981 11982 if (NO_ISCSI_OOO(bp)) 11983 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 11984 11985 if (NO_ISCSI(bp)) 11986 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; 11987 11988 if (NO_FCOE(bp)) 11989 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 11990 11991 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, " 11992 "starting cid %d\n", 11993 cp->ctx_blk_size, 11994 cp->ctx_tbl_offset, 11995 cp->ctx_tbl_len, 11996 cp->starting_cid); 11997 return cp; 11998} 11999EXPORT_SYMBOL(bnx2x_cnic_probe); 12000 12001#endif /* BCM_CNIC */ 12002 12003