bnx2x_reg.h revision 27d9129f5ae830cc031a898e0c220e1cdda69b34
1/* bnx2x_reg.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * The registers description starts with the register Access type followed 10 * by size in bits. For example [RW 32]. The access types are: 11 * R - Read only 12 * RC - Clear on read 13 * RW - Read/Write 14 * ST - Statistics register (clear on read) 15 * W - Write only 16 * WB - Wide bus register - the size is over 32 bits and it should be 17 * read/write in consecutive 32 bits accesses 18 * WR - Write Clear (write 1 to clear the bit) 19 * 20 */ 21#ifndef BNX2X_REG_H 22#define BNX2X_REG_H 23 24#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 25#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2) 26#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5) 27#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3) 28#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4) 29#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1) 30/* [RW 1] Initiate the ATC array - reset all the valid bits */ 31#define ATC_REG_ATC_INIT_ARRAY 0x1100b8 32/* [R 1] ATC initalization done */ 33#define ATC_REG_ATC_INIT_DONE 0x1100bc 34/* [RC 6] Interrupt register #0 read clear */ 35#define ATC_REG_ATC_INT_STS_CLR 0x1101c0 36/* [RW 5] Parity mask register #0 read/write */ 37#define ATC_REG_ATC_PRTY_MASK 0x1101d8 38/* [RC 5] Parity register #0 read clear */ 39#define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0 40/* [RW 19] Interrupt mask register #0 read/write */ 41#define BRB1_REG_BRB1_INT_MASK 0x60128 42/* [R 19] Interrupt register #0 read */ 43#define BRB1_REG_BRB1_INT_STS 0x6011c 44/* [RW 4] Parity mask register #0 read/write */ 45#define BRB1_REG_BRB1_PRTY_MASK 0x60138 46/* [R 4] Parity register #0 read */ 47#define BRB1_REG_BRB1_PRTY_STS 0x6012c 48/* [RC 4] Parity register #0 read clear */ 49#define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130 50/* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At 51 * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address 52 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning - 53 * following reset the first rbc access to this reg must be write; there can 54 * be no more rbc writes after the first one; there can be any number of rbc 55 * read following the first write; rbc access not following these rules will 56 * result in hang condition. */ 57#define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200 58/* [RW 10] The number of free blocks below which the full signal to class 0 59 * is asserted */ 60#define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0 61#define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230 62/* [RW 11] The number of free blocks above which the full signal to class 0 63 * is de-asserted */ 64#define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4 65#define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234 66/* [RW 11] The number of free blocks below which the full signal to class 1 67 * is asserted */ 68#define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8 69#define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238 70/* [RW 11] The number of free blocks above which the full signal to class 1 71 * is de-asserted */ 72#define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc 73#define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c 74/* [RW 11] The number of free blocks below which the full signal to the LB 75 * port is asserted */ 76#define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0 77/* [RW 10] The number of free blocks above which the full signal to the LB 78 * port is de-asserted */ 79#define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4 80/* [RW 10] The number of free blocks above which the High_llfc signal to 81 interface #n is de-asserted. */ 82#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c 83/* [RW 10] The number of free blocks below which the High_llfc signal to 84 interface #n is asserted. */ 85#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c 86/* [RW 11] The number of blocks guarantied for the LB port */ 87#define BRB1_REG_LB_GUARANTIED 0x601ec 88/* [RW 11] The hysteresis on the guarantied buffer space for the Lb port 89 * before signaling XON. */ 90#define BRB1_REG_LB_GUARANTIED_HYST 0x60264 91/* [RW 24] LL RAM data. */ 92#define BRB1_REG_LL_RAM 0x61000 93/* [RW 10] The number of free blocks above which the Low_llfc signal to 94 interface #n is de-asserted. */ 95#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c 96/* [RW 10] The number of free blocks below which the Low_llfc signal to 97 interface #n is asserted. */ 98#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c 99/* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The 100 * register is applicable only when per_class_guaranty_mode is set. */ 101#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244 102/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC 103 * 1 before signaling XON. The register is applicable only when 104 * per_class_guaranty_mode is set. */ 105#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254 106/* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The 107 * register is applicable only when per_class_guaranty_mode is set. */ 108#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248 109/* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0 110 * before signaling XON. The register is applicable only when 111 * per_class_guaranty_mode is set. */ 112#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258 113/* [RW 11] The number of blocks guarantied for class 0in MAC1.The register 114 * is applicable only when per_class_guaranty_mode is set. */ 115#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c 116/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC 117 * 1 before signaling XON. The register is applicable only when 118 * per_class_guaranty_mode is set. */ 119#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c 120/* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The 121 * register is applicable only when per_class_guaranty_mode is set. */ 122#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250 123/* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC 124 * 1 before signaling XON. The register is applicable only when 125 * per_class_guaranty_mode is set. */ 126#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260 127/* [RW 11] The number of blocks guarantied for the MAC port. The register is 128 * applicable only when per_class_guaranty_mode is reset. */ 129#define BRB1_REG_MAC_GUARANTIED_0 0x601e8 130#define BRB1_REG_MAC_GUARANTIED_1 0x60240 131/* [R 24] The number of full blocks. */ 132#define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090 133/* [ST 32] The number of cycles that the write_full signal towards MAC #0 134 was asserted. */ 135#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8 136#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc 137#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8 138/* [ST 32] The number of cycles that the pause signal towards MAC #0 was 139 asserted. */ 140#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8 141#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc 142/* [RW 10] The number of free blocks below which the pause signal to class 0 143 * is asserted */ 144#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0 145#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220 146/* [RW 11] The number of free blocks above which the pause signal to class 0 147 * is de-asserted */ 148#define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4 149#define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224 150/* [RW 11] The number of free blocks below which the pause signal to class 1 151 * is asserted */ 152#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8 153#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228 154/* [RW 11] The number of free blocks above which the pause signal to class 1 155 * is de-asserted */ 156#define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc 157#define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c 158/* [RW 10] Write client 0: De-assert pause threshold. Not Functional */ 159#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078 160#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c 161/* [RW 10] Write client 0: Assert pause threshold. */ 162#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068 163/* [RW 1] Indicates if to use per-class guaranty mode (new mode) or per-MAC 164 * guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC 165 * mode). 1=per-class guaranty mode (new mode). */ 166#define BRB1_REG_PER_CLASS_GUARANTY_MODE 0x60268 167/* [R 24] The number of full blocks occpied by port. */ 168#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094 169/* [RW 1] Reset the design by software. */ 170#define BRB1_REG_SOFT_RESET 0x600dc 171/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */ 172#define CCM_REG_CAM_OCCUP 0xd0188 173/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 174 acknowledge output is deasserted; all other signals are treated as usual; 175 if 1 - normal activity. */ 176#define CCM_REG_CCM_CFC_IFEN 0xd003c 177/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 178 disregarded; valid is deasserted; all other signals are treated as usual; 179 if 1 - normal activity. */ 180#define CCM_REG_CCM_CQM_IFEN 0xd000c 181/* [RW 1] If set the Q index; received from the QM is inserted to event ID. 182 Otherwise 0 is inserted. */ 183#define CCM_REG_CCM_CQM_USE_Q 0xd00c0 184/* [RW 11] Interrupt mask register #0 read/write */ 185#define CCM_REG_CCM_INT_MASK 0xd01e4 186/* [R 11] Interrupt register #0 read */ 187#define CCM_REG_CCM_INT_STS 0xd01d8 188/* [RW 27] Parity mask register #0 read/write */ 189#define CCM_REG_CCM_PRTY_MASK 0xd01f4 190/* [R 27] Parity register #0 read */ 191#define CCM_REG_CCM_PRTY_STS 0xd01e8 192/* [RC 27] Parity register #0 read clear */ 193#define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec 194/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS 195 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 196 Is used to determine the number of the AG context REG-pairs written back; 197 when the input message Reg1WbFlg isn't set. */ 198#define CCM_REG_CCM_REG0_SZ 0xd00c4 199/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 200 disregarded; valid is deasserted; all other signals are treated as usual; 201 if 1 - normal activity. */ 202#define CCM_REG_CCM_STORM0_IFEN 0xd0004 203/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 204 disregarded; valid is deasserted; all other signals are treated as usual; 205 if 1 - normal activity. */ 206#define CCM_REG_CCM_STORM1_IFEN 0xd0008 207/* [RW 1] CDU AG read Interface enable. If 0 - the request input is 208 disregarded; valid output is deasserted; all other signals are treated as 209 usual; if 1 - normal activity. */ 210#define CCM_REG_CDU_AG_RD_IFEN 0xd0030 211/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 212 are disregarded; all other signals are treated as usual; if 1 - normal 213 activity. */ 214#define CCM_REG_CDU_AG_WR_IFEN 0xd002c 215/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 216 disregarded; valid output is deasserted; all other signals are treated as 217 usual; if 1 - normal activity. */ 218#define CCM_REG_CDU_SM_RD_IFEN 0xd0038 219/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 220 input is disregarded; all other signals are treated as usual; if 1 - 221 normal activity. */ 222#define CCM_REG_CDU_SM_WR_IFEN 0xd0034 223/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 224 the initial credit value; read returns the current value of the credit 225 counter. Must be initialized to 1 at start-up. */ 226#define CCM_REG_CFC_INIT_CRD 0xd0204 227/* [RW 2] Auxiliary counter flag Q number 1. */ 228#define CCM_REG_CNT_AUX1_Q 0xd00c8 229/* [RW 2] Auxiliary counter flag Q number 2. */ 230#define CCM_REG_CNT_AUX2_Q 0xd00cc 231/* [RW 28] The CM header value for QM request (primary). */ 232#define CCM_REG_CQM_CCM_HDR_P 0xd008c 233/* [RW 28] The CM header value for QM request (secondary). */ 234#define CCM_REG_CQM_CCM_HDR_S 0xd0090 235/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 236 acknowledge output is deasserted; all other signals are treated as usual; 237 if 1 - normal activity. */ 238#define CCM_REG_CQM_CCM_IFEN 0xd0014 239/* [RW 6] QM output initial credit. Max credit available - 32. Write writes 240 the initial credit value; read returns the current value of the credit 241 counter. Must be initialized to 32 at start-up. */ 242#define CCM_REG_CQM_INIT_CRD 0xd020c 243/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 244 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 245 prioritised); 2 stands for weight 2; tc. */ 246#define CCM_REG_CQM_P_WEIGHT 0xd00b8 247/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 248 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 249 prioritised); 2 stands for weight 2; tc. */ 250#define CCM_REG_CQM_S_WEIGHT 0xd00bc 251/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 252 acknowledge output is deasserted; all other signals are treated as usual; 253 if 1 - normal activity. */ 254#define CCM_REG_CSDM_IFEN 0xd0018 255/* [RC 1] Set when the message length mismatch (relative to last indication) 256 at the SDM interface is detected. */ 257#define CCM_REG_CSDM_LENGTH_MIS 0xd0170 258/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 259 weight 8 (the most prioritised); 1 stands for weight 1(least 260 prioritised); 2 stands for weight 2; tc. */ 261#define CCM_REG_CSDM_WEIGHT 0xd00b4 262/* [RW 28] The CM header for QM formatting in case of an error in the QM 263 inputs. */ 264#define CCM_REG_ERR_CCM_HDR 0xd0094 265/* [RW 8] The Event ID in case the input message ErrorFlg is set. */ 266#define CCM_REG_ERR_EVNT_ID 0xd0098 267/* [RW 8] FIC0 output initial credit. Max credit available - 255. Write 268 writes the initial credit value; read returns the current value of the 269 credit counter. Must be initialized to 64 at start-up. */ 270#define CCM_REG_FIC0_INIT_CRD 0xd0210 271/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 272 writes the initial credit value; read returns the current value of the 273 credit counter. Must be initialized to 64 at start-up. */ 274#define CCM_REG_FIC1_INIT_CRD 0xd0214 275/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 276 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr; 277 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and 278 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and 279 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */ 280#define CCM_REG_GR_ARB_TYPE 0xd015c 281/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 282 highest priority is 3. It is supposed; that the Store channel priority is 283 the compliment to 4 of the rest priorities - Aggregation channel; Load 284 (FIC0) channel and Load (FIC1). */ 285#define CCM_REG_GR_LD0_PR 0xd0164 286/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 287 highest priority is 3. It is supposed; that the Store channel priority is 288 the compliment to 4 of the rest priorities - Aggregation channel; Load 289 (FIC0) channel and Load (FIC1). */ 290#define CCM_REG_GR_LD1_PR 0xd0168 291/* [RW 2] General flags index. */ 292#define CCM_REG_INV_DONE_Q 0xd0108 293/* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM 294 context and sent to STORM; for a specific connection type. The double 295 REG-pairs are used in order to align to STORM context row size of 128 296 bits. The offset of these data in the STORM context is always 0. Index 297 _(0..15) stands for the connection type (one of 16). */ 298#define CCM_REG_N_SM_CTX_LD_0 0xd004c 299#define CCM_REG_N_SM_CTX_LD_1 0xd0050 300#define CCM_REG_N_SM_CTX_LD_2 0xd0054 301#define CCM_REG_N_SM_CTX_LD_3 0xd0058 302#define CCM_REG_N_SM_CTX_LD_4 0xd005c 303/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 304 acknowledge output is deasserted; all other signals are treated as usual; 305 if 1 - normal activity. */ 306#define CCM_REG_PBF_IFEN 0xd0028 307/* [RC 1] Set when the message length mismatch (relative to last indication) 308 at the pbf interface is detected. */ 309#define CCM_REG_PBF_LENGTH_MIS 0xd0180 310/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 311 weight 8 (the most prioritised); 1 stands for weight 1(least 312 prioritised); 2 stands for weight 2; tc. */ 313#define CCM_REG_PBF_WEIGHT 0xd00ac 314#define CCM_REG_PHYS_QNUM1_0 0xd0134 315#define CCM_REG_PHYS_QNUM1_1 0xd0138 316#define CCM_REG_PHYS_QNUM2_0 0xd013c 317#define CCM_REG_PHYS_QNUM2_1 0xd0140 318#define CCM_REG_PHYS_QNUM3_0 0xd0144 319#define CCM_REG_PHYS_QNUM3_1 0xd0148 320#define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114 321#define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118 322#define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c 323#define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120 324#define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124 325#define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128 326#define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c 327#define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130 328/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 329 disregarded; acknowledge output is deasserted; all other signals are 330 treated as usual; if 1 - normal activity. */ 331#define CCM_REG_STORM_CCM_IFEN 0xd0010 332/* [RC 1] Set when the message length mismatch (relative to last indication) 333 at the STORM interface is detected. */ 334#define CCM_REG_STORM_LENGTH_MIS 0xd016c 335/* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin) 336 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for 337 weight 1(least prioritised); 2 stands for weight 2 (more prioritised); 338 tc. */ 339#define CCM_REG_STORM_WEIGHT 0xd009c 340/* [RW 1] Input tsem Interface enable. If 0 - the valid input is 341 disregarded; acknowledge output is deasserted; all other signals are 342 treated as usual; if 1 - normal activity. */ 343#define CCM_REG_TSEM_IFEN 0xd001c 344/* [RC 1] Set when the message length mismatch (relative to last indication) 345 at the tsem interface is detected. */ 346#define CCM_REG_TSEM_LENGTH_MIS 0xd0174 347/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 348 weight 8 (the most prioritised); 1 stands for weight 1(least 349 prioritised); 2 stands for weight 2; tc. */ 350#define CCM_REG_TSEM_WEIGHT 0xd00a0 351/* [RW 1] Input usem Interface enable. If 0 - the valid input is 352 disregarded; acknowledge output is deasserted; all other signals are 353 treated as usual; if 1 - normal activity. */ 354#define CCM_REG_USEM_IFEN 0xd0024 355/* [RC 1] Set when message length mismatch (relative to last indication) at 356 the usem interface is detected. */ 357#define CCM_REG_USEM_LENGTH_MIS 0xd017c 358/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 359 weight 8 (the most prioritised); 1 stands for weight 1(least 360 prioritised); 2 stands for weight 2; tc. */ 361#define CCM_REG_USEM_WEIGHT 0xd00a8 362/* [RW 1] Input xsem Interface enable. If 0 - the valid input is 363 disregarded; acknowledge output is deasserted; all other signals are 364 treated as usual; if 1 - normal activity. */ 365#define CCM_REG_XSEM_IFEN 0xd0020 366/* [RC 1] Set when the message length mismatch (relative to last indication) 367 at the xsem interface is detected. */ 368#define CCM_REG_XSEM_LENGTH_MIS 0xd0178 369/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for 370 weight 8 (the most prioritised); 1 stands for weight 1(least 371 prioritised); 2 stands for weight 2; tc. */ 372#define CCM_REG_XSEM_WEIGHT 0xd00a4 373/* [RW 19] Indirect access to the descriptor table of the XX protection 374 mechanism. The fields are: [5:0] - message length; [12:6] - message 375 pointer; 18:13] - next pointer. */ 376#define CCM_REG_XX_DESCR_TABLE 0xd0300 377#define CCM_REG_XX_DESCR_TABLE_SIZE 24 378/* [R 7] Used to read the value of XX protection Free counter. */ 379#define CCM_REG_XX_FREE 0xd0184 380/* [RW 6] Initial value for the credit counter; responsible for fulfilling 381 of the Input Stage XX protection buffer by the XX protection pending 382 messages. Max credit available - 127. Write writes the initial credit 383 value; read returns the current value of the credit counter. Must be 384 initialized to maximum XX protected message size - 2 at start-up. */ 385#define CCM_REG_XX_INIT_CRD 0xd0220 386/* [RW 7] The maximum number of pending messages; which may be stored in XX 387 protection. At read the ~ccm_registers_xx_free.xx_free counter is read. 388 At write comprises the start value of the ~ccm_registers_xx_free.xx_free 389 counter. */ 390#define CCM_REG_XX_MSG_NUM 0xd0224 391/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 392#define CCM_REG_XX_OVFL_EVNT_ID 0xd0044 393/* [RW 18] Indirect access to the XX table of the XX protection mechanism. 394 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] - 395 header pointer. */ 396#define CCM_REG_XX_TABLE 0xd0280 397#define CDU_REG_CDU_CHK_MASK0 0x101000 398#define CDU_REG_CDU_CHK_MASK1 0x101004 399#define CDU_REG_CDU_CONTROL0 0x101008 400#define CDU_REG_CDU_DEBUG 0x101010 401#define CDU_REG_CDU_GLOBAL_PARAMS 0x101020 402/* [RW 7] Interrupt mask register #0 read/write */ 403#define CDU_REG_CDU_INT_MASK 0x10103c 404/* [R 7] Interrupt register #0 read */ 405#define CDU_REG_CDU_INT_STS 0x101030 406/* [RW 5] Parity mask register #0 read/write */ 407#define CDU_REG_CDU_PRTY_MASK 0x10104c 408/* [R 5] Parity register #0 read */ 409#define CDU_REG_CDU_PRTY_STS 0x101040 410/* [RC 5] Parity register #0 read clear */ 411#define CDU_REG_CDU_PRTY_STS_CLR 0x101044 412/* [RC 32] logging of error data in case of a CDU load error: 413 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error; 414 ype_error; ctual_active; ctual_compressed_context}; */ 415#define CDU_REG_ERROR_DATA 0x101014 416/* [WB 216] L1TT ram access. each entry has the following format : 417 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0]; 418 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */ 419#define CDU_REG_L1TT 0x101800 420/* [WB 24] MATT ram access. each entry has the following 421 format:{RegionLength[11:0]; egionOffset[11:0]} */ 422#define CDU_REG_MATT 0x101100 423/* [RW 1] when this bit is set the CDU operates in e1hmf mode */ 424#define CDU_REG_MF_MODE 0x101050 425/* [R 1] indication the initializing the activity counter by the hardware 426 was done. */ 427#define CFC_REG_AC_INIT_DONE 0x104078 428/* [RW 13] activity counter ram access */ 429#define CFC_REG_ACTIVITY_COUNTER 0x104400 430#define CFC_REG_ACTIVITY_COUNTER_SIZE 256 431/* [R 1] indication the initializing the cams by the hardware was done. */ 432#define CFC_REG_CAM_INIT_DONE 0x10407c 433/* [RW 2] Interrupt mask register #0 read/write */ 434#define CFC_REG_CFC_INT_MASK 0x104108 435/* [R 2] Interrupt register #0 read */ 436#define CFC_REG_CFC_INT_STS 0x1040fc 437/* [RC 2] Interrupt register #0 read clear */ 438#define CFC_REG_CFC_INT_STS_CLR 0x104100 439/* [RW 4] Parity mask register #0 read/write */ 440#define CFC_REG_CFC_PRTY_MASK 0x104118 441/* [R 4] Parity register #0 read */ 442#define CFC_REG_CFC_PRTY_STS 0x10410c 443/* [RC 4] Parity register #0 read clear */ 444#define CFC_REG_CFC_PRTY_STS_CLR 0x104110 445/* [RW 21] CID cam access (21:1 - Data; alid - 0) */ 446#define CFC_REG_CID_CAM 0x104800 447#define CFC_REG_CONTROL0 0x104028 448#define CFC_REG_DEBUG0 0x104050 449/* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error 450 vector) whether the cfc should be disabled upon it */ 451#define CFC_REG_DISABLE_ON_ERROR 0x104044 452/* [RC 14] CFC error vector. when the CFC detects an internal error it will 453 set one of these bits. the bit description can be found in CFC 454 specifications */ 455#define CFC_REG_ERROR_VECTOR 0x10403c 456/* [WB 93] LCID info ram access */ 457#define CFC_REG_INFO_RAM 0x105000 458#define CFC_REG_INFO_RAM_SIZE 1024 459#define CFC_REG_INIT_REG 0x10404c 460#define CFC_REG_INTERFACES 0x104058 461/* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this 462 field allows changing the priorities of the weighted-round-robin arbiter 463 which selects which CFC load client should be served next */ 464#define CFC_REG_LCREQ_WEIGHTS 0x104084 465/* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */ 466#define CFC_REG_LINK_LIST 0x104c00 467#define CFC_REG_LINK_LIST_SIZE 256 468/* [R 1] indication the initializing the link list by the hardware was done. */ 469#define CFC_REG_LL_INIT_DONE 0x104074 470/* [R 9] Number of allocated LCIDs which are at empty state */ 471#define CFC_REG_NUM_LCIDS_ALLOC 0x104020 472/* [R 9] Number of Arriving LCIDs in Link List Block */ 473#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004 474#define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120 475/* [R 9] Number of Leaving LCIDs in Link List Block */ 476#define CFC_REG_NUM_LCIDS_LEAVING 0x104018 477#define CFC_REG_WEAK_ENABLE_PF 0x104124 478/* [RW 8] The event id for aggregated interrupt 0 */ 479#define CSDM_REG_AGG_INT_EVENT_0 0xc2038 480#define CSDM_REG_AGG_INT_EVENT_10 0xc2060 481#define CSDM_REG_AGG_INT_EVENT_11 0xc2064 482#define CSDM_REG_AGG_INT_EVENT_12 0xc2068 483#define CSDM_REG_AGG_INT_EVENT_13 0xc206c 484#define CSDM_REG_AGG_INT_EVENT_14 0xc2070 485#define CSDM_REG_AGG_INT_EVENT_15 0xc2074 486#define CSDM_REG_AGG_INT_EVENT_16 0xc2078 487#define CSDM_REG_AGG_INT_EVENT_2 0xc2040 488#define CSDM_REG_AGG_INT_EVENT_3 0xc2044 489#define CSDM_REG_AGG_INT_EVENT_4 0xc2048 490#define CSDM_REG_AGG_INT_EVENT_5 0xc204c 491#define CSDM_REG_AGG_INT_EVENT_6 0xc2050 492#define CSDM_REG_AGG_INT_EVENT_7 0xc2054 493#define CSDM_REG_AGG_INT_EVENT_8 0xc2058 494#define CSDM_REG_AGG_INT_EVENT_9 0xc205c 495/* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 496 or auto-mask-mode (1) */ 497#define CSDM_REG_AGG_INT_MODE_10 0xc21e0 498#define CSDM_REG_AGG_INT_MODE_11 0xc21e4 499#define CSDM_REG_AGG_INT_MODE_12 0xc21e8 500#define CSDM_REG_AGG_INT_MODE_13 0xc21ec 501#define CSDM_REG_AGG_INT_MODE_14 0xc21f0 502#define CSDM_REG_AGG_INT_MODE_15 0xc21f4 503#define CSDM_REG_AGG_INT_MODE_16 0xc21f8 504#define CSDM_REG_AGG_INT_MODE_6 0xc21d0 505#define CSDM_REG_AGG_INT_MODE_7 0xc21d4 506#define CSDM_REG_AGG_INT_MODE_8 0xc21d8 507#define CSDM_REG_AGG_INT_MODE_9 0xc21dc 508/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 509#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008 510/* [RW 16] The maximum value of the completion counter #0 */ 511#define CSDM_REG_CMP_COUNTER_MAX0 0xc201c 512/* [RW 16] The maximum value of the completion counter #1 */ 513#define CSDM_REG_CMP_COUNTER_MAX1 0xc2020 514/* [RW 16] The maximum value of the completion counter #2 */ 515#define CSDM_REG_CMP_COUNTER_MAX2 0xc2024 516/* [RW 16] The maximum value of the completion counter #3 */ 517#define CSDM_REG_CMP_COUNTER_MAX3 0xc2028 518/* [RW 13] The start address in the internal RAM for the completion 519 counters. */ 520#define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c 521/* [RW 32] Interrupt mask register #0 read/write */ 522#define CSDM_REG_CSDM_INT_MASK_0 0xc229c 523#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac 524/* [R 32] Interrupt register #0 read */ 525#define CSDM_REG_CSDM_INT_STS_0 0xc2290 526#define CSDM_REG_CSDM_INT_STS_1 0xc22a0 527/* [RW 11] Parity mask register #0 read/write */ 528#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc 529/* [R 11] Parity register #0 read */ 530#define CSDM_REG_CSDM_PRTY_STS 0xc22b0 531/* [RC 11] Parity register #0 read clear */ 532#define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4 533#define CSDM_REG_ENABLE_IN1 0xc2238 534#define CSDM_REG_ENABLE_IN2 0xc223c 535#define CSDM_REG_ENABLE_OUT1 0xc2240 536#define CSDM_REG_ENABLE_OUT2 0xc2244 537/* [RW 4] The initial number of messages that can be sent to the pxp control 538 interface without receiving any ACK. */ 539#define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc 540/* [ST 32] The number of ACK after placement messages received */ 541#define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c 542/* [ST 32] The number of packet end messages received from the parser */ 543#define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274 544/* [ST 32] The number of requests received from the pxp async if */ 545#define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278 546/* [ST 32] The number of commands received in queue 0 */ 547#define CSDM_REG_NUM_OF_Q0_CMD 0xc2248 548/* [ST 32] The number of commands received in queue 10 */ 549#define CSDM_REG_NUM_OF_Q10_CMD 0xc226c 550/* [ST 32] The number of commands received in queue 11 */ 551#define CSDM_REG_NUM_OF_Q11_CMD 0xc2270 552/* [ST 32] The number of commands received in queue 1 */ 553#define CSDM_REG_NUM_OF_Q1_CMD 0xc224c 554/* [ST 32] The number of commands received in queue 3 */ 555#define CSDM_REG_NUM_OF_Q3_CMD 0xc2250 556/* [ST 32] The number of commands received in queue 4 */ 557#define CSDM_REG_NUM_OF_Q4_CMD 0xc2254 558/* [ST 32] The number of commands received in queue 5 */ 559#define CSDM_REG_NUM_OF_Q5_CMD 0xc2258 560/* [ST 32] The number of commands received in queue 6 */ 561#define CSDM_REG_NUM_OF_Q6_CMD 0xc225c 562/* [ST 32] The number of commands received in queue 7 */ 563#define CSDM_REG_NUM_OF_Q7_CMD 0xc2260 564/* [ST 32] The number of commands received in queue 8 */ 565#define CSDM_REG_NUM_OF_Q8_CMD 0xc2264 566/* [ST 32] The number of commands received in queue 9 */ 567#define CSDM_REG_NUM_OF_Q9_CMD 0xc2268 568/* [RW 13] The start address in the internal RAM for queue counters */ 569#define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010 570/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 571#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548 572/* [R 1] parser fifo empty in sdm_sync block */ 573#define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550 574/* [R 1] parser serial fifo empty in sdm_sync block */ 575#define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558 576/* [RW 32] Tick for timer counter. Applicable only when 577 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */ 578#define CSDM_REG_TIMER_TICK 0xc2000 579/* [RW 5] The number of time_slots in the arbitration cycle */ 580#define CSEM_REG_ARB_CYCLE_SIZE 0x200034 581/* [RW 3] The source that is associated with arbitration element 0. Source 582 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 583 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 584#define CSEM_REG_ARB_ELEMENT0 0x200020 585/* [RW 3] The source that is associated with arbitration element 1. Source 586 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 587 sleeping thread with priority 1; 4- sleeping thread with priority 2. 588 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */ 589#define CSEM_REG_ARB_ELEMENT1 0x200024 590/* [RW 3] The source that is associated with arbitration element 2. Source 591 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 592 sleeping thread with priority 1; 4- sleeping thread with priority 2. 593 Could not be equal to register ~csem_registers_arb_element0.arb_element0 594 and ~csem_registers_arb_element1.arb_element1 */ 595#define CSEM_REG_ARB_ELEMENT2 0x200028 596/* [RW 3] The source that is associated with arbitration element 3. Source 597 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 598 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 599 not be equal to register ~csem_registers_arb_element0.arb_element0 and 600 ~csem_registers_arb_element1.arb_element1 and 601 ~csem_registers_arb_element2.arb_element2 */ 602#define CSEM_REG_ARB_ELEMENT3 0x20002c 603/* [RW 3] The source that is associated with arbitration element 4. Source 604 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 605 sleeping thread with priority 1; 4- sleeping thread with priority 2. 606 Could not be equal to register ~csem_registers_arb_element0.arb_element0 607 and ~csem_registers_arb_element1.arb_element1 and 608 ~csem_registers_arb_element2.arb_element2 and 609 ~csem_registers_arb_element3.arb_element3 */ 610#define CSEM_REG_ARB_ELEMENT4 0x200030 611/* [RW 32] Interrupt mask register #0 read/write */ 612#define CSEM_REG_CSEM_INT_MASK_0 0x200110 613#define CSEM_REG_CSEM_INT_MASK_1 0x200120 614/* [R 32] Interrupt register #0 read */ 615#define CSEM_REG_CSEM_INT_STS_0 0x200104 616#define CSEM_REG_CSEM_INT_STS_1 0x200114 617/* [RW 32] Parity mask register #0 read/write */ 618#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130 619#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140 620/* [R 32] Parity register #0 read */ 621#define CSEM_REG_CSEM_PRTY_STS_0 0x200124 622#define CSEM_REG_CSEM_PRTY_STS_1 0x200134 623/* [RC 32] Parity register #0 read clear */ 624#define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128 625#define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138 626#define CSEM_REG_ENABLE_IN 0x2000a4 627#define CSEM_REG_ENABLE_OUT 0x2000a8 628/* [RW 32] This address space contains all registers and memories that are 629 placed in SEM_FAST block. The SEM_FAST registers are described in 630 appendix B. In order to access the sem_fast registers the base address 631 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 632#define CSEM_REG_FAST_MEMORY 0x220000 633/* [RW 1] Disables input messages from FIC0 May be updated during run_time 634 by the microcode */ 635#define CSEM_REG_FIC0_DISABLE 0x200224 636/* [RW 1] Disables input messages from FIC1 May be updated during run_time 637 by the microcode */ 638#define CSEM_REG_FIC1_DISABLE 0x200234 639/* [RW 15] Interrupt table Read and write access to it is not possible in 640 the middle of the work */ 641#define CSEM_REG_INT_TABLE 0x200400 642/* [ST 24] Statistics register. The number of messages that entered through 643 FIC0 */ 644#define CSEM_REG_MSG_NUM_FIC0 0x200000 645/* [ST 24] Statistics register. The number of messages that entered through 646 FIC1 */ 647#define CSEM_REG_MSG_NUM_FIC1 0x200004 648/* [ST 24] Statistics register. The number of messages that were sent to 649 FOC0 */ 650#define CSEM_REG_MSG_NUM_FOC0 0x200008 651/* [ST 24] Statistics register. The number of messages that were sent to 652 FOC1 */ 653#define CSEM_REG_MSG_NUM_FOC1 0x20000c 654/* [ST 24] Statistics register. The number of messages that were sent to 655 FOC2 */ 656#define CSEM_REG_MSG_NUM_FOC2 0x200010 657/* [ST 24] Statistics register. The number of messages that were sent to 658 FOC3 */ 659#define CSEM_REG_MSG_NUM_FOC3 0x200014 660/* [RW 1] Disables input messages from the passive buffer May be updated 661 during run_time by the microcode */ 662#define CSEM_REG_PAS_DISABLE 0x20024c 663/* [WB 128] Debug only. Passive buffer memory */ 664#define CSEM_REG_PASSIVE_BUFFER 0x202000 665/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 666#define CSEM_REG_PRAM 0x240000 667/* [R 16] Valid sleeping threads indication have bit per thread */ 668#define CSEM_REG_SLEEP_THREADS_VALID 0x20026c 669/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 670#define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0 671/* [RW 16] List of free threads . There is a bit per thread. */ 672#define CSEM_REG_THREADS_LIST 0x2002e4 673/* [RW 3] The arbitration scheme of time_slot 0 */ 674#define CSEM_REG_TS_0_AS 0x200038 675/* [RW 3] The arbitration scheme of time_slot 10 */ 676#define CSEM_REG_TS_10_AS 0x200060 677/* [RW 3] The arbitration scheme of time_slot 11 */ 678#define CSEM_REG_TS_11_AS 0x200064 679/* [RW 3] The arbitration scheme of time_slot 12 */ 680#define CSEM_REG_TS_12_AS 0x200068 681/* [RW 3] The arbitration scheme of time_slot 13 */ 682#define CSEM_REG_TS_13_AS 0x20006c 683/* [RW 3] The arbitration scheme of time_slot 14 */ 684#define CSEM_REG_TS_14_AS 0x200070 685/* [RW 3] The arbitration scheme of time_slot 15 */ 686#define CSEM_REG_TS_15_AS 0x200074 687/* [RW 3] The arbitration scheme of time_slot 16 */ 688#define CSEM_REG_TS_16_AS 0x200078 689/* [RW 3] The arbitration scheme of time_slot 17 */ 690#define CSEM_REG_TS_17_AS 0x20007c 691/* [RW 3] The arbitration scheme of time_slot 18 */ 692#define CSEM_REG_TS_18_AS 0x200080 693/* [RW 3] The arbitration scheme of time_slot 1 */ 694#define CSEM_REG_TS_1_AS 0x20003c 695/* [RW 3] The arbitration scheme of time_slot 2 */ 696#define CSEM_REG_TS_2_AS 0x200040 697/* [RW 3] The arbitration scheme of time_slot 3 */ 698#define CSEM_REG_TS_3_AS 0x200044 699/* [RW 3] The arbitration scheme of time_slot 4 */ 700#define CSEM_REG_TS_4_AS 0x200048 701/* [RW 3] The arbitration scheme of time_slot 5 */ 702#define CSEM_REG_TS_5_AS 0x20004c 703/* [RW 3] The arbitration scheme of time_slot 6 */ 704#define CSEM_REG_TS_6_AS 0x200050 705/* [RW 3] The arbitration scheme of time_slot 7 */ 706#define CSEM_REG_TS_7_AS 0x200054 707/* [RW 3] The arbitration scheme of time_slot 8 */ 708#define CSEM_REG_TS_8_AS 0x200058 709/* [RW 3] The arbitration scheme of time_slot 9 */ 710#define CSEM_REG_TS_9_AS 0x20005c 711/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 712 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 713#define CSEM_REG_VFPF_ERR_NUM 0x200380 714/* [RW 1] Parity mask register #0 read/write */ 715#define DBG_REG_DBG_PRTY_MASK 0xc0a8 716/* [R 1] Parity register #0 read */ 717#define DBG_REG_DBG_PRTY_STS 0xc09c 718/* [RC 1] Parity register #0 read clear */ 719#define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0 720/* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The 721 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0; 722 * 4.Completion function=0; 5.Error handling=0 */ 723#define DMAE_REG_BACKWARD_COMP_EN 0x10207c 724/* [RW 32] Commands memory. The address to command X; row Y is to calculated 725 as 14*X+Y. */ 726#define DMAE_REG_CMD_MEM 0x102400 727#define DMAE_REG_CMD_MEM_SIZE 224 728/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c 729 initial value is all ones. */ 730#define DMAE_REG_CRC16C_INIT 0x10201c 731/* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the 732 CRC-16 T10 initial value is all ones. */ 733#define DMAE_REG_CRC16T10_INIT 0x102020 734/* [RW 2] Interrupt mask register #0 read/write */ 735#define DMAE_REG_DMAE_INT_MASK 0x102054 736/* [RW 4] Parity mask register #0 read/write */ 737#define DMAE_REG_DMAE_PRTY_MASK 0x102064 738/* [R 4] Parity register #0 read */ 739#define DMAE_REG_DMAE_PRTY_STS 0x102058 740/* [RC 4] Parity register #0 read clear */ 741#define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c 742/* [RW 1] Command 0 go. */ 743#define DMAE_REG_GO_C0 0x102080 744/* [RW 1] Command 1 go. */ 745#define DMAE_REG_GO_C1 0x102084 746/* [RW 1] Command 10 go. */ 747#define DMAE_REG_GO_C10 0x102088 748/* [RW 1] Command 11 go. */ 749#define DMAE_REG_GO_C11 0x10208c 750/* [RW 1] Command 12 go. */ 751#define DMAE_REG_GO_C12 0x102090 752/* [RW 1] Command 13 go. */ 753#define DMAE_REG_GO_C13 0x102094 754/* [RW 1] Command 14 go. */ 755#define DMAE_REG_GO_C14 0x102098 756/* [RW 1] Command 15 go. */ 757#define DMAE_REG_GO_C15 0x10209c 758/* [RW 1] Command 2 go. */ 759#define DMAE_REG_GO_C2 0x1020a0 760/* [RW 1] Command 3 go. */ 761#define DMAE_REG_GO_C3 0x1020a4 762/* [RW 1] Command 4 go. */ 763#define DMAE_REG_GO_C4 0x1020a8 764/* [RW 1] Command 5 go. */ 765#define DMAE_REG_GO_C5 0x1020ac 766/* [RW 1] Command 6 go. */ 767#define DMAE_REG_GO_C6 0x1020b0 768/* [RW 1] Command 7 go. */ 769#define DMAE_REG_GO_C7 0x1020b4 770/* [RW 1] Command 8 go. */ 771#define DMAE_REG_GO_C8 0x1020b8 772/* [RW 1] Command 9 go. */ 773#define DMAE_REG_GO_C9 0x1020bc 774/* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge 775 input is disregarded; valid is deasserted; all other signals are treated 776 as usual; if 1 - normal activity. */ 777#define DMAE_REG_GRC_IFEN 0x102008 778/* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the 779 acknowledge input is disregarded; valid is deasserted; full is asserted; 780 all other signals are treated as usual; if 1 - normal activity. */ 781#define DMAE_REG_PCI_IFEN 0x102004 782/* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the 783 initial value to the credit counter; related to the address. Read returns 784 the current value of the counter. */ 785#define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0 786/* [RW 8] Aggregation command. */ 787#define DORQ_REG_AGG_CMD0 0x170060 788/* [RW 8] Aggregation command. */ 789#define DORQ_REG_AGG_CMD1 0x170064 790/* [RW 8] Aggregation command. */ 791#define DORQ_REG_AGG_CMD2 0x170068 792/* [RW 8] Aggregation command. */ 793#define DORQ_REG_AGG_CMD3 0x17006c 794/* [RW 28] UCM Header. */ 795#define DORQ_REG_CMHEAD_RX 0x170050 796/* [RW 32] Doorbell address for RBC doorbells (function 0). */ 797#define DORQ_REG_DB_ADDR0 0x17008c 798/* [RW 5] Interrupt mask register #0 read/write */ 799#define DORQ_REG_DORQ_INT_MASK 0x170180 800/* [R 5] Interrupt register #0 read */ 801#define DORQ_REG_DORQ_INT_STS 0x170174 802/* [RC 5] Interrupt register #0 read clear */ 803#define DORQ_REG_DORQ_INT_STS_CLR 0x170178 804/* [RW 2] Parity mask register #0 read/write */ 805#define DORQ_REG_DORQ_PRTY_MASK 0x170190 806/* [R 2] Parity register #0 read */ 807#define DORQ_REG_DORQ_PRTY_STS 0x170184 808/* [RC 2] Parity register #0 read clear */ 809#define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188 810/* [RW 8] The address to write the DPM CID to STORM. */ 811#define DORQ_REG_DPM_CID_ADDR 0x170044 812/* [RW 5] The DPM mode CID extraction offset. */ 813#define DORQ_REG_DPM_CID_OFST 0x170030 814/* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */ 815#define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c 816/* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */ 817#define DORQ_REG_DQ_FIFO_FULL_TH 0x170078 818/* [R 13] Current value of the DQ FIFO fill level according to following 819 pointer. The range is 0 - 256 FIFO rows; where each row stands for the 820 doorbell. */ 821#define DORQ_REG_DQ_FILL_LVLF 0x1700a4 822/* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or 823 equal to full threshold; reset on full clear. */ 824#define DORQ_REG_DQ_FULL_ST 0x1700c0 825/* [RW 28] The value sent to CM header in the case of CFC load error. */ 826#define DORQ_REG_ERR_CMHEAD 0x170058 827#define DORQ_REG_IF_EN 0x170004 828#define DORQ_REG_MODE_ACT 0x170008 829/* [RW 5] The normal mode CID extraction offset. */ 830#define DORQ_REG_NORM_CID_OFST 0x17002c 831/* [RW 28] TCM Header when only TCP context is loaded. */ 832#define DORQ_REG_NORM_CMHEAD_TX 0x17004c 833/* [RW 3] The number of simultaneous outstanding requests to Context Fetch 834 Interface. */ 835#define DORQ_REG_OUTST_REQ 0x17003c 836#define DORQ_REG_PF_USAGE_CNT 0x1701d0 837#define DORQ_REG_REGN 0x170038 838/* [R 4] Current value of response A counter credit. Initial credit is 839 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd 840 register. */ 841#define DORQ_REG_RSPA_CRD_CNT 0x1700ac 842/* [R 4] Current value of response B counter credit. Initial credit is 843 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd 844 register. */ 845#define DORQ_REG_RSPB_CRD_CNT 0x1700b0 846/* [RW 4] The initial credit at the Doorbell Response Interface. The write 847 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The 848 read reads this written value. */ 849#define DORQ_REG_RSP_INIT_CRD 0x170048 850/* [RW 4] Initial activity counter value on the load request; when the 851 shortcut is done. */ 852#define DORQ_REG_SHRT_ACT_CNT 0x170070 853/* [RW 28] TCM Header when both ULP and TCP context is loaded. */ 854#define DORQ_REG_SHRT_CMHEAD 0x170054 855#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4) 856#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0) 857#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3) 858#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7) 859#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2) 860#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1) 861#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0) 862#define HC_REG_AGG_INT_0 0x108050 863#define HC_REG_AGG_INT_1 0x108054 864#define HC_REG_ATTN_BIT 0x108120 865#define HC_REG_ATTN_IDX 0x108100 866#define HC_REG_ATTN_MSG0_ADDR_L 0x108018 867#define HC_REG_ATTN_MSG1_ADDR_L 0x108020 868#define HC_REG_ATTN_NUM_P0 0x108038 869#define HC_REG_ATTN_NUM_P1 0x10803c 870#define HC_REG_COMMAND_REG 0x108180 871#define HC_REG_CONFIG_0 0x108000 872#define HC_REG_CONFIG_1 0x108004 873#define HC_REG_FUNC_NUM_P0 0x1080ac 874#define HC_REG_FUNC_NUM_P1 0x1080b0 875/* [RW 3] Parity mask register #0 read/write */ 876#define HC_REG_HC_PRTY_MASK 0x1080a0 877/* [R 3] Parity register #0 read */ 878#define HC_REG_HC_PRTY_STS 0x108094 879/* [RC 3] Parity register #0 read clear */ 880#define HC_REG_HC_PRTY_STS_CLR 0x108098 881#define HC_REG_INT_MASK 0x108108 882#define HC_REG_LEADING_EDGE_0 0x108040 883#define HC_REG_LEADING_EDGE_1 0x108048 884#define HC_REG_MAIN_MEMORY 0x108800 885#define HC_REG_MAIN_MEMORY_SIZE 152 886#define HC_REG_P0_PROD_CONS 0x108200 887#define HC_REG_P1_PROD_CONS 0x108400 888#define HC_REG_PBA_COMMAND 0x108140 889#define HC_REG_PCI_CONFIG_0 0x108010 890#define HC_REG_PCI_CONFIG_1 0x108014 891#define HC_REG_STATISTIC_COUNTERS 0x109000 892#define HC_REG_TRAILING_EDGE_0 0x108044 893#define HC_REG_TRAILING_EDGE_1 0x10804c 894#define HC_REG_UC_RAM_ADDR_0 0x108028 895#define HC_REG_UC_RAM_ADDR_1 0x108030 896#define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068 897#define HC_REG_VQID_0 0x108008 898#define HC_REG_VQID_1 0x10800c 899#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1) 900#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0) 901#define IGU_REG_ATTENTION_ACK_BITS 0x130108 902/* [R 4] Debug: attn_fsm */ 903#define IGU_REG_ATTN_FSM 0x130054 904#define IGU_REG_ATTN_MSG_ADDR_H 0x13011c 905#define IGU_REG_ATTN_MSG_ADDR_L 0x130120 906/* [R 4] Debug: [3] - attention write done message is pending (0-no pending; 907 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but 908 * write done didn't receive. */ 909#define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030 910#define IGU_REG_BLOCK_CONFIGURATION 0x130000 911#define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124 912#define IGU_REG_COMMAND_REG_CTRL 0x13012c 913/* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit 914 * is clear. The bits in this registers are set and clear via the producer 915 * command. Data valid only in addresses 0-4. all the rest are zero. */ 916#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200 917/* [R 5] Debug: ctrl_fsm */ 918#define IGU_REG_CTRL_FSM 0x130064 919/* [R 1] data available for error memory. If this bit is clear do not red 920 * from error_handling_memory. */ 921#define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130 922/* [RW 11] Parity mask register #0 read/write */ 923#define IGU_REG_IGU_PRTY_MASK 0x1300a8 924/* [R 11] Parity register #0 read */ 925#define IGU_REG_IGU_PRTY_STS 0x13009c 926/* [RC 11] Parity register #0 read clear */ 927#define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0 928/* [R 4] Debug: int_handle_fsm */ 929#define IGU_REG_INT_HANDLE_FSM 0x130050 930#define IGU_REG_LEADING_EDGE_LATCH 0x130134 931/* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid. 932 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF 933 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */ 934#define IGU_REG_MAPPING_MEMORY 0x131000 935#define IGU_REG_MAPPING_MEMORY_SIZE 136 936#define IGU_REG_PBA_STATUS_LSB 0x130138 937#define IGU_REG_PBA_STATUS_MSB 0x13013c 938#define IGU_REG_PCI_PF_MSI_EN 0x130140 939#define IGU_REG_PCI_PF_MSIX_EN 0x130144 940#define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148 941/* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no 942 * pending; 1 = pending. Pendings means interrupt was asserted; and write 943 * done was not received. Data valid only in addresses 0-4. all the rest are 944 * zero. */ 945#define IGU_REG_PENDING_BITS_STATUS 0x130300 946#define IGU_REG_PF_CONFIGURATION 0x130154 947/* [RW 20] producers only. E2 mode: address 0-135 match to the mapping 948 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default 949 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod; 950 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode 951 * - In backward compatible mode; for non default SB; each even line in the 952 * memory holds the U producer and each odd line hold the C producer. The 953 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The 954 * last 20 producers are for the DSB for each PF. each PF has five segments 955 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 956 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */ 957#define IGU_REG_PROD_CONS_MEMORY 0x132000 958/* [R 3] Debug: pxp_arb_fsm */ 959#define IGU_REG_PXP_ARB_FSM 0x130068 960/* [RW 6] Write one for each bit will reset the appropriate memory. When the 961 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping 962 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3 963 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */ 964#define IGU_REG_RESET_MEMORIES 0x130158 965/* [R 4] Debug: sb_ctrl_fsm */ 966#define IGU_REG_SB_CTRL_FSM 0x13004c 967#define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c 968#define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160 969#define IGU_REG_SB_MASK_LSB 0x130164 970#define IGU_REG_SB_MASK_MSB 0x130168 971/* [RW 16] Number of command that were dropped without causing an interrupt 972 * due to: read access for WO BAR address; or write access for RO BAR 973 * address or any access for reserved address or PCI function error is set 974 * and address is not MSIX; PBA or cleanup */ 975#define IGU_REG_SILENT_DROP 0x13016c 976/* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 - 977 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per 978 * PF; 68-71 number of ATTN messages per PF */ 979#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800 980/* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a 981 * timer mask command arrives. Value must be bigger than 100. */ 982#define IGU_REG_TIMER_MASKING_VALUE 0x13003c 983#define IGU_REG_TRAILING_EDGE_LATCH 0x130104 984#define IGU_REG_VF_CONFIGURATION 0x130170 985/* [WB_R 32] Each bit represent write done pending bits status for that SB 986 * (MSI/MSIX message was sent and write done was not received yet). 0 = 987 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */ 988#define IGU_REG_WRITE_DONE_PENDING 0x130480 989#define MCP_A_REG_MCPR_SCRATCH 0x3a0000 990#define MCP_REG_MCPR_ACCESS_LOCK 0x8009c 991#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c 992#define MCP_REG_MCPR_GP_INPUTS 0x800c0 993#define MCP_REG_MCPR_GP_OENABLE 0x800c8 994#define MCP_REG_MCPR_GP_OUTPUTS 0x800c4 995#define MCP_REG_MCPR_IMC_COMMAND 0x85900 996#define MCP_REG_MCPR_IMC_DATAREG0 0x85920 997#define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904 998#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c 999#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424 1000#define MCP_REG_MCPR_NVM_ADDR 0x8640c 1001#define MCP_REG_MCPR_NVM_CFG4 0x8642c 1002#define MCP_REG_MCPR_NVM_COMMAND 0x86400 1003#define MCP_REG_MCPR_NVM_READ 0x86410 1004#define MCP_REG_MCPR_NVM_SW_ARB 0x86420 1005#define MCP_REG_MCPR_NVM_WRITE 0x86408 1006#define MCP_REG_MCPR_SCRATCH 0xa0000 1007#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1) 1008#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0) 1009/* [R 32] read first 32 bit after inversion of function 0. mapped as 1010 follows: [0] NIG attention for function0; [1] NIG attention for 1011 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; 1012 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] 1013 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE 1014 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; 1015 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] 1016 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB 1017 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw 1018 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity 1019 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw 1020 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF 1021 Parity error; [31] PBF Hw interrupt; */ 1022#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c 1023#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430 1024/* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0] 1025 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 1026 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; 1027 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] 1028 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event 1029 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP 1030 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for 1031 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] 1032 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC 1033 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw 1034 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI 1035 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw 1036 interrupt; */ 1037#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434 1038/* [R 32] read second 32 bit after inversion of function 0. mapped as 1039 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1040 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1041 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1042 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1043 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1044 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1045 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1046 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1047 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1048 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1049 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1050 interrupt; */ 1051#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438 1052#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c 1053/* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0] 1054 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error; 1055 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; 1056 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] 1057 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] 1058 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity 1059 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux 1060 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; 1061 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; 1062 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; 1063 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; 1064 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ 1065#define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440 1066/* [R 32] read third 32 bit after inversion of function 0. mapped as 1067 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity 1068 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] 1069 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1070 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1071 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1072 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1073 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1074 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1075 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1076 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1077 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1078 attn1; */ 1079#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444 1080#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448 1081/* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0] 1082 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP 1083 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient 1084 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity 1085 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw 1086 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] 1087 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] 1088 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW 1089 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 1090 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 1091 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW 1092 timers attn_4 func1; [30] General attn0; [31] General attn1; */ 1093#define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c 1094/* [R 32] read fourth 32 bit after inversion of function 0. mapped as 1095 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1096 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1097 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1098 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1099 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1100 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1101 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1102 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1103 Latched timeout attention; [27] GRC Latched reserved access attention; 1104 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1105 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1106#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450 1107#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454 1108/* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0] 1109 General attn2; [1] General attn3; [2] General attn4; [3] General attn5; 1110 [4] General attn6; [5] General attn7; [6] General attn8; [7] General 1111 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] 1112 General attn13; [12] General attn14; [13] General attn15; [14] General 1113 attn16; [15] General attn17; [16] General attn18; [17] General attn19; 1114 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] 1115 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] 1116 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout 1117 attention; [27] GRC Latched reserved access attention; [28] MCP Latched 1118 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched 1119 ump_tx_parity; [31] MCP Latched scpad_parity; */ 1120#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458 1121/* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as 1122 * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC 1123 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] 1124 * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */ 1125#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700 1126/* [W 14] write to this register results with the clear of the latched 1127 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in 1128 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP 1129 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears 1130 GRC Latched reserved access attention; one in d7 clears Latched 1131 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears 1132 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both 1133 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears 1134 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read 1135 from this register return zero */ 1136#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c 1137/* [RW 32] first 32b for enabling the output for function 0 output0. mapped 1138 as follows: [0] NIG attention for function0; [1] NIG attention for 1139 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 1140 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1141 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1142 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1143 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1144 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 1145 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1146 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1147 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1148 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1149 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1150#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c 1151#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c 1152#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c 1153#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c 1154#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc 1155#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc 1156#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc 1157/* [RW 32] first 32b for enabling the output for function 1 output0. mapped 1158 as follows: [0] NIG attention for function0; [1] NIG attention for 1159 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 1160 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1161 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1162 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1163 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1164 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X 1165 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1166 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1167 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1168 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1169 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1170#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c 1171#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c 1172#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c 1173#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c 1174#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c 1175#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c 1176#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c 1177/* [RW 32] first 32b for enabling the output for close the gate nig. mapped 1178 as follows: [0] NIG attention for function0; [1] NIG attention for 1179 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 1180 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1181 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1182 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1183 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1184 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 1185 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1186 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1187 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1188 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1189 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1190#define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec 1191#define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c 1192/* [RW 32] first 32b for enabling the output for close the gate pxp. mapped 1193 as follows: [0] NIG attention for function0; [1] NIG attention for 1194 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 1195 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1196 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1197 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1198 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1199 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 1200 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1201 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1202 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1203 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1204 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1205#define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc 1206#define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c 1207/* [RW 32] second 32b for enabling the output for function 0 output0. mapped 1208 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1209 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1210 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1211 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1212 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1213 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1214 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1215 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1216 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1217 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1218 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1219 interrupt; */ 1220#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070 1221#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080 1222/* [RW 32] second 32b for enabling the output for function 1 output0. mapped 1223 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1224 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1225 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1226 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1227 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1228 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1229 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1230 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1231 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1232 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1233 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1234 interrupt; */ 1235#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110 1236#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120 1237/* [RW 32] second 32b for enabling the output for close the gate nig. mapped 1238 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1239 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1240 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1241 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1242 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1243 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1244 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1245 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1246 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1247 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1248 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1249 interrupt; */ 1250#define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0 1251#define MISC_REG_AEU_ENABLE2_NIG_1 0xa190 1252/* [RW 32] second 32b for enabling the output for close the gate pxp. mapped 1253 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1254 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1255 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1256 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1257 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1258 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1259 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1260 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1261 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1262 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1263 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1264 interrupt; */ 1265#define MISC_REG_AEU_ENABLE2_PXP_0 0xa100 1266#define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0 1267/* [RW 32] third 32b for enabling the output for function 0 output0. mapped 1268 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1269 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1270 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1271 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1272 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1273 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1274 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1275 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1276 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1277 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1278 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1279 attn1; */ 1280#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074 1281#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084 1282/* [RW 32] third 32b for enabling the output for function 1 output0. mapped 1283 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1284 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1285 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1286 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1287 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1288 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1289 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1290 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1291 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1292 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1293 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1294 attn1; */ 1295#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114 1296#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124 1297/* [RW 32] third 32b for enabling the output for close the gate nig. mapped 1298 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1299 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1300 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1301 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1302 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1303 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1304 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1305 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1306 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1307 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1308 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1309 attn1; */ 1310#define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4 1311#define MISC_REG_AEU_ENABLE3_NIG_1 0xa194 1312/* [RW 32] third 32b for enabling the output for close the gate pxp. mapped 1313 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1314 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1315 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1316 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1317 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1318 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1319 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1320 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1321 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1322 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1323 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1324 attn1; */ 1325#define MISC_REG_AEU_ENABLE3_PXP_0 0xa104 1326#define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4 1327/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped 1328 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1329 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1330 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1331 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1332 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1333 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1334 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1335 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1336 Latched timeout attention; [27] GRC Latched reserved access attention; 1337 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1338 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1339#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078 1340#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098 1341#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8 1342#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8 1343#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8 1344#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8 1345/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped 1346 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1347 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1348 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1349 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1350 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1351 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1352 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1353 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1354 Latched timeout attention; [27] GRC Latched reserved access attention; 1355 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1356 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1357#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118 1358#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138 1359#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158 1360#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168 1361#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178 1362#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188 1363/* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped 1364 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1365 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1366 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1367 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1368 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1369 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1370 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1371 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1372 Latched timeout attention; [27] GRC Latched reserved access attention; 1373 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1374 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1375#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8 1376#define MISC_REG_AEU_ENABLE4_NIG_1 0xa198 1377/* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped 1378 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1379 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1380 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1381 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1382 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1383 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1384 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1385 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1386 Latched timeout attention; [27] GRC Latched reserved access attention; 1387 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1388 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1389#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108 1390#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8 1391/* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped 1392 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC 1393 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] 1394 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 1395 * parity; [31-10] Reserved; */ 1396#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688 1397/* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped 1398 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC 1399 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] 1400 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 1401 * parity; [31-10] Reserved; */ 1402#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0 1403/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu 1404 128 bit vector */ 1405#define MISC_REG_AEU_GENERAL_ATTN_0 0xa000 1406#define MISC_REG_AEU_GENERAL_ATTN_1 0xa004 1407#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028 1408#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c 1409#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030 1410#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008 1411#define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c 1412#define MISC_REG_AEU_GENERAL_ATTN_4 0xa010 1413#define MISC_REG_AEU_GENERAL_ATTN_5 0xa014 1414#define MISC_REG_AEU_GENERAL_ATTN_6 0xa018 1415#define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c 1416#define MISC_REG_AEU_GENERAL_ATTN_8 0xa020 1417#define MISC_REG_AEU_GENERAL_ATTN_9 0xa024 1418#define MISC_REG_AEU_GENERAL_MASK 0xa61c 1419/* [RW 32] first 32b for inverting the input for function 0; for each bit: 1420 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for 1421 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; 1422 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; 1423 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1424 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1425 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1426 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication 1427 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS 1428 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw 1429 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM 1430 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI 1431 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1432#define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c 1433#define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c 1434/* [RW 32] second 32b for inverting the input for function 0; for each bit: 1435 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity 1436 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw 1437 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM 1438 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw 1439 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] 1440 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity 1441 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux 1442 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; 1443 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; 1444 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; 1445 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; 1446 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ 1447#define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230 1448#define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240 1449/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0; 1450 [9:8] = raserved. Zero = mask; one = unmask */ 1451#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060 1452#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064 1453/* [RW 1] If set a system kill occurred */ 1454#define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610 1455/* [RW 32] Represent the status of the input vector to the AEU when a system 1456 kill occurred. The register is reset in por reset. Mapped as follows: [0] 1457 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 1458 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; 1459 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] 1460 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event 1461 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP 1462 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for 1463 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] 1464 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC 1465 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw 1466 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI 1467 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw 1468 interrupt; */ 1469#define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600 1470#define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604 1471#define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608 1472#define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c 1473/* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1 1474 Port. */ 1475#define MISC_REG_BOND_ID 0xa400 1476/* [R 8] These bits indicate the metal revision of the chip. This value 1477 starts at 0x00 for each all-layer tape-out and increments by one for each 1478 tape-out. */ 1479#define MISC_REG_CHIP_METAL 0xa404 1480/* [R 16] These bits indicate the part number for the chip. */ 1481#define MISC_REG_CHIP_NUM 0xa408 1482/* [R 4] These bits indicate the base revision of the chip. This value 1483 starts at 0x0 for the A0 tape-out and increments by one for each 1484 all-layer tape-out. */ 1485#define MISC_REG_CHIP_REV 0xa40c 1486/* [RW 32] The following driver registers(1...16) represent 16 drivers and 1487 32 clients. Each client can be controlled by one driver only. One in each 1488 bit represent that this driver control the appropriate client (Ex: bit 5 1489 is set means this driver control client number 5). addr1 = set; addr0 = 1490 clear; read from both addresses will give the same result = status. write 1491 to address 1 will set a request to control all the clients that their 1492 appropriate bit (in the write command) is set. if the client is free (the 1493 appropriate bit in all the other drivers is clear) one will be written to 1494 that driver register; if the client isn't free the bit will remain zero. 1495 if the appropriate bit is set (the driver request to gain control on a 1496 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW 1497 interrupt will be asserted). write to address 0 will set a request to 1498 free all the clients that their appropriate bit (in the write command) is 1499 set. if the appropriate bit is clear (the driver request to free a client 1500 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will 1501 be asserted). */ 1502#define MISC_REG_DRIVER_CONTROL_1 0xa510 1503#define MISC_REG_DRIVER_CONTROL_7 0xa3c8 1504/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0 1505 only. */ 1506#define MISC_REG_E1HMF_MODE 0xa5f8 1507/* [R 1] Status of four port mode path swap input pin. */ 1508#define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c 1509/* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 - 1510 the path_swap output is equal to 4 port mode path swap input pin; if it 1511 is 1 - the path_swap output is equal to bit[1] of this register; [1] - 1512 Overwrite value. If bit[0] of this register is 1 this is the value that 1513 receives the path_swap output. Reset on Hard reset. */ 1514#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738 1515/* [R 1] Status of 4 port mode port swap input pin. */ 1516#define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754 1517/* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 - 1518 the port_swap output is equal to 4 port mode port swap input pin; if it 1519 is 1 - the port_swap output is equal to bit[1] of this register; [1] - 1520 Overwrite value. If bit[0] of this register is 1 this is the value that 1521 receives the port_swap output. Reset on Hard reset. */ 1522#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734 1523/* [RW 32] Debug only: spare RW register reset by core reset */ 1524#define MISC_REG_GENERIC_CR_0 0xa460 1525#define MISC_REG_GENERIC_CR_1 0xa464 1526/* [RW 32] Debug only: spare RW register reset by por reset */ 1527#define MISC_REG_GENERIC_POR_1 0xa474 1528/* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to 1529 use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO 1530 can not be configured as an output. Each output has its output enable in 1531 the MCP register space; but this bit needs to be set to make use of that. 1532 Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When 1533 set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON. 1534 When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change 1535 the i/o to an output and will drive the TimeSync output. Bit[31:7]: 1536 spare. Global register. Reset by hard reset. */ 1537#define MISC_REG_GEN_PURP_HWG 0xa9a0 1538/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of 1539 these bits is written as a '1'; the corresponding SPIO bit will turn off 1540 it's drivers and become an input. This is the reset state of all GPIO 1541 pins. The read value of these bits will be a '1' if that last command 1542 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff). 1543 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written 1544 as a '1'; the corresponding GPIO bit will drive low. The read value of 1545 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for 1546 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0; 1547 SET When any of these bits is written as a '1'; the corresponding GPIO 1548 bit will drive high (if it has that capability). The read value of these 1549 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this 1550 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0; 1551 RO; These bits indicate the read value of each of the eight GPIO pins. 1552 This is the result value of the pin; not the drive value. Writing these 1553 bits will have not effect. */ 1554#define MISC_REG_GPIO 0xa490 1555/* [RW 8] These bits enable the GPIO_INTs to signals event to the 1556 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2] 1557 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2; 1558 [7] p1_gpio_3; */ 1559#define MISC_REG_GPIO_EVENT_EN 0xa2bc 1560/* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a 1561 '1' to these bit clears the corresponding bit in the #OLD_VALUE register. 1562 This will acknowledge an interrupt on the falling edge of corresponding 1563 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0; 1564 Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE 1565 register. This will acknowledge an interrupt on the rising edge of 1566 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1; 1567 OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input 1568 value. When the ~INT_STATE bit is set; this bit indicates the OLD value 1569 of the pin such that if ~INT_STATE is set and this bit is '0'; then the 1570 interrupt is due to a low to high edge. If ~INT_STATE is set and this bit 1571 is '1'; then the interrupt is due to a high to low edge (reset value 0). 1572 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the 1573 current GPIO interrupt state for each GPIO pin. This bit is cleared when 1574 the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is 1575 set when the GPIO input does not match the current value in #OLD_VALUE 1576 (reset value 0). */ 1577#define MISC_REG_GPIO_INT 0xa494 1578/* [R 28] this field hold the last information that caused reserved 1579 attention. bits [19:0] - address; [22:20] function; [23] reserved; 1580 [27:24] the master that caused the attention - according to the following 1581 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1582 dbu; 8 = dmae */ 1583#define MISC_REG_GRC_RSV_ATTN 0xa3c0 1584/* [R 28] this field hold the last information that caused timeout 1585 attention. bits [19:0] - address; [22:20] function; [23] reserved; 1586 [27:24] the master that caused the attention - according to the following 1587 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1588 dbu; 8 = dmae */ 1589#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4 1590/* [RW 1] Setting this bit enables a timer in the GRC block to timeout any 1591 access that does not finish within 1592 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is 1593 cleared; this timeout is disabled. If this timeout occurs; the GRC shall 1594 assert it attention output. */ 1595#define MISC_REG_GRC_TIMEOUT_EN 0xa280 1596/* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of 1597 the bits is: [2:0] OAC reset value 001) CML output buffer bias control; 1598 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl 1599 (reset value 001) Charge pump current control; 111 for 720u; 011 for 1600 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00) 1601 Global bias control; When bit 7 is high bias current will be 10 0gh; When 1602 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8] 1603 Pll_observe (reset value 010) Bits to control observability. bit 10 is 1604 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl 1605 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V 1606 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning 1607 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted 1608 internally). [14] reserved (reset value 0) Reset for VCO sequencer is 1609 connected to RESET input directly. [15] capRetry_en (reset value 0) 1610 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset 1611 value 0) bit to continuously monitor vco freq (inverted). [17] 1612 freqDetRestart_en (reset value 0) bit to enable restart when not freq 1613 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable 1614 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value 1615 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20] 1616 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass 1617 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value 1618 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0) 1619 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to 1620 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force 1621 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to 1622 restart. [27] capSelectM_en (reset value 0) bit to enable cap select 1623 register bits. */ 1624#define MISC_REG_LCPLL_CTRL_1 0xa2a4 1625#define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8 1626/* [RW 1] LCPLL power down. Global register. Active High. Reset on POR 1627 * reset. */ 1628#define MISC_REG_LCPLL_E40_PWRDWN 0xaa74 1629/* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */ 1630#define MISC_REG_LCPLL_E40_RESETB_ANA 0xaa78 1631/* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR 1632 * reset. */ 1633#define MISC_REG_LCPLL_E40_RESETB_DIG 0xaa7c 1634/* [RW 4] Interrupt mask register #0 read/write */ 1635#define MISC_REG_MISC_INT_MASK 0xa388 1636/* [RW 1] Parity mask register #0 read/write */ 1637#define MISC_REG_MISC_PRTY_MASK 0xa398 1638/* [R 1] Parity register #0 read */ 1639#define MISC_REG_MISC_PRTY_STS 0xa38c 1640/* [RC 1] Parity register #0 read clear */ 1641#define MISC_REG_MISC_PRTY_STS_CLR 0xa390 1642#define MISC_REG_NIG_WOL_P0 0xa270 1643#define MISC_REG_NIG_WOL_P1 0xa274 1644/* [R 1] If set indicate that the pcie_rst_b was asserted without perst 1645 assertion */ 1646#define MISC_REG_PCIE_HOT_RESET 0xa618 1647/* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911. 1648 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1 1649 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1 1650 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2 1651 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2 1652 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9] 1653 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1] 1654 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value 1655 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16] 1656 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset 1657 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value 1658 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0); 1659 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25] 1660 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27] 1661 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29] 1662 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31] 1663 testa_en (reset value 0); */ 1664#define MISC_REG_PLL_STORM_CTRL_1 0xa294 1665#define MISC_REG_PLL_STORM_CTRL_2 0xa298 1666#define MISC_REG_PLL_STORM_CTRL_3 0xa29c 1667#define MISC_REG_PLL_STORM_CTRL_4 0xa2a0 1668/* [R 1] Status of 4 port mode enable input pin. */ 1669#define MISC_REG_PORT4MODE_EN 0xa750 1670/* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 - 1671 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 - 1672 * the port4mode_en output is equal to bit[1] of this register; [1] - 1673 * Overwrite value. If bit[0] of this register is 1 this is the value that 1674 * receives the port4mode_en output . */ 1675#define MISC_REG_PORT4MODE_EN_OVWR 0xa720 1676/* [RW 32] reset reg#2; rite/read one = the specific block is out of reset; 1677 write/read zero = the specific block is in reset; addr 0-wr- the write 1678 value will be written to the register; addr 1-set - one will be written 1679 to all the bits that have the value of one in the data written (bits that 1680 have the value of zero will not be change) ; addr 2-clear - zero will be 1681 written to all the bits that have the value of one in the data written 1682 (bits that have the value of zero will not be change); addr 3-ignore; 1683 read ignore from all addr except addr 00; inside order of the bits is: 1684 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc; 1685 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7] 1686 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn; 1687 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13] 1688 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16] 1689 rst_pxp_rq_rd_wr; 31:17] reserved */ 1690#define MISC_REG_RESET_REG_1 0xa580 1691#define MISC_REG_RESET_REG_2 0xa590 1692/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is 1693 shared with the driver resides */ 1694#define MISC_REG_SHARED_MEM_ADDR 0xa2b4 1695/* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1'; 1696 the corresponding SPIO bit will turn off it's drivers and become an 1697 input. This is the reset state of all SPIO pins. The read value of these 1698 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this 1699 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits 1700 is written as a '1'; the corresponding SPIO bit will drive low. The read 1701 value of these bits will be a '1' if that last command (#SET; #CLR; or 1702#FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of 1703 these bits is written as a '1'; the corresponding SPIO bit will drive 1704 high (if it has that capability). The read value of these bits will be a 1705 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET. 1706 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of 1707 each of the eight SPIO pins. This is the result value of the pin; not the 1708 drive value. Writing these bits will have not effect. Each 8 bits field 1709 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply 1710 from VAUX. (This is an output pin only; the FLOAT field is not applicable 1711 for this pin); [1] VAUX Disable; when pulsed low; disables supply form 1712 VAUX. (This is an output pin only; FLOAT field is not applicable for this 1713 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to 1714 select VAUX supply. (This is an output pin only; it is not controlled by 1715 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT 1716 field is not applicable for this pin; only the VALUE fields is relevant - 1717 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6] 1718 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP 1719 device ID select; read by UMP firmware. */ 1720#define MISC_REG_SPIO 0xa4fc 1721/* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC. 1722 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5; 1723 [7:0] reserved */ 1724#define MISC_REG_SPIO_EVENT_EN 0xa2b8 1725/* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the 1726 corresponding bit in the #OLD_VALUE register. This will acknowledge an 1727 interrupt on the falling edge of corresponding SPIO input (reset value 1728 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit 1729 in the #OLD_VALUE register. This will acknowledge an interrupt on the 1730 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE 1731 RO; These bits indicate the old value of the SPIO input value. When the 1732 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such 1733 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due 1734 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the 1735 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE 1736 RO; These bits indicate the current SPIO interrupt state for each SPIO 1737 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR 1738 command bit is written. This bit is set when the SPIO input does not 1739 match the current value in #OLD_VALUE (reset value 0). */ 1740#define MISC_REG_SPIO_INT 0xa500 1741/* [RW 32] reload value for counter 4 if reload; the value will be reload if 1742 the counter reached zero and the reload bit 1743 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */ 1744#define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc 1745/* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses 1746 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 - 1747 timer 8 */ 1748#define MISC_REG_SW_TIMER_VAL 0xa5c0 1749/* [R 1] Status of two port mode path swap input pin. */ 1750#define MISC_REG_TWO_PORT_PATH_SWAP 0xa758 1751/* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the 1752 path_swap output is equal to 2 port mode path swap input pin; if it is 1 1753 - the path_swap output is equal to bit[1] of this register; [1] - 1754 Overwrite value. If bit[0] of this register is 1 this is the value that 1755 receives the path_swap output. Reset on Hard reset. */ 1756#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c 1757/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are 1758 loaded; 0-prepare; -unprepare */ 1759#define MISC_REG_UNPREPARED 0xa424 1760#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0) 1761#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1) 1762#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4) 1763#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2) 1764#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3) 1765/* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or 1766 * not it is the recipient of the message on the MDIO interface. The value 1767 * is compared to the value on ctrl_md_devad. Drives output 1768 * misc_xgxs0_phy_addr. Global register. */ 1769#define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc 1770#define MISC_REG_WC0_RESET 0xac30 1771/* [RW 2] XMAC Core port mode. Indicates the number of ports on the system 1772 side. This should be less than or equal to phy_port_mode; if some of the 1773 ports are not used. This enables reduction of frequency on the core side. 1774 This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - 1775 Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap 1776 input for the XMAC_MP core; and should be changed only while reset is 1777 held low. Reset on Hard reset. */ 1778#define MISC_REG_XMAC_CORE_PORT_MODE 0xa964 1779/* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp 1780 Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 1781 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the 1782 XMAC_MP core; and should be changed only while reset is held low. Reset 1783 on Hard reset. */ 1784#define MISC_REG_XMAC_PHY_PORT_MODE 0xa960 1785/* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0. 1786 * Reads from this register will clear bits 31:0. */ 1787#define MSTAT_REG_RX_STAT_GR64_LO 0x200 1788/* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits 1789 * 31:0. Reads from this register will clear bits 31:0. */ 1790#define MSTAT_REG_TX_STAT_GTXPOK_LO 0 1791#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0) 1792#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1) 1793#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4) 1794#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2) 1795#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3) 1796#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0) 1797#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0) 1798#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0) 1799#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9) 1800#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15) 1801#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18) 1802/* [RW 1] Input enable for RX_BMAC0 IF */ 1803#define NIG_REG_BMAC0_IN_EN 0x100ac 1804/* [RW 1] output enable for TX_BMAC0 IF */ 1805#define NIG_REG_BMAC0_OUT_EN 0x100e0 1806/* [RW 1] output enable for TX BMAC pause port 0 IF */ 1807#define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110 1808/* [RW 1] output enable for RX_BMAC0_REGS IF */ 1809#define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8 1810/* [RW 1] output enable for RX BRB1 port0 IF */ 1811#define NIG_REG_BRB0_OUT_EN 0x100f8 1812/* [RW 1] Input enable for TX BRB1 pause port 0 IF */ 1813#define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4 1814/* [RW 1] output enable for RX BRB1 port1 IF */ 1815#define NIG_REG_BRB1_OUT_EN 0x100fc 1816/* [RW 1] Input enable for TX BRB1 pause port 1 IF */ 1817#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8 1818/* [RW 1] output enable for RX BRB1 LP IF */ 1819#define NIG_REG_BRB_LB_OUT_EN 0x10100 1820/* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64] 1821 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush; 1822 72:73]-vnic_num; 81:74]-sideband_info */ 1823#define NIG_REG_DEBUG_PACKET_LB 0x10800 1824/* [RW 1] Input enable for TX Debug packet */ 1825#define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc 1826/* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all 1827 packets from PBFare not forwarded to the MAC and just deleted from FIFO. 1828 First packet may be deleted from the middle. And last packet will be 1829 always deleted till the end. */ 1830#define NIG_REG_EGRESS_DRAIN0_MODE 0x10060 1831/* [RW 1] Output enable to EMAC0 */ 1832#define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120 1833/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs 1834 to emac for port0; other way to bmac for port0 */ 1835#define NIG_REG_EGRESS_EMAC0_PORT 0x10058 1836/* [RW 1] Input enable for TX PBF user packet port0 IF */ 1837#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc 1838/* [RW 1] Input enable for TX PBF user packet port1 IF */ 1839#define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0 1840/* [RW 1] Input enable for TX UMP management packet port0 IF */ 1841#define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4 1842/* [RW 1] Input enable for RX_EMAC0 IF */ 1843#define NIG_REG_EMAC0_IN_EN 0x100a4 1844/* [RW 1] output enable for TX EMAC pause port 0 IF */ 1845#define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118 1846/* [R 1] status from emac0. This bit is set when MDINT from either the 1847 EXT_MDINT pin or from the Copper PHY is driven low. This condition must 1848 be cleared in the attached PHY device that is driving the MINT pin. */ 1849#define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494 1850/* [WB 48] This address space contains BMAC0 registers. The BMAC registers 1851 are described in appendix A. In order to access the BMAC0 registers; the 1852 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be 1853 added to each BMAC register offset */ 1854#define NIG_REG_INGRESS_BMAC0_MEM 0x10c00 1855/* [WB 48] This address space contains BMAC1 registers. The BMAC registers 1856 are described in appendix A. In order to access the BMAC0 registers; the 1857 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be 1858 added to each BMAC register offset */ 1859#define NIG_REG_INGRESS_BMAC1_MEM 0x11000 1860/* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */ 1861#define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0 1862/* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data 1863 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */ 1864#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4 1865/* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch 1866 logic for interrupts must be used. Enable per bit of interrupt of 1867 ~latch_status.latch_status */ 1868#define NIG_REG_LATCH_BC_0 0x16210 1869/* [RW 27] Latch for each interrupt from Unicore.b[0] 1870 status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete; 1871 b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status; 1872 b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn; 1873 b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete; 1874 b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status; 1875 b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete; 1876 b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet; 1877 b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g; 1878 b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact; 1879 b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx; 1880 b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx; 1881 b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */ 1882#define NIG_REG_LATCH_STATUS_0 0x18000 1883/* [RW 1] led 10g for port 0 */ 1884#define NIG_REG_LED_10G_P0 0x10320 1885/* [RW 1] led 10g for port 1 */ 1886#define NIG_REG_LED_10G_P1 0x10324 1887/* [RW 1] Port0: This bit is set to enable the use of the 1888 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field 1889 defined below. If this bit is cleared; then the blink rate will be about 1890 8Hz. */ 1891#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318 1892/* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for 1893 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field 1894 is reset to 0x080; giving a default blink period of approximately 8Hz. */ 1895#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310 1896/* [RW 1] Port0: If set along with the 1897 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0 1898 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED 1899 bit; the Traffic LED will blink with the blink rate specified in 1900 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and 1901 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 1902 fields. */ 1903#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308 1904/* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The 1905 Traffic LED will then be controlled via bit ~nig_registers_ 1906 led_control_traffic_p0.led_control_traffic_p0 and bit 1907 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */ 1908#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8 1909/* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit; 1910 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also 1911 set; the LED will blink with blink rate specified in 1912 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and 1913 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 1914 fields. */ 1915#define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300 1916/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3; 1917 9-11PHY7; 12 MAC4; 13-15 PHY10; */ 1918#define NIG_REG_LED_MODE_P0 0x102f0 1919/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1- 1920 tsdm enable; b2- usdm enable */ 1921#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070 1922#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074 1923/* [RW 1] SAFC enable for port0. This register may get 1 only when 1924 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same 1925 port */ 1926#define NIG_REG_LLFC_ENABLE_0 0x16208 1927#define NIG_REG_LLFC_ENABLE_1 0x1620c 1928/* [RW 16] classes are high-priority for port0 */ 1929#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058 1930#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c 1931/* [RW 16] classes are low-priority for port0 */ 1932#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060 1933#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064 1934/* [RW 1] Output enable of message to LLFC BMAC IF for port0 */ 1935#define NIG_REG_LLFC_OUT_EN_0 0x160c8 1936#define NIG_REG_LLFC_OUT_EN_1 0x160cc 1937#define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c 1938#define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154 1939#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244 1940#define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048 1941/* [RW 1] send to BRB1 if no match on any of RMP rules. */ 1942#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c 1943/* [RW 2] Determine the classification participants. 0: no classification.1: 1944 classification upon VLAN id. 2: classification upon MAC address. 3: 1945 classification upon both VLAN id & MAC addr. */ 1946#define NIG_REG_LLH0_CLS_TYPE 0x16080 1947/* [RW 32] cm header for llh0 */ 1948#define NIG_REG_LLH0_CM_HEADER 0x1007c 1949#define NIG_REG_LLH0_DEST_IP_0_1 0x101dc 1950#define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0 1951/* [RW 16] destination TCP address 1. The LLH will look for this address in 1952 all incoming packets. */ 1953#define NIG_REG_LLH0_DEST_TCP_0 0x10220 1954/* [RW 16] destination UDP address 1 The LLH will look for this address in 1955 all incoming packets. */ 1956#define NIG_REG_LLH0_DEST_UDP_0 0x10214 1957#define NIG_REG_LLH0_ERROR_MASK 0x1008c 1958/* [RW 8] event id for llh0 */ 1959#define NIG_REG_LLH0_EVENT_ID 0x10084 1960#define NIG_REG_LLH0_FUNC_EN 0x160fc 1961#define NIG_REG_LLH0_FUNC_MEM 0x16180 1962#define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140 1963#define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100 1964/* [RW 1] Determine the IP version to look for in 1965 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */ 1966#define NIG_REG_LLH0_IPV4_IPV6_0 0x10208 1967/* [RW 1] t bit for llh0 */ 1968#define NIG_REG_LLH0_T_BIT 0x10074 1969/* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */ 1970#define NIG_REG_LLH0_VLAN_ID_0 0x1022c 1971/* [RW 8] init credit counter for port0 in LLH */ 1972#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554 1973#define NIG_REG_LLH0_XCM_MASK 0x10130 1974#define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248 1975/* [RW 1] send to BRB1 if no match on any of RMP rules. */ 1976#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc 1977/* [RW 2] Determine the classification participants. 0: no classification.1: 1978 classification upon VLAN id. 2: classification upon MAC address. 3: 1979 classification upon both VLAN id & MAC addr. */ 1980#define NIG_REG_LLH1_CLS_TYPE 0x16084 1981/* [RW 32] cm header for llh1 */ 1982#define NIG_REG_LLH1_CM_HEADER 0x10080 1983#define NIG_REG_LLH1_ERROR_MASK 0x10090 1984/* [RW 8] event id for llh1 */ 1985#define NIG_REG_LLH1_EVENT_ID 0x10088 1986#define NIG_REG_LLH1_FUNC_MEM 0x161c0 1987#define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160 1988#define NIG_REG_LLH1_FUNC_MEM_SIZE 16 1989/* [RW 1] When this bit is set; the LLH will classify the packet before 1990 * sending it to the BRB or calculating WoL on it. This bit controls port 1 1991 * only. The legacy llh_multi_function_mode bit controls port 0. */ 1992#define NIG_REG_LLH1_MF_MODE 0x18614 1993/* [RW 8] init credit counter for port1 in LLH */ 1994#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564 1995#define NIG_REG_LLH1_XCM_MASK 0x10134 1996/* [RW 1] When this bit is set; the LLH will expect all packets to be with 1997 e1hov */ 1998#define NIG_REG_LLH_E1HOV_MODE 0x160d8 1999/* [RW 1] When this bit is set; the LLH will classify the packet before 2000 sending it to the BRB or calculating WoL on it. */ 2001#define NIG_REG_LLH_MF_MODE 0x16024 2002#define NIG_REG_MASK_INTERRUPT_PORT0 0x10330 2003#define NIG_REG_MASK_INTERRUPT_PORT1 0x10334 2004/* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */ 2005#define NIG_REG_NIG_EMAC0_EN 0x1003c 2006/* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */ 2007#define NIG_REG_NIG_EMAC1_EN 0x10040 2008/* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the 2009 EMAC0 to strip the CRC from the ingress packets. */ 2010#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044 2011/* [R 32] Interrupt register #0 read */ 2012#define NIG_REG_NIG_INT_STS_0 0x103b0 2013#define NIG_REG_NIG_INT_STS_1 0x103c0 2014/* [R 32] Legacy E1 and E1H location for parity error mask register. */ 2015#define NIG_REG_NIG_PRTY_MASK 0x103dc 2016/* [RW 32] Parity mask register #0 read/write */ 2017#define NIG_REG_NIG_PRTY_MASK_0 0x183c8 2018#define NIG_REG_NIG_PRTY_MASK_1 0x183d8 2019/* [R 32] Legacy E1 and E1H location for parity error status register. */ 2020#define NIG_REG_NIG_PRTY_STS 0x103d0 2021/* [R 32] Parity register #0 read */ 2022#define NIG_REG_NIG_PRTY_STS_0 0x183bc 2023#define NIG_REG_NIG_PRTY_STS_1 0x183cc 2024/* [R 32] Legacy E1 and E1H location for parity error status clear register. */ 2025#define NIG_REG_NIG_PRTY_STS_CLR 0x103d4 2026/* [RC 32] Parity register #0 read clear */ 2027#define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0 2028#define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0 2029#define MCPR_IMC_COMMAND_ENABLE (1L<<31) 2030#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16 2031#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28 2032#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8 2033/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2034 * Ethernet header. */ 2035#define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038 2036/* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in 2037 * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be 2038 * disabled when this bit is set. */ 2039#define NIG_REG_P0_HWPFC_ENABLE 0x18078 2040#define NIG_REG_P0_LLH_FUNC_MEM2 0x18480 2041#define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440 2042/* [RW 1] Input enable for RX MAC interface. */ 2043#define NIG_REG_P0_MAC_IN_EN 0x185ac 2044/* [RW 1] Output enable for TX MAC interface */ 2045#define NIG_REG_P0_MAC_OUT_EN 0x185b0 2046/* [RW 1] Output enable for TX PAUSE signal to the MAC. */ 2047#define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4 2048/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for 2049 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the 2050 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit 2051 * priority field is extracted from the outer-most VLAN in receive packet. 2052 * Only COS 0 and COS 1 are supported in E2. */ 2053#define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054 2054/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A 2055 * priority is mapped to COS 0 when the corresponding mask bit is 1. More 2056 * than one bit may be set; allowing multiple priorities to be mapped to one 2057 * COS. */ 2058#define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058 2059/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A 2060 * priority is mapped to COS 1 when the corresponding mask bit is 1. More 2061 * than one bit may be set; allowing multiple priorities to be mapped to one 2062 * COS. */ 2063#define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c 2064/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A 2065 * priority is mapped to COS 2 when the corresponding mask bit is 1. More 2066 * than one bit may be set; allowing multiple priorities to be mapped to one 2067 * COS. */ 2068#define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0 2069/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A 2070 * priority is mapped to COS 3 when the corresponding mask bit is 1. More 2071 * than one bit may be set; allowing multiple priorities to be mapped to one 2072 * COS. */ 2073#define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4 2074/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A 2075 * priority is mapped to COS 4 when the corresponding mask bit is 1. More 2076 * than one bit may be set; allowing multiple priorities to be mapped to one 2077 * COS. */ 2078#define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8 2079/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A 2080 * priority is mapped to COS 5 when the corresponding mask bit is 1. More 2081 * than one bit may be set; allowing multiple priorities to be mapped to one 2082 * COS. */ 2083#define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc 2084/* [R 1] RX FIFO for receiving data from MAC is empty. */ 2085/* [RW 15] Specify which of the credit registers the client is to be mapped 2086 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For 2087 * clients that are not subject to WFQ credit blocking - their 2088 * specifications here are not used. */ 2089#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0 2090/* [RW 32] Specify which of the credit registers the client is to be mapped 2091 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are 2092 * for client 0; bits [35:32] are for client 8. For clients that are not 2093 * subject to WFQ credit blocking - their specifications here are not used. 2094 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2095 * input clients to ETS arbiter. The reset default is set for management and 2096 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2097 * use credit registers 0-5 respectively (0x543210876). Note that credit 2098 * registers can not be shared between clients. */ 2099#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688 2100/* [RW 4] Specify which of the credit registers the client is to be mapped 2101 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are 2102 * for client 0; bits [35:32] are for client 8. For clients that are not 2103 * subject to WFQ credit blocking - their specifications here are not used. 2104 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2105 * input clients to ETS arbiter. The reset default is set for management and 2106 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2107 * use credit registers 0-5 respectively (0x543210876). Note that credit 2108 * registers can not be shared between clients. */ 2109#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c 2110/* [RW 5] Specify whether the client competes directly in the strict 2111 * priority arbiter. The bits are mapped according to client ID (client IDs 2112 * are defined in tx_arb_priority_client). Default value is set to enable 2113 * strict priorities for clients 0-2 -- management and debug traffic. */ 2114#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8 2115/* [RW 5] Specify whether the client is subject to WFQ credit blocking. The 2116 * bits are mapped according to client ID (client IDs are defined in 2117 * tx_arb_priority_client). Default value is 0 for not using WFQ credit 2118 * blocking. */ 2119#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec 2120/* [RW 32] Specify the upper bound that credit register 0 is allowed to 2121 * reach. */ 2122#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c 2123#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110 2124#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114 2125#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118 2126#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c 2127#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0 2128#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4 2129#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8 2130#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac 2131/* [RW 32] Specify the weight (in bytes) to be added to credit register 0 2132 * when it is time to increment. */ 2133#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8 2134#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc 2135#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100 2136#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104 2137#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108 2138#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690 2139#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694 2140#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698 2141#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c 2142/* [RW 12] Specify the number of strict priority arbitration slots between 2143 * two round-robin arbitration slots to avoid starvation. A value of 0 means 2144 * no strict priority cycles - the strict priority with anti-starvation 2145 * arbiter becomes a round-robin arbiter. */ 2146#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4 2147/* [RW 15] Specify the client number to be assigned to each priority of the 2148 * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0] 2149 * are for priority 0 client; bits [14:12] are for priority 4 client. The 2150 * clients are assigned the following IDs: 0-management; 1-debug traffic 2151 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 2152 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000) 2153 * for management at priority 0; debug traffic at priorities 1 and 2; COS0 2154 * traffic at priority 3; and COS1 traffic at priority 4. */ 2155#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4 2156/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2157 * Ethernet header. */ 2158#define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c 2159#define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0 2160#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460 2161/* [RW 32] Specify the client number to be assigned to each priority of the 2162 * strict priority arbiter. This register specifies bits 31:0 of the 36-bit 2163 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2164 * client; bits [35-32] are for priority 8 client. The clients are assigned 2165 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2166 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2167 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2168 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2169 * accommodate the 9 input clients to ETS arbiter. */ 2170#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680 2171/* [RW 4] Specify the client number to be assigned to each priority of the 2172 * strict priority arbiter. This register specifies bits 35:32 of the 36-bit 2173 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2174 * client; bits [35-32] are for priority 8 client. The clients are assigned 2175 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2176 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2177 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2178 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2179 * accommodate the 9 input clients to ETS arbiter. */ 2180#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684 2181#define NIG_REG_P1_HWPFC_ENABLE 0x181d0 2182#define NIG_REG_P1_MAC_IN_EN 0x185c0 2183/* [RW 1] Output enable for TX MAC interface */ 2184#define NIG_REG_P1_MAC_OUT_EN 0x185c4 2185/* [RW 1] Output enable for TX PAUSE signal to the MAC. */ 2186#define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8 2187/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for 2188 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the 2189 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit 2190 * priority field is extracted from the outer-most VLAN in receive packet. 2191 * Only COS 0 and COS 1 are supported in E2. */ 2192#define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8 2193/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A 2194 * priority is mapped to COS 0 when the corresponding mask bit is 1. More 2195 * than one bit may be set; allowing multiple priorities to be mapped to one 2196 * COS. */ 2197#define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac 2198/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A 2199 * priority is mapped to COS 1 when the corresponding mask bit is 1. More 2200 * than one bit may be set; allowing multiple priorities to be mapped to one 2201 * COS. */ 2202#define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0 2203/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A 2204 * priority is mapped to COS 2 when the corresponding mask bit is 1. More 2205 * than one bit may be set; allowing multiple priorities to be mapped to one 2206 * COS. */ 2207#define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8 2208/* [R 1] RX FIFO for receiving data from MAC is empty. */ 2209#define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c 2210/* [R 1] TLLH FIFO is empty. */ 2211#define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338 2212/* [RW 32] Specify which of the credit registers the client is to be mapped 2213 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are 2214 * for client 0; bits [35:32] are for client 8. For clients that are not 2215 * subject to WFQ credit blocking - their specifications here are not used. 2216 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2217 * input clients to ETS arbiter. The reset default is set for management and 2218 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2219 * use credit registers 0-5 respectively (0x543210876). Note that credit 2220 * registers can not be shared between clients. Note also that there are 2221 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only 2222 * credit registers 0-5 are valid. This register should be configured 2223 * appropriately before enabling WFQ. */ 2224#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8 2225/* [RW 4] Specify which of the credit registers the client is to be mapped 2226 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are 2227 * for client 0; bits [35:32] are for client 8. For clients that are not 2228 * subject to WFQ credit blocking - their specifications here are not used. 2229 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2230 * input clients to ETS arbiter. The reset default is set for management and 2231 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2232 * use credit registers 0-5 respectively (0x543210876). Note that credit 2233 * registers can not be shared between clients. Note also that there are 2234 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only 2235 * credit registers 0-5 are valid. This register should be configured 2236 * appropriately before enabling WFQ. */ 2237#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec 2238/* [RW 9] Specify whether the client competes directly in the strict 2239 * priority arbiter. The bits are mapped according to client ID (client IDs 2240 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic 2241 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 2242 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. 2243 * Default value is set to enable strict priorities for all clients. */ 2244#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234 2245/* [RW 9] Specify whether the client is subject to WFQ credit blocking. The 2246 * bits are mapped according to client ID (client IDs are defined in 2247 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port; 2248 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 2249 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is 2250 * 0 for not using WFQ credit blocking. */ 2251#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238 2252#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258 2253#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c 2254#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260 2255#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264 2256#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268 2257#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4 2258/* [RW 32] Specify the weight (in bytes) to be added to credit register 0 2259 * when it is time to increment. */ 2260#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244 2261#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248 2262#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c 2263#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250 2264#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254 2265#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0 2266/* [RW 12] Specify the number of strict priority arbitration slots between 2267 two round-robin arbitration slots to avoid starvation. A value of 0 means 2268 no strict priority cycles - the strict priority with anti-starvation 2269 arbiter becomes a round-robin arbiter. */ 2270#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240 2271/* [RW 32] Specify the client number to be assigned to each priority of the 2272 strict priority arbiter. This register specifies bits 31:0 of the 36-bit 2273 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2274 client; bits [35-32] are for priority 8 client. The clients are assigned 2275 the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2276 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2277 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2278 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2279 accommodate the 9 input clients to ETS arbiter. Note that this register 2280 is the same as the one for port 0, except that port 1 only has COS 0-2 2281 traffic. There is no traffic for COS 3-5 of port 1. */ 2282#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0 2283/* [RW 4] Specify the client number to be assigned to each priority of the 2284 strict priority arbiter. This register specifies bits 35:32 of the 36-bit 2285 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2286 client; bits [35-32] are for priority 8 client. The clients are assigned 2287 the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2288 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2289 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2290 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2291 accommodate the 9 input clients to ETS arbiter. Note that this register 2292 is the same as the one for port 0, except that port 1 only has COS 0-2 2293 traffic. There is no traffic for COS 3-5 of port 1. */ 2294#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4 2295/* [R 1] TX FIFO for transmitting data to MAC is empty. */ 2296#define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594 2297/* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets 2298 forwarded to the host. */ 2299#define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8 2300/* [RW 32] Specify the upper bound that credit register 0 is allowed to 2301 * reach. */ 2302/* [RW 1] Pause enable for port0. This register may get 1 only when 2303 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same 2304 port */ 2305#define NIG_REG_PAUSE_ENABLE_0 0x160c0 2306#define NIG_REG_PAUSE_ENABLE_1 0x160c4 2307/* [RW 1] Input enable for RX PBF LP IF */ 2308#define NIG_REG_PBF_LB_IN_EN 0x100b4 2309/* [RW 1] Value of this register will be transmitted to port swap when 2310 ~nig_registers_strap_override.strap_override =1 */ 2311#define NIG_REG_PORT_SWAP 0x10394 2312/* [RW 1] PPP enable for port0. This register may get 1 only when 2313 * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the 2314 * same port */ 2315#define NIG_REG_PPP_ENABLE_0 0x160b0 2316#define NIG_REG_PPP_ENABLE_1 0x160b4 2317/* [RW 1] output enable for RX parser descriptor IF */ 2318#define NIG_REG_PRS_EOP_OUT_EN 0x10104 2319/* [RW 1] Input enable for RX parser request IF */ 2320#define NIG_REG_PRS_REQ_IN_EN 0x100b8 2321/* [RW 5] control to serdes - CL45 DEVAD */ 2322#define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370 2323/* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */ 2324#define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c 2325/* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */ 2326#define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374 2327/* [R 1] status from serdes0 that inputs to interrupt logic of link status */ 2328#define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578 2329/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 2330 for port0 */ 2331#define NIG_REG_STAT0_BRB_DISCARD 0x105f0 2332/* [R 32] Rx statistics : In user packets truncated due to BRB backpressure 2333 for port0 */ 2334#define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8 2335/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that 2336 between 1024 and 1522 bytes for port0 */ 2337#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750 2338/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that 2339 between 1523 bytes and above for port0 */ 2340#define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760 2341/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 2342 for port1 */ 2343#define NIG_REG_STAT1_BRB_DISCARD 0x10628 2344/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that 2345 between 1024 and 1522 bytes for port1 */ 2346#define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0 2347/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that 2348 between 1523 bytes and above for port1 */ 2349#define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0 2350/* [WB_R 64] Rx statistics : User octets received for LP */ 2351#define NIG_REG_STAT2_BRB_OCTET 0x107e0 2352#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328 2353#define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c 2354/* [RW 1] port swap mux selection. If this register equal to 0 then port 2355 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then 2356 ort swap is equal to ~nig_registers_port_swap.port_swap */ 2357#define NIG_REG_STRAP_OVERRIDE 0x10398 2358/* [RW 1] output enable for RX_XCM0 IF */ 2359#define NIG_REG_XCM0_OUT_EN 0x100f0 2360/* [RW 1] output enable for RX_XCM1 IF */ 2361#define NIG_REG_XCM1_OUT_EN 0x100f4 2362/* [RW 1] control to xgxs - remote PHY in-band MDIO */ 2363#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348 2364/* [RW 5] control to xgxs - CL45 DEVAD */ 2365#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c 2366/* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */ 2367#define NIG_REG_XGXS0_CTRL_MD_ST 0x10338 2368/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */ 2369#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340 2370/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */ 2371#define NIG_REG_XGXS0_STATUS_LINK10G 0x10680 2372/* [R 4] status from xgxs0 that inputs to interrupt logic of link status */ 2373#define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684 2374/* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */ 2375#define NIG_REG_XGXS_LANE_SEL_P0 0x102e8 2376/* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */ 2377#define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0 2378#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0) 2379#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9) 2380#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15) 2381#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18) 2382#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18 2383/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */ 2384#define PBF_REG_COS0_UPPER_BOUND 0x15c05c 2385/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter 2386 * of port 0. */ 2387#define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc 2388/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter 2389 * of port 1. */ 2390#define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4 2391/* [RW 31] The weight of COS0 in the ETS command arbiter. */ 2392#define PBF_REG_COS0_WEIGHT 0x15c054 2393/* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */ 2394#define PBF_REG_COS0_WEIGHT_P0 0x15c2a8 2395/* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */ 2396#define PBF_REG_COS0_WEIGHT_P1 0x15c2c0 2397/* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */ 2398#define PBF_REG_COS1_UPPER_BOUND 0x15c060 2399/* [RW 31] The weight of COS1 in the ETS command arbiter. */ 2400#define PBF_REG_COS1_WEIGHT 0x15c058 2401/* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */ 2402#define PBF_REG_COS1_WEIGHT_P0 0x15c2ac 2403/* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */ 2404#define PBF_REG_COS1_WEIGHT_P1 0x15c2c4 2405/* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */ 2406#define PBF_REG_COS2_WEIGHT_P0 0x15c2b0 2407/* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */ 2408#define PBF_REG_COS2_WEIGHT_P1 0x15c2c8 2409/* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */ 2410#define PBF_REG_COS3_WEIGHT_P0 0x15c2b4 2411/* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */ 2412#define PBF_REG_COS4_WEIGHT_P0 0x15c2b8 2413/* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */ 2414#define PBF_REG_COS5_WEIGHT_P0 0x15c2bc 2415/* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte 2416 * lines. */ 2417#define PBF_REG_CREDIT_LB_Q 0x140338 2418/* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte 2419 * lines. */ 2420#define PBF_REG_CREDIT_Q0 0x14033c 2421/* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte 2422 * lines. */ 2423#define PBF_REG_CREDIT_Q1 0x140340 2424/* [RW 1] Disable processing further tasks from port 0 (after ending the 2425 current task in process). */ 2426#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c 2427/* [RW 1] Disable processing further tasks from port 1 (after ending the 2428 current task in process). */ 2429#define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060 2430/* [RW 1] Disable processing further tasks from port 4 (after ending the 2431 current task in process). */ 2432#define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c 2433#define PBF_REG_DISABLE_PF 0x1402e8 2434/* [RW 18] For port 0: For each client that is subject to WFQ (the 2435 * corresponding bit is 1); indicates to which of the credit registers this 2436 * client is mapped. For clients which are not credit blocked; their mapping 2437 * is dont care. */ 2438#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288 2439/* [RW 9] For port 1: For each client that is subject to WFQ (the 2440 * corresponding bit is 1); indicates to which of the credit registers this 2441 * client is mapped. For clients which are not credit blocked; their mapping 2442 * is dont care. */ 2443#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c 2444/* [RW 6] For port 0: Bit per client to indicate if the client competes in 2445 * the strict priority arbiter directly (corresponding bit = 1); or first 2446 * goes to the RR arbiter (corresponding bit = 0); and then competes in the 2447 * lowest priority in the strict-priority arbiter. */ 2448#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278 2449/* [RW 3] For port 1: Bit per client to indicate if the client competes in 2450 * the strict priority arbiter directly (corresponding bit = 1); or first 2451 * goes to the RR arbiter (corresponding bit = 0); and then competes in the 2452 * lowest priority in the strict-priority arbiter. */ 2453#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c 2454/* [RW 6] For port 0: Bit per client to indicate if the client is subject to 2455 * WFQ credit blocking (corresponding bit = 1). */ 2456#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280 2457/* [RW 3] For port 0: Bit per client to indicate if the client is subject to 2458 * WFQ credit blocking (corresponding bit = 1). */ 2459#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284 2460/* [RW 16] For port 0: The number of strict priority arbitration slots 2461 * between 2 RR arbitration slots. A value of 0 means no strict priority 2462 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR 2463 * arbiter. */ 2464#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0 2465/* [RW 16] For port 1: The number of strict priority arbitration slots 2466 * between 2 RR arbitration slots. A value of 0 means no strict priority 2467 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR 2468 * arbiter. */ 2469#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4 2470/* [RW 18] For port 0: Indicates which client is connected to each priority 2471 * in the strict-priority arbiter. Priority 0 is the highest priority, and 2472 * priority 5 is the lowest; to which the RR output is connected to (this is 2473 * not configurable). */ 2474#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270 2475/* [RW 9] For port 1: Indicates which client is connected to each priority 2476 * in the strict-priority arbiter. Priority 0 is the highest priority, and 2477 * priority 5 is the lowest; to which the RR output is connected to (this is 2478 * not configurable). */ 2479#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274 2480/* [RW 1] Indicates that ETS is performed between the COSes in the command 2481 * arbiter. If reset strict priority w/ anti-starvation will be performed 2482 * w/o WFQ. */ 2483#define PBF_REG_ETS_ENABLED 0x15c050 2484/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2485 * Ethernet header. */ 2486#define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8 2487/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */ 2488#define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8 2489/* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest 2490 * priority in the command arbiter. */ 2491#define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c 2492#define PBF_REG_IF_ENABLE_REG 0x140044 2493/* [RW 1] Init bit. When set the initial credits are copied to the credit 2494 registers (except the port credits). Should be set and then reset after 2495 the configuration of the block has ended. */ 2496#define PBF_REG_INIT 0x140000 2497/* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte 2498 * lines. */ 2499#define PBF_REG_INIT_CRD_LB_Q 0x15c248 2500/* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte 2501 * lines. */ 2502#define PBF_REG_INIT_CRD_Q0 0x15c230 2503/* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte 2504 * lines. */ 2505#define PBF_REG_INIT_CRD_Q1 0x15c234 2506/* [RW 1] Init bit for port 0. When set the initial credit of port 0 is 2507 copied to the credit register. Should be set and then reset after the 2508 configuration of the port has ended. */ 2509#define PBF_REG_INIT_P0 0x140004 2510/* [RW 1] Init bit for port 1. When set the initial credit of port 1 is 2511 copied to the credit register. Should be set and then reset after the 2512 configuration of the port has ended. */ 2513#define PBF_REG_INIT_P1 0x140008 2514/* [RW 1] Init bit for port 4. When set the initial credit of port 4 is 2515 copied to the credit register. Should be set and then reset after the 2516 configuration of the port has ended. */ 2517#define PBF_REG_INIT_P4 0x14000c 2518/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2519 * the LB queue. Reset upon init. */ 2520#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354 2521/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2522 * queue 0. Reset upon init. */ 2523#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358 2524/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2525 * queue 1. Reset upon init. */ 2526#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c 2527/* [RW 1] Enable for mac interface 0. */ 2528#define PBF_REG_MAC_IF0_ENABLE 0x140030 2529/* [RW 1] Enable for mac interface 1. */ 2530#define PBF_REG_MAC_IF1_ENABLE 0x140034 2531/* [RW 1] Enable for the loopback interface. */ 2532#define PBF_REG_MAC_LB_ENABLE 0x140040 2533/* [RW 6] Bit-map indicating which headers must appear in the packet */ 2534#define PBF_REG_MUST_HAVE_HDRS 0x15c0c4 2535/* [RW 16] The number of strict priority arbitration slots between 2 RR 2536 * arbitration slots. A value of 0 means no strict priority cycles; i.e. the 2537 * strict-priority w/ anti-starvation arbiter is a RR arbiter. */ 2538#define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064 2539/* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause 2540 not suppoterd. */ 2541#define PBF_REG_P0_ARB_THRSH 0x1400e4 2542/* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */ 2543#define PBF_REG_P0_CREDIT 0x140200 2544/* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte 2545 lines. */ 2546#define PBF_REG_P0_INIT_CRD 0x1400d0 2547/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2548 * port 0. Reset upon init. */ 2549#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308 2550/* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */ 2551#define PBF_REG_P0_PAUSE_ENABLE 0x140014 2552/* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */ 2553#define PBF_REG_P0_TASK_CNT 0x140204 2554/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2555 * freed from the task queue of port 0. Reset upon init. */ 2556#define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0 2557/* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */ 2558#define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc 2559/* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port 2560 * buffers in 16 byte lines. */ 2561#define PBF_REG_P1_CREDIT 0x140208 2562/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port 2563 * buffers in 16 byte lines. */ 2564#define PBF_REG_P1_INIT_CRD 0x1400d4 2565/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2566 * port 1. Reset upon init. */ 2567#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c 2568/* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */ 2569#define PBF_REG_P1_TASK_CNT 0x14020c 2570/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2571 * freed from the task queue of port 1. Reset upon init. */ 2572#define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4 2573/* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */ 2574#define PBF_REG_P1_TQ_OCCUPANCY 0x140300 2575/* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */ 2576#define PBF_REG_P4_CREDIT 0x140210 2577/* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte 2578 lines. */ 2579#define PBF_REG_P4_INIT_CRD 0x1400e0 2580/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2581 * port 4. Reset upon init. */ 2582#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310 2583/* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */ 2584#define PBF_REG_P4_TASK_CNT 0x140214 2585/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2586 * freed from the task queue of port 4. Reset upon init. */ 2587#define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8 2588/* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */ 2589#define PBF_REG_P4_TQ_OCCUPANCY 0x140304 2590/* [RW 5] Interrupt mask register #0 read/write */ 2591#define PBF_REG_PBF_INT_MASK 0x1401d4 2592/* [R 5] Interrupt register #0 read */ 2593#define PBF_REG_PBF_INT_STS 0x1401c8 2594/* [RW 20] Parity mask register #0 read/write */ 2595#define PBF_REG_PBF_PRTY_MASK 0x1401e4 2596/* [RC 20] Parity register #0 read clear */ 2597#define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc 2598/* [RW 16] The Ethernet type value for L2 tag 0 */ 2599#define PBF_REG_TAG_ETHERTYPE_0 0x15c090 2600/* [RW 4] The length of the info field for L2 tag 0. The length is between 2601 * 2B and 14B; in 2B granularity */ 2602#define PBF_REG_TAG_LEN_0 0x15c09c 2603/* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task 2604 * queue. Reset upon init. */ 2605#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c 2606/* [R 32] Cyclic counter for number of 8 byte lines freed from the task 2607 * queue 0. Reset upon init. */ 2608#define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390 2609/* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1. 2610 * Reset upon init. */ 2611#define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394 2612/* [R 13] Number of 8 bytes lines occupied in the task queue of the LB 2613 * queue. */ 2614#define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8 2615/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */ 2616#define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac 2617/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */ 2618#define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0 2619#define PB_REG_CONTROL 0 2620/* [RW 2] Interrupt mask register #0 read/write */ 2621#define PB_REG_PB_INT_MASK 0x28 2622/* [R 2] Interrupt register #0 read */ 2623#define PB_REG_PB_INT_STS 0x1c 2624/* [RW 4] Parity mask register #0 read/write */ 2625#define PB_REG_PB_PRTY_MASK 0x38 2626/* [R 4] Parity register #0 read */ 2627#define PB_REG_PB_PRTY_STS 0x2c 2628/* [RC 4] Parity register #0 read clear */ 2629#define PB_REG_PB_PRTY_STS_CLR 0x30 2630#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 2631#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8) 2632#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1) 2633#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6) 2634#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7) 2635#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4) 2636#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3) 2637#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5) 2638#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2) 2639/* [R 8] Config space A attention dirty bits. Each bit indicates that the 2640 * corresponding PF generates config space A attention. Set by PXP. Reset by 2641 * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits 2642 * from both paths. */ 2643#define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010 2644/* [R 8] Config space B attention dirty bits. Each bit indicates that the 2645 * corresponding PF generates config space B attention. Set by PXP. Reset by 2646 * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits 2647 * from both paths. */ 2648#define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014 2649/* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1 2650 * - enable. */ 2651#define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194 2652/* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask; 2653 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */ 2654#define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c 2655/* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1 2656 * - enable. */ 2657#define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c 2658/* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */ 2659#define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100 2660/* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */ 2661#define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108 2662/* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */ 2663#define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110 2664/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 2665#define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac 2666/* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates 2667 * that the FLR register of the corresponding PF was set. Set by PXP. Reset 2668 * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits 2669 * from both paths. */ 2670#define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028 2671/* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1 2672 * to a bit in this register in order to clear the corresponding bit in 2673 * flr_request_pf_7_0 register. Note: register contains bits from both 2674 * paths. */ 2675#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418 2676/* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit 2677 * indicates that the FLR register of the corresponding VF was set. Set by 2678 * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */ 2679#define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024 2680/* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit 2681 * indicates that the FLR register of the corresponding VF was set. Set by 2682 * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */ 2683#define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018 2684/* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit 2685 * indicates that the FLR register of the corresponding VF was set. Set by 2686 * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */ 2687#define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c 2688/* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit 2689 * indicates that the FLR register of the corresponding VF was set. Set by 2690 * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */ 2691#define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020 2692/* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit 2693 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target 2694 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW 2695 * arrived with a correctable error. Bit 3 - Configuration RW arrived with 2696 * an uncorrectable error. Bit 4 - Completion with Configuration Request 2697 * Retry Status. Bit 5 - Expansion ROM access received with a write request. 2698 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and 2699 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010; 2700 * and pcie_rx_last not asserted. */ 2701#define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068 2702#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c 2703#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430 2704#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434 2705#define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438 2706/* [R 9] Interrupt register #0 read */ 2707#define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298 2708/* [RC 9] Interrupt register #0 read clear */ 2709#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c 2710/* [RW 2] Parity mask register #0 read/write */ 2711#define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4 2712/* [R 2] Parity register #0 read */ 2713#define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8 2714/* [RC 2] Parity register #0 read clear */ 2715#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac 2716/* [R 13] Details of first request received with error. [2:0] - PFID. [3] - 2717 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion 2718 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 - 2719 * completer abort. 3 - Illegal value for this field. [12] valid - indicates 2720 * if there was a completion error since the last time this register was 2721 * cleared. */ 2722#define PGLUE_B_REG_RX_ERR_DETAILS 0x9080 2723/* [R 18] Details of first ATS Translation Completion request received with 2724 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code - 2725 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 - 2726 * unsupported request. 2 - completer abort. 3 - Illegal value for this 2727 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a 2728 * completion error since the last time this register was cleared. */ 2729#define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084 2730/* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to 2731 * a bit in this register in order to clear the corresponding bit in 2732 * shadow_bme_pf_7_0 register. MCP should never use this unless a 2733 * work-around is needed. Note: register contains bits from both paths. */ 2734#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458 2735/* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the 2736 * VF enable register of the corresponding PF is written to 0 and was 2737 * previously 1. Set by PXP. Reset by MCP writing 1 to 2738 * sr_iov_disabled_request_clr. Note: register contains bits from both 2739 * paths. */ 2740#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030 2741/* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read 2742 * completion did not return yet. 1 - tag is unused. Same functionality as 2743 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */ 2744#define PGLUE_B_REG_TAGS_63_32 0x9244 2745/* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1 2746 * - enable. */ 2747#define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170 2748/* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */ 2749#define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4 2750/* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */ 2751#define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc 2752/* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */ 2753#define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4 2754/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 2755#define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0 2756/* [R 32] Address [31:0] of first read request not submitted due to error */ 2757#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098 2758/* [R 32] Address [63:32] of first read request not submitted due to error */ 2759#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c 2760/* [R 31] Details of first read request not submitted due to error. [4:0] 2761 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. 2762 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] - 2763 * VFID. */ 2764#define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0 2765/* [R 26] Details of first read request not submitted due to error. [15:0] 2766 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type - 2767 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared; 2768 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent 2769 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid - 2770 * indicates if there was a request not submitted due to error since the 2771 * last time this register was cleared. */ 2772#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4 2773/* [R 32] Address [31:0] of first write request not submitted due to error */ 2774#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088 2775/* [R 32] Address [63:32] of first write request not submitted due to error */ 2776#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c 2777/* [R 31] Details of first write request not submitted due to error. [4:0] 2778 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] 2779 * - VFID. */ 2780#define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090 2781/* [R 26] Details of first write request not submitted due to error. [15:0] 2782 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type - 2783 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared; 2784 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent 2785 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid - 2786 * indicates if there was a request not submitted due to error since the 2787 * last time this register was cleared. */ 2788#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094 2789/* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask; 2790 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any 2791 * value (Byte resolution address). */ 2792#define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128 2793#define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c 2794#define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130 2795#define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134 2796#define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138 2797#define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c 2798#define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140 2799/* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1 2800 * - enable. */ 2801#define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c 2802/* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1 2803 * - enable. */ 2804#define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180 2805/* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1 2806 * - enable. */ 2807#define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184 2808/* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */ 2809#define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8 2810/* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */ 2811#define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0 2812/* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */ 2813#define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8 2814/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 2815#define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4 2816/* [R 26] Details of first target VF request accessing VF GRC space that 2817 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write. 2818 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a 2819 * request accessing VF GRC space that failed permission check since the 2820 * last time this register was cleared. Permission checks are: function 2821 * permission; R/W permission; address range permission. */ 2822#define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234 2823/* [R 31] Details of first target VF request with length violation (too many 2824 * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address). 2825 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30] 2826 * valid - indicates if there was a request with length violation since the 2827 * last time this register was cleared. Length violations: length of more 2828 * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and 2829 * length is more than 1 DW. */ 2830#define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230 2831/* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates 2832 * that there was a completion with uncorrectable error for the 2833 * corresponding PF. Set by PXP. Reset by MCP writing 1 to 2834 * was_error_pf_7_0_clr. */ 2835#define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c 2836/* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1 2837 * to a bit in this register in order to clear the corresponding bit in 2838 * flr_request_pf_7_0 register. */ 2839#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470 2840/* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit 2841 * indicates that there was a completion with uncorrectable error for the 2842 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2843 * was_error_vf_127_96_clr. */ 2844#define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078 2845/* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP 2846 * writes 1 to a bit in this register in order to clear the corresponding 2847 * bit in was_error_vf_127_96 register. */ 2848#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474 2849/* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit 2850 * indicates that there was a completion with uncorrectable error for the 2851 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2852 * was_error_vf_31_0_clr. */ 2853#define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c 2854/* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes 2855 * 1 to a bit in this register in order to clear the corresponding bit in 2856 * was_error_vf_31_0 register. */ 2857#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478 2858/* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit 2859 * indicates that there was a completion with uncorrectable error for the 2860 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2861 * was_error_vf_63_32_clr. */ 2862#define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070 2863/* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes 2864 * 1 to a bit in this register in order to clear the corresponding bit in 2865 * was_error_vf_63_32 register. */ 2866#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c 2867/* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit 2868 * indicates that there was a completion with uncorrectable error for the 2869 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2870 * was_error_vf_95_64_clr. */ 2871#define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074 2872/* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes 2873 * 1 to a bit in this register in order to clear the corresponding bit in 2874 * was_error_vf_95_64 register. */ 2875#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480 2876/* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1 2877 * - enable. */ 2878#define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188 2879/* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */ 2880#define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec 2881/* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */ 2882#define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4 2883/* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */ 2884#define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc 2885/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 2886#define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8 2887#define PRS_REG_A_PRSU_20 0x40134 2888/* [R 8] debug only: CFC load request current credit. Transaction based. */ 2889#define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164 2890/* [R 8] debug only: CFC search request current credit. Transaction based. */ 2891#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168 2892/* [RW 6] The initial credit for the search message to the CFC interface. 2893 Credit is transaction based. */ 2894#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c 2895/* [RW 24] CID for port 0 if no match */ 2896#define PRS_REG_CID_PORT_0 0x400fc 2897/* [RW 32] The CM header for flush message where 'load existed' bit in CFC 2898 load response is reset and packet type is 0. Used in packet start message 2899 to TCM. */ 2900#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc 2901#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0 2902#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4 2903#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8 2904#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec 2905#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0 2906/* [RW 32] The CM header for flush message where 'load existed' bit in CFC 2907 load response is set and packet type is 0. Used in packet start message 2908 to TCM. */ 2909#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc 2910#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0 2911#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4 2912#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8 2913#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc 2914#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0 2915/* [RW 32] The CM header for a match and packet type 1 for loopback port. 2916 Used in packet start message to TCM. */ 2917#define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c 2918#define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0 2919#define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4 2920#define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8 2921/* [RW 32] The CM header for a match and packet type 0. Used in packet start 2922 message to TCM. */ 2923#define PRS_REG_CM_HDR_TYPE_0 0x40078 2924#define PRS_REG_CM_HDR_TYPE_1 0x4007c 2925#define PRS_REG_CM_HDR_TYPE_2 0x40080 2926#define PRS_REG_CM_HDR_TYPE_3 0x40084 2927#define PRS_REG_CM_HDR_TYPE_4 0x40088 2928/* [RW 32] The CM header in case there was not a match on the connection */ 2929#define PRS_REG_CM_NO_MATCH_HDR 0x400b8 2930/* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */ 2931#define PRS_REG_E1HOV_MODE 0x401c8 2932/* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet 2933 start message to TCM. */ 2934#define PRS_REG_EVENT_ID_1 0x40054 2935#define PRS_REG_EVENT_ID_2 0x40058 2936#define PRS_REG_EVENT_ID_3 0x4005c 2937/* [RW 16] The Ethernet type value for FCoE */ 2938#define PRS_REG_FCOE_TYPE 0x401d0 2939/* [RW 8] Context region for flush packet with packet type 0. Used in CFC 2940 load request message. */ 2941#define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004 2942#define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008 2943#define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c 2944#define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010 2945#define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014 2946#define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018 2947#define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c 2948#define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020 2949/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2950 * Ethernet header. */ 2951#define PRS_REG_HDRS_AFTER_BASIC 0x40238 2952/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2953 * Ethernet header for port 0 packets. */ 2954#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270 2955#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290 2956/* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */ 2957#define PRS_REG_HDRS_AFTER_TAG_0 0x40248 2958/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for 2959 * port 0 packets */ 2960#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280 2961#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0 2962/* [RW 4] The increment value to send in the CFC load request message */ 2963#define PRS_REG_INC_VALUE 0x40048 2964/* [RW 6] Bit-map indicating which headers must appear in the packet */ 2965#define PRS_REG_MUST_HAVE_HDRS 0x40254 2966/* [RW 6] Bit-map indicating which headers must appear in the packet for 2967 * port 0 packets */ 2968#define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c 2969#define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac 2970#define PRS_REG_NIC_MODE 0x40138 2971/* [RW 8] The 8-bit event ID for cases where there is no match on the 2972 connection. Used in packet start message to TCM. */ 2973#define PRS_REG_NO_MATCH_EVENT_ID 0x40070 2974/* [ST 24] The number of input CFC flush packets */ 2975#define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128 2976/* [ST 32] The number of cycles the Parser halted its operation since it 2977 could not allocate the next serial number */ 2978#define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130 2979/* [ST 24] The number of input packets */ 2980#define PRS_REG_NUM_OF_PACKETS 0x40124 2981/* [ST 24] The number of input transparent flush packets */ 2982#define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c 2983/* [RW 8] Context region for received Ethernet packet with a match and 2984 packet type 0. Used in CFC load request message */ 2985#define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028 2986#define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c 2987#define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030 2988#define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034 2989#define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038 2990#define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c 2991#define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040 2992#define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044 2993/* [R 2] debug only: Number of pending requests for CAC on port 0. */ 2994#define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174 2995/* [R 2] debug only: Number of pending requests for header parsing. */ 2996#define PRS_REG_PENDING_BRB_PRS_RQ 0x40170 2997/* [R 1] Interrupt register #0 read */ 2998#define PRS_REG_PRS_INT_STS 0x40188 2999/* [RW 8] Parity mask register #0 read/write */ 3000#define PRS_REG_PRS_PRTY_MASK 0x401a4 3001/* [R 8] Parity register #0 read */ 3002#define PRS_REG_PRS_PRTY_STS 0x40198 3003/* [RC 8] Parity register #0 read clear */ 3004#define PRS_REG_PRS_PRTY_STS_CLR 0x4019c 3005/* [RW 8] Context region for pure acknowledge packets. Used in CFC load 3006 request message */ 3007#define PRS_REG_PURE_REGIONS 0x40024 3008/* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this 3009 serail number was released by SDM but cannot be used because a previous 3010 serial number was not released. */ 3011#define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154 3012/* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this 3013 serail number was released by SDM but cannot be used because a previous 3014 serial number was not released. */ 3015#define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158 3016/* [R 4] debug only: SRC current credit. Transaction based. */ 3017#define PRS_REG_SRC_CURRENT_CREDIT 0x4016c 3018/* [RW 16] The Ethernet type value for L2 tag 0 */ 3019#define PRS_REG_TAG_ETHERTYPE_0 0x401d4 3020/* [RW 4] The length of the info field for L2 tag 0. The length is between 3021 * 2B and 14B; in 2B granularity */ 3022#define PRS_REG_TAG_LEN_0 0x4022c 3023/* [R 8] debug only: TCM current credit. Cycle based. */ 3024#define PRS_REG_TCM_CURRENT_CREDIT 0x40160 3025/* [R 8] debug only: TSDM current credit. Transaction based. */ 3026#define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c 3027#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19) 3028#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20) 3029#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22) 3030#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23) 3031#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24) 3032#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7) 3033#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7) 3034/* [R 6] Debug only: Number of used entries in the data FIFO */ 3035#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c 3036/* [R 7] Debug only: Number of used entries in the header FIFO */ 3037#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478 3038#define PXP2_REG_PGL_ADDR_88_F0 0x120534 3039/* [R 32] GRC address for configuration access to PCIE config address 0x88. 3040 * any write to this PCIE address will cause a GRC write access to the 3041 * address that's in t this register */ 3042#define PXP2_REG_PGL_ADDR_88_F1 0x120544 3043#define PXP2_REG_PGL_ADDR_8C_F0 0x120538 3044/* [R 32] GRC address for configuration access to PCIE config address 0x8c. 3045 * any write to this PCIE address will cause a GRC write access to the 3046 * address that's in t this register */ 3047#define PXP2_REG_PGL_ADDR_8C_F1 0x120548 3048#define PXP2_REG_PGL_ADDR_90_F0 0x12053c 3049/* [R 32] GRC address for configuration access to PCIE config address 0x90. 3050 * any write to this PCIE address will cause a GRC write access to the 3051 * address that's in t this register */ 3052#define PXP2_REG_PGL_ADDR_90_F1 0x12054c 3053#define PXP2_REG_PGL_ADDR_94_F0 0x120540 3054/* [R 32] GRC address for configuration access to PCIE config address 0x94. 3055 * any write to this PCIE address will cause a GRC write access to the 3056 * address that's in t this register */ 3057#define PXP2_REG_PGL_ADDR_94_F1 0x120550 3058#define PXP2_REG_PGL_CONTROL0 0x120490 3059#define PXP2_REG_PGL_CONTROL1 0x120514 3060#define PXP2_REG_PGL_DEBUG 0x120520 3061/* [RW 32] third dword data of expansion rom request. this register is 3062 special. reading from it provides a vector outstanding read requests. if 3063 a bit is zero it means that a read request on the corresponding tag did 3064 not finish yet (not all completions have arrived for it) */ 3065#define PXP2_REG_PGL_EXP_ROM2 0x120808 3066/* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask; 3067 its[15:0]-address */ 3068#define PXP2_REG_PGL_INT_CSDM_0 0x1204f4 3069#define PXP2_REG_PGL_INT_CSDM_1 0x1204f8 3070#define PXP2_REG_PGL_INT_CSDM_2 0x1204fc 3071#define PXP2_REG_PGL_INT_CSDM_3 0x120500 3072#define PXP2_REG_PGL_INT_CSDM_4 0x120504 3073#define PXP2_REG_PGL_INT_CSDM_5 0x120508 3074#define PXP2_REG_PGL_INT_CSDM_6 0x12050c 3075#define PXP2_REG_PGL_INT_CSDM_7 0x120510 3076/* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask; 3077 its[15:0]-address */ 3078#define PXP2_REG_PGL_INT_TSDM_0 0x120494 3079#define PXP2_REG_PGL_INT_TSDM_1 0x120498 3080#define PXP2_REG_PGL_INT_TSDM_2 0x12049c 3081#define PXP2_REG_PGL_INT_TSDM_3 0x1204a0 3082#define PXP2_REG_PGL_INT_TSDM_4 0x1204a4 3083#define PXP2_REG_PGL_INT_TSDM_5 0x1204a8 3084#define PXP2_REG_PGL_INT_TSDM_6 0x1204ac 3085#define PXP2_REG_PGL_INT_TSDM_7 0x1204b0 3086/* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask; 3087 its[15:0]-address */ 3088#define PXP2_REG_PGL_INT_USDM_0 0x1204b4 3089#define PXP2_REG_PGL_INT_USDM_1 0x1204b8 3090#define PXP2_REG_PGL_INT_USDM_2 0x1204bc 3091#define PXP2_REG_PGL_INT_USDM_3 0x1204c0 3092#define PXP2_REG_PGL_INT_USDM_4 0x1204c4 3093#define PXP2_REG_PGL_INT_USDM_5 0x1204c8 3094#define PXP2_REG_PGL_INT_USDM_6 0x1204cc 3095#define PXP2_REG_PGL_INT_USDM_7 0x1204d0 3096/* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask; 3097 its[15:0]-address */ 3098#define PXP2_REG_PGL_INT_XSDM_0 0x1204d4 3099#define PXP2_REG_PGL_INT_XSDM_1 0x1204d8 3100#define PXP2_REG_PGL_INT_XSDM_2 0x1204dc 3101#define PXP2_REG_PGL_INT_XSDM_3 0x1204e0 3102#define PXP2_REG_PGL_INT_XSDM_4 0x1204e4 3103#define PXP2_REG_PGL_INT_XSDM_5 0x1204e8 3104#define PXP2_REG_PGL_INT_XSDM_6 0x1204ec 3105#define PXP2_REG_PGL_INT_XSDM_7 0x1204f0 3106/* [RW 3] this field allows one function to pretend being another function 3107 when accessing any BAR mapped resource within the device. the value of 3108 the field is the number of the function that will be accessed 3109 effectively. after software write to this bit it must read it in order to 3110 know that the new value is updated */ 3111#define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674 3112#define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678 3113#define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c 3114#define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680 3115#define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684 3116#define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688 3117#define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c 3118#define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690 3119/* [R 1] this bit indicates that a read request was blocked because of 3120 bus_master_en was deasserted */ 3121#define PXP2_REG_PGL_READ_BLOCKED 0x120568 3122#define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8 3123/* [R 18] debug only */ 3124#define PXP2_REG_PGL_TXW_CDTS 0x12052c 3125/* [R 1] this bit indicates that a write request was blocked because of 3126 bus_master_en was deasserted */ 3127#define PXP2_REG_PGL_WRITE_BLOCKED 0x120564 3128#define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0 3129#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4 3130#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8 3131#define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4 3132#define PXP2_REG_PSWRQ_BW_ADD28 0x120228 3133#define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8 3134#define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4 3135#define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8 3136#define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc 3137#define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0 3138#define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c 3139#define PXP2_REG_PSWRQ_BW_L1 0x1202b0 3140#define PXP2_REG_PSWRQ_BW_L10 0x1202d4 3141#define PXP2_REG_PSWRQ_BW_L11 0x1202d8 3142#define PXP2_REG_PSWRQ_BW_L2 0x1202b4 3143#define PXP2_REG_PSWRQ_BW_L28 0x120318 3144#define PXP2_REG_PSWRQ_BW_L3 0x1202b8 3145#define PXP2_REG_PSWRQ_BW_L6 0x1202c4 3146#define PXP2_REG_PSWRQ_BW_L7 0x1202c8 3147#define PXP2_REG_PSWRQ_BW_L8 0x1202cc 3148#define PXP2_REG_PSWRQ_BW_L9 0x1202d0 3149#define PXP2_REG_PSWRQ_BW_RD 0x120324 3150#define PXP2_REG_PSWRQ_BW_UB1 0x120238 3151#define PXP2_REG_PSWRQ_BW_UB10 0x12025c 3152#define PXP2_REG_PSWRQ_BW_UB11 0x120260 3153#define PXP2_REG_PSWRQ_BW_UB2 0x12023c 3154#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0 3155#define PXP2_REG_PSWRQ_BW_UB3 0x120240 3156#define PXP2_REG_PSWRQ_BW_UB6 0x12024c 3157#define PXP2_REG_PSWRQ_BW_UB7 0x120250 3158#define PXP2_REG_PSWRQ_BW_UB8 0x120254 3159#define PXP2_REG_PSWRQ_BW_UB9 0x120258 3160#define PXP2_REG_PSWRQ_BW_WR 0x120328 3161#define PXP2_REG_PSWRQ_CDU0_L2P 0x120000 3162#define PXP2_REG_PSWRQ_QM0_L2P 0x120038 3163#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054 3164#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c 3165#define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0 3166/* [RW 32] Interrupt mask register #0 read/write */ 3167#define PXP2_REG_PXP2_INT_MASK_0 0x120578 3168/* [R 32] Interrupt register #0 read */ 3169#define PXP2_REG_PXP2_INT_STS_0 0x12056c 3170#define PXP2_REG_PXP2_INT_STS_1 0x120608 3171/* [RC 32] Interrupt register #0 read clear */ 3172#define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570 3173/* [RW 32] Parity mask register #0 read/write */ 3174#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588 3175#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598 3176/* [R 32] Parity register #0 read */ 3177#define PXP2_REG_PXP2_PRTY_STS_0 0x12057c 3178#define PXP2_REG_PXP2_PRTY_STS_1 0x12058c 3179/* [RC 32] Parity register #0 read clear */ 3180#define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580 3181#define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590 3182/* [R 1] Debug only: The 'almost full' indication from each fifo (gives 3183 indication about backpressure) */ 3184#define PXP2_REG_RD_ALMOST_FULL_0 0x120424 3185/* [R 8] Debug only: The blocks counter - number of unused block ids */ 3186#define PXP2_REG_RD_BLK_CNT 0x120418 3187/* [RW 8] Debug only: Total number of available blocks in Tetris Buffer. 3188 Must be bigger than 6. Normally should not be changed. */ 3189#define PXP2_REG_RD_BLK_NUM_CFG 0x12040c 3190/* [RW 2] CDU byte swapping mode configuration for master read requests */ 3191#define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404 3192/* [RW 1] When '1'; inputs to the PSWRD block are ignored */ 3193#define PXP2_REG_RD_DISABLE_INPUTS 0x120374 3194/* [R 1] PSWRD internal memories initialization is done */ 3195#define PXP2_REG_RD_INIT_DONE 0x120370 3196/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3197 allocated for vq10 */ 3198#define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0 3199/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3200 allocated for vq11 */ 3201#define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4 3202/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3203 allocated for vq17 */ 3204#define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc 3205/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3206 allocated for vq18 */ 3207#define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0 3208/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3209 allocated for vq19 */ 3210#define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4 3211/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3212 allocated for vq22 */ 3213#define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0 3214/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3215 allocated for vq25 */ 3216#define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc 3217/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3218 allocated for vq6 */ 3219#define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390 3220/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3221 allocated for vq9 */ 3222#define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c 3223/* [RW 2] PBF byte swapping mode configuration for master read requests */ 3224#define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4 3225/* [R 1] Debug only: Indication if delivery ports are idle */ 3226#define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c 3227#define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420 3228/* [RW 2] QM byte swapping mode configuration for master read requests */ 3229#define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8 3230/* [R 7] Debug only: The SR counter - number of unused sub request ids */ 3231#define PXP2_REG_RD_SR_CNT 0x120414 3232/* [RW 2] SRC byte swapping mode configuration for master read requests */ 3233#define PXP2_REG_RD_SRC_SWAP_MODE 0x120400 3234/* [RW 7] Debug only: Total number of available PCI read sub-requests. Must 3235 be bigger than 1. Normally should not be changed. */ 3236#define PXP2_REG_RD_SR_NUM_CFG 0x120408 3237/* [RW 1] Signals the PSWRD block to start initializing internal memories */ 3238#define PXP2_REG_RD_START_INIT 0x12036c 3239/* [RW 2] TM byte swapping mode configuration for master read requests */ 3240#define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc 3241/* [RW 10] Bandwidth addition to VQ0 write requests */ 3242#define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc 3243/* [RW 10] Bandwidth addition to VQ12 read requests */ 3244#define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec 3245/* [RW 10] Bandwidth addition to VQ13 read requests */ 3246#define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0 3247/* [RW 10] Bandwidth addition to VQ14 read requests */ 3248#define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4 3249/* [RW 10] Bandwidth addition to VQ15 read requests */ 3250#define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8 3251/* [RW 10] Bandwidth addition to VQ16 read requests */ 3252#define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc 3253/* [RW 10] Bandwidth addition to VQ17 read requests */ 3254#define PXP2_REG_RQ_BW_RD_ADD17 0x120200 3255/* [RW 10] Bandwidth addition to VQ18 read requests */ 3256#define PXP2_REG_RQ_BW_RD_ADD18 0x120204 3257/* [RW 10] Bandwidth addition to VQ19 read requests */ 3258#define PXP2_REG_RQ_BW_RD_ADD19 0x120208 3259/* [RW 10] Bandwidth addition to VQ20 read requests */ 3260#define PXP2_REG_RQ_BW_RD_ADD20 0x12020c 3261/* [RW 10] Bandwidth addition to VQ22 read requests */ 3262#define PXP2_REG_RQ_BW_RD_ADD22 0x120210 3263/* [RW 10] Bandwidth addition to VQ23 read requests */ 3264#define PXP2_REG_RQ_BW_RD_ADD23 0x120214 3265/* [RW 10] Bandwidth addition to VQ24 read requests */ 3266#define PXP2_REG_RQ_BW_RD_ADD24 0x120218 3267/* [RW 10] Bandwidth addition to VQ25 read requests */ 3268#define PXP2_REG_RQ_BW_RD_ADD25 0x12021c 3269/* [RW 10] Bandwidth addition to VQ26 read requests */ 3270#define PXP2_REG_RQ_BW_RD_ADD26 0x120220 3271/* [RW 10] Bandwidth addition to VQ27 read requests */ 3272#define PXP2_REG_RQ_BW_RD_ADD27 0x120224 3273/* [RW 10] Bandwidth addition to VQ4 read requests */ 3274#define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc 3275/* [RW 10] Bandwidth addition to VQ5 read requests */ 3276#define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0 3277/* [RW 10] Bandwidth Typical L for VQ0 Read requests */ 3278#define PXP2_REG_RQ_BW_RD_L0 0x1202ac 3279/* [RW 10] Bandwidth Typical L for VQ12 Read requests */ 3280#define PXP2_REG_RQ_BW_RD_L12 0x1202dc 3281/* [RW 10] Bandwidth Typical L for VQ13 Read requests */ 3282#define PXP2_REG_RQ_BW_RD_L13 0x1202e0 3283/* [RW 10] Bandwidth Typical L for VQ14 Read requests */ 3284#define PXP2_REG_RQ_BW_RD_L14 0x1202e4 3285/* [RW 10] Bandwidth Typical L for VQ15 Read requests */ 3286#define PXP2_REG_RQ_BW_RD_L15 0x1202e8 3287/* [RW 10] Bandwidth Typical L for VQ16 Read requests */ 3288#define PXP2_REG_RQ_BW_RD_L16 0x1202ec 3289/* [RW 10] Bandwidth Typical L for VQ17 Read requests */ 3290#define PXP2_REG_RQ_BW_RD_L17 0x1202f0 3291/* [RW 10] Bandwidth Typical L for VQ18 Read requests */ 3292#define PXP2_REG_RQ_BW_RD_L18 0x1202f4 3293/* [RW 10] Bandwidth Typical L for VQ19 Read requests */ 3294#define PXP2_REG_RQ_BW_RD_L19 0x1202f8 3295/* [RW 10] Bandwidth Typical L for VQ20 Read requests */ 3296#define PXP2_REG_RQ_BW_RD_L20 0x1202fc 3297/* [RW 10] Bandwidth Typical L for VQ22 Read requests */ 3298#define PXP2_REG_RQ_BW_RD_L22 0x120300 3299/* [RW 10] Bandwidth Typical L for VQ23 Read requests */ 3300#define PXP2_REG_RQ_BW_RD_L23 0x120304 3301/* [RW 10] Bandwidth Typical L for VQ24 Read requests */ 3302#define PXP2_REG_RQ_BW_RD_L24 0x120308 3303/* [RW 10] Bandwidth Typical L for VQ25 Read requests */ 3304#define PXP2_REG_RQ_BW_RD_L25 0x12030c 3305/* [RW 10] Bandwidth Typical L for VQ26 Read requests */ 3306#define PXP2_REG_RQ_BW_RD_L26 0x120310 3307/* [RW 10] Bandwidth Typical L for VQ27 Read requests */ 3308#define PXP2_REG_RQ_BW_RD_L27 0x120314 3309/* [RW 10] Bandwidth Typical L for VQ4 Read requests */ 3310#define PXP2_REG_RQ_BW_RD_L4 0x1202bc 3311/* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */ 3312#define PXP2_REG_RQ_BW_RD_L5 0x1202c0 3313/* [RW 7] Bandwidth upper bound for VQ0 read requests */ 3314#define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234 3315/* [RW 7] Bandwidth upper bound for VQ12 read requests */ 3316#define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264 3317/* [RW 7] Bandwidth upper bound for VQ13 read requests */ 3318#define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268 3319/* [RW 7] Bandwidth upper bound for VQ14 read requests */ 3320#define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c 3321/* [RW 7] Bandwidth upper bound for VQ15 read requests */ 3322#define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270 3323/* [RW 7] Bandwidth upper bound for VQ16 read requests */ 3324#define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274 3325/* [RW 7] Bandwidth upper bound for VQ17 read requests */ 3326#define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278 3327/* [RW 7] Bandwidth upper bound for VQ18 read requests */ 3328#define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c 3329/* [RW 7] Bandwidth upper bound for VQ19 read requests */ 3330#define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280 3331/* [RW 7] Bandwidth upper bound for VQ20 read requests */ 3332#define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284 3333/* [RW 7] Bandwidth upper bound for VQ22 read requests */ 3334#define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288 3335/* [RW 7] Bandwidth upper bound for VQ23 read requests */ 3336#define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c 3337/* [RW 7] Bandwidth upper bound for VQ24 read requests */ 3338#define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290 3339/* [RW 7] Bandwidth upper bound for VQ25 read requests */ 3340#define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294 3341/* [RW 7] Bandwidth upper bound for VQ26 read requests */ 3342#define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298 3343/* [RW 7] Bandwidth upper bound for VQ27 read requests */ 3344#define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c 3345/* [RW 7] Bandwidth upper bound for VQ4 read requests */ 3346#define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244 3347/* [RW 7] Bandwidth upper bound for VQ5 read requests */ 3348#define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248 3349/* [RW 10] Bandwidth addition to VQ29 write requests */ 3350#define PXP2_REG_RQ_BW_WR_ADD29 0x12022c 3351/* [RW 10] Bandwidth addition to VQ30 write requests */ 3352#define PXP2_REG_RQ_BW_WR_ADD30 0x120230 3353/* [RW 10] Bandwidth Typical L for VQ29 Write requests */ 3354#define PXP2_REG_RQ_BW_WR_L29 0x12031c 3355/* [RW 10] Bandwidth Typical L for VQ30 Write requests */ 3356#define PXP2_REG_RQ_BW_WR_L30 0x120320 3357/* [RW 7] Bandwidth upper bound for VQ29 */ 3358#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4 3359/* [RW 7] Bandwidth upper bound for VQ30 */ 3360#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8 3361/* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */ 3362#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008 3363/* [RW 2] Endian mode for cdu */ 3364#define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0 3365#define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c 3366#define PXP2_REG_RQ_CDU_LAST_ILT 0x120620 3367/* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k; 3368 -128k */ 3369#define PXP2_REG_RQ_CDU_P_SIZE 0x120018 3370/* [R 1] 1' indicates that the requester has finished its internal 3371 configuration */ 3372#define PXP2_REG_RQ_CFG_DONE 0x1201b4 3373/* [RW 2] Endian mode for debug */ 3374#define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4 3375/* [RW 1] When '1'; requests will enter input buffers but wont get out 3376 towards the glue */ 3377#define PXP2_REG_RQ_DISABLE_INPUTS 0x120330 3378/* [RW 4] Determines alignment of write SRs when a request is split into 3379 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B 3380 * aligned. 4 - 512B aligned. */ 3381#define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0 3382/* [RW 4] Determines alignment of read SRs when a request is split into 3383 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B 3384 * aligned. 4 - 512B aligned. */ 3385#define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c 3386/* [RW 1] when set the new alignment method (E2) will be applied; when reset 3387 * the original alignment method (E1 E1H) will be applied */ 3388#define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930 3389/* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will 3390 be asserted */ 3391#define PXP2_REG_RQ_ELT_DISABLE 0x12066c 3392/* [RW 2] Endian mode for hc */ 3393#define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8 3394/* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back 3395 compatibility needs; Note that different registers are used per mode */ 3396#define PXP2_REG_RQ_ILT_MODE 0x1205b4 3397/* [WB 53] Onchip address table */ 3398#define PXP2_REG_RQ_ONCHIP_AT 0x122000 3399/* [WB 53] Onchip address table - B0 */ 3400#define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000 3401/* [RW 13] Pending read limiter threshold; in Dwords */ 3402#define PXP2_REG_RQ_PDR_LIMIT 0x12033c 3403/* [RW 2] Endian mode for qm */ 3404#define PXP2_REG_RQ_QM_ENDIAN_M 0x120194 3405#define PXP2_REG_RQ_QM_FIRST_ILT 0x120634 3406#define PXP2_REG_RQ_QM_LAST_ILT 0x120638 3407/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k; 3408 -128k */ 3409#define PXP2_REG_RQ_QM_P_SIZE 0x120050 3410/* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */ 3411#define PXP2_REG_RQ_RBC_DONE 0x1201b0 3412/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B; 3413 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ 3414#define PXP2_REG_RQ_RD_MBS0 0x120160 3415/* [RW 3] Max burst size filed for read requests port 1; 000 - 128B; 3416 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ 3417#define PXP2_REG_RQ_RD_MBS1 0x120168 3418/* [RW 2] Endian mode for src */ 3419#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c 3420#define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c 3421#define PXP2_REG_RQ_SRC_LAST_ILT 0x120640 3422/* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k; 3423 -128k */ 3424#define PXP2_REG_RQ_SRC_P_SIZE 0x12006c 3425/* [RW 2] Endian mode for tm */ 3426#define PXP2_REG_RQ_TM_ENDIAN_M 0x120198 3427#define PXP2_REG_RQ_TM_FIRST_ILT 0x120644 3428#define PXP2_REG_RQ_TM_LAST_ILT 0x120648 3429/* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k; 3430 -128k */ 3431#define PXP2_REG_RQ_TM_P_SIZE 0x120034 3432/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */ 3433#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c 3434/* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */ 3435#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094 3436/* [R 8] Number of entries occupied by vq 0 in pswrq memory */ 3437#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810 3438/* [R 8] Number of entries occupied by vq 10 in pswrq memory */ 3439#define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818 3440/* [R 8] Number of entries occupied by vq 11 in pswrq memory */ 3441#define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820 3442/* [R 8] Number of entries occupied by vq 12 in pswrq memory */ 3443#define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828 3444/* [R 8] Number of entries occupied by vq 13 in pswrq memory */ 3445#define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830 3446/* [R 8] Number of entries occupied by vq 14 in pswrq memory */ 3447#define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838 3448/* [R 8] Number of entries occupied by vq 15 in pswrq memory */ 3449#define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840 3450/* [R 8] Number of entries occupied by vq 16 in pswrq memory */ 3451#define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848 3452/* [R 8] Number of entries occupied by vq 17 in pswrq memory */ 3453#define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850 3454/* [R 8] Number of entries occupied by vq 18 in pswrq memory */ 3455#define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858 3456/* [R 8] Number of entries occupied by vq 19 in pswrq memory */ 3457#define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860 3458/* [R 8] Number of entries occupied by vq 1 in pswrq memory */ 3459#define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868 3460/* [R 8] Number of entries occupied by vq 20 in pswrq memory */ 3461#define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870 3462/* [R 8] Number of entries occupied by vq 21 in pswrq memory */ 3463#define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878 3464/* [R 8] Number of entries occupied by vq 22 in pswrq memory */ 3465#define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880 3466/* [R 8] Number of entries occupied by vq 23 in pswrq memory */ 3467#define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888 3468/* [R 8] Number of entries occupied by vq 24 in pswrq memory */ 3469#define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890 3470/* [R 8] Number of entries occupied by vq 25 in pswrq memory */ 3471#define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898 3472/* [R 8] Number of entries occupied by vq 26 in pswrq memory */ 3473#define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0 3474/* [R 8] Number of entries occupied by vq 27 in pswrq memory */ 3475#define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8 3476/* [R 8] Number of entries occupied by vq 28 in pswrq memory */ 3477#define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0 3478/* [R 8] Number of entries occupied by vq 29 in pswrq memory */ 3479#define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8 3480/* [R 8] Number of entries occupied by vq 2 in pswrq memory */ 3481#define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0 3482/* [R 8] Number of entries occupied by vq 30 in pswrq memory */ 3483#define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8 3484/* [R 8] Number of entries occupied by vq 31 in pswrq memory */ 3485#define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0 3486/* [R 8] Number of entries occupied by vq 3 in pswrq memory */ 3487#define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8 3488/* [R 8] Number of entries occupied by vq 4 in pswrq memory */ 3489#define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0 3490/* [R 8] Number of entries occupied by vq 5 in pswrq memory */ 3491#define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8 3492/* [R 8] Number of entries occupied by vq 6 in pswrq memory */ 3493#define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0 3494/* [R 8] Number of entries occupied by vq 7 in pswrq memory */ 3495#define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8 3496/* [R 8] Number of entries occupied by vq 8 in pswrq memory */ 3497#define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900 3498/* [R 8] Number of entries occupied by vq 9 in pswrq memory */ 3499#define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908 3500/* [RW 3] Max burst size filed for write requests port 0; 000 - 128B; 3501 001:256B; 010: 512B; */ 3502#define PXP2_REG_RQ_WR_MBS0 0x12015c 3503/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B; 3504 001:256B; 010: 512B; */ 3505#define PXP2_REG_RQ_WR_MBS1 0x120164 3506/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3507 buffer reaches this number has_payload will be asserted */ 3508#define PXP2_REG_WR_CDU_MPS 0x1205f0 3509/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3510 buffer reaches this number has_payload will be asserted */ 3511#define PXP2_REG_WR_CSDM_MPS 0x1205d0 3512/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3513 buffer reaches this number has_payload will be asserted */ 3514#define PXP2_REG_WR_DBG_MPS 0x1205e8 3515/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3516 buffer reaches this number has_payload will be asserted */ 3517#define PXP2_REG_WR_DMAE_MPS 0x1205ec 3518/* [RW 10] if Number of entries in dmae fifo will be higher than this 3519 threshold then has_payload indication will be asserted; the default value 3520 should be equal to > write MBS size! */ 3521#define PXP2_REG_WR_DMAE_TH 0x120368 3522/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3523 buffer reaches this number has_payload will be asserted */ 3524#define PXP2_REG_WR_HC_MPS 0x1205c8 3525/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3526 buffer reaches this number has_payload will be asserted */ 3527#define PXP2_REG_WR_QM_MPS 0x1205dc 3528/* [RW 1] 0 - working in A0 mode; - working in B0 mode */ 3529#define PXP2_REG_WR_REV_MODE 0x120670 3530/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3531 buffer reaches this number has_payload will be asserted */ 3532#define PXP2_REG_WR_SRC_MPS 0x1205e4 3533/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3534 buffer reaches this number has_payload will be asserted */ 3535#define PXP2_REG_WR_TM_MPS 0x1205e0 3536/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3537 buffer reaches this number has_payload will be asserted */ 3538#define PXP2_REG_WR_TSDM_MPS 0x1205d4 3539/* [RW 10] if Number of entries in usdmdp fifo will be higher than this 3540 threshold then has_payload indication will be asserted; the default value 3541 should be equal to > write MBS size! */ 3542#define PXP2_REG_WR_USDMDP_TH 0x120348 3543/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3544 buffer reaches this number has_payload will be asserted */ 3545#define PXP2_REG_WR_USDM_MPS 0x1205cc 3546/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3547 buffer reaches this number has_payload will be asserted */ 3548#define PXP2_REG_WR_XSDM_MPS 0x1205d8 3549/* [R 1] debug only: Indication if PSWHST arbiter is idle */ 3550#define PXP_REG_HST_ARB_IS_IDLE 0x103004 3551/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means 3552 this client is waiting for the arbiter. */ 3553#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008 3554/* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue 3555 block. Should be used for close the gates. */ 3556#define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4 3557/* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit 3558 should update according to 'hst_discard_doorbells' register when the state 3559 machine is idle */ 3560#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0 3561/* [RW 1] When 1; new internal writes arriving to the block are discarded. 3562 Should be used for close the gates. */ 3563#define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8 3564/* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1' 3565 means this PSWHST is discarding inputs from this client. Each bit should 3566 update according to 'hst_discard_internal_writes' register when the state 3567 machine is idle. */ 3568#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c 3569/* [WB 160] Used for initialization of the inbound interrupts memory */ 3570#define PXP_REG_HST_INBOUND_INT 0x103800 3571/* [RW 32] Interrupt mask register #0 read/write */ 3572#define PXP_REG_PXP_INT_MASK_0 0x103074 3573#define PXP_REG_PXP_INT_MASK_1 0x103084 3574/* [R 32] Interrupt register #0 read */ 3575#define PXP_REG_PXP_INT_STS_0 0x103068 3576#define PXP_REG_PXP_INT_STS_1 0x103078 3577/* [RC 32] Interrupt register #0 read clear */ 3578#define PXP_REG_PXP_INT_STS_CLR_0 0x10306c 3579#define PXP_REG_PXP_INT_STS_CLR_1 0x10307c 3580/* [RW 27] Parity mask register #0 read/write */ 3581#define PXP_REG_PXP_PRTY_MASK 0x103094 3582/* [R 26] Parity register #0 read */ 3583#define PXP_REG_PXP_PRTY_STS 0x103088 3584/* [RC 27] Parity register #0 read clear */ 3585#define PXP_REG_PXP_PRTY_STS_CLR 0x10308c 3586/* [RW 4] The activity counter initial increment value sent in the load 3587 request */ 3588#define QM_REG_ACTCTRINITVAL_0 0x168040 3589#define QM_REG_ACTCTRINITVAL_1 0x168044 3590#define QM_REG_ACTCTRINITVAL_2 0x168048 3591#define QM_REG_ACTCTRINITVAL_3 0x16804c 3592/* [RW 32] The base logical address (in bytes) of each physical queue. The 3593 index I represents the physical queue number. The 12 lsbs are ignore and 3594 considered zero so practically there are only 20 bits in this register; 3595 queues 63-0 */ 3596#define QM_REG_BASEADDR 0x168900 3597/* [RW 32] The base logical address (in bytes) of each physical queue. The 3598 index I represents the physical queue number. The 12 lsbs are ignore and 3599 considered zero so practically there are only 20 bits in this register; 3600 queues 127-64 */ 3601#define QM_REG_BASEADDR_EXT_A 0x16e100 3602/* [RW 16] The byte credit cost for each task. This value is for both ports */ 3603#define QM_REG_BYTECRDCOST 0x168234 3604/* [RW 16] The initial byte credit value for both ports. */ 3605#define QM_REG_BYTECRDINITVAL 0x168238 3606/* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3607 queue uses port 0 else it uses port 1; queues 31-0 */ 3608#define QM_REG_BYTECRDPORT_LSB 0x168228 3609/* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3610 queue uses port 0 else it uses port 1; queues 95-64 */ 3611#define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520 3612/* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3613 queue uses port 0 else it uses port 1; queues 63-32 */ 3614#define QM_REG_BYTECRDPORT_MSB 0x168224 3615/* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3616 queue uses port 0 else it uses port 1; queues 127-96 */ 3617#define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c 3618/* [RW 16] The byte credit value that if above the QM is considered almost 3619 full */ 3620#define QM_REG_BYTECREDITAFULLTHR 0x168094 3621/* [RW 4] The initial credit for interface */ 3622#define QM_REG_CMINITCRD_0 0x1680cc 3623#define QM_REG_BYTECRDCMDQ_0 0x16e6e8 3624#define QM_REG_CMINITCRD_1 0x1680d0 3625#define QM_REG_CMINITCRD_2 0x1680d4 3626#define QM_REG_CMINITCRD_3 0x1680d8 3627#define QM_REG_CMINITCRD_4 0x1680dc 3628#define QM_REG_CMINITCRD_5 0x1680e0 3629#define QM_REG_CMINITCRD_6 0x1680e4 3630#define QM_REG_CMINITCRD_7 0x1680e8 3631/* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface 3632 is masked */ 3633#define QM_REG_CMINTEN 0x1680ec 3634/* [RW 12] A bit vector which indicates which one of the queues are tied to 3635 interface 0 */ 3636#define QM_REG_CMINTVOQMASK_0 0x1681f4 3637#define QM_REG_CMINTVOQMASK_1 0x1681f8 3638#define QM_REG_CMINTVOQMASK_2 0x1681fc 3639#define QM_REG_CMINTVOQMASK_3 0x168200 3640#define QM_REG_CMINTVOQMASK_4 0x168204 3641#define QM_REG_CMINTVOQMASK_5 0x168208 3642#define QM_REG_CMINTVOQMASK_6 0x16820c 3643#define QM_REG_CMINTVOQMASK_7 0x168210 3644/* [RW 20] The number of connections divided by 16 which dictates the size 3645 of each queue which belongs to even function number. */ 3646#define QM_REG_CONNNUM_0 0x168020 3647/* [R 6] Keep the fill level of the fifo from write client 4 */ 3648#define QM_REG_CQM_WRC_FIFOLVL 0x168018 3649/* [RW 8] The context regions sent in the CFC load request */ 3650#define QM_REG_CTXREG_0 0x168030 3651#define QM_REG_CTXREG_1 0x168034 3652#define QM_REG_CTXREG_2 0x168038 3653#define QM_REG_CTXREG_3 0x16803c 3654/* [RW 12] The VOQ mask used to select the VOQs which needs to be full for 3655 bypass enable */ 3656#define QM_REG_ENBYPVOQMASK 0x16823c 3657/* [RW 32] A bit mask per each physical queue. If a bit is set then the 3658 physical queue uses the byte credit; queues 31-0 */ 3659#define QM_REG_ENBYTECRD_LSB 0x168220 3660/* [RW 32] A bit mask per each physical queue. If a bit is set then the 3661 physical queue uses the byte credit; queues 95-64 */ 3662#define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518 3663/* [RW 32] A bit mask per each physical queue. If a bit is set then the 3664 physical queue uses the byte credit; queues 63-32 */ 3665#define QM_REG_ENBYTECRD_MSB 0x16821c 3666/* [RW 32] A bit mask per each physical queue. If a bit is set then the 3667 physical queue uses the byte credit; queues 127-96 */ 3668#define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514 3669/* [RW 4] If cleared then the secondary interface will not be served by the 3670 RR arbiter */ 3671#define QM_REG_ENSEC 0x1680f0 3672/* [RW 32] NA */ 3673#define QM_REG_FUNCNUMSEL_LSB 0x168230 3674/* [RW 32] NA */ 3675#define QM_REG_FUNCNUMSEL_MSB 0x16822c 3676/* [RW 32] A mask register to mask the Almost empty signals which will not 3677 be use for the almost empty indication to the HW block; queues 31:0 */ 3678#define QM_REG_HWAEMPTYMASK_LSB 0x168218 3679/* [RW 32] A mask register to mask the Almost empty signals which will not 3680 be use for the almost empty indication to the HW block; queues 95-64 */ 3681#define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510 3682/* [RW 32] A mask register to mask the Almost empty signals which will not 3683 be use for the almost empty indication to the HW block; queues 63:32 */ 3684#define QM_REG_HWAEMPTYMASK_MSB 0x168214 3685/* [RW 32] A mask register to mask the Almost empty signals which will not 3686 be use for the almost empty indication to the HW block; queues 127-96 */ 3687#define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c 3688/* [RW 4] The number of outstanding request to CFC */ 3689#define QM_REG_OUTLDREQ 0x168804 3690/* [RC 1] A flag to indicate that overflow error occurred in one of the 3691 queues. */ 3692#define QM_REG_OVFERROR 0x16805c 3693/* [RC 7] the Q where the overflow occurs */ 3694#define QM_REG_OVFQNUM 0x168058 3695/* [R 16] Pause state for physical queues 15-0 */ 3696#define QM_REG_PAUSESTATE0 0x168410 3697/* [R 16] Pause state for physical queues 31-16 */ 3698#define QM_REG_PAUSESTATE1 0x168414 3699/* [R 16] Pause state for physical queues 47-32 */ 3700#define QM_REG_PAUSESTATE2 0x16e684 3701/* [R 16] Pause state for physical queues 63-48 */ 3702#define QM_REG_PAUSESTATE3 0x16e688 3703/* [R 16] Pause state for physical queues 79-64 */ 3704#define QM_REG_PAUSESTATE4 0x16e68c 3705/* [R 16] Pause state for physical queues 95-80 */ 3706#define QM_REG_PAUSESTATE5 0x16e690 3707/* [R 16] Pause state for physical queues 111-96 */ 3708#define QM_REG_PAUSESTATE6 0x16e694 3709/* [R 16] Pause state for physical queues 127-112 */ 3710#define QM_REG_PAUSESTATE7 0x16e698 3711/* [RW 2] The PCI attributes field used in the PCI request. */ 3712#define QM_REG_PCIREQAT 0x168054 3713#define QM_REG_PF_EN 0x16e70c 3714/* [R 24] The number of tasks stored in the QM for the PF. only even 3715 * functions are valid in E2 (odd I registers will be hard wired to 0) */ 3716#define QM_REG_PF_USG_CNT_0 0x16e040 3717/* [R 16] NOT USED */ 3718#define QM_REG_PORT0BYTECRD 0x168300 3719/* [R 16] The byte credit of port 1 */ 3720#define QM_REG_PORT1BYTECRD 0x168304 3721/* [RW 3] pci function number of queues 15-0 */ 3722#define QM_REG_PQ2PCIFUNC_0 0x16e6bc 3723#define QM_REG_PQ2PCIFUNC_1 0x16e6c0 3724#define QM_REG_PQ2PCIFUNC_2 0x16e6c4 3725#define QM_REG_PQ2PCIFUNC_3 0x16e6c8 3726#define QM_REG_PQ2PCIFUNC_4 0x16e6cc 3727#define QM_REG_PQ2PCIFUNC_5 0x16e6d0 3728#define QM_REG_PQ2PCIFUNC_6 0x16e6d4 3729#define QM_REG_PQ2PCIFUNC_7 0x16e6d8 3730/* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow: 3731 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read 3732 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ 3733#define QM_REG_PTRTBL 0x168a00 3734/* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow: 3735 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read 3736 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ 3737#define QM_REG_PTRTBL_EXT_A 0x16e200 3738/* [RW 2] Interrupt mask register #0 read/write */ 3739#define QM_REG_QM_INT_MASK 0x168444 3740/* [R 2] Interrupt register #0 read */ 3741#define QM_REG_QM_INT_STS 0x168438 3742/* [RW 12] Parity mask register #0 read/write */ 3743#define QM_REG_QM_PRTY_MASK 0x168454 3744/* [R 12] Parity register #0 read */ 3745#define QM_REG_QM_PRTY_STS 0x168448 3746/* [RC 12] Parity register #0 read clear */ 3747#define QM_REG_QM_PRTY_STS_CLR 0x16844c 3748/* [R 32] Current queues in pipeline: Queues from 32 to 63 */ 3749#define QM_REG_QSTATUS_HIGH 0x16802c 3750/* [R 32] Current queues in pipeline: Queues from 96 to 127 */ 3751#define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408 3752/* [R 32] Current queues in pipeline: Queues from 0 to 31 */ 3753#define QM_REG_QSTATUS_LOW 0x168028 3754/* [R 32] Current queues in pipeline: Queues from 64 to 95 */ 3755#define QM_REG_QSTATUS_LOW_EXT_A 0x16e404 3756/* [R 24] The number of tasks queued for each queue; queues 63-0 */ 3757#define QM_REG_QTASKCTR_0 0x168308 3758/* [R 24] The number of tasks queued for each queue; queues 127-64 */ 3759#define QM_REG_QTASKCTR_EXT_A_0 0x16e584 3760/* [RW 4] Queue tied to VOQ */ 3761#define QM_REG_QVOQIDX_0 0x1680f4 3762#define QM_REG_QVOQIDX_10 0x16811c 3763#define QM_REG_QVOQIDX_100 0x16e49c 3764#define QM_REG_QVOQIDX_101 0x16e4a0 3765#define QM_REG_QVOQIDX_102 0x16e4a4 3766#define QM_REG_QVOQIDX_103 0x16e4a8 3767#define QM_REG_QVOQIDX_104 0x16e4ac 3768#define QM_REG_QVOQIDX_105 0x16e4b0 3769#define QM_REG_QVOQIDX_106 0x16e4b4 3770#define QM_REG_QVOQIDX_107 0x16e4b8 3771#define QM_REG_QVOQIDX_108 0x16e4bc 3772#define QM_REG_QVOQIDX_109 0x16e4c0 3773#define QM_REG_QVOQIDX_11 0x168120 3774#define QM_REG_QVOQIDX_110 0x16e4c4 3775#define QM_REG_QVOQIDX_111 0x16e4c8 3776#define QM_REG_QVOQIDX_112 0x16e4cc 3777#define QM_REG_QVOQIDX_113 0x16e4d0 3778#define QM_REG_QVOQIDX_114 0x16e4d4 3779#define QM_REG_QVOQIDX_115 0x16e4d8 3780#define QM_REG_QVOQIDX_116 0x16e4dc 3781#define QM_REG_QVOQIDX_117 0x16e4e0 3782#define QM_REG_QVOQIDX_118 0x16e4e4 3783#define QM_REG_QVOQIDX_119 0x16e4e8 3784#define QM_REG_QVOQIDX_12 0x168124 3785#define QM_REG_QVOQIDX_120 0x16e4ec 3786#define QM_REG_QVOQIDX_121 0x16e4f0 3787#define QM_REG_QVOQIDX_122 0x16e4f4 3788#define QM_REG_QVOQIDX_123 0x16e4f8 3789#define QM_REG_QVOQIDX_124 0x16e4fc 3790#define QM_REG_QVOQIDX_125 0x16e500 3791#define QM_REG_QVOQIDX_126 0x16e504 3792#define QM_REG_QVOQIDX_127 0x16e508 3793#define QM_REG_QVOQIDX_13 0x168128 3794#define QM_REG_QVOQIDX_14 0x16812c 3795#define QM_REG_QVOQIDX_15 0x168130 3796#define QM_REG_QVOQIDX_16 0x168134 3797#define QM_REG_QVOQIDX_17 0x168138 3798#define QM_REG_QVOQIDX_21 0x168148 3799#define QM_REG_QVOQIDX_22 0x16814c 3800#define QM_REG_QVOQIDX_23 0x168150 3801#define QM_REG_QVOQIDX_24 0x168154 3802#define QM_REG_QVOQIDX_25 0x168158 3803#define QM_REG_QVOQIDX_26 0x16815c 3804#define QM_REG_QVOQIDX_27 0x168160 3805#define QM_REG_QVOQIDX_28 0x168164 3806#define QM_REG_QVOQIDX_29 0x168168 3807#define QM_REG_QVOQIDX_30 0x16816c 3808#define QM_REG_QVOQIDX_31 0x168170 3809#define QM_REG_QVOQIDX_32 0x168174 3810#define QM_REG_QVOQIDX_33 0x168178 3811#define QM_REG_QVOQIDX_34 0x16817c 3812#define QM_REG_QVOQIDX_35 0x168180 3813#define QM_REG_QVOQIDX_36 0x168184 3814#define QM_REG_QVOQIDX_37 0x168188 3815#define QM_REG_QVOQIDX_38 0x16818c 3816#define QM_REG_QVOQIDX_39 0x168190 3817#define QM_REG_QVOQIDX_40 0x168194 3818#define QM_REG_QVOQIDX_41 0x168198 3819#define QM_REG_QVOQIDX_42 0x16819c 3820#define QM_REG_QVOQIDX_43 0x1681a0 3821#define QM_REG_QVOQIDX_44 0x1681a4 3822#define QM_REG_QVOQIDX_45 0x1681a8 3823#define QM_REG_QVOQIDX_46 0x1681ac 3824#define QM_REG_QVOQIDX_47 0x1681b0 3825#define QM_REG_QVOQIDX_48 0x1681b4 3826#define QM_REG_QVOQIDX_49 0x1681b8 3827#define QM_REG_QVOQIDX_5 0x168108 3828#define QM_REG_QVOQIDX_50 0x1681bc 3829#define QM_REG_QVOQIDX_51 0x1681c0 3830#define QM_REG_QVOQIDX_52 0x1681c4 3831#define QM_REG_QVOQIDX_53 0x1681c8 3832#define QM_REG_QVOQIDX_54 0x1681cc 3833#define QM_REG_QVOQIDX_55 0x1681d0 3834#define QM_REG_QVOQIDX_56 0x1681d4 3835#define QM_REG_QVOQIDX_57 0x1681d8 3836#define QM_REG_QVOQIDX_58 0x1681dc 3837#define QM_REG_QVOQIDX_59 0x1681e0 3838#define QM_REG_QVOQIDX_6 0x16810c 3839#define QM_REG_QVOQIDX_60 0x1681e4 3840#define QM_REG_QVOQIDX_61 0x1681e8 3841#define QM_REG_QVOQIDX_62 0x1681ec 3842#define QM_REG_QVOQIDX_63 0x1681f0 3843#define QM_REG_QVOQIDX_64 0x16e40c 3844#define QM_REG_QVOQIDX_65 0x16e410 3845#define QM_REG_QVOQIDX_69 0x16e420 3846#define QM_REG_QVOQIDX_7 0x168110 3847#define QM_REG_QVOQIDX_70 0x16e424 3848#define QM_REG_QVOQIDX_71 0x16e428 3849#define QM_REG_QVOQIDX_72 0x16e42c 3850#define QM_REG_QVOQIDX_73 0x16e430 3851#define QM_REG_QVOQIDX_74 0x16e434 3852#define QM_REG_QVOQIDX_75 0x16e438 3853#define QM_REG_QVOQIDX_76 0x16e43c 3854#define QM_REG_QVOQIDX_77 0x16e440 3855#define QM_REG_QVOQIDX_78 0x16e444 3856#define QM_REG_QVOQIDX_79 0x16e448 3857#define QM_REG_QVOQIDX_8 0x168114 3858#define QM_REG_QVOQIDX_80 0x16e44c 3859#define QM_REG_QVOQIDX_81 0x16e450 3860#define QM_REG_QVOQIDX_85 0x16e460 3861#define QM_REG_QVOQIDX_86 0x16e464 3862#define QM_REG_QVOQIDX_87 0x16e468 3863#define QM_REG_QVOQIDX_88 0x16e46c 3864#define QM_REG_QVOQIDX_89 0x16e470 3865#define QM_REG_QVOQIDX_9 0x168118 3866#define QM_REG_QVOQIDX_90 0x16e474 3867#define QM_REG_QVOQIDX_91 0x16e478 3868#define QM_REG_QVOQIDX_92 0x16e47c 3869#define QM_REG_QVOQIDX_93 0x16e480 3870#define QM_REG_QVOQIDX_94 0x16e484 3871#define QM_REG_QVOQIDX_95 0x16e488 3872#define QM_REG_QVOQIDX_96 0x16e48c 3873#define QM_REG_QVOQIDX_97 0x16e490 3874#define QM_REG_QVOQIDX_98 0x16e494 3875#define QM_REG_QVOQIDX_99 0x16e498 3876/* [RW 1] Initialization bit command */ 3877#define QM_REG_SOFT_RESET 0x168428 3878/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */ 3879#define QM_REG_TASKCRDCOST_0 0x16809c 3880#define QM_REG_TASKCRDCOST_1 0x1680a0 3881#define QM_REG_TASKCRDCOST_2 0x1680a4 3882#define QM_REG_TASKCRDCOST_4 0x1680ac 3883#define QM_REG_TASKCRDCOST_5 0x1680b0 3884/* [R 6] Keep the fill level of the fifo from write client 3 */ 3885#define QM_REG_TQM_WRC_FIFOLVL 0x168010 3886/* [R 6] Keep the fill level of the fifo from write client 2 */ 3887#define QM_REG_UQM_WRC_FIFOLVL 0x168008 3888/* [RC 32] Credit update error register */ 3889#define QM_REG_VOQCRDERRREG 0x168408 3890/* [R 16] The credit value for each VOQ */ 3891#define QM_REG_VOQCREDIT_0 0x1682d0 3892#define QM_REG_VOQCREDIT_1 0x1682d4 3893#define QM_REG_VOQCREDIT_4 0x1682e0 3894/* [RW 16] The credit value that if above the QM is considered almost full */ 3895#define QM_REG_VOQCREDITAFULLTHR 0x168090 3896/* [RW 16] The init and maximum credit for each VoQ */ 3897#define QM_REG_VOQINITCREDIT_0 0x168060 3898#define QM_REG_VOQINITCREDIT_1 0x168064 3899#define QM_REG_VOQINITCREDIT_2 0x168068 3900#define QM_REG_VOQINITCREDIT_4 0x168070 3901#define QM_REG_VOQINITCREDIT_5 0x168074 3902/* [RW 1] The port of which VOQ belongs */ 3903#define QM_REG_VOQPORT_0 0x1682a0 3904#define QM_REG_VOQPORT_1 0x1682a4 3905#define QM_REG_VOQPORT_2 0x1682a8 3906/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3907#define QM_REG_VOQQMASK_0_LSB 0x168240 3908/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3909#define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524 3910/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3911#define QM_REG_VOQQMASK_0_MSB 0x168244 3912/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3913#define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528 3914/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3915#define QM_REG_VOQQMASK_10_LSB 0x168290 3916/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3917#define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574 3918/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3919#define QM_REG_VOQQMASK_10_MSB 0x168294 3920/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3921#define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578 3922/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3923#define QM_REG_VOQQMASK_11_LSB 0x168298 3924/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3925#define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c 3926/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3927#define QM_REG_VOQQMASK_11_MSB 0x16829c 3928/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3929#define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580 3930/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3931#define QM_REG_VOQQMASK_1_LSB 0x168248 3932/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3933#define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c 3934/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3935#define QM_REG_VOQQMASK_1_MSB 0x16824c 3936/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3937#define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530 3938/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3939#define QM_REG_VOQQMASK_2_LSB 0x168250 3940/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3941#define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534 3942/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3943#define QM_REG_VOQQMASK_2_MSB 0x168254 3944/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3945#define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538 3946/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3947#define QM_REG_VOQQMASK_3_LSB 0x168258 3948/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3949#define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c 3950/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3951#define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540 3952/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3953#define QM_REG_VOQQMASK_4_LSB 0x168260 3954/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3955#define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544 3956/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3957#define QM_REG_VOQQMASK_4_MSB 0x168264 3958/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3959#define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548 3960/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3961#define QM_REG_VOQQMASK_5_LSB 0x168268 3962/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3963#define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c 3964/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3965#define QM_REG_VOQQMASK_5_MSB 0x16826c 3966/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3967#define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550 3968/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3969#define QM_REG_VOQQMASK_6_LSB 0x168270 3970/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3971#define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554 3972/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3973#define QM_REG_VOQQMASK_6_MSB 0x168274 3974/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3975#define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558 3976/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3977#define QM_REG_VOQQMASK_7_LSB 0x168278 3978/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3979#define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c 3980/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3981#define QM_REG_VOQQMASK_7_MSB 0x16827c 3982/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3983#define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560 3984/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3985#define QM_REG_VOQQMASK_8_LSB 0x168280 3986/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3987#define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564 3988/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3989#define QM_REG_VOQQMASK_8_MSB 0x168284 3990/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3991#define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568 3992/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3993#define QM_REG_VOQQMASK_9_LSB 0x168288 3994/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3995#define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c 3996/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3997#define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570 3998/* [RW 32] Wrr weights */ 3999#define QM_REG_WRRWEIGHTS_0 0x16880c 4000#define QM_REG_WRRWEIGHTS_1 0x168810 4001#define QM_REG_WRRWEIGHTS_10 0x168814 4002#define QM_REG_WRRWEIGHTS_11 0x168818 4003#define QM_REG_WRRWEIGHTS_12 0x16881c 4004#define QM_REG_WRRWEIGHTS_13 0x168820 4005#define QM_REG_WRRWEIGHTS_14 0x168824 4006#define QM_REG_WRRWEIGHTS_15 0x168828 4007#define QM_REG_WRRWEIGHTS_16 0x16e000 4008#define QM_REG_WRRWEIGHTS_17 0x16e004 4009#define QM_REG_WRRWEIGHTS_18 0x16e008 4010#define QM_REG_WRRWEIGHTS_19 0x16e00c 4011#define QM_REG_WRRWEIGHTS_2 0x16882c 4012#define QM_REG_WRRWEIGHTS_20 0x16e010 4013#define QM_REG_WRRWEIGHTS_21 0x16e014 4014#define QM_REG_WRRWEIGHTS_22 0x16e018 4015#define QM_REG_WRRWEIGHTS_23 0x16e01c 4016#define QM_REG_WRRWEIGHTS_24 0x16e020 4017#define QM_REG_WRRWEIGHTS_25 0x16e024 4018#define QM_REG_WRRWEIGHTS_26 0x16e028 4019#define QM_REG_WRRWEIGHTS_27 0x16e02c 4020#define QM_REG_WRRWEIGHTS_28 0x16e030 4021#define QM_REG_WRRWEIGHTS_29 0x16e034 4022#define QM_REG_WRRWEIGHTS_3 0x168830 4023#define QM_REG_WRRWEIGHTS_30 0x16e038 4024#define QM_REG_WRRWEIGHTS_31 0x16e03c 4025#define QM_REG_WRRWEIGHTS_4 0x168834 4026#define QM_REG_WRRWEIGHTS_5 0x168838 4027#define QM_REG_WRRWEIGHTS_6 0x16883c 4028#define QM_REG_WRRWEIGHTS_7 0x168840 4029#define QM_REG_WRRWEIGHTS_8 0x168844 4030#define QM_REG_WRRWEIGHTS_9 0x168848 4031/* [R 6] Keep the fill level of the fifo from write client 1 */ 4032#define QM_REG_XQM_WRC_FIFOLVL 0x168000 4033/* [W 1] reset to parity interrupt */ 4034#define SEM_FAST_REG_PARITY_RST 0x18840 4035#define SRC_REG_COUNTFREE0 0x40500 4036/* [RW 1] If clr the searcher is compatible to E1 A0 - support only two 4037 ports. If set the searcher support 8 functions. */ 4038#define SRC_REG_E1HMF_ENABLE 0x404cc 4039#define SRC_REG_FIRSTFREE0 0x40510 4040#define SRC_REG_KEYRSS0_0 0x40408 4041#define SRC_REG_KEYRSS0_7 0x40424 4042#define SRC_REG_KEYRSS1_9 0x40454 4043#define SRC_REG_KEYSEARCH_0 0x40458 4044#define SRC_REG_KEYSEARCH_1 0x4045c 4045#define SRC_REG_KEYSEARCH_2 0x40460 4046#define SRC_REG_KEYSEARCH_3 0x40464 4047#define SRC_REG_KEYSEARCH_4 0x40468 4048#define SRC_REG_KEYSEARCH_5 0x4046c 4049#define SRC_REG_KEYSEARCH_6 0x40470 4050#define SRC_REG_KEYSEARCH_7 0x40474 4051#define SRC_REG_KEYSEARCH_8 0x40478 4052#define SRC_REG_KEYSEARCH_9 0x4047c 4053#define SRC_REG_LASTFREE0 0x40530 4054#define SRC_REG_NUMBER_HASH_BITS0 0x40400 4055/* [RW 1] Reset internal state machines. */ 4056#define SRC_REG_SOFT_RST 0x4049c 4057/* [R 3] Interrupt register #0 read */ 4058#define SRC_REG_SRC_INT_STS 0x404ac 4059/* [RW 3] Parity mask register #0 read/write */ 4060#define SRC_REG_SRC_PRTY_MASK 0x404c8 4061/* [R 3] Parity register #0 read */ 4062#define SRC_REG_SRC_PRTY_STS 0x404bc 4063/* [RC 3] Parity register #0 read clear */ 4064#define SRC_REG_SRC_PRTY_STS_CLR 0x404c0 4065/* [R 4] Used to read the value of the XX protection CAM occupancy counter. */ 4066#define TCM_REG_CAM_OCCUP 0x5017c 4067/* [RW 1] CDU AG read Interface enable. If 0 - the request input is 4068 disregarded; valid output is deasserted; all other signals are treated as 4069 usual; if 1 - normal activity. */ 4070#define TCM_REG_CDU_AG_RD_IFEN 0x50034 4071/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 4072 are disregarded; all other signals are treated as usual; if 1 - normal 4073 activity. */ 4074#define TCM_REG_CDU_AG_WR_IFEN 0x50030 4075/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 4076 disregarded; valid output is deasserted; all other signals are treated as 4077 usual; if 1 - normal activity. */ 4078#define TCM_REG_CDU_SM_RD_IFEN 0x5003c 4079/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 4080 input is disregarded; all other signals are treated as usual; if 1 - 4081 normal activity. */ 4082#define TCM_REG_CDU_SM_WR_IFEN 0x50038 4083/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 4084 the initial credit value; read returns the current value of the credit 4085 counter. Must be initialized to 1 at start-up. */ 4086#define TCM_REG_CFC_INIT_CRD 0x50204 4087/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 4088 weight 8 (the most prioritised); 1 stands for weight 1(least 4089 prioritised); 2 stands for weight 2; tc. */ 4090#define TCM_REG_CP_WEIGHT 0x500c0 4091/* [RW 1] Input csem Interface enable. If 0 - the valid input is 4092 disregarded; acknowledge output is deasserted; all other signals are 4093 treated as usual; if 1 - normal activity. */ 4094#define TCM_REG_CSEM_IFEN 0x5002c 4095/* [RC 1] Message length mismatch (relative to last indication) at the In#9 4096 interface. */ 4097#define TCM_REG_CSEM_LENGTH_MIS 0x50174 4098/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for 4099 weight 8 (the most prioritised); 1 stands for weight 1(least 4100 prioritised); 2 stands for weight 2; tc. */ 4101#define TCM_REG_CSEM_WEIGHT 0x500bc 4102/* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */ 4103#define TCM_REG_ERR_EVNT_ID 0x500a0 4104/* [RW 28] The CM erroneous header for QM and Timers formatting. */ 4105#define TCM_REG_ERR_TCM_HDR 0x5009c 4106/* [RW 8] The Event ID for Timers expiration. */ 4107#define TCM_REG_EXPR_EVNT_ID 0x500a4 4108/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 4109 writes the initial credit value; read returns the current value of the 4110 credit counter. Must be initialized to 64 at start-up. */ 4111#define TCM_REG_FIC0_INIT_CRD 0x5020c 4112/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 4113 writes the initial credit value; read returns the current value of the 4114 credit counter. Must be initialized to 64 at start-up. */ 4115#define TCM_REG_FIC1_INIT_CRD 0x50210 4116/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 4117 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr; 4118 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and 4119 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */ 4120#define TCM_REG_GR_ARB_TYPE 0x50114 4121/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 4122 highest priority is 3. It is supposed that the Store channel is the 4123 compliment of the other 3 groups. */ 4124#define TCM_REG_GR_LD0_PR 0x5011c 4125/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 4126 highest priority is 3. It is supposed that the Store channel is the 4127 compliment of the other 3 groups. */ 4128#define TCM_REG_GR_LD1_PR 0x50120 4129/* [RW 4] The number of double REG-pairs; loaded from the STORM context and 4130 sent to STORM; for a specific connection type. The double REG-pairs are 4131 used to align to STORM context row size of 128 bits. The offset of these 4132 data in the STORM context is always 0. Index _i stands for the connection 4133 type (one of 16). */ 4134#define TCM_REG_N_SM_CTX_LD_0 0x50050 4135#define TCM_REG_N_SM_CTX_LD_1 0x50054 4136#define TCM_REG_N_SM_CTX_LD_2 0x50058 4137#define TCM_REG_N_SM_CTX_LD_3 0x5005c 4138#define TCM_REG_N_SM_CTX_LD_4 0x50060 4139#define TCM_REG_N_SM_CTX_LD_5 0x50064 4140/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 4141 acknowledge output is deasserted; all other signals are treated as usual; 4142 if 1 - normal activity. */ 4143#define TCM_REG_PBF_IFEN 0x50024 4144/* [RC 1] Message length mismatch (relative to last indication) at the In#7 4145 interface. */ 4146#define TCM_REG_PBF_LENGTH_MIS 0x5016c 4147/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 4148 weight 8 (the most prioritised); 1 stands for weight 1(least 4149 prioritised); 2 stands for weight 2; tc. */ 4150#define TCM_REG_PBF_WEIGHT 0x500b4 4151#define TCM_REG_PHYS_QNUM0_0 0x500e0 4152#define TCM_REG_PHYS_QNUM0_1 0x500e4 4153#define TCM_REG_PHYS_QNUM1_0 0x500e8 4154#define TCM_REG_PHYS_QNUM1_1 0x500ec 4155#define TCM_REG_PHYS_QNUM2_0 0x500f0 4156#define TCM_REG_PHYS_QNUM2_1 0x500f4 4157#define TCM_REG_PHYS_QNUM3_0 0x500f8 4158#define TCM_REG_PHYS_QNUM3_1 0x500fc 4159/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded; 4160 acknowledge output is deasserted; all other signals are treated as usual; 4161 if 1 - normal activity. */ 4162#define TCM_REG_PRS_IFEN 0x50020 4163/* [RC 1] Message length mismatch (relative to last indication) at the In#6 4164 interface. */ 4165#define TCM_REG_PRS_LENGTH_MIS 0x50168 4166/* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for 4167 weight 8 (the most prioritised); 1 stands for weight 1(least 4168 prioritised); 2 stands for weight 2; tc. */ 4169#define TCM_REG_PRS_WEIGHT 0x500b0 4170/* [RW 8] The Event ID for Timers formatting in case of stop done. */ 4171#define TCM_REG_STOP_EVNT_ID 0x500a8 4172/* [RC 1] Message length mismatch (relative to last indication) at the STORM 4173 interface. */ 4174#define TCM_REG_STORM_LENGTH_MIS 0x50160 4175/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 4176 disregarded; acknowledge output is deasserted; all other signals are 4177 treated as usual; if 1 - normal activity. */ 4178#define TCM_REG_STORM_TCM_IFEN 0x50010 4179/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for 4180 weight 8 (the most prioritised); 1 stands for weight 1(least 4181 prioritised); 2 stands for weight 2; tc. */ 4182#define TCM_REG_STORM_WEIGHT 0x500ac 4183/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 4184 acknowledge output is deasserted; all other signals are treated as usual; 4185 if 1 - normal activity. */ 4186#define TCM_REG_TCM_CFC_IFEN 0x50040 4187/* [RW 11] Interrupt mask register #0 read/write */ 4188#define TCM_REG_TCM_INT_MASK 0x501dc 4189/* [R 11] Interrupt register #0 read */ 4190#define TCM_REG_TCM_INT_STS 0x501d0 4191/* [RW 27] Parity mask register #0 read/write */ 4192#define TCM_REG_TCM_PRTY_MASK 0x501ec 4193/* [R 27] Parity register #0 read */ 4194#define TCM_REG_TCM_PRTY_STS 0x501e0 4195/* [RC 27] Parity register #0 read clear */ 4196#define TCM_REG_TCM_PRTY_STS_CLR 0x501e4 4197/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS 4198 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 4199 Is used to determine the number of the AG context REG-pairs written back; 4200 when the input message Reg1WbFlg isn't set. */ 4201#define TCM_REG_TCM_REG0_SZ 0x500d8 4202/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 4203 disregarded; valid is deasserted; all other signals are treated as usual; 4204 if 1 - normal activity. */ 4205#define TCM_REG_TCM_STORM0_IFEN 0x50004 4206/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 4207 disregarded; valid is deasserted; all other signals are treated as usual; 4208 if 1 - normal activity. */ 4209#define TCM_REG_TCM_STORM1_IFEN 0x50008 4210/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 4211 disregarded; valid is deasserted; all other signals are treated as usual; 4212 if 1 - normal activity. */ 4213#define TCM_REG_TCM_TQM_IFEN 0x5000c 4214/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 4215#define TCM_REG_TCM_TQM_USE_Q 0x500d4 4216/* [RW 28] The CM header for Timers expiration command. */ 4217#define TCM_REG_TM_TCM_HDR 0x50098 4218/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 4219 disregarded; acknowledge output is deasserted; all other signals are 4220 treated as usual; if 1 - normal activity. */ 4221#define TCM_REG_TM_TCM_IFEN 0x5001c 4222/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for 4223 weight 8 (the most prioritised); 1 stands for weight 1(least 4224 prioritised); 2 stands for weight 2; tc. */ 4225#define TCM_REG_TM_WEIGHT 0x500d0 4226/* [RW 6] QM output initial credit. Max credit available - 32.Write writes 4227 the initial credit value; read returns the current value of the credit 4228 counter. Must be initialized to 32 at start-up. */ 4229#define TCM_REG_TQM_INIT_CRD 0x5021c 4230/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 4231 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4232 prioritised); 2 stands for weight 2; tc. */ 4233#define TCM_REG_TQM_P_WEIGHT 0x500c8 4234/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 4235 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4236 prioritised); 2 stands for weight 2; tc. */ 4237#define TCM_REG_TQM_S_WEIGHT 0x500cc 4238/* [RW 28] The CM header value for QM request (primary). */ 4239#define TCM_REG_TQM_TCM_HDR_P 0x50090 4240/* [RW 28] The CM header value for QM request (secondary). */ 4241#define TCM_REG_TQM_TCM_HDR_S 0x50094 4242/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 4243 acknowledge output is deasserted; all other signals are treated as usual; 4244 if 1 - normal activity. */ 4245#define TCM_REG_TQM_TCM_IFEN 0x50014 4246/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 4247 acknowledge output is deasserted; all other signals are treated as usual; 4248 if 1 - normal activity. */ 4249#define TCM_REG_TSDM_IFEN 0x50018 4250/* [RC 1] Message length mismatch (relative to last indication) at the SDM 4251 interface. */ 4252#define TCM_REG_TSDM_LENGTH_MIS 0x50164 4253/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 4254 weight 8 (the most prioritised); 1 stands for weight 1(least 4255 prioritised); 2 stands for weight 2; tc. */ 4256#define TCM_REG_TSDM_WEIGHT 0x500c4 4257/* [RW 1] Input usem Interface enable. If 0 - the valid input is 4258 disregarded; acknowledge output is deasserted; all other signals are 4259 treated as usual; if 1 - normal activity. */ 4260#define TCM_REG_USEM_IFEN 0x50028 4261/* [RC 1] Message length mismatch (relative to last indication) at the In#8 4262 interface. */ 4263#define TCM_REG_USEM_LENGTH_MIS 0x50170 4264/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 4265 weight 8 (the most prioritised); 1 stands for weight 1(least 4266 prioritised); 2 stands for weight 2; tc. */ 4267#define TCM_REG_USEM_WEIGHT 0x500b8 4268/* [RW 21] Indirect access to the descriptor table of the XX protection 4269 mechanism. The fields are: [5:0] - length of the message; 15:6] - message 4270 pointer; 20:16] - next pointer. */ 4271#define TCM_REG_XX_DESCR_TABLE 0x50280 4272#define TCM_REG_XX_DESCR_TABLE_SIZE 29 4273/* [R 6] Use to read the value of XX protection Free counter. */ 4274#define TCM_REG_XX_FREE 0x50178 4275/* [RW 6] Initial value for the credit counter; responsible for fulfilling 4276 of the Input Stage XX protection buffer by the XX protection pending 4277 messages. Max credit available - 127.Write writes the initial credit 4278 value; read returns the current value of the credit counter. Must be 4279 initialized to 19 at start-up. */ 4280#define TCM_REG_XX_INIT_CRD 0x50220 4281/* [RW 6] Maximum link list size (messages locked) per connection in the XX 4282 protection. */ 4283#define TCM_REG_XX_MAX_LL_SZ 0x50044 4284/* [RW 6] The maximum number of pending messages; which may be stored in XX 4285 protection. ~tcm_registers_xx_free.xx_free is read on read. */ 4286#define TCM_REG_XX_MSG_NUM 0x50224 4287/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 4288#define TCM_REG_XX_OVFL_EVNT_ID 0x50048 4289/* [RW 16] Indirect access to the XX table of the XX protection mechanism. 4290 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] - 4291 header pointer. */ 4292#define TCM_REG_XX_TABLE 0x50240 4293/* [RW 4] Load value for cfc ac credit cnt. */ 4294#define TM_REG_CFC_AC_CRDCNT_VAL 0x164208 4295/* [RW 4] Load value for cfc cld credit cnt. */ 4296#define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210 4297/* [RW 8] Client0 context region. */ 4298#define TM_REG_CL0_CONT_REGION 0x164030 4299/* [RW 8] Client1 context region. */ 4300#define TM_REG_CL1_CONT_REGION 0x164034 4301/* [RW 8] Client2 context region. */ 4302#define TM_REG_CL2_CONT_REGION 0x164038 4303/* [RW 2] Client in High priority client number. */ 4304#define TM_REG_CLIN_PRIOR0_CLIENT 0x164024 4305/* [RW 4] Load value for clout0 cred cnt. */ 4306#define TM_REG_CLOUT_CRDCNT0_VAL 0x164220 4307/* [RW 4] Load value for clout1 cred cnt. */ 4308#define TM_REG_CLOUT_CRDCNT1_VAL 0x164228 4309/* [RW 4] Load value for clout2 cred cnt. */ 4310#define TM_REG_CLOUT_CRDCNT2_VAL 0x164230 4311/* [RW 1] Enable client0 input. */ 4312#define TM_REG_EN_CL0_INPUT 0x164008 4313/* [RW 1] Enable client1 input. */ 4314#define TM_REG_EN_CL1_INPUT 0x16400c 4315/* [RW 1] Enable client2 input. */ 4316#define TM_REG_EN_CL2_INPUT 0x164010 4317#define TM_REG_EN_LINEAR0_TIMER 0x164014 4318/* [RW 1] Enable real time counter. */ 4319#define TM_REG_EN_REAL_TIME_CNT 0x1640d8 4320/* [RW 1] Enable for Timers state machines. */ 4321#define TM_REG_EN_TIMERS 0x164000 4322/* [RW 4] Load value for expiration credit cnt. CFC max number of 4323 outstanding load requests for timers (expiration) context loading. */ 4324#define TM_REG_EXP_CRDCNT_VAL 0x164238 4325/* [RW 32] Linear0 logic address. */ 4326#define TM_REG_LIN0_LOGIC_ADDR 0x164240 4327/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */ 4328#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048 4329/* [ST 16] Linear0 Number of scans counter. */ 4330#define TM_REG_LIN0_NUM_SCANS 0x1640a0 4331/* [WB 64] Linear0 phy address. */ 4332#define TM_REG_LIN0_PHY_ADDR 0x164270 4333/* [RW 1] Linear0 physical address valid. */ 4334#define TM_REG_LIN0_PHY_ADDR_VALID 0x164248 4335#define TM_REG_LIN0_SCAN_ON 0x1640d0 4336/* [RW 24] Linear0 array scan timeout. */ 4337#define TM_REG_LIN0_SCAN_TIME 0x16403c 4338#define TM_REG_LIN0_VNIC_UC 0x164128 4339/* [RW 32] Linear1 logic address. */ 4340#define TM_REG_LIN1_LOGIC_ADDR 0x164250 4341/* [WB 64] Linear1 phy address. */ 4342#define TM_REG_LIN1_PHY_ADDR 0x164280 4343/* [RW 1] Linear1 physical address valid. */ 4344#define TM_REG_LIN1_PHY_ADDR_VALID 0x164258 4345/* [RW 6] Linear timer set_clear fifo threshold. */ 4346#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070 4347/* [RW 2] Load value for pci arbiter credit cnt. */ 4348#define TM_REG_PCIARB_CRDCNT_VAL 0x164260 4349/* [RW 20] The amount of hardware cycles for each timer tick. */ 4350#define TM_REG_TIMER_TICK_SIZE 0x16401c 4351/* [RW 8] Timers Context region. */ 4352#define TM_REG_TM_CONTEXT_REGION 0x164044 4353/* [RW 1] Interrupt mask register #0 read/write */ 4354#define TM_REG_TM_INT_MASK 0x1640fc 4355/* [R 1] Interrupt register #0 read */ 4356#define TM_REG_TM_INT_STS 0x1640f0 4357/* [RW 7] Parity mask register #0 read/write */ 4358#define TM_REG_TM_PRTY_MASK 0x16410c 4359/* [RC 7] Parity register #0 read clear */ 4360#define TM_REG_TM_PRTY_STS_CLR 0x164104 4361/* [RW 8] The event id for aggregated interrupt 0 */ 4362#define TSDM_REG_AGG_INT_EVENT_0 0x42038 4363#define TSDM_REG_AGG_INT_EVENT_1 0x4203c 4364#define TSDM_REG_AGG_INT_EVENT_2 0x42040 4365#define TSDM_REG_AGG_INT_EVENT_3 0x42044 4366#define TSDM_REG_AGG_INT_EVENT_4 0x42048 4367/* [RW 1] The T bit for aggregated interrupt 0 */ 4368#define TSDM_REG_AGG_INT_T_0 0x420b8 4369#define TSDM_REG_AGG_INT_T_1 0x420bc 4370/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 4371#define TSDM_REG_CFC_RSP_START_ADDR 0x42008 4372/* [RW 16] The maximum value of the completion counter #0 */ 4373#define TSDM_REG_CMP_COUNTER_MAX0 0x4201c 4374/* [RW 16] The maximum value of the completion counter #1 */ 4375#define TSDM_REG_CMP_COUNTER_MAX1 0x42020 4376/* [RW 16] The maximum value of the completion counter #2 */ 4377#define TSDM_REG_CMP_COUNTER_MAX2 0x42024 4378/* [RW 16] The maximum value of the completion counter #3 */ 4379#define TSDM_REG_CMP_COUNTER_MAX3 0x42028 4380/* [RW 13] The start address in the internal RAM for the completion 4381 counters. */ 4382#define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c 4383#define TSDM_REG_ENABLE_IN1 0x42238 4384#define TSDM_REG_ENABLE_IN2 0x4223c 4385#define TSDM_REG_ENABLE_OUT1 0x42240 4386#define TSDM_REG_ENABLE_OUT2 0x42244 4387/* [RW 4] The initial number of messages that can be sent to the pxp control 4388 interface without receiving any ACK. */ 4389#define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc 4390/* [ST 32] The number of ACK after placement messages received */ 4391#define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c 4392/* [ST 32] The number of packet end messages received from the parser */ 4393#define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274 4394/* [ST 32] The number of requests received from the pxp async if */ 4395#define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278 4396/* [ST 32] The number of commands received in queue 0 */ 4397#define TSDM_REG_NUM_OF_Q0_CMD 0x42248 4398/* [ST 32] The number of commands received in queue 10 */ 4399#define TSDM_REG_NUM_OF_Q10_CMD 0x4226c 4400/* [ST 32] The number of commands received in queue 11 */ 4401#define TSDM_REG_NUM_OF_Q11_CMD 0x42270 4402/* [ST 32] The number of commands received in queue 1 */ 4403#define TSDM_REG_NUM_OF_Q1_CMD 0x4224c 4404/* [ST 32] The number of commands received in queue 3 */ 4405#define TSDM_REG_NUM_OF_Q3_CMD 0x42250 4406/* [ST 32] The number of commands received in queue 4 */ 4407#define TSDM_REG_NUM_OF_Q4_CMD 0x42254 4408/* [ST 32] The number of commands received in queue 5 */ 4409#define TSDM_REG_NUM_OF_Q5_CMD 0x42258 4410/* [ST 32] The number of commands received in queue 6 */ 4411#define TSDM_REG_NUM_OF_Q6_CMD 0x4225c 4412/* [ST 32] The number of commands received in queue 7 */ 4413#define TSDM_REG_NUM_OF_Q7_CMD 0x42260 4414/* [ST 32] The number of commands received in queue 8 */ 4415#define TSDM_REG_NUM_OF_Q8_CMD 0x42264 4416/* [ST 32] The number of commands received in queue 9 */ 4417#define TSDM_REG_NUM_OF_Q9_CMD 0x42268 4418/* [RW 13] The start address in the internal RAM for the packet end message */ 4419#define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014 4420/* [RW 13] The start address in the internal RAM for queue counters */ 4421#define TSDM_REG_Q_COUNTER_START_ADDR 0x42010 4422/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 4423#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548 4424/* [R 1] parser fifo empty in sdm_sync block */ 4425#define TSDM_REG_SYNC_PARSER_EMPTY 0x42550 4426/* [R 1] parser serial fifo empty in sdm_sync block */ 4427#define TSDM_REG_SYNC_SYNC_EMPTY 0x42558 4428/* [RW 32] Tick for timer counter. Applicable only when 4429 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */ 4430#define TSDM_REG_TIMER_TICK 0x42000 4431/* [RW 32] Interrupt mask register #0 read/write */ 4432#define TSDM_REG_TSDM_INT_MASK_0 0x4229c 4433#define TSDM_REG_TSDM_INT_MASK_1 0x422ac 4434/* [R 32] Interrupt register #0 read */ 4435#define TSDM_REG_TSDM_INT_STS_0 0x42290 4436#define TSDM_REG_TSDM_INT_STS_1 0x422a0 4437/* [RW 11] Parity mask register #0 read/write */ 4438#define TSDM_REG_TSDM_PRTY_MASK 0x422bc 4439/* [R 11] Parity register #0 read */ 4440#define TSDM_REG_TSDM_PRTY_STS 0x422b0 4441/* [RC 11] Parity register #0 read clear */ 4442#define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4 4443/* [RW 5] The number of time_slots in the arbitration cycle */ 4444#define TSEM_REG_ARB_CYCLE_SIZE 0x180034 4445/* [RW 3] The source that is associated with arbitration element 0. Source 4446 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4447 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 4448#define TSEM_REG_ARB_ELEMENT0 0x180020 4449/* [RW 3] The source that is associated with arbitration element 1. Source 4450 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4451 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4452 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */ 4453#define TSEM_REG_ARB_ELEMENT1 0x180024 4454/* [RW 3] The source that is associated with arbitration element 2. Source 4455 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4456 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4457 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 4458 and ~tsem_registers_arb_element1.arb_element1 */ 4459#define TSEM_REG_ARB_ELEMENT2 0x180028 4460/* [RW 3] The source that is associated with arbitration element 3. Source 4461 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4462 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 4463 not be equal to register ~tsem_registers_arb_element0.arb_element0 and 4464 ~tsem_registers_arb_element1.arb_element1 and 4465 ~tsem_registers_arb_element2.arb_element2 */ 4466#define TSEM_REG_ARB_ELEMENT3 0x18002c 4467/* [RW 3] The source that is associated with arbitration element 4. Source 4468 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4469 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4470 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 4471 and ~tsem_registers_arb_element1.arb_element1 and 4472 ~tsem_registers_arb_element2.arb_element2 and 4473 ~tsem_registers_arb_element3.arb_element3 */ 4474#define TSEM_REG_ARB_ELEMENT4 0x180030 4475#define TSEM_REG_ENABLE_IN 0x1800a4 4476#define TSEM_REG_ENABLE_OUT 0x1800a8 4477/* [RW 32] This address space contains all registers and memories that are 4478 placed in SEM_FAST block. The SEM_FAST registers are described in 4479 appendix B. In order to access the sem_fast registers the base address 4480 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 4481#define TSEM_REG_FAST_MEMORY 0x1a0000 4482/* [RW 1] Disables input messages from FIC0 May be updated during run_time 4483 by the microcode */ 4484#define TSEM_REG_FIC0_DISABLE 0x180224 4485/* [RW 1] Disables input messages from FIC1 May be updated during run_time 4486 by the microcode */ 4487#define TSEM_REG_FIC1_DISABLE 0x180234 4488/* [RW 15] Interrupt table Read and write access to it is not possible in 4489 the middle of the work */ 4490#define TSEM_REG_INT_TABLE 0x180400 4491/* [ST 24] Statistics register. The number of messages that entered through 4492 FIC0 */ 4493#define TSEM_REG_MSG_NUM_FIC0 0x180000 4494/* [ST 24] Statistics register. The number of messages that entered through 4495 FIC1 */ 4496#define TSEM_REG_MSG_NUM_FIC1 0x180004 4497/* [ST 24] Statistics register. The number of messages that were sent to 4498 FOC0 */ 4499#define TSEM_REG_MSG_NUM_FOC0 0x180008 4500/* [ST 24] Statistics register. The number of messages that were sent to 4501 FOC1 */ 4502#define TSEM_REG_MSG_NUM_FOC1 0x18000c 4503/* [ST 24] Statistics register. The number of messages that were sent to 4504 FOC2 */ 4505#define TSEM_REG_MSG_NUM_FOC2 0x180010 4506/* [ST 24] Statistics register. The number of messages that were sent to 4507 FOC3 */ 4508#define TSEM_REG_MSG_NUM_FOC3 0x180014 4509/* [RW 1] Disables input messages from the passive buffer May be updated 4510 during run_time by the microcode */ 4511#define TSEM_REG_PAS_DISABLE 0x18024c 4512/* [WB 128] Debug only. Passive buffer memory */ 4513#define TSEM_REG_PASSIVE_BUFFER 0x181000 4514/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 4515#define TSEM_REG_PRAM 0x1c0000 4516/* [R 8] Valid sleeping threads indication have bit per thread */ 4517#define TSEM_REG_SLEEP_THREADS_VALID 0x18026c 4518/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 4519#define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0 4520/* [RW 8] List of free threads . There is a bit per thread. */ 4521#define TSEM_REG_THREADS_LIST 0x1802e4 4522/* [RC 32] Parity register #0 read clear */ 4523#define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118 4524#define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128 4525/* [RW 3] The arbitration scheme of time_slot 0 */ 4526#define TSEM_REG_TS_0_AS 0x180038 4527/* [RW 3] The arbitration scheme of time_slot 10 */ 4528#define TSEM_REG_TS_10_AS 0x180060 4529/* [RW 3] The arbitration scheme of time_slot 11 */ 4530#define TSEM_REG_TS_11_AS 0x180064 4531/* [RW 3] The arbitration scheme of time_slot 12 */ 4532#define TSEM_REG_TS_12_AS 0x180068 4533/* [RW 3] The arbitration scheme of time_slot 13 */ 4534#define TSEM_REG_TS_13_AS 0x18006c 4535/* [RW 3] The arbitration scheme of time_slot 14 */ 4536#define TSEM_REG_TS_14_AS 0x180070 4537/* [RW 3] The arbitration scheme of time_slot 15 */ 4538#define TSEM_REG_TS_15_AS 0x180074 4539/* [RW 3] The arbitration scheme of time_slot 16 */ 4540#define TSEM_REG_TS_16_AS 0x180078 4541/* [RW 3] The arbitration scheme of time_slot 17 */ 4542#define TSEM_REG_TS_17_AS 0x18007c 4543/* [RW 3] The arbitration scheme of time_slot 18 */ 4544#define TSEM_REG_TS_18_AS 0x180080 4545/* [RW 3] The arbitration scheme of time_slot 1 */ 4546#define TSEM_REG_TS_1_AS 0x18003c 4547/* [RW 3] The arbitration scheme of time_slot 2 */ 4548#define TSEM_REG_TS_2_AS 0x180040 4549/* [RW 3] The arbitration scheme of time_slot 3 */ 4550#define TSEM_REG_TS_3_AS 0x180044 4551/* [RW 3] The arbitration scheme of time_slot 4 */ 4552#define TSEM_REG_TS_4_AS 0x180048 4553/* [RW 3] The arbitration scheme of time_slot 5 */ 4554#define TSEM_REG_TS_5_AS 0x18004c 4555/* [RW 3] The arbitration scheme of time_slot 6 */ 4556#define TSEM_REG_TS_6_AS 0x180050 4557/* [RW 3] The arbitration scheme of time_slot 7 */ 4558#define TSEM_REG_TS_7_AS 0x180054 4559/* [RW 3] The arbitration scheme of time_slot 8 */ 4560#define TSEM_REG_TS_8_AS 0x180058 4561/* [RW 3] The arbitration scheme of time_slot 9 */ 4562#define TSEM_REG_TS_9_AS 0x18005c 4563/* [RW 32] Interrupt mask register #0 read/write */ 4564#define TSEM_REG_TSEM_INT_MASK_0 0x180100 4565#define TSEM_REG_TSEM_INT_MASK_1 0x180110 4566/* [R 32] Interrupt register #0 read */ 4567#define TSEM_REG_TSEM_INT_STS_0 0x1800f4 4568#define TSEM_REG_TSEM_INT_STS_1 0x180104 4569/* [RW 32] Parity mask register #0 read/write */ 4570#define TSEM_REG_TSEM_PRTY_MASK_0 0x180120 4571#define TSEM_REG_TSEM_PRTY_MASK_1 0x180130 4572/* [R 32] Parity register #0 read */ 4573#define TSEM_REG_TSEM_PRTY_STS_0 0x180114 4574#define TSEM_REG_TSEM_PRTY_STS_1 0x180124 4575/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 4576 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 4577#define TSEM_REG_VFPF_ERR_NUM 0x180380 4578/* [RW 32] Indirect access to AG context with 32-bits granularity. The bits 4579 * [10:8] of the address should be the offset within the accessed LCID 4580 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10 4581 * LCID100. The RBC address should be 12'ha64. */ 4582#define UCM_REG_AG_CTX 0xe2000 4583/* [R 5] Used to read the XX protection CAM occupancy counter. */ 4584#define UCM_REG_CAM_OCCUP 0xe0170 4585/* [RW 1] CDU AG read Interface enable. If 0 - the request input is 4586 disregarded; valid output is deasserted; all other signals are treated as 4587 usual; if 1 - normal activity. */ 4588#define UCM_REG_CDU_AG_RD_IFEN 0xe0038 4589/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 4590 are disregarded; all other signals are treated as usual; if 1 - normal 4591 activity. */ 4592#define UCM_REG_CDU_AG_WR_IFEN 0xe0034 4593/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 4594 disregarded; valid output is deasserted; all other signals are treated as 4595 usual; if 1 - normal activity. */ 4596#define UCM_REG_CDU_SM_RD_IFEN 0xe0040 4597/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 4598 input is disregarded; all other signals are treated as usual; if 1 - 4599 normal activity. */ 4600#define UCM_REG_CDU_SM_WR_IFEN 0xe003c 4601/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 4602 the initial credit value; read returns the current value of the credit 4603 counter. Must be initialized to 1 at start-up. */ 4604#define UCM_REG_CFC_INIT_CRD 0xe0204 4605/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 4606 weight 8 (the most prioritised); 1 stands for weight 1(least 4607 prioritised); 2 stands for weight 2; tc. */ 4608#define UCM_REG_CP_WEIGHT 0xe00c4 4609/* [RW 1] Input csem Interface enable. If 0 - the valid input is 4610 disregarded; acknowledge output is deasserted; all other signals are 4611 treated as usual; if 1 - normal activity. */ 4612#define UCM_REG_CSEM_IFEN 0xe0028 4613/* [RC 1] Set when the message length mismatch (relative to last indication) 4614 at the csem interface is detected. */ 4615#define UCM_REG_CSEM_LENGTH_MIS 0xe0160 4616/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for 4617 weight 8 (the most prioritised); 1 stands for weight 1(least 4618 prioritised); 2 stands for weight 2; tc. */ 4619#define UCM_REG_CSEM_WEIGHT 0xe00b8 4620/* [RW 1] Input dorq Interface enable. If 0 - the valid input is 4621 disregarded; acknowledge output is deasserted; all other signals are 4622 treated as usual; if 1 - normal activity. */ 4623#define UCM_REG_DORQ_IFEN 0xe0030 4624/* [RC 1] Set when the message length mismatch (relative to last indication) 4625 at the dorq interface is detected. */ 4626#define UCM_REG_DORQ_LENGTH_MIS 0xe0168 4627/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for 4628 weight 8 (the most prioritised); 1 stands for weight 1(least 4629 prioritised); 2 stands for weight 2; tc. */ 4630#define UCM_REG_DORQ_WEIGHT 0xe00c0 4631/* [RW 8] The Event ID in case ErrorFlg input message bit is set. */ 4632#define UCM_REG_ERR_EVNT_ID 0xe00a4 4633/* [RW 28] The CM erroneous header for QM and Timers formatting. */ 4634#define UCM_REG_ERR_UCM_HDR 0xe00a0 4635/* [RW 8] The Event ID for Timers expiration. */ 4636#define UCM_REG_EXPR_EVNT_ID 0xe00a8 4637/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 4638 writes the initial credit value; read returns the current value of the 4639 credit counter. Must be initialized to 64 at start-up. */ 4640#define UCM_REG_FIC0_INIT_CRD 0xe020c 4641/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 4642 writes the initial credit value; read returns the current value of the 4643 credit counter. Must be initialized to 64 at start-up. */ 4644#define UCM_REG_FIC1_INIT_CRD 0xe0210 4645/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 4646 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr; 4647 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and 4648 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */ 4649#define UCM_REG_GR_ARB_TYPE 0xe0144 4650/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 4651 highest priority is 3. It is supposed that the Store channel group is 4652 compliment to the others. */ 4653#define UCM_REG_GR_LD0_PR 0xe014c 4654/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 4655 highest priority is 3. It is supposed that the Store channel group is 4656 compliment to the others. */ 4657#define UCM_REG_GR_LD1_PR 0xe0150 4658/* [RW 2] The queue index for invalidate counter flag decision. */ 4659#define UCM_REG_INV_CFLG_Q 0xe00e4 4660/* [RW 5] The number of double REG-pairs; loaded from the STORM context and 4661 sent to STORM; for a specific connection type. the double REG-pairs are 4662 used in order to align to STORM context row size of 128 bits. The offset 4663 of these data in the STORM context is always 0. Index _i stands for the 4664 connection type (one of 16). */ 4665#define UCM_REG_N_SM_CTX_LD_0 0xe0054 4666#define UCM_REG_N_SM_CTX_LD_1 0xe0058 4667#define UCM_REG_N_SM_CTX_LD_2 0xe005c 4668#define UCM_REG_N_SM_CTX_LD_3 0xe0060 4669#define UCM_REG_N_SM_CTX_LD_4 0xe0064 4670#define UCM_REG_N_SM_CTX_LD_5 0xe0068 4671#define UCM_REG_PHYS_QNUM0_0 0xe0110 4672#define UCM_REG_PHYS_QNUM0_1 0xe0114 4673#define UCM_REG_PHYS_QNUM1_0 0xe0118 4674#define UCM_REG_PHYS_QNUM1_1 0xe011c 4675#define UCM_REG_PHYS_QNUM2_0 0xe0120 4676#define UCM_REG_PHYS_QNUM2_1 0xe0124 4677#define UCM_REG_PHYS_QNUM3_0 0xe0128 4678#define UCM_REG_PHYS_QNUM3_1 0xe012c 4679/* [RW 8] The Event ID for Timers formatting in case of stop done. */ 4680#define UCM_REG_STOP_EVNT_ID 0xe00ac 4681/* [RC 1] Set when the message length mismatch (relative to last indication) 4682 at the STORM interface is detected. */ 4683#define UCM_REG_STORM_LENGTH_MIS 0xe0154 4684/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 4685 disregarded; acknowledge output is deasserted; all other signals are 4686 treated as usual; if 1 - normal activity. */ 4687#define UCM_REG_STORM_UCM_IFEN 0xe0010 4688/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for 4689 weight 8 (the most prioritised); 1 stands for weight 1(least 4690 prioritised); 2 stands for weight 2; tc. */ 4691#define UCM_REG_STORM_WEIGHT 0xe00b0 4692/* [RW 4] Timers output initial credit. Max credit available - 15.Write 4693 writes the initial credit value; read returns the current value of the 4694 credit counter. Must be initialized to 4 at start-up. */ 4695#define UCM_REG_TM_INIT_CRD 0xe021c 4696/* [RW 28] The CM header for Timers expiration command. */ 4697#define UCM_REG_TM_UCM_HDR 0xe009c 4698/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 4699 disregarded; acknowledge output is deasserted; all other signals are 4700 treated as usual; if 1 - normal activity. */ 4701#define UCM_REG_TM_UCM_IFEN 0xe001c 4702/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for 4703 weight 8 (the most prioritised); 1 stands for weight 1(least 4704 prioritised); 2 stands for weight 2; tc. */ 4705#define UCM_REG_TM_WEIGHT 0xe00d4 4706/* [RW 1] Input tsem Interface enable. If 0 - the valid input is 4707 disregarded; acknowledge output is deasserted; all other signals are 4708 treated as usual; if 1 - normal activity. */ 4709#define UCM_REG_TSEM_IFEN 0xe0024 4710/* [RC 1] Set when the message length mismatch (relative to last indication) 4711 at the tsem interface is detected. */ 4712#define UCM_REG_TSEM_LENGTH_MIS 0xe015c 4713/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 4714 weight 8 (the most prioritised); 1 stands for weight 1(least 4715 prioritised); 2 stands for weight 2; tc. */ 4716#define UCM_REG_TSEM_WEIGHT 0xe00b4 4717/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 4718 acknowledge output is deasserted; all other signals are treated as usual; 4719 if 1 - normal activity. */ 4720#define UCM_REG_UCM_CFC_IFEN 0xe0044 4721/* [RW 11] Interrupt mask register #0 read/write */ 4722#define UCM_REG_UCM_INT_MASK 0xe01d4 4723/* [R 11] Interrupt register #0 read */ 4724#define UCM_REG_UCM_INT_STS 0xe01c8 4725/* [RW 27] Parity mask register #0 read/write */ 4726#define UCM_REG_UCM_PRTY_MASK 0xe01e4 4727/* [R 27] Parity register #0 read */ 4728#define UCM_REG_UCM_PRTY_STS 0xe01d8 4729/* [RC 27] Parity register #0 read clear */ 4730#define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc 4731/* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS 4732 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 4733 Is used to determine the number of the AG context REG-pairs written back; 4734 when the Reg1WbFlg isn't set. */ 4735#define UCM_REG_UCM_REG0_SZ 0xe00dc 4736/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 4737 disregarded; valid is deasserted; all other signals are treated as usual; 4738 if 1 - normal activity. */ 4739#define UCM_REG_UCM_STORM0_IFEN 0xe0004 4740/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 4741 disregarded; valid is deasserted; all other signals are treated as usual; 4742 if 1 - normal activity. */ 4743#define UCM_REG_UCM_STORM1_IFEN 0xe0008 4744/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is 4745 disregarded; acknowledge output is deasserted; all other signals are 4746 treated as usual; if 1 - normal activity. */ 4747#define UCM_REG_UCM_TM_IFEN 0xe0020 4748/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 4749 disregarded; valid is deasserted; all other signals are treated as usual; 4750 if 1 - normal activity. */ 4751#define UCM_REG_UCM_UQM_IFEN 0xe000c 4752/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 4753#define UCM_REG_UCM_UQM_USE_Q 0xe00d8 4754/* [RW 6] QM output initial credit. Max credit available - 32.Write writes 4755 the initial credit value; read returns the current value of the credit 4756 counter. Must be initialized to 32 at start-up. */ 4757#define UCM_REG_UQM_INIT_CRD 0xe0220 4758/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 4759 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4760 prioritised); 2 stands for weight 2; tc. */ 4761#define UCM_REG_UQM_P_WEIGHT 0xe00cc 4762/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 4763 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4764 prioritised); 2 stands for weight 2; tc. */ 4765#define UCM_REG_UQM_S_WEIGHT 0xe00d0 4766/* [RW 28] The CM header value for QM request (primary). */ 4767#define UCM_REG_UQM_UCM_HDR_P 0xe0094 4768/* [RW 28] The CM header value for QM request (secondary). */ 4769#define UCM_REG_UQM_UCM_HDR_S 0xe0098 4770/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 4771 acknowledge output is deasserted; all other signals are treated as usual; 4772 if 1 - normal activity. */ 4773#define UCM_REG_UQM_UCM_IFEN 0xe0014 4774/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 4775 acknowledge output is deasserted; all other signals are treated as usual; 4776 if 1 - normal activity. */ 4777#define UCM_REG_USDM_IFEN 0xe0018 4778/* [RC 1] Set when the message length mismatch (relative to last indication) 4779 at the SDM interface is detected. */ 4780#define UCM_REG_USDM_LENGTH_MIS 0xe0158 4781/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 4782 weight 8 (the most prioritised); 1 stands for weight 1(least 4783 prioritised); 2 stands for weight 2; tc. */ 4784#define UCM_REG_USDM_WEIGHT 0xe00c8 4785/* [RW 1] Input xsem Interface enable. If 0 - the valid input is 4786 disregarded; acknowledge output is deasserted; all other signals are 4787 treated as usual; if 1 - normal activity. */ 4788#define UCM_REG_XSEM_IFEN 0xe002c 4789/* [RC 1] Set when the message length mismatch (relative to last indication) 4790 at the xsem interface isdetected. */ 4791#define UCM_REG_XSEM_LENGTH_MIS 0xe0164 4792/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for 4793 weight 8 (the most prioritised); 1 stands for weight 1(least 4794 prioritised); 2 stands for weight 2; tc. */ 4795#define UCM_REG_XSEM_WEIGHT 0xe00bc 4796/* [RW 20] Indirect access to the descriptor table of the XX protection 4797 mechanism. The fields are:[5:0] - message length; 14:6] - message 4798 pointer; 19:15] - next pointer. */ 4799#define UCM_REG_XX_DESCR_TABLE 0xe0280 4800#define UCM_REG_XX_DESCR_TABLE_SIZE 27 4801/* [R 6] Use to read the XX protection Free counter. */ 4802#define UCM_REG_XX_FREE 0xe016c 4803/* [RW 6] Initial value for the credit counter; responsible for fulfilling 4804 of the Input Stage XX protection buffer by the XX protection pending 4805 messages. Write writes the initial credit value; read returns the current 4806 value of the credit counter. Must be initialized to 12 at start-up. */ 4807#define UCM_REG_XX_INIT_CRD 0xe0224 4808/* [RW 6] The maximum number of pending messages; which may be stored in XX 4809 protection. ~ucm_registers_xx_free.xx_free read on read. */ 4810#define UCM_REG_XX_MSG_NUM 0xe0228 4811/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 4812#define UCM_REG_XX_OVFL_EVNT_ID 0xe004c 4813/* [RW 16] Indirect access to the XX table of the XX protection mechanism. 4814 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] - 4815 header pointer. */ 4816#define UCM_REG_XX_TABLE 0xe0300 4817#define UMAC_COMMAND_CONFIG_REG_HD_ENA (0x1<<10) 4818#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1<<28) 4819#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15) 4820#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24) 4821#define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5) 4822#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1<<8) 4823#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4) 4824#define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1) 4825#define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13) 4826#define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0) 4827#define UMAC_REG_COMMAND_CONFIG 0x8 4828/* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers 4829 * to bit 17 of the MAC address etc. */ 4830#define UMAC_REG_MAC_ADDR0 0xc 4831/* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1 4832 * refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved. */ 4833#define UMAC_REG_MAC_ADDR1 0x10 4834/* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive 4835 * logic to check frames. */ 4836#define UMAC_REG_MAXFR 0x14 4837/* [RW 8] The event id for aggregated interrupt 0 */ 4838#define USDM_REG_AGG_INT_EVENT_0 0xc4038 4839#define USDM_REG_AGG_INT_EVENT_1 0xc403c 4840#define USDM_REG_AGG_INT_EVENT_2 0xc4040 4841#define USDM_REG_AGG_INT_EVENT_4 0xc4048 4842#define USDM_REG_AGG_INT_EVENT_5 0xc404c 4843#define USDM_REG_AGG_INT_EVENT_6 0xc4050 4844/* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 4845 or auto-mask-mode (1) */ 4846#define USDM_REG_AGG_INT_MODE_0 0xc41b8 4847#define USDM_REG_AGG_INT_MODE_1 0xc41bc 4848#define USDM_REG_AGG_INT_MODE_4 0xc41c8 4849#define USDM_REG_AGG_INT_MODE_5 0xc41cc 4850#define USDM_REG_AGG_INT_MODE_6 0xc41d0 4851/* [RW 1] The T bit for aggregated interrupt 5 */ 4852#define USDM_REG_AGG_INT_T_5 0xc40cc 4853#define USDM_REG_AGG_INT_T_6 0xc40d0 4854/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 4855#define USDM_REG_CFC_RSP_START_ADDR 0xc4008 4856/* [RW 16] The maximum value of the completion counter #0 */ 4857#define USDM_REG_CMP_COUNTER_MAX0 0xc401c 4858/* [RW 16] The maximum value of the completion counter #1 */ 4859#define USDM_REG_CMP_COUNTER_MAX1 0xc4020 4860/* [RW 16] The maximum value of the completion counter #2 */ 4861#define USDM_REG_CMP_COUNTER_MAX2 0xc4024 4862/* [RW 16] The maximum value of the completion counter #3 */ 4863#define USDM_REG_CMP_COUNTER_MAX3 0xc4028 4864/* [RW 13] The start address in the internal RAM for the completion 4865 counters. */ 4866#define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c 4867#define USDM_REG_ENABLE_IN1 0xc4238 4868#define USDM_REG_ENABLE_IN2 0xc423c 4869#define USDM_REG_ENABLE_OUT1 0xc4240 4870#define USDM_REG_ENABLE_OUT2 0xc4244 4871/* [RW 4] The initial number of messages that can be sent to the pxp control 4872 interface without receiving any ACK. */ 4873#define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0 4874/* [ST 32] The number of ACK after placement messages received */ 4875#define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280 4876/* [ST 32] The number of packet end messages received from the parser */ 4877#define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278 4878/* [ST 32] The number of requests received from the pxp async if */ 4879#define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c 4880/* [ST 32] The number of commands received in queue 0 */ 4881#define USDM_REG_NUM_OF_Q0_CMD 0xc4248 4882/* [ST 32] The number of commands received in queue 10 */ 4883#define USDM_REG_NUM_OF_Q10_CMD 0xc4270 4884/* [ST 32] The number of commands received in queue 11 */ 4885#define USDM_REG_NUM_OF_Q11_CMD 0xc4274 4886/* [ST 32] The number of commands received in queue 1 */ 4887#define USDM_REG_NUM_OF_Q1_CMD 0xc424c 4888/* [ST 32] The number of commands received in queue 2 */ 4889#define USDM_REG_NUM_OF_Q2_CMD 0xc4250 4890/* [ST 32] The number of commands received in queue 3 */ 4891#define USDM_REG_NUM_OF_Q3_CMD 0xc4254 4892/* [ST 32] The number of commands received in queue 4 */ 4893#define USDM_REG_NUM_OF_Q4_CMD 0xc4258 4894/* [ST 32] The number of commands received in queue 5 */ 4895#define USDM_REG_NUM_OF_Q5_CMD 0xc425c 4896/* [ST 32] The number of commands received in queue 6 */ 4897#define USDM_REG_NUM_OF_Q6_CMD 0xc4260 4898/* [ST 32] The number of commands received in queue 7 */ 4899#define USDM_REG_NUM_OF_Q7_CMD 0xc4264 4900/* [ST 32] The number of commands received in queue 8 */ 4901#define USDM_REG_NUM_OF_Q8_CMD 0xc4268 4902/* [ST 32] The number of commands received in queue 9 */ 4903#define USDM_REG_NUM_OF_Q9_CMD 0xc426c 4904/* [RW 13] The start address in the internal RAM for the packet end message */ 4905#define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014 4906/* [RW 13] The start address in the internal RAM for queue counters */ 4907#define USDM_REG_Q_COUNTER_START_ADDR 0xc4010 4908/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 4909#define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550 4910/* [R 1] parser fifo empty in sdm_sync block */ 4911#define USDM_REG_SYNC_PARSER_EMPTY 0xc4558 4912/* [R 1] parser serial fifo empty in sdm_sync block */ 4913#define USDM_REG_SYNC_SYNC_EMPTY 0xc4560 4914/* [RW 32] Tick for timer counter. Applicable only when 4915 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */ 4916#define USDM_REG_TIMER_TICK 0xc4000 4917/* [RW 32] Interrupt mask register #0 read/write */ 4918#define USDM_REG_USDM_INT_MASK_0 0xc42a0 4919#define USDM_REG_USDM_INT_MASK_1 0xc42b0 4920/* [R 32] Interrupt register #0 read */ 4921#define USDM_REG_USDM_INT_STS_0 0xc4294 4922#define USDM_REG_USDM_INT_STS_1 0xc42a4 4923/* [RW 11] Parity mask register #0 read/write */ 4924#define USDM_REG_USDM_PRTY_MASK 0xc42c0 4925/* [R 11] Parity register #0 read */ 4926#define USDM_REG_USDM_PRTY_STS 0xc42b4 4927/* [RC 11] Parity register #0 read clear */ 4928#define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8 4929/* [RW 5] The number of time_slots in the arbitration cycle */ 4930#define USEM_REG_ARB_CYCLE_SIZE 0x300034 4931/* [RW 3] The source that is associated with arbitration element 0. Source 4932 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4933 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 4934#define USEM_REG_ARB_ELEMENT0 0x300020 4935/* [RW 3] The source that is associated with arbitration element 1. Source 4936 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4937 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4938 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */ 4939#define USEM_REG_ARB_ELEMENT1 0x300024 4940/* [RW 3] The source that is associated with arbitration element 2. Source 4941 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4942 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4943 Could not be equal to register ~usem_registers_arb_element0.arb_element0 4944 and ~usem_registers_arb_element1.arb_element1 */ 4945#define USEM_REG_ARB_ELEMENT2 0x300028 4946/* [RW 3] The source that is associated with arbitration element 3. Source 4947 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4948 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 4949 not be equal to register ~usem_registers_arb_element0.arb_element0 and 4950 ~usem_registers_arb_element1.arb_element1 and 4951 ~usem_registers_arb_element2.arb_element2 */ 4952#define USEM_REG_ARB_ELEMENT3 0x30002c 4953/* [RW 3] The source that is associated with arbitration element 4. Source 4954 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4955 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4956 Could not be equal to register ~usem_registers_arb_element0.arb_element0 4957 and ~usem_registers_arb_element1.arb_element1 and 4958 ~usem_registers_arb_element2.arb_element2 and 4959 ~usem_registers_arb_element3.arb_element3 */ 4960#define USEM_REG_ARB_ELEMENT4 0x300030 4961#define USEM_REG_ENABLE_IN 0x3000a4 4962#define USEM_REG_ENABLE_OUT 0x3000a8 4963/* [RW 32] This address space contains all registers and memories that are 4964 placed in SEM_FAST block. The SEM_FAST registers are described in 4965 appendix B. In order to access the sem_fast registers the base address 4966 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 4967#define USEM_REG_FAST_MEMORY 0x320000 4968/* [RW 1] Disables input messages from FIC0 May be updated during run_time 4969 by the microcode */ 4970#define USEM_REG_FIC0_DISABLE 0x300224 4971/* [RW 1] Disables input messages from FIC1 May be updated during run_time 4972 by the microcode */ 4973#define USEM_REG_FIC1_DISABLE 0x300234 4974/* [RW 15] Interrupt table Read and write access to it is not possible in 4975 the middle of the work */ 4976#define USEM_REG_INT_TABLE 0x300400 4977/* [ST 24] Statistics register. The number of messages that entered through 4978 FIC0 */ 4979#define USEM_REG_MSG_NUM_FIC0 0x300000 4980/* [ST 24] Statistics register. The number of messages that entered through 4981 FIC1 */ 4982#define USEM_REG_MSG_NUM_FIC1 0x300004 4983/* [ST 24] Statistics register. The number of messages that were sent to 4984 FOC0 */ 4985#define USEM_REG_MSG_NUM_FOC0 0x300008 4986/* [ST 24] Statistics register. The number of messages that were sent to 4987 FOC1 */ 4988#define USEM_REG_MSG_NUM_FOC1 0x30000c 4989/* [ST 24] Statistics register. The number of messages that were sent to 4990 FOC2 */ 4991#define USEM_REG_MSG_NUM_FOC2 0x300010 4992/* [ST 24] Statistics register. The number of messages that were sent to 4993 FOC3 */ 4994#define USEM_REG_MSG_NUM_FOC3 0x300014 4995/* [RW 1] Disables input messages from the passive buffer May be updated 4996 during run_time by the microcode */ 4997#define USEM_REG_PAS_DISABLE 0x30024c 4998/* [WB 128] Debug only. Passive buffer memory */ 4999#define USEM_REG_PASSIVE_BUFFER 0x302000 5000/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 5001#define USEM_REG_PRAM 0x340000 5002/* [R 16] Valid sleeping threads indication have bit per thread */ 5003#define USEM_REG_SLEEP_THREADS_VALID 0x30026c 5004/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 5005#define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0 5006/* [RW 16] List of free threads . There is a bit per thread. */ 5007#define USEM_REG_THREADS_LIST 0x3002e4 5008/* [RW 3] The arbitration scheme of time_slot 0 */ 5009#define USEM_REG_TS_0_AS 0x300038 5010/* [RW 3] The arbitration scheme of time_slot 10 */ 5011#define USEM_REG_TS_10_AS 0x300060 5012/* [RW 3] The arbitration scheme of time_slot 11 */ 5013#define USEM_REG_TS_11_AS 0x300064 5014/* [RW 3] The arbitration scheme of time_slot 12 */ 5015#define USEM_REG_TS_12_AS 0x300068 5016/* [RW 3] The arbitration scheme of time_slot 13 */ 5017#define USEM_REG_TS_13_AS 0x30006c 5018/* [RW 3] The arbitration scheme of time_slot 14 */ 5019#define USEM_REG_TS_14_AS 0x300070 5020/* [RW 3] The arbitration scheme of time_slot 15 */ 5021#define USEM_REG_TS_15_AS 0x300074 5022/* [RW 3] The arbitration scheme of time_slot 16 */ 5023#define USEM_REG_TS_16_AS 0x300078 5024/* [RW 3] The arbitration scheme of time_slot 17 */ 5025#define USEM_REG_TS_17_AS 0x30007c 5026/* [RW 3] The arbitration scheme of time_slot 18 */ 5027#define USEM_REG_TS_18_AS 0x300080 5028/* [RW 3] The arbitration scheme of time_slot 1 */ 5029#define USEM_REG_TS_1_AS 0x30003c 5030/* [RW 3] The arbitration scheme of time_slot 2 */ 5031#define USEM_REG_TS_2_AS 0x300040 5032/* [RW 3] The arbitration scheme of time_slot 3 */ 5033#define USEM_REG_TS_3_AS 0x300044 5034/* [RW 3] The arbitration scheme of time_slot 4 */ 5035#define USEM_REG_TS_4_AS 0x300048 5036/* [RW 3] The arbitration scheme of time_slot 5 */ 5037#define USEM_REG_TS_5_AS 0x30004c 5038/* [RW 3] The arbitration scheme of time_slot 6 */ 5039#define USEM_REG_TS_6_AS 0x300050 5040/* [RW 3] The arbitration scheme of time_slot 7 */ 5041#define USEM_REG_TS_7_AS 0x300054 5042/* [RW 3] The arbitration scheme of time_slot 8 */ 5043#define USEM_REG_TS_8_AS 0x300058 5044/* [RW 3] The arbitration scheme of time_slot 9 */ 5045#define USEM_REG_TS_9_AS 0x30005c 5046/* [RW 32] Interrupt mask register #0 read/write */ 5047#define USEM_REG_USEM_INT_MASK_0 0x300110 5048#define USEM_REG_USEM_INT_MASK_1 0x300120 5049/* [R 32] Interrupt register #0 read */ 5050#define USEM_REG_USEM_INT_STS_0 0x300104 5051#define USEM_REG_USEM_INT_STS_1 0x300114 5052/* [RW 32] Parity mask register #0 read/write */ 5053#define USEM_REG_USEM_PRTY_MASK_0 0x300130 5054#define USEM_REG_USEM_PRTY_MASK_1 0x300140 5055/* [R 32] Parity register #0 read */ 5056#define USEM_REG_USEM_PRTY_STS_0 0x300124 5057#define USEM_REG_USEM_PRTY_STS_1 0x300134 5058/* [RC 32] Parity register #0 read clear */ 5059#define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128 5060#define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138 5061/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 5062 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 5063#define USEM_REG_VFPF_ERR_NUM 0x300380 5064#define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0) 5065#define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1) 5066#define VFC_REG_MEMORIES_RST 0x1943c 5067/* [RW 32] Indirect access to AG context with 32-bits granularity. The bits 5068 * [12:8] of the address should be the offset within the accessed LCID 5069 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10 5070 * LCID100. The RBC address should be 13'ha64. */ 5071#define XCM_REG_AG_CTX 0x28000 5072/* [RW 2] The queue index for registration on Aux1 counter flag. */ 5073#define XCM_REG_AUX1_Q 0x20134 5074/* [RW 2] Per each decision rule the queue index to register to. */ 5075#define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0 5076/* [R 5] Used to read the XX protection CAM occupancy counter. */ 5077#define XCM_REG_CAM_OCCUP 0x20244 5078/* [RW 1] CDU AG read Interface enable. If 0 - the request input is 5079 disregarded; valid output is deasserted; all other signals are treated as 5080 usual; if 1 - normal activity. */ 5081#define XCM_REG_CDU_AG_RD_IFEN 0x20044 5082/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 5083 are disregarded; all other signals are treated as usual; if 1 - normal 5084 activity. */ 5085#define XCM_REG_CDU_AG_WR_IFEN 0x20040 5086/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 5087 disregarded; valid output is deasserted; all other signals are treated as 5088 usual; if 1 - normal activity. */ 5089#define XCM_REG_CDU_SM_RD_IFEN 0x2004c 5090/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 5091 input is disregarded; all other signals are treated as usual; if 1 - 5092 normal activity. */ 5093#define XCM_REG_CDU_SM_WR_IFEN 0x20048 5094/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 5095 the initial credit value; read returns the current value of the credit 5096 counter. Must be initialized to 1 at start-up. */ 5097#define XCM_REG_CFC_INIT_CRD 0x20404 5098/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 5099 weight 8 (the most prioritised); 1 stands for weight 1(least 5100 prioritised); 2 stands for weight 2; tc. */ 5101#define XCM_REG_CP_WEIGHT 0x200dc 5102/* [RW 1] Input csem Interface enable. If 0 - the valid input is 5103 disregarded; acknowledge output is deasserted; all other signals are 5104 treated as usual; if 1 - normal activity. */ 5105#define XCM_REG_CSEM_IFEN 0x20028 5106/* [RC 1] Set at message length mismatch (relative to last indication) at 5107 the csem interface. */ 5108#define XCM_REG_CSEM_LENGTH_MIS 0x20228 5109/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for 5110 weight 8 (the most prioritised); 1 stands for weight 1(least 5111 prioritised); 2 stands for weight 2; tc. */ 5112#define XCM_REG_CSEM_WEIGHT 0x200c4 5113/* [RW 1] Input dorq Interface enable. If 0 - the valid input is 5114 disregarded; acknowledge output is deasserted; all other signals are 5115 treated as usual; if 1 - normal activity. */ 5116#define XCM_REG_DORQ_IFEN 0x20030 5117/* [RC 1] Set at message length mismatch (relative to last indication) at 5118 the dorq interface. */ 5119#define XCM_REG_DORQ_LENGTH_MIS 0x20230 5120/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for 5121 weight 8 (the most prioritised); 1 stands for weight 1(least 5122 prioritised); 2 stands for weight 2; tc. */ 5123#define XCM_REG_DORQ_WEIGHT 0x200cc 5124/* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */ 5125#define XCM_REG_ERR_EVNT_ID 0x200b0 5126/* [RW 28] The CM erroneous header for QM and Timers formatting. */ 5127#define XCM_REG_ERR_XCM_HDR 0x200ac 5128/* [RW 8] The Event ID for Timers expiration. */ 5129#define XCM_REG_EXPR_EVNT_ID 0x200b4 5130/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 5131 writes the initial credit value; read returns the current value of the 5132 credit counter. Must be initialized to 64 at start-up. */ 5133#define XCM_REG_FIC0_INIT_CRD 0x2040c 5134/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 5135 writes the initial credit value; read returns the current value of the 5136 credit counter. Must be initialized to 64 at start-up. */ 5137#define XCM_REG_FIC1_INIT_CRD 0x20410 5138#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118 5139#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c 5140#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108 5141#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c 5142/* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1 5143 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr; 5144 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and 5145 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */ 5146#define XCM_REG_GR_ARB_TYPE 0x2020c 5147/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 5148 highest priority is 3. It is supposed that the Channel group is the 5149 compliment of the other 3 groups. */ 5150#define XCM_REG_GR_LD0_PR 0x20214 5151/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 5152 highest priority is 3. It is supposed that the Channel group is the 5153 compliment of the other 3 groups. */ 5154#define XCM_REG_GR_LD1_PR 0x20218 5155/* [RW 1] Input nig0 Interface enable. If 0 - the valid input is 5156 disregarded; acknowledge output is deasserted; all other signals are 5157 treated as usual; if 1 - normal activity. */ 5158#define XCM_REG_NIG0_IFEN 0x20038 5159/* [RC 1] Set at message length mismatch (relative to last indication) at 5160 the nig0 interface. */ 5161#define XCM_REG_NIG0_LENGTH_MIS 0x20238 5162/* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for 5163 weight 8 (the most prioritised); 1 stands for weight 1(least 5164 prioritised); 2 stands for weight 2; tc. */ 5165#define XCM_REG_NIG0_WEIGHT 0x200d4 5166/* [RW 1] Input nig1 Interface enable. If 0 - the valid input is 5167 disregarded; acknowledge output is deasserted; all other signals are 5168 treated as usual; if 1 - normal activity. */ 5169#define XCM_REG_NIG1_IFEN 0x2003c 5170/* [RC 1] Set at message length mismatch (relative to last indication) at 5171 the nig1 interface. */ 5172#define XCM_REG_NIG1_LENGTH_MIS 0x2023c 5173/* [RW 5] The number of double REG-pairs; loaded from the STORM context and 5174 sent to STORM; for a specific connection type. The double REG-pairs are 5175 used in order to align to STORM context row size of 128 bits. The offset 5176 of these data in the STORM context is always 0. Index _i stands for the 5177 connection type (one of 16). */ 5178#define XCM_REG_N_SM_CTX_LD_0 0x20060 5179#define XCM_REG_N_SM_CTX_LD_1 0x20064 5180#define XCM_REG_N_SM_CTX_LD_2 0x20068 5181#define XCM_REG_N_SM_CTX_LD_3 0x2006c 5182#define XCM_REG_N_SM_CTX_LD_4 0x20070 5183#define XCM_REG_N_SM_CTX_LD_5 0x20074 5184/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 5185 acknowledge output is deasserted; all other signals are treated as usual; 5186 if 1 - normal activity. */ 5187#define XCM_REG_PBF_IFEN 0x20034 5188/* [RC 1] Set at message length mismatch (relative to last indication) at 5189 the pbf interface. */ 5190#define XCM_REG_PBF_LENGTH_MIS 0x20234 5191/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 5192 weight 8 (the most prioritised); 1 stands for weight 1(least 5193 prioritised); 2 stands for weight 2; tc. */ 5194#define XCM_REG_PBF_WEIGHT 0x200d0 5195#define XCM_REG_PHYS_QNUM3_0 0x20100 5196#define XCM_REG_PHYS_QNUM3_1 0x20104 5197/* [RW 8] The Event ID for Timers formatting in case of stop done. */ 5198#define XCM_REG_STOP_EVNT_ID 0x200b8 5199/* [RC 1] Set at message length mismatch (relative to last indication) at 5200 the STORM interface. */ 5201#define XCM_REG_STORM_LENGTH_MIS 0x2021c 5202/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for 5203 weight 8 (the most prioritised); 1 stands for weight 1(least 5204 prioritised); 2 stands for weight 2; tc. */ 5205#define XCM_REG_STORM_WEIGHT 0x200bc 5206/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 5207 disregarded; acknowledge output is deasserted; all other signals are 5208 treated as usual; if 1 - normal activity. */ 5209#define XCM_REG_STORM_XCM_IFEN 0x20010 5210/* [RW 4] Timers output initial credit. Max credit available - 15.Write 5211 writes the initial credit value; read returns the current value of the 5212 credit counter. Must be initialized to 4 at start-up. */ 5213#define XCM_REG_TM_INIT_CRD 0x2041c 5214/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for 5215 weight 8 (the most prioritised); 1 stands for weight 1(least 5216 prioritised); 2 stands for weight 2; tc. */ 5217#define XCM_REG_TM_WEIGHT 0x200ec 5218/* [RW 28] The CM header for Timers expiration command. */ 5219#define XCM_REG_TM_XCM_HDR 0x200a8 5220/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 5221 disregarded; acknowledge output is deasserted; all other signals are 5222 treated as usual; if 1 - normal activity. */ 5223#define XCM_REG_TM_XCM_IFEN 0x2001c 5224/* [RW 1] Input tsem Interface enable. If 0 - the valid input is 5225 disregarded; acknowledge output is deasserted; all other signals are 5226 treated as usual; if 1 - normal activity. */ 5227#define XCM_REG_TSEM_IFEN 0x20024 5228/* [RC 1] Set at message length mismatch (relative to last indication) at 5229 the tsem interface. */ 5230#define XCM_REG_TSEM_LENGTH_MIS 0x20224 5231/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 5232 weight 8 (the most prioritised); 1 stands for weight 1(least 5233 prioritised); 2 stands for weight 2; tc. */ 5234#define XCM_REG_TSEM_WEIGHT 0x200c0 5235/* [RW 2] The queue index for registration on UNA greater NXT decision rule. */ 5236#define XCM_REG_UNA_GT_NXT_Q 0x20120 5237/* [RW 1] Input usem Interface enable. If 0 - the valid input is 5238 disregarded; acknowledge output is deasserted; all other signals are 5239 treated as usual; if 1 - normal activity. */ 5240#define XCM_REG_USEM_IFEN 0x2002c 5241/* [RC 1] Message length mismatch (relative to last indication) at the usem 5242 interface. */ 5243#define XCM_REG_USEM_LENGTH_MIS 0x2022c 5244/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 5245 weight 8 (the most prioritised); 1 stands for weight 1(least 5246 prioritised); 2 stands for weight 2; tc. */ 5247#define XCM_REG_USEM_WEIGHT 0x200c8 5248#define XCM_REG_WU_DA_CNT_CMD00 0x201d4 5249#define XCM_REG_WU_DA_CNT_CMD01 0x201d8 5250#define XCM_REG_WU_DA_CNT_CMD10 0x201dc 5251#define XCM_REG_WU_DA_CNT_CMD11 0x201e0 5252#define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4 5253#define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8 5254#define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec 5255#define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0 5256#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4 5257#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8 5258#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc 5259#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0 5260/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 5261 acknowledge output is deasserted; all other signals are treated as usual; 5262 if 1 - normal activity. */ 5263#define XCM_REG_XCM_CFC_IFEN 0x20050 5264/* [RW 14] Interrupt mask register #0 read/write */ 5265#define XCM_REG_XCM_INT_MASK 0x202b4 5266/* [R 14] Interrupt register #0 read */ 5267#define XCM_REG_XCM_INT_STS 0x202a8 5268/* [RW 30] Parity mask register #0 read/write */ 5269#define XCM_REG_XCM_PRTY_MASK 0x202c4 5270/* [R 30] Parity register #0 read */ 5271#define XCM_REG_XCM_PRTY_STS 0x202b8 5272/* [RC 30] Parity register #0 read clear */ 5273#define XCM_REG_XCM_PRTY_STS_CLR 0x202bc 5274 5275/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS 5276 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 5277 Is used to determine the number of the AG context REG-pairs written back; 5278 when the Reg1WbFlg isn't set. */ 5279#define XCM_REG_XCM_REG0_SZ 0x200f4 5280/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 5281 disregarded; valid is deasserted; all other signals are treated as usual; 5282 if 1 - normal activity. */ 5283#define XCM_REG_XCM_STORM0_IFEN 0x20004 5284/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 5285 disregarded; valid is deasserted; all other signals are treated as usual; 5286 if 1 - normal activity. */ 5287#define XCM_REG_XCM_STORM1_IFEN 0x20008 5288/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is 5289 disregarded; acknowledge output is deasserted; all other signals are 5290 treated as usual; if 1 - normal activity. */ 5291#define XCM_REG_XCM_TM_IFEN 0x20020 5292/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 5293 disregarded; valid is deasserted; all other signals are treated as usual; 5294 if 1 - normal activity. */ 5295#define XCM_REG_XCM_XQM_IFEN 0x2000c 5296/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 5297#define XCM_REG_XCM_XQM_USE_Q 0x200f0 5298/* [RW 4] The value by which CFC updates the activity counter at QM bypass. */ 5299#define XCM_REG_XQM_BYP_ACT_UPD 0x200fc 5300/* [RW 6] QM output initial credit. Max credit available - 32.Write writes 5301 the initial credit value; read returns the current value of the credit 5302 counter. Must be initialized to 32 at start-up. */ 5303#define XCM_REG_XQM_INIT_CRD 0x20420 5304/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 5305 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 5306 prioritised); 2 stands for weight 2; tc. */ 5307#define XCM_REG_XQM_P_WEIGHT 0x200e4 5308/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 5309 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 5310 prioritised); 2 stands for weight 2; tc. */ 5311#define XCM_REG_XQM_S_WEIGHT 0x200e8 5312/* [RW 28] The CM header value for QM request (primary). */ 5313#define XCM_REG_XQM_XCM_HDR_P 0x200a0 5314/* [RW 28] The CM header value for QM request (secondary). */ 5315#define XCM_REG_XQM_XCM_HDR_S 0x200a4 5316/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 5317 acknowledge output is deasserted; all other signals are treated as usual; 5318 if 1 - normal activity. */ 5319#define XCM_REG_XQM_XCM_IFEN 0x20014 5320/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 5321 acknowledge output is deasserted; all other signals are treated as usual; 5322 if 1 - normal activity. */ 5323#define XCM_REG_XSDM_IFEN 0x20018 5324/* [RC 1] Set at message length mismatch (relative to last indication) at 5325 the SDM interface. */ 5326#define XCM_REG_XSDM_LENGTH_MIS 0x20220 5327/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 5328 weight 8 (the most prioritised); 1 stands for weight 1(least 5329 prioritised); 2 stands for weight 2; tc. */ 5330#define XCM_REG_XSDM_WEIGHT 0x200e0 5331/* [RW 17] Indirect access to the descriptor table of the XX protection 5332 mechanism. The fields are: [5:0] - message length; 11:6] - message 5333 pointer; 16:12] - next pointer. */ 5334#define XCM_REG_XX_DESCR_TABLE 0x20480 5335#define XCM_REG_XX_DESCR_TABLE_SIZE 32 5336/* [R 6] Used to read the XX protection Free counter. */ 5337#define XCM_REG_XX_FREE 0x20240 5338/* [RW 6] Initial value for the credit counter; responsible for fulfilling 5339 of the Input Stage XX protection buffer by the XX protection pending 5340 messages. Max credit available - 3.Write writes the initial credit value; 5341 read returns the current value of the credit counter. Must be initialized 5342 to 2 at start-up. */ 5343#define XCM_REG_XX_INIT_CRD 0x20424 5344/* [RW 6] The maximum number of pending messages; which may be stored in XX 5345 protection. ~xcm_registers_xx_free.xx_free read on read. */ 5346#define XCM_REG_XX_MSG_NUM 0x20428 5347/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 5348#define XCM_REG_XX_OVFL_EVNT_ID 0x20058 5349#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0) 5350#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1) 5351#define XMAC_CTRL_REG_LINE_LOCAL_LPBK (0x1<<2) 5352#define XMAC_CTRL_REG_RX_EN (0x1<<1) 5353#define XMAC_CTRL_REG_SOFT_RESET (0x1<<6) 5354#define XMAC_CTRL_REG_TX_EN (0x1<<0) 5355#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18) 5356#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17) 5357#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON (0x1<<1) 5358#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0) 5359#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3) 5360#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4) 5361#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5) 5362#define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60 5363#define XMAC_REG_CTRL 0 5364/* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC 5365 * packets transmitted by the MAC */ 5366#define XMAC_REG_CTRL_SA_HI 0x2c 5367/* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC 5368 * packets transmitted by the MAC */ 5369#define XMAC_REG_CTRL_SA_LO 0x28 5370#define XMAC_REG_PAUSE_CTRL 0x68 5371#define XMAC_REG_PFC_CTRL 0x70 5372#define XMAC_REG_PFC_CTRL_HI 0x74 5373#define XMAC_REG_RX_LSS_STATUS 0x58 5374/* [RW 14] Maximum packet size in receive direction; exclusive of preamble & 5375 * CRC in strip mode */ 5376#define XMAC_REG_RX_MAX_SIZE 0x40 5377#define XMAC_REG_TX_CTRL 0x20 5378/* [RW 16] Indirect access to the XX table of the XX protection mechanism. 5379 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] - 5380 header pointer. */ 5381#define XCM_REG_XX_TABLE 0x20500 5382/* [RW 8] The event id for aggregated interrupt 0 */ 5383#define XSDM_REG_AGG_INT_EVENT_0 0x166038 5384#define XSDM_REG_AGG_INT_EVENT_1 0x16603c 5385#define XSDM_REG_AGG_INT_EVENT_10 0x166060 5386#define XSDM_REG_AGG_INT_EVENT_11 0x166064 5387#define XSDM_REG_AGG_INT_EVENT_12 0x166068 5388#define XSDM_REG_AGG_INT_EVENT_13 0x16606c 5389#define XSDM_REG_AGG_INT_EVENT_14 0x166070 5390#define XSDM_REG_AGG_INT_EVENT_2 0x166040 5391#define XSDM_REG_AGG_INT_EVENT_3 0x166044 5392#define XSDM_REG_AGG_INT_EVENT_4 0x166048 5393#define XSDM_REG_AGG_INT_EVENT_5 0x16604c 5394#define XSDM_REG_AGG_INT_EVENT_6 0x166050 5395#define XSDM_REG_AGG_INT_EVENT_7 0x166054 5396#define XSDM_REG_AGG_INT_EVENT_8 0x166058 5397#define XSDM_REG_AGG_INT_EVENT_9 0x16605c 5398/* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 5399 or auto-mask-mode (1) */ 5400#define XSDM_REG_AGG_INT_MODE_0 0x1661b8 5401#define XSDM_REG_AGG_INT_MODE_1 0x1661bc 5402/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 5403#define XSDM_REG_CFC_RSP_START_ADDR 0x166008 5404/* [RW 16] The maximum value of the completion counter #0 */ 5405#define XSDM_REG_CMP_COUNTER_MAX0 0x16601c 5406/* [RW 16] The maximum value of the completion counter #1 */ 5407#define XSDM_REG_CMP_COUNTER_MAX1 0x166020 5408/* [RW 16] The maximum value of the completion counter #2 */ 5409#define XSDM_REG_CMP_COUNTER_MAX2 0x166024 5410/* [RW 16] The maximum value of the completion counter #3 */ 5411#define XSDM_REG_CMP_COUNTER_MAX3 0x166028 5412/* [RW 13] The start address in the internal RAM for the completion 5413 counters. */ 5414#define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c 5415#define XSDM_REG_ENABLE_IN1 0x166238 5416#define XSDM_REG_ENABLE_IN2 0x16623c 5417#define XSDM_REG_ENABLE_OUT1 0x166240 5418#define XSDM_REG_ENABLE_OUT2 0x166244 5419/* [RW 4] The initial number of messages that can be sent to the pxp control 5420 interface without receiving any ACK. */ 5421#define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc 5422/* [ST 32] The number of ACK after placement messages received */ 5423#define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c 5424/* [ST 32] The number of packet end messages received from the parser */ 5425#define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274 5426/* [ST 32] The number of requests received from the pxp async if */ 5427#define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278 5428/* [ST 32] The number of commands received in queue 0 */ 5429#define XSDM_REG_NUM_OF_Q0_CMD 0x166248 5430/* [ST 32] The number of commands received in queue 10 */ 5431#define XSDM_REG_NUM_OF_Q10_CMD 0x16626c 5432/* [ST 32] The number of commands received in queue 11 */ 5433#define XSDM_REG_NUM_OF_Q11_CMD 0x166270 5434/* [ST 32] The number of commands received in queue 1 */ 5435#define XSDM_REG_NUM_OF_Q1_CMD 0x16624c 5436/* [ST 32] The number of commands received in queue 3 */ 5437#define XSDM_REG_NUM_OF_Q3_CMD 0x166250 5438/* [ST 32] The number of commands received in queue 4 */ 5439#define XSDM_REG_NUM_OF_Q4_CMD 0x166254 5440/* [ST 32] The number of commands received in queue 5 */ 5441#define XSDM_REG_NUM_OF_Q5_CMD 0x166258 5442/* [ST 32] The number of commands received in queue 6 */ 5443#define XSDM_REG_NUM_OF_Q6_CMD 0x16625c 5444/* [ST 32] The number of commands received in queue 7 */ 5445#define XSDM_REG_NUM_OF_Q7_CMD 0x166260 5446/* [ST 32] The number of commands received in queue 8 */ 5447#define XSDM_REG_NUM_OF_Q8_CMD 0x166264 5448/* [ST 32] The number of commands received in queue 9 */ 5449#define XSDM_REG_NUM_OF_Q9_CMD 0x166268 5450/* [RW 13] The start address in the internal RAM for queue counters */ 5451#define XSDM_REG_Q_COUNTER_START_ADDR 0x166010 5452/* [W 17] Generate an operation after completion; bit-16 is 5453 * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and 5454 * bits 4:0 are the T124Param[4:0] */ 5455#define XSDM_REG_OPERATION_GEN 0x1664c4 5456/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 5457#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548 5458/* [R 1] parser fifo empty in sdm_sync block */ 5459#define XSDM_REG_SYNC_PARSER_EMPTY 0x166550 5460/* [R 1] parser serial fifo empty in sdm_sync block */ 5461#define XSDM_REG_SYNC_SYNC_EMPTY 0x166558 5462/* [RW 32] Tick for timer counter. Applicable only when 5463 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */ 5464#define XSDM_REG_TIMER_TICK 0x166000 5465/* [RW 32] Interrupt mask register #0 read/write */ 5466#define XSDM_REG_XSDM_INT_MASK_0 0x16629c 5467#define XSDM_REG_XSDM_INT_MASK_1 0x1662ac 5468/* [R 32] Interrupt register #0 read */ 5469#define XSDM_REG_XSDM_INT_STS_0 0x166290 5470#define XSDM_REG_XSDM_INT_STS_1 0x1662a0 5471/* [RW 11] Parity mask register #0 read/write */ 5472#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc 5473/* [R 11] Parity register #0 read */ 5474#define XSDM_REG_XSDM_PRTY_STS 0x1662b0 5475/* [RC 11] Parity register #0 read clear */ 5476#define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4 5477/* [RW 5] The number of time_slots in the arbitration cycle */ 5478#define XSEM_REG_ARB_CYCLE_SIZE 0x280034 5479/* [RW 3] The source that is associated with arbitration element 0. Source 5480 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5481 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 5482#define XSEM_REG_ARB_ELEMENT0 0x280020 5483/* [RW 3] The source that is associated with arbitration element 1. Source 5484 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5485 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5486 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */ 5487#define XSEM_REG_ARB_ELEMENT1 0x280024 5488/* [RW 3] The source that is associated with arbitration element 2. Source 5489 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5490 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5491 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 5492 and ~xsem_registers_arb_element1.arb_element1 */ 5493#define XSEM_REG_ARB_ELEMENT2 0x280028 5494/* [RW 3] The source that is associated with arbitration element 3. Source 5495 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5496 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 5497 not be equal to register ~xsem_registers_arb_element0.arb_element0 and 5498 ~xsem_registers_arb_element1.arb_element1 and 5499 ~xsem_registers_arb_element2.arb_element2 */ 5500#define XSEM_REG_ARB_ELEMENT3 0x28002c 5501/* [RW 3] The source that is associated with arbitration element 4. Source 5502 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5503 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5504 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 5505 and ~xsem_registers_arb_element1.arb_element1 and 5506 ~xsem_registers_arb_element2.arb_element2 and 5507 ~xsem_registers_arb_element3.arb_element3 */ 5508#define XSEM_REG_ARB_ELEMENT4 0x280030 5509#define XSEM_REG_ENABLE_IN 0x2800a4 5510#define XSEM_REG_ENABLE_OUT 0x2800a8 5511/* [RW 32] This address space contains all registers and memories that are 5512 placed in SEM_FAST block. The SEM_FAST registers are described in 5513 appendix B. In order to access the sem_fast registers the base address 5514 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 5515#define XSEM_REG_FAST_MEMORY 0x2a0000 5516/* [RW 1] Disables input messages from FIC0 May be updated during run_time 5517 by the microcode */ 5518#define XSEM_REG_FIC0_DISABLE 0x280224 5519/* [RW 1] Disables input messages from FIC1 May be updated during run_time 5520 by the microcode */ 5521#define XSEM_REG_FIC1_DISABLE 0x280234 5522/* [RW 15] Interrupt table Read and write access to it is not possible in 5523 the middle of the work */ 5524#define XSEM_REG_INT_TABLE 0x280400 5525/* [ST 24] Statistics register. The number of messages that entered through 5526 FIC0 */ 5527#define XSEM_REG_MSG_NUM_FIC0 0x280000 5528/* [ST 24] Statistics register. The number of messages that entered through 5529 FIC1 */ 5530#define XSEM_REG_MSG_NUM_FIC1 0x280004 5531/* [ST 24] Statistics register. The number of messages that were sent to 5532 FOC0 */ 5533#define XSEM_REG_MSG_NUM_FOC0 0x280008 5534/* [ST 24] Statistics register. The number of messages that were sent to 5535 FOC1 */ 5536#define XSEM_REG_MSG_NUM_FOC1 0x28000c 5537/* [ST 24] Statistics register. The number of messages that were sent to 5538 FOC2 */ 5539#define XSEM_REG_MSG_NUM_FOC2 0x280010 5540/* [ST 24] Statistics register. The number of messages that were sent to 5541 FOC3 */ 5542#define XSEM_REG_MSG_NUM_FOC3 0x280014 5543/* [RW 1] Disables input messages from the passive buffer May be updated 5544 during run_time by the microcode */ 5545#define XSEM_REG_PAS_DISABLE 0x28024c 5546/* [WB 128] Debug only. Passive buffer memory */ 5547#define XSEM_REG_PASSIVE_BUFFER 0x282000 5548/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 5549#define XSEM_REG_PRAM 0x2c0000 5550/* [R 16] Valid sleeping threads indication have bit per thread */ 5551#define XSEM_REG_SLEEP_THREADS_VALID 0x28026c 5552/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 5553#define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0 5554/* [RW 16] List of free threads . There is a bit per thread. */ 5555#define XSEM_REG_THREADS_LIST 0x2802e4 5556/* [RW 3] The arbitration scheme of time_slot 0 */ 5557#define XSEM_REG_TS_0_AS 0x280038 5558/* [RW 3] The arbitration scheme of time_slot 10 */ 5559#define XSEM_REG_TS_10_AS 0x280060 5560/* [RW 3] The arbitration scheme of time_slot 11 */ 5561#define XSEM_REG_TS_11_AS 0x280064 5562/* [RW 3] The arbitration scheme of time_slot 12 */ 5563#define XSEM_REG_TS_12_AS 0x280068 5564/* [RW 3] The arbitration scheme of time_slot 13 */ 5565#define XSEM_REG_TS_13_AS 0x28006c 5566/* [RW 3] The arbitration scheme of time_slot 14 */ 5567#define XSEM_REG_TS_14_AS 0x280070 5568/* [RW 3] The arbitration scheme of time_slot 15 */ 5569#define XSEM_REG_TS_15_AS 0x280074 5570/* [RW 3] The arbitration scheme of time_slot 16 */ 5571#define XSEM_REG_TS_16_AS 0x280078 5572/* [RW 3] The arbitration scheme of time_slot 17 */ 5573#define XSEM_REG_TS_17_AS 0x28007c 5574/* [RW 3] The arbitration scheme of time_slot 18 */ 5575#define XSEM_REG_TS_18_AS 0x280080 5576/* [RW 3] The arbitration scheme of time_slot 1 */ 5577#define XSEM_REG_TS_1_AS 0x28003c 5578/* [RW 3] The arbitration scheme of time_slot 2 */ 5579#define XSEM_REG_TS_2_AS 0x280040 5580/* [RW 3] The arbitration scheme of time_slot 3 */ 5581#define XSEM_REG_TS_3_AS 0x280044 5582/* [RW 3] The arbitration scheme of time_slot 4 */ 5583#define XSEM_REG_TS_4_AS 0x280048 5584/* [RW 3] The arbitration scheme of time_slot 5 */ 5585#define XSEM_REG_TS_5_AS 0x28004c 5586/* [RW 3] The arbitration scheme of time_slot 6 */ 5587#define XSEM_REG_TS_6_AS 0x280050 5588/* [RW 3] The arbitration scheme of time_slot 7 */ 5589#define XSEM_REG_TS_7_AS 0x280054 5590/* [RW 3] The arbitration scheme of time_slot 8 */ 5591#define XSEM_REG_TS_8_AS 0x280058 5592/* [RW 3] The arbitration scheme of time_slot 9 */ 5593#define XSEM_REG_TS_9_AS 0x28005c 5594/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 5595 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 5596#define XSEM_REG_VFPF_ERR_NUM 0x280380 5597/* [RW 32] Interrupt mask register #0 read/write */ 5598#define XSEM_REG_XSEM_INT_MASK_0 0x280110 5599#define XSEM_REG_XSEM_INT_MASK_1 0x280120 5600/* [R 32] Interrupt register #0 read */ 5601#define XSEM_REG_XSEM_INT_STS_0 0x280104 5602#define XSEM_REG_XSEM_INT_STS_1 0x280114 5603/* [RW 32] Parity mask register #0 read/write */ 5604#define XSEM_REG_XSEM_PRTY_MASK_0 0x280130 5605#define XSEM_REG_XSEM_PRTY_MASK_1 0x280140 5606/* [R 32] Parity register #0 read */ 5607#define XSEM_REG_XSEM_PRTY_STS_0 0x280124 5608#define XSEM_REG_XSEM_PRTY_STS_1 0x280134 5609/* [RC 32] Parity register #0 read clear */ 5610#define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128 5611#define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138 5612#define MCPR_ACCESS_LOCK_LOCK (1L<<31) 5613#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0) 5614#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 5615#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 5616#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0) 5617#define MCPR_NVM_COMMAND_DOIT (1L<<4) 5618#define MCPR_NVM_COMMAND_DONE (1L<<3) 5619#define MCPR_NVM_COMMAND_FIRST (1L<<7) 5620#define MCPR_NVM_COMMAND_LAST (1L<<8) 5621#define MCPR_NVM_COMMAND_WR (1L<<5) 5622#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9) 5623#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 5624#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 5625#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3) 5626#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) 5627#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3) 5628#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3) 5629#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3) 5630#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3) 5631#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3) 5632#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3) 5633#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3) 5634#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3) 5635#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3) 5636#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3) 5637#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3) 5638#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3) 5639#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3) 5640#define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3) 5641#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) 5642#define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3) 5643#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3) 5644#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3) 5645#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3) 5646#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3) 5647#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3) 5648#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3) 5649#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3) 5650#define BIGMAC2_REGISTER_RX_STAT_GRPP (0x51<<3) 5651#define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3) 5652#define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3) 5653#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3) 5654#define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3) 5655#define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3) 5656#define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3) 5657#define BIGMAC2_REGISTER_TX_STAT_GTPP (0x24<<3) 5658#define EMAC_LED_1000MB_OVERRIDE (1L<<1) 5659#define EMAC_LED_100MB_OVERRIDE (1L<<2) 5660#define EMAC_LED_10MB_OVERRIDE (1L<<3) 5661#define EMAC_LED_2500MB_OVERRIDE (1L<<12) 5662#define EMAC_LED_OVERRIDE (1L<<0) 5663#define EMAC_LED_TRAFFIC (1L<<6) 5664#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26) 5665#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26) 5666#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26) 5667#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26) 5668#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26) 5669#define EMAC_MDIO_COMM_DATA (0xffffL<<0) 5670#define EMAC_MDIO_COMM_START_BUSY (1L<<29) 5671#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 5672#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31) 5673#define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16) 5674#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16 5675#define EMAC_MDIO_STATUS_10MB (1L<<1) 5676#define EMAC_MODE_25G_MODE (1L<<5) 5677#define EMAC_MODE_HALF_DUPLEX (1L<<1) 5678#define EMAC_MODE_PORT_GMII (2L<<2) 5679#define EMAC_MODE_PORT_MII (1L<<2) 5680#define EMAC_MODE_PORT_MII_10M (3L<<2) 5681#define EMAC_MODE_RESET (1L<<0) 5682#define EMAC_REG_EMAC_LED 0xc 5683#define EMAC_REG_EMAC_MAC_MATCH 0x10 5684#define EMAC_REG_EMAC_MDIO_COMM 0xac 5685#define EMAC_REG_EMAC_MDIO_MODE 0xb4 5686#define EMAC_REG_EMAC_MDIO_STATUS 0xb0 5687#define EMAC_REG_EMAC_MODE 0x0 5688#define EMAC_REG_EMAC_RX_MODE 0xc8 5689#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c 5690#define EMAC_REG_EMAC_RX_STAT_AC 0x180 5691#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4 5692#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23 5693#define EMAC_REG_EMAC_TX_MODE 0xbc 5694#define EMAC_REG_EMAC_TX_STAT_AC 0x280 5695#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22 5696#define EMAC_REG_RX_PFC_MODE 0x320 5697#define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2) 5698#define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1) 5699#define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0) 5700#define EMAC_REG_RX_PFC_PARAM 0x324 5701#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0 5702#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16 5703#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328 5704#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0) 5705#define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330 5706#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0) 5707#define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c 5708#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0) 5709#define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334 5710#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0) 5711#define EMAC_RX_MODE_FLOW_EN (1L<<2) 5712#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) 5713#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 5714#define EMAC_RX_MODE_PROMISCUOUS (1L<<8) 5715#define EMAC_RX_MODE_RESET (1L<<0) 5716#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 5717#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 5718#define EMAC_TX_MODE_FLOW_EN (1L<<4) 5719#define EMAC_TX_MODE_RESET (1L<<0) 5720#define MISC_REGISTERS_GPIO_0 0 5721#define MISC_REGISTERS_GPIO_1 1 5722#define MISC_REGISTERS_GPIO_2 2 5723#define MISC_REGISTERS_GPIO_3 3 5724#define MISC_REGISTERS_GPIO_CLR_POS 16 5725#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24) 5726#define MISC_REGISTERS_GPIO_FLOAT_POS 24 5727#define MISC_REGISTERS_GPIO_HIGH 1 5728#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2 5729#define MISC_REGISTERS_GPIO_INT_CLR_POS 24 5730#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0 5731#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1 5732#define MISC_REGISTERS_GPIO_INT_SET_POS 16 5733#define MISC_REGISTERS_GPIO_LOW 0 5734#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1 5735#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0 5736#define MISC_REGISTERS_GPIO_PORT_SHIFT 4 5737#define MISC_REGISTERS_GPIO_SET_POS 8 5738#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 5739#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0) 5740#define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1<<19) 5741#define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29) 5742#define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7) 5743#define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26) 5744#define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27) 5745#define MISC_REGISTERS_RESET_REG_1_SET 0x584 5746#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 5747#define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24) 5748#define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25) 5749#define MISC_REGISTERS_RESET_REG_2_PGLC (0x1<<19) 5750#define MISC_REGISTERS_RESET_REG_2_RST_ATC (0x1<<17) 5751#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0) 5752#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1) 5753#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2) 5754#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14) 5755#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3) 5756#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15) 5757#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4) 5758#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6) 5759#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8) 5760#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7) 5761#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5) 5762#define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13) 5763#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11) 5764#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13) 5765#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9) 5766#define MISC_REGISTERS_RESET_REG_2_SET 0x594 5767#define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20) 5768#define MISC_REGISTERS_RESET_REG_2_UMAC1 (0x1<<21) 5769#define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22) 5770#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23) 5771#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8 5772#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1) 5773#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2) 5774#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3) 5775#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0) 5776#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5) 5777#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6) 5778#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7) 5779#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4) 5780#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8) 5781#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4 5782#define MISC_REGISTERS_SPIO_4 4 5783#define MISC_REGISTERS_SPIO_5 5 5784#define MISC_REGISTERS_SPIO_7 7 5785#define MISC_REGISTERS_SPIO_CLR_POS 16 5786#define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24) 5787#define MISC_REGISTERS_SPIO_FLOAT_POS 24 5788#define MISC_REGISTERS_SPIO_INPUT_HI_Z 2 5789#define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16 5790#define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1 5791#define MISC_REGISTERS_SPIO_OUTPUT_LOW 0 5792#define MISC_REGISTERS_SPIO_SET_POS 8 5793#define HW_LOCK_MAX_RESOURCE_VALUE 31 5794#define HW_LOCK_RESOURCE_DRV_FLAGS 10 5795#define HW_LOCK_RESOURCE_GPIO 1 5796#define HW_LOCK_RESOURCE_MDIO 0 5797#define HW_LOCK_RESOURCE_NVRAM 12 5798#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 5799#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8 5800#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9 5801#define HW_LOCK_RESOURCE_RECOVERY_REG 11 5802#define HW_LOCK_RESOURCE_RESET 5 5803#define HW_LOCK_RESOURCE_SPIO 2 5804#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4) 5805#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5) 5806#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18) 5807#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31) 5808#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30) 5809#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9) 5810#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8) 5811#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7) 5812#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6) 5813#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29) 5814#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28) 5815#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1) 5816#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0) 5817#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18) 5818#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11) 5819#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10) 5820#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13) 5821#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12) 5822#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2) 5823#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12) 5824#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28) 5825#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1<<31) 5826#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29) 5827#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30) 5828#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15) 5829#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14) 5830#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14) 5831#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20) 5832#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1<<31) 5833#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30) 5834#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0) 5835#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2) 5836#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3) 5837#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5) 5838#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4) 5839#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3) 5840#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2) 5841#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3) 5842#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2) 5843#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22) 5844#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15) 5845#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27) 5846#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26) 5847#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5) 5848#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4) 5849#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25) 5850#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24) 5851#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29) 5852#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28) 5853#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23) 5854#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22) 5855#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27) 5856#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26) 5857#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21) 5858#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20) 5859#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25) 5860#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24) 5861#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16) 5862#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9) 5863#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8) 5864#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7) 5865#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6) 5866#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11) 5867#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10) 5868 5869#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5) 5870#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<9) 5871 5872#define RESERVED_GENERAL_ATTENTION_BIT_0 0 5873 5874#define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0 5875#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000 5876 5877#define RESERVED_GENERAL_ATTENTION_BIT_6 6 5878#define RESERVED_GENERAL_ATTENTION_BIT_7 7 5879#define RESERVED_GENERAL_ATTENTION_BIT_8 8 5880#define RESERVED_GENERAL_ATTENTION_BIT_9 9 5881#define RESERVED_GENERAL_ATTENTION_BIT_10 10 5882#define RESERVED_GENERAL_ATTENTION_BIT_11 11 5883#define RESERVED_GENERAL_ATTENTION_BIT_12 12 5884#define RESERVED_GENERAL_ATTENTION_BIT_13 13 5885#define RESERVED_GENERAL_ATTENTION_BIT_14 14 5886#define RESERVED_GENERAL_ATTENTION_BIT_15 15 5887#define RESERVED_GENERAL_ATTENTION_BIT_16 16 5888#define RESERVED_GENERAL_ATTENTION_BIT_17 17 5889#define RESERVED_GENERAL_ATTENTION_BIT_18 18 5890#define RESERVED_GENERAL_ATTENTION_BIT_19 19 5891#define RESERVED_GENERAL_ATTENTION_BIT_20 20 5892#define RESERVED_GENERAL_ATTENTION_BIT_21 21 5893 5894/* storm asserts attention bits */ 5895#define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7 5896#define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8 5897#define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9 5898#define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10 5899 5900/* mcp error attention bit */ 5901#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11 5902 5903/*E1H NIG status sync attention mapped to group 4-7*/ 5904#define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12 5905#define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13 5906#define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14 5907#define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15 5908#define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16 5909#define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17 5910#define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18 5911#define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19 5912 5913 5914#define LATCHED_ATTN_RBCR 23 5915#define LATCHED_ATTN_RBCT 24 5916#define LATCHED_ATTN_RBCN 25 5917#define LATCHED_ATTN_RBCU 26 5918#define LATCHED_ATTN_RBCP 27 5919#define LATCHED_ATTN_TIMEOUT_GRC 28 5920#define LATCHED_ATTN_RSVD_GRC 29 5921#define LATCHED_ATTN_ROM_PARITY_MCP 30 5922#define LATCHED_ATTN_UM_RX_PARITY_MCP 31 5923#define LATCHED_ATTN_UM_TX_PARITY_MCP 32 5924#define LATCHED_ATTN_SCPAD_PARITY_MCP 33 5925 5926#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32) 5927#define GENERAL_ATTEN_OFFSET(atten_name)\ 5928 (1UL << ((94 + atten_name) % 32)) 5929/* 5930 * This file defines GRC base address for every block. 5931 * This file is included by chipsim, asm microcode and cpp microcode. 5932 * These values are used in Design.xml on regBase attribute 5933 * Use the base with the generated offsets of specific registers. 5934 */ 5935 5936#define GRCBASE_PXPCS 0x000000 5937#define GRCBASE_PCICONFIG 0x002000 5938#define GRCBASE_PCIREG 0x002400 5939#define GRCBASE_EMAC0 0x008000 5940#define GRCBASE_EMAC1 0x008400 5941#define GRCBASE_DBU 0x008800 5942#define GRCBASE_MISC 0x00A000 5943#define GRCBASE_DBG 0x00C000 5944#define GRCBASE_NIG 0x010000 5945#define GRCBASE_XCM 0x020000 5946#define GRCBASE_PRS 0x040000 5947#define GRCBASE_SRCH 0x040400 5948#define GRCBASE_TSDM 0x042000 5949#define GRCBASE_TCM 0x050000 5950#define GRCBASE_BRB1 0x060000 5951#define GRCBASE_MCP 0x080000 5952#define GRCBASE_UPB 0x0C1000 5953#define GRCBASE_CSDM 0x0C2000 5954#define GRCBASE_USDM 0x0C4000 5955#define GRCBASE_CCM 0x0D0000 5956#define GRCBASE_UCM 0x0E0000 5957#define GRCBASE_CDU 0x101000 5958#define GRCBASE_DMAE 0x102000 5959#define GRCBASE_PXP 0x103000 5960#define GRCBASE_CFC 0x104000 5961#define GRCBASE_HC 0x108000 5962#define GRCBASE_PXP2 0x120000 5963#define GRCBASE_PBF 0x140000 5964#define GRCBASE_UMAC0 0x160000 5965#define GRCBASE_UMAC1 0x160400 5966#define GRCBASE_XPB 0x161000 5967#define GRCBASE_MSTAT0 0x162000 5968#define GRCBASE_MSTAT1 0x162800 5969#define GRCBASE_XMAC0 0x163000 5970#define GRCBASE_XMAC1 0x163800 5971#define GRCBASE_TIMERS 0x164000 5972#define GRCBASE_XSDM 0x166000 5973#define GRCBASE_QM 0x168000 5974#define GRCBASE_DQ 0x170000 5975#define GRCBASE_TSEM 0x180000 5976#define GRCBASE_CSEM 0x200000 5977#define GRCBASE_XSEM 0x280000 5978#define GRCBASE_USEM 0x300000 5979#define GRCBASE_MISC_AEU GRCBASE_MISC 5980 5981 5982/* offset of configuration space in the pci core register */ 5983#define PCICFG_OFFSET 0x2000 5984#define PCICFG_VENDOR_ID_OFFSET 0x00 5985#define PCICFG_DEVICE_ID_OFFSET 0x02 5986#define PCICFG_COMMAND_OFFSET 0x04 5987#define PCICFG_COMMAND_IO_SPACE (1<<0) 5988#define PCICFG_COMMAND_MEM_SPACE (1<<1) 5989#define PCICFG_COMMAND_BUS_MASTER (1<<2) 5990#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) 5991#define PCICFG_COMMAND_MWI_CYCLES (1<<4) 5992#define PCICFG_COMMAND_VGA_SNOOP (1<<5) 5993#define PCICFG_COMMAND_PERR_ENA (1<<6) 5994#define PCICFG_COMMAND_STEPPING (1<<7) 5995#define PCICFG_COMMAND_SERR_ENA (1<<8) 5996#define PCICFG_COMMAND_FAST_B2B (1<<9) 5997#define PCICFG_COMMAND_INT_DISABLE (1<<10) 5998#define PCICFG_COMMAND_RESERVED (0x1f<<11) 5999#define PCICFG_STATUS_OFFSET 0x06 6000#define PCICFG_REVESION_ID_OFFSET 0x08 6001#define PCICFG_CACHE_LINE_SIZE 0x0c 6002#define PCICFG_LATENCY_TIMER 0x0d 6003#define PCICFG_BAR_1_LOW 0x10 6004#define PCICFG_BAR_1_HIGH 0x14 6005#define PCICFG_BAR_2_LOW 0x18 6006#define PCICFG_BAR_2_HIGH 0x1c 6007#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 6008#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 6009#define PCICFG_INT_LINE 0x3c 6010#define PCICFG_INT_PIN 0x3d 6011#define PCICFG_PM_CAPABILITY 0x48 6012#define PCICFG_PM_CAPABILITY_VERSION (0x3<<16) 6013#define PCICFG_PM_CAPABILITY_CLOCK (1<<19) 6014#define PCICFG_PM_CAPABILITY_RESERVED (1<<20) 6015#define PCICFG_PM_CAPABILITY_DSI (1<<21) 6016#define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22) 6017#define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25) 6018#define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26) 6019#define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27) 6020#define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28) 6021#define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29) 6022#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30) 6023#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31) 6024#define PCICFG_PM_CSR_OFFSET 0x4c 6025#define PCICFG_PM_CSR_STATE (0x3<<0) 6026#define PCICFG_PM_CSR_PME_ENABLE (1<<8) 6027#define PCICFG_PM_CSR_PME_STATUS (1<<15) 6028#define PCICFG_MSI_CAP_ID_OFFSET 0x58 6029#define PCICFG_MSI_CONTROL_ENABLE (0x1<<16) 6030#define PCICFG_MSI_CONTROL_MCAP (0x7<<17) 6031#define PCICFG_MSI_CONTROL_MENA (0x7<<20) 6032#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23) 6033#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24) 6034#define PCICFG_GRC_ADDRESS 0x78 6035#define PCICFG_GRC_DATA 0x80 6036#define PCICFG_ME_REGISTER 0x98 6037#define PCICFG_MSIX_CAP_ID_OFFSET 0xa0 6038#define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16) 6039#define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27) 6040#define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30) 6041#define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31) 6042 6043#define PCICFG_DEVICE_CONTROL 0xb4 6044#define PCICFG_DEVICE_STATUS 0xb6 6045#define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) 6046#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) 6047#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) 6048#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) 6049#define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) 6050#define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) 6051#define PCICFG_LINK_CONTROL 0xbc 6052 6053 6054#define BAR_USTRORM_INTMEM 0x400000 6055#define BAR_CSTRORM_INTMEM 0x410000 6056#define BAR_XSTRORM_INTMEM 0x420000 6057#define BAR_TSTRORM_INTMEM 0x430000 6058 6059/* for accessing the IGU in case of status block ACK */ 6060#define BAR_IGU_INTMEM 0x440000 6061 6062#define BAR_DOORBELL_OFFSET 0x800000 6063 6064#define BAR_ME_REGISTER 0x450000 6065 6066/* config_2 offset */ 6067#define GRC_CONFIG_2_SIZE_REG 0x408 6068#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 6069#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 6070#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 6071#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 6072#define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 6073#define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 6074#define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 6075#define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 6076#define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 6077#define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 6078#define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 6079#define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 6080#define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 6081#define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 6082#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 6083#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 6084#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 6085#define PCI_CONFIG_2_BAR1_64ENA (1L<<4) 6086#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 6087#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 6088#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 6089#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 6090#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 6091#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) 6092#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) 6093#define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8) 6094#define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8) 6095#define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8) 6096#define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8) 6097#define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8) 6098#define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8) 6099#define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8) 6100#define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8) 6101#define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8) 6102#define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8) 6103#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) 6104#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) 6105#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) 6106#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) 6107#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) 6108 6109/* config_3 offset */ 6110#define GRC_CONFIG_3_SIZE_REG 0x40c 6111#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 6112#define PCI_CONFIG_3_FORCE_PME (1L<<24) 6113#define PCI_CONFIG_3_PME_STATUS (1L<<25) 6114#define PCI_CONFIG_3_PME_ENABLE (1L<<26) 6115#define PCI_CONFIG_3_PM_STATE (0x3L<<27) 6116#define PCI_CONFIG_3_VAUX_PRESET (1L<<30) 6117#define PCI_CONFIG_3_PCI_POWER (1L<<31) 6118 6119#define GRC_BAR2_CONFIG 0x4e0 6120#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) 6121#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) 6122#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) 6123#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) 6124#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) 6125#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) 6126#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) 6127#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) 6128#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) 6129#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) 6130#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) 6131#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) 6132#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) 6133#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) 6134#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) 6135#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) 6136#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) 6137#define PCI_CONFIG_2_BAR2_64ENA (1L<<4) 6138 6139#define PCI_PM_DATA_A 0x410 6140#define PCI_PM_DATA_B 0x414 6141#define PCI_ID_VAL1 0x434 6142#define PCI_ID_VAL2 0x438 6143 6144#define PXPCS_TL_CONTROL_5 0x814 6145#define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/ 6146#define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/ 6147#define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/ 6148#define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/ 6149#define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/ 6150#define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/ 6151#define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/ 6152#define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/ 6153#define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/ 6154#define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/ 6155#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/ 6156#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/ 6157#define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/ 6158#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/ 6159#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/ 6160#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/ 6161#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/ 6162#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/ 6163#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/ 6164#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/ 6165#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/ 6166#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/ 6167#define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/ 6168#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/ 6169#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/ 6170#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/ 6171#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/ 6172#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/ 6173#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/ 6174#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/ 6175 6176 6177#define PXPCS_TL_FUNC345_STAT 0x854 6178#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */ 6179#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4\ 6180 (1 << 28) /* Unsupported Request Error Status in function4, if \ 6181 set, generate pcie_err_attn output when this error is seen. WC */ 6182#define PXPCS_TL_FUNC345_STAT_ERR_ECRC4\ 6183 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \ 6184 generate pcie_err_attn output when this error is seen.. WC */ 6185#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4\ 6186 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \ 6187 generate pcie_err_attn output when this error is seen.. WC */ 6188#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4\ 6189 (1 << 25) /* Receiver Overflow Status Status in function 4, if \ 6190 set, generate pcie_err_attn output when this error is seen.. WC \ 6191 */ 6192#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4\ 6193 (1 << 24) /* Unexpected Completion Status Status in function 4, \ 6194 if set, generate pcie_err_attn output when this error is seen. WC \ 6195 */ 6196#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4\ 6197 (1 << 23) /* Receive UR Statusin function 4. If set, generate \ 6198 pcie_err_attn output when this error is seen. WC */ 6199#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4\ 6200 (1 << 22) /* Completer Timeout Status Status in function 4, if \ 6201 set, generate pcie_err_attn output when this error is seen. WC */ 6202#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4\ 6203 (1 << 21) /* Flow Control Protocol Error Status Status in \ 6204 function 4, if set, generate pcie_err_attn output when this error \ 6205 is seen. WC */ 6206#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4\ 6207 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \ 6208 generate pcie_err_attn output when this error is seen.. WC */ 6209#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */ 6210#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3\ 6211 (1 << 18) /* Unsupported Request Error Status in function3, if \ 6212 set, generate pcie_err_attn output when this error is seen. WC */ 6213#define PXPCS_TL_FUNC345_STAT_ERR_ECRC3\ 6214 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \ 6215 generate pcie_err_attn output when this error is seen.. WC */ 6216#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3\ 6217 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \ 6218 generate pcie_err_attn output when this error is seen.. WC */ 6219#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3\ 6220 (1 << 15) /* Receiver Overflow Status Status in function 3, if \ 6221 set, generate pcie_err_attn output when this error is seen.. WC \ 6222 */ 6223#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3\ 6224 (1 << 14) /* Unexpected Completion Status Status in function 3, \ 6225 if set, generate pcie_err_attn output when this error is seen. WC \ 6226 */ 6227#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3\ 6228 (1 << 13) /* Receive UR Statusin function 3. If set, generate \ 6229 pcie_err_attn output when this error is seen. WC */ 6230#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3\ 6231 (1 << 12) /* Completer Timeout Status Status in function 3, if \ 6232 set, generate pcie_err_attn output when this error is seen. WC */ 6233#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3\ 6234 (1 << 11) /* Flow Control Protocol Error Status Status in \ 6235 function 3, if set, generate pcie_err_attn output when this error \ 6236 is seen. WC */ 6237#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3\ 6238 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \ 6239 generate pcie_err_attn output when this error is seen.. WC */ 6240#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */ 6241#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2\ 6242 (1 << 8) /* Unsupported Request Error Status for Function 2, if \ 6243 set, generate pcie_err_attn output when this error is seen. WC */ 6244#define PXPCS_TL_FUNC345_STAT_ERR_ECRC2\ 6245 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \ 6246 generate pcie_err_attn output when this error is seen.. WC */ 6247#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2\ 6248 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \ 6249 generate pcie_err_attn output when this error is seen.. WC */ 6250#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2\ 6251 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \ 6252 set, generate pcie_err_attn output when this error is seen.. WC \ 6253 */ 6254#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2\ 6255 (1 << 4) /* Unexpected Completion Status Status for Function 2, \ 6256 if set, generate pcie_err_attn output when this error is seen. WC \ 6257 */ 6258#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2\ 6259 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \ 6260 pcie_err_attn output when this error is seen. WC */ 6261#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2\ 6262 (1 << 2) /* Completer Timeout Status Status for Function 2, if \ 6263 set, generate pcie_err_attn output when this error is seen. WC */ 6264#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2\ 6265 (1 << 1) /* Flow Control Protocol Error Status Status for \ 6266 Function 2, if set, generate pcie_err_attn output when this error \ 6267 is seen. WC */ 6268#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2\ 6269 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \ 6270 generate pcie_err_attn output when this error is seen.. WC */ 6271 6272 6273#define PXPCS_TL_FUNC678_STAT 0x85C 6274#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */ 6275#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7\ 6276 (1 << 28) /* Unsupported Request Error Status in function7, if \ 6277 set, generate pcie_err_attn output when this error is seen. WC */ 6278#define PXPCS_TL_FUNC678_STAT_ERR_ECRC7\ 6279 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \ 6280 generate pcie_err_attn output when this error is seen.. WC */ 6281#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7\ 6282 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \ 6283 generate pcie_err_attn output when this error is seen.. WC */ 6284#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7\ 6285 (1 << 25) /* Receiver Overflow Status Status in function 7, if \ 6286 set, generate pcie_err_attn output when this error is seen.. WC \ 6287 */ 6288#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7\ 6289 (1 << 24) /* Unexpected Completion Status Status in function 7, \ 6290 if set, generate pcie_err_attn output when this error is seen. WC \ 6291 */ 6292#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7\ 6293 (1 << 23) /* Receive UR Statusin function 7. If set, generate \ 6294 pcie_err_attn output when this error is seen. WC */ 6295#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7\ 6296 (1 << 22) /* Completer Timeout Status Status in function 7, if \ 6297 set, generate pcie_err_attn output when this error is seen. WC */ 6298#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7\ 6299 (1 << 21) /* Flow Control Protocol Error Status Status in \ 6300 function 7, if set, generate pcie_err_attn output when this error \ 6301 is seen. WC */ 6302#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7\ 6303 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \ 6304 generate pcie_err_attn output when this error is seen.. WC */ 6305#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */ 6306#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6\ 6307 (1 << 18) /* Unsupported Request Error Status in function6, if \ 6308 set, generate pcie_err_attn output when this error is seen. WC */ 6309#define PXPCS_TL_FUNC678_STAT_ERR_ECRC6\ 6310 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \ 6311 generate pcie_err_attn output when this error is seen.. WC */ 6312#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6\ 6313 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \ 6314 generate pcie_err_attn output when this error is seen.. WC */ 6315#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6\ 6316 (1 << 15) /* Receiver Overflow Status Status in function 6, if \ 6317 set, generate pcie_err_attn output when this error is seen.. WC \ 6318 */ 6319#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6\ 6320 (1 << 14) /* Unexpected Completion Status Status in function 6, \ 6321 if set, generate pcie_err_attn output when this error is seen. WC \ 6322 */ 6323#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6\ 6324 (1 << 13) /* Receive UR Statusin function 6. If set, generate \ 6325 pcie_err_attn output when this error is seen. WC */ 6326#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6\ 6327 (1 << 12) /* Completer Timeout Status Status in function 6, if \ 6328 set, generate pcie_err_attn output when this error is seen. WC */ 6329#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6\ 6330 (1 << 11) /* Flow Control Protocol Error Status Status in \ 6331 function 6, if set, generate pcie_err_attn output when this error \ 6332 is seen. WC */ 6333#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6\ 6334 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \ 6335 generate pcie_err_attn output when this error is seen.. WC */ 6336#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */ 6337#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5\ 6338 (1 << 8) /* Unsupported Request Error Status for Function 5, if \ 6339 set, generate pcie_err_attn output when this error is seen. WC */ 6340#define PXPCS_TL_FUNC678_STAT_ERR_ECRC5\ 6341 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \ 6342 generate pcie_err_attn output when this error is seen.. WC */ 6343#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5\ 6344 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \ 6345 generate pcie_err_attn output when this error is seen.. WC */ 6346#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5\ 6347 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \ 6348 set, generate pcie_err_attn output when this error is seen.. WC \ 6349 */ 6350#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5\ 6351 (1 << 4) /* Unexpected Completion Status Status for Function 5, \ 6352 if set, generate pcie_err_attn output when this error is seen. WC \ 6353 */ 6354#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5\ 6355 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \ 6356 pcie_err_attn output when this error is seen. WC */ 6357#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5\ 6358 (1 << 2) /* Completer Timeout Status Status for Function 5, if \ 6359 set, generate pcie_err_attn output when this error is seen. WC */ 6360#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5\ 6361 (1 << 1) /* Flow Control Protocol Error Status Status for \ 6362 Function 5, if set, generate pcie_err_attn output when this error \ 6363 is seen. WC */ 6364#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5\ 6365 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \ 6366 generate pcie_err_attn output when this error is seen.. WC */ 6367 6368 6369#define BAR_USTRORM_INTMEM 0x400000 6370#define BAR_CSTRORM_INTMEM 0x410000 6371#define BAR_XSTRORM_INTMEM 0x420000 6372#define BAR_TSTRORM_INTMEM 0x430000 6373 6374/* for accessing the IGU in case of status block ACK */ 6375#define BAR_IGU_INTMEM 0x440000 6376 6377#define BAR_DOORBELL_OFFSET 0x800000 6378 6379#define BAR_ME_REGISTER 0x450000 6380#define ME_REG_PF_NUM_SHIFT 0 6381#define ME_REG_PF_NUM\ 6382 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */ 6383#define ME_REG_VF_VALID (1<<8) 6384#define ME_REG_VF_NUM_SHIFT 9 6385#define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT) 6386#define ME_REG_VF_ERR (0x1<<3) 6387#define ME_REG_ABS_PF_NUM_SHIFT 16 6388#define ME_REG_ABS_PF_NUM\ 6389 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */ 6390 6391 6392#define MDIO_REG_BANK_CL73_IEEEB0 0x0 6393#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 6394#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200 6395#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000 6396#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000 6397 6398#define MDIO_REG_BANK_CL73_IEEEB1 0x10 6399#define MDIO_CL73_IEEEB1_AN_ADV1 0x00 6400#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400 6401#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800 6402#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00 6403#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00 6404#define MDIO_CL73_IEEEB1_AN_ADV2 0x01 6405#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000 6406#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020 6407#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040 6408#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080 6409#define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03 6410#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400 6411#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800 6412#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00 6413#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00 6414#define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04 6415 6416#define MDIO_REG_BANK_RX0 0x80b0 6417#define MDIO_RX0_RX_STATUS 0x10 6418#define MDIO_RX0_RX_STATUS_SIGDET 0x8000 6419#define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000 6420#define MDIO_RX0_RX_EQ_BOOST 0x1c 6421#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6422#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10 6423 6424#define MDIO_REG_BANK_RX1 0x80c0 6425#define MDIO_RX1_RX_EQ_BOOST 0x1c 6426#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6427#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10 6428 6429#define MDIO_REG_BANK_RX2 0x80d0 6430#define MDIO_RX2_RX_EQ_BOOST 0x1c 6431#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6432#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10 6433 6434#define MDIO_REG_BANK_RX3 0x80e0 6435#define MDIO_RX3_RX_EQ_BOOST 0x1c 6436#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6437#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10 6438 6439#define MDIO_REG_BANK_RX_ALL 0x80f0 6440#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c 6441#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6442#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10 6443 6444#define MDIO_REG_BANK_TX0 0x8060 6445#define MDIO_TX0_TX_DRIVER 0x17 6446#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6447#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6448#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6449#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6450#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6451#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6452#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6453#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6454#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6455 6456#define MDIO_REG_BANK_TX1 0x8070 6457#define MDIO_TX1_TX_DRIVER 0x17 6458#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6459#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6460#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6461#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6462#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6463#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6464#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6465#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6466#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6467 6468#define MDIO_REG_BANK_TX2 0x8080 6469#define MDIO_TX2_TX_DRIVER 0x17 6470#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6471#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6472#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6473#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6474#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6475#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6476#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6477#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6478#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6479 6480#define MDIO_REG_BANK_TX3 0x8090 6481#define MDIO_TX3_TX_DRIVER 0x17 6482#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6483#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6484#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6485#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6486#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6487#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6488#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6489#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6490#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6491 6492#define MDIO_REG_BANK_XGXS_BLOCK0 0x8000 6493#define MDIO_BLOCK0_XGXS_CONTROL 0x10 6494 6495#define MDIO_REG_BANK_XGXS_BLOCK1 0x8010 6496#define MDIO_BLOCK1_LANE_CTRL0 0x15 6497#define MDIO_BLOCK1_LANE_CTRL1 0x16 6498#define MDIO_BLOCK1_LANE_CTRL2 0x17 6499#define MDIO_BLOCK1_LANE_PRBS 0x19 6500 6501#define MDIO_REG_BANK_XGXS_BLOCK2 0x8100 6502#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10 6503#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000 6504#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 6505#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 6506#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 6507#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 6508#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 6509#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 6510#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 6511 6512#define MDIO_REG_BANK_GP_STATUS 0x8120 6513#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B 6514#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001 6515#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002 6516#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 6517#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 6518#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 6519#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 6520#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040 6521#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080 6522#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00 6523#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 6524#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 6525#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 6526#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 6527#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 6528#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 6529#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 6530#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 6531#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 6532#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 6533#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 6534#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 6535#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 6536#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 6537#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00 6538#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00 6539#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00 6540#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00 6541#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00 6542 6543 6544#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 6545#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10 6546#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000 6547#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 6548#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 6549#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 6550#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1) 6551 6552#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300 6553#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10 6554#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001 6555#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002 6556#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004 6557#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008 6558#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010 6559#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020 6560#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11 6561#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001 6562#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040 6563#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14 6564#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001 6565#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002 6566#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004 6567#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018 6568#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3 6569#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018 6570#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 6571#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 6572#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 6573#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15 6574#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002 6575#define MDIO_SERDES_DIGITAL_MISC1 0x18 6576#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 6577#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 6578#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000 6579#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000 6580#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000 6581#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000 6582#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010 6583#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f 6584#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000 6585#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001 6586#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002 6587#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003 6588#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004 6589#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005 6590#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006 6591#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007 6592#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008 6593#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009 6594 6595#define MDIO_REG_BANK_OVER_1G 0x8320 6596#define MDIO_OVER_1G_DIGCTL_3_4 0x14 6597#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0 6598#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5 6599#define MDIO_OVER_1G_UP1 0x19 6600#define MDIO_OVER_1G_UP1_2_5G 0x0001 6601#define MDIO_OVER_1G_UP1_5G 0x0002 6602#define MDIO_OVER_1G_UP1_6G 0x0004 6603#define MDIO_OVER_1G_UP1_10G 0x0010 6604#define MDIO_OVER_1G_UP1_10GH 0x0008 6605#define MDIO_OVER_1G_UP1_12G 0x0020 6606#define MDIO_OVER_1G_UP1_12_5G 0x0040 6607#define MDIO_OVER_1G_UP1_13G 0x0080 6608#define MDIO_OVER_1G_UP1_15G 0x0100 6609#define MDIO_OVER_1G_UP1_16G 0x0200 6610#define MDIO_OVER_1G_UP2 0x1A 6611#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007 6612#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038 6613#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0 6614#define MDIO_OVER_1G_UP3 0x1B 6615#define MDIO_OVER_1G_UP3_HIGIG2 0x0001 6616#define MDIO_OVER_1G_LP_UP1 0x1C 6617#define MDIO_OVER_1G_LP_UP2 0x1D 6618#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff 6619#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780 6620#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7 6621#define MDIO_OVER_1G_LP_UP3 0x1E 6622 6623#define MDIO_REG_BANK_REMOTE_PHY 0x8330 6624#define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10 6625#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010 6626#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600 6627 6628#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350 6629#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10 6630#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 6631#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 6632 6633#define MDIO_REG_BANK_CL73_USERB0 0x8370 6634#define MDIO_CL73_USERB0_CL73_UCTRL 0x10 6635#define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002 6636#define MDIO_CL73_USERB0_CL73_USTAT1 0x11 6637#define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100 6638#define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400 6639#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12 6640#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 6641#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000 6642#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000 6643#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14 6644#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001 6645 6646#define MDIO_REG_BANK_AER_BLOCK 0xFFD0 6647#define MDIO_AER_BLOCK_AER_REG 0x1E 6648 6649#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0 6650#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10 6651#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040 6652#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000 6653#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000 6654#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040 6655#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100 6656#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200 6657#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000 6658#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000 6659#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000 6660#define MDIO_COMBO_IEEE0_MII_STATUS 0x11 6661#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004 6662#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020 6663#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14 6664#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020 6665#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040 6666#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180 6667#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000 6668#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080 6669#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100 6670#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180 6671#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000 6672#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15 6673#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000 6674#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000 6675#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180 6676#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000 6677#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180 6678#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040 6679#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020 6680/*WhenthelinkpartnerisinSGMIImode(bit0=1),then 6681bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge. 6682Theotherbitsarereservedandshouldbezero*/ 6683#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001 6684 6685 6686#define MDIO_PMA_DEVAD 0x1 6687/*ieee*/ 6688#define MDIO_PMA_REG_CTRL 0x0 6689#define MDIO_PMA_REG_STATUS 0x1 6690#define MDIO_PMA_REG_10G_CTRL2 0x7 6691#define MDIO_PMA_REG_TX_DISABLE 0x0009 6692#define MDIO_PMA_REG_RX_SD 0xa 6693/*bcm*/ 6694#define MDIO_PMA_REG_BCM_CTRL 0x0096 6695#define MDIO_PMA_REG_FEC_CTRL 0x00ab 6696#define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800 6697#define MDIO_PMA_REG_DIGITAL_CTRL 0xc808 6698#define MDIO_PMA_REG_DIGITAL_STATUS 0xc809 6699#define MDIO_PMA_REG_TX_POWER_DOWN 0xca02 6700#define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09 6701#define MDIO_PMA_REG_MISC_CTRL 0xca0a 6702#define MDIO_PMA_REG_GEN_CTRL 0xca10 6703#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 6704#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a 6705#define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12 6706#define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13 6707#define MDIO_PMA_REG_ROM_VER1 0xca19 6708#define MDIO_PMA_REG_ROM_VER2 0xca1a 6709#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b 6710#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d 6711#define MDIO_PMA_REG_PLL_CTRL 0xca1e 6712#define MDIO_PMA_REG_MISC_CTRL0 0xca23 6713#define MDIO_PMA_REG_LRM_MODE 0xca3f 6714#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46 6715#define MDIO_PMA_REG_MISC_CTRL1 0xca85 6716 6717#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000 6718#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c 6719#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000 6720#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004 6721#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008 6722#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c 6723#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002 6724#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003 6725#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820 6726#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff 6727#define MDIO_PMA_REG_8726_TX_CTRL1 0xca01 6728#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 6729 6730#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005 6731#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007 6732#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff 6733#define MDIO_PMA_REG_8727_TX_CTRL1 0xca02 6734#define MDIO_PMA_REG_8727_TX_CTRL2 0xca05 6735#define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808 6736#define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e 6737#define MDIO_PMA_REG_8727_PCS_GP 0xc842 6738#define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4 6739 6740#define MDIO_AN_REG_8727_MISC_CTRL 0x8309 6741 6742#define MDIO_PMA_REG_8073_CHIP_REV 0xc801 6743#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820 6744#define MDIO_PMA_REG_8073_XAUI_WA 0xc841 6745#define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08 6746 6747#define MDIO_PMA_REG_7101_RESET 0xc000 6748#define MDIO_PMA_REG_7107_LED_CNTL 0xc007 6749#define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009 6750#define MDIO_PMA_REG_7101_VER1 0xc026 6751#define MDIO_PMA_REG_7101_VER2 0xc027 6752 6753#define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811 6754#define MDIO_PMA_REG_8481_LED1_MASK 0xa82c 6755#define MDIO_PMA_REG_8481_LED2_MASK 0xa82f 6756#define MDIO_PMA_REG_8481_LED3_MASK 0xa832 6757#define MDIO_PMA_REG_8481_LED3_BLINK 0xa834 6758#define MDIO_PMA_REG_8481_LED5_MASK 0xa838 6759#define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835 6760#define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b 6761#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800 6762#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11 6763 6764 6765#define MDIO_WIS_DEVAD 0x2 6766/*bcm*/ 6767#define MDIO_WIS_REG_LASI_CNTL 0x9002 6768#define MDIO_WIS_REG_LASI_STATUS 0x9005 6769 6770#define MDIO_PCS_DEVAD 0x3 6771#define MDIO_PCS_REG_STATUS 0x0020 6772#define MDIO_PCS_REG_LASI_STATUS 0x9005 6773#define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000 6774#define MDIO_PCS_REG_7101_SPI_MUX 0xD008 6775#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A 6776#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5) 6777#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A 6778#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6) 6779#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7) 6780#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2) 6781#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028 6782 6783 6784#define MDIO_XS_DEVAD 0x4 6785#define MDIO_XS_PLL_SEQUENCER 0x8000 6786#define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a 6787 6788#define MDIO_XS_8706_REG_BANK_RX0 0x80bc 6789#define MDIO_XS_8706_REG_BANK_RX1 0x80cc 6790#define MDIO_XS_8706_REG_BANK_RX2 0x80dc 6791#define MDIO_XS_8706_REG_BANK_RX3 0x80ec 6792#define MDIO_XS_8706_REG_BANK_RXA 0x80fc 6793 6794#define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA 6795 6796#define MDIO_AN_DEVAD 0x7 6797/*ieee*/ 6798#define MDIO_AN_REG_CTRL 0x0000 6799#define MDIO_AN_REG_STATUS 0x0001 6800#define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020 6801#define MDIO_AN_REG_ADV_PAUSE 0x0010 6802#define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400 6803#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800 6804#define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00 6805#define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00 6806#define MDIO_AN_REG_ADV 0x0011 6807#define MDIO_AN_REG_ADV2 0x0012 6808#define MDIO_AN_REG_LP_AUTO_NEG 0x0013 6809#define MDIO_AN_REG_LP_AUTO_NEG2 0x0014 6810#define MDIO_AN_REG_MASTER_STATUS 0x0021 6811/*bcm*/ 6812#define MDIO_AN_REG_LINK_STATUS 0x8304 6813#define MDIO_AN_REG_CL37_CL73 0x8370 6814#define MDIO_AN_REG_CL37_AN 0xffe0 6815#define MDIO_AN_REG_CL37_FC_LD 0xffe4 6816#define MDIO_AN_REG_CL37_FC_LP 0xffe5 6817#define MDIO_AN_REG_1000T_STATUS 0xffea 6818 6819#define MDIO_AN_REG_8073_2_5G 0x8329 6820#define MDIO_AN_REG_8073_BAM 0x8350 6821 6822#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020 6823#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0 6824#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1 6825#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4 6826#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6 6827#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9 6828#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5 6829#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7 6830#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8 6831#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc 6832 6833/* BCM84823 only */ 6834#define MDIO_CTL_DEVAD 0x1e 6835#define MDIO_CTL_REG_84823_MEDIA 0x401a 6836#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018 6837 /* These pins configure the BCM84823 interface to MAC after reset. */ 6838#define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008 6839#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010 6840 /* These pins configure the BCM84823 interface to Line after reset. */ 6841#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060 6842#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020 6843#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040 6844 /* When this pin is active high during reset, 10GBASE-T core is power 6845 * down, When it is active low the 10GBASE-T is power up 6846 */ 6847#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080 6848#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100 6849#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000 6850#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100 6851#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000 6852#define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005 6853#define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080 6854#define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b 6855#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f 6856#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3 6857#define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec 6858#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080 6859 6860/* BCM84833 only */ 6861#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a 6862#define MDIO_84833_SUPER_ISOLATE 0x8000 6863/* These are mailbox register set used by 84833. */ 6864#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005 6865#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006 6866#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007 6867#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008 6868#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009 6869#define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037 6870#define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038 6871#define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039 6872#define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a 6873#define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b 6874#define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c 6875#define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0 6876#define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26 6877#define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27 6878#define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28 6879#define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29 6880#define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30 6881#define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31 6882 6883/* Mailbox command set used by 84833. */ 6884#define PHY84833_CMD_SET_PAIR_SWAP 0x8001 6885#define PHY84833_CMD_GET_EEE_MODE 0x8008 6886#define PHY84833_CMD_SET_EEE_MODE 0x8009 6887/* Mailbox status set used by 84833. */ 6888#define PHY84833_STATUS_CMD_RECEIVED 0x0001 6889#define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002 6890#define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004 6891#define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008 6892#define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010 6893#define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020 6894#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040 6895#define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080 6896#define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5 6897 6898 6899/* Warpcore clause 45 addressing */ 6900#define MDIO_WC_DEVAD 0x3 6901#define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0 6902#define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7 6903#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10 6904#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11 6905#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12 6906#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000 6907#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000 6908#define MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150 0x96 6909#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000 6910#define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e 6911#define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010 6912#define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015 6913#define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016 6914#define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017 6915#define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061 6916#define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071 6917#define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081 6918#define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091 6919#define MDIO_WC_REG_TX0_TX_DRIVER 0x8067 6920#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04 6921#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0 6922#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08 6923#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6924#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c 6925#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000 6926#define MDIO_WC_REG_TX1_TX_DRIVER 0x8077 6927#define MDIO_WC_REG_TX2_TX_DRIVER 0x8087 6928#define MDIO_WC_REG_TX3_TX_DRIVER 0x8097 6929#define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9 6930#define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9 6931#define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba 6932#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca 6933#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da 6934#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea 6935#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104 6936#define MDIO_WC_REG_XGXS_STATUS3 0x8129 6937#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130 6938#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131 6939#define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141 6940#define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B 6941#define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169 6942#define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0 6943#define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1 6944#define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2 6945#define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3 6946#define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4 6947#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE 6948#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0 6949#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2 6950#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0 6951#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0 6952#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1 6953#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2 6954#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3 6955#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4 6956#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4 6957#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8 6958#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc 6959#define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE 6960#define MDIO_WC_REG_DSC_SMC 0x8213 6961#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e 6962#define MDIO_WC_REG_TX_FIR_TAP 0x82e2 6963#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00 6964#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f 6965#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04 6966#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0 6967#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a 6968#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00 6969#define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000 6970#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3 6971#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6 6972#define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7 6973#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8 6974#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec 6975#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300 6976#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301 6977#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302 6978#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304 6979#define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308 6980#define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309 6981#define MDIO_WC_REG_DIGITAL3_UP1 0x8329 6982#define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c 6983#define MDIO_WC_REG_DIGITAL4_MISC3 0x833c 6984#define MDIO_WC_REG_DIGITAL5_MISC6 0x8345 6985#define MDIO_WC_REG_DIGITAL5_MISC7 0x8349 6986#define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e 6987#define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350 6988#define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368 6989#define MDIO_WC_REG_TX66_CONTROL 0x83b0 6990#define MDIO_WC_REG_RX66_CONTROL 0x83c0 6991#define MDIO_WC_REG_RX66_SCW0 0x83c2 6992#define MDIO_WC_REG_RX66_SCW1 0x83c3 6993#define MDIO_WC_REG_RX66_SCW2 0x83c4 6994#define MDIO_WC_REG_RX66_SCW3 0x83c5 6995#define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6 6996#define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7 6997#define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8 6998#define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9 6999#define MDIO_WC_REG_FX100_CTRL1 0x8400 7000#define MDIO_WC_REG_FX100_CTRL3 0x8402 7001 7002#define MDIO_WC_REG_MICROBLK_CMD 0xffc2 7003#define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5 7004#define MDIO_WC_REG_MICROBLK_CMD3 0xffcc 7005 7006#define MDIO_WC_REG_AERBLK_AER 0xffde 7007#define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0 7008#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1 7009 7010#define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A 7011#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0 7012#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4 7013 7014#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141 7015 7016#define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f 7017 7018/* 54618se */ 7019#define MDIO_REG_GPHY_PHYID_LSB 0x3 7020#define MDIO_REG_GPHY_ID_54618SE 0x5cd5 7021#define MDIO_REG_GPHY_CL45_ADDR_REG 0xd 7022#define MDIO_REG_GPHY_CL45_DATA_REG 0xe 7023#define MDIO_REG_GPHY_EEE_ADV 0x3c 7024#define MDIO_REG_GPHY_EEE_1G (0x1 << 2) 7025#define MDIO_REG_GPHY_EEE_100 (0x1 << 1) 7026#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e 7027#define MDIO_REG_INTR_STATUS 0x1a 7028#define MDIO_REG_INTR_MASK 0x1b 7029#define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1) 7030#define MDIO_REG_GPHY_SHADOW 0x1c 7031#define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10) 7032#define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10) 7033#define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15) 7034#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10) 7035#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8) 7036 7037#define IGU_FUNC_BASE 0x0400 7038 7039#define IGU_ADDR_MSIX 0x0000 7040#define IGU_ADDR_INT_ACK 0x0200 7041#define IGU_ADDR_PROD_UPD 0x0201 7042#define IGU_ADDR_ATTN_BITS_UPD 0x0202 7043#define IGU_ADDR_ATTN_BITS_SET 0x0203 7044#define IGU_ADDR_ATTN_BITS_CLR 0x0204 7045#define IGU_ADDR_COALESCE_NOW 0x0205 7046#define IGU_ADDR_SIMD_MASK 0x0206 7047#define IGU_ADDR_SIMD_NOMASK 0x0207 7048#define IGU_ADDR_MSI_CTL 0x0210 7049#define IGU_ADDR_MSI_ADDR_LO 0x0211 7050#define IGU_ADDR_MSI_ADDR_HI 0x0212 7051#define IGU_ADDR_MSI_DATA 0x0213 7052 7053#define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0 7054#define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1 7055#define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2 7056#define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3 7057 7058#define COMMAND_REG_INT_ACK 0x0 7059#define COMMAND_REG_PROD_UPD 0x4 7060#define COMMAND_REG_ATTN_BITS_UPD 0x8 7061#define COMMAND_REG_ATTN_BITS_SET 0xc 7062#define COMMAND_REG_ATTN_BITS_CLR 0x10 7063#define COMMAND_REG_COALESCE_NOW 0x14 7064#define COMMAND_REG_SIMD_MASK 0x18 7065#define COMMAND_REG_SIMD_NOMASK 0x1c 7066 7067 7068#define IGU_MEM_BASE 0x0000 7069 7070#define IGU_MEM_MSIX_BASE 0x0000 7071#define IGU_MEM_MSIX_UPPER 0x007f 7072#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 7073 7074#define IGU_MEM_PBA_MSIX_BASE 0x0200 7075#define IGU_MEM_PBA_MSIX_UPPER 0x0200 7076 7077#define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201 7078#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 7079 7080#define IGU_CMD_INT_ACK_BASE 0x0400 7081#define IGU_CMD_INT_ACK_UPPER\ 7082 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1) 7083#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff 7084 7085#define IGU_CMD_E2_PROD_UPD_BASE 0x0500 7086#define IGU_CMD_E2_PROD_UPD_UPPER\ 7087 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1) 7088#define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f 7089 7090#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0 7091#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1 7092#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2 7093 7094#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3 7095#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4 7096#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5 7097#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6 7098 7099#define IGU_REG_RESERVED_UPPER 0x05ff 7100/* Fields of IGU PF CONFIGRATION REGISTER */ 7101#define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */ 7102#define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 7103#define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */ 7104#define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */ 7105#define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 7106#define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */ 7107 7108/* Fields of IGU VF CONFIGRATION REGISTER */ 7109#define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */ 7110#define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 7111#define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */ 7112#define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */ 7113#define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 7114 7115 7116#define IGU_BC_DSB_NUM_SEGS 5 7117#define IGU_BC_NDSB_NUM_SEGS 2 7118#define IGU_NORM_DSB_NUM_SEGS 2 7119#define IGU_NORM_NDSB_NUM_SEGS 1 7120#define IGU_BC_BASE_DSB_PROD 128 7121#define IGU_NORM_BASE_DSB_PROD 136 7122 7123 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \ 7124 [5:2] = 0; [1:0] = PF number) */ 7125#define IGU_FID_ENCODE_IS_PF (0x1<<6) 7126#define IGU_FID_ENCODE_IS_PF_SHIFT 6 7127#define IGU_FID_VF_NUM_MASK (0x3f) 7128#define IGU_FID_PF_NUM_MASK (0x7) 7129 7130#define IGU_REG_MAPPING_MEMORY_VALID (1<<0) 7131#define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1) 7132#define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1 7133#define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7) 7134#define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7 7135 7136 7137#define CDU_REGION_NUMBER_XCM_AG 2 7138#define CDU_REGION_NUMBER_UCM_AG 4 7139 7140 7141/** 7142 * String-to-compress [31:8] = CID (all 24 bits) 7143 * String-to-compress [7:4] = Region 7144 * String-to-compress [3:0] = Type 7145 */ 7146#define CDU_VALID_DATA(_cid, _region, _type)\ 7147 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf))) 7148#define CDU_CRC8(_cid, _region, _type)\ 7149 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)) 7150#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\ 7151 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f)) 7152#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\ 7153 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7)) 7154#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80) 7155 7156/****************************************************************************** 7157 * Description: 7158 * Calculates crc 8 on a word value: polynomial 0-1-2-8 7159 * Code was translated from Verilog. 7160 * Return: 7161 *****************************************************************************/ 7162static inline u8 calc_crc8(u32 data, u8 crc) 7163{ 7164 u8 D[32]; 7165 u8 NewCRC[8]; 7166 u8 C[8]; 7167 u8 crc_res; 7168 u8 i; 7169 7170 /* split the data into 31 bits */ 7171 for (i = 0; i < 32; i++) { 7172 D[i] = (u8)(data & 1); 7173 data = data >> 1; 7174 } 7175 7176 /* split the crc into 8 bits */ 7177 for (i = 0; i < 8; i++) { 7178 C[i] = crc & 1; 7179 crc = crc >> 1; 7180 } 7181 7182 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^ 7183 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^ 7184 C[6] ^ C[7]; 7185 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^ 7186 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ 7187 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ 7188 C[6]; 7189 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^ 7190 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ 7191 C[0] ^ C[1] ^ C[4] ^ C[5]; 7192 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^ 7193 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^ 7194 C[1] ^ C[2] ^ C[5] ^ C[6]; 7195 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^ 7196 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^ 7197 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7]; 7198 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^ 7199 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^ 7200 C[3] ^ C[4] ^ C[7]; 7201 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^ 7202 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ 7203 C[5]; 7204 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^ 7205 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ 7206 C[6]; 7207 7208 crc_res = 0; 7209 for (i = 0; i < 8; i++) 7210 crc_res |= (NewCRC[i] << i); 7211 7212 return crc_res; 7213} 7214 7215 7216#endif /* BNX2X_REG_H */ 7217