bnx2x_sp.h revision 259afa1f725dc7ec1626835b9ac54827a46cdf80
1/* bnx2x_sp.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2011-2012 Broadcom Corporation 4 * 5 * Unless you and Broadcom execute a separate written software license 6 * agreement governing use of this software, this software is licensed to you 7 * under the terms of the GNU General Public License version 2, available 8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 9 * 10 * Notwithstanding the above, under no circumstances may you combine this 11 * software in any way with any other Broadcom software provided under a 12 * license other than the GPL, without Broadcom's express prior written 13 * consent. 14 * 15 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 16 * Written by: Vladislav Zolotarov 17 * 18 */ 19#ifndef BNX2X_SP_VERBS 20#define BNX2X_SP_VERBS 21 22struct bnx2x; 23struct eth_context; 24 25/* Bits representing general command's configuration */ 26enum { 27 RAMROD_TX, 28 RAMROD_RX, 29 /* Wait until all pending commands complete */ 30 RAMROD_COMP_WAIT, 31 /* Don't send a ramrod, only update a registry */ 32 RAMROD_DRV_CLR_ONLY, 33 /* Configure HW according to the current object state */ 34 RAMROD_RESTORE, 35 /* Execute the next command now */ 36 RAMROD_EXEC, 37 /* 38 * Don't add a new command and continue execution of posponed 39 * commands. If not set a new command will be added to the 40 * pending commands list. 41 */ 42 RAMROD_CONT, 43}; 44 45typedef enum { 46 BNX2X_OBJ_TYPE_RX, 47 BNX2X_OBJ_TYPE_TX, 48 BNX2X_OBJ_TYPE_RX_TX, 49} bnx2x_obj_type; 50 51/* Filtering states */ 52enum { 53 BNX2X_FILTER_MAC_PENDING, 54 BNX2X_FILTER_VLAN_PENDING, 55 BNX2X_FILTER_VLAN_MAC_PENDING, 56 BNX2X_FILTER_RX_MODE_PENDING, 57 BNX2X_FILTER_RX_MODE_SCHED, 58 BNX2X_FILTER_ISCSI_ETH_START_SCHED, 59 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 60 BNX2X_FILTER_FCOE_ETH_START_SCHED, 61 BNX2X_FILTER_FCOE_ETH_STOP_SCHED, 62 BNX2X_FILTER_MCAST_PENDING, 63 BNX2X_FILTER_MCAST_SCHED, 64 BNX2X_FILTER_RSS_CONF_PENDING, 65}; 66 67struct bnx2x_raw_obj { 68 u8 func_id; 69 70 /* Queue params */ 71 u8 cl_id; 72 u32 cid; 73 74 /* Ramrod data buffer params */ 75 void *rdata; 76 dma_addr_t rdata_mapping; 77 78 /* Ramrod state params */ 79 int state; /* "ramrod is pending" state bit */ 80 unsigned long *pstate; /* pointer to state buffer */ 81 82 bnx2x_obj_type obj_type; 83 84 int (*wait_comp)(struct bnx2x *bp, 85 struct bnx2x_raw_obj *o); 86 87 bool (*check_pending)(struct bnx2x_raw_obj *o); 88 void (*clear_pending)(struct bnx2x_raw_obj *o); 89 void (*set_pending)(struct bnx2x_raw_obj *o); 90}; 91 92/************************* VLAN-MAC commands related parameters ***************/ 93struct bnx2x_mac_ramrod_data { 94 u8 mac[ETH_ALEN]; 95}; 96 97struct bnx2x_vlan_ramrod_data { 98 u16 vlan; 99}; 100 101struct bnx2x_vlan_mac_ramrod_data { 102 u8 mac[ETH_ALEN]; 103 u16 vlan; 104}; 105 106union bnx2x_classification_ramrod_data { 107 struct bnx2x_mac_ramrod_data mac; 108 struct bnx2x_vlan_ramrod_data vlan; 109 struct bnx2x_vlan_mac_ramrod_data vlan_mac; 110}; 111 112/* VLAN_MAC commands */ 113enum bnx2x_vlan_mac_cmd { 114 BNX2X_VLAN_MAC_ADD, 115 BNX2X_VLAN_MAC_DEL, 116 BNX2X_VLAN_MAC_MOVE, 117}; 118 119struct bnx2x_vlan_mac_data { 120 /* Requested command: BNX2X_VLAN_MAC_XX */ 121 enum bnx2x_vlan_mac_cmd cmd; 122 /* 123 * used to contain the data related vlan_mac_flags bits from 124 * ramrod parameters. 125 */ 126 unsigned long vlan_mac_flags; 127 128 /* Needed for MOVE command */ 129 struct bnx2x_vlan_mac_obj *target_obj; 130 131 union bnx2x_classification_ramrod_data u; 132}; 133 134/*************************** Exe Queue obj ************************************/ 135union bnx2x_exe_queue_cmd_data { 136 struct bnx2x_vlan_mac_data vlan_mac; 137 138 struct { 139 /* TODO */ 140 } mcast; 141}; 142 143struct bnx2x_exeq_elem { 144 struct list_head link; 145 146 /* Length of this element in the exe_chunk. */ 147 int cmd_len; 148 149 union bnx2x_exe_queue_cmd_data cmd_data; 150}; 151 152union bnx2x_qable_obj; 153 154union bnx2x_exeq_comp_elem { 155 union event_ring_elem *elem; 156}; 157 158struct bnx2x_exe_queue_obj; 159 160typedef int (*exe_q_validate)(struct bnx2x *bp, 161 union bnx2x_qable_obj *o, 162 struct bnx2x_exeq_elem *elem); 163 164typedef int (*exe_q_remove)(struct bnx2x *bp, 165 union bnx2x_qable_obj *o, 166 struct bnx2x_exeq_elem *elem); 167 168/** 169 * @return positive is entry was optimized, 0 - if not, negative 170 * in case of an error. 171 */ 172typedef int (*exe_q_optimize)(struct bnx2x *bp, 173 union bnx2x_qable_obj *o, 174 struct bnx2x_exeq_elem *elem); 175typedef int (*exe_q_execute)(struct bnx2x *bp, 176 union bnx2x_qable_obj *o, 177 struct list_head *exe_chunk, 178 unsigned long *ramrod_flags); 179typedef struct bnx2x_exeq_elem * 180 (*exe_q_get)(struct bnx2x_exe_queue_obj *o, 181 struct bnx2x_exeq_elem *elem); 182 183struct bnx2x_exe_queue_obj { 184 /* 185 * Commands pending for an execution. 186 */ 187 struct list_head exe_queue; 188 189 /* 190 * Commands pending for an completion. 191 */ 192 struct list_head pending_comp; 193 194 spinlock_t lock; 195 196 /* Maximum length of commands' list for one execution */ 197 int exe_chunk_len; 198 199 union bnx2x_qable_obj *owner; 200 201 /****** Virtual functions ******/ 202 /** 203 * Called before commands execution for commands that are really 204 * going to be executed (after 'optimize'). 205 * 206 * Must run under exe_queue->lock 207 */ 208 exe_q_validate validate; 209 210 /** 211 * Called before removing pending commands, cleaning allocated 212 * resources (e.g., credits from validate) 213 */ 214 exe_q_remove remove; 215 216 /** 217 * This will try to cancel the current pending commands list 218 * considering the new command. 219 * 220 * Returns the number of optimized commands or a negative error code 221 * 222 * Must run under exe_queue->lock 223 */ 224 exe_q_optimize optimize; 225 226 /** 227 * Run the next commands chunk (owner specific). 228 */ 229 exe_q_execute execute; 230 231 /** 232 * Return the exe_queue element containing the specific command 233 * if any. Otherwise return NULL. 234 */ 235 exe_q_get get; 236}; 237/***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 238/* 239 * Element in the VLAN_MAC registry list having all currenty configured 240 * rules. 241 */ 242struct bnx2x_vlan_mac_registry_elem { 243 struct list_head link; 244 245 /* 246 * Used to store the cam offset used for the mac/vlan/vlan-mac. 247 * Relevant for 57710 and 57711 only. VLANs and MACs share the 248 * same CAM for these chips. 249 */ 250 int cam_offset; 251 252 /* Needed for DEL and RESTORE flows */ 253 unsigned long vlan_mac_flags; 254 255 union bnx2x_classification_ramrod_data u; 256}; 257 258/* Bits representing VLAN_MAC commands specific flags */ 259enum { 260 BNX2X_UC_LIST_MAC, 261 BNX2X_ETH_MAC, 262 BNX2X_ISCSI_ETH_MAC, 263 BNX2X_NETQ_ETH_MAC, 264 BNX2X_DONT_CONSUME_CAM_CREDIT, 265 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, 266}; 267 268struct bnx2x_vlan_mac_ramrod_params { 269 /* Object to run the command from */ 270 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 271 272 /* General command flags: COMP_WAIT, etc. */ 273 unsigned long ramrod_flags; 274 275 /* Command specific configuration request */ 276 struct bnx2x_vlan_mac_data user_req; 277}; 278 279struct bnx2x_vlan_mac_obj { 280 struct bnx2x_raw_obj raw; 281 282 /* Bookkeeping list: will prevent the addition of already existing 283 * entries. 284 */ 285 struct list_head head; 286 287 /* TODO: Add it's initialization in the init functions */ 288 struct bnx2x_exe_queue_obj exe_queue; 289 290 /* MACs credit pool */ 291 struct bnx2x_credit_pool_obj *macs_pool; 292 293 /* VLANs credit pool */ 294 struct bnx2x_credit_pool_obj *vlans_pool; 295 296 /* RAMROD command to be used */ 297 int ramrod_cmd; 298 299 /* copy first n elements onto preallocated buffer 300 * 301 * @param n number of elements to get 302 * @param buf buffer preallocated by caller into which elements 303 * will be copied. Note elements are 4-byte aligned 304 * so buffer size must be able to accomodate the 305 * aligned elements. 306 * 307 * @return number of copied bytes 308 */ 309 int (*get_n_elements)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 310 int n, u8 *buf); 311 312 /** 313 * Checks if ADD-ramrod with the given params may be performed. 314 * 315 * @return zero if the element may be added 316 */ 317 318 int (*check_add)(struct bnx2x_vlan_mac_obj *o, 319 union bnx2x_classification_ramrod_data *data); 320 321 /** 322 * Checks if DEL-ramrod with the given params may be performed. 323 * 324 * @return true if the element may be deleted 325 */ 326 struct bnx2x_vlan_mac_registry_elem * 327 (*check_del)(struct bnx2x_vlan_mac_obj *o, 328 union bnx2x_classification_ramrod_data *data); 329 330 /** 331 * Checks if DEL-ramrod with the given params may be performed. 332 * 333 * @return true if the element may be deleted 334 */ 335 bool (*check_move)(struct bnx2x_vlan_mac_obj *src_o, 336 struct bnx2x_vlan_mac_obj *dst_o, 337 union bnx2x_classification_ramrod_data *data); 338 339 /** 340 * Update the relevant credit object(s) (consume/return 341 * correspondingly). 342 */ 343 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o); 344 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o); 345 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset); 346 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset); 347 348 /** 349 * Configures one rule in the ramrod data buffer. 350 */ 351 void (*set_one_rule)(struct bnx2x *bp, 352 struct bnx2x_vlan_mac_obj *o, 353 struct bnx2x_exeq_elem *elem, int rule_idx, 354 int cam_offset); 355 356 /** 357 * Delete all configured elements having the given 358 * vlan_mac_flags specification. Assumes no pending for 359 * execution commands. Will schedule all all currently 360 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 361 * specification for deletion and will use the given 362 * ramrod_flags for the last DEL operation. 363 * 364 * @param bp 365 * @param o 366 * @param ramrod_flags RAMROD_XX flags 367 * 368 * @return 0 if the last operation has completed successfully 369 * and there are no more elements left, positive value 370 * if there are pending for completion commands, 371 * negative value in case of failure. 372 */ 373 int (*delete_all)(struct bnx2x *bp, 374 struct bnx2x_vlan_mac_obj *o, 375 unsigned long *vlan_mac_flags, 376 unsigned long *ramrod_flags); 377 378 /** 379 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 380 * configured elements list. 381 * 382 * @param bp 383 * @param p Command parameters (RAMROD_COMP_WAIT bit in 384 * ramrod_flags is only taken into an account) 385 * @param ppos a pointer to the cooky that should be given back in the 386 * next call to make function handle the next element. If 387 * *ppos is set to NULL it will restart the iterator. 388 * If returned *ppos == NULL this means that the last 389 * element has been handled. 390 * 391 * @return int 392 */ 393 int (*restore)(struct bnx2x *bp, 394 struct bnx2x_vlan_mac_ramrod_params *p, 395 struct bnx2x_vlan_mac_registry_elem **ppos); 396 397 /** 398 * Should be called on a completion arival. 399 * 400 * @param bp 401 * @param o 402 * @param cqe Completion element we are handling 403 * @param ramrod_flags if RAMROD_CONT is set the next bulk of 404 * pending commands will be executed. 405 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 406 * may also be set if needed. 407 * 408 * @return 0 if there are neither pending nor waiting for 409 * completion commands. Positive value if there are 410 * pending for execution or for completion commands. 411 * Negative value in case of an error (including an 412 * error in the cqe). 413 */ 414 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 415 union event_ring_elem *cqe, 416 unsigned long *ramrod_flags); 417 418 /** 419 * Wait for completion of all commands. Don't schedule new ones, 420 * just wait. It assumes that the completion code will schedule 421 * for new commands. 422 */ 423 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o); 424}; 425 426enum { 427 BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0, 428 BNX2X_LLH_CAM_ETH_LINE, 429 BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 430}; 431 432 433/** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 434 435/* RX_MODE ramrod spesial flags: set in rx_mode_flags field in 436 * a bnx2x_rx_mode_ramrod_params. 437 */ 438enum { 439 BNX2X_RX_MODE_FCOE_ETH, 440 BNX2X_RX_MODE_ISCSI_ETH, 441}; 442 443enum { 444 BNX2X_ACCEPT_UNICAST, 445 BNX2X_ACCEPT_MULTICAST, 446 BNX2X_ACCEPT_ALL_UNICAST, 447 BNX2X_ACCEPT_ALL_MULTICAST, 448 BNX2X_ACCEPT_BROADCAST, 449 BNX2X_ACCEPT_UNMATCHED, 450 BNX2X_ACCEPT_ANY_VLAN 451}; 452 453struct bnx2x_rx_mode_ramrod_params { 454 struct bnx2x_rx_mode_obj *rx_mode_obj; 455 unsigned long *pstate; 456 int state; 457 u8 cl_id; 458 u32 cid; 459 u8 func_id; 460 unsigned long ramrod_flags; 461 unsigned long rx_mode_flags; 462 463 /* 464 * rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 465 * a tstorm_eth_mac_filter_config (e1x). 466 */ 467 void *rdata; 468 dma_addr_t rdata_mapping; 469 470 /* Rx mode settings */ 471 unsigned long rx_accept_flags; 472 473 /* internal switching settings */ 474 unsigned long tx_accept_flags; 475}; 476 477struct bnx2x_rx_mode_obj { 478 int (*config_rx_mode)(struct bnx2x *bp, 479 struct bnx2x_rx_mode_ramrod_params *p); 480 481 int (*wait_comp)(struct bnx2x *bp, 482 struct bnx2x_rx_mode_ramrod_params *p); 483}; 484 485/********************** Set multicast group ***********************************/ 486 487struct bnx2x_mcast_list_elem { 488 struct list_head link; 489 u8 *mac; 490}; 491 492union bnx2x_mcast_config_data { 493 u8 *mac; 494 u8 bin; /* used in a RESTORE flow */ 495}; 496 497struct bnx2x_mcast_ramrod_params { 498 struct bnx2x_mcast_obj *mcast_obj; 499 500 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 501 unsigned long ramrod_flags; 502 503 struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */ 504 /** TODO: 505 * - rename it to macs_num. 506 * - Add a new command type for handling pending commands 507 * (remove "zero semantics"). 508 * 509 * Length of mcast_list. If zero and ADD_CONT command - post 510 * pending commands. 511 */ 512 int mcast_list_len; 513}; 514 515enum { 516 BNX2X_MCAST_CMD_ADD, 517 BNX2X_MCAST_CMD_CONT, 518 BNX2X_MCAST_CMD_DEL, 519 BNX2X_MCAST_CMD_RESTORE, 520}; 521 522struct bnx2x_mcast_obj { 523 struct bnx2x_raw_obj raw; 524 525 union { 526 struct { 527 #define BNX2X_MCAST_BINS_NUM 256 528 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64) 529 u64 vec[BNX2X_MCAST_VEC_SZ]; 530 531 /** Number of BINs to clear. Should be updated 532 * immediately when a command arrives in order to 533 * properly create DEL commands. 534 */ 535 int num_bins_set; 536 } aprox_match; 537 538 struct { 539 struct list_head macs; 540 int num_macs_set; 541 } exact_match; 542 } registry; 543 544 /* Pending commands */ 545 struct list_head pending_cmds_head; 546 547 /* A state that is set in raw.pstate, when there are pending commands */ 548 int sched_state; 549 550 /* Maximal number of mcast MACs configured in one command */ 551 int max_cmd_len; 552 553 /* Total number of currently pending MACs to configure: both 554 * in the pending commands list and in the current command. 555 */ 556 int total_pending_num; 557 558 u8 engine_id; 559 560 /** 561 * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above) 562 */ 563 int (*config_mcast)(struct bnx2x *bp, 564 struct bnx2x_mcast_ramrod_params *p, int cmd); 565 566 /** 567 * Fills the ramrod data during the RESTORE flow. 568 * 569 * @param bp 570 * @param o 571 * @param start_idx Registry index to start from 572 * @param rdata_idx Index in the ramrod data to start from 573 * 574 * @return -1 if we handled the whole registry or index of the last 575 * handled registry element. 576 */ 577 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 578 int start_bin, int *rdata_idx); 579 580 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 581 struct bnx2x_mcast_ramrod_params *p, int cmd); 582 583 void (*set_one_rule)(struct bnx2x *bp, 584 struct bnx2x_mcast_obj *o, int idx, 585 union bnx2x_mcast_config_data *cfg_data, int cmd); 586 587 /** Checks if there are more mcast MACs to be set or a previous 588 * command is still pending. 589 */ 590 bool (*check_pending)(struct bnx2x_mcast_obj *o); 591 592 /** 593 * Set/Clear/Check SCHEDULED state of the object 594 */ 595 void (*set_sched)(struct bnx2x_mcast_obj *o); 596 void (*clear_sched)(struct bnx2x_mcast_obj *o); 597 bool (*check_sched)(struct bnx2x_mcast_obj *o); 598 599 /* Wait until all pending commands complete */ 600 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o); 601 602 /** 603 * Handle the internal object counters needed for proper 604 * commands handling. Checks that the provided parameters are 605 * feasible. 606 */ 607 int (*validate)(struct bnx2x *bp, 608 struct bnx2x_mcast_ramrod_params *p, int cmd); 609 610 /** 611 * Restore the values of internal counters in case of a failure. 612 */ 613 void (*revert)(struct bnx2x *bp, 614 struct bnx2x_mcast_ramrod_params *p, 615 int old_num_bins); 616 617 int (*get_registry_size)(struct bnx2x_mcast_obj *o); 618 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n); 619}; 620 621/*************************** Credit handling **********************************/ 622struct bnx2x_credit_pool_obj { 623 624 /* Current amount of credit in the pool */ 625 atomic_t credit; 626 627 /* Maximum allowed credit. put() will check against it. */ 628 int pool_sz; 629 630 /* 631 * Allocate a pool table statically. 632 * 633 * Currently the mamimum allowed size is MAX_MAC_CREDIT_E2(272) 634 * 635 * The set bit in the table will mean that the entry is available. 636 */ 637#define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 638 u64 pool_mirror[BNX2X_POOL_VEC_SIZE]; 639 640 /* Base pool offset (initialized differently */ 641 int base_pool_offset; 642 643 /** 644 * Get the next free pool entry. 645 * 646 * @return true if there was a free entry in the pool 647 */ 648 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry); 649 650 /** 651 * Return the entry back to the pool. 652 * 653 * @return true if entry is legal and has been successfully 654 * returned to the pool. 655 */ 656 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry); 657 658 /** 659 * Get the requested amount of credit from the pool. 660 * 661 * @param cnt Amount of requested credit 662 * @return true if the operation is successful 663 */ 664 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt); 665 666 /** 667 * Returns the credit to the pool. 668 * 669 * @param cnt Amount of credit to return 670 * @return true if the operation is successful 671 */ 672 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt); 673 674 /** 675 * Reads the current amount of credit. 676 */ 677 int (*check)(struct bnx2x_credit_pool_obj *o); 678}; 679 680/*************************** RSS configuration ********************************/ 681enum { 682 /* RSS_MODE bits are mutually exclusive */ 683 BNX2X_RSS_MODE_DISABLED, 684 BNX2X_RSS_MODE_REGULAR, 685 BNX2X_RSS_MODE_VLAN_PRI, 686 BNX2X_RSS_MODE_E1HOV_PRI, 687 BNX2X_RSS_MODE_IP_DSCP, 688 689 BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 690 691 BNX2X_RSS_IPV4, 692 BNX2X_RSS_IPV4_TCP, 693 BNX2X_RSS_IPV6, 694 BNX2X_RSS_IPV6_TCP, 695}; 696 697struct bnx2x_config_rss_params { 698 struct bnx2x_rss_config_obj *rss_obj; 699 700 /* may have RAMROD_COMP_WAIT set only */ 701 unsigned long ramrod_flags; 702 703 /* BNX2X_RSS_X bits */ 704 unsigned long rss_flags; 705 706 /* Number hash bits to take into an account */ 707 u8 rss_result_mask; 708 709 /* Indirection table */ 710 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 711 712 /* RSS hash values */ 713 u32 rss_key[10]; 714 715 /* valid only iff BNX2X_RSS_UPDATE_TOE is set */ 716 u16 toe_rss_bitmap; 717}; 718 719struct bnx2x_rss_config_obj { 720 struct bnx2x_raw_obj raw; 721 722 /* RSS engine to use */ 723 u8 engine_id; 724 725 /* Last configured indirection table */ 726 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 727 728 int (*config_rss)(struct bnx2x *bp, 729 struct bnx2x_config_rss_params *p); 730}; 731 732/*********************** Queue state update ***********************************/ 733 734/* UPDATE command options */ 735enum { 736 BNX2X_Q_UPDATE_IN_VLAN_REM, 737 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, 738 BNX2X_Q_UPDATE_OUT_VLAN_REM, 739 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, 740 BNX2X_Q_UPDATE_ANTI_SPOOF, 741 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, 742 BNX2X_Q_UPDATE_ACTIVATE, 743 BNX2X_Q_UPDATE_ACTIVATE_CHNG, 744 BNX2X_Q_UPDATE_DEF_VLAN_EN, 745 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 746 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 747 BNX2X_Q_UPDATE_SILENT_VLAN_REM 748}; 749 750/* Allowed Queue states */ 751enum bnx2x_q_state { 752 BNX2X_Q_STATE_RESET, 753 BNX2X_Q_STATE_INITIALIZED, 754 BNX2X_Q_STATE_ACTIVE, 755 BNX2X_Q_STATE_MULTI_COS, 756 BNX2X_Q_STATE_MCOS_TERMINATED, 757 BNX2X_Q_STATE_INACTIVE, 758 BNX2X_Q_STATE_STOPPED, 759 BNX2X_Q_STATE_TERMINATED, 760 BNX2X_Q_STATE_FLRED, 761 BNX2X_Q_STATE_MAX, 762}; 763 764/* Allowed commands */ 765enum bnx2x_queue_cmd { 766 BNX2X_Q_CMD_INIT, 767 BNX2X_Q_CMD_SETUP, 768 BNX2X_Q_CMD_SETUP_TX_ONLY, 769 BNX2X_Q_CMD_DEACTIVATE, 770 BNX2X_Q_CMD_ACTIVATE, 771 BNX2X_Q_CMD_UPDATE, 772 BNX2X_Q_CMD_UPDATE_TPA, 773 BNX2X_Q_CMD_HALT, 774 BNX2X_Q_CMD_CFC_DEL, 775 BNX2X_Q_CMD_TERMINATE, 776 BNX2X_Q_CMD_EMPTY, 777 BNX2X_Q_CMD_MAX, 778}; 779 780/* queue SETUP + INIT flags */ 781enum { 782 BNX2X_Q_FLG_TPA, 783 BNX2X_Q_FLG_TPA_IPV6, 784 BNX2X_Q_FLG_TPA_GRO, 785 BNX2X_Q_FLG_STATS, 786 BNX2X_Q_FLG_ZERO_STATS, 787 BNX2X_Q_FLG_ACTIVE, 788 BNX2X_Q_FLG_OV, 789 BNX2X_Q_FLG_VLAN, 790 BNX2X_Q_FLG_COS, 791 BNX2X_Q_FLG_HC, 792 BNX2X_Q_FLG_HC_EN, 793 BNX2X_Q_FLG_DHC, 794 BNX2X_Q_FLG_FCOE, 795 BNX2X_Q_FLG_LEADING_RSS, 796 BNX2X_Q_FLG_MCAST, 797 BNX2X_Q_FLG_DEF_VLAN, 798 BNX2X_Q_FLG_TX_SWITCH, 799 BNX2X_Q_FLG_TX_SEC, 800 BNX2X_Q_FLG_ANTI_SPOOF, 801 BNX2X_Q_FLG_SILENT_VLAN_REM 802}; 803 804/* Queue type options: queue type may be a compination of below. */ 805enum bnx2x_q_type { 806 /** TODO: Consider moving both these flags into the init() 807 * ramrod params. 808 */ 809 BNX2X_Q_TYPE_HAS_RX, 810 BNX2X_Q_TYPE_HAS_TX, 811}; 812 813#define BNX2X_PRIMARY_CID_INDEX 0 814#define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */ 815#define BNX2X_MULTI_TX_COS_E2_E3A0 2 816#define BNX2X_MULTI_TX_COS_E3B0 3 817#define BNX2X_MULTI_TX_COS 3 /* Maximum possible */ 818 819 820struct bnx2x_queue_init_params { 821 struct { 822 unsigned long flags; 823 u16 hc_rate; 824 u8 fw_sb_id; 825 u8 sb_cq_index; 826 } tx; 827 828 struct { 829 unsigned long flags; 830 u16 hc_rate; 831 u8 fw_sb_id; 832 u8 sb_cq_index; 833 } rx; 834 835 /* CID context in the host memory */ 836 struct eth_context *cxts[BNX2X_MULTI_TX_COS]; 837 838 /* maximum number of cos supported by hardware */ 839 u8 max_cos; 840}; 841 842struct bnx2x_queue_terminate_params { 843 /* index within the tx_only cids of this queue object */ 844 u8 cid_index; 845}; 846 847struct bnx2x_queue_cfc_del_params { 848 /* index within the tx_only cids of this queue object */ 849 u8 cid_index; 850}; 851 852struct bnx2x_queue_update_params { 853 unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */ 854 u16 def_vlan; 855 u16 silent_removal_value; 856 u16 silent_removal_mask; 857/* index within the tx_only cids of this queue object */ 858 u8 cid_index; 859}; 860 861struct rxq_pause_params { 862 u16 bd_th_lo; 863 u16 bd_th_hi; 864 u16 rcq_th_lo; 865 u16 rcq_th_hi; 866 u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */ 867 u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */ 868 u16 pri_map; 869}; 870 871/* general */ 872struct bnx2x_general_setup_params { 873 /* valid iff BNX2X_Q_FLG_STATS */ 874 u8 stat_id; 875 876 u8 spcl_id; 877 u16 mtu; 878 u8 cos; 879}; 880 881struct bnx2x_rxq_setup_params { 882 /* dma */ 883 dma_addr_t dscr_map; 884 dma_addr_t sge_map; 885 dma_addr_t rcq_map; 886 dma_addr_t rcq_np_map; 887 888 u16 drop_flags; 889 u16 buf_sz; 890 u8 fw_sb_id; 891 u8 cl_qzone_id; 892 893 /* valid iff BNX2X_Q_FLG_TPA */ 894 u16 tpa_agg_sz; 895 u16 sge_buf_sz; 896 u8 max_sges_pkt; 897 u8 max_tpa_queues; 898 u8 rss_engine_id; 899 900 /* valid iff BNX2X_Q_FLG_MCAST */ 901 u8 mcast_engine_id; 902 903 u8 cache_line_log; 904 905 u8 sb_cq_index; 906 907 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ 908 u16 silent_removal_value; 909 u16 silent_removal_mask; 910}; 911 912struct bnx2x_txq_setup_params { 913 /* dma */ 914 dma_addr_t dscr_map; 915 916 u8 fw_sb_id; 917 u8 sb_cq_index; 918 u8 cos; /* valid iff BNX2X_Q_FLG_COS */ 919 u16 traffic_type; 920 /* equals to the leading rss client id, used for TX classification*/ 921 u8 tss_leading_cl_id; 922 923 /* valid iff BNX2X_Q_FLG_DEF_VLAN */ 924 u16 default_vlan; 925}; 926 927struct bnx2x_queue_setup_params { 928 struct bnx2x_general_setup_params gen_params; 929 struct bnx2x_txq_setup_params txq_params; 930 struct bnx2x_rxq_setup_params rxq_params; 931 struct rxq_pause_params pause_params; 932 unsigned long flags; 933}; 934 935struct bnx2x_queue_setup_tx_only_params { 936 struct bnx2x_general_setup_params gen_params; 937 struct bnx2x_txq_setup_params txq_params; 938 unsigned long flags; 939 /* index within the tx_only cids of this queue object */ 940 u8 cid_index; 941}; 942 943struct bnx2x_queue_state_params { 944 struct bnx2x_queue_sp_obj *q_obj; 945 946 /* Current command */ 947 enum bnx2x_queue_cmd cmd; 948 949 /* may have RAMROD_COMP_WAIT set only */ 950 unsigned long ramrod_flags; 951 952 /* Params according to the current command */ 953 union { 954 struct bnx2x_queue_update_params update; 955 struct bnx2x_queue_setup_params setup; 956 struct bnx2x_queue_init_params init; 957 struct bnx2x_queue_setup_tx_only_params tx_only; 958 struct bnx2x_queue_terminate_params terminate; 959 struct bnx2x_queue_cfc_del_params cfc_del; 960 } params; 961}; 962 963struct bnx2x_queue_sp_obj { 964 u32 cids[BNX2X_MULTI_TX_COS]; 965 u8 cl_id; 966 u8 func_id; 967 968 /* 969 * number of traffic classes supported by queue. 970 * The primary connection of the queue suppotrs the first traffic 971 * class. Any further traffic class is suppoted by a tx-only 972 * connection. 973 * 974 * Therefore max_cos is also a number of valid entries in the cids 975 * array. 976 */ 977 u8 max_cos; 978 u8 num_tx_only, next_tx_only; 979 980 enum bnx2x_q_state state, next_state; 981 982 /* bits from enum bnx2x_q_type */ 983 unsigned long type; 984 985 /* BNX2X_Q_CMD_XX bits. This object implements "one 986 * pending" paradigm but for debug and tracing purposes it's 987 * more convinient to have different bits for different 988 * commands. 989 */ 990 unsigned long pending; 991 992 /* Buffer to use as a ramrod data and its mapping */ 993 void *rdata; 994 dma_addr_t rdata_mapping; 995 996 /** 997 * Performs one state change according to the given parameters. 998 * 999 * @return 0 in case of success and negative value otherwise. 1000 */ 1001 int (*send_cmd)(struct bnx2x *bp, 1002 struct bnx2x_queue_state_params *params); 1003 1004 /** 1005 * Sets the pending bit according to the requested transition. 1006 */ 1007 int (*set_pending)(struct bnx2x_queue_sp_obj *o, 1008 struct bnx2x_queue_state_params *params); 1009 1010 /** 1011 * Checks that the requested state transition is legal. 1012 */ 1013 int (*check_transition)(struct bnx2x *bp, 1014 struct bnx2x_queue_sp_obj *o, 1015 struct bnx2x_queue_state_params *params); 1016 1017 /** 1018 * Completes the pending command. 1019 */ 1020 int (*complete_cmd)(struct bnx2x *bp, 1021 struct bnx2x_queue_sp_obj *o, 1022 enum bnx2x_queue_cmd); 1023 1024 int (*wait_comp)(struct bnx2x *bp, 1025 struct bnx2x_queue_sp_obj *o, 1026 enum bnx2x_queue_cmd cmd); 1027}; 1028 1029/********************** Function state update *********************************/ 1030/* Allowed Function states */ 1031enum bnx2x_func_state { 1032 BNX2X_F_STATE_RESET, 1033 BNX2X_F_STATE_INITIALIZED, 1034 BNX2X_F_STATE_STARTED, 1035 BNX2X_F_STATE_TX_STOPPED, 1036 BNX2X_F_STATE_MAX, 1037}; 1038 1039/* Allowed Function commands */ 1040enum bnx2x_func_cmd { 1041 BNX2X_F_CMD_HW_INIT, 1042 BNX2X_F_CMD_START, 1043 BNX2X_F_CMD_STOP, 1044 BNX2X_F_CMD_HW_RESET, 1045 BNX2X_F_CMD_TX_STOP, 1046 BNX2X_F_CMD_TX_START, 1047 BNX2X_F_CMD_MAX, 1048}; 1049 1050struct bnx2x_func_hw_init_params { 1051 /* A load phase returned by MCP. 1052 * 1053 * May be: 1054 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1055 * FW_MSG_CODE_DRV_LOAD_COMMON 1056 * FW_MSG_CODE_DRV_LOAD_PORT 1057 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1058 */ 1059 u32 load_phase; 1060}; 1061 1062struct bnx2x_func_hw_reset_params { 1063 /* A load phase returned by MCP. 1064 * 1065 * May be: 1066 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1067 * FW_MSG_CODE_DRV_LOAD_COMMON 1068 * FW_MSG_CODE_DRV_LOAD_PORT 1069 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1070 */ 1071 u32 reset_phase; 1072}; 1073 1074struct bnx2x_func_start_params { 1075 /* Multi Function mode: 1076 * - Single Function 1077 * - Switch Dependent 1078 * - Switch Independent 1079 */ 1080 u16 mf_mode; 1081 1082 /* Switch Dependent mode outer VLAN tag */ 1083 u16 sd_vlan_tag; 1084 1085 /* Function cos mode */ 1086 u8 network_cos_mode; 1087}; 1088 1089struct bnx2x_func_tx_start_params { 1090 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1091 u8 dcb_enabled; 1092 u8 dcb_version; 1093 u8 dont_add_pri_0_en; 1094}; 1095 1096struct bnx2x_func_state_params { 1097 struct bnx2x_func_sp_obj *f_obj; 1098 1099 /* Current command */ 1100 enum bnx2x_func_cmd cmd; 1101 1102 /* may have RAMROD_COMP_WAIT set only */ 1103 unsigned long ramrod_flags; 1104 1105 /* Params according to the current command */ 1106 union { 1107 struct bnx2x_func_hw_init_params hw_init; 1108 struct bnx2x_func_hw_reset_params hw_reset; 1109 struct bnx2x_func_start_params start; 1110 struct bnx2x_func_tx_start_params tx_start; 1111 } params; 1112}; 1113 1114struct bnx2x_func_sp_drv_ops { 1115 /* Init tool + runtime initialization: 1116 * - Common Chip 1117 * - Common (per Path) 1118 * - Port 1119 * - Function phases 1120 */ 1121 int (*init_hw_cmn_chip)(struct bnx2x *bp); 1122 int (*init_hw_cmn)(struct bnx2x *bp); 1123 int (*init_hw_port)(struct bnx2x *bp); 1124 int (*init_hw_func)(struct bnx2x *bp); 1125 1126 /* Reset Function HW: Common, Port, Function phases. */ 1127 void (*reset_hw_cmn)(struct bnx2x *bp); 1128 void (*reset_hw_port)(struct bnx2x *bp); 1129 void (*reset_hw_func)(struct bnx2x *bp); 1130 1131 /* Init/Free GUNZIP resources */ 1132 int (*gunzip_init)(struct bnx2x *bp); 1133 void (*gunzip_end)(struct bnx2x *bp); 1134 1135 /* Prepare/Release FW resources */ 1136 int (*init_fw)(struct bnx2x *bp); 1137 void (*release_fw)(struct bnx2x *bp); 1138}; 1139 1140struct bnx2x_func_sp_obj { 1141 enum bnx2x_func_state state, next_state; 1142 1143 /* BNX2X_FUNC_CMD_XX bits. This object implements "one 1144 * pending" paradigm but for debug and tracing purposes it's 1145 * more convinient to have different bits for different 1146 * commands. 1147 */ 1148 unsigned long pending; 1149 1150 /* Buffer to use as a ramrod data and its mapping */ 1151 void *rdata; 1152 dma_addr_t rdata_mapping; 1153 1154 /* this mutex validates that when pending flag is taken, the next 1155 * ramrod to be sent will be the one set the pending bit 1156 */ 1157 struct mutex one_pending_mutex; 1158 1159 /* Driver interface */ 1160 struct bnx2x_func_sp_drv_ops *drv; 1161 1162 /** 1163 * Performs one state change according to the given parameters. 1164 * 1165 * @return 0 in case of success and negative value otherwise. 1166 */ 1167 int (*send_cmd)(struct bnx2x *bp, 1168 struct bnx2x_func_state_params *params); 1169 1170 /** 1171 * Checks that the requested state transition is legal. 1172 */ 1173 int (*check_transition)(struct bnx2x *bp, 1174 struct bnx2x_func_sp_obj *o, 1175 struct bnx2x_func_state_params *params); 1176 1177 /** 1178 * Completes the pending command. 1179 */ 1180 int (*complete_cmd)(struct bnx2x *bp, 1181 struct bnx2x_func_sp_obj *o, 1182 enum bnx2x_func_cmd cmd); 1183 1184 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o, 1185 enum bnx2x_func_cmd cmd); 1186}; 1187 1188/********************** Interfaces ********************************************/ 1189/* Queueable objects set */ 1190union bnx2x_qable_obj { 1191 struct bnx2x_vlan_mac_obj vlan_mac; 1192}; 1193/************** Function state update *********/ 1194void bnx2x_init_func_obj(struct bnx2x *bp, 1195 struct bnx2x_func_sp_obj *obj, 1196 void *rdata, dma_addr_t rdata_mapping, 1197 struct bnx2x_func_sp_drv_ops *drv_iface); 1198 1199int bnx2x_func_state_change(struct bnx2x *bp, 1200 struct bnx2x_func_state_params *params); 1201 1202enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, 1203 struct bnx2x_func_sp_obj *o); 1204/******************* Queue State **************/ 1205void bnx2x_init_queue_obj(struct bnx2x *bp, 1206 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids, 1207 u8 cid_cnt, u8 func_id, void *rdata, 1208 dma_addr_t rdata_mapping, unsigned long type); 1209 1210int bnx2x_queue_state_change(struct bnx2x *bp, 1211 struct bnx2x_queue_state_params *params); 1212 1213/********************* VLAN-MAC ****************/ 1214void bnx2x_init_mac_obj(struct bnx2x *bp, 1215 struct bnx2x_vlan_mac_obj *mac_obj, 1216 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1217 dma_addr_t rdata_mapping, int state, 1218 unsigned long *pstate, bnx2x_obj_type type, 1219 struct bnx2x_credit_pool_obj *macs_pool); 1220 1221void bnx2x_init_vlan_obj(struct bnx2x *bp, 1222 struct bnx2x_vlan_mac_obj *vlan_obj, 1223 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1224 dma_addr_t rdata_mapping, int state, 1225 unsigned long *pstate, bnx2x_obj_type type, 1226 struct bnx2x_credit_pool_obj *vlans_pool); 1227 1228void bnx2x_init_vlan_mac_obj(struct bnx2x *bp, 1229 struct bnx2x_vlan_mac_obj *vlan_mac_obj, 1230 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1231 dma_addr_t rdata_mapping, int state, 1232 unsigned long *pstate, bnx2x_obj_type type, 1233 struct bnx2x_credit_pool_obj *macs_pool, 1234 struct bnx2x_credit_pool_obj *vlans_pool); 1235 1236int bnx2x_config_vlan_mac(struct bnx2x *bp, 1237 struct bnx2x_vlan_mac_ramrod_params *p); 1238 1239int bnx2x_vlan_mac_move(struct bnx2x *bp, 1240 struct bnx2x_vlan_mac_ramrod_params *p, 1241 struct bnx2x_vlan_mac_obj *dest_o); 1242 1243/********************* RX MODE ****************/ 1244 1245void bnx2x_init_rx_mode_obj(struct bnx2x *bp, 1246 struct bnx2x_rx_mode_obj *o); 1247 1248/** 1249 * Send and RX_MODE ramrod according to the provided parameters. 1250 * 1251 * @param bp 1252 * @param p Command parameters 1253 * 1254 * @return 0 - if operation was successfull and there is no pending completions, 1255 * positive number - if there are pending completions, 1256 * negative - if there were errors 1257 */ 1258int bnx2x_config_rx_mode(struct bnx2x *bp, 1259 struct bnx2x_rx_mode_ramrod_params *p); 1260 1261/****************** MULTICASTS ****************/ 1262 1263void bnx2x_init_mcast_obj(struct bnx2x *bp, 1264 struct bnx2x_mcast_obj *mcast_obj, 1265 u8 mcast_cl_id, u32 mcast_cid, u8 func_id, 1266 u8 engine_id, void *rdata, dma_addr_t rdata_mapping, 1267 int state, unsigned long *pstate, 1268 bnx2x_obj_type type); 1269 1270/** 1271 * Configure multicast MACs list. May configure a new list 1272 * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up 1273 * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current 1274 * configuration, continue to execute the pending commands 1275 * (BNX2X_MCAST_CMD_CONT). 1276 * 1277 * If previous command is still pending or if number of MACs to 1278 * configure is more that maximum number of MACs in one command, 1279 * the current command will be enqueued to the tail of the 1280 * pending commands list. 1281 * 1282 * @param bp 1283 * @param p 1284 * @param command to execute: BNX2X_MCAST_CMD_X 1285 * 1286 * @return 0 is operation was sucessfull and there are no pending completions, 1287 * negative if there were errors, positive if there are pending 1288 * completions. 1289 */ 1290int bnx2x_config_mcast(struct bnx2x *bp, 1291 struct bnx2x_mcast_ramrod_params *p, int cmd); 1292 1293/****************** CREDIT POOL ****************/ 1294void bnx2x_init_mac_credit_pool(struct bnx2x *bp, 1295 struct bnx2x_credit_pool_obj *p, u8 func_id, 1296 u8 func_num); 1297void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, 1298 struct bnx2x_credit_pool_obj *p, u8 func_id, 1299 u8 func_num); 1300 1301 1302/****************** RSS CONFIGURATION ****************/ 1303void bnx2x_init_rss_config_obj(struct bnx2x *bp, 1304 struct bnx2x_rss_config_obj *rss_obj, 1305 u8 cl_id, u32 cid, u8 func_id, u8 engine_id, 1306 void *rdata, dma_addr_t rdata_mapping, 1307 int state, unsigned long *pstate, 1308 bnx2x_obj_type type); 1309 1310/** 1311 * Updates RSS configuration according to provided parameters. 1312 * 1313 * @param bp 1314 * @param p 1315 * 1316 * @return 0 in case of success 1317 */ 1318int bnx2x_config_rss(struct bnx2x *bp, 1319 struct bnx2x_config_rss_params *p); 1320 1321/** 1322 * Return the current ind_table configuration. 1323 * 1324 * @param bp 1325 * @param ind_table buffer to fill with the current indirection 1326 * table content. Should be at least 1327 * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1328 */ 1329void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, 1330 u8 *ind_table); 1331 1332#endif /* BNX2X_SP_VERBS */ 1333