16849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/* 26849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * Linux network driver for Brocade Converged Network Adapter. 36849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * 46849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * This program is free software; you can redistribute it and/or modify it 56849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * under the terms of the GNU General Public License (GPL) Version 2 as 66849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * published by the Free Software Foundation 76849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * 86849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * This program is distributed in the hope that it will be useful, but 96849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * WITHOUT ANY WARRANTY; without even the implied warranty of 106849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 116849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * General Public License for more details. 126849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody */ 136849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/* 146849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * Copyright (c) 2005-2011 Brocade Communications Systems, Inc. 156849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * All rights reserved 166849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * www.brocade.com 176849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody */ 186849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 196849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/** 206849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * File for interrupt macros and functions 216849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody */ 226849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 236849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#ifndef __BNA_HW_DEFS_H__ 246849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define __BNA_HW_DEFS_H__ 256849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 266849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#include "bfi_reg.h" 276849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 286849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/** 296849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * 306849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * SW imposed limits 316849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * 326849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody */ 33761fab374e5b8efa6f7a8650ff546905578a482dRasesh Mody#define BFI_ENET_DEF_TXQ 1 34761fab374e5b8efa6f7a8650ff546905578a482dRasesh Mody#define BFI_ENET_DEF_RXP 1 35761fab374e5b8efa6f7a8650ff546905578a482dRasesh Mody#define BFI_ENET_DEF_UCAM 1 36761fab374e5b8efa6f7a8650ff546905578a482dRasesh Mody#define BFI_ENET_DEF_RITSZ 1 376849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 386849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_ENET_MAX_MCAM 256 396849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 406849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_INVALID_RID -1 416849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 426849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_IBIDX_SIZE 4 436849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 446849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_VLAN_WORD_SHIFT 5 /* 32 bits */ 456849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_VLAN_WORD_MASK 0x1F 466849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_VLAN_BLOCK_SHIFT 9 /* 512 bits */ 476849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_VLAN_BMASK_ALL 0xFF 486849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 496849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_COALESCING_TIMER_UNIT 5 /* 5us */ 506849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_MAX_COALESCING_TIMEO 0xFF /* in 5us units */ 516849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_MAX_INTERPKT_COUNT 0xFF 526849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_MAX_INTERPKT_TIMEO 0xF /* in 0.5us units */ 536849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_TX_COALESCING_TIMEO 20 /* 20 * 5 = 100us */ 546849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_TX_INTERPKT_COUNT 32 556849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_RX_COALESCING_TIMEO 12 /* 12 * 5 = 60us */ 566849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_RX_INTERPKT_COUNT 6 /* Pkt Cnt = 6 */ 576849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_RX_INTERPKT_TIMEO 3 /* 3 * 0.5 = 1.5us */ 586849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 596849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_TXQ_WI_SIZE 64 /* bytes */ 606849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_RXQ_WI_SIZE 8 /* bytes */ 616849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_CQ_WI_SIZE 16 /* bytes */ 626849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_TX_MAX_WRR_QUOTA 0xFFF 636849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 646849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_TX_MAX_VECTORS_PER_WI 4 656849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_TX_MAX_VECTORS_PER_PKT 0xFF 666849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_TX_MAX_DATA_PER_VECTOR 0xFFFF 676849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_TX_MAX_DATA_PER_PKT 0xFFFFFF 686849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 696849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/* Small Q buffer size */ 706849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_SMALL_RXBUF_SIZE 128 716849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 726849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_TX_MAX_PRIO 8 736849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BFI_TX_PRIO_MAP_ALL 0xFF 746849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 756849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/* 766849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * 776849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * Register definitions and macros 786849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * 796849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody */ 806849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 816849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_PCI_REG_CT_ADDRSZ (0x40000) 826849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 836849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define ct_reg_addr_init(_bna, _pcidev) \ 846849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody{ \ 856849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody struct bna_reg_offset reg_offset[] = \ 866849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody {{HOSTFN0_INT_STATUS, HOSTFN0_INT_MSK}, \ 876849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody {HOSTFN1_INT_STATUS, HOSTFN1_INT_MSK}, \ 886849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody {HOSTFN2_INT_STATUS, HOSTFN2_INT_MSK}, \ 896849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody {HOSTFN3_INT_STATUS, HOSTFN3_INT_MSK} }; \ 906849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody \ 916849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva + \ 926849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody reg_offset[(_pcidev)->pci_func].fn_int_status;\ 936849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva + \ 946849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody reg_offset[(_pcidev)->pci_func].fn_int_mask;\ 956849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody} 966849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 976849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define ct_bit_defn_init(_bna, _pcidev) \ 986849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody{ \ 996849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0 | \ 1006849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody __HFN_INT_MBOX_LPU1); \ 1016849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0 | \ 1026849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody __HFN_INT_MBOX_LPU1); \ 1036849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK); \ 1046849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK); \ 1056849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_bna)->bits.halt_status_bits = __HFN_INT_LL_HALT; \ 1063caa1e9556087ecee27bfddc7beb5758213a4507Rasesh Mody (_bna)->bits.halt_mask_bits = __HFN_INT_LL_HALT; \ 1076849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody} 1086849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 1096849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define ct2_reg_addr_init(_bna, _pcidev) \ 1106849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody{ \ 1116849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva + \ 1126849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody CT2_HOSTFN_INT_STATUS; \ 1136849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva + \ 1146849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody CT2_HOSTFN_INTR_MASK; \ 1156849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody} 1166849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 1176849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define ct2_bit_defn_init(_bna, _pcidev) \ 1186849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody{ \ 1196849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0_CT2 | \ 1206849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody __HFN_INT_MBOX_LPU1_CT2); \ 1216849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0_CT2 | \ 1226849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody __HFN_INT_MBOX_LPU1_CT2); \ 1236849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK_CT2); \ 1246849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK_CT2); \ 1256849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_bna)->bits.halt_status_bits = __HFN_INT_CPQ_HALT_CT2; \ 1266849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_bna)->bits.halt_mask_bits = __HFN_INT_CPQ_HALT_CT2; \ 1276849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody} 1286849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 1296849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define bna_reg_addr_init(_bna, _pcidev) \ 1306849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody{ \ 1316849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody switch ((_pcidev)->device_id) { \ 1326849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody case PCI_DEVICE_ID_BROCADE_CT: \ 1336849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody ct_reg_addr_init((_bna), (_pcidev)); \ 1346849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody ct_bit_defn_init((_bna), (_pcidev)); \ 1356849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody break; \ 136586b2816e3eaf187341f75c4f4e27404f943cb29Rasesh Mody case BFA_PCI_DEVICE_ID_CT2: \ 137586b2816e3eaf187341f75c4f4e27404f943cb29Rasesh Mody ct2_reg_addr_init((_bna), (_pcidev)); \ 138586b2816e3eaf187341f75c4f4e27404f943cb29Rasesh Mody ct2_bit_defn_init((_bna), (_pcidev)); \ 139586b2816e3eaf187341f75c4f4e27404f943cb29Rasesh Mody break; \ 1406849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody } \ 1416849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody} 1426849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 1436849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define bna_port_id_get(_bna) ((_bna)->ioceth.ioc.port_id) 1446849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/** 1456849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * 1466849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * Interrupt related bits, flags and macros 1476849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * 1486849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody */ 1496849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 1506849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define IB_STATUS_BITS 0x0000ffff 1516849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 1526849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_IS_MBOX_INTR(_bna, _intr_status) \ 1536849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody ((_intr_status) & (_bna)->bits.mbox_status_bits) 1546849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 1556849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_IS_HALT_INTR(_bna, _intr_status) \ 1566849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody ((_intr_status) & (_bna)->bits.halt_status_bits) 1576849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 1586849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_IS_ERR_INTR(_bna, _intr_status) \ 1596849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody ((_intr_status) & (_bna)->bits.error_status_bits) 1606849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 1616849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_IS_MBOX_ERR_INTR(_bna, _intr_status) \ 1626849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (BNA_IS_MBOX_INTR(_bna, _intr_status) | \ 1636849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody BNA_IS_ERR_INTR(_bna, _intr_status)) 1646849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 1656849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_IS_INTX_DATA_INTR(_intr_status) \ 1666849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody ((_intr_status) & IB_STATUS_BITS) 1676849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 1686849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define bna_halt_clear(_bna) \ 1696849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Modydo { \ 1706849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 init_halt; \ 1716849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \ 1726849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody init_halt &= ~__FW_INIT_HALT_P; \ 1736849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody writel(init_halt, (_bna)->ioceth.ioc.ioc_regs.ll_halt); \ 1746849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \ 1756849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody} while (0) 1766849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 1776849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define bna_intx_disable(_bna, _cur_mask) \ 1786849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody{ \ 1796849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_cur_mask) = readl((_bna)->regs.fn_int_mask); \ 1806849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody writel(0xffffffff, (_bna)->regs.fn_int_mask); \ 1816849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody} 1826849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 1836849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define bna_intx_enable(bna, new_mask) \ 1846849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody writel((new_mask), (bna)->regs.fn_int_mask) 1856849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define bna_mbox_intr_disable(bna) \ 1866849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Modydo { \ 1876849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 mask; \ 1886849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody mask = readl((bna)->regs.fn_int_mask); \ 1896849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody writel((mask | (bna)->bits.mbox_mask_bits | \ 1906849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (bna)->bits.error_mask_bits), (bna)->regs.fn_int_mask); \ 1916849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody mask = readl((bna)->regs.fn_int_mask); \ 1926849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody} while (0) 1936849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 1946849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define bna_mbox_intr_enable(bna) \ 1956849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Modydo { \ 1966849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 mask; \ 1976849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody mask = readl((bna)->regs.fn_int_mask); \ 1986849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody writel((mask & ~((bna)->bits.mbox_mask_bits | \ 1996849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (bna)->bits.error_mask_bits)), (bna)->regs.fn_int_mask);\ 2006849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody mask = readl((bna)->regs.fn_int_mask); \ 2016849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody} while (0) 2026849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 2036849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define bna_intr_status_get(_bna, _status) \ 2046849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody{ \ 2056849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_status) = readl((_bna)->regs.fn_int_status); \ 2066849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody if (_status) { \ 2076849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody writel(((_status) & ~(_bna)->bits.mbox_status_bits), \ 2086849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_bna)->regs.fn_int_status); \ 2096849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody } \ 2106849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody} 2116849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 2126849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/* 2136849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * MAX ACK EVENTS : No. of acks that can be accumulated in driver, 2146849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * before acking to h/w. The no. of bits is 16 in the doorbell register, 2156849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * however we keep this limited to 15 bits. 2166849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * This is because around the edge of 64K boundary (16 bits), one 2176849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * single poll can make the accumulated ACK counter cross the 64K boundary, 2186849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * causing problems, when we try to ack with a value greater than 64K. 2196849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * 15 bits (32K) should be large enough to accumulate, anyways, and the max. 2206849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * acked events to h/w can be (32K + max poll weight) (currently 64). 2216849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody */ 2226849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_IB_MAX_ACK_EVENTS (1 << 15) 2236849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 2246849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/* These macros build the data portion of the TxQ/RxQ doorbell */ 2256849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_DOORBELL_Q_PRD_IDX(_pi) (0x80000000 | (_pi)) 2266849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_DOORBELL_Q_STOP (0x40000000) 2276849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 2286849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/* These macros build the data portion of the IB doorbell */ 2296849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_DOORBELL_IB_INT_ACK(_timeout, _events) \ 2306849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (0x80000000 | ((_timeout) << 16) | (_events)) 2316849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_DOORBELL_IB_INT_DISABLE (0x40000000) 2326849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 2336849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/* Set the coalescing timer for the given ib */ 2346849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define bna_ib_coalescing_timer_set(_i_dbell, _cls_timer) \ 2356849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody ((_i_dbell)->doorbell_ack = BNA_DOORBELL_IB_INT_ACK((_cls_timer), 0)); 2366849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 2376849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/* Acks 'events' # of events for a given ib while disabling interrupts */ 2386849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define bna_ib_ack_disable_irq(_i_dbell, _events) \ 2396849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (writel(BNA_DOORBELL_IB_INT_ACK(0, (_events)), \ 2406849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_i_dbell)->doorbell_addr)); 2416849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 2426849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/* Acks 'events' # of events for a given ib */ 2436849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define bna_ib_ack(_i_dbell, _events) \ 2446849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (writel(((_i_dbell)->doorbell_ack | (_events)), \ 2456849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_i_dbell)->doorbell_addr)); 2466849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 2476849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define bna_ib_start(_bna, _ib, _is_regular) \ 2486849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody{ \ 2496849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 intx_mask; \ 2506849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody struct bna_ib *ib = _ib; \ 2516849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody if ((ib->intr_type == BNA_INTR_T_INTX)) { \ 2526849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody bna_intx_disable((_bna), intx_mask); \ 2536849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody intx_mask &= ~(ib->intr_vector); \ 2546849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody bna_intx_enable((_bna), intx_mask); \ 2556849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody } \ 2566849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody bna_ib_coalescing_timer_set(&ib->door_bell, \ 2576849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody ib->coalescing_timeo); \ 2586849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody if (_is_regular) \ 2596849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody bna_ib_ack(&ib->door_bell, 0); \ 2606849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody} 2616849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 2626849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define bna_ib_stop(_bna, _ib) \ 2636849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody{ \ 2646849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 intx_mask; \ 2656849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody struct bna_ib *ib = _ib; \ 2666849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody writel(BNA_DOORBELL_IB_INT_DISABLE, \ 2676849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody ib->door_bell.doorbell_addr); \ 2686849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody if (ib->intr_type == BNA_INTR_T_INTX) { \ 2696849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody bna_intx_disable((_bna), intx_mask); \ 2706849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody intx_mask |= ib->intr_vector; \ 2716849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody bna_intx_enable((_bna), intx_mask); \ 2726849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody } \ 2736849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody} 2746849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 2756849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define bna_txq_prod_indx_doorbell(_tcb) \ 2766849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (writel(BNA_DOORBELL_Q_PRD_IDX((_tcb)->producer_index), \ 2776849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_tcb)->q_dbell)); 2786849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 2796849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define bna_rxq_prod_indx_doorbell(_rcb) \ 2806849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (writel(BNA_DOORBELL_Q_PRD_IDX((_rcb)->producer_index), \ 2816849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (_rcb)->q_dbell)); 2826849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 2836849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/** 2846849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * 2856849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * TxQ, RxQ, CQ related bits, offsets, macros 2866849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * 2876849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody */ 2886849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 2896849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/* TxQ Entry Opcodes */ 2906849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_TXQ_WI_SEND (0x402) /* Single Frame Transmission */ 2916849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_TXQ_WI_SEND_LSO (0x403) /* Multi-Frame Transmission */ 2926849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_TXQ_WI_EXTENSION (0x104) /* Extension WI */ 2936849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 2946849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/* TxQ Entry Control Flags */ 2956849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_TXQ_WI_CF_FCOE_CRC (1 << 8) 2966849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_TXQ_WI_CF_IPID_MODE (1 << 5) 2976849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_TXQ_WI_CF_INS_PRIO (1 << 4) 2986849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_TXQ_WI_CF_INS_VLAN (1 << 3) 2996849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_TXQ_WI_CF_UDP_CKSUM (1 << 2) 3006849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_TXQ_WI_CF_TCP_CKSUM (1 << 1) 3016849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_TXQ_WI_CF_IP_CKSUM (1 << 0) 3026849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 3036849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \ 3046849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody (((_hdr_size) << 10) | ((_offset) & 0x3FF)) 3056849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 3066849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/* 3076849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * Completion Q defines 3086849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody */ 3096849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/* CQ Entry Flags */ 3106849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_MAC_ERROR (1 << 0) 3116849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_FCS_ERROR (1 << 1) 3126849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_TOO_LONG (1 << 2) 3136849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_FC_CRC_OK (1 << 3) 3146849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 3156849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_RSVD1 (1 << 4) 3166849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_L4_CKSUM_OK (1 << 5) 3176849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_L3_CKSUM_OK (1 << 6) 3186849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_HDS_HEADER (1 << 7) 3196849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 3206849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_UDP (1 << 8) 3216849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_TCP (1 << 9) 3226849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_IP_OPTIONS (1 << 10) 3236849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_IPV6 (1 << 11) 3246849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 3256849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_IPV4 (1 << 12) 3266849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_VLAN (1 << 13) 3276849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_RSS (1 << 14) 3286849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_RSVD2 (1 << 15) 3296849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 3306849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_MCAST_MATCH (1 << 16) 3316849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_MCAST (1 << 17) 3326849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_BCAST (1 << 18) 3336849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_REMOTE (1 << 19) 3346849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 3356849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#define BNA_CQ_EF_LOCAL (1 << 20) 3366849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 3376849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/** 3386849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * 3396849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * Data structures 3406849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * 3416849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody */ 3426849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 3436849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Modystruct bna_reg_offset { 3446849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 fn_int_status; 3456849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 fn_int_mask; 3466849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody}; 3476849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 3486849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Modystruct bna_bit_defn { 3496849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 mbox_status_bits; 3506849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 mbox_mask_bits; 3516849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 error_status_bits; 3526849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 error_mask_bits; 3536849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 halt_status_bits; 3546849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 halt_mask_bits; 3556849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody}; 3566849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 3576849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Modystruct bna_reg { 3586849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody void __iomem *fn_int_status; 3596849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody void __iomem *fn_int_mask; 3606849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody}; 3616849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 3626849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/* TxQ Vector (a.k.a. Tx-Buffer Descriptor) */ 3636849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Modystruct bna_dma_addr { 3646849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 msb; 3656849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 lsb; 3666849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody}; 3676849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 3686849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Modystruct bna_txq_wi_vector { 3696849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u16 reserved; 3706849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u16 length; /* Only 14 LSB are valid */ 3716849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody struct bna_dma_addr host_addr; /* Tx-Buf DMA addr */ 3726849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody}; 3736849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 3746849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/** 3756849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * TxQ Entry Structure 3766849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * 3776849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody * BEWARE: Load values into this structure with correct endianess. 3786849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody */ 3796849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Modystruct bna_txq_entry { 3806849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody union { 3816849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody struct { 3826849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u8 reserved; 3836849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u8 num_vectors; /* number of vectors present */ 3846849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u16 opcode; /* Either */ 3856849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody /* BNA_TXQ_WI_SEND or */ 3866849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody /* BNA_TXQ_WI_SEND_LSO */ 3876849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u16 flags; /* OR of all the flags */ 3886849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u16 l4_hdr_size_n_offset; 3896849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u16 vlan_tag; 3906849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u16 lso_mss; /* Only 14 LSB are valid */ 3916849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 frame_length; /* Only 24 LSB are valid */ 3926849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody } wi; 3936849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 3946849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody struct { 3956849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u16 reserved; 3966849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u16 opcode; /* Must be */ 3976849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody /* BNA_TXQ_WI_EXTENSION */ 3986849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 reserved2[3]; /* Place holder for */ 3996849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody /* removed vector (12 bytes) */ 4006849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody } wi_ext; 4016849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody } hdr; 4026849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody struct bna_txq_wi_vector vector[4]; 4036849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody}; 4046849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 4056849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/* RxQ Entry Structure */ 4066849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Modystruct bna_rxq_entry { /* Rx-Buffer */ 4076849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody struct bna_dma_addr host_addr; /* Rx-Buffer DMA address */ 4086849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody}; 4096849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 4106849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody/* CQ Entry Structure */ 4116849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Modystruct bna_cq_entry { 4126849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 flags; 4136849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u16 vlan_tag; 4146849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u16 length; 4156849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u32 rss_hash; 4166849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u8 valid; 4176849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u8 reserved1; 4186849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u8 reserved2; 4196849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody u8 rxq_id; 4206849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody}; 4216849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody 4226849c6b30772bb08ed52c3ec00e8245e70e25a2bRasesh Mody#endif /* __BNA_HW_DEFS_H__ */ 423