at91_ether.h revision cf42553ab43e102bc98eca05523d2390a1eedde9
1d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* 2d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Ethernet driver for the Atmel AT91RM9200 (Thunder) 3d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * 4d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Copyright (C) SAN People (Pty) Ltd 5d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * 6d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc. 7d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * Initial version by Rick Bronson. 8d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * 9d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * This program is free software; you can redistribute it and/or 10d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * modify it under the terms of the GNU General Public License 11d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * as published by the Free Software Foundation; either version 12d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor * 2 of the License, or (at your option) any later version. 13d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor */ 14d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 15d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#ifndef AT91_ETHERNET 16d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define AT91_ETHERNET 17d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 18d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 19d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* Davicom 9161 PHY */ 20d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define MII_DM9161_ID 0x0181b880 21d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define MII_DM9161A_ID 0x0181b8a0 22d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 23d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* Davicom specific registers */ 24d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define MII_DSCR_REG 16 25d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define MII_DSCSR_REG 17 26d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define MII_DSINTR_REG 21 27d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 28d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* Intel LXT971A PHY */ 29d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define MII_LXT971A_ID 0x001378E0 30d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 31d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* Intel specific registers */ 32d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define MII_ISINTE_REG 18 33d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define MII_ISINTS_REG 19 34d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define MII_LEDCTRL_REG 20 35d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 36d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* Realtek RTL8201 PHY */ 37d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define MII_RTL8201_ID 0x00008200 38d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 39d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* Broadcom BCM5221 PHY */ 40d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define MII_BCM5221_ID 0x004061e0 41d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 42d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* Broadcom specific registers */ 43d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define MII_BCMINTR_REG 26 44d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 45d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* National Semiconductor DP83847 */ 46d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define MII_DP83847_ID 0x20005c30 47d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 48d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* Altima AC101L PHY */ 49d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define MII_AC101L_ID 0x00225520 50d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 51d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* Micrel KS8721 PHY */ 52d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define MII_KS8721_ID 0x00221610 53d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 54d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor/* ........................................................................ */ 55d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 56d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define MAX_RBUFF_SZ 0x600 /* 1518 rounded up */ 57d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define MAX_RX_DESCR 9 /* max number of receive buffers */ 58d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 59d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define EMAC_DESC_DONE 0x00000001 /* bit for if DMA is done */ 60d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */ 61d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 62d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define EMAC_BROADCAST 0x80000000 /* broadcast address */ 63d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define EMAC_MULTICAST 0x40000000 /* multicast address */ 64d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#define EMAC_UNICAST 0x20000000 /* unicast address */ 65d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 66d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstruct rbf_t 67d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 68d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned int addr; 69d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned long size; 70d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor}; 71d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 72d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstruct recv_desc_bufs 73d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 74d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor struct rbf_t descriptors[MAX_RX_DESCR]; /* must be on sizeof (rbf_t) boundary */ 75d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor char recv_buf[MAX_RX_DESCR][MAX_RBUFF_SZ]; /* must be on long boundary */ 76d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor}; 77d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 78d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victorstruct at91_private 79d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor{ 80d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor struct net_device_stats stats; 81d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor struct mii_if_info mii; /* ethtool support */ 82d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor struct at91_eth_data board_data; /* board-specific configuration */ 83427d269f17fd02d192e9ae3bd93bdc07790fa02cAndrew Victor struct clk *ether_clk; /* clock */ 84d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 85d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* PHY */ 86d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned long phy_type; /* type of PHY (PHY_ID) */ 87d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor spinlock_t lock; /* lock for MDI interface */ 88d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor short phy_media; /* media interface type */ 89d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor unsigned short phy_address; /* 5-bit MDI address of PHY (0..31) */ 90cf42553ab43e102bc98eca05523d2390a1eedde9Andrew Victor struct timer_list check_timer; /* Poll link status */ 91d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 92d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Transmit */ 93d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor struct sk_buff *skb; /* holds skb until xmit interrupt completes */ 94d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor dma_addr_t skb_physaddr; /* phys addr from pci_map_single */ 95d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor int skb_length; /* saved skb length for pci_unmap_single */ 96d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 97d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor /* Receive */ 98d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor int rxBuffIndex; /* index into receive descriptor list */ 99d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor struct recv_desc_bufs *dlist; /* descriptor list address */ 100d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor struct recv_desc_bufs *dlist_phys; /* descriptor list physical address */ 101d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor}; 102d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor 103d4b7780ea1d2e08410fcc9963a57254147ae577aAndrew Victor#endif 104