macb.c revision fb97a8466522f8f35ab886f7af8eefefa0a4905e
1/* 2 * Cadence MACB/GEM Ethernet Controller driver 3 * 4 * Copyright (C) 2004-2006 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12#include <linux/clk.h> 13#include <linux/module.h> 14#include <linux/moduleparam.h> 15#include <linux/kernel.h> 16#include <linux/types.h> 17#include <linux/slab.h> 18#include <linux/init.h> 19#include <linux/interrupt.h> 20#include <linux/netdevice.h> 21#include <linux/etherdevice.h> 22#include <linux/dma-mapping.h> 23#include <linux/platform_data/macb.h> 24#include <linux/platform_device.h> 25#include <linux/phy.h> 26#include <linux/of_device.h> 27#include <linux/of_net.h> 28 29#include "macb.h" 30 31#define RX_BUFFER_SIZE 128 32#define RX_RING_SIZE 512 33#define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE) 34 35/* Make the IP header word-aligned (the ethernet header is 14 bytes) */ 36#define RX_OFFSET 2 37 38#define TX_RING_SIZE 128 39#define DEF_TX_RING_PENDING (TX_RING_SIZE - 1) 40#define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE) 41 42#define TX_RING_GAP(bp) \ 43 (TX_RING_SIZE - (bp)->tx_pending) 44#define TX_BUFFS_AVAIL(bp) \ 45 (((bp)->tx_tail <= (bp)->tx_head) ? \ 46 (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \ 47 (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp)) 48#define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1)) 49 50#define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1)) 51 52/* minimum number of free TX descriptors before waking up TX process */ 53#define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4) 54 55#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ 56 | MACB_BIT(ISR_ROVR)) 57 58static void __macb_set_hwaddr(struct macb *bp) 59{ 60 u32 bottom; 61 u16 top; 62 63 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr)); 64 macb_or_gem_writel(bp, SA1B, bottom); 65 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); 66 macb_or_gem_writel(bp, SA1T, top); 67} 68 69static void __init macb_get_hwaddr(struct macb *bp) 70{ 71 u32 bottom; 72 u16 top; 73 u8 addr[6]; 74 75 bottom = macb_or_gem_readl(bp, SA1B); 76 top = macb_or_gem_readl(bp, SA1T); 77 78 addr[0] = bottom & 0xff; 79 addr[1] = (bottom >> 8) & 0xff; 80 addr[2] = (bottom >> 16) & 0xff; 81 addr[3] = (bottom >> 24) & 0xff; 82 addr[4] = top & 0xff; 83 addr[5] = (top >> 8) & 0xff; 84 85 if (is_valid_ether_addr(addr)) { 86 memcpy(bp->dev->dev_addr, addr, sizeof(addr)); 87 } else { 88 netdev_info(bp->dev, "invalid hw address, using random\n"); 89 random_ether_addr(bp->dev->dev_addr); 90 } 91} 92 93static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 94{ 95 struct macb *bp = bus->priv; 96 int value; 97 98 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) 99 | MACB_BF(RW, MACB_MAN_READ) 100 | MACB_BF(PHYA, mii_id) 101 | MACB_BF(REGA, regnum) 102 | MACB_BF(CODE, MACB_MAN_CODE))); 103 104 /* wait for end of transfer */ 105 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) 106 cpu_relax(); 107 108 value = MACB_BFEXT(DATA, macb_readl(bp, MAN)); 109 110 return value; 111} 112 113static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 114 u16 value) 115{ 116 struct macb *bp = bus->priv; 117 118 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) 119 | MACB_BF(RW, MACB_MAN_WRITE) 120 | MACB_BF(PHYA, mii_id) 121 | MACB_BF(REGA, regnum) 122 | MACB_BF(CODE, MACB_MAN_CODE) 123 | MACB_BF(DATA, value))); 124 125 /* wait for end of transfer */ 126 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) 127 cpu_relax(); 128 129 return 0; 130} 131 132static int macb_mdio_reset(struct mii_bus *bus) 133{ 134 return 0; 135} 136 137static void macb_handle_link_change(struct net_device *dev) 138{ 139 struct macb *bp = netdev_priv(dev); 140 struct phy_device *phydev = bp->phy_dev; 141 unsigned long flags; 142 143 int status_change = 0; 144 145 spin_lock_irqsave(&bp->lock, flags); 146 147 if (phydev->link) { 148 if ((bp->speed != phydev->speed) || 149 (bp->duplex != phydev->duplex)) { 150 u32 reg; 151 152 reg = macb_readl(bp, NCFGR); 153 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); 154 155 if (phydev->duplex) 156 reg |= MACB_BIT(FD); 157 if (phydev->speed == SPEED_100) 158 reg |= MACB_BIT(SPD); 159 160 macb_writel(bp, NCFGR, reg); 161 162 bp->speed = phydev->speed; 163 bp->duplex = phydev->duplex; 164 status_change = 1; 165 } 166 } 167 168 if (phydev->link != bp->link) { 169 if (!phydev->link) { 170 bp->speed = 0; 171 bp->duplex = -1; 172 } 173 bp->link = phydev->link; 174 175 status_change = 1; 176 } 177 178 spin_unlock_irqrestore(&bp->lock, flags); 179 180 if (status_change) { 181 if (phydev->link) 182 netdev_info(dev, "link up (%d/%s)\n", 183 phydev->speed, 184 phydev->duplex == DUPLEX_FULL ? 185 "Full" : "Half"); 186 else 187 netdev_info(dev, "link down\n"); 188 } 189} 190 191/* based on au1000_eth. c*/ 192static int macb_mii_probe(struct net_device *dev) 193{ 194 struct macb *bp = netdev_priv(dev); 195 struct phy_device *phydev; 196 int ret; 197 198 phydev = phy_find_first(bp->mii_bus); 199 if (!phydev) { 200 netdev_err(dev, "no PHY found\n"); 201 return -1; 202 } 203 204 /* TODO : add pin_irq */ 205 206 /* attach the mac to the phy */ 207 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0, 208 bp->phy_interface); 209 if (ret) { 210 netdev_err(dev, "Could not attach to PHY\n"); 211 return ret; 212 } 213 214 /* mask with MAC supported features */ 215 phydev->supported &= PHY_BASIC_FEATURES; 216 217 phydev->advertising = phydev->supported; 218 219 bp->link = 0; 220 bp->speed = 0; 221 bp->duplex = -1; 222 bp->phy_dev = phydev; 223 224 return 0; 225} 226 227static int macb_mii_init(struct macb *bp) 228{ 229 struct macb_platform_data *pdata; 230 int err = -ENXIO, i; 231 232 /* Enable management port */ 233 macb_writel(bp, NCR, MACB_BIT(MPE)); 234 235 bp->mii_bus = mdiobus_alloc(); 236 if (bp->mii_bus == NULL) { 237 err = -ENOMEM; 238 goto err_out; 239 } 240 241 bp->mii_bus->name = "MACB_mii_bus"; 242 bp->mii_bus->read = &macb_mdio_read; 243 bp->mii_bus->write = &macb_mdio_write; 244 bp->mii_bus->reset = &macb_mdio_reset; 245 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", bp->pdev->id); 246 bp->mii_bus->priv = bp; 247 bp->mii_bus->parent = &bp->dev->dev; 248 pdata = bp->pdev->dev.platform_data; 249 250 if (pdata) 251 bp->mii_bus->phy_mask = pdata->phy_mask; 252 253 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); 254 if (!bp->mii_bus->irq) { 255 err = -ENOMEM; 256 goto err_out_free_mdiobus; 257 } 258 259 for (i = 0; i < PHY_MAX_ADDR; i++) 260 bp->mii_bus->irq[i] = PHY_POLL; 261 262 dev_set_drvdata(&bp->dev->dev, bp->mii_bus); 263 264 if (mdiobus_register(bp->mii_bus)) 265 goto err_out_free_mdio_irq; 266 267 if (macb_mii_probe(bp->dev) != 0) { 268 goto err_out_unregister_bus; 269 } 270 271 return 0; 272 273err_out_unregister_bus: 274 mdiobus_unregister(bp->mii_bus); 275err_out_free_mdio_irq: 276 kfree(bp->mii_bus->irq); 277err_out_free_mdiobus: 278 mdiobus_free(bp->mii_bus); 279err_out: 280 return err; 281} 282 283static void macb_update_stats(struct macb *bp) 284{ 285 u32 __iomem *reg = bp->regs + MACB_PFR; 286 u32 *p = &bp->hw_stats.macb.rx_pause_frames; 287 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1; 288 289 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); 290 291 for(; p < end; p++, reg++) 292 *p += __raw_readl(reg); 293} 294 295static void macb_tx(struct macb *bp) 296{ 297 unsigned int tail; 298 unsigned int head; 299 u32 status; 300 301 status = macb_readl(bp, TSR); 302 macb_writel(bp, TSR, status); 303 304 netdev_dbg(bp->dev, "macb_tx status = %02lx\n", (unsigned long)status); 305 306 if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) { 307 int i; 308 netdev_err(bp->dev, "TX %s, resetting buffers\n", 309 status & MACB_BIT(UND) ? 310 "underrun" : "retry limit exceeded"); 311 312 /* Transfer ongoing, disable transmitter, to avoid confusion */ 313 if (status & MACB_BIT(TGO)) 314 macb_writel(bp, NCR, macb_readl(bp, NCR) & ~MACB_BIT(TE)); 315 316 head = bp->tx_head; 317 318 /*Mark all the buffer as used to avoid sending a lost buffer*/ 319 for (i = 0; i < TX_RING_SIZE; i++) 320 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); 321 322 /* Add wrap bit */ 323 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); 324 325 /* free transmit buffer in upper layer*/ 326 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) { 327 struct ring_info *rp = &bp->tx_skb[tail]; 328 struct sk_buff *skb = rp->skb; 329 330 BUG_ON(skb == NULL); 331 332 rmb(); 333 334 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len, 335 DMA_TO_DEVICE); 336 rp->skb = NULL; 337 dev_kfree_skb_irq(skb); 338 } 339 340 bp->tx_head = bp->tx_tail = 0; 341 342 /* Enable the transmitter again */ 343 if (status & MACB_BIT(TGO)) 344 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE)); 345 } 346 347 if (!(status & MACB_BIT(COMP))) 348 /* 349 * This may happen when a buffer becomes complete 350 * between reading the ISR and scanning the 351 * descriptors. Nothing to worry about. 352 */ 353 return; 354 355 head = bp->tx_head; 356 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) { 357 struct ring_info *rp = &bp->tx_skb[tail]; 358 struct sk_buff *skb = rp->skb; 359 u32 bufstat; 360 361 BUG_ON(skb == NULL); 362 363 rmb(); 364 bufstat = bp->tx_ring[tail].ctrl; 365 366 if (!(bufstat & MACB_BIT(TX_USED))) 367 break; 368 369 netdev_dbg(bp->dev, "skb %u (data %p) TX complete\n", 370 tail, skb->data); 371 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len, 372 DMA_TO_DEVICE); 373 bp->stats.tx_packets++; 374 bp->stats.tx_bytes += skb->len; 375 rp->skb = NULL; 376 dev_kfree_skb_irq(skb); 377 } 378 379 bp->tx_tail = tail; 380 if (netif_queue_stopped(bp->dev) && 381 TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH) 382 netif_wake_queue(bp->dev); 383} 384 385static int macb_rx_frame(struct macb *bp, unsigned int first_frag, 386 unsigned int last_frag) 387{ 388 unsigned int len; 389 unsigned int frag; 390 unsigned int offset = 0; 391 struct sk_buff *skb; 392 393 len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl); 394 395 netdev_dbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n", 396 first_frag, last_frag, len); 397 398 skb = dev_alloc_skb(len + RX_OFFSET); 399 if (!skb) { 400 bp->stats.rx_dropped++; 401 for (frag = first_frag; ; frag = NEXT_RX(frag)) { 402 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); 403 if (frag == last_frag) 404 break; 405 } 406 wmb(); 407 return 1; 408 } 409 410 skb_reserve(skb, RX_OFFSET); 411 skb_checksum_none_assert(skb); 412 skb_put(skb, len); 413 414 for (frag = first_frag; ; frag = NEXT_RX(frag)) { 415 unsigned int frag_len = RX_BUFFER_SIZE; 416 417 if (offset + frag_len > len) { 418 BUG_ON(frag != last_frag); 419 frag_len = len - offset; 420 } 421 skb_copy_to_linear_data_offset(skb, offset, 422 (bp->rx_buffers + 423 (RX_BUFFER_SIZE * frag)), 424 frag_len); 425 offset += RX_BUFFER_SIZE; 426 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); 427 wmb(); 428 429 if (frag == last_frag) 430 break; 431 } 432 433 skb->protocol = eth_type_trans(skb, bp->dev); 434 435 bp->stats.rx_packets++; 436 bp->stats.rx_bytes += len; 437 netdev_dbg(bp->dev, "received skb of length %u, csum: %08x\n", 438 skb->len, skb->csum); 439 netif_receive_skb(skb); 440 441 return 0; 442} 443 444/* Mark DMA descriptors from begin up to and not including end as unused */ 445static void discard_partial_frame(struct macb *bp, unsigned int begin, 446 unsigned int end) 447{ 448 unsigned int frag; 449 450 for (frag = begin; frag != end; frag = NEXT_RX(frag)) 451 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); 452 wmb(); 453 454 /* 455 * When this happens, the hardware stats registers for 456 * whatever caused this is updated, so we don't have to record 457 * anything. 458 */ 459} 460 461static int macb_rx(struct macb *bp, int budget) 462{ 463 int received = 0; 464 unsigned int tail = bp->rx_tail; 465 int first_frag = -1; 466 467 for (; budget > 0; tail = NEXT_RX(tail)) { 468 u32 addr, ctrl; 469 470 rmb(); 471 addr = bp->rx_ring[tail].addr; 472 ctrl = bp->rx_ring[tail].ctrl; 473 474 if (!(addr & MACB_BIT(RX_USED))) 475 break; 476 477 if (ctrl & MACB_BIT(RX_SOF)) { 478 if (first_frag != -1) 479 discard_partial_frame(bp, first_frag, tail); 480 first_frag = tail; 481 } 482 483 if (ctrl & MACB_BIT(RX_EOF)) { 484 int dropped; 485 BUG_ON(first_frag == -1); 486 487 dropped = macb_rx_frame(bp, first_frag, tail); 488 first_frag = -1; 489 if (!dropped) { 490 received++; 491 budget--; 492 } 493 } 494 } 495 496 if (first_frag != -1) 497 bp->rx_tail = first_frag; 498 else 499 bp->rx_tail = tail; 500 501 return received; 502} 503 504static int macb_poll(struct napi_struct *napi, int budget) 505{ 506 struct macb *bp = container_of(napi, struct macb, napi); 507 int work_done; 508 u32 status; 509 510 status = macb_readl(bp, RSR); 511 macb_writel(bp, RSR, status); 512 513 work_done = 0; 514 515 netdev_dbg(bp->dev, "poll: status = %08lx, budget = %d\n", 516 (unsigned long)status, budget); 517 518 work_done = macb_rx(bp, budget); 519 if (work_done < budget) { 520 napi_complete(napi); 521 522 /* 523 * We've done what we can to clean the buffers. Make sure we 524 * get notified when new packets arrive. 525 */ 526 macb_writel(bp, IER, MACB_RX_INT_FLAGS); 527 } 528 529 /* TODO: Handle errors */ 530 531 return work_done; 532} 533 534static irqreturn_t macb_interrupt(int irq, void *dev_id) 535{ 536 struct net_device *dev = dev_id; 537 struct macb *bp = netdev_priv(dev); 538 u32 status; 539 540 status = macb_readl(bp, ISR); 541 542 if (unlikely(!status)) 543 return IRQ_NONE; 544 545 spin_lock(&bp->lock); 546 547 while (status) { 548 /* close possible race with dev_close */ 549 if (unlikely(!netif_running(dev))) { 550 macb_writel(bp, IDR, ~0UL); 551 break; 552 } 553 554 if (status & MACB_RX_INT_FLAGS) { 555 /* 556 * There's no point taking any more interrupts 557 * until we have processed the buffers. The 558 * scheduling call may fail if the poll routine 559 * is already scheduled, so disable interrupts 560 * now. 561 */ 562 macb_writel(bp, IDR, MACB_RX_INT_FLAGS); 563 564 if (napi_schedule_prep(&bp->napi)) { 565 netdev_dbg(bp->dev, "scheduling RX softirq\n"); 566 __napi_schedule(&bp->napi); 567 } 568 } 569 570 if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | 571 MACB_BIT(ISR_RLE))) 572 macb_tx(bp); 573 574 /* 575 * Link change detection isn't possible with RMII, so we'll 576 * add that if/when we get our hands on a full-blown MII PHY. 577 */ 578 579 if (status & MACB_BIT(ISR_ROVR)) { 580 /* We missed at least one packet */ 581 if (macb_is_gem(bp)) 582 bp->hw_stats.gem.rx_overruns++; 583 else 584 bp->hw_stats.macb.rx_overruns++; 585 } 586 587 if (status & MACB_BIT(HRESP)) { 588 /* 589 * TODO: Reset the hardware, and maybe move the 590 * netdev_err to a lower-priority context as well 591 * (work queue?) 592 */ 593 netdev_err(dev, "DMA bus error: HRESP not OK\n"); 594 } 595 596 status = macb_readl(bp, ISR); 597 } 598 599 spin_unlock(&bp->lock); 600 601 return IRQ_HANDLED; 602} 603 604#ifdef CONFIG_NET_POLL_CONTROLLER 605/* 606 * Polling receive - used by netconsole and other diagnostic tools 607 * to allow network i/o with interrupts disabled. 608 */ 609static void macb_poll_controller(struct net_device *dev) 610{ 611 unsigned long flags; 612 613 local_irq_save(flags); 614 macb_interrupt(dev->irq, dev); 615 local_irq_restore(flags); 616} 617#endif 618 619static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) 620{ 621 struct macb *bp = netdev_priv(dev); 622 dma_addr_t mapping; 623 unsigned int len, entry; 624 u32 ctrl; 625 unsigned long flags; 626 627#ifdef DEBUG 628 netdev_dbg(bp->dev, 629 "start_xmit: len %u head %p data %p tail %p end %p\n", 630 skb->len, skb->head, skb->data, 631 skb_tail_pointer(skb), skb_end_pointer(skb)); 632 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1, 633 skb->data, 16, true); 634#endif 635 636 len = skb->len; 637 spin_lock_irqsave(&bp->lock, flags); 638 639 /* This is a hard error, log it. */ 640 if (TX_BUFFS_AVAIL(bp) < 1) { 641 netif_stop_queue(dev); 642 spin_unlock_irqrestore(&bp->lock, flags); 643 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n"); 644 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n", 645 bp->tx_head, bp->tx_tail); 646 return NETDEV_TX_BUSY; 647 } 648 649 entry = bp->tx_head; 650 netdev_dbg(bp->dev, "Allocated ring entry %u\n", entry); 651 mapping = dma_map_single(&bp->pdev->dev, skb->data, 652 len, DMA_TO_DEVICE); 653 bp->tx_skb[entry].skb = skb; 654 bp->tx_skb[entry].mapping = mapping; 655 netdev_dbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n", 656 skb->data, (unsigned long)mapping); 657 658 ctrl = MACB_BF(TX_FRMLEN, len); 659 ctrl |= MACB_BIT(TX_LAST); 660 if (entry == (TX_RING_SIZE - 1)) 661 ctrl |= MACB_BIT(TX_WRAP); 662 663 bp->tx_ring[entry].addr = mapping; 664 bp->tx_ring[entry].ctrl = ctrl; 665 wmb(); 666 667 entry = NEXT_TX(entry); 668 bp->tx_head = entry; 669 670 skb_tx_timestamp(skb); 671 672 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); 673 674 if (TX_BUFFS_AVAIL(bp) < 1) 675 netif_stop_queue(dev); 676 677 spin_unlock_irqrestore(&bp->lock, flags); 678 679 return NETDEV_TX_OK; 680} 681 682static void macb_free_consistent(struct macb *bp) 683{ 684 if (bp->tx_skb) { 685 kfree(bp->tx_skb); 686 bp->tx_skb = NULL; 687 } 688 if (bp->rx_ring) { 689 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES, 690 bp->rx_ring, bp->rx_ring_dma); 691 bp->rx_ring = NULL; 692 } 693 if (bp->tx_ring) { 694 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES, 695 bp->tx_ring, bp->tx_ring_dma); 696 bp->tx_ring = NULL; 697 } 698 if (bp->rx_buffers) { 699 dma_free_coherent(&bp->pdev->dev, 700 RX_RING_SIZE * RX_BUFFER_SIZE, 701 bp->rx_buffers, bp->rx_buffers_dma); 702 bp->rx_buffers = NULL; 703 } 704} 705 706static int macb_alloc_consistent(struct macb *bp) 707{ 708 int size; 709 710 size = TX_RING_SIZE * sizeof(struct ring_info); 711 bp->tx_skb = kmalloc(size, GFP_KERNEL); 712 if (!bp->tx_skb) 713 goto out_err; 714 715 size = RX_RING_BYTES; 716 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size, 717 &bp->rx_ring_dma, GFP_KERNEL); 718 if (!bp->rx_ring) 719 goto out_err; 720 netdev_dbg(bp->dev, 721 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n", 722 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring); 723 724 size = TX_RING_BYTES; 725 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size, 726 &bp->tx_ring_dma, GFP_KERNEL); 727 if (!bp->tx_ring) 728 goto out_err; 729 netdev_dbg(bp->dev, 730 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n", 731 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring); 732 733 size = RX_RING_SIZE * RX_BUFFER_SIZE; 734 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size, 735 &bp->rx_buffers_dma, GFP_KERNEL); 736 if (!bp->rx_buffers) 737 goto out_err; 738 netdev_dbg(bp->dev, 739 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n", 740 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers); 741 742 return 0; 743 744out_err: 745 macb_free_consistent(bp); 746 return -ENOMEM; 747} 748 749static void macb_init_rings(struct macb *bp) 750{ 751 int i; 752 dma_addr_t addr; 753 754 addr = bp->rx_buffers_dma; 755 for (i = 0; i < RX_RING_SIZE; i++) { 756 bp->rx_ring[i].addr = addr; 757 bp->rx_ring[i].ctrl = 0; 758 addr += RX_BUFFER_SIZE; 759 } 760 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP); 761 762 for (i = 0; i < TX_RING_SIZE; i++) { 763 bp->tx_ring[i].addr = 0; 764 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); 765 } 766 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); 767 768 bp->rx_tail = bp->tx_head = bp->tx_tail = 0; 769} 770 771static void macb_reset_hw(struct macb *bp) 772{ 773 /* Make sure we have the write buffer for ourselves */ 774 wmb(); 775 776 /* 777 * Disable RX and TX (XXX: Should we halt the transmission 778 * more gracefully?) 779 */ 780 macb_writel(bp, NCR, 0); 781 782 /* Clear the stats registers (XXX: Update stats first?) */ 783 macb_writel(bp, NCR, MACB_BIT(CLRSTAT)); 784 785 /* Clear all status flags */ 786 macb_writel(bp, TSR, ~0UL); 787 macb_writel(bp, RSR, ~0UL); 788 789 /* Disable all interrupts */ 790 macb_writel(bp, IDR, ~0UL); 791 macb_readl(bp, ISR); 792} 793 794static u32 gem_mdc_clk_div(struct macb *bp) 795{ 796 u32 config; 797 unsigned long pclk_hz = clk_get_rate(bp->pclk); 798 799 if (pclk_hz <= 20000000) 800 config = GEM_BF(CLK, GEM_CLK_DIV8); 801 else if (pclk_hz <= 40000000) 802 config = GEM_BF(CLK, GEM_CLK_DIV16); 803 else if (pclk_hz <= 80000000) 804 config = GEM_BF(CLK, GEM_CLK_DIV32); 805 else if (pclk_hz <= 120000000) 806 config = GEM_BF(CLK, GEM_CLK_DIV48); 807 else if (pclk_hz <= 160000000) 808 config = GEM_BF(CLK, GEM_CLK_DIV64); 809 else 810 config = GEM_BF(CLK, GEM_CLK_DIV96); 811 812 return config; 813} 814 815static u32 macb_mdc_clk_div(struct macb *bp) 816{ 817 u32 config; 818 unsigned long pclk_hz; 819 820 if (macb_is_gem(bp)) 821 return gem_mdc_clk_div(bp); 822 823 pclk_hz = clk_get_rate(bp->pclk); 824 if (pclk_hz <= 20000000) 825 config = MACB_BF(CLK, MACB_CLK_DIV8); 826 else if (pclk_hz <= 40000000) 827 config = MACB_BF(CLK, MACB_CLK_DIV16); 828 else if (pclk_hz <= 80000000) 829 config = MACB_BF(CLK, MACB_CLK_DIV32); 830 else 831 config = MACB_BF(CLK, MACB_CLK_DIV64); 832 833 return config; 834} 835 836/* 837 * Get the DMA bus width field of the network configuration register that we 838 * should program. We find the width from decoding the design configuration 839 * register to find the maximum supported data bus width. 840 */ 841static u32 macb_dbw(struct macb *bp) 842{ 843 if (!macb_is_gem(bp)) 844 return 0; 845 846 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) { 847 case 4: 848 return GEM_BF(DBW, GEM_DBW128); 849 case 2: 850 return GEM_BF(DBW, GEM_DBW64); 851 case 1: 852 default: 853 return GEM_BF(DBW, GEM_DBW32); 854 } 855} 856 857/* 858 * Configure the receive DMA engine to use the correct receive buffer size. 859 * This is a configurable parameter for GEM. 860 */ 861static void macb_configure_dma(struct macb *bp) 862{ 863 u32 dmacfg; 864 865 if (macb_is_gem(bp)) { 866 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L); 867 dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64); 868 gem_writel(bp, DMACFG, dmacfg); 869 } 870} 871 872static void macb_init_hw(struct macb *bp) 873{ 874 u32 config; 875 876 macb_reset_hw(bp); 877 __macb_set_hwaddr(bp); 878 879 config = macb_mdc_clk_div(bp); 880 config |= MACB_BIT(PAE); /* PAuse Enable */ 881 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */ 882 config |= MACB_BIT(BIG); /* Receive oversized frames */ 883 if (bp->dev->flags & IFF_PROMISC) 884 config |= MACB_BIT(CAF); /* Copy All Frames */ 885 if (!(bp->dev->flags & IFF_BROADCAST)) 886 config |= MACB_BIT(NBC); /* No BroadCast */ 887 config |= macb_dbw(bp); 888 macb_writel(bp, NCFGR, config); 889 890 macb_configure_dma(bp); 891 892 /* Initialize TX and RX buffers */ 893 macb_writel(bp, RBQP, bp->rx_ring_dma); 894 macb_writel(bp, TBQP, bp->tx_ring_dma); 895 896 /* Enable TX and RX */ 897 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE)); 898 899 /* Enable interrupts */ 900 macb_writel(bp, IER, (MACB_BIT(RCOMP) 901 | MACB_BIT(RXUBR) 902 | MACB_BIT(ISR_TUND) 903 | MACB_BIT(ISR_RLE) 904 | MACB_BIT(TXERR) 905 | MACB_BIT(TCOMP) 906 | MACB_BIT(ISR_ROVR) 907 | MACB_BIT(HRESP))); 908 909} 910 911/* 912 * The hash address register is 64 bits long and takes up two 913 * locations in the memory map. The least significant bits are stored 914 * in EMAC_HSL and the most significant bits in EMAC_HSH. 915 * 916 * The unicast hash enable and the multicast hash enable bits in the 917 * network configuration register enable the reception of hash matched 918 * frames. The destination address is reduced to a 6 bit index into 919 * the 64 bit hash register using the following hash function. The 920 * hash function is an exclusive or of every sixth bit of the 921 * destination address. 922 * 923 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] 924 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] 925 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] 926 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] 927 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] 928 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] 929 * 930 * da[0] represents the least significant bit of the first byte 931 * received, that is, the multicast/unicast indicator, and da[47] 932 * represents the most significant bit of the last byte received. If 933 * the hash index, hi[n], points to a bit that is set in the hash 934 * register then the frame will be matched according to whether the 935 * frame is multicast or unicast. A multicast match will be signalled 936 * if the multicast hash enable bit is set, da[0] is 1 and the hash 937 * index points to a bit set in the hash register. A unicast match 938 * will be signalled if the unicast hash enable bit is set, da[0] is 0 939 * and the hash index points to a bit set in the hash register. To 940 * receive all multicast frames, the hash register should be set with 941 * all ones and the multicast hash enable bit should be set in the 942 * network configuration register. 943 */ 944 945static inline int hash_bit_value(int bitnr, __u8 *addr) 946{ 947 if (addr[bitnr / 8] & (1 << (bitnr % 8))) 948 return 1; 949 return 0; 950} 951 952/* 953 * Return the hash index value for the specified address. 954 */ 955static int hash_get_index(__u8 *addr) 956{ 957 int i, j, bitval; 958 int hash_index = 0; 959 960 for (j = 0; j < 6; j++) { 961 for (i = 0, bitval = 0; i < 8; i++) 962 bitval ^= hash_bit_value(i*6 + j, addr); 963 964 hash_index |= (bitval << j); 965 } 966 967 return hash_index; 968} 969 970/* 971 * Add multicast addresses to the internal multicast-hash table. 972 */ 973static void macb_sethashtable(struct net_device *dev) 974{ 975 struct netdev_hw_addr *ha; 976 unsigned long mc_filter[2]; 977 unsigned int bitnr; 978 struct macb *bp = netdev_priv(dev); 979 980 mc_filter[0] = mc_filter[1] = 0; 981 982 netdev_for_each_mc_addr(ha, dev) { 983 bitnr = hash_get_index(ha->addr); 984 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); 985 } 986 987 macb_or_gem_writel(bp, HRB, mc_filter[0]); 988 macb_or_gem_writel(bp, HRT, mc_filter[1]); 989} 990 991/* 992 * Enable/Disable promiscuous and multicast modes. 993 */ 994static void macb_set_rx_mode(struct net_device *dev) 995{ 996 unsigned long cfg; 997 struct macb *bp = netdev_priv(dev); 998 999 cfg = macb_readl(bp, NCFGR); 1000 1001 if (dev->flags & IFF_PROMISC) 1002 /* Enable promiscuous mode */ 1003 cfg |= MACB_BIT(CAF); 1004 else if (dev->flags & (~IFF_PROMISC)) 1005 /* Disable promiscuous mode */ 1006 cfg &= ~MACB_BIT(CAF); 1007 1008 if (dev->flags & IFF_ALLMULTI) { 1009 /* Enable all multicast mode */ 1010 macb_or_gem_writel(bp, HRB, -1); 1011 macb_or_gem_writel(bp, HRT, -1); 1012 cfg |= MACB_BIT(NCFGR_MTI); 1013 } else if (!netdev_mc_empty(dev)) { 1014 /* Enable specific multicasts */ 1015 macb_sethashtable(dev); 1016 cfg |= MACB_BIT(NCFGR_MTI); 1017 } else if (dev->flags & (~IFF_ALLMULTI)) { 1018 /* Disable all multicast mode */ 1019 macb_or_gem_writel(bp, HRB, 0); 1020 macb_or_gem_writel(bp, HRT, 0); 1021 cfg &= ~MACB_BIT(NCFGR_MTI); 1022 } 1023 1024 macb_writel(bp, NCFGR, cfg); 1025} 1026 1027static int macb_open(struct net_device *dev) 1028{ 1029 struct macb *bp = netdev_priv(dev); 1030 int err; 1031 1032 netdev_dbg(bp->dev, "open\n"); 1033 1034 /* if the phy is not yet register, retry later*/ 1035 if (!bp->phy_dev) 1036 return -EAGAIN; 1037 1038 if (!is_valid_ether_addr(dev->dev_addr)) 1039 return -EADDRNOTAVAIL; 1040 1041 err = macb_alloc_consistent(bp); 1042 if (err) { 1043 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n", 1044 err); 1045 return err; 1046 } 1047 1048 napi_enable(&bp->napi); 1049 1050 macb_init_rings(bp); 1051 macb_init_hw(bp); 1052 1053 /* schedule a link state check */ 1054 phy_start(bp->phy_dev); 1055 1056 netif_start_queue(dev); 1057 1058 return 0; 1059} 1060 1061static int macb_close(struct net_device *dev) 1062{ 1063 struct macb *bp = netdev_priv(dev); 1064 unsigned long flags; 1065 1066 netif_stop_queue(dev); 1067 napi_disable(&bp->napi); 1068 1069 if (bp->phy_dev) 1070 phy_stop(bp->phy_dev); 1071 1072 spin_lock_irqsave(&bp->lock, flags); 1073 macb_reset_hw(bp); 1074 netif_carrier_off(dev); 1075 spin_unlock_irqrestore(&bp->lock, flags); 1076 1077 macb_free_consistent(bp); 1078 1079 return 0; 1080} 1081 1082static void gem_update_stats(struct macb *bp) 1083{ 1084 u32 __iomem *reg = bp->regs + GEM_OTX; 1085 u32 *p = &bp->hw_stats.gem.tx_octets_31_0; 1086 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1; 1087 1088 for (; p < end; p++, reg++) 1089 *p += __raw_readl(reg); 1090} 1091 1092static struct net_device_stats *gem_get_stats(struct macb *bp) 1093{ 1094 struct gem_stats *hwstat = &bp->hw_stats.gem; 1095 struct net_device_stats *nstat = &bp->stats; 1096 1097 gem_update_stats(bp); 1098 1099 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors + 1100 hwstat->rx_alignment_errors + 1101 hwstat->rx_resource_errors + 1102 hwstat->rx_overruns + 1103 hwstat->rx_oversize_frames + 1104 hwstat->rx_jabbers + 1105 hwstat->rx_undersized_frames + 1106 hwstat->rx_length_field_frame_errors); 1107 nstat->tx_errors = (hwstat->tx_late_collisions + 1108 hwstat->tx_excessive_collisions + 1109 hwstat->tx_underrun + 1110 hwstat->tx_carrier_sense_errors); 1111 nstat->multicast = hwstat->rx_multicast_frames; 1112 nstat->collisions = (hwstat->tx_single_collision_frames + 1113 hwstat->tx_multiple_collision_frames + 1114 hwstat->tx_excessive_collisions); 1115 nstat->rx_length_errors = (hwstat->rx_oversize_frames + 1116 hwstat->rx_jabbers + 1117 hwstat->rx_undersized_frames + 1118 hwstat->rx_length_field_frame_errors); 1119 nstat->rx_over_errors = hwstat->rx_resource_errors; 1120 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors; 1121 nstat->rx_frame_errors = hwstat->rx_alignment_errors; 1122 nstat->rx_fifo_errors = hwstat->rx_overruns; 1123 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions; 1124 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors; 1125 nstat->tx_fifo_errors = hwstat->tx_underrun; 1126 1127 return nstat; 1128} 1129 1130static struct net_device_stats *macb_get_stats(struct net_device *dev) 1131{ 1132 struct macb *bp = netdev_priv(dev); 1133 struct net_device_stats *nstat = &bp->stats; 1134 struct macb_stats *hwstat = &bp->hw_stats.macb; 1135 1136 if (macb_is_gem(bp)) 1137 return gem_get_stats(bp); 1138 1139 /* read stats from hardware */ 1140 macb_update_stats(bp); 1141 1142 /* Convert HW stats into netdevice stats */ 1143 nstat->rx_errors = (hwstat->rx_fcs_errors + 1144 hwstat->rx_align_errors + 1145 hwstat->rx_resource_errors + 1146 hwstat->rx_overruns + 1147 hwstat->rx_oversize_pkts + 1148 hwstat->rx_jabbers + 1149 hwstat->rx_undersize_pkts + 1150 hwstat->sqe_test_errors + 1151 hwstat->rx_length_mismatch); 1152 nstat->tx_errors = (hwstat->tx_late_cols + 1153 hwstat->tx_excessive_cols + 1154 hwstat->tx_underruns + 1155 hwstat->tx_carrier_errors); 1156 nstat->collisions = (hwstat->tx_single_cols + 1157 hwstat->tx_multiple_cols + 1158 hwstat->tx_excessive_cols); 1159 nstat->rx_length_errors = (hwstat->rx_oversize_pkts + 1160 hwstat->rx_jabbers + 1161 hwstat->rx_undersize_pkts + 1162 hwstat->rx_length_mismatch); 1163 nstat->rx_over_errors = hwstat->rx_resource_errors + 1164 hwstat->rx_overruns; 1165 nstat->rx_crc_errors = hwstat->rx_fcs_errors; 1166 nstat->rx_frame_errors = hwstat->rx_align_errors; 1167 nstat->rx_fifo_errors = hwstat->rx_overruns; 1168 /* XXX: What does "missed" mean? */ 1169 nstat->tx_aborted_errors = hwstat->tx_excessive_cols; 1170 nstat->tx_carrier_errors = hwstat->tx_carrier_errors; 1171 nstat->tx_fifo_errors = hwstat->tx_underruns; 1172 /* Don't know about heartbeat or window errors... */ 1173 1174 return nstat; 1175} 1176 1177static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1178{ 1179 struct macb *bp = netdev_priv(dev); 1180 struct phy_device *phydev = bp->phy_dev; 1181 1182 if (!phydev) 1183 return -ENODEV; 1184 1185 return phy_ethtool_gset(phydev, cmd); 1186} 1187 1188static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1189{ 1190 struct macb *bp = netdev_priv(dev); 1191 struct phy_device *phydev = bp->phy_dev; 1192 1193 if (!phydev) 1194 return -ENODEV; 1195 1196 return phy_ethtool_sset(phydev, cmd); 1197} 1198 1199static void macb_get_drvinfo(struct net_device *dev, 1200 struct ethtool_drvinfo *info) 1201{ 1202 struct macb *bp = netdev_priv(dev); 1203 1204 strcpy(info->driver, bp->pdev->dev.driver->name); 1205 strcpy(info->version, "$Revision: 1.14 $"); 1206 strcpy(info->bus_info, dev_name(&bp->pdev->dev)); 1207} 1208 1209static const struct ethtool_ops macb_ethtool_ops = { 1210 .get_settings = macb_get_settings, 1211 .set_settings = macb_set_settings, 1212 .get_drvinfo = macb_get_drvinfo, 1213 .get_link = ethtool_op_get_link, 1214}; 1215 1216static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1217{ 1218 struct macb *bp = netdev_priv(dev); 1219 struct phy_device *phydev = bp->phy_dev; 1220 1221 if (!netif_running(dev)) 1222 return -EINVAL; 1223 1224 if (!phydev) 1225 return -ENODEV; 1226 1227 return phy_mii_ioctl(phydev, rq, cmd); 1228} 1229 1230static const struct net_device_ops macb_netdev_ops = { 1231 .ndo_open = macb_open, 1232 .ndo_stop = macb_close, 1233 .ndo_start_xmit = macb_start_xmit, 1234 .ndo_set_rx_mode = macb_set_rx_mode, 1235 .ndo_get_stats = macb_get_stats, 1236 .ndo_do_ioctl = macb_ioctl, 1237 .ndo_validate_addr = eth_validate_addr, 1238 .ndo_change_mtu = eth_change_mtu, 1239 .ndo_set_mac_address = eth_mac_addr, 1240#ifdef CONFIG_NET_POLL_CONTROLLER 1241 .ndo_poll_controller = macb_poll_controller, 1242#endif 1243}; 1244 1245#if defined(CONFIG_OF) 1246static const struct of_device_id macb_dt_ids[] = { 1247 { .compatible = "cdns,at32ap7000-macb" }, 1248 { .compatible = "cdns,at91sam9260-macb" }, 1249 { .compatible = "cdns,macb" }, 1250 { .compatible = "cdns,pc302-gem" }, 1251 { .compatible = "cdns,gem" }, 1252 { /* sentinel */ } 1253}; 1254 1255MODULE_DEVICE_TABLE(of, macb_dt_ids); 1256 1257static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev) 1258{ 1259 struct device_node *np = pdev->dev.of_node; 1260 1261 if (np) 1262 return of_get_phy_mode(np); 1263 1264 return -ENODEV; 1265} 1266 1267static int __devinit macb_get_hwaddr_dt(struct macb *bp) 1268{ 1269 struct device_node *np = bp->pdev->dev.of_node; 1270 if (np) { 1271 const char *mac = of_get_mac_address(np); 1272 if (mac) { 1273 memcpy(bp->dev->dev_addr, mac, ETH_ALEN); 1274 return 0; 1275 } 1276 } 1277 1278 return -ENODEV; 1279} 1280#else 1281static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev) 1282{ 1283 return -ENODEV; 1284} 1285static int __devinit macb_get_hwaddr_dt(struct macb *bp) 1286{ 1287 return -ENODEV; 1288} 1289#endif 1290 1291static int __init macb_probe(struct platform_device *pdev) 1292{ 1293 struct macb_platform_data *pdata; 1294 struct resource *regs; 1295 struct net_device *dev; 1296 struct macb *bp; 1297 struct phy_device *phydev; 1298 u32 config; 1299 int err = -ENXIO; 1300 1301 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1302 if (!regs) { 1303 dev_err(&pdev->dev, "no mmio resource defined\n"); 1304 goto err_out; 1305 } 1306 1307 err = -ENOMEM; 1308 dev = alloc_etherdev(sizeof(*bp)); 1309 if (!dev) { 1310 dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n"); 1311 goto err_out; 1312 } 1313 1314 SET_NETDEV_DEV(dev, &pdev->dev); 1315 1316 /* TODO: Actually, we have some interesting features... */ 1317 dev->features |= 0; 1318 1319 bp = netdev_priv(dev); 1320 bp->pdev = pdev; 1321 bp->dev = dev; 1322 1323 spin_lock_init(&bp->lock); 1324 1325 bp->pclk = clk_get(&pdev->dev, "pclk"); 1326 if (IS_ERR(bp->pclk)) { 1327 dev_err(&pdev->dev, "failed to get macb_clk\n"); 1328 goto err_out_free_dev; 1329 } 1330 clk_enable(bp->pclk); 1331 1332 bp->hclk = clk_get(&pdev->dev, "hclk"); 1333 if (IS_ERR(bp->hclk)) { 1334 dev_err(&pdev->dev, "failed to get hclk\n"); 1335 goto err_out_put_pclk; 1336 } 1337 clk_enable(bp->hclk); 1338 1339 bp->regs = ioremap(regs->start, resource_size(regs)); 1340 if (!bp->regs) { 1341 dev_err(&pdev->dev, "failed to map registers, aborting.\n"); 1342 err = -ENOMEM; 1343 goto err_out_disable_clocks; 1344 } 1345 1346 dev->irq = platform_get_irq(pdev, 0); 1347 err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev); 1348 if (err) { 1349 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n", 1350 dev->irq, err); 1351 goto err_out_iounmap; 1352 } 1353 1354 dev->netdev_ops = &macb_netdev_ops; 1355 netif_napi_add(dev, &bp->napi, macb_poll, 64); 1356 dev->ethtool_ops = &macb_ethtool_ops; 1357 1358 dev->base_addr = regs->start; 1359 1360 /* Set MII management clock divider */ 1361 config = macb_mdc_clk_div(bp); 1362 config |= macb_dbw(bp); 1363 macb_writel(bp, NCFGR, config); 1364 1365 err = macb_get_hwaddr_dt(bp); 1366 if (err < 0) 1367 macb_get_hwaddr(bp); 1368 1369 err = macb_get_phy_mode_dt(pdev); 1370 if (err < 0) { 1371 pdata = pdev->dev.platform_data; 1372 if (pdata && pdata->is_rmii) 1373 bp->phy_interface = PHY_INTERFACE_MODE_RMII; 1374 else 1375 bp->phy_interface = PHY_INTERFACE_MODE_MII; 1376 } else { 1377 bp->phy_interface = err; 1378 } 1379 1380 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII) 1381#if defined(CONFIG_ARCH_AT91) 1382 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) | 1383 MACB_BIT(CLKEN))); 1384#else 1385 macb_or_gem_writel(bp, USRIO, 0); 1386#endif 1387 else 1388#if defined(CONFIG_ARCH_AT91) 1389 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN)); 1390#else 1391 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII)); 1392#endif 1393 1394 bp->tx_pending = DEF_TX_RING_PENDING; 1395 1396 err = register_netdev(dev); 1397 if (err) { 1398 dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); 1399 goto err_out_free_irq; 1400 } 1401 1402 if (macb_mii_init(bp) != 0) { 1403 goto err_out_unregister_netdev; 1404 } 1405 1406 platform_set_drvdata(pdev, dev); 1407 1408 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n", 1409 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr, 1410 dev->irq, dev->dev_addr); 1411 1412 phydev = bp->phy_dev; 1413 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 1414 phydev->drv->name, dev_name(&phydev->dev), phydev->irq); 1415 1416 return 0; 1417 1418err_out_unregister_netdev: 1419 unregister_netdev(dev); 1420err_out_free_irq: 1421 free_irq(dev->irq, dev); 1422err_out_iounmap: 1423 iounmap(bp->regs); 1424err_out_disable_clocks: 1425 clk_disable(bp->hclk); 1426 clk_put(bp->hclk); 1427 clk_disable(bp->pclk); 1428err_out_put_pclk: 1429 clk_put(bp->pclk); 1430err_out_free_dev: 1431 free_netdev(dev); 1432err_out: 1433 platform_set_drvdata(pdev, NULL); 1434 return err; 1435} 1436 1437static int __exit macb_remove(struct platform_device *pdev) 1438{ 1439 struct net_device *dev; 1440 struct macb *bp; 1441 1442 dev = platform_get_drvdata(pdev); 1443 1444 if (dev) { 1445 bp = netdev_priv(dev); 1446 if (bp->phy_dev) 1447 phy_disconnect(bp->phy_dev); 1448 mdiobus_unregister(bp->mii_bus); 1449 kfree(bp->mii_bus->irq); 1450 mdiobus_free(bp->mii_bus); 1451 unregister_netdev(dev); 1452 free_irq(dev->irq, dev); 1453 iounmap(bp->regs); 1454 clk_disable(bp->hclk); 1455 clk_put(bp->hclk); 1456 clk_disable(bp->pclk); 1457 clk_put(bp->pclk); 1458 free_netdev(dev); 1459 platform_set_drvdata(pdev, NULL); 1460 } 1461 1462 return 0; 1463} 1464 1465#ifdef CONFIG_PM 1466static int macb_suspend(struct platform_device *pdev, pm_message_t state) 1467{ 1468 struct net_device *netdev = platform_get_drvdata(pdev); 1469 struct macb *bp = netdev_priv(netdev); 1470 1471 netif_device_detach(netdev); 1472 1473 clk_disable(bp->hclk); 1474 clk_disable(bp->pclk); 1475 1476 return 0; 1477} 1478 1479static int macb_resume(struct platform_device *pdev) 1480{ 1481 struct net_device *netdev = platform_get_drvdata(pdev); 1482 struct macb *bp = netdev_priv(netdev); 1483 1484 clk_enable(bp->pclk); 1485 clk_enable(bp->hclk); 1486 1487 netif_device_attach(netdev); 1488 1489 return 0; 1490} 1491#else 1492#define macb_suspend NULL 1493#define macb_resume NULL 1494#endif 1495 1496static struct platform_driver macb_driver = { 1497 .remove = __exit_p(macb_remove), 1498 .suspend = macb_suspend, 1499 .resume = macb_resume, 1500 .driver = { 1501 .name = "macb", 1502 .owner = THIS_MODULE, 1503 .of_match_table = of_match_ptr(macb_dt_ids), 1504 }, 1505}; 1506 1507static int __init macb_init(void) 1508{ 1509 return platform_driver_probe(&macb_driver, macb_probe); 1510} 1511 1512static void __exit macb_exit(void) 1513{ 1514 platform_driver_unregister(&macb_driver); 1515} 1516 1517module_init(macb_init); 1518module_exit(macb_exit); 1519 1520MODULE_LICENSE("GPL"); 1521MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver"); 1522MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 1523MODULE_ALIAS("platform:macb"); 1524