be.h revision 97767a87f3be8834192dc3fc9412aaccf708d87f 
1/*
2 * Copyright (C) 2005 - 2011 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation.  The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@emulex.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18#ifndef BE_H
19#define BE_H
20
21#include <linux/pci.h>
22#include <linux/etherdevice.h>
23#include <linux/delay.h>
24#include <net/tcp.h>
25#include <net/ip.h>
26#include <net/ipv6.h>
27#include <linux/if_vlan.h>
28#include <linux/workqueue.h>
29#include <linux/interrupt.h>
30#include <linux/firmware.h>
31#include <linux/slab.h>
32#include <linux/u64_stats_sync.h>
33
34#include "be_hw.h"
35
36#define DRV_VER			"4.2.116u"
37#define DRV_NAME		"be2net"
38#define BE_NAME			"ServerEngines BladeEngine2 10Gbps NIC"
39#define BE3_NAME		"ServerEngines BladeEngine3 10Gbps NIC"
40#define OC_NAME			"Emulex OneConnect 10Gbps NIC"
41#define OC_NAME_BE		OC_NAME	"(be3)"
42#define OC_NAME_LANCER		OC_NAME "(Lancer)"
43#define OC_NAME_SH		OC_NAME "(Skyhawk)"
44#define DRV_DESC		"ServerEngines BladeEngine 10Gbps NIC Driver"
45
46#define BE_VENDOR_ID 		0x19a2
47#define EMULEX_VENDOR_ID	0x10df
48#define BE_DEVICE_ID1		0x211
49#define BE_DEVICE_ID2		0x221
50#define OC_DEVICE_ID1		0x700	/* Device Id for BE2 cards */
51#define OC_DEVICE_ID2		0x710	/* Device Id for BE3 cards */
52#define OC_DEVICE_ID3		0xe220	/* Device id for Lancer cards */
53#define OC_DEVICE_ID4           0xe228   /* Device id for VF in Lancer */
54#define OC_DEVICE_ID5		0x720	/* Device Id for Skyhawk cards */
55
56static inline char *nic_name(struct pci_dev *pdev)
57{
58	switch (pdev->device) {
59	case OC_DEVICE_ID1:
60		return OC_NAME;
61	case OC_DEVICE_ID2:
62		return OC_NAME_BE;
63	case OC_DEVICE_ID3:
64	case OC_DEVICE_ID4:
65		return OC_NAME_LANCER;
66	case BE_DEVICE_ID2:
67		return BE3_NAME;
68	case OC_DEVICE_ID5:
69		return OC_NAME_SH;
70	default:
71		return BE_NAME;
72	}
73}
74
75/* Number of bytes of an RX frame that are copied to skb->data */
76#define BE_HDR_LEN		((u16) 64)
77/* allocate extra space to allow tunneling decapsulation without head reallocation */
78#define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64)
79
80#define BE_MAX_JUMBO_FRAME_SIZE	9018
81#define BE_MIN_MTU		256
82
83#define BE_NUM_VLANS_SUPPORTED	64
84#define BE_MAX_EQD		96u
85#define	BE_MAX_TX_FRAG_COUNT	30
86
87#define EVNT_Q_LEN		1024
88#define TX_Q_LEN		2048
89#define TX_CQ_LEN		1024
90#define RX_Q_LEN		1024	/* Does not support any other value */
91#define RX_CQ_LEN		1024
92#define MCC_Q_LEN		128	/* total size not to exceed 8 pages */
93#define MCC_CQ_LEN		256
94
95#define BE3_MAX_RSS_QS		8
96#define BE2_MAX_RSS_QS		4
97#define MAX_RSS_QS		BE3_MAX_RSS_QS
98#define MAX_RX_QS		(MAX_RSS_QS + 1) /* RSS qs + 1 def Rx */
99
100#define MAX_TX_QS		8
101#define MAX_MSIX_VECTORS	MAX_RSS_QS
102#define BE_TX_BUDGET		256
103#define BE_NAPI_WEIGHT		64
104#define MAX_RX_POST		BE_NAPI_WEIGHT /* Frags posted at a time */
105#define RX_FRAGS_REFILL_WM	(RX_Q_LEN - MAX_RX_POST)
106
107#define FW_VER_LEN		32
108
109struct be_dma_mem {
110	void *va;
111	dma_addr_t dma;
112	u32 size;
113};
114
115struct be_queue_info {
116	struct be_dma_mem dma_mem;
117	u16 len;
118	u16 entry_size;	/* Size of an element in the queue */
119	u16 id;
120	u16 tail, head;
121	bool created;
122	atomic_t used;	/* Number of valid elements in the queue */
123};
124
125static inline u32 MODULO(u16 val, u16 limit)
126{
127	BUG_ON(limit & (limit - 1));
128	return val & (limit - 1);
129}
130
131static inline void index_adv(u16 *index, u16 val, u16 limit)
132{
133	*index = MODULO((*index + val), limit);
134}
135
136static inline void index_inc(u16 *index, u16 limit)
137{
138	*index = MODULO((*index + 1), limit);
139}
140
141static inline void *queue_head_node(struct be_queue_info *q)
142{
143	return q->dma_mem.va + q->head * q->entry_size;
144}
145
146static inline void *queue_tail_node(struct be_queue_info *q)
147{
148	return q->dma_mem.va + q->tail * q->entry_size;
149}
150
151static inline void *queue_index_node(struct be_queue_info *q, u16 index)
152{
153	return q->dma_mem.va + index * q->entry_size;
154}
155
156static inline void queue_head_inc(struct be_queue_info *q)
157{
158	index_inc(&q->head, q->len);
159}
160
161static inline void queue_tail_inc(struct be_queue_info *q)
162{
163	index_inc(&q->tail, q->len);
164}
165
166struct be_eq_obj {
167	struct be_queue_info q;
168	char desc[32];
169
170	/* Adaptive interrupt coalescing (AIC) info */
171	bool enable_aic;
172	u32 min_eqd;		/* in usecs */
173	u32 max_eqd;		/* in usecs */
174	u32 eqd;		/* configured val when aic is off */
175	u32 cur_eqd;		/* in usecs */
176
177	u8 idx;			/* array index */
178	u16 tx_budget;
179	struct napi_struct napi;
180	struct be_adapter *adapter;
181} ____cacheline_aligned_in_smp;
182
183struct be_mcc_obj {
184	struct be_queue_info q;
185	struct be_queue_info cq;
186	bool rearm_cq;
187};
188
189struct be_tx_stats {
190	u64 tx_bytes;
191	u64 tx_pkts;
192	u64 tx_reqs;
193	u64 tx_wrbs;
194	u64 tx_compl;
195	ulong tx_jiffies;
196	u32 tx_stops;
197	struct u64_stats_sync sync;
198	struct u64_stats_sync sync_compl;
199};
200
201struct be_tx_obj {
202	struct be_queue_info q;
203	struct be_queue_info cq;
204	/* Remember the skbs that were transmitted */
205	struct sk_buff *sent_skb_list[TX_Q_LEN];
206	struct be_tx_stats stats;
207} ____cacheline_aligned_in_smp;
208
209/* Struct to remember the pages posted for rx frags */
210struct be_rx_page_info {
211	struct page *page;
212	DEFINE_DMA_UNMAP_ADDR(bus);
213	u16 page_offset;
214	bool last_page_user;
215};
216
217struct be_rx_stats {
218	u64 rx_bytes;
219	u64 rx_pkts;
220	u64 rx_pkts_prev;
221	ulong rx_jiffies;
222	u32 rx_drops_no_skbs;	/* skb allocation errors */
223	u32 rx_drops_no_frags;	/* HW has no fetched frags */
224	u32 rx_post_fail;	/* page post alloc failures */
225	u32 rx_compl;
226	u32 rx_mcast_pkts;
227	u32 rx_compl_err;	/* completions with err set */
228	u32 rx_pps;		/* pkts per second */
229	struct u64_stats_sync sync;
230};
231
232struct be_rx_compl_info {
233	u32 rss_hash;
234	u16 vlan_tag;
235	u16 pkt_size;
236	u16 rxq_idx;
237	u16 port;
238	u8 vlanf;
239	u8 num_rcvd;
240	u8 err;
241	u8 ipf;
242	u8 tcpf;
243	u8 udpf;
244	u8 ip_csum;
245	u8 l4_csum;
246	u8 ipv6;
247	u8 vtm;
248	u8 pkt_type;
249};
250
251struct be_rx_obj {
252	struct be_adapter *adapter;
253	struct be_queue_info q;
254	struct be_queue_info cq;
255	struct be_rx_compl_info rxcp;
256	struct be_rx_page_info page_info_tbl[RX_Q_LEN];
257	struct be_rx_stats stats;
258	u8 rss_id;
259	bool rx_post_starved;	/* Zero rx frags have been posted to BE */
260} ____cacheline_aligned_in_smp;
261
262struct be_drv_stats {
263	u32 be_on_die_temperature;
264	u32 eth_red_drops;
265	u32 rx_drops_no_pbuf;
266	u32 rx_drops_no_txpb;
267	u32 rx_drops_no_erx_descr;
268	u32 rx_drops_no_tpre_descr;
269	u32 rx_drops_too_many_frags;
270	u32 forwarded_packets;
271	u32 rx_drops_mtu;
272	u32 rx_crc_errors;
273	u32 rx_alignment_symbol_errors;
274	u32 rx_pause_frames;
275	u32 rx_priority_pause_frames;
276	u32 rx_control_frames;
277	u32 rx_in_range_errors;
278	u32 rx_out_range_errors;
279	u32 rx_frame_too_long;
280	u32 rx_address_mismatch_drops;
281	u32 rx_dropped_too_small;
282	u32 rx_dropped_too_short;
283	u32 rx_dropped_header_too_small;
284	u32 rx_dropped_tcp_length;
285	u32 rx_dropped_runt;
286	u32 rx_ip_checksum_errs;
287	u32 rx_tcp_checksum_errs;
288	u32 rx_udp_checksum_errs;
289	u32 tx_pauseframes;
290	u32 tx_priority_pauseframes;
291	u32 tx_controlframes;
292	u32 rxpp_fifo_overflow_drop;
293	u32 rx_input_fifo_overflow_drop;
294	u32 pmem_fifo_overflow_drop;
295	u32 jabber_events;
296};
297
298struct be_vf_cfg {
299	unsigned char mac_addr[ETH_ALEN];
300	int if_handle;
301	int pmac_id;
302	u16 vlan_tag;
303	u32 tx_rate;
304};
305
306#define BE_FLAGS_LINK_STATUS_INIT		1
307#define BE_FLAGS_WORKER_SCHEDULED		(1 << 3)
308
309struct be_adapter {
310	struct pci_dev *pdev;
311	struct net_device *netdev;
312
313	u8 __iomem *csr;
314	u8 __iomem *db;		/* Door Bell */
315
316	struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
317	struct be_dma_mem mbox_mem;
318	/* Mbox mem is adjusted to align to 16 bytes. The allocated addr
319	 * is stored for freeing purpose */
320	struct be_dma_mem mbox_mem_alloced;
321
322	struct be_mcc_obj mcc_obj;
323	spinlock_t mcc_lock;	/* For serializing mcc cmds to BE card */
324	spinlock_t mcc_cq_lock;
325
326	u32 num_msix_vec;
327	u32 num_evt_qs;
328	struct be_eq_obj eq_obj[MAX_MSIX_VECTORS];
329	struct msix_entry msix_entries[MAX_MSIX_VECTORS];
330	bool isr_registered;
331
332	/* TX Rings */
333	u32 num_tx_qs;
334	struct be_tx_obj tx_obj[MAX_TX_QS];
335
336	/* Rx rings */
337	u32 num_rx_qs;
338	struct be_rx_obj rx_obj[MAX_RX_QS];
339	u32 big_page_size;	/* Compounded page size shared by rx wrbs */
340
341	u8 eq_next_idx;
342	struct be_drv_stats drv_stats;
343
344	u16 vlans_added;
345	u16 max_vlans;	/* Number of vlans supported */
346	u8 vlan_tag[VLAN_N_VID];
347	u8 vlan_prio_bmap;	/* Available Priority BitMap */
348	u16 recommended_prio;	/* Recommended Priority */
349	struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */
350
351	struct be_dma_mem stats_cmd;
352	/* Work queue used to perform periodic tasks like getting statistics */
353	struct delayed_work work;
354	u16 work_counter;
355
356	u32 flags;
357	/* Ethtool knobs and info */
358	char fw_ver[FW_VER_LEN];
359	int if_handle;		/* Used to configure filtering */
360	u32 pmac_id;		/* MAC addr handle used by BE card */
361	u32 beacon_state;	/* for set_phys_id */
362
363	bool eeh_err;
364	bool ue_detected;
365	bool fw_timeout;
366	u32 port_num;
367	bool promiscuous;
368	bool wol;
369	u32 function_mode;
370	u32 function_caps;
371	u32 rx_fc;		/* Rx flow control */
372	u32 tx_fc;		/* Tx flow control */
373	bool stats_cmd_sent;
374	int link_speed;
375	u8 port_type;
376	u8 transceiver;
377	u8 autoneg;
378	u8 generation;		/* BladeEngine ASIC generation */
379	u32 flash_status;
380	struct completion flash_compl;
381
382	u32 num_vfs;
383	u8 is_virtfn;
384	struct be_vf_cfg *vf_cfg;
385	bool be3_native;
386	u32 sli_family;
387	u8 hba_port_num;
388	u16 pvid;
389};
390
391#define be_physfn(adapter) (!adapter->is_virtfn)
392#define	sriov_enabled(adapter)		(adapter->num_vfs > 0)
393#define for_all_vfs(adapter, vf_cfg, i)					\
394	for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs;	\
395		i++, vf_cfg++)
396
397/* BladeEngine Generation numbers */
398#define BE_GEN2 2
399#define BE_GEN3 3
400
401#define ON				1
402#define OFF				0
403#define lancer_chip(adapter)	((adapter->pdev->device == OC_DEVICE_ID3) || \
404				 (adapter->pdev->device == OC_DEVICE_ID4))
405
406extern const struct ethtool_ops be_ethtool_ops;
407
408#define msix_enabled(adapter)		(adapter->num_msix_vec > 0)
409#define num_irqs(adapter)		(msix_enabled(adapter) ?	\
410						adapter->num_msix_vec : 1)
411#define tx_stats(txo)			(&(txo)->stats)
412#define rx_stats(rxo)			(&(rxo)->stats)
413
414/* The default RXQ is the last RXQ */
415#define default_rxo(adpt)		(&adpt->rx_obj[adpt->num_rx_qs - 1])
416
417#define for_all_rx_queues(adapter, rxo, i)				\
418	for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;	\
419		i++, rxo++)
420
421/* Skip the default non-rss queue (last one)*/
422#define for_all_rss_queues(adapter, rxo, i)				\
423	for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\
424		i++, rxo++)
425
426#define for_all_tx_queues(adapter, txo, i)				\
427	for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;	\
428		i++, txo++)
429
430#define for_all_evt_queues(adapter, eqo, i)				\
431	for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
432		i++, eqo++)
433
434#define is_mcc_eqo(eqo)			(eqo->idx == 0)
435#define mcc_eqo(adapter)		(&adapter->eq_obj[0])
436
437#define PAGE_SHIFT_4K		12
438#define PAGE_SIZE_4K		(1 << PAGE_SHIFT_4K)
439
440/* Returns number of pages spanned by the data starting at the given addr */
441#define PAGES_4K_SPANNED(_address, size) 				\
442		((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + 	\
443			(size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
444
445/* Returns bit offset within a DWORD of a bitfield */
446#define AMAP_BIT_OFFSET(_struct, field)  				\
447		(((size_t)&(((_struct *)0)->field))%32)
448
449/* Returns the bit mask of the field that is NOT shifted into location. */
450static inline u32 amap_mask(u32 bitsize)
451{
452	return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
453}
454
455static inline void
456amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
457{
458	u32 *dw = (u32 *) ptr + dw_offset;
459	*dw &= ~(mask << offset);
460	*dw |= (mask & value) << offset;
461}
462
463#define AMAP_SET_BITS(_struct, field, ptr, val)				\
464		amap_set(ptr,						\
465			offsetof(_struct, field)/32,			\
466			amap_mask(sizeof(((_struct *)0)->field)),	\
467			AMAP_BIT_OFFSET(_struct, field),		\
468			val)
469
470static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
471{
472	u32 *dw = (u32 *) ptr;
473	return mask & (*(dw + dw_offset) >> offset);
474}
475
476#define AMAP_GET_BITS(_struct, field, ptr)				\
477		amap_get(ptr,						\
478			offsetof(_struct, field)/32,			\
479			amap_mask(sizeof(((_struct *)0)->field)),	\
480			AMAP_BIT_OFFSET(_struct, field))
481
482#define be_dws_cpu_to_le(wrb, len)	swap_dws(wrb, len)
483#define be_dws_le_to_cpu(wrb, len)	swap_dws(wrb, len)
484static inline void swap_dws(void *wrb, int len)
485{
486#ifdef __BIG_ENDIAN
487	u32 *dw = wrb;
488	BUG_ON(len % 4);
489	do {
490		*dw = cpu_to_le32(*dw);
491		dw++;
492		len -= 4;
493	} while (len);
494#endif				/* __BIG_ENDIAN */
495}
496
497static inline u8 is_tcp_pkt(struct sk_buff *skb)
498{
499	u8 val = 0;
500
501	if (ip_hdr(skb)->version == 4)
502		val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
503	else if (ip_hdr(skb)->version == 6)
504		val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
505
506	return val;
507}
508
509static inline u8 is_udp_pkt(struct sk_buff *skb)
510{
511	u8 val = 0;
512
513	if (ip_hdr(skb)->version == 4)
514		val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
515	else if (ip_hdr(skb)->version == 6)
516		val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
517
518	return val;
519}
520
521static inline void be_check_sriov_fn_type(struct be_adapter *adapter)
522{
523	u32 sli_intf;
524
525	pci_read_config_dword(adapter->pdev, SLI_INTF_REG_OFFSET, &sli_intf);
526	adapter->is_virtfn = (sli_intf & SLI_INTF_FT_MASK) ? 1 : 0;
527}
528
529static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac)
530{
531	u32 addr;
532
533	addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0);
534
535	mac[5] = (u8)(addr & 0xFF);
536	mac[4] = (u8)((addr >> 8) & 0xFF);
537	mac[3] = (u8)((addr >> 16) & 0xFF);
538	/* Use the OUI from the current MAC address */
539	memcpy(mac, adapter->netdev->dev_addr, 3);
540}
541
542static inline bool be_multi_rxq(const struct be_adapter *adapter)
543{
544	return adapter->num_rx_qs > 1;
545}
546
547static inline bool be_error(struct be_adapter *adapter)
548{
549	return adapter->eeh_err || adapter->ue_detected || adapter->fw_timeout;
550}
551
552extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
553		u16 num_popped);
554extern void be_link_status_update(struct be_adapter *adapter, u8 link_status);
555extern void be_parse_stats(struct be_adapter *adapter);
556extern int be_load_fw(struct be_adapter *adapter, u8 *func);
557#endif				/* BE_H */
558