18d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang/* 28d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * Faraday FTMAC100 10/100 Ethernet 38d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * 48d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * (C) Copyright 2009-2011 Faraday Technology 58d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * Po-Yu Chuang <ratbert@faraday-tech.com> 68d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * 78d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * This program is free software; you can redistribute it and/or modify 88d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * it under the terms of the GNU General Public License as published by 98d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * the Free Software Foundation; either version 2 of the License, or 108d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * (at your option) any later version. 118d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * 128d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * This program is distributed in the hope that it will be useful, 138d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * but WITHOUT ANY WARRANTY; without even the implied warranty of 148d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 158d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * GNU General Public License for more details. 168d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * 178d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * You should have received a copy of the GNU General Public License 188d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * along with this program; if not, write to the Free Software 198d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 208d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang */ 218d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang 228d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#ifndef __FTMAC100_H 238d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define __FTMAC100_H 248d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang 258d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_ISR 0x00 268d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_IMR 0x04 278d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_MAC_MADR 0x08 288d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_MAC_LADR 0x0c 298d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_MAHT0 0x10 308d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_MAHT1 0x14 318d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_TXPD 0x18 328d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_RXPD 0x1c 338d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_TXR_BADR 0x20 348d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_RXR_BADR 0x24 358d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_ITC 0x28 368d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_APTC 0x2c 378d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_DBLAC 0x30 388d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_MACCR 0x88 398d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_MACSR 0x8c 408d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_PHYCR 0x90 418d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_PHYWDATA 0x94 428d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_FCR 0x98 438d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_BPR 0x9c 448d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_TS 0xc4 458d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_DMAFIFOS 0xc8 468d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_TM 0xcc 478d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_TX_MCOL_SCOL 0xd4 488d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_RPF_AEP 0xd8 498d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_XM_PG 0xdc 508d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_RUNT_TLCC 0xe0 518d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_CRCER_FTL 0xe4 528d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_RLC_RCC 0xe8 538d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_BROC 0xec 548d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_MULCA 0xf0 558d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_RP 0xf4 568d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_OFFSET_XP 0xf8 578d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang 588d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang/* 598d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * Interrupt status register & interrupt mask register 608d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang */ 618d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_INT_RPKT_FINISH (1 << 0) 628d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_INT_NORXBUF (1 << 1) 638d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_INT_XPKT_FINISH (1 << 2) 648d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_INT_NOTXBUF (1 << 3) 658d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_INT_XPKT_OK (1 << 4) 668d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_INT_XPKT_LOST (1 << 5) 678d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_INT_RPKT_SAV (1 << 6) 688d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_INT_RPKT_LOST (1 << 7) 698d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_INT_AHB_ERR (1 << 8) 708d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_INT_PHYSTS_CHG (1 << 9) 718d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang 728d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang/* 738d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * Interrupt timer control register 748d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang */ 758d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0) 768d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4) 778d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_ITC_RXINT_TIME_SEL (1 << 7) 788d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8) 798d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12) 808d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_ITC_TXINT_TIME_SEL (1 << 15) 818d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang 828d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang/* 838d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * Automatic polling timer control register 848d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang */ 858d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) 868d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) 878d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) 888d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) 898d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang 908d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang/* 918d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * DMA burst length and arbitration control register 928d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang */ 938d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_DBLAC_INCR4_EN (1 << 0) 948d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_DBLAC_INCR8_EN (1 << 1) 958d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_DBLAC_INCR16_EN (1 << 2) 968d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 3) 978d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 6) 988d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_DBLAC_RX_THR_EN (1 << 9) 998d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang 1008d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang/* 1018d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * MAC control register 1028d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang */ 1038d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_MACCR_XDMA_EN (1 << 0) 1048d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_MACCR_RDMA_EN (1 << 1) 1058d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_MACCR_SW_RST (1 << 2) 1068d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_MACCR_LOOP_EN (1 << 3) 1078d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_MACCR_CRC_DIS (1 << 4) 1088d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_MACCR_XMT_EN (1 << 5) 1098d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_MACCR_ENRX_IN_HALFTX (1 << 6) 1108d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_MACCR_RCV_EN (1 << 8) 1118d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_MACCR_HT_MULTI_EN (1 << 9) 1128d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_MACCR_RX_RUNT (1 << 10) 1138d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_MACCR_RX_FTL (1 << 11) 1148d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_MACCR_RCV_ALL (1 << 12) 1158d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_MACCR_CRC_APD (1 << 14) 1168d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_MACCR_FULLDUP (1 << 15) 1178d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_MACCR_RX_MULTIPKT (1 << 16) 1188d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_MACCR_RX_BROADPKT (1 << 17) 1198d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang 1208d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang/* 1218d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * PHY control register 1228d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang */ 1238d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_PHYCR_MIIRDATA 0xffff 1248d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) 1258d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) 1268d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_PHYCR_MIIRD (1 << 26) 1278d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_PHYCR_MIIWR (1 << 27) 1288d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang 1298d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang/* 1308d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * PHY write data register 1318d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang */ 1328d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_PHYWDATA_MIIWDATA(x) ((x) & 0xffff) 1338d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang 1348d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang/* 1358d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * Transmit descriptor, aligned to 16 bytes 1368d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang */ 1378d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuangstruct ftmac100_txdes { 1388d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang unsigned int txdes0; 1398d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang unsigned int txdes1; 1408d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang unsigned int txdes2; /* TXBUF_BADR */ 1418d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang unsigned int txdes3; /* not used by HW */ 1428d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang} __attribute__ ((aligned(16))); 1438d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang 1448d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_TXDES0_TXPKT_LATECOL (1 << 0) 1458d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_TXDES0_TXPKT_EXSCOL (1 << 1) 1468d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_TXDES0_TXDMA_OWN (1 << 31) 1478d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang 1488d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_TXDES1_TXBUF_SIZE(x) ((x) & 0x7ff) 1498d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_TXDES1_LTS (1 << 27) 1508d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_TXDES1_FTS (1 << 28) 1518d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_TXDES1_TX2FIC (1 << 29) 1528d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_TXDES1_TXIC (1 << 30) 1538d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_TXDES1_EDOTR (1 << 31) 1548d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang 1558d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang/* 1568d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang * Receive descriptor, aligned to 16 bytes 1578d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang */ 1588d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuangstruct ftmac100_rxdes { 1598d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang unsigned int rxdes0; 1608d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang unsigned int rxdes1; 1618d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang unsigned int rxdes2; /* RXBUF_BADR */ 1628d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang unsigned int rxdes3; /* not used by HW */ 1638d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang} __attribute__ ((aligned(16))); 1648d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang 1658d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_RXDES0_RFL 0x7ff 1668d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_RXDES0_MULTICAST (1 << 16) 1678d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_RXDES0_BROADCAST (1 << 17) 1688d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_RXDES0_RX_ERR (1 << 18) 1698d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_RXDES0_CRC_ERR (1 << 19) 1708d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_RXDES0_FTL (1 << 20) 1718d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_RXDES0_RUNT (1 << 21) 1728d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_RXDES0_RX_ODD_NB (1 << 22) 1738d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_RXDES0_LRS (1 << 28) 1748d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_RXDES0_FRS (1 << 29) 1758d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_RXDES0_RXDMA_OWN (1 << 31) 1768d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang 1778d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_RXDES1_RXBUF_SIZE(x) ((x) & 0x7ff) 1788d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#define FTMAC100_RXDES1_EDORR (1 << 31) 1798d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang 1808d77c036b57cf813d838f859e11b6a188acdb1fbPo-Yu Chuang#endif /* __FTMAC100_H */ 181