148257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#ifndef FS_ENET_H 248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define FS_ENET_H 348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#include <linux/mii.h> 548257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#include <linux/netdevice.h> 648257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#include <linux/types.h> 748257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#include <linux/list.h> 85b4b8454344a0391bb0f69fda0f4ec8e1f0d2fedVitaly Bordug#include <linux/phy.h> 9d6bd3a39f7c6ebad49c261c3d458df974c880758Rolf Eike Beer#include <linux/dma-mapping.h> 1048257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 1148257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#include <linux/fs_enet_pd.h> 125427828e83b7f3c000eaec1cfb09c9bc4d024ad1Vitaly Bordug#include <asm/fs_pd.h> 1348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 1448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#ifdef CONFIG_CPM1 15b5677d848cbb94220ac2cfd36d93bcdbe49c3280Jochen Friedrich#include <asm/cpm1.h> 1660ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin#endif 1760ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin 1860ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin#if defined(CONFIG_FS_ENET_HAS_FEC) 1960ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin#include <asm/cpm.h> 2060ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin 2160ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin#if defined(CONFIG_FS_ENET_MPC5121_FEC) 2260ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin/* MPC5121 FEC has different register layout */ 2360ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschinstruct fec { 2460ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_reserved0; 2560ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_ievent; /* Interrupt event reg */ 2660ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_imask; /* Interrupt mask reg */ 2760ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_reserved1; 2860ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_r_des_active; /* Receive descriptor reg */ 2960ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_x_des_active; /* Transmit descriptor reg */ 3060ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_reserved2[3]; 3160ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_ecntrl; /* Ethernet control reg */ 3260ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_reserved3[6]; 3360ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_mii_data; /* MII manage frame reg */ 3460ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_mii_speed; /* MII speed control reg */ 3560ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_reserved4[7]; 3660ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_mib_ctrlstat; /* MIB control/status reg */ 3760ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_reserved5[7]; 3860ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_r_cntrl; /* Receive control reg */ 3960ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_reserved6[15]; 4060ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_x_cntrl; /* Transmit Control reg */ 4160ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_reserved7[7]; 4260ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_addr_low; /* Low 32bits MAC address */ 4360ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_addr_high; /* High 16bits MAC address */ 4460ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_opd; /* Opcode + Pause duration */ 4560ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_reserved8[10]; 4660ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_hash_table_high; /* High 32bits hash table */ 4760ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_hash_table_low; /* Low 32bits hash table */ 4860ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_grp_hash_table_high; /* High 32bits hash table */ 4960ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_grp_hash_table_low; /* Low 32bits hash table */ 5060ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_reserved9[7]; 5160ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_x_wmrk; /* FIFO transmit water mark */ 5260ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_reserved10; 5360ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_r_bound; /* FIFO receive bound reg */ 5460ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_r_fstart; /* FIFO receive start reg */ 5560ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_reserved11[11]; 5660ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_r_des_start; /* Receive descriptor ring */ 5760ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_x_des_start; /* Transmit descriptor ring */ 5860ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_r_buff_size; /* Maximum receive buff size */ 5960ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_reserved12[26]; 6060ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin u32 fec_dma_control; /* DMA Endian and other ctrl */ 6160ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin}; 6260ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin#endif 635b4b8454344a0391bb0f69fda0f4ec8e1f0d2fedVitaly Bordug 645b4b8454344a0391bb0f69fda0f4ec8e1f0d2fedVitaly Bordugstruct fec_info { 6560ab4361adc188fb47da1c4892cc7a2bb621efefAnatolij Gustschin struct fec __iomem *fecp; 660fb300fa9d54118c6dce772a29362d896775eff2Scott Wood u32 mii_speed; 675b4b8454344a0391bb0f69fda0f4ec8e1f0d2fedVitaly Bordug}; 6848257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#endif 6948257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 7048257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#ifdef CONFIG_CPM2 7148257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#include <asm/cpm2.h> 7248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#endif 7348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 7448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/* hw driver ops */ 7548257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antonioustruct fs_ops { 7648257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou int (*setup_data)(struct net_device *dev); 7748257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou int (*allocate_bd)(struct net_device *dev); 7848257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou void (*free_bd)(struct net_device *dev); 7948257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou void (*cleanup_data)(struct net_device *dev); 8048257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou void (*set_multicast_list)(struct net_device *dev); 815b4b8454344a0391bb0f69fda0f4ec8e1f0d2fedVitaly Bordug void (*adjust_link)(struct net_device *dev); 8248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou void (*restart)(struct net_device *dev); 8348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou void (*stop)(struct net_device *dev); 8448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou void (*napi_clear_rx_event)(struct net_device *dev); 8548257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou void (*napi_enable_rx)(struct net_device *dev); 8648257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou void (*napi_disable_rx)(struct net_device *dev); 8748257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou void (*rx_bd_done)(struct net_device *dev); 8848257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou void (*tx_kickstart)(struct net_device *dev); 8948257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou u32 (*get_int_events)(struct net_device *dev); 9048257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou void (*clear_int_events)(struct net_device *dev, u32 int_events); 9148257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou void (*ev_error)(struct net_device *dev, u32 int_events); 9248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou int (*get_regs)(struct net_device *dev, void *p, int *sizep); 9348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou int (*get_regs_len)(struct net_device *dev); 9448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou void (*tx_restart)(struct net_device *dev); 9548257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou}; 9648257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 9748257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antonioustruct phy_info { 9848257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou unsigned int id; 9948257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou const char *name; 10048257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou void (*startup) (struct net_device * dev); 10148257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou void (*shutdown) (struct net_device * dev); 10248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou void (*ack_int) (struct net_device * dev); 10348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou}; 10448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 10548257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/* The FEC stores dest/src/type, data, and checksum for receive packets. 10648257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou */ 10748257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define MAX_MTU 1508 /* Allow fullsized pppoe packets over VLAN */ 10848257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define MIN_MTU 46 /* this is data size */ 10948257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define CRC_LEN 4 11048257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 11148257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define PKT_MAXBUF_SIZE (MAX_MTU+ETH_HLEN+CRC_LEN) 11248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define PKT_MINBUF_SIZE (MIN_MTU+ETH_HLEN+CRC_LEN) 11348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 11448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/* Must be a multiple of 32 (to cover both FEC & FCC) */ 11548257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define PKT_MAXBLR_SIZE ((PKT_MAXBUF_SIZE + 31) & ~31) 11648257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/* This is needed so that invalidate_xxx wont invalidate too much */ 1170d0d9c150c046cbd3e507adcfa2d78db82f1f452Scott Wood#define ENET_RX_ALIGN 16 1180d0d9c150c046cbd3e507adcfa2d78db82f1f452Scott Wood#define ENET_RX_FRSIZE L1_CACHE_ALIGN(PKT_MAXBUF_SIZE + ENET_RX_ALIGN - 1) 11948257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 12048257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antonioustruct fs_enet_private { 121bea3348eef27e6044b6161fd04c3152215f96411Stephen Hemminger struct napi_struct napi; 12248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou struct device *dev; /* pointer back to the device (must be initialized first) */ 123f860f49ee2e59d1a665416c9155cad7661ee0552Scott Wood struct net_device *ndev; 12448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou spinlock_t lock; /* during all ops except TX pckt processing */ 12548257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou spinlock_t tx_lock; /* during fs_start_xmit and fs_tx */ 126976de6a8c304dcc43e38efcb8a0bace7866b6242Scott Wood struct fs_platform_info *fpi; 12748257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou const struct fs_ops *ops; 12848257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou int rx_ring, tx_ring; 12948257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou dma_addr_t ring_mem_addr; 13031a5bb04d59931eb4657826213a439d37d12d4a9Scott Wood void __iomem *ring_base; 13148257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou struct sk_buff **rx_skbuff; 13248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou struct sk_buff **tx_skbuff; 13331a5bb04d59931eb4657826213a439d37d12d4a9Scott Wood cbd_t __iomem *rx_bd_base; /* Address of Rx and Tx buffers. */ 13431a5bb04d59931eb4657826213a439d37d12d4a9Scott Wood cbd_t __iomem *tx_bd_base; 13531a5bb04d59931eb4657826213a439d37d12d4a9Scott Wood cbd_t __iomem *dirty_tx; /* ring entries to be free()ed. */ 13631a5bb04d59931eb4657826213a439d37d12d4a9Scott Wood cbd_t __iomem *cur_rx; 13731a5bb04d59931eb4657826213a439d37d12d4a9Scott Wood cbd_t __iomem *cur_tx; 13848257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou int tx_free; 13948257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou struct net_device_stats stats; 14048257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou struct timer_list phy_timer_list; 14148257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou const struct phy_info *phy; 14248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou u32 msg_enable; 14348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou struct mii_if_info mii_if; 14448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou unsigned int last_mii_status; 14548257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou int interrupt; 14648257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 1475b4b8454344a0391bb0f69fda0f4ec8e1f0d2fedVitaly Bordug struct phy_device *phydev; 1485b4b8454344a0391bb0f69fda0f4ec8e1f0d2fedVitaly Bordug int oldduplex, oldspeed, oldlink; /* current settings */ 14948257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 15048257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou /* event masks */ 15148257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou u32 ev_napi_rx; /* mask of NAPI rx events */ 15248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou u32 ev_rx; /* rx event mask */ 15348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou u32 ev_tx; /* tx event mask */ 15448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou u32 ev_err; /* error event mask */ 15548257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 15648257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou u16 bd_rx_empty; /* mask of BD rx empty */ 15748257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou u16 bd_rx_err; /* mask of BD rx errors */ 15848257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 15948257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou union { 16048257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou struct { 16148257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou int idx; /* FEC1 = 0, FEC2 = 1 */ 16231a5bb04d59931eb4657826213a439d37d12d4a9Scott Wood void __iomem *fecp; /* hw registers */ 16348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou u32 hthi, htlo; /* state for multicast */ 16448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou } fec; 16548257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 16648257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou struct { 16748257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou int idx; /* FCC1-3 = 0-2 */ 16831a5bb04d59931eb4657826213a439d37d12d4a9Scott Wood void __iomem *fccp; /* hw registers */ 16931a5bb04d59931eb4657826213a439d37d12d4a9Scott Wood void __iomem *ep; /* parameter ram */ 17031a5bb04d59931eb4657826213a439d37d12d4a9Scott Wood void __iomem *fcccp; /* hw registers cont. */ 17131a5bb04d59931eb4657826213a439d37d12d4a9Scott Wood void __iomem *mem; /* FCC DPRAM */ 17248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou u32 gaddrh, gaddrl; /* group address */ 17348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou } fcc; 17448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 17548257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou struct { 17648257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou int idx; /* FEC1 = 0, FEC2 = 1 */ 17731a5bb04d59931eb4657826213a439d37d12d4a9Scott Wood void __iomem *sccp; /* hw registers */ 17831a5bb04d59931eb4657826213a439d37d12d4a9Scott Wood void __iomem *ep; /* parameter ram */ 17948257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou u32 hthi, htlo; /* state for multicast */ 18048257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou } scc; 18148257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 18248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou }; 18348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou}; 18448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 18548257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/***************************************************************************/ 18648257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 18748257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniouvoid fs_init_bds(struct net_device *dev); 18848257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniouvoid fs_cleanup_bds(struct net_device *dev); 18948257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 19048257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/***************************************************************************/ 19148257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 19248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define DRV_MODULE_NAME "fs_enet" 19348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define PFX DRV_MODULE_NAME ": " 19448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define DRV_MODULE_VERSION "1.0" 19548257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define DRV_MODULE_RELDATE "Aug 8, 2005" 19648257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 19748257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/***************************************************************************/ 19848257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 19948257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniouint fs_enet_platform_init(void); 20048257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniouvoid fs_enet_platform_cleanup(void); 20148257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 20248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/***************************************************************************/ 20348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/* buffer descriptor access macros */ 20448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 20548257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/* access macros */ 20648257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#if defined(CONFIG_CPM1) 20748257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/* for a a CPM1 __raw_xxx's are sufficient */ 20848257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define __cbd_out32(addr, x) __raw_writel(x, addr) 20948257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define __cbd_out16(addr, x) __raw_writew(x, addr) 21048257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define __cbd_in32(addr) __raw_readl(addr) 21148257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define __cbd_in16(addr) __raw_readw(addr) 21248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#else 21348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/* for others play it safe */ 21448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define __cbd_out32(addr, x) out_be32(addr, x) 21548257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define __cbd_out16(addr, x) out_be16(addr, x) 21648257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define __cbd_in32(addr) in_be32(addr) 21748257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define __cbd_in16(addr) in_be16(addr) 21848257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#endif 21948257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 22048257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/* write */ 22148257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define CBDW_SC(_cbd, _sc) __cbd_out16(&(_cbd)->cbd_sc, (_sc)) 22248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define CBDW_DATLEN(_cbd, _datlen) __cbd_out16(&(_cbd)->cbd_datlen, (_datlen)) 22348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define CBDW_BUFADDR(_cbd, _bufaddr) __cbd_out32(&(_cbd)->cbd_bufaddr, (_bufaddr)) 22448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 22548257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/* read */ 22648257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define CBDR_SC(_cbd) __cbd_in16(&(_cbd)->cbd_sc) 22748257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define CBDR_DATLEN(_cbd) __cbd_in16(&(_cbd)->cbd_datlen) 22848257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define CBDR_BUFADDR(_cbd) __cbd_in32(&(_cbd)->cbd_bufaddr) 22948257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 23048257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/* set bits */ 23148257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define CBDS_SC(_cbd, _sc) CBDW_SC(_cbd, CBDR_SC(_cbd) | (_sc)) 23248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 23348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/* clear bits */ 23448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#define CBDC_SC(_cbd, _sc) CBDW_SC(_cbd, CBDR_SC(_cbd) & ~(_sc)) 23548257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 23648257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/*******************************************************************/ 23748257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 23848257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniouextern const struct fs_ops fs_fec_ops; 23948257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniouextern const struct fs_ops fs_fcc_ops; 24048257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniouextern const struct fs_ops fs_scc_ops; 24148257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 24248257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou/*******************************************************************/ 24348257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou 24448257c4f168e5d040394aeca4d37b59f68e0d36bPantelis Antoniou#endif 245