core.h revision b68d185ab12b1fc8000432c5d5ab5404d4788b4c
11d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* 21d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * drivers/net/ibm_newemac/core.h 31d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * 41d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * Driver for PowerPC 4xx on-chip ethernet controller. 51d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * 617cf803a57c89c5afe6d5299ac9416683c3240ddBenjamin Herrenschmidt * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. 717cf803a57c89c5afe6d5299ac9416683c3240ddBenjamin Herrenschmidt * <benh@kernel.crashing.org> 817cf803a57c89c5afe6d5299ac9416683c3240ddBenjamin Herrenschmidt * 917cf803a57c89c5afe6d5299ac9416683c3240ddBenjamin Herrenschmidt * Based on the arch/ppc version of the driver: 1017cf803a57c89c5afe6d5299ac9416683c3240ddBenjamin Herrenschmidt * 111d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * Copyright (c) 2004, 2005 Zultys Technologies. 121d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 131d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * 141d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * Based on original work by 151d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * Armin Kuster <akuster@mvista.com> 161d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * Johnnie Peters <jpeters@mvista.com> 171d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * Copyright 2000, 2001 MontaVista Softare Inc. 181d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * 191d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * This program is free software; you can redistribute it and/or modify it 201d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * under the terms of the GNU General Public License as published by the 211d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * Free Software Foundation; either version 2 of the License, or (at your 221d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * option) any later version. 231d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * 241d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson */ 251d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#ifndef __IBM_NEWEMAC_CORE_H 261d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#define __IBM_NEWEMAC_CORE_H 271d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 281d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#include <linux/module.h> 291d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#include <linux/init.h> 301d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#include <linux/list.h> 311d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#include <linux/kernel.h> 321d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#include <linux/interrupt.h> 331d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#include <linux/netdevice.h> 341d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#include <linux/dma-mapping.h> 351d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#include <linux/spinlock.h> 3655b6c8e99d582cc66947b465d0ff3147a0219808Stephen Rothwell#include <linux/of_platform.h> 371d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 381d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#include <asm/io.h> 391d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#include <asm/dcr.h> 401d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 411d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#include "emac.h" 421d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#include "phy.h" 431d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#include "zmii.h" 441d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#include "rgmii.h" 451d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#include "mal.h" 461d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#include "tah.h" 471d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#include "debug.h" 481d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 491d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#define NUM_TX_BUFF CONFIG_IBM_NEW_EMAC_TXB 501d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#define NUM_RX_BUFF CONFIG_IBM_NEW_EMAC_RXB 511d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 521d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* Simple sanity check */ 531d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256 541d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#error Invalid number of buffer descriptors (greater than 256) 551d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#endif 561d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 571d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#define EMAC_MIN_MTU 46 581d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 591d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* Maximum L2 header length (VLAN tagged, no FCS) */ 601d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#define EMAC_MTU_OVERHEAD (6 * 2 + 2 + 4) 611d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 621d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* RX BD size for the given MTU */ 631d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibsonstatic inline int emac_rx_size(int mtu) 641d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson{ 651d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson if (mtu > ETH_DATA_LEN) 661d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson return MAL_MAX_RX_SIZE; 671d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson else 681d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD); 691d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson} 701d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 711d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#define EMAC_DMA_ALIGN(x) ALIGN((x), dma_get_cache_alignment()) 721d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 731d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#define EMAC_RX_SKB_HEADROOM \ 741d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson EMAC_DMA_ALIGN(CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM) 751d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 761d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* Size of RX skb for the given MTU */ 771d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibsonstatic inline int emac_rx_skb_size(int mtu) 781d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson{ 791d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu)); 801d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson return EMAC_DMA_ALIGN(size + 2) + EMAC_RX_SKB_HEADROOM; 811d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson} 821d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 831d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* RX DMA sync size */ 841d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibsonstatic inline int emac_rx_sync_size(int mtu) 851d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson{ 861d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson return EMAC_DMA_ALIGN(emac_rx_size(mtu) + 2); 871d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson} 881d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 891d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* Driver statistcs is split into two parts to make it more cache friendly: 901d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * - normal statistics (packet count, etc) 911d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * - error statistics 921d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * 931d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * When statistics is requested by ethtool, these parts are concatenated, 941d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * normal one goes first. 951d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * 961d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * Please, keep these structures in sync with emac_stats_keys. 971d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson */ 981d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 991d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* Normal TX/RX Statistics */ 1001d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibsonstruct emac_stats { 1011d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_packets; 1021d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_bytes; 1031d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_packets; 1041d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_bytes; 1051d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_packets_csum; 1061d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_packets_csum; 1071d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson}; 1081d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 1091d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* Error statistics */ 1101d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibsonstruct emac_error_stats { 1111d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_undo; 1121d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 1131d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* Software RX Errors */ 1141d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_dropped_stack; 1151d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_dropped_oom; 1161d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_dropped_error; 1171d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_dropped_resize; 1181d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_dropped_mtu; 1191d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_stopped; 1201d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* BD reported RX errors */ 1211d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_bd_errors; 1221d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_bd_overrun; 1231d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_bd_bad_packet; 1241d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_bd_runt_packet; 1251d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_bd_short_event; 1261d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_bd_alignment_error; 1271d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_bd_bad_fcs; 1281d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_bd_packet_too_long; 1291d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_bd_out_of_range; 1301d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_bd_in_range; 1311d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* EMAC IRQ reported RX errors */ 1321d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_parity; 1331d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_fifo_overrun; 1341d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_overrun; 1351d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_bad_packet; 1361d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_runt_packet; 1371d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_short_event; 1381d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_alignment_error; 1391d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_bad_fcs; 1401d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_packet_too_long; 1411d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_out_of_range; 1421d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 rx_in_range; 1431d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 1441d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* Software TX Errors */ 1451d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_dropped; 1461d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* BD reported TX errors */ 1471d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_bd_errors; 1481d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_bd_bad_fcs; 1491d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_bd_carrier_loss; 1501d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_bd_excessive_deferral; 1511d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_bd_excessive_collisions; 1521d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_bd_late_collision; 1531d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_bd_multple_collisions; 1541d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_bd_single_collision; 1551d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_bd_underrun; 1561d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_bd_sqe; 1571d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* EMAC IRQ reported TX errors */ 1581d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_parity; 1591d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_underrun; 1601d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_sqe; 1611d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u64 tx_errors; 1621d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson}; 1631d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 1641d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#define EMAC_ETHTOOL_STATS_COUNT ((sizeof(struct emac_stats) + \ 1651d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson sizeof(struct emac_error_stats)) \ 1661d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson / sizeof(u64)) 1671d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 1681d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibsonstruct emac_instance { 1691d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct net_device *ndev; 1701d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct resource rsrc_regs; 1711d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct emac_regs __iomem *emacp; 1721d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct of_device *ofdev; 1731d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct device_node **blist; /* bootlist entry */ 1741d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 1751d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* MAL linkage */ 1761d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 mal_ph; 1771d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct of_device *mal_dev; 1781d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 mal_rx_chan; 1791d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 mal_tx_chan; 1801d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct mal_instance *mal; 1811d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct mal_commac commac; 1821d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 1831d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* PHY infos */ 1841d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 phy_mode; 1851d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 phy_map; 1861d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 phy_address; 1871d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 phy_feat_exc; 1881d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct mii_phy phy; 1891d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct mutex link_lock; 1901d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct delayed_work link_work; 1911d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson int link_polling; 1921d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 1931d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* Shared MDIO if any */ 1941d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 mdio_ph; 1951d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct of_device *mdio_dev; 1961d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct emac_instance *mdio_instance; 1971d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct mutex mdio_lock; 1981d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 1991d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* ZMII infos if any */ 2001d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 zmii_ph; 2011d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 zmii_port; 2021d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct of_device *zmii_dev; 2031d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 2041d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* RGMII infos if any */ 2051d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 rgmii_ph; 2061d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 rgmii_port; 2071d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct of_device *rgmii_dev; 2081d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 2091d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* TAH infos if any */ 2101d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 tah_ph; 2111d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 tah_port; 2121d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct of_device *tah_dev; 2131d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 2141d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* IRQs */ 2151d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson int wol_irq; 2161d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson int emac_irq; 2171d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 2181d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* OPB bus frequency in Mhz */ 2191d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 opb_bus_freq; 2201d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 2211d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* Cell index within an ASIC (for clk mgmnt) */ 2221d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 cell_index; 2231d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 2241d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* Max supported MTU */ 2251d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 max_mtu; 2261d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 2271d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* Feature bits (from probe table) */ 2281d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson unsigned int features; 2291d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 2301d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* Tx and Rx fifo sizes & other infos in bytes */ 2311d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 tx_fifo_size; 2321d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 tx_fifo_size_gige; 2331d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 rx_fifo_size; 2341d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 rx_fifo_size_gige; 2351d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 fifo_entry_size; 2361d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 mal_burst_size; /* move to MAL ? */ 2371d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 23805781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson /* IAHT and GAHT filter parameterization */ 23905781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson u32 xaht_slots_shift; 24005781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson u32 xaht_width_shift; 24105781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson 2421d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* Descriptor management 2431d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson */ 2441d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct mal_descriptor *tx_desc; 2451d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson int tx_cnt; 2461d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson int tx_slot; 2471d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson int ack_slot; 2481d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 2491d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct mal_descriptor *rx_desc; 2501d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson int rx_slot; 2511d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct sk_buff *rx_sg_skb; /* 1 */ 2521d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson int rx_skb_size; 2531d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson int rx_sync_size; 2541d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 2551d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct sk_buff *tx_skb[NUM_TX_BUFF]; 2561d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct sk_buff *rx_skb[NUM_RX_BUFF]; 2571d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 2581d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* Stats 2591d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson */ 2601d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct emac_error_stats estats; 2611d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct net_device_stats nstats; 2621d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct emac_stats stats; 2631d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 2641d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson /* Misc 2651d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson */ 2661d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson int reset_failed; 2671d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson int stop_timeout; /* in us */ 2681d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson int no_mcast; 2691d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson int mcast_pending; 27061dbcecef568450de954115180881bf2f68511bcBenjamin Herrenschmidt int opened; 2711d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson struct work_struct reset_work; 2721d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson spinlock_t lock; 2731d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson}; 2741d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 2751d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* 2761d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * Features of various EMAC implementations 2771d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson */ 2781d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 2791d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* 2801d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * No flow control on 40x according to the original driver 2811d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson */ 2821d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#define EMAC_FTR_NO_FLOW_CONTROL_40x 0x00000001 2831d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* 2841d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * Cell is an EMAC4 2851d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson */ 2861d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#define EMAC_FTR_EMAC4 0x00000002 2871d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* 2881d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * For the 440SPe, AMCC inexplicably changed the polarity of 2891d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * the "operation complete" bit in the MII control register. 2901d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson */ 2911d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#define EMAC_FTR_STACR_OC_INVERT 0x00000004 2921d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* 2931d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * Set if we have a TAH. 2941d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson */ 2951d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#define EMAC_FTR_HAS_TAH 0x00000008 2961d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* 2971d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * Set if we have a ZMII. 2981d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson */ 2991d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#define EMAC_FTR_HAS_ZMII 0x00000010 3001d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* 3011d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * Set if we have a RGMII. 3021d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson */ 3031d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#define EMAC_FTR_HAS_RGMII 0x00000020 3041d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* 305bff713b562d495658093f1716a80c6ad76920e8bBenjamin Herrenschmidt * Set if we have new type STACR with STAOPC 3061d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson */ 307bff713b562d495658093f1716a80c6ad76920e8bBenjamin Herrenschmidt#define EMAC_FTR_HAS_NEW_STACR 0x00000040 3080925ab5d385b6cd1c435c82bfc01898c81f3d062Valentine Barshak/* 3090925ab5d385b6cd1c435c82bfc01898c81f3d062Valentine Barshak * Set if we need phy clock workaround for 440gx 3100925ab5d385b6cd1c435c82bfc01898c81f3d062Valentine Barshak */ 3110925ab5d385b6cd1c435c82bfc01898c81f3d062Valentine Barshak#define EMAC_FTR_440GX_PHY_CLK_FIX 0x00000080 31211121e3008a9282fc185cb2e81eda2d5436d099bValentine Barshak/* 31311121e3008a9282fc185cb2e81eda2d5436d099bValentine Barshak * Set if we need phy clock workaround for 440ep or 440gr 31411121e3008a9282fc185cb2e81eda2d5436d099bValentine Barshak */ 31511121e3008a9282fc185cb2e81eda2d5436d099bValentine Barshak#define EMAC_FTR_440EP_PHY_CLK_FIX 0x00000100 31605781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson/* 31705781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson * The 405EX and 460EX contain the EMAC4SYNC core 31805781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson */ 31905781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson#define EMAC_FTR_EMAC4SYNC 0x00000200 3201d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 3211d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 3221d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* Right now, we don't quite handle the always/possible masks on the 3231d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * most optimal way as we don't have a way to say something like 3241d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * always EMAC4. Patches welcome. 3251d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson */ 3261d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibsonenum { 3271d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson EMAC_FTRS_ALWAYS = 0, 3281d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 3291d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson EMAC_FTRS_POSSIBLE = 3301d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#ifdef CONFIG_IBM_NEW_EMAC_EMAC4 33105781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC | 33205781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson EMAC_FTR_HAS_NEW_STACR | 3330925ab5d385b6cd1c435c82bfc01898c81f3d062Valentine Barshak EMAC_FTR_STACR_OC_INVERT | EMAC_FTR_440GX_PHY_CLK_FIX | 3341d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#endif 3351d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#ifdef CONFIG_IBM_NEW_EMAC_TAH 3361d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson EMAC_FTR_HAS_TAH | 3371d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#endif 3381d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#ifdef CONFIG_IBM_NEW_EMAC_ZMII 3391d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson EMAC_FTR_HAS_ZMII | 3401d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#endif 3411d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#ifdef CONFIG_IBM_NEW_EMAC_RGMII 3421d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson EMAC_FTR_HAS_RGMII | 3431d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#endif 344b68d185ab12b1fc8000432c5d5ab5404d4788b4cJosh Boyer#ifdef CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL 345b68d185ab12b1fc8000432c5d5ab5404d4788b4cJosh Boyer EMAC_FTR_NO_FLOW_CONTROL_40x | 346b68d185ab12b1fc8000432c5d5ab5404d4788b4cJosh Boyer#endif 34711121e3008a9282fc185cb2e81eda2d5436d099bValentine Barshak EMAC_FTR_440EP_PHY_CLK_FIX, 3481d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson}; 3491d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 3501d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibsonstatic inline int emac_has_feature(struct emac_instance *dev, 3511d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson unsigned long feature) 3521d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson{ 3531d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson return (EMAC_FTRS_ALWAYS & feature) || 3541d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson (EMAC_FTRS_POSSIBLE & dev->features & feature); 3551d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson} 3561d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 35705781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson/* 35805781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson * Various instances of the EMAC core have varying 1) number of 35905781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson * address match slots, 2) width of the registers for handling address 36005781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson * match slots, 3) number of registers for handling address match 36105781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson * slots and 4) base offset for those registers. 36205781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson * 36305781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson * These macros and inlines handle these differences based on 36405781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson * parameters supplied by the device structure which are, in turn, 36505781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson * initialized based on the "compatible" entry in the device tree. 36605781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson */ 36705781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson 36805781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson#define EMAC4_XAHT_SLOTS_SHIFT 6 36905781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson#define EMAC4_XAHT_WIDTH_SHIFT 4 37005781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson 37105781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson#define EMAC4SYNC_XAHT_SLOTS_SHIFT 8 37205781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson#define EMAC4SYNC_XAHT_WIDTH_SHIFT 5 37305781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson 37405781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson#define EMAC_XAHT_SLOTS(dev) (1 << (dev)->xaht_slots_shift) 37505781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson#define EMAC_XAHT_WIDTH(dev) (1 << (dev)->xaht_width_shift) 37605781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson#define EMAC_XAHT_REGS(dev) (1 << ((dev)->xaht_slots_shift - \ 37705781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson (dev)->xaht_width_shift)) 37805781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson 37905781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson#define EMAC_XAHT_CRC_TO_SLOT(dev, crc) \ 38005781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson ((EMAC_XAHT_SLOTS(dev) - 1) - \ 38105781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson ((crc) >> ((sizeof (u32) * BITS_PER_BYTE) - \ 38205781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson (dev)->xaht_slots_shift))) 38305781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson 38405781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson#define EMAC_XAHT_SLOT_TO_REG(dev, slot) \ 38505781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson ((slot) >> (dev)->xaht_width_shift) 38605781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson 38705781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson#define EMAC_XAHT_SLOT_TO_MASK(dev, slot) \ 38805781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson ((u32)(1 << (EMAC_XAHT_WIDTH(dev) - 1)) >> \ 38905781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson ((slot) & (u32)(EMAC_XAHT_WIDTH(dev) - 1))) 39005781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson 39105781ccd74c63c6c8567f99101587d5c07c163e0Grant Ericksonstatic inline u32 *emac_xaht_base(struct emac_instance *dev) 39205781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson{ 39305781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson struct emac_regs __iomem *p = dev->emacp; 39405781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson int offset; 39505781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson 39605781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson /* The first IAHT entry always is the base of the block of 39705781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson * IAHT and GAHT registers. 39805781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson */ 39905781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) 40005781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson offset = offsetof(struct emac_regs, u1.emac4sync.iaht1); 40105781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson else 40205781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson offset = offsetof(struct emac_regs, u0.emac4.iaht1); 40305781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson 40405781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson return ((u32 *)((ptrdiff_t)p + offset)); 40505781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson} 40605781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson 40705781ccd74c63c6c8567f99101587d5c07c163e0Grant Ericksonstatic inline u32 *emac_gaht_base(struct emac_instance *dev) 40805781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson{ 40905781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson /* GAHT registers always come after an identical number of 41005781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson * IAHT registers. 41105781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson */ 41205781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson return (emac_xaht_base(dev) + EMAC_XAHT_REGS(dev)); 41305781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson} 41405781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson 41505781ccd74c63c6c8567f99101587d5c07c163e0Grant Ericksonstatic inline u32 *emac_iaht_base(struct emac_instance *dev) 41605781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson{ 41705781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson /* IAHT registers always come before an identical number of 41805781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson * GAHT registers. 41905781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson */ 42005781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson return (emac_xaht_base(dev)); 42105781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson} 4221d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 4231d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson/* Ethtool get_regs complex data. 4241d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH 4251d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * when available. 4261d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * 4271d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr, 4281d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers. 4291d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * Each register component is preceded with emac_ethtool_regs_subhdr. 4301d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * Order of the optional headers follows their relative bit posititions 4311d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson * in emac_ethtool_regs_hdr.components 4321d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson */ 4331d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#define EMAC_ETHTOOL_REGS_ZMII 0x00000001 4341d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#define EMAC_ETHTOOL_REGS_RGMII 0x00000002 4351d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#define EMAC_ETHTOOL_REGS_TAH 0x00000004 4361d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 4371d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibsonstruct emac_ethtool_regs_hdr { 4381d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 components; 4391d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson}; 4401d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 4411d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibsonstruct emac_ethtool_regs_subhdr { 4421d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 version; 4431d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson u32 index; 4441d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson}; 4451d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson 44605781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson#define EMAC_ETHTOOL_REGS_VER 0 44705781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson#define EMAC_ETHTOOL_REGS_SIZE(dev) ((dev)->rsrc_regs.end - \ 44805781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson (dev)->rsrc_regs.start + 1) 44905781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson#define EMAC4_ETHTOOL_REGS_VER 1 45005781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson#define EMAC4_ETHTOOL_REGS_SIZE(dev) ((dev)->rsrc_regs.end - \ 45105781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson (dev)->rsrc_regs.start + 1) 45205781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson 4531d3bb996481e116f5f2b127cbd29b83365d2cf62David Gibson#endif /* __IBM_NEWEMAC_CORE_H */ 454