1bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/*******************************************************************************
2bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
3bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok  Intel PRO/1000 Linux driver
4f5e261e626eb3fe07adf484aaad2ecfc757feba3Bruce Allan  Copyright(c) 1999 - 2012 Intel Corporation.
5bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
6bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok  This program is free software; you can redistribute it and/or modify it
7bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok  under the terms and conditions of the GNU General Public License,
8bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok  version 2, as published by the Free Software Foundation.
9bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
10bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok  This program is distributed in the hope it will be useful, but WITHOUT
11bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok  more details.
14bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
15bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok  You should have received a copy of the GNU General Public License along with
16bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok  this program; if not, write to the Free Software Foundation, Inc.,
17bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
19bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok  The full GNU General Public License is included in this distribution in
20bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok  the file called "COPYING".
21bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
22bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok  Contact Information:
23bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok  Linux NICS <linux.nics@intel.com>
24bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
27bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok*******************************************************************************/
28bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
29bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#include "e1000.h"
30bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
31bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
32bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_get_bus_info_pcie - Get PCIe bus information
33bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
34bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
35bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Determines and stores the system bus information for a particular
36bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  network interface.  The following bus information is determined and stored:
37bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  bus speed, bus width, type (PCIe), and PCIe function.
38bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
39bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Koks32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
40bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
41f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan	struct e1000_mac_info *mac = &hw->mac;
42bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	struct e1000_bus_info *bus = &hw->bus;
43bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	struct e1000_adapter *adapter = hw->adapter;
44f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan	u16 pcie_link_status, cap_offset;
45bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
46353064de8af3bf46757376db66c29fa87a9fda3aJon Mason	cap_offset = adapter->pdev->pcie_cap;
47bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (!cap_offset) {
48bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		bus->width = e1000_bus_width_unknown;
49bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	} else {
50bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		pci_read_config_word(adapter->pdev,
51bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok				     cap_offset + PCIE_LINK_STATUS,
52bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok				     &pcie_link_status);
53bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		bus->width = (enum e1000_bus_width)((pcie_link_status &
54bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok						     PCIE_LINK_WIDTH_MASK) >>
55bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok						    PCIE_LINK_WIDTH_SHIFT);
56bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
57bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
58f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan	mac->ops.set_lan_id(hw);
59bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
60bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
61bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
62bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
63bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
64f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan *  e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
65f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan *
66f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan *  @hw: pointer to the HW structure
67f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan *
68f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan *  Determines the LAN function id by reading memory-mapped registers
69f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan *  and swaps the port value if requested.
70f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan **/
71f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allanvoid e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
72f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan{
73f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan	struct e1000_bus_info *bus = &hw->bus;
74f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan	u32 reg;
75f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan
76f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan	/*
77f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan	 * The status register reports the correct function number
78f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan	 * for the device regardless of function swap state.
79f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan	 */
80f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan	reg = er32(STATUS);
81f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan	bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
82f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan}
83f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan
84f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan/**
85f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan *  e1000_set_lan_id_single_port - Set LAN id for a single port device
86f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan *  @hw: pointer to the HW structure
87f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan *
88f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan *  Sets the LAN function id to zero for a single port device.
89f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan **/
90f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allanvoid e1000_set_lan_id_single_port(struct e1000_hw *hw)
91f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan{
92f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan	struct e1000_bus_info *bus = &hw->bus;
93f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan
94f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan	bus->func = 0;
95f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan}
96f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan
97f4d2dd4cd4d001f5dc20fc76c780c0c20c000c23Bruce Allan/**
98caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allan *  e1000_clear_vfta_generic - Clear VLAN filter table
99caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allan *  @hw: pointer to the HW structure
100caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allan *
101caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allan *  Clears the register array which contains the VLAN filter table by
102caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allan *  setting all the values to 0.
103caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allan **/
104caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allanvoid e1000_clear_vfta_generic(struct e1000_hw *hw)
105caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allan{
106caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allan	u32 offset;
107caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allan
108caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allan	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
109caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allan		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
110caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allan		e1e_flush();
111caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allan	}
112caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allan}
113caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allan
114caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allan/**
115caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allan *  e1000_write_vfta_generic - Write value to VLAN filter table
116bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
117bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @offset: register offset in VLAN filter table
118bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @value: register value written to VLAN filter table
119bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
120bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Writes value at the given offset in the register array which stores
121bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  the VLAN filter table.
122bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
123caaddaf83501c79fe11b183c8972e60d8b7d5d56Bruce Allanvoid e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
124bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
125bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
126bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	e1e_flush();
127bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
128bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
129bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
130bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_init_rx_addrs - Initialize receive address's
131bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
132bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @rar_count: receive address registers
133bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
134d64a6f4dca0b45495dd5be8116b618d9cc004eeaBruce Allan *  Setup the receive address registers by setting the base receive address
135bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  register to the devices MAC address and clearing all the other receive
136bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  address registers to 0.
137bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
138bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokvoid e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
139bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
140bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 i;
141fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan	u8 mac_addr[ETH_ALEN] = { 0 };
142bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
143bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	/* Setup the receive address */
1443bb99fe226ead584a4db674dab546689f705201fBruce Allan	e_dbg("Programming MAC Address into RAR[0]\n");
145bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
146bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	e1000e_rar_set(hw, hw->mac.addr, 0);
147bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
148bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	/* Zero out the other (rar_entry_count - 1) receive addresses */
149fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan	e_dbg("Clearing RAR[1-%u]\n", rar_count - 1);
150b7a9216c5a3205a6d721972bfd012c4eb5950e9cBruce Allan	for (i = 1; i < rar_count; i++)
151b7a9216c5a3205a6d721972bfd012c4eb5950e9cBruce Allan		e1000e_rar_set(hw, mac_addr, i);
152bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
153bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
154bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
155608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan *  e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
156608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan *  @hw: pointer to the HW structure
157608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan *
158608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan *  Checks the nvm for an alternate MAC address.  An alternate MAC address
159608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan *  can be setup by pre-boot software and must be treated like a permanent
160608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan *  address and must override the actual permanent MAC address. If an
161608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan *  alternate MAC address is found it is programmed into RAR0, replacing
162608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan *  the permanent address that was installed into RAR0 by the Si on reset.
163608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan *  This function will return SUCCESS unless it encounters an error while
164608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan *  reading the EEPROM.
165608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan **/
166608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allans32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
167608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan{
168608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	u32 i;
169608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	s32 ret_val = 0;
170608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	u16 offset, nvm_alt_mac_addr_offset, nvm_data;
171608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	u8 alt_mac_addr[ETH_ALEN];
172608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan
1731aef70ef125165e0114a8e475636eff242a52030Bruce Allan	ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data);
1741aef70ef125165e0114a8e475636eff242a52030Bruce Allan	if (ret_val)
1755015e53a4cf0c88977120faede7eb02b0459d90eBruce Allan		return ret_val;
1761aef70ef125165e0114a8e475636eff242a52030Bruce Allan
1774bcf053baf6b255e8c82c7ecd0d15954adb0379bBruce Allan	/* not supported on 82573 */
1784bcf053baf6b255e8c82c7ecd0d15954adb0379bBruce Allan	if (hw->mac.type == e1000_82573)
1795015e53a4cf0c88977120faede7eb02b0459d90eBruce Allan		return 0;
1801aef70ef125165e0114a8e475636eff242a52030Bruce Allan
181608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
182fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan				 &nvm_alt_mac_addr_offset);
183608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	if (ret_val) {
184608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan		e_dbg("NVM Read Error\n");
1855015e53a4cf0c88977120faede7eb02b0459d90eBruce Allan		return ret_val;
186608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	}
187608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan
188244735f6ebccbf72a283db89472309f770e14c80Bruce Allan	if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
189244735f6ebccbf72a283db89472309f770e14c80Bruce Allan	    (nvm_alt_mac_addr_offset == 0x0000))
190608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan		/* There is no Alternate MAC Address */
1915015e53a4cf0c88977120faede7eb02b0459d90eBruce Allan		return 0;
192608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan
193608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	if (hw->bus.func == E1000_FUNC_1)
194608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
195608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	for (i = 0; i < ETH_ALEN; i += 2) {
196608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan		offset = nvm_alt_mac_addr_offset + (i >> 1);
197608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan		ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
198608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan		if (ret_val) {
199608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan			e_dbg("NVM Read Error\n");
2005015e53a4cf0c88977120faede7eb02b0459d90eBruce Allan			return ret_val;
201608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan		}
202608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan
203608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan		alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
204608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan		alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
205608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	}
206608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan
207608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	/* if multicast bit is set, the alternate address will not be used */
2083e714ad3c2a07ee120044b72222cc20c14959efbTobias Klauser	if (is_multicast_ether_addr(alt_mac_addr)) {
209608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan		e_dbg("Ignoring Alternate Mac Address with MC bit set\n");
2105015e53a4cf0c88977120faede7eb02b0459d90eBruce Allan		return 0;
211608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	}
212608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan
213608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	/*
214608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	 * We have a valid alternate MAC address, and we want to treat it the
215608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	 * same as the normal permanent MAC address stored by the HW into the
216608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	 * RAR. Do this by mapping this address into RAR0.
217608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	 */
218608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan	e1000e_rar_set(hw, alt_mac_addr, 0);
219608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan
2205015e53a4cf0c88977120faede7eb02b0459d90eBruce Allan	return 0;
221608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan}
222608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan
223608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan/**
224bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_rar_set - Set receive address register
225bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
226bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @addr: pointer to the receive address
227bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @index: receive address array register
228bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
229bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Sets the receive address array register at index to the address passed
230bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  in by addr.
231bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
232bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokvoid e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
233bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
234bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 rar_low, rar_high;
235bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
236ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
237ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * HW expects these in little endian so we reverse the byte order
238bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * from network order (big endian) to little endian
239bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
240fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan	rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
241fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan		   ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
242bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
243fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
244bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
245b7a9216c5a3205a6d721972bfd012c4eb5950e9cBruce Allan	/* If MAC address zero, no need to set the AV bit */
246b7a9216c5a3205a6d721972bfd012c4eb5950e9cBruce Allan	if (rar_low || rar_high)
247b7a9216c5a3205a6d721972bfd012c4eb5950e9cBruce Allan		rar_high |= E1000_RAH_AV;
248bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
249b7a9216c5a3205a6d721972bfd012c4eb5950e9cBruce Allan	/*
250b7a9216c5a3205a6d721972bfd012c4eb5950e9cBruce Allan	 * Some bridges will combine consecutive 32-bit writes into
251b7a9216c5a3205a6d721972bfd012c4eb5950e9cBruce Allan	 * a single burst write, which will malfunction on some parts.
252b7a9216c5a3205a6d721972bfd012c4eb5950e9cBruce Allan	 * The flushes avoid this.
253b7a9216c5a3205a6d721972bfd012c4eb5950e9cBruce Allan	 */
254b7a9216c5a3205a6d721972bfd012c4eb5950e9cBruce Allan	ew32(RAL(index), rar_low);
255b7a9216c5a3205a6d721972bfd012c4eb5950e9cBruce Allan	e1e_flush();
256b7a9216c5a3205a6d721972bfd012c4eb5950e9cBruce Allan	ew32(RAH(index), rar_high);
257b7a9216c5a3205a6d721972bfd012c4eb5950e9cBruce Allan	e1e_flush();
258bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
259bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
260bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
261bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000_hash_mc_addr - Generate a multicast hash value
262bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
263bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @mc_addr: pointer to a multicast address
264bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
265bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Generates a multicast address hash value which is used to determine
266b2a50e1a1d16d8e377a0c540de36803197bde3fbBruce Allan *  the multicast filter table array address and new table value.
267bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
268bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokstatic u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
269bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
270bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 hash_value, hash_mask;
271bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u8 bit_shift = 0;
272bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
273bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	/* Register count multiplied by bits per register */
274bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	hash_mask = (hw->mac.mta_reg_count * 32) - 1;
275bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
276ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
277ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
278ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * where 0xFF would still fall within the hash mask.
279ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 */
280bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	while (hash_mask >> bit_shift != 0xFF)
281bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		bit_shift++;
282bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
283ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
284ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * The portion of the address that is used for the hash table
285bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * is determined by the mc_filter_type setting.
286bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * The algorithm is such that there is a total of 8 bits of shifting.
287bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * The bit_shift for a mc_filter_type of 0 represents the number of
288bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * left-shifts where the MSB of mc_addr[5] would still fall within
289bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * the hash_mask.  Case 0 does this exactly.  Since there are a total
290bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * of 8 bits of shifting, then mc_addr[4] will shift right the
291bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * remaining number of bits. Thus 8 - bit_shift.  The rest of the
292bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * cases are a variation of this algorithm...essentially raising the
293bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * number of bits to shift mc_addr[5] left, while still keeping the
294bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * 8-bit shifting total.
295ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 *
296ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * For example, given the following Destination MAC Address and an
297bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
298bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * we can see that the bit_shift for case 0 is 4.  These are the hash
299bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * values resulting from each mc_filter_type...
300bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * [0] [1] [2] [3] [4] [5]
301bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * 01  AA  00  12  34  56
302fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan	 * LSB           MSB
303bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 *
304bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
305bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
306bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
307bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
308bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
309bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	switch (hw->mac.mc_filter_type) {
310bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	default:
311bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	case 0:
312bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
313bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	case 1:
314bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		bit_shift += 1;
315bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
316bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	case 2:
317bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		bit_shift += 2;
318bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
319bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	case 3:
320bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		bit_shift += 4;
321bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
322bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
323bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
324bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
325fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan				   (((u16)mc_addr[5]) << bit_shift)));
326bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
327bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return hash_value;
328bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
329bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
330bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
331e2de3eb69c40c01739ce9b154c65e51d94d72966Jeff Kirsher *  e1000e_update_mc_addr_list_generic - Update Multicast addresses
332bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
333bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @mc_addr_list: array of multicast addresses to program
334bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @mc_addr_count: number of multicast addresses to program
335bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
336ab8932f3e8e07df92d6ce3fa41f5af0dda865429Bruce Allan *  Updates entire Multicast Table Array.
337bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  The caller must have a packed mc_addr_list of multicast addresses.
338bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
339e2de3eb69c40c01739ce9b154c65e51d94d72966Jeff Kirshervoid e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
340ab8932f3e8e07df92d6ce3fa41f5af0dda865429Bruce Allan					u8 *mc_addr_list, u32 mc_addr_count)
341bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
342ab8932f3e8e07df92d6ce3fa41f5af0dda865429Bruce Allan	u32 hash_value, hash_bit, hash_reg;
343ab8932f3e8e07df92d6ce3fa41f5af0dda865429Bruce Allan	int i;
344bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
345ab8932f3e8e07df92d6ce3fa41f5af0dda865429Bruce Allan	/* clear mta_shadow */
346ab8932f3e8e07df92d6ce3fa41f5af0dda865429Bruce Allan	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
347bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
348ab8932f3e8e07df92d6ce3fa41f5af0dda865429Bruce Allan	/* update mta_shadow from mc_addr_list */
349fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan	for (i = 0; (u32)i < mc_addr_count; i++) {
350bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
351ab8932f3e8e07df92d6ce3fa41f5af0dda865429Bruce Allan
352a72d2b2cc63994cb8d592a004bf5331be6905814Jesse Brandeburg		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
353a72d2b2cc63994cb8d592a004bf5331be6905814Jesse Brandeburg		hash_bit = hash_value & 0x1F;
354a72d2b2cc63994cb8d592a004bf5331be6905814Jesse Brandeburg
355ab8932f3e8e07df92d6ce3fa41f5af0dda865429Bruce Allan		hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
356ab8932f3e8e07df92d6ce3fa41f5af0dda865429Bruce Allan		mc_addr_list += (ETH_ALEN);
357ab8932f3e8e07df92d6ce3fa41f5af0dda865429Bruce Allan	}
358a72d2b2cc63994cb8d592a004bf5331be6905814Jesse Brandeburg
359ab8932f3e8e07df92d6ce3fa41f5af0dda865429Bruce Allan	/* replace the entire MTA table */
360ab8932f3e8e07df92d6ce3fa41f5af0dda865429Bruce Allan	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
361ab8932f3e8e07df92d6ce3fa41f5af0dda865429Bruce Allan		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
362a72d2b2cc63994cb8d592a004bf5331be6905814Jesse Brandeburg	e1e_flush();
363bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
364bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
365bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
366bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_clear_hw_cntrs_base - Clear base hardware counters
367bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
368bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
369bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Clears the base hardware counters by reading the counter registers.
370bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
371bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokvoid e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
372bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
37399673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(CRCERRS);
37499673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(SYMERRS);
37599673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(MPC);
37699673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(SCC);
37799673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(ECOL);
37899673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(MCC);
37999673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(LATECOL);
38099673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(COLC);
38199673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(DC);
38299673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(SEC);
38399673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(RLEC);
38499673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(XONRXC);
38599673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(XONTXC);
38699673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(XOFFRXC);
38799673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(XOFFTXC);
38899673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(FCRUC);
38999673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(GPRC);
39099673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(BPRC);
39199673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(MPRC);
39299673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(GPTC);
39399673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(GORCL);
39499673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(GORCH);
39599673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(GOTCL);
39699673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(GOTCH);
39799673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(RNBC);
39899673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(RUC);
39999673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(RFC);
40099673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(ROC);
40199673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(RJC);
40299673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(TORL);
40399673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(TORH);
40499673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(TOTL);
40599673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(TOTH);
40699673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(TPR);
40799673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(TPT);
40899673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(MPTC);
40999673d9b5d48c81f2e9fe094c0d9e42815c60b3fBruce Allan	er32(BPTC);
410bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
411bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
412bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
413bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_check_for_copper_link - Check for link (Copper)
414bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
415bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
416bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Checks to see of the link status of the hardware has changed.  If a
417bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  change in link status has been detected, then we read the PHY registers
418bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  to get the current speed/duplex if link exists.
419bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
420bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Koks32 e1000e_check_for_copper_link(struct e1000_hw *hw)
421bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
422bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	struct e1000_mac_info *mac = &hw->mac;
423bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	s32 ret_val;
424bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	bool link;
425bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
426ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
427ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * We only want to go out to the PHY registers to see if Auto-Neg
428bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * has completed and/or if our link status has changed.  The
429bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * get_link_status flag is set upon receiving a Link Status
430bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * Change or Rx Sequence Error interrupt.
431bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
432bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (!mac->get_link_status)
433bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		return 0;
434bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
435ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
436ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * First we want to see if the MII Status Register reports
437bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * link.  If so, then we want to get the current speed/duplex
438bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * of the PHY.
439bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
440bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
441bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (ret_val)
442bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		return ret_val;
443bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
444bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (!link)
445826072555b0dceac44a6e69a0c5be137e829c9d4Bruce Allan		return 0;	/* No link detected */
446bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
447564ea9bba1a1380d5474504bcd943ee84075534fBruce Allan	mac->get_link_status = false;
448bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
449ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
450ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * Check if there was DownShift, must be checked
451ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * immediately after link-up
452ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 */
453bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	e1000e_check_downshift(hw);
454bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
455ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
456ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * If we are forcing speed/duplex, then we simply return since
457bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * we have already determined whether we have link or not.
458bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
4597eb61d81946ccb61726600c6e8ceefcce9844f02Bruce Allan	if (!mac->autoneg)
4607eb61d81946ccb61726600c6e8ceefcce9844f02Bruce Allan		return -E1000_ERR_CONFIG;
461bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
462ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
463ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * Auto-Neg is enabled.  Auto Speed Detection takes care
464bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * of MAC speed/duplex configuration.  So we only need to
465bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * configure Collision Distance in the MAC.
466bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
46757cde7630c1911ea7e8e1561cccfde8096e8bcc7Bruce Allan	mac->ops.config_collision_dist(hw);
468bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
469ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
470ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * Configure Flow Control now that Auto-Neg has completed.
471bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * First, we need to restore the desired flow control
472bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * settings because we may have had to re-autoneg with a
473bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * different link partner.
474bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
475bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ret_val = e1000e_config_fc_after_link_up(hw);
476b1cdfead0e532d7614b5d5b97044df94cc8945aeBruce Allan	if (ret_val)
4773bb99fe226ead584a4db674dab546689f705201fBruce Allan		e_dbg("Error configuring flow control\n");
478bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
479bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return ret_val;
480bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
481bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
482bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
483bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_check_for_fiber_link - Check for link (Fiber)
484bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
485bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
486bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Checks for link up on the hardware.  If link is not up and we have
487bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  a signal, then we need to force link up.
488bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
489bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Koks32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
490bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
491bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	struct e1000_mac_info *mac = &hw->mac;
492bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 rxcw;
493bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 ctrl;
494bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 status;
495bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	s32 ret_val;
496bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
497bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ctrl = er32(CTRL);
498bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	status = er32(STATUS);
499bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	rxcw = er32(RXCW);
500bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
501ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
502ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * If we don't have link (auto-negotiation failed or link partner
503bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * cannot auto-negotiate), the cable is plugged in (we have signal),
504bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * and our link partner is not trying to auto-negotiate with us (we
505bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * are receiving idles or data), we need to force link up. We also
506bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * need to give auto-negotiation time to complete, in case the cable
507bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * was just plugged in. The autoneg_failed flag does this.
508bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
509bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
510668018d74762741c3fe5a54f0eea1bd65dcabd7eBruce Allan	if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
511668018d74762741c3fe5a54f0eea1bd65dcabd7eBruce Allan	    !(rxcw & E1000_RXCW_C)) {
51207914ee3ccbf93ce688f1aaba15d8b01f19c5d77Bruce Allan		if (!mac->autoneg_failed) {
51307914ee3ccbf93ce688f1aaba15d8b01f19c5d77Bruce Allan			mac->autoneg_failed = true;
514bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			return 0;
515bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		}
516af667a29dd3dfc0464f83bac30cc3c63fe5d0206Bruce Allan		e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
517bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
518bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		/* Disable auto-negotiation in the TXCW register */
519bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
520bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
521bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		/* Force link-up and also force full-duplex. */
522bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ctrl = er32(CTRL);
523bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
524bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ew32(CTRL, ctrl);
525bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
526bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		/* Configure Flow Control after forcing link up. */
527bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ret_val = e1000e_config_fc_after_link_up(hw);
528bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if (ret_val) {
5293bb99fe226ead584a4db674dab546689f705201fBruce Allan			e_dbg("Error configuring flow control\n");
530bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			return ret_val;
531bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		}
532bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
533ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		/*
534ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * If we are forcing link and we are receiving /C/ ordered
535bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * sets, re-enable auto-negotiation in the TXCW register
536bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * and disable forced link in the Device Control register
537bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * in an attempt to auto-negotiate with our link partner.
538bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 */
539af667a29dd3dfc0464f83bac30cc3c63fe5d0206Bruce Allan		e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
540bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ew32(TXCW, mac->txcw);
541bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
542bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
543612e244c12215f6f74973ea3b89bff96450dc530Alex Chiang		mac->serdes_has_link = true;
544bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
545bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
546bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
547bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
548bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
549bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
550bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_check_for_serdes_link - Check for link (Serdes)
551bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
552bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
553bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Checks for link up on the hardware.  If link is not up and we have
554bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  a signal, then we need to force link up.
555bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
556bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Koks32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
557bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
558bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	struct e1000_mac_info *mac = &hw->mac;
559bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 rxcw;
560bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 ctrl;
561bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 status;
562bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	s32 ret_val;
563bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
564bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ctrl = er32(CTRL);
565bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	status = er32(STATUS);
566bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	rxcw = er32(RXCW);
567bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
568ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
569ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * If we don't have link (auto-negotiation failed or link partner
570bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * cannot auto-negotiate), and our link partner is not trying to
571bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * auto-negotiate with us (we are receiving idles or data),
572bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * we need to force link up. We also need to give auto-negotiation
573bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * time to complete.
574bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
575bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
576668018d74762741c3fe5a54f0eea1bd65dcabd7eBruce Allan	if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
57707914ee3ccbf93ce688f1aaba15d8b01f19c5d77Bruce Allan		if (!mac->autoneg_failed) {
57807914ee3ccbf93ce688f1aaba15d8b01f19c5d77Bruce Allan			mac->autoneg_failed = true;
579bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			return 0;
580bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		}
581af667a29dd3dfc0464f83bac30cc3c63fe5d0206Bruce Allan		e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
582bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
583bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		/* Disable auto-negotiation in the TXCW register */
584bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
585bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
586bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		/* Force link-up and also force full-duplex. */
587bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ctrl = er32(CTRL);
588bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
589bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ew32(CTRL, ctrl);
590bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
591bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		/* Configure Flow Control after forcing link up. */
592bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ret_val = e1000e_config_fc_after_link_up(hw);
593bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if (ret_val) {
5943bb99fe226ead584a4db674dab546689f705201fBruce Allan			e_dbg("Error configuring flow control\n");
595bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			return ret_val;
596bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		}
597bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
598ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		/*
599ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * If we are forcing link and we are receiving /C/ ordered
600bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * sets, re-enable auto-negotiation in the TXCW register
601bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * and disable forced link in the Device Control register
602bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * in an attempt to auto-negotiate with our link partner.
603bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 */
604af667a29dd3dfc0464f83bac30cc3c63fe5d0206Bruce Allan		e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
605bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ew32(TXCW, mac->txcw);
606bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
607bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
608612e244c12215f6f74973ea3b89bff96450dc530Alex Chiang		mac->serdes_has_link = true;
609bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	} else if (!(E1000_TXCW_ANE & er32(TXCW))) {
610ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		/*
611ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * If we force link for non-auto-negotiation switch, check
612bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * link status based on MAC synchronization for internal
613bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * serdes media type.
614bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 */
615bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		/* SYNCH bit and IV bit are sticky. */
616bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		udelay(10);
61763dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan		rxcw = er32(RXCW);
61863dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan		if (rxcw & E1000_RXCW_SYNCH) {
619bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			if (!(rxcw & E1000_RXCW_IV)) {
62063dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan				mac->serdes_has_link = true;
6213bb99fe226ead584a4db674dab546689f705201fBruce Allan				e_dbg("SERDES: Link up - forced.\n");
622bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			}
623bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		} else {
62463dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan			mac->serdes_has_link = false;
6253bb99fe226ead584a4db674dab546689f705201fBruce Allan			e_dbg("SERDES: Link down - force failed.\n");
626bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		}
627bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
628bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
629bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (E1000_TXCW_ANE & er32(TXCW)) {
630bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		status = er32(STATUS);
63163dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan		if (status & E1000_STATUS_LU) {
6323d3a1676561cfb0dcef0cf5e146ddefbb16f5598Bruce Allan			/* SYNCH bit and IV bit are sticky, so reread rxcw. */
63363dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan			udelay(10);
63463dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan			rxcw = er32(RXCW);
63563dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan			if (rxcw & E1000_RXCW_SYNCH) {
63663dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan				if (!(rxcw & E1000_RXCW_IV)) {
63763dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan					mac->serdes_has_link = true;
638434f1392ae3a3934a33d2d16987d857c97951c3dBruce Allan					e_dbg("SERDES: Link up - autoneg completed successfully.\n");
63963dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan				} else {
64063dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan					mac->serdes_has_link = false;
641434f1392ae3a3934a33d2d16987d857c97951c3dBruce Allan					e_dbg("SERDES: Link down - invalid codewords detected in autoneg.\n");
64263dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan				}
64363dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan			} else {
64463dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan				mac->serdes_has_link = false;
6453bb99fe226ead584a4db674dab546689f705201fBruce Allan				e_dbg("SERDES: Link down - no sync.\n");
64663dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan			}
64763dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan		} else {
64863dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan			mac->serdes_has_link = false;
6493bb99fe226ead584a4db674dab546689f705201fBruce Allan			e_dbg("SERDES: Link down - autoneg failed\n");
65063dcf3d353f32ca7007bfa53a9384f3283076afcBruce Allan		}
651bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
652bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
653bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
654bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
655bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
656bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
657bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000_set_default_fc_generic - Set flow control default values
658bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
659bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
660bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Read the EEPROM for the default values for flow control and store the
661bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  values.
662bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
663bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokstatic s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
664bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
665bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	s32 ret_val;
666bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u16 nvm_data;
667bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
668ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
669ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * Read and store word 0x0F of the EEPROM. This word contains bits
670bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * that determine the hardware's default PAUSE (flow control) mode,
671bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * a bit that determines whether the HW defaults to enabling or
672bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * disabling auto-negotiation, and the direction of the
673bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * SW defined pins. If there is no SW over-ride of the flow
674bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * control setting, then the variable hw->fc will
675bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * be initialized based on a value in the EEPROM.
676bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
677bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
678bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
679bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (ret_val) {
6803bb99fe226ead584a4db674dab546689f705201fBruce Allan		e_dbg("NVM Read Error\n");
681bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		return ret_val;
682bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
683bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
684bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
6855c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan		hw->fc.requested_mode = e1000_fc_none;
686fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan	else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR)
6875c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan		hw->fc.requested_mode = e1000_fc_tx_pause;
688bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	else
6895c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan		hw->fc.requested_mode = e1000_fc_full;
690bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
691bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
692bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
693bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
694bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
6951a46b40fbb1dfd698efbc7a9575aa64aed04d568Bruce Allan *  e1000e_setup_link_generic - Setup flow control and link settings
696bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
697bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
698bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Determines which flow control settings to use, then configures flow
699bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  control.  Calls the appropriate media-specific link configuration
700bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  function.  Assuming the adapter has a valid link partner, a valid link
701bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  should be established.  Assumes the hardware has previously been reset
702bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  and the transmitter and receiver are not enabled.
703bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
7041a46b40fbb1dfd698efbc7a9575aa64aed04d568Bruce Allans32 e1000e_setup_link_generic(struct e1000_hw *hw)
705bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
706bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	s32 ret_val;
707bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
708ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
709ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * In the case of the phy reset being blocked, we already have a link.
710bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * We do not need to set it up again.
711bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
712e831cf2d290e1ecf7825d2ecfabeb0d6733b133dBruce Allan	if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
713bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		return 0;
714bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
715309af40b5f4c2065c9a5f74a360ad3d3b0c9c9cdAuke Kok	/*
7165c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan	 * If requested flow control is set to default, set flow control
7175c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan	 * based on the EEPROM flow control settings.
718309af40b5f4c2065c9a5f74a360ad3d3b0c9c9cdAuke Kok	 */
7195c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan	if (hw->fc.requested_mode == e1000_fc_default) {
720309af40b5f4c2065c9a5f74a360ad3d3b0c9c9cdAuke Kok		ret_val = e1000_set_default_fc_generic(hw);
721309af40b5f4c2065c9a5f74a360ad3d3b0c9c9cdAuke Kok		if (ret_val)
722309af40b5f4c2065c9a5f74a360ad3d3b0c9c9cdAuke Kok			return ret_val;
723309af40b5f4c2065c9a5f74a360ad3d3b0c9c9cdAuke Kok	}
724bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
725ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
7265c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan	 * Save off the requested flow control mode for use later.  Depending
7275c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan	 * on the link partner's capabilities, we may or may not use this mode.
728bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
7295c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan	hw->fc.current_mode = hw->fc.requested_mode;
730bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
731fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
732bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
733bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	/* Call the necessary media_type subroutine to configure the link. */
7340d37678e16fd4db3cf74fa840e7f98a0b7d40742Bruce Allan	ret_val = hw->mac.ops.setup_physical_interface(hw);
735bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (ret_val)
736bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		return ret_val;
737bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
738ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
739ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * Initialize the flow control address, type, and PAUSE timer
740bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * registers to their default values.  This is done even if flow
741bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * control is disabled, because it does not hurt anything to
742bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * initialize these registers.
743bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
7443bb99fe226ead584a4db674dab546689f705201fBruce Allan	e_dbg("Initializing the Flow Control address, type and timer regs\n");
745bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ew32(FCT, FLOW_CONTROL_TYPE);
746bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
747bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
748bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
749318a94d68979cbe9cc98a3050b4b7be2f08513c8Jeff Kirsher	ew32(FCTTV, hw->fc.pause_time);
750bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
751bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return e1000e_set_fc_watermarks(hw);
752bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
753bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
754bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
755bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000_commit_fc_settings_generic - Configure flow control
756bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
757bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
758bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Write the flow control settings to the Transmit Config Word Register (TXCW)
759bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  base on the flow control settings in e1000_mac_info.
760bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
761bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokstatic s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
762bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
763bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	struct e1000_mac_info *mac = &hw->mac;
764bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 txcw;
765bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
766ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
767ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * Check for a software override of the flow control settings, and
768bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * setup the device accordingly.  If auto-negotiation is enabled, then
769bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * software will have to set the "PAUSE" bits to the correct value in
770bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * the Transmit Config Word Register (TXCW) and re-start auto-
771bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * negotiation.  However, if auto-negotiation is disabled, then
772bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * software will have to manually configure the two flow control enable
773bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * bits in the CTRL register.
774bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 *
775bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * The possible values of the "fc" parameter are:
776bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 *      0:  Flow control is completely disabled
777bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 *      1:  Rx flow control is enabled (we can receive pause frames,
778af667a29dd3dfc0464f83bac30cc3c63fe5d0206Bruce Allan	 *          but not send pause frames).
779bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 *      2:  Tx flow control is enabled (we can send pause frames but we
780af667a29dd3dfc0464f83bac30cc3c63fe5d0206Bruce Allan	 *          do not support receiving pause frames).
781ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 *      3:  Both Rx and Tx flow control (symmetric) are enabled.
782bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
7835c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan	switch (hw->fc.current_mode) {
784bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	case e1000_fc_none:
785bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		/* Flow control completely disabled by a software over-ride. */
786bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
787bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
788bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	case e1000_fc_rx_pause:
789ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		/*
790ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * Rx Flow control is enabled and Tx Flow control is disabled
791bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * by a software over-ride. Since there really isn't a way to
792ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * advertise that we are capable of Rx Pause ONLY, we will
793ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * advertise that we support both symmetric and asymmetric Rx
794bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * PAUSE.  Later, we will disable the adapter's ability to send
795bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * PAUSE frames.
796bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 */
797bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
798bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
799bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	case e1000_fc_tx_pause:
800ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		/*
801ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * Tx Flow control is enabled, and Rx Flow control is disabled,
802bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * by a software over-ride.
803bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 */
804bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
805bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
806bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	case e1000_fc_full:
807ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		/*
808ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * Flow control (both Rx and Tx) is enabled by a software
809bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * over-ride.
810bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 */
811bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
812bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
813bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	default:
8143bb99fe226ead584a4db674dab546689f705201fBruce Allan		e_dbg("Flow control param set incorrectly\n");
815bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		return -E1000_ERR_CONFIG;
816bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
817bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
818bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
819bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ew32(TXCW, txcw);
820bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	mac->txcw = txcw;
821bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
822bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
823bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
824bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
825bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
826bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000_poll_fiber_serdes_link_generic - Poll for link up
827bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
828bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
829bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Polls for link up by reading the status register, if link fails to come
830bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  up with auto-negotiation, then the link is forced if a signal is detected.
831bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
832bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokstatic s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
833bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
834bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	struct e1000_mac_info *mac = &hw->mac;
835bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 i, status;
836bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	s32 ret_val;
837bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
838ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
839ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * If we have a signal (the cable is plugged in, or assumed true for
840bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * serdes media) then poll for a "Link-Up" indication in the Device
841bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * Status Register.  Time-out if a link isn't seen in 500 milliseconds
842bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * seconds (Auto-negotiation should complete in less than 500
843bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * milliseconds even if the other end is doing it in SW).
844bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
845bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
8461bba4386ab4f67a53c9649268dd9c83bc6110a9bBruce Allan		usleep_range(10000, 20000);
847bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		status = er32(STATUS);
848bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if (status & E1000_STATUS_LU)
849bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			break;
850bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
851bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (i == FIBER_LINK_UP_LIMIT) {
8523bb99fe226ead584a4db674dab546689f705201fBruce Allan		e_dbg("Never got a valid link from auto-neg!!!\n");
85307914ee3ccbf93ce688f1aaba15d8b01f19c5d77Bruce Allan		mac->autoneg_failed = true;
854ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		/*
855ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * AutoNeg failed to achieve a link, so we'll call
856bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * mac->check_for_link. This routine will force the
857bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * link up if we detect a signal. This will allow us to
858bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * communicate with non-autonegotiating link partners.
859bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 */
860bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ret_val = mac->ops.check_for_link(hw);
861bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if (ret_val) {
8623bb99fe226ead584a4db674dab546689f705201fBruce Allan			e_dbg("Error while checking for link\n");
863bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			return ret_val;
864bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		}
86507914ee3ccbf93ce688f1aaba15d8b01f19c5d77Bruce Allan		mac->autoneg_failed = false;
866bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	} else {
86707914ee3ccbf93ce688f1aaba15d8b01f19c5d77Bruce Allan		mac->autoneg_failed = false;
8683bb99fe226ead584a4db674dab546689f705201fBruce Allan		e_dbg("Valid Link Found\n");
869bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
870bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
871bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
872bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
873bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
874bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
875bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
876bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
877bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
878bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Configures collision distance and flow control for fiber and serdes
879bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  links.  Upon successful setup, poll for link.
880bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
881bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Koks32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
882bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
883bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 ctrl;
884bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	s32 ret_val;
885bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
886bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ctrl = er32(CTRL);
887bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
888bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	/* Take the link out of reset */
889bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ctrl &= ~E1000_CTRL_LRST;
890bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
89157cde7630c1911ea7e8e1561cccfde8096e8bcc7Bruce Allan	hw->mac.ops.config_collision_dist(hw);
892bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
893bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ret_val = e1000_commit_fc_settings_generic(hw);
894bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (ret_val)
895bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		return ret_val;
896bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
897ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
898ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * Since auto-negotiation is enabled, take the link out of reset (the
899bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * link will be in reset, because we previously reset the chip). This
900bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * will restart auto-negotiation.  If auto-negotiation is successful
901bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * then the link-up status bit will be set and the flow control enable
902bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * bits (RFCE and TFCE) will be set according to their negotiated value.
903bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
9043bb99fe226ead584a4db674dab546689f705201fBruce Allan	e_dbg("Auto-negotiation enabled\n");
905bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
906bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ew32(CTRL, ctrl);
907bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	e1e_flush();
9081bba4386ab4f67a53c9649268dd9c83bc6110a9bBruce Allan	usleep_range(1000, 2000);
909bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
910ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
911ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * For these adapters, the SW definable pin 1 is set when the optics
912bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * detect a signal.  If we have a signal, then poll for a "Link-Up"
913bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * indication.
914bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
915318a94d68979cbe9cc98a3050b4b7be2f08513c8Jeff Kirsher	if (hw->phy.media_type == e1000_media_type_internal_serdes ||
916bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	    (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
917bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ret_val = e1000_poll_fiber_serdes_link_generic(hw);
918bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	} else {
9193bb99fe226ead584a4db674dab546689f705201fBruce Allan		e_dbg("No signal detected\n");
920bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
921bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
9222a31b37a8956154df099400ba93cd6898a629c6dBruce Allan	return ret_val;
923bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
924bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
925bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
92657cde7630c1911ea7e8e1561cccfde8096e8bcc7Bruce Allan *  e1000e_config_collision_dist_generic - Configure collision distance
927bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
928bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
929bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Configures the collision distance to the default value and is used
93057cde7630c1911ea7e8e1561cccfde8096e8bcc7Bruce Allan *  during link setup.
931bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
93257cde7630c1911ea7e8e1561cccfde8096e8bcc7Bruce Allanvoid e1000e_config_collision_dist_generic(struct e1000_hw *hw)
933bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
934bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 tctl;
935bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
936bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	tctl = er32(TCTL);
937bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
938bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	tctl &= ~E1000_TCTL_COLD;
939bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
940bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
941bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ew32(TCTL, tctl);
942bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	e1e_flush();
943bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
944bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
945bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
946bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_set_fc_watermarks - Set flow control high/low watermarks
947bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
948bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
949bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Sets the flow control high/low threshold (watermark) registers.  If
950bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  flow control XON frame transmission is enabled, then set XON frame
951ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan *  transmission as well.
952bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
953bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Koks32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
954bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
955bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 fcrtl = 0, fcrth = 0;
956bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
957ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
958ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * Set the flow control receive threshold registers.  Normally,
959bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * these registers will be set to a default threshold that may be
960bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * adjusted later by the driver's runtime code.  However, if the
961bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * ability to transmit pause frames is not enabled, then these
962bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * registers will be set to 0.
963bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
9645c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan	if (hw->fc.current_mode & e1000_fc_tx_pause) {
965ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		/*
966ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * We need to set up the Receive Threshold high and low water
967bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * marks as well as (optionally) enabling the transmission of
968bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * XON frames.
969bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 */
970318a94d68979cbe9cc98a3050b4b7be2f08513c8Jeff Kirsher		fcrtl = hw->fc.low_water;
971b20caa80e8c9b0180defb42678209dc0d6c229d2Bruce Allan		if (hw->fc.send_xon)
972b20caa80e8c9b0180defb42678209dc0d6c229d2Bruce Allan			fcrtl |= E1000_FCRTL_XONE;
973b20caa80e8c9b0180defb42678209dc0d6c229d2Bruce Allan
974318a94d68979cbe9cc98a3050b4b7be2f08513c8Jeff Kirsher		fcrth = hw->fc.high_water;
975bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
976bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ew32(FCRTL, fcrtl);
977bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ew32(FCRTH, fcrth);
978bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
979bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
980bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
981bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
982bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
983bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_force_mac_fc - Force the MAC's flow control settings
984bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
985bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
986bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Force the MAC's flow control settings.  Sets the TFCE and RFCE bits in the
987bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  device control register to reflect the adapter settings.  TFCE and RFCE
988bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  need to be explicitly set by software when a copper PHY is used because
989bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  autonegotiation is managed by the PHY rather than the MAC.  Software must
990bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  also configure these bits when link is forced on a fiber connection.
991bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
992bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Koks32 e1000e_force_mac_fc(struct e1000_hw *hw)
993bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
994bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 ctrl;
995bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
996bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ctrl = er32(CTRL);
997bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
998ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
999ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * Because we didn't get link via the internal auto-negotiation
1000bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * mechanism (we either forced link or we got link via PHY
1001bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * auto-neg), we have to manually enable/disable transmit an
1002bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * receive flow control.
1003bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 *
1004bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * The "Case" statement below enables/disable flow control
10055c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan	 * according to the "hw->fc.current_mode" parameter.
1006bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 *
1007bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * The possible values of the "fc" parameter are:
1008bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 *      0:  Flow control is completely disabled
1009bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 *      1:  Rx flow control is enabled (we can receive pause
1010af667a29dd3dfc0464f83bac30cc3c63fe5d0206Bruce Allan	 *          frames but not send pause frames).
1011bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 *      2:  Tx flow control is enabled (we can send pause frames
1012af667a29dd3dfc0464f83bac30cc3c63fe5d0206Bruce Allan	 *          frames but we do not receive pause frames).
1013ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 *      3:  Both Rx and Tx flow control (symmetric) is enabled.
1014bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 *  other:  No other values should be possible at this point.
1015bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
10163bb99fe226ead584a4db674dab546689f705201fBruce Allan	e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1017bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
10185c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan	switch (hw->fc.current_mode) {
1019bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	case e1000_fc_none:
1020bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1021bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
1022bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	case e1000_fc_rx_pause:
1023bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ctrl &= (~E1000_CTRL_TFCE);
1024bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ctrl |= E1000_CTRL_RFCE;
1025bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
1026bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	case e1000_fc_tx_pause:
1027bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ctrl &= (~E1000_CTRL_RFCE);
1028bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ctrl |= E1000_CTRL_TFCE;
1029bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
1030bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	case e1000_fc_full:
1031bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1032bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
1033bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	default:
10343bb99fe226ead584a4db674dab546689f705201fBruce Allan		e_dbg("Flow control param set incorrectly\n");
1035bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		return -E1000_ERR_CONFIG;
1036bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1037bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1038bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ew32(CTRL, ctrl);
1039bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1040bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
1041bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
1042bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1043bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
1044bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_config_fc_after_link_up - Configures flow control after link
1045bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
1046bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
1047bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Checks the status of auto-negotiation after link up to ensure that the
1048bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  speed and duplex were not forced.  If the link needed to be forced, then
1049bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  flow control needs to be forced also.  If auto-negotiation is enabled
1050bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  and did not fail, then we configure flow control based on our link
1051bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  partner.
1052bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
1053bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Koks32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1054bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
1055bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	struct e1000_mac_info *mac = &hw->mac;
1056bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	s32 ret_val = 0;
1057bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1058bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u16 speed, duplex;
1059bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1060ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
1061ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * Check for the case where we have fiber media and auto-neg failed
1062bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * so we had to force link.  In this case, we need to force the
1063bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * configuration of the MAC to match the "fc" parameter.
1064bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
1065bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (mac->autoneg_failed) {
1066318a94d68979cbe9cc98a3050b4b7be2f08513c8Jeff Kirsher		if (hw->phy.media_type == e1000_media_type_fiber ||
1067318a94d68979cbe9cc98a3050b4b7be2f08513c8Jeff Kirsher		    hw->phy.media_type == e1000_media_type_internal_serdes)
1068bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			ret_val = e1000e_force_mac_fc(hw);
1069bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	} else {
1070318a94d68979cbe9cc98a3050b4b7be2f08513c8Jeff Kirsher		if (hw->phy.media_type == e1000_media_type_copper)
1071bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			ret_val = e1000e_force_mac_fc(hw);
1072bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1073bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1074bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (ret_val) {
10753bb99fe226ead584a4db674dab546689f705201fBruce Allan		e_dbg("Error forcing flow control settings\n");
1076bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		return ret_val;
1077bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1078bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1079ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	/*
1080ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan	 * Check for the case where we have copper media and auto-neg is
1081bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * enabled.  In this case, we need to check and see if Auto-Neg
1082bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * has completed, and if so, how the PHY and link partner has
1083bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 * flow control configured.
1084bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	 */
1085318a94d68979cbe9cc98a3050b4b7be2f08513c8Jeff Kirsher	if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1086ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		/*
1087ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * Read the MII Status Register and check to see if AutoNeg
1088bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * has completed.  We read this twice because this reg has
1089bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * some "sticky" (latched) bits.
1090bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 */
1091bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1092bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if (ret_val)
1093bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			return ret_val;
1094bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1095bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if (ret_val)
1096bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			return ret_val;
1097bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1098bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1099434f1392ae3a3934a33d2d16987d857c97951c3dBruce Allan			e_dbg("Copper PHY and Auto Neg has not completed.\n");
1100bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			return ret_val;
1101bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		}
1102bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1103ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		/*
1104ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * The AutoNeg process has completed, so we now need to
1105bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * read both the Auto Negotiation Advertisement
1106bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * Register (Address 4) and the Auto_Negotiation Base
1107bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * Page Ability Register (Address 5) to determine how
1108bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * flow control was negotiated.
1109bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 */
1110bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
1111bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if (ret_val)
1112bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			return ret_val;
1113482fed85e64958f678a138a4b5f8891190d2b169Bruce Allan		ret_val =
1114482fed85e64958f678a138a4b5f8891190d2b169Bruce Allan		    e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
1115bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if (ret_val)
1116bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			return ret_val;
1117bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1118ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		/*
1119ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * Two bits in the Auto Negotiation Advertisement Register
1120bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * (Address 4) and two bits in the Auto Negotiation Base
1121bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * Page Ability Register (Address 5) determine flow control
1122bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * for both the PHY and the link partner.  The following
1123bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1124bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * 1999, describes these PAUSE resolution bits and how flow
1125bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * control is determined based upon these settings.
1126bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * NOTE:  DC = Don't Care
1127bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *
1128bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *   LOCAL DEVICE  |   LINK PARTNER
1129bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1130bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *-------|---------|-------|---------|--------------------
1131bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *   0   |    0    |  DC   |   DC    | e1000_fc_none
1132bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *   0   |    1    |   0   |   DC    | e1000_fc_none
1133bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *   0   |    1    |   1   |    0    | e1000_fc_none
1134bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1135bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *   1   |    0    |   0   |   DC    | e1000_fc_none
1136bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1137bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *   1   |    1    |   0   |    0    | e1000_fc_none
1138bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1139bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *
1140ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * Are both PAUSE bits set to 1?  If so, this implies
1141bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * Symmetric Flow Control is enabled at both ends.  The
1142bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * ASM_DIR bits are irrelevant per the spec.
1143bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *
1144bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * For Symmetric Flow Control:
1145bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *
1146bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *   LOCAL DEVICE  |   LINK PARTNER
1147bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1148bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *-------|---------|-------|---------|--------------------
1149bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *   1   |   DC    |   1   |   DC    | E1000_fc_full
1150bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *
1151bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 */
1152bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1153bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1154ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan			/*
1155ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan			 * Now we need to check if the user selected Rx ONLY
1156bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			 * of pause frames.  In this case, we had to advertise
1157ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan			 * FULL flow control because we could not advertise Rx
1158bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			 * ONLY. Hence, we must now check to see if we need to
1159d64a6f4dca0b45495dd5be8116b618d9cc004eeaBruce Allan			 * turn OFF the TRANSMISSION of PAUSE frames.
1160bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			 */
11615c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan			if (hw->fc.requested_mode == e1000_fc_full) {
11625c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan				hw->fc.current_mode = e1000_fc_full;
1163434f1392ae3a3934a33d2d16987d857c97951c3dBruce Allan				e_dbg("Flow Control = FULL.\n");
1164bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			} else {
11655c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan				hw->fc.current_mode = e1000_fc_rx_pause;
1166434f1392ae3a3934a33d2d16987d857c97951c3dBruce Allan				e_dbg("Flow Control = Rx PAUSE frames only.\n");
1167bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			}
1168bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		}
1169ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		/*
1170ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * For receiving PAUSE frames ONLY.
1171bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *
1172bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *   LOCAL DEVICE  |   LINK PARTNER
1173bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1174bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *-------|---------|-------|---------|--------------------
1175bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1176bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 */
1177bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1178fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan			 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1179fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan			 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1180fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan			 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
11815c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan			hw->fc.current_mode = e1000_fc_tx_pause;
1182434f1392ae3a3934a33d2d16987d857c97951c3dBruce Allan			e_dbg("Flow Control = Tx PAUSE frames only.\n");
1183bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		}
1184ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		/*
1185ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * For transmitting PAUSE frames ONLY.
1186bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *
1187bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *   LOCAL DEVICE  |   LINK PARTNER
1188bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1189bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *-------|---------|-------|---------|--------------------
1190bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1191bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 */
1192bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1193bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1194bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1195bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
11965c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan			hw->fc.current_mode = e1000_fc_rx_pause;
1197434f1392ae3a3934a33d2d16987d857c97951c3dBruce Allan			e_dbg("Flow Control = Rx PAUSE frames only.\n");
1198de92d84ec2305c490aa1db33f6e40680f8c236a8Jesse Brandeburg		} else {
1199de92d84ec2305c490aa1db33f6e40680f8c236a8Jesse Brandeburg			/*
1200de92d84ec2305c490aa1db33f6e40680f8c236a8Jesse Brandeburg			 * Per the IEEE spec, at this point flow control
1201de92d84ec2305c490aa1db33f6e40680f8c236a8Jesse Brandeburg			 * should be disabled.
1202de92d84ec2305c490aa1db33f6e40680f8c236a8Jesse Brandeburg			 */
12035c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan			hw->fc.current_mode = e1000_fc_none;
1204434f1392ae3a3934a33d2d16987d857c97951c3dBruce Allan			e_dbg("Flow Control = NONE.\n");
1205bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		}
1206bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1207ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		/*
1208ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * Now we need to do one last check...  If we auto-
1209bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * negotiated to HALF DUPLEX, flow control should not be
1210bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * enabled per IEEE 802.3 spec.
1211bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 */
1212bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1213bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if (ret_val) {
12143bb99fe226ead584a4db674dab546689f705201fBruce Allan			e_dbg("Error getting link speed and duplex\n");
1215bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			return ret_val;
1216bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		}
1217bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1218bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if (duplex == HALF_DUPLEX)
12195c48ef3e2028677a890d46d9a38b19174274f2e9Bruce Allan			hw->fc.current_mode = e1000_fc_none;
1220bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1221ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		/*
1222ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * Now we call a subroutine to actually force the MAC
1223bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 * controller to use the correct flow control settings.
1224bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		 */
1225bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ret_val = e1000e_force_mac_fc(hw);
1226bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if (ret_val) {
12273bb99fe226ead584a4db674dab546689f705201fBruce Allan			e_dbg("Error forcing flow control settings\n");
1228bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			return ret_val;
1229bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		}
1230bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1231bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1232bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
1233bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
1234bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1235bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
1236489815ce224e75c2fcd5ebdfaa740d7f9a4f20d3Auke Kok *  e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1237bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
1238bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @speed: stores the current speed
1239bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @duplex: stores the current duplex
1240bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
1241bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Read the status register for the current speed/duplex and store the current
1242bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  speed and duplex for copper connections.
1243bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
1244fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allans32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
1245fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan				       u16 *duplex)
1246bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
1247bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 status;
1248bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1249bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	status = er32(STATUS);
12502c73e1fe94b1962ae5df7618519c18526e9d9072Joe Perches	if (status & E1000_STATUS_SPEED_1000)
1251bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		*speed = SPEED_1000;
12522c73e1fe94b1962ae5df7618519c18526e9d9072Joe Perches	else if (status & E1000_STATUS_SPEED_100)
1253bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		*speed = SPEED_100;
12542c73e1fe94b1962ae5df7618519c18526e9d9072Joe Perches	else
1255bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		*speed = SPEED_10;
1256bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
12572c73e1fe94b1962ae5df7618519c18526e9d9072Joe Perches	if (status & E1000_STATUS_FD)
1258bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		*duplex = FULL_DUPLEX;
12592c73e1fe94b1962ae5df7618519c18526e9d9072Joe Perches	else
1260bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		*duplex = HALF_DUPLEX;
12612c73e1fe94b1962ae5df7618519c18526e9d9072Joe Perches
12622c73e1fe94b1962ae5df7618519c18526e9d9072Joe Perches	e_dbg("%u Mbps, %s Duplex\n",
12632c73e1fe94b1962ae5df7618519c18526e9d9072Joe Perches	      *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10,
12642c73e1fe94b1962ae5df7618519c18526e9d9072Joe Perches	      *duplex == FULL_DUPLEX ? "Full" : "Half");
1265bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1266bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
1267bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
1268bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1269bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
1270489815ce224e75c2fcd5ebdfaa740d7f9a4f20d3Auke Kok *  e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1271bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
1272bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @speed: stores the current speed
1273bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @duplex: stores the current duplex
1274bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
1275bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Sets the speed and duplex to gigabit full duplex (the only possible option)
1276bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  for fiber/serdes links.
1277bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
1278fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allans32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed,
1279fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan					     u16 *duplex)
1280bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
1281bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	*speed = SPEED_1000;
1282bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	*duplex = FULL_DUPLEX;
1283bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1284bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
1285bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
1286bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1287bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
1288bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_get_hw_semaphore - Acquire hardware semaphore
1289bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
1290bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
1291bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Acquire the HW semaphore to access the PHY or NVM
1292bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
1293bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Koks32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1294bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
1295bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 swsm;
1296bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	s32 timeout = hw->nvm.word_size + 1;
1297bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	s32 i = 0;
1298bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1299bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	/* Get the SW semaphore */
1300bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	while (i < timeout) {
1301bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		swsm = er32(SWSM);
1302bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if (!(swsm & E1000_SWSM_SMBI))
1303bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			break;
1304bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1305bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		udelay(50);
1306bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		i++;
1307bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1308bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1309bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (i == timeout) {
13103bb99fe226ead584a4db674dab546689f705201fBruce Allan		e_dbg("Driver can't access device - SMBI bit is set.\n");
1311bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		return -E1000_ERR_NVM;
1312bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1313bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1314bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	/* Get the FW semaphore. */
1315bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	for (i = 0; i < timeout; i++) {
1316bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		swsm = er32(SWSM);
1317bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1318bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1319bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		/* Semaphore acquired if bit latched */
1320bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if (er32(SWSM) & E1000_SWSM_SWESMBI)
1321bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			break;
1322bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1323bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		udelay(50);
1324bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1325bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1326bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (i == timeout) {
1327bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		/* Release semaphores */
1328bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		e1000e_put_hw_semaphore(hw);
13293bb99fe226ead584a4db674dab546689f705201fBruce Allan		e_dbg("Driver can't access the NVM\n");
1330bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		return -E1000_ERR_NVM;
1331bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1332bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1333bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
1334bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
1335bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1336bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
1337bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_put_hw_semaphore - Release hardware semaphore
1338bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
1339bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
1340bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Release hardware semaphore used to access the PHY or NVM
1341bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
1342bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokvoid e1000e_put_hw_semaphore(struct e1000_hw *hw)
1343bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
1344bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 swsm;
1345bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1346bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	swsm = er32(SWSM);
1347bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1348bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ew32(SWSM, swsm);
1349bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
1350bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1351bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
1352bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_get_auto_rd_done - Check for auto read completion
1353bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
1354bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
1355bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Check EEPROM for Auto Read done bit.
1356bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
1357bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Koks32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1358bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
1359bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	s32 i = 0;
1360bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1361bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	while (i < AUTO_READ_DONE_TIMEOUT) {
1362bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if (er32(EECD) & E1000_EECD_AUTO_RD)
1363bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			break;
13641bba4386ab4f67a53c9649268dd9c83bc6110a9bBruce Allan		usleep_range(1000, 2000);
1365bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		i++;
1366bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1367bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1368bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (i == AUTO_READ_DONE_TIMEOUT) {
13693bb99fe226ead584a4db674dab546689f705201fBruce Allan		e_dbg("Auto read by HW from NVM has not completed.\n");
1370bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		return -E1000_ERR_RESET;
1371bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1372bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1373bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
1374bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
1375bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1376bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
1377bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_valid_led_default - Verify a valid default LED config
1378bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
1379bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @data: pointer to the NVM (EEPROM)
1380bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
1381bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Read the EEPROM for the current default LED configuration.  If the
1382bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  LED configuration is not valid, set to a valid LED configuration.
1383bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
1384bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Koks32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1385bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
1386bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	s32 ret_val;
1387bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1388bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1389bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (ret_val) {
13903bb99fe226ead584a4db674dab546689f705201fBruce Allan		e_dbg("NVM Read Error\n");
1391bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		return ret_val;
1392bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1393bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1394bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1395bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		*data = ID_LED_DEFAULT;
1396bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1397bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
1398bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
1399bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1400bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
1401d1964eb138901286a170de8ed422efd227dd4dafBruce Allan *  e1000e_id_led_init_generic -
1402bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
1403bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
1404bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
1405d1964eb138901286a170de8ed422efd227dd4dafBruce Allans32 e1000e_id_led_init_generic(struct e1000_hw *hw)
1406bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
1407bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	struct e1000_mac_info *mac = &hw->mac;
1408bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	s32 ret_val;
1409bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	const u32 ledctl_mask = 0x000000FF;
1410bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1411bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1412bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u16 data, i, temp;
1413bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	const u16 led_mask = 0x0F;
1414bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1415bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1416bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (ret_val)
1417bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		return ret_val;
1418bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1419bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	mac->ledctl_default = er32(LEDCTL);
1420bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	mac->ledctl_mode1 = mac->ledctl_default;
1421bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	mac->ledctl_mode2 = mac->ledctl_default;
1422bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1423bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	for (i = 0; i < 4; i++) {
1424bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		temp = (data >> (i << 2)) & led_mask;
1425bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		switch (temp) {
1426bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		case ID_LED_ON1_DEF2:
1427bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		case ID_LED_ON1_ON2:
1428bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		case ID_LED_ON1_OFF2:
1429bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1430bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			mac->ledctl_mode1 |= ledctl_on << (i << 3);
1431bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			break;
1432bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		case ID_LED_OFF1_DEF2:
1433bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		case ID_LED_OFF1_ON2:
1434bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		case ID_LED_OFF1_OFF2:
1435bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1436bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			mac->ledctl_mode1 |= ledctl_off << (i << 3);
1437bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			break;
1438bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		default:
1439bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			/* Do nothing */
1440bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			break;
1441bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		}
1442bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		switch (temp) {
1443bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		case ID_LED_DEF1_ON2:
1444bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		case ID_LED_ON1_ON2:
1445bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		case ID_LED_OFF1_ON2:
1446bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1447bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			mac->ledctl_mode2 |= ledctl_on << (i << 3);
1448bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			break;
1449bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		case ID_LED_DEF1_OFF2:
1450bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		case ID_LED_ON1_OFF2:
1451bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		case ID_LED_OFF1_OFF2:
1452bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1453bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			mac->ledctl_mode2 |= ledctl_off << (i << 3);
1454bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			break;
1455bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		default:
1456bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			/* Do nothing */
1457bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			break;
1458bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		}
1459bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1460bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1461bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
1462bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
1463bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1464bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
1465a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan *  e1000e_setup_led_generic - Configures SW controllable LED
1466a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan *  @hw: pointer to the HW structure
1467a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan *
1468a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan *  This prepares the SW controllable LED for use and saves the current state
1469a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan *  of the LED so it can be later restored.
1470a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan **/
1471a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allans32 e1000e_setup_led_generic(struct e1000_hw *hw)
1472a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan{
1473a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan	u32 ledctl;
1474a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan
1475b1cdfead0e532d7614b5d5b97044df94cc8945aeBruce Allan	if (hw->mac.ops.setup_led != e1000e_setup_led_generic)
1476a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan		return -E1000_ERR_CONFIG;
1477a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan
1478a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan	if (hw->phy.media_type == e1000_media_type_fiber) {
1479a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan		ledctl = er32(LEDCTL);
1480a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan		hw->mac.ledctl_default = ledctl;
1481a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan		/* Turn off LED0 */
1482fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan		ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1483fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan			    E1000_LEDCTL_LED0_MODE_MASK);
1484a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan		ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1485fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan			   E1000_LEDCTL_LED0_MODE_SHIFT);
1486a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan		ew32(LEDCTL, ledctl);
1487a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan	} else if (hw->phy.media_type == e1000_media_type_copper) {
1488a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan		ew32(LEDCTL, hw->mac.ledctl_mode1);
1489a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan	}
1490a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan
1491a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan	return 0;
1492a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan}
1493a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan
1494a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan/**
1495bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_cleanup_led_generic - Set LED config to default operation
1496bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
1497bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
1498bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Remove the current LED configuration and set the LED configuration
1499bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  to the default value, saved from the EEPROM.
1500bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
1501bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Koks32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1502bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
1503bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ew32(LEDCTL, hw->mac.ledctl_default);
1504bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
1505bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
1506bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1507bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
1508dbf80dcbd8ca0c50f343401fedd2d6200cb8097eBruce Allan *  e1000e_blink_led_generic - Blink LED
1509bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
1510bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
1511489815ce224e75c2fcd5ebdfaa740d7f9a4f20d3Auke Kok *  Blink the LEDs which are set to be on.
1512bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
1513dbf80dcbd8ca0c50f343401fedd2d6200cb8097eBruce Allans32 e1000e_blink_led_generic(struct e1000_hw *hw)
1514bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
1515bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 ledctl_blink = 0;
1516bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 i;
1517bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1518318a94d68979cbe9cc98a3050b4b7be2f08513c8Jeff Kirsher	if (hw->phy.media_type == e1000_media_type_fiber) {
1519bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		/* always blink LED0 for PCI-E fiber */
1520bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1521fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan		    (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1522bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	} else {
1523ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		/*
1524ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * set the blink bit for each LED that's "on" (0x0E)
1525ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 * in ledctl_mode2
1526ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan		 */
1527bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ledctl_blink = hw->mac.ledctl_mode2;
1528bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		for (i = 0; i < 4; i++)
1529bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1530bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			    E1000_LEDCTL_MODE_LED_ON)
1531bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok				ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1532bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok						 (i * 8));
1533bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1534bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1535bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ew32(LEDCTL, ledctl_blink);
1536bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1537bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
1538bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
1539bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1540bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
1541bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_led_on_generic - Turn LED on
1542bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
1543bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
1544bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Turn LED on.
1545bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
1546bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Koks32 e1000e_led_on_generic(struct e1000_hw *hw)
1547bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
1548bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 ctrl;
1549bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1550318a94d68979cbe9cc98a3050b4b7be2f08513c8Jeff Kirsher	switch (hw->phy.media_type) {
1551bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	case e1000_media_type_fiber:
1552bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ctrl = er32(CTRL);
1553bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ctrl &= ~E1000_CTRL_SWDPIN0;
1554bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ctrl |= E1000_CTRL_SWDPIO0;
1555bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ew32(CTRL, ctrl);
1556bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
1557bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	case e1000_media_type_copper:
1558bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ew32(LEDCTL, hw->mac.ledctl_mode2);
1559bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
1560bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	default:
1561bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
1562bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1563bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1564bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
1565bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
1566bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1567bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
1568bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_led_off_generic - Turn LED off
1569bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
1570bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
1571bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Turn LED off.
1572bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
1573bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Koks32 e1000e_led_off_generic(struct e1000_hw *hw)
1574bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
1575bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 ctrl;
1576bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1577318a94d68979cbe9cc98a3050b4b7be2f08513c8Jeff Kirsher	switch (hw->phy.media_type) {
1578bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	case e1000_media_type_fiber:
1579bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ctrl = er32(CTRL);
1580bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ctrl |= E1000_CTRL_SWDPIN0;
1581bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ctrl |= E1000_CTRL_SWDPIO0;
1582bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ew32(CTRL, ctrl);
1583bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
1584bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	case e1000_media_type_copper:
1585bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ew32(LEDCTL, hw->mac.ledctl_mode1);
1586bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
1587bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	default:
1588bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		break;
1589bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1590bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1591bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
1592bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
1593bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1594bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
1595bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1596bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
1597bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @no_snoop: bitmap of snoop events
1598bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
1599bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1600bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
1601bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokvoid e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1602bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
1603bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 gcr;
1604bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1605bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (no_snoop) {
1606bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		gcr = er32(GCR);
1607bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		gcr &= ~(PCIE_NO_SNOOP_ALL);
1608bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		gcr |= no_snoop;
1609bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		ew32(GCR, gcr);
1610bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1611bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
1612bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1613bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
1614bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_disable_pcie_master - Disables PCI-express master access
1615bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
1616bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
1617bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Returns 0 if successful, else returns -10
1618489815ce224e75c2fcd5ebdfaa740d7f9a4f20d3Auke Kok *  (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1619bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  the master requests to be disabled.
1620bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
1621bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Disables PCI-Express master access and verifies there are no pending
1622bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  requests.
1623bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
1624bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Koks32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1625bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
1626bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	u32 ctrl;
1627bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	s32 timeout = MASTER_DISABLE_TIMEOUT;
1628bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1629bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ctrl = er32(CTRL);
1630bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1631bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ew32(CTRL, ctrl);
1632bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1633bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	while (timeout) {
1634fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan		if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
1635bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			break;
1636bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		udelay(100);
1637bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		timeout--;
1638bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1639bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1640bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if (!timeout) {
16413bb99fe226ead584a4db674dab546689f705201fBruce Allan		e_dbg("Master requests are pending.\n");
1642bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		return -E1000_ERR_MASTER_REQUESTS_PENDING;
1643bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1644bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1645bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	return 0;
1646bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
1647bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1648bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
1649bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1650bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
1651bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
1652bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Reset the Adaptive Interframe Spacing throttle to default values.
1653bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
1654bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokvoid e1000e_reset_adaptive(struct e1000_hw *hw)
1655bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
1656bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	struct e1000_mac_info *mac = &hw->mac;
1657bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1658f464ba87fe7f346e270239354eb0d38f7a3b3e6bBruce Allan	if (!mac->adaptive_ifs) {
1659f464ba87fe7f346e270239354eb0d38f7a3b3e6bBruce Allan		e_dbg("Not in Adaptive IFS mode!\n");
1660fe1e980f24697edb7d4e17cd74bbeae4a0388525Bruce Allan		return;
1661f464ba87fe7f346e270239354eb0d38f7a3b3e6bBruce Allan	}
1662f464ba87fe7f346e270239354eb0d38f7a3b3e6bBruce Allan
1663bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	mac->current_ifs_val = 0;
1664bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	mac->ifs_min_val = IFS_MIN;
1665bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	mac->ifs_max_val = IFS_MAX;
1666bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	mac->ifs_step_size = IFS_STEP;
1667bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	mac->ifs_ratio = IFS_RATIO;
1668bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1669564ea9bba1a1380d5474504bcd943ee84075534fBruce Allan	mac->in_ifs_mode = false;
1670bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	ew32(AIT, 0);
1671bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
1672bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1673bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/**
1674bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  e1000e_update_adaptive - Update Adaptive Interframe Spacing
1675bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  @hw: pointer to the HW structure
1676bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *
1677bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  Update the Adaptive Interframe Spacing Throttle value based on the
1678bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok *  time between transmitted packets and time between collisions.
1679bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok **/
1680bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokvoid e1000e_update_adaptive(struct e1000_hw *hw)
1681bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{
1682bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	struct e1000_mac_info *mac = &hw->mac;
1683bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok
1684f464ba87fe7f346e270239354eb0d38f7a3b3e6bBruce Allan	if (!mac->adaptive_ifs) {
1685f464ba87fe7f346e270239354eb0d38f7a3b3e6bBruce Allan		e_dbg("Not in Adaptive IFS mode!\n");
1686fe1e980f24697edb7d4e17cd74bbeae4a0388525Bruce Allan		return;
1687f464ba87fe7f346e270239354eb0d38f7a3b3e6bBruce Allan	}
1688f464ba87fe7f346e270239354eb0d38f7a3b3e6bBruce Allan
1689bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1690bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1691564ea9bba1a1380d5474504bcd943ee84075534fBruce Allan			mac->in_ifs_mode = true;
1692bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			if (mac->current_ifs_val < mac->ifs_max_val) {
1693bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok				if (!mac->current_ifs_val)
1694bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok					mac->current_ifs_val = mac->ifs_min_val;
1695bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok				else
1696bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok					mac->current_ifs_val +=
1697fe2ddfb510f9d305a6654c7538c5c8faf326a16cBruce Allan					    mac->ifs_step_size;
1698ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan				ew32(AIT, mac->current_ifs_val);
1699bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			}
1700bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		}
1701bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	} else {
1702bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		if (mac->in_ifs_mode &&
1703bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		    (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1704bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			mac->current_ifs_val = 0;
1705564ea9bba1a1380d5474504bcd943ee84075534fBruce Allan			mac->in_ifs_mode = false;
1706bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok			ew32(AIT, 0);
1707bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok		}
1708bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok	}
1709bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}
1710