e1000_phy.c revision d5a0e3640c05b7d07c548f9f8f986dbb87cfad98
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2011 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28#include <linux/if_ether.h> 29#include <linux/delay.h> 30 31#include "e1000_mac.h" 32#include "e1000_phy.h" 33 34static s32 igb_phy_setup_autoneg(struct e1000_hw *hw); 35static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, 36 u16 *phy_ctrl); 37static s32 igb_wait_autoneg(struct e1000_hw *hw); 38 39/* Cable length tables */ 40static const u16 e1000_m88_cable_length_table[] = 41 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 42#define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 43 (sizeof(e1000_m88_cable_length_table) / \ 44 sizeof(e1000_m88_cable_length_table[0])) 45 46static const u16 e1000_igp_2_cable_length_table[] = 47 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 48 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 49 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 50 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 51 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 52 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 53 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 54 104, 109, 114, 118, 121, 124}; 55#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 56 (sizeof(e1000_igp_2_cable_length_table) / \ 57 sizeof(e1000_igp_2_cable_length_table[0])) 58 59/** 60 * igb_check_reset_block - Check if PHY reset is blocked 61 * @hw: pointer to the HW structure 62 * 63 * Read the PHY management control register and check whether a PHY reset 64 * is blocked. If a reset is not blocked return 0, otherwise 65 * return E1000_BLK_PHY_RESET (12). 66 **/ 67s32 igb_check_reset_block(struct e1000_hw *hw) 68{ 69 u32 manc; 70 71 manc = rd32(E1000_MANC); 72 73 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 74 E1000_BLK_PHY_RESET : 0; 75} 76 77/** 78 * igb_get_phy_id - Retrieve the PHY ID and revision 79 * @hw: pointer to the HW structure 80 * 81 * Reads the PHY registers and stores the PHY ID and possibly the PHY 82 * revision in the hardware structure. 83 **/ 84s32 igb_get_phy_id(struct e1000_hw *hw) 85{ 86 struct e1000_phy_info *phy = &hw->phy; 87 s32 ret_val = 0; 88 u16 phy_id; 89 90 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 91 if (ret_val) 92 goto out; 93 94 phy->id = (u32)(phy_id << 16); 95 udelay(20); 96 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 97 if (ret_val) 98 goto out; 99 100 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 101 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 102 103out: 104 return ret_val; 105} 106 107/** 108 * igb_phy_reset_dsp - Reset PHY DSP 109 * @hw: pointer to the HW structure 110 * 111 * Reset the digital signal processor. 112 **/ 113static s32 igb_phy_reset_dsp(struct e1000_hw *hw) 114{ 115 s32 ret_val = 0; 116 117 if (!(hw->phy.ops.write_reg)) 118 goto out; 119 120 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 121 if (ret_val) 122 goto out; 123 124 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 125 126out: 127 return ret_val; 128} 129 130/** 131 * igb_read_phy_reg_mdic - Read MDI control register 132 * @hw: pointer to the HW structure 133 * @offset: register offset to be read 134 * @data: pointer to the read data 135 * 136 * Reads the MDI control regsiter in the PHY at offset and stores the 137 * information read to data. 138 **/ 139s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 140{ 141 struct e1000_phy_info *phy = &hw->phy; 142 u32 i, mdic = 0; 143 s32 ret_val = 0; 144 145 if (offset > MAX_PHY_REG_ADDRESS) { 146 hw_dbg("PHY Address %d is out of range\n", offset); 147 ret_val = -E1000_ERR_PARAM; 148 goto out; 149 } 150 151 /* 152 * Set up Op-code, Phy Address, and register offset in the MDI 153 * Control register. The MAC will take care of interfacing with the 154 * PHY to retrieve the desired data. 155 */ 156 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 157 (phy->addr << E1000_MDIC_PHY_SHIFT) | 158 (E1000_MDIC_OP_READ)); 159 160 wr32(E1000_MDIC, mdic); 161 162 /* 163 * Poll the ready bit to see if the MDI read completed 164 * Increasing the time out as testing showed failures with 165 * the lower time out 166 */ 167 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 168 udelay(50); 169 mdic = rd32(E1000_MDIC); 170 if (mdic & E1000_MDIC_READY) 171 break; 172 } 173 if (!(mdic & E1000_MDIC_READY)) { 174 hw_dbg("MDI Read did not complete\n"); 175 ret_val = -E1000_ERR_PHY; 176 goto out; 177 } 178 if (mdic & E1000_MDIC_ERROR) { 179 hw_dbg("MDI Error\n"); 180 ret_val = -E1000_ERR_PHY; 181 goto out; 182 } 183 *data = (u16) mdic; 184 185out: 186 return ret_val; 187} 188 189/** 190 * igb_write_phy_reg_mdic - Write MDI control register 191 * @hw: pointer to the HW structure 192 * @offset: register offset to write to 193 * @data: data to write to register at offset 194 * 195 * Writes data to MDI control register in the PHY at offset. 196 **/ 197s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 198{ 199 struct e1000_phy_info *phy = &hw->phy; 200 u32 i, mdic = 0; 201 s32 ret_val = 0; 202 203 if (offset > MAX_PHY_REG_ADDRESS) { 204 hw_dbg("PHY Address %d is out of range\n", offset); 205 ret_val = -E1000_ERR_PARAM; 206 goto out; 207 } 208 209 /* 210 * Set up Op-code, Phy Address, and register offset in the MDI 211 * Control register. The MAC will take care of interfacing with the 212 * PHY to retrieve the desired data. 213 */ 214 mdic = (((u32)data) | 215 (offset << E1000_MDIC_REG_SHIFT) | 216 (phy->addr << E1000_MDIC_PHY_SHIFT) | 217 (E1000_MDIC_OP_WRITE)); 218 219 wr32(E1000_MDIC, mdic); 220 221 /* 222 * Poll the ready bit to see if the MDI read completed 223 * Increasing the time out as testing showed failures with 224 * the lower time out 225 */ 226 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 227 udelay(50); 228 mdic = rd32(E1000_MDIC); 229 if (mdic & E1000_MDIC_READY) 230 break; 231 } 232 if (!(mdic & E1000_MDIC_READY)) { 233 hw_dbg("MDI Write did not complete\n"); 234 ret_val = -E1000_ERR_PHY; 235 goto out; 236 } 237 if (mdic & E1000_MDIC_ERROR) { 238 hw_dbg("MDI Error\n"); 239 ret_val = -E1000_ERR_PHY; 240 goto out; 241 } 242 243out: 244 return ret_val; 245} 246 247/** 248 * igb_read_phy_reg_i2c - Read PHY register using i2c 249 * @hw: pointer to the HW structure 250 * @offset: register offset to be read 251 * @data: pointer to the read data 252 * 253 * Reads the PHY register at offset using the i2c interface and stores the 254 * retrieved information in data. 255 **/ 256s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 257{ 258 struct e1000_phy_info *phy = &hw->phy; 259 u32 i, i2ccmd = 0; 260 261 262 /* 263 * Set up Op-code, Phy Address, and register address in the I2CCMD 264 * register. The MAC will take care of interfacing with the 265 * PHY to retrieve the desired data. 266 */ 267 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 268 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 269 (E1000_I2CCMD_OPCODE_READ)); 270 271 wr32(E1000_I2CCMD, i2ccmd); 272 273 /* Poll the ready bit to see if the I2C read completed */ 274 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 275 udelay(50); 276 i2ccmd = rd32(E1000_I2CCMD); 277 if (i2ccmd & E1000_I2CCMD_READY) 278 break; 279 } 280 if (!(i2ccmd & E1000_I2CCMD_READY)) { 281 hw_dbg("I2CCMD Read did not complete\n"); 282 return -E1000_ERR_PHY; 283 } 284 if (i2ccmd & E1000_I2CCMD_ERROR) { 285 hw_dbg("I2CCMD Error bit set\n"); 286 return -E1000_ERR_PHY; 287 } 288 289 /* Need to byte-swap the 16-bit value. */ 290 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 291 292 return 0; 293} 294 295/** 296 * igb_write_phy_reg_i2c - Write PHY register using i2c 297 * @hw: pointer to the HW structure 298 * @offset: register offset to write to 299 * @data: data to write at register offset 300 * 301 * Writes the data to PHY register at the offset using the i2c interface. 302 **/ 303s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 304{ 305 struct e1000_phy_info *phy = &hw->phy; 306 u32 i, i2ccmd = 0; 307 u16 phy_data_swapped; 308 309 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/ 310 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { 311 hw_dbg("PHY I2C Address %d is out of range.\n", 312 hw->phy.addr); 313 return -E1000_ERR_CONFIG; 314 } 315 316 /* Swap the data bytes for the I2C interface */ 317 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 318 319 /* 320 * Set up Op-code, Phy Address, and register address in the I2CCMD 321 * register. The MAC will take care of interfacing with the 322 * PHY to retrieve the desired data. 323 */ 324 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 325 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 326 E1000_I2CCMD_OPCODE_WRITE | 327 phy_data_swapped); 328 329 wr32(E1000_I2CCMD, i2ccmd); 330 331 /* Poll the ready bit to see if the I2C read completed */ 332 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 333 udelay(50); 334 i2ccmd = rd32(E1000_I2CCMD); 335 if (i2ccmd & E1000_I2CCMD_READY) 336 break; 337 } 338 if (!(i2ccmd & E1000_I2CCMD_READY)) { 339 hw_dbg("I2CCMD Write did not complete\n"); 340 return -E1000_ERR_PHY; 341 } 342 if (i2ccmd & E1000_I2CCMD_ERROR) { 343 hw_dbg("I2CCMD Error bit set\n"); 344 return -E1000_ERR_PHY; 345 } 346 347 return 0; 348} 349 350/** 351 * igb_read_phy_reg_igp - Read igp PHY register 352 * @hw: pointer to the HW structure 353 * @offset: register offset to be read 354 * @data: pointer to the read data 355 * 356 * Acquires semaphore, if necessary, then reads the PHY register at offset 357 * and storing the retrieved information in data. Release any acquired 358 * semaphores before exiting. 359 **/ 360s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 361{ 362 s32 ret_val = 0; 363 364 if (!(hw->phy.ops.acquire)) 365 goto out; 366 367 ret_val = hw->phy.ops.acquire(hw); 368 if (ret_val) 369 goto out; 370 371 if (offset > MAX_PHY_MULTI_PAGE_REG) { 372 ret_val = igb_write_phy_reg_mdic(hw, 373 IGP01E1000_PHY_PAGE_SELECT, 374 (u16)offset); 375 if (ret_val) { 376 hw->phy.ops.release(hw); 377 goto out; 378 } 379 } 380 381 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 382 data); 383 384 hw->phy.ops.release(hw); 385 386out: 387 return ret_val; 388} 389 390/** 391 * igb_write_phy_reg_igp - Write igp PHY register 392 * @hw: pointer to the HW structure 393 * @offset: register offset to write to 394 * @data: data to write at register offset 395 * 396 * Acquires semaphore, if necessary, then writes the data to PHY register 397 * at the offset. Release any acquired semaphores before exiting. 398 **/ 399s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 400{ 401 s32 ret_val = 0; 402 403 if (!(hw->phy.ops.acquire)) 404 goto out; 405 406 ret_val = hw->phy.ops.acquire(hw); 407 if (ret_val) 408 goto out; 409 410 if (offset > MAX_PHY_MULTI_PAGE_REG) { 411 ret_val = igb_write_phy_reg_mdic(hw, 412 IGP01E1000_PHY_PAGE_SELECT, 413 (u16)offset); 414 if (ret_val) { 415 hw->phy.ops.release(hw); 416 goto out; 417 } 418 } 419 420 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 421 data); 422 423 hw->phy.ops.release(hw); 424 425out: 426 return ret_val; 427} 428 429/** 430 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link 431 * @hw: pointer to the HW structure 432 * 433 * Sets up Carrier-sense on Transmit and downshift values. 434 **/ 435s32 igb_copper_link_setup_82580(struct e1000_hw *hw) 436{ 437 struct e1000_phy_info *phy = &hw->phy; 438 s32 ret_val; 439 u16 phy_data; 440 441 442 if (phy->reset_disable) { 443 ret_val = 0; 444 goto out; 445 } 446 447 if (phy->type == e1000_phy_82580) { 448 ret_val = hw->phy.ops.reset(hw); 449 if (ret_val) { 450 hw_dbg("Error resetting the PHY.\n"); 451 goto out; 452 } 453 } 454 455 /* Enable CRS on TX. This must be set for half-duplex operation. */ 456 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data); 457 if (ret_val) 458 goto out; 459 460 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX; 461 462 /* Enable downshift */ 463 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT; 464 465 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); 466 467out: 468 return ret_val; 469} 470 471/** 472 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link 473 * @hw: pointer to the HW structure 474 * 475 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 476 * and downshift values are set also. 477 **/ 478s32 igb_copper_link_setup_m88(struct e1000_hw *hw) 479{ 480 struct e1000_phy_info *phy = &hw->phy; 481 s32 ret_val; 482 u16 phy_data; 483 484 if (phy->reset_disable) { 485 ret_val = 0; 486 goto out; 487 } 488 489 /* Enable CRS on TX. This must be set for half-duplex operation. */ 490 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 491 if (ret_val) 492 goto out; 493 494 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 495 496 /* 497 * Options: 498 * MDI/MDI-X = 0 (default) 499 * 0 - Auto for all speeds 500 * 1 - MDI mode 501 * 2 - MDI-X mode 502 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 503 */ 504 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 505 506 switch (phy->mdix) { 507 case 1: 508 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 509 break; 510 case 2: 511 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 512 break; 513 case 3: 514 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 515 break; 516 case 0: 517 default: 518 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 519 break; 520 } 521 522 /* 523 * Options: 524 * disable_polarity_correction = 0 (default) 525 * Automatic Correction for Reversed Cable Polarity 526 * 0 - Disabled 527 * 1 - Enabled 528 */ 529 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 530 if (phy->disable_polarity_correction == 1) 531 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 532 533 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 534 if (ret_val) 535 goto out; 536 537 if (phy->revision < E1000_REVISION_4) { 538 /* 539 * Force TX_CLK in the Extended PHY Specific Control Register 540 * to 25MHz clock. 541 */ 542 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 543 &phy_data); 544 if (ret_val) 545 goto out; 546 547 phy_data |= M88E1000_EPSCR_TX_CLK_25; 548 549 if ((phy->revision == E1000_REVISION_2) && 550 (phy->id == M88E1111_I_PHY_ID)) { 551 /* 82573L PHY - set the downshift counter to 5x. */ 552 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 553 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 554 } else { 555 /* Configure Master and Slave downshift values */ 556 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 557 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 558 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 559 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 560 } 561 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 562 phy_data); 563 if (ret_val) 564 goto out; 565 } 566 567 /* Commit the changes. */ 568 ret_val = igb_phy_sw_reset(hw); 569 if (ret_val) { 570 hw_dbg("Error committing the PHY changes\n"); 571 goto out; 572 } 573 574out: 575 return ret_val; 576} 577 578/** 579 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 580 * @hw: pointer to the HW structure 581 * 582 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 583 * Also enables and sets the downshift parameters. 584 **/ 585s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw) 586{ 587 struct e1000_phy_info *phy = &hw->phy; 588 s32 ret_val; 589 u16 phy_data; 590 591 if (phy->reset_disable) { 592 ret_val = 0; 593 goto out; 594 } 595 596 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 597 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 598 if (ret_val) 599 goto out; 600 601 /* 602 * Options: 603 * MDI/MDI-X = 0 (default) 604 * 0 - Auto for all speeds 605 * 1 - MDI mode 606 * 2 - MDI-X mode 607 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 608 */ 609 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 610 611 switch (phy->mdix) { 612 case 1: 613 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 614 break; 615 case 2: 616 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 617 break; 618 case 3: 619 /* M88E1112 does not support this mode) */ 620 if (phy->id != M88E1112_E_PHY_ID) { 621 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 622 break; 623 } 624 case 0: 625 default: 626 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 627 break; 628 } 629 630 /* 631 * Options: 632 * disable_polarity_correction = 0 (default) 633 * Automatic Correction for Reversed Cable Polarity 634 * 0 - Disabled 635 * 1 - Enabled 636 */ 637 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 638 if (phy->disable_polarity_correction == 1) 639 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 640 641 /* Enable downshift and setting it to X6 */ 642 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 643 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 644 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 645 646 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 647 if (ret_val) 648 goto out; 649 650 /* Commit the changes. */ 651 ret_val = igb_phy_sw_reset(hw); 652 if (ret_val) { 653 hw_dbg("Error committing the PHY changes\n"); 654 goto out; 655 } 656 657out: 658 return ret_val; 659} 660 661/** 662 * igb_copper_link_setup_igp - Setup igp PHY's for copper link 663 * @hw: pointer to the HW structure 664 * 665 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 666 * igp PHY's. 667 **/ 668s32 igb_copper_link_setup_igp(struct e1000_hw *hw) 669{ 670 struct e1000_phy_info *phy = &hw->phy; 671 s32 ret_val; 672 u16 data; 673 674 if (phy->reset_disable) { 675 ret_val = 0; 676 goto out; 677 } 678 679 ret_val = phy->ops.reset(hw); 680 if (ret_val) { 681 hw_dbg("Error resetting the PHY.\n"); 682 goto out; 683 } 684 685 /* 686 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 687 * timeout issues when LFS is enabled. 688 */ 689 msleep(100); 690 691 /* 692 * The NVM settings will configure LPLU in D3 for 693 * non-IGP1 PHYs. 694 */ 695 if (phy->type == e1000_phy_igp) { 696 /* disable lplu d3 during driver init */ 697 if (phy->ops.set_d3_lplu_state) 698 ret_val = phy->ops.set_d3_lplu_state(hw, false); 699 if (ret_val) { 700 hw_dbg("Error Disabling LPLU D3\n"); 701 goto out; 702 } 703 } 704 705 /* disable lplu d0 during driver init */ 706 ret_val = phy->ops.set_d0_lplu_state(hw, false); 707 if (ret_val) { 708 hw_dbg("Error Disabling LPLU D0\n"); 709 goto out; 710 } 711 /* Configure mdi-mdix settings */ 712 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 713 if (ret_val) 714 goto out; 715 716 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 717 718 switch (phy->mdix) { 719 case 1: 720 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 721 break; 722 case 2: 723 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 724 break; 725 case 0: 726 default: 727 data |= IGP01E1000_PSCR_AUTO_MDIX; 728 break; 729 } 730 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 731 if (ret_val) 732 goto out; 733 734 /* set auto-master slave resolution settings */ 735 if (hw->mac.autoneg) { 736 /* 737 * when autonegotiation advertisement is only 1000Mbps then we 738 * should disable SmartSpeed and enable Auto MasterSlave 739 * resolution as hardware default. 740 */ 741 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 742 /* Disable SmartSpeed */ 743 ret_val = phy->ops.read_reg(hw, 744 IGP01E1000_PHY_PORT_CONFIG, 745 &data); 746 if (ret_val) 747 goto out; 748 749 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 750 ret_val = phy->ops.write_reg(hw, 751 IGP01E1000_PHY_PORT_CONFIG, 752 data); 753 if (ret_val) 754 goto out; 755 756 /* Set auto Master/Slave resolution process */ 757 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 758 if (ret_val) 759 goto out; 760 761 data &= ~CR_1000T_MS_ENABLE; 762 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 763 if (ret_val) 764 goto out; 765 } 766 767 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 768 if (ret_val) 769 goto out; 770 771 /* load defaults for future use */ 772 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 773 ((data & CR_1000T_MS_VALUE) ? 774 e1000_ms_force_master : 775 e1000_ms_force_slave) : 776 e1000_ms_auto; 777 778 switch (phy->ms_type) { 779 case e1000_ms_force_master: 780 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 781 break; 782 case e1000_ms_force_slave: 783 data |= CR_1000T_MS_ENABLE; 784 data &= ~(CR_1000T_MS_VALUE); 785 break; 786 case e1000_ms_auto: 787 data &= ~CR_1000T_MS_ENABLE; 788 default: 789 break; 790 } 791 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 792 if (ret_val) 793 goto out; 794 } 795 796out: 797 return ret_val; 798} 799 800/** 801 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link 802 * @hw: pointer to the HW structure 803 * 804 * Performs initial bounds checking on autoneg advertisement parameter, then 805 * configure to advertise the full capability. Setup the PHY to autoneg 806 * and restart the negotiation process between the link partner. If 807 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 808 **/ 809static s32 igb_copper_link_autoneg(struct e1000_hw *hw) 810{ 811 struct e1000_phy_info *phy = &hw->phy; 812 s32 ret_val; 813 u16 phy_ctrl; 814 815 /* 816 * Perform some bounds checking on the autoneg advertisement 817 * parameter. 818 */ 819 phy->autoneg_advertised &= phy->autoneg_mask; 820 821 /* 822 * If autoneg_advertised is zero, we assume it was not defaulted 823 * by the calling code so we set to advertise full capability. 824 */ 825 if (phy->autoneg_advertised == 0) 826 phy->autoneg_advertised = phy->autoneg_mask; 827 828 hw_dbg("Reconfiguring auto-neg advertisement params\n"); 829 ret_val = igb_phy_setup_autoneg(hw); 830 if (ret_val) { 831 hw_dbg("Error Setting up Auto-Negotiation\n"); 832 goto out; 833 } 834 hw_dbg("Restarting Auto-Neg\n"); 835 836 /* 837 * Restart auto-negotiation by setting the Auto Neg Enable bit and 838 * the Auto Neg Restart bit in the PHY control register. 839 */ 840 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 841 if (ret_val) 842 goto out; 843 844 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 845 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 846 if (ret_val) 847 goto out; 848 849 /* 850 * Does the user want to wait for Auto-Neg to complete here, or 851 * check at a later time (for example, callback routine). 852 */ 853 if (phy->autoneg_wait_to_complete) { 854 ret_val = igb_wait_autoneg(hw); 855 if (ret_val) { 856 hw_dbg("Error while waiting for " 857 "autoneg to complete\n"); 858 goto out; 859 } 860 } 861 862 hw->mac.get_link_status = true; 863 864out: 865 return ret_val; 866} 867 868/** 869 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation 870 * @hw: pointer to the HW structure 871 * 872 * Reads the MII auto-neg advertisement register and/or the 1000T control 873 * register and if the PHY is already setup for auto-negotiation, then 874 * return successful. Otherwise, setup advertisement and flow control to 875 * the appropriate values for the wanted auto-negotiation. 876 **/ 877static s32 igb_phy_setup_autoneg(struct e1000_hw *hw) 878{ 879 struct e1000_phy_info *phy = &hw->phy; 880 s32 ret_val; 881 u16 mii_autoneg_adv_reg; 882 u16 mii_1000t_ctrl_reg = 0; 883 884 phy->autoneg_advertised &= phy->autoneg_mask; 885 886 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 887 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 888 if (ret_val) 889 goto out; 890 891 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 892 /* Read the MII 1000Base-T Control Register (Address 9). */ 893 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 894 &mii_1000t_ctrl_reg); 895 if (ret_val) 896 goto out; 897 } 898 899 /* 900 * Need to parse both autoneg_advertised and fc and set up 901 * the appropriate PHY registers. First we will parse for 902 * autoneg_advertised software override. Since we can advertise 903 * a plethora of combinations, we need to check each bit 904 * individually. 905 */ 906 907 /* 908 * First we clear all the 10/100 mb speed bits in the Auto-Neg 909 * Advertisement Register (Address 4) and the 1000 mb speed bits in 910 * the 1000Base-T Control Register (Address 9). 911 */ 912 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 913 NWAY_AR_100TX_HD_CAPS | 914 NWAY_AR_10T_FD_CAPS | 915 NWAY_AR_10T_HD_CAPS); 916 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 917 918 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); 919 920 /* Do we want to advertise 10 Mb Half Duplex? */ 921 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 922 hw_dbg("Advertise 10mb Half duplex\n"); 923 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 924 } 925 926 /* Do we want to advertise 10 Mb Full Duplex? */ 927 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 928 hw_dbg("Advertise 10mb Full duplex\n"); 929 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 930 } 931 932 /* Do we want to advertise 100 Mb Half Duplex? */ 933 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 934 hw_dbg("Advertise 100mb Half duplex\n"); 935 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 936 } 937 938 /* Do we want to advertise 100 Mb Full Duplex? */ 939 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 940 hw_dbg("Advertise 100mb Full duplex\n"); 941 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 942 } 943 944 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 945 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 946 hw_dbg("Advertise 1000mb Half duplex request denied!\n"); 947 948 /* Do we want to advertise 1000 Mb Full Duplex? */ 949 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 950 hw_dbg("Advertise 1000mb Full duplex\n"); 951 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 952 } 953 954 /* 955 * Check for a software override of the flow control settings, and 956 * setup the PHY advertisement registers accordingly. If 957 * auto-negotiation is enabled, then software will have to set the 958 * "PAUSE" bits to the correct value in the Auto-Negotiation 959 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 960 * negotiation. 961 * 962 * The possible values of the "fc" parameter are: 963 * 0: Flow control is completely disabled 964 * 1: Rx flow control is enabled (we can receive pause frames 965 * but not send pause frames). 966 * 2: Tx flow control is enabled (we can send pause frames 967 * but we do not support receiving pause frames). 968 * 3: Both Rx and TX flow control (symmetric) are enabled. 969 * other: No software override. The flow control configuration 970 * in the EEPROM is used. 971 */ 972 switch (hw->fc.current_mode) { 973 case e1000_fc_none: 974 /* 975 * Flow control (RX & TX) is completely disabled by a 976 * software over-ride. 977 */ 978 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 979 break; 980 case e1000_fc_rx_pause: 981 /* 982 * RX Flow control is enabled, and TX Flow control is 983 * disabled, by a software over-ride. 984 * 985 * Since there really isn't a way to advertise that we are 986 * capable of RX Pause ONLY, we will advertise that we 987 * support both symmetric and asymmetric RX PAUSE. Later 988 * (in e1000_config_fc_after_link_up) we will disable the 989 * hw's ability to send PAUSE frames. 990 */ 991 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 992 break; 993 case e1000_fc_tx_pause: 994 /* 995 * TX Flow control is enabled, and RX Flow control is 996 * disabled, by a software over-ride. 997 */ 998 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 999 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1000 break; 1001 case e1000_fc_full: 1002 /* 1003 * Flow control (both RX and TX) is enabled by a software 1004 * over-ride. 1005 */ 1006 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1007 break; 1008 default: 1009 hw_dbg("Flow control param set incorrectly\n"); 1010 ret_val = -E1000_ERR_CONFIG; 1011 goto out; 1012 } 1013 1014 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1015 if (ret_val) 1016 goto out; 1017 1018 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1019 1020 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1021 ret_val = phy->ops.write_reg(hw, 1022 PHY_1000T_CTRL, 1023 mii_1000t_ctrl_reg); 1024 if (ret_val) 1025 goto out; 1026 } 1027 1028out: 1029 return ret_val; 1030} 1031 1032/** 1033 * igb_setup_copper_link - Configure copper link settings 1034 * @hw: pointer to the HW structure 1035 * 1036 * Calls the appropriate function to configure the link for auto-neg or forced 1037 * speed and duplex. Then we check for link, once link is established calls 1038 * to configure collision distance and flow control are called. If link is 1039 * not established, we return -E1000_ERR_PHY (-2). 1040 **/ 1041s32 igb_setup_copper_link(struct e1000_hw *hw) 1042{ 1043 s32 ret_val; 1044 bool link; 1045 1046 1047 if (hw->mac.autoneg) { 1048 /* 1049 * Setup autoneg and flow control advertisement and perform 1050 * autonegotiation. 1051 */ 1052 ret_val = igb_copper_link_autoneg(hw); 1053 if (ret_val) 1054 goto out; 1055 } else { 1056 /* 1057 * PHY will be set to 10H, 10F, 100H or 100F 1058 * depending on user settings. 1059 */ 1060 hw_dbg("Forcing Speed and Duplex\n"); 1061 ret_val = hw->phy.ops.force_speed_duplex(hw); 1062 if (ret_val) { 1063 hw_dbg("Error Forcing Speed and Duplex\n"); 1064 goto out; 1065 } 1066 } 1067 1068 /* 1069 * Check link status. Wait up to 100 microseconds for link to become 1070 * valid. 1071 */ 1072 ret_val = igb_phy_has_link(hw, 1073 COPPER_LINK_UP_LIMIT, 1074 10, 1075 &link); 1076 if (ret_val) 1077 goto out; 1078 1079 if (link) { 1080 hw_dbg("Valid link established!!!\n"); 1081 igb_config_collision_dist(hw); 1082 ret_val = igb_config_fc_after_link_up(hw); 1083 } else { 1084 hw_dbg("Unable to establish link!!!\n"); 1085 } 1086 1087out: 1088 return ret_val; 1089} 1090 1091/** 1092 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1093 * @hw: pointer to the HW structure 1094 * 1095 * Calls the PHY setup function to force speed and duplex. Clears the 1096 * auto-crossover to force MDI manually. Waits for link and returns 1097 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1098 **/ 1099s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1100{ 1101 struct e1000_phy_info *phy = &hw->phy; 1102 s32 ret_val; 1103 u16 phy_data; 1104 bool link; 1105 1106 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1107 if (ret_val) 1108 goto out; 1109 1110 igb_phy_force_speed_duplex_setup(hw, &phy_data); 1111 1112 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1113 if (ret_val) 1114 goto out; 1115 1116 /* 1117 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1118 * forced whenever speed and duplex are forced. 1119 */ 1120 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1121 if (ret_val) 1122 goto out; 1123 1124 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1125 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1126 1127 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1128 if (ret_val) 1129 goto out; 1130 1131 hw_dbg("IGP PSCR: %X\n", phy_data); 1132 1133 udelay(1); 1134 1135 if (phy->autoneg_wait_to_complete) { 1136 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); 1137 1138 ret_val = igb_phy_has_link(hw, 1139 PHY_FORCE_LIMIT, 1140 100000, 1141 &link); 1142 if (ret_val) 1143 goto out; 1144 1145 if (!link) 1146 hw_dbg("Link taking longer than expected.\n"); 1147 1148 /* Try once more */ 1149 ret_val = igb_phy_has_link(hw, 1150 PHY_FORCE_LIMIT, 1151 100000, 1152 &link); 1153 if (ret_val) 1154 goto out; 1155 } 1156 1157out: 1158 return ret_val; 1159} 1160 1161/** 1162 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1163 * @hw: pointer to the HW structure 1164 * 1165 * Calls the PHY setup function to force speed and duplex. Clears the 1166 * auto-crossover to force MDI manually. Resets the PHY to commit the 1167 * changes. If time expires while waiting for link up, we reset the DSP. 1168 * After reset, TX_CLK and CRS on TX must be set. Return successful upon 1169 * successful completion, else return corresponding error code. 1170 **/ 1171s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1172{ 1173 struct e1000_phy_info *phy = &hw->phy; 1174 s32 ret_val; 1175 u16 phy_data; 1176 bool link; 1177 1178 /* 1179 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1180 * forced whenever speed and duplex are forced. 1181 */ 1182 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1183 if (ret_val) 1184 goto out; 1185 1186 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1187 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1188 if (ret_val) 1189 goto out; 1190 1191 hw_dbg("M88E1000 PSCR: %X\n", phy_data); 1192 1193 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1194 if (ret_val) 1195 goto out; 1196 1197 igb_phy_force_speed_duplex_setup(hw, &phy_data); 1198 1199 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1200 if (ret_val) 1201 goto out; 1202 1203 /* Reset the phy to commit changes. */ 1204 ret_val = igb_phy_sw_reset(hw); 1205 if (ret_val) 1206 goto out; 1207 1208 if (phy->autoneg_wait_to_complete) { 1209 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); 1210 1211 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 1212 if (ret_val) 1213 goto out; 1214 1215 if (!link) { 1216 if (hw->phy.type != e1000_phy_m88 || 1217 hw->phy.id == I347AT4_E_PHY_ID || 1218 hw->phy.id == M88E1112_E_PHY_ID) { 1219 hw_dbg("Link taking longer than expected.\n"); 1220 } else { 1221 1222 /* 1223 * We didn't get link. 1224 * Reset the DSP and cross our fingers. 1225 */ 1226 ret_val = phy->ops.write_reg(hw, 1227 M88E1000_PHY_PAGE_SELECT, 1228 0x001d); 1229 if (ret_val) 1230 goto out; 1231 ret_val = igb_phy_reset_dsp(hw); 1232 if (ret_val) 1233 goto out; 1234 } 1235 } 1236 1237 /* Try once more */ 1238 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 1239 100000, &link); 1240 if (ret_val) 1241 goto out; 1242 } 1243 1244 if (hw->phy.type != e1000_phy_m88 || 1245 hw->phy.id == I347AT4_E_PHY_ID || 1246 hw->phy.id == M88E1112_E_PHY_ID) 1247 goto out; 1248 1249 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1250 if (ret_val) 1251 goto out; 1252 1253 /* 1254 * Resetting the phy means we need to re-force TX_CLK in the 1255 * Extended PHY Specific Control Register to 25MHz clock from 1256 * the reset value of 2.5MHz. 1257 */ 1258 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1259 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1260 if (ret_val) 1261 goto out; 1262 1263 /* 1264 * In addition, we must re-enable CRS on Tx for both half and full 1265 * duplex. 1266 */ 1267 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1268 if (ret_val) 1269 goto out; 1270 1271 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1272 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1273 1274out: 1275 return ret_val; 1276} 1277 1278/** 1279 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1280 * @hw: pointer to the HW structure 1281 * @phy_ctrl: pointer to current value of PHY_CONTROL 1282 * 1283 * Forces speed and duplex on the PHY by doing the following: disable flow 1284 * control, force speed/duplex on the MAC, disable auto speed detection, 1285 * disable auto-negotiation, configure duplex, configure speed, configure 1286 * the collision distance, write configuration to CTRL register. The 1287 * caller must write to the PHY_CONTROL register for these settings to 1288 * take affect. 1289 **/ 1290static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, 1291 u16 *phy_ctrl) 1292{ 1293 struct e1000_mac_info *mac = &hw->mac; 1294 u32 ctrl; 1295 1296 /* Turn off flow control when forcing speed/duplex */ 1297 hw->fc.current_mode = e1000_fc_none; 1298 1299 /* Force speed/duplex on the mac */ 1300 ctrl = rd32(E1000_CTRL); 1301 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1302 ctrl &= ~E1000_CTRL_SPD_SEL; 1303 1304 /* Disable Auto Speed Detection */ 1305 ctrl &= ~E1000_CTRL_ASDE; 1306 1307 /* Disable autoneg on the phy */ 1308 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1309 1310 /* Forcing Full or Half Duplex? */ 1311 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1312 ctrl &= ~E1000_CTRL_FD; 1313 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1314 hw_dbg("Half Duplex\n"); 1315 } else { 1316 ctrl |= E1000_CTRL_FD; 1317 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1318 hw_dbg("Full Duplex\n"); 1319 } 1320 1321 /* Forcing 10mb or 100mb? */ 1322 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1323 ctrl |= E1000_CTRL_SPD_100; 1324 *phy_ctrl |= MII_CR_SPEED_100; 1325 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1326 hw_dbg("Forcing 100mb\n"); 1327 } else { 1328 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1329 *phy_ctrl |= MII_CR_SPEED_10; 1330 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1331 hw_dbg("Forcing 10mb\n"); 1332 } 1333 1334 igb_config_collision_dist(hw); 1335 1336 wr32(E1000_CTRL, ctrl); 1337} 1338 1339/** 1340 * igb_set_d3_lplu_state - Sets low power link up state for D3 1341 * @hw: pointer to the HW structure 1342 * @active: boolean used to enable/disable lplu 1343 * 1344 * Success returns 0, Failure returns 1 1345 * 1346 * The low power link up (lplu) state is set to the power management level D3 1347 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1348 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1349 * is used during Dx states where the power conservation is most important. 1350 * During driver activity, SmartSpeed should be enabled so performance is 1351 * maintained. 1352 **/ 1353s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active) 1354{ 1355 struct e1000_phy_info *phy = &hw->phy; 1356 s32 ret_val = 0; 1357 u16 data; 1358 1359 if (!(hw->phy.ops.read_reg)) 1360 goto out; 1361 1362 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1363 if (ret_val) 1364 goto out; 1365 1366 if (!active) { 1367 data &= ~IGP02E1000_PM_D3_LPLU; 1368 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1369 data); 1370 if (ret_val) 1371 goto out; 1372 /* 1373 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1374 * during Dx states where the power conservation is most 1375 * important. During driver activity we should enable 1376 * SmartSpeed, so performance is maintained. 1377 */ 1378 if (phy->smart_speed == e1000_smart_speed_on) { 1379 ret_val = phy->ops.read_reg(hw, 1380 IGP01E1000_PHY_PORT_CONFIG, 1381 &data); 1382 if (ret_val) 1383 goto out; 1384 1385 data |= IGP01E1000_PSCFR_SMART_SPEED; 1386 ret_val = phy->ops.write_reg(hw, 1387 IGP01E1000_PHY_PORT_CONFIG, 1388 data); 1389 if (ret_val) 1390 goto out; 1391 } else if (phy->smart_speed == e1000_smart_speed_off) { 1392 ret_val = phy->ops.read_reg(hw, 1393 IGP01E1000_PHY_PORT_CONFIG, 1394 &data); 1395 if (ret_val) 1396 goto out; 1397 1398 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1399 ret_val = phy->ops.write_reg(hw, 1400 IGP01E1000_PHY_PORT_CONFIG, 1401 data); 1402 if (ret_val) 1403 goto out; 1404 } 1405 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1406 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1407 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1408 data |= IGP02E1000_PM_D3_LPLU; 1409 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1410 data); 1411 if (ret_val) 1412 goto out; 1413 1414 /* When LPLU is enabled, we should disable SmartSpeed */ 1415 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1416 &data); 1417 if (ret_val) 1418 goto out; 1419 1420 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1421 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1422 data); 1423 } 1424 1425out: 1426 return ret_val; 1427} 1428 1429/** 1430 * igb_check_downshift - Checks whether a downshift in speed occurred 1431 * @hw: pointer to the HW structure 1432 * 1433 * Success returns 0, Failure returns 1 1434 * 1435 * A downshift is detected by querying the PHY link health. 1436 **/ 1437s32 igb_check_downshift(struct e1000_hw *hw) 1438{ 1439 struct e1000_phy_info *phy = &hw->phy; 1440 s32 ret_val; 1441 u16 phy_data, offset, mask; 1442 1443 switch (phy->type) { 1444 case e1000_phy_m88: 1445 case e1000_phy_gg82563: 1446 offset = M88E1000_PHY_SPEC_STATUS; 1447 mask = M88E1000_PSSR_DOWNSHIFT; 1448 break; 1449 case e1000_phy_igp_2: 1450 case e1000_phy_igp: 1451 case e1000_phy_igp_3: 1452 offset = IGP01E1000_PHY_LINK_HEALTH; 1453 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1454 break; 1455 default: 1456 /* speed downshift not supported */ 1457 phy->speed_downgraded = false; 1458 ret_val = 0; 1459 goto out; 1460 } 1461 1462 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1463 1464 if (!ret_val) 1465 phy->speed_downgraded = (phy_data & mask) ? true : false; 1466 1467out: 1468 return ret_val; 1469} 1470 1471/** 1472 * igb_check_polarity_m88 - Checks the polarity. 1473 * @hw: pointer to the HW structure 1474 * 1475 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1476 * 1477 * Polarity is determined based on the PHY specific status register. 1478 **/ 1479static s32 igb_check_polarity_m88(struct e1000_hw *hw) 1480{ 1481 struct e1000_phy_info *phy = &hw->phy; 1482 s32 ret_val; 1483 u16 data; 1484 1485 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1486 1487 if (!ret_val) 1488 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1489 ? e1000_rev_polarity_reversed 1490 : e1000_rev_polarity_normal; 1491 1492 return ret_val; 1493} 1494 1495/** 1496 * igb_check_polarity_igp - Checks the polarity. 1497 * @hw: pointer to the HW structure 1498 * 1499 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1500 * 1501 * Polarity is determined based on the PHY port status register, and the 1502 * current speed (since there is no polarity at 100Mbps). 1503 **/ 1504static s32 igb_check_polarity_igp(struct e1000_hw *hw) 1505{ 1506 struct e1000_phy_info *phy = &hw->phy; 1507 s32 ret_val; 1508 u16 data, offset, mask; 1509 1510 /* 1511 * Polarity is determined based on the speed of 1512 * our connection. 1513 */ 1514 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1515 if (ret_val) 1516 goto out; 1517 1518 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1519 IGP01E1000_PSSR_SPEED_1000MBPS) { 1520 offset = IGP01E1000_PHY_PCS_INIT_REG; 1521 mask = IGP01E1000_PHY_POLARITY_MASK; 1522 } else { 1523 /* 1524 * This really only applies to 10Mbps since 1525 * there is no polarity for 100Mbps (always 0). 1526 */ 1527 offset = IGP01E1000_PHY_PORT_STATUS; 1528 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1529 } 1530 1531 ret_val = phy->ops.read_reg(hw, offset, &data); 1532 1533 if (!ret_val) 1534 phy->cable_polarity = (data & mask) 1535 ? e1000_rev_polarity_reversed 1536 : e1000_rev_polarity_normal; 1537 1538out: 1539 return ret_val; 1540} 1541 1542/** 1543 * igb_wait_autoneg - Wait for auto-neg compeletion 1544 * @hw: pointer to the HW structure 1545 * 1546 * Waits for auto-negotiation to complete or for the auto-negotiation time 1547 * limit to expire, which ever happens first. 1548 **/ 1549static s32 igb_wait_autoneg(struct e1000_hw *hw) 1550{ 1551 s32 ret_val = 0; 1552 u16 i, phy_status; 1553 1554 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1555 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1556 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1557 if (ret_val) 1558 break; 1559 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1560 if (ret_val) 1561 break; 1562 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1563 break; 1564 msleep(100); 1565 } 1566 1567 /* 1568 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1569 * has completed. 1570 */ 1571 return ret_val; 1572} 1573 1574/** 1575 * igb_phy_has_link - Polls PHY for link 1576 * @hw: pointer to the HW structure 1577 * @iterations: number of times to poll for link 1578 * @usec_interval: delay between polling attempts 1579 * @success: pointer to whether polling was successful or not 1580 * 1581 * Polls the PHY status register for link, 'iterations' number of times. 1582 **/ 1583s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, 1584 u32 usec_interval, bool *success) 1585{ 1586 s32 ret_val = 0; 1587 u16 i, phy_status; 1588 1589 for (i = 0; i < iterations; i++) { 1590 /* 1591 * Some PHYs require the PHY_STATUS register to be read 1592 * twice due to the link bit being sticky. No harm doing 1593 * it across the board. 1594 */ 1595 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1596 if (ret_val) { 1597 /* 1598 * If the first read fails, another entity may have 1599 * ownership of the resources, wait and try again to 1600 * see if they have relinquished the resources yet. 1601 */ 1602 udelay(usec_interval); 1603 } 1604 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1605 if (ret_val) 1606 break; 1607 if (phy_status & MII_SR_LINK_STATUS) 1608 break; 1609 if (usec_interval >= 1000) 1610 mdelay(usec_interval/1000); 1611 else 1612 udelay(usec_interval); 1613 } 1614 1615 *success = (i < iterations) ? true : false; 1616 1617 return ret_val; 1618} 1619 1620/** 1621 * igb_get_cable_length_m88 - Determine cable length for m88 PHY 1622 * @hw: pointer to the HW structure 1623 * 1624 * Reads the PHY specific status register to retrieve the cable length 1625 * information. The cable length is determined by averaging the minimum and 1626 * maximum values to get the "average" cable length. The m88 PHY has four 1627 * possible cable length values, which are: 1628 * Register Value Cable Length 1629 * 0 < 50 meters 1630 * 1 50 - 80 meters 1631 * 2 80 - 110 meters 1632 * 3 110 - 140 meters 1633 * 4 > 140 meters 1634 **/ 1635s32 igb_get_cable_length_m88(struct e1000_hw *hw) 1636{ 1637 struct e1000_phy_info *phy = &hw->phy; 1638 s32 ret_val; 1639 u16 phy_data, index; 1640 1641 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1642 if (ret_val) 1643 goto out; 1644 1645 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1646 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1647 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 1648 ret_val = -E1000_ERR_PHY; 1649 goto out; 1650 } 1651 1652 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1653 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1654 1655 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1656 1657out: 1658 return ret_val; 1659} 1660 1661s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw) 1662{ 1663 struct e1000_phy_info *phy = &hw->phy; 1664 s32 ret_val; 1665 u16 phy_data, phy_data2, index, default_page, is_cm; 1666 1667 switch (hw->phy.id) { 1668 case I347AT4_E_PHY_ID: 1669 /* Remember the original page select and set it to 7 */ 1670 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 1671 &default_page); 1672 if (ret_val) 1673 goto out; 1674 1675 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 1676 if (ret_val) 1677 goto out; 1678 1679 /* Get cable length from PHY Cable Diagnostics Control Reg */ 1680 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), 1681 &phy_data); 1682 if (ret_val) 1683 goto out; 1684 1685 /* Check if the unit of cable length is meters or cm */ 1686 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 1687 if (ret_val) 1688 goto out; 1689 1690 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 1691 1692 /* Populate the phy structure with cable length in meters */ 1693 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 1694 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 1695 phy->cable_length = phy_data / (is_cm ? 100 : 1); 1696 1697 /* Reset the page selec to its original value */ 1698 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 1699 default_page); 1700 if (ret_val) 1701 goto out; 1702 break; 1703 case M88E1112_E_PHY_ID: 1704 /* Remember the original page select and set it to 5 */ 1705 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 1706 &default_page); 1707 if (ret_val) 1708 goto out; 1709 1710 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 1711 if (ret_val) 1712 goto out; 1713 1714 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 1715 &phy_data); 1716 if (ret_val) 1717 goto out; 1718 1719 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1720 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1721 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 1722 ret_val = -E1000_ERR_PHY; 1723 goto out; 1724 } 1725 1726 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1727 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1728 1729 phy->cable_length = (phy->min_cable_length + 1730 phy->max_cable_length) / 2; 1731 1732 /* Reset the page select to its original value */ 1733 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 1734 default_page); 1735 if (ret_val) 1736 goto out; 1737 1738 break; 1739 default: 1740 ret_val = -E1000_ERR_PHY; 1741 goto out; 1742 } 1743 1744out: 1745 return ret_val; 1746} 1747 1748/** 1749 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1750 * @hw: pointer to the HW structure 1751 * 1752 * The automatic gain control (agc) normalizes the amplitude of the 1753 * received signal, adjusting for the attenuation produced by the 1754 * cable. By reading the AGC registers, which represent the 1755 * combination of coarse and fine gain value, the value can be put 1756 * into a lookup table to obtain the approximate cable length 1757 * for each channel. 1758 **/ 1759s32 igb_get_cable_length_igp_2(struct e1000_hw *hw) 1760{ 1761 struct e1000_phy_info *phy = &hw->phy; 1762 s32 ret_val = 0; 1763 u16 phy_data, i, agc_value = 0; 1764 u16 cur_agc_index, max_agc_index = 0; 1765 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1766 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 1767 IGP02E1000_PHY_AGC_A, 1768 IGP02E1000_PHY_AGC_B, 1769 IGP02E1000_PHY_AGC_C, 1770 IGP02E1000_PHY_AGC_D 1771 }; 1772 1773 /* Read the AGC registers for all channels */ 1774 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1775 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 1776 if (ret_val) 1777 goto out; 1778 1779 /* 1780 * Getting bits 15:9, which represent the combination of 1781 * coarse and fine gain values. The result is a number 1782 * that can be put into the lookup table to obtain the 1783 * approximate cable length. 1784 */ 1785 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1786 IGP02E1000_AGC_LENGTH_MASK; 1787 1788 /* Array index bound check. */ 1789 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1790 (cur_agc_index == 0)) { 1791 ret_val = -E1000_ERR_PHY; 1792 goto out; 1793 } 1794 1795 /* Remove min & max AGC values from calculation. */ 1796 if (e1000_igp_2_cable_length_table[min_agc_index] > 1797 e1000_igp_2_cable_length_table[cur_agc_index]) 1798 min_agc_index = cur_agc_index; 1799 if (e1000_igp_2_cable_length_table[max_agc_index] < 1800 e1000_igp_2_cable_length_table[cur_agc_index]) 1801 max_agc_index = cur_agc_index; 1802 1803 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1804 } 1805 1806 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1807 e1000_igp_2_cable_length_table[max_agc_index]); 1808 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1809 1810 /* Calculate cable length with the error range of +/- 10 meters. */ 1811 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1812 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1813 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1814 1815 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1816 1817out: 1818 return ret_val; 1819} 1820 1821/** 1822 * igb_get_phy_info_m88 - Retrieve PHY information 1823 * @hw: pointer to the HW structure 1824 * 1825 * Valid for only copper links. Read the PHY status register (sticky read) 1826 * to verify that link is up. Read the PHY special control register to 1827 * determine the polarity and 10base-T extended distance. Read the PHY 1828 * special status register to determine MDI/MDIx and current speed. If 1829 * speed is 1000, then determine cable length, local and remote receiver. 1830 **/ 1831s32 igb_get_phy_info_m88(struct e1000_hw *hw) 1832{ 1833 struct e1000_phy_info *phy = &hw->phy; 1834 s32 ret_val; 1835 u16 phy_data; 1836 bool link; 1837 1838 if (phy->media_type != e1000_media_type_copper) { 1839 hw_dbg("Phy info is only valid for copper media\n"); 1840 ret_val = -E1000_ERR_CONFIG; 1841 goto out; 1842 } 1843 1844 ret_val = igb_phy_has_link(hw, 1, 0, &link); 1845 if (ret_val) 1846 goto out; 1847 1848 if (!link) { 1849 hw_dbg("Phy info is only valid if link is up\n"); 1850 ret_val = -E1000_ERR_CONFIG; 1851 goto out; 1852 } 1853 1854 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1855 if (ret_val) 1856 goto out; 1857 1858 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 1859 ? true : false; 1860 1861 ret_val = igb_check_polarity_m88(hw); 1862 if (ret_val) 1863 goto out; 1864 1865 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1866 if (ret_val) 1867 goto out; 1868 1869 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; 1870 1871 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 1872 ret_val = phy->ops.get_cable_length(hw); 1873 if (ret_val) 1874 goto out; 1875 1876 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 1877 if (ret_val) 1878 goto out; 1879 1880 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 1881 ? e1000_1000t_rx_status_ok 1882 : e1000_1000t_rx_status_not_ok; 1883 1884 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 1885 ? e1000_1000t_rx_status_ok 1886 : e1000_1000t_rx_status_not_ok; 1887 } else { 1888 /* Set values to "undefined" */ 1889 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1890 phy->local_rx = e1000_1000t_rx_status_undefined; 1891 phy->remote_rx = e1000_1000t_rx_status_undefined; 1892 } 1893 1894out: 1895 return ret_val; 1896} 1897 1898/** 1899 * igb_get_phy_info_igp - Retrieve igp PHY information 1900 * @hw: pointer to the HW structure 1901 * 1902 * Read PHY status to determine if link is up. If link is up, then 1903 * set/determine 10base-T extended distance and polarity correction. Read 1904 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 1905 * determine on the cable length, local and remote receiver. 1906 **/ 1907s32 igb_get_phy_info_igp(struct e1000_hw *hw) 1908{ 1909 struct e1000_phy_info *phy = &hw->phy; 1910 s32 ret_val; 1911 u16 data; 1912 bool link; 1913 1914 ret_val = igb_phy_has_link(hw, 1, 0, &link); 1915 if (ret_val) 1916 goto out; 1917 1918 if (!link) { 1919 hw_dbg("Phy info is only valid if link is up\n"); 1920 ret_val = -E1000_ERR_CONFIG; 1921 goto out; 1922 } 1923 1924 phy->polarity_correction = true; 1925 1926 ret_val = igb_check_polarity_igp(hw); 1927 if (ret_val) 1928 goto out; 1929 1930 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1931 if (ret_val) 1932 goto out; 1933 1934 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; 1935 1936 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1937 IGP01E1000_PSSR_SPEED_1000MBPS) { 1938 ret_val = phy->ops.get_cable_length(hw); 1939 if (ret_val) 1940 goto out; 1941 1942 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 1943 if (ret_val) 1944 goto out; 1945 1946 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 1947 ? e1000_1000t_rx_status_ok 1948 : e1000_1000t_rx_status_not_ok; 1949 1950 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 1951 ? e1000_1000t_rx_status_ok 1952 : e1000_1000t_rx_status_not_ok; 1953 } else { 1954 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1955 phy->local_rx = e1000_1000t_rx_status_undefined; 1956 phy->remote_rx = e1000_1000t_rx_status_undefined; 1957 } 1958 1959out: 1960 return ret_val; 1961} 1962 1963/** 1964 * igb_phy_sw_reset - PHY software reset 1965 * @hw: pointer to the HW structure 1966 * 1967 * Does a software reset of the PHY by reading the PHY control register and 1968 * setting/write the control register reset bit to the PHY. 1969 **/ 1970s32 igb_phy_sw_reset(struct e1000_hw *hw) 1971{ 1972 s32 ret_val = 0; 1973 u16 phy_ctrl; 1974 1975 if (!(hw->phy.ops.read_reg)) 1976 goto out; 1977 1978 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1979 if (ret_val) 1980 goto out; 1981 1982 phy_ctrl |= MII_CR_RESET; 1983 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 1984 if (ret_val) 1985 goto out; 1986 1987 udelay(1); 1988 1989out: 1990 return ret_val; 1991} 1992 1993/** 1994 * igb_phy_hw_reset - PHY hardware reset 1995 * @hw: pointer to the HW structure 1996 * 1997 * Verify the reset block is not blocking us from resetting. Acquire 1998 * semaphore (if necessary) and read/set/write the device control reset 1999 * bit in the PHY. Wait the appropriate delay time for the device to 2000 * reset and relase the semaphore (if necessary). 2001 **/ 2002s32 igb_phy_hw_reset(struct e1000_hw *hw) 2003{ 2004 struct e1000_phy_info *phy = &hw->phy; 2005 s32 ret_val; 2006 u32 ctrl; 2007 2008 ret_val = igb_check_reset_block(hw); 2009 if (ret_val) { 2010 ret_val = 0; 2011 goto out; 2012 } 2013 2014 ret_val = phy->ops.acquire(hw); 2015 if (ret_val) 2016 goto out; 2017 2018 ctrl = rd32(E1000_CTRL); 2019 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2020 wrfl(); 2021 2022 udelay(phy->reset_delay_us); 2023 2024 wr32(E1000_CTRL, ctrl); 2025 wrfl(); 2026 2027 udelay(150); 2028 2029 phy->ops.release(hw); 2030 2031 ret_val = phy->ops.get_cfg_done(hw); 2032 2033out: 2034 return ret_val; 2035} 2036 2037/** 2038 * igb_phy_init_script_igp3 - Inits the IGP3 PHY 2039 * @hw: pointer to the HW structure 2040 * 2041 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2042 **/ 2043s32 igb_phy_init_script_igp3(struct e1000_hw *hw) 2044{ 2045 hw_dbg("Running IGP 3 PHY init script\n"); 2046 2047 /* PHY init IGP 3 */ 2048 /* Enable rise/fall, 10-mode work in class-A */ 2049 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2050 /* Remove all caps from Replica path filter */ 2051 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2052 /* Bias trimming for ADC, AFE and Driver (Default) */ 2053 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2054 /* Increase Hybrid poly bias */ 2055 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2056 /* Add 4% to TX amplitude in Giga mode */ 2057 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2058 /* Disable trimming (TTT) */ 2059 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2060 /* Poly DC correction to 94.6% + 2% for all channels */ 2061 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2062 /* ABS DC correction to 95.9% */ 2063 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2064 /* BG temp curve trim */ 2065 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2066 /* Increasing ADC OPAMP stage 1 currents to max */ 2067 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2068 /* Force 1000 ( required for enabling PHY regs configuration) */ 2069 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2070 /* Set upd_freq to 6 */ 2071 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2072 /* Disable NPDFE */ 2073 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2074 /* Disable adaptive fixed FFE (Default) */ 2075 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2076 /* Enable FFE hysteresis */ 2077 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2078 /* Fixed FFE for short cable lengths */ 2079 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2080 /* Fixed FFE for medium cable lengths */ 2081 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2082 /* Fixed FFE for long cable lengths */ 2083 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2084 /* Enable Adaptive Clip Threshold */ 2085 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2086 /* AHT reset limit to 1 */ 2087 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2088 /* Set AHT master delay to 127 msec */ 2089 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2090 /* Set scan bits for AHT */ 2091 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2092 /* Set AHT Preset bits */ 2093 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2094 /* Change integ_factor of channel A to 3 */ 2095 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2096 /* Change prop_factor of channels BCD to 8 */ 2097 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2098 /* Change cg_icount + enable integbp for channels BCD */ 2099 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2100 /* 2101 * Change cg_icount + enable integbp + change prop_factor_master 2102 * to 8 for channel A 2103 */ 2104 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2105 /* Disable AHT in Slave mode on channel A */ 2106 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2107 /* 2108 * Enable LPLU and disable AN to 1000 in non-D0a states, 2109 * Enable SPD+B2B 2110 */ 2111 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2112 /* Enable restart AN on an1000_dis change */ 2113 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2114 /* Enable wh_fifo read clock in 10/100 modes */ 2115 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2116 /* Restart AN, Speed selection is 1000 */ 2117 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2118 2119 return 0; 2120} 2121 2122/** 2123 * igb_power_up_phy_copper - Restore copper link in case of PHY power down 2124 * @hw: pointer to the HW structure 2125 * 2126 * In the case of a PHY power down to save power, or to turn off link during a 2127 * driver unload, restore the link to previous settings. 2128 **/ 2129void igb_power_up_phy_copper(struct e1000_hw *hw) 2130{ 2131 u16 mii_reg = 0; 2132 2133 /* The PHY will retain its settings across a power down/up cycle */ 2134 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2135 mii_reg &= ~MII_CR_POWER_DOWN; 2136 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2137} 2138 2139/** 2140 * igb_power_down_phy_copper - Power down copper PHY 2141 * @hw: pointer to the HW structure 2142 * 2143 * Power down PHY to save power when interface is down and wake on lan 2144 * is not enabled. 2145 **/ 2146void igb_power_down_phy_copper(struct e1000_hw *hw) 2147{ 2148 u16 mii_reg = 0; 2149 2150 /* The PHY will retain its settings across a power down/up cycle */ 2151 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2152 mii_reg |= MII_CR_POWER_DOWN; 2153 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2154 msleep(1); 2155} 2156 2157/** 2158 * igb_check_polarity_82580 - Checks the polarity. 2159 * @hw: pointer to the HW structure 2160 * 2161 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2162 * 2163 * Polarity is determined based on the PHY specific status register. 2164 **/ 2165static s32 igb_check_polarity_82580(struct e1000_hw *hw) 2166{ 2167 struct e1000_phy_info *phy = &hw->phy; 2168 s32 ret_val; 2169 u16 data; 2170 2171 2172 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); 2173 2174 if (!ret_val) 2175 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY) 2176 ? e1000_rev_polarity_reversed 2177 : e1000_rev_polarity_normal; 2178 2179 return ret_val; 2180} 2181 2182/** 2183 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY 2184 * @hw: pointer to the HW structure 2185 * 2186 * Calls the PHY setup function to force speed and duplex. Clears the 2187 * auto-crossover to force MDI manually. Waits for link and returns 2188 * successful if link up is successful, else -E1000_ERR_PHY (-2). 2189 **/ 2190s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw) 2191{ 2192 struct e1000_phy_info *phy = &hw->phy; 2193 s32 ret_val; 2194 u16 phy_data; 2195 bool link; 2196 2197 2198 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 2199 if (ret_val) 2200 goto out; 2201 2202 igb_phy_force_speed_duplex_setup(hw, &phy_data); 2203 2204 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 2205 if (ret_val) 2206 goto out; 2207 2208 /* 2209 * Clear Auto-Crossover to force MDI manually. 82580 requires MDI 2210 * forced whenever speed and duplex are forced. 2211 */ 2212 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); 2213 if (ret_val) 2214 goto out; 2215 2216 phy_data &= ~I82580_PHY_CTRL2_AUTO_MDIX; 2217 phy_data &= ~I82580_PHY_CTRL2_FORCE_MDI_MDIX; 2218 2219 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); 2220 if (ret_val) 2221 goto out; 2222 2223 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data); 2224 2225 udelay(1); 2226 2227 if (phy->autoneg_wait_to_complete) { 2228 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n"); 2229 2230 ret_val = igb_phy_has_link(hw, 2231 PHY_FORCE_LIMIT, 2232 100000, 2233 &link); 2234 if (ret_val) 2235 goto out; 2236 2237 if (!link) 2238 hw_dbg("Link taking longer than expected.\n"); 2239 2240 /* Try once more */ 2241 ret_val = igb_phy_has_link(hw, 2242 PHY_FORCE_LIMIT, 2243 100000, 2244 &link); 2245 if (ret_val) 2246 goto out; 2247 } 2248 2249out: 2250 return ret_val; 2251} 2252 2253/** 2254 * igb_get_phy_info_82580 - Retrieve I82580 PHY information 2255 * @hw: pointer to the HW structure 2256 * 2257 * Read PHY status to determine if link is up. If link is up, then 2258 * set/determine 10base-T extended distance and polarity correction. Read 2259 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2260 * determine on the cable length, local and remote receiver. 2261 **/ 2262s32 igb_get_phy_info_82580(struct e1000_hw *hw) 2263{ 2264 struct e1000_phy_info *phy = &hw->phy; 2265 s32 ret_val; 2266 u16 data; 2267 bool link; 2268 2269 2270 ret_val = igb_phy_has_link(hw, 1, 0, &link); 2271 if (ret_val) 2272 goto out; 2273 2274 if (!link) { 2275 hw_dbg("Phy info is only valid if link is up\n"); 2276 ret_val = -E1000_ERR_CONFIG; 2277 goto out; 2278 } 2279 2280 phy->polarity_correction = true; 2281 2282 ret_val = igb_check_polarity_82580(hw); 2283 if (ret_val) 2284 goto out; 2285 2286 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); 2287 if (ret_val) 2288 goto out; 2289 2290 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false; 2291 2292 if ((data & I82580_PHY_STATUS2_SPEED_MASK) == 2293 I82580_PHY_STATUS2_SPEED_1000MBPS) { 2294 ret_val = hw->phy.ops.get_cable_length(hw); 2295 if (ret_val) 2296 goto out; 2297 2298 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2299 if (ret_val) 2300 goto out; 2301 2302 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2303 ? e1000_1000t_rx_status_ok 2304 : e1000_1000t_rx_status_not_ok; 2305 2306 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2307 ? e1000_1000t_rx_status_ok 2308 : e1000_1000t_rx_status_not_ok; 2309 } else { 2310 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2311 phy->local_rx = e1000_1000t_rx_status_undefined; 2312 phy->remote_rx = e1000_1000t_rx_status_undefined; 2313 } 2314 2315out: 2316 return ret_val; 2317} 2318 2319/** 2320 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY 2321 * @hw: pointer to the HW structure 2322 * 2323 * Reads the diagnostic status register and verifies result is valid before 2324 * placing it in the phy_cable_length field. 2325 **/ 2326s32 igb_get_cable_length_82580(struct e1000_hw *hw) 2327{ 2328 struct e1000_phy_info *phy = &hw->phy; 2329 s32 ret_val; 2330 u16 phy_data, length; 2331 2332 2333 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data); 2334 if (ret_val) 2335 goto out; 2336 2337 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >> 2338 I82580_DSTATUS_CABLE_LENGTH_SHIFT; 2339 2340 if (length == E1000_CABLE_LENGTH_UNDEFINED) 2341 ret_val = -E1000_ERR_PHY; 2342 2343 phy->cable_length = length; 2344 2345out: 2346 return ret_val; 2347} 2348