mlx4.h revision 096335b3f9830b90d13aee77252cf6f5f12a258c
1/* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37#ifndef MLX4_H 38#define MLX4_H 39 40#include <linux/mutex.h> 41#include <linux/radix-tree.h> 42#include <linux/timer.h> 43#include <linux/semaphore.h> 44#include <linux/workqueue.h> 45 46#include <linux/mlx4/device.h> 47#include <linux/mlx4/driver.h> 48#include <linux/mlx4/doorbell.h> 49#include <linux/mlx4/cmd.h> 50 51#define DRV_NAME "mlx4_core" 52#define PFX DRV_NAME ": " 53#define DRV_VERSION "1.1" 54#define DRV_RELDATE "Dec, 2011" 55 56enum { 57 MLX4_HCR_BASE = 0x80680, 58 MLX4_HCR_SIZE = 0x0001c, 59 MLX4_CLR_INT_SIZE = 0x00008, 60 MLX4_SLAVE_COMM_BASE = 0x0, 61 MLX4_COMM_PAGESIZE = 0x1000 62}; 63 64enum { 65 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000, 66 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2), 67 MLX4_MTT_ENTRY_PER_SEG = 8, 68}; 69 70enum { 71 MLX4_NUM_PDS = 1 << 15 72}; 73 74enum { 75 MLX4_CMPT_TYPE_QP = 0, 76 MLX4_CMPT_TYPE_SRQ = 1, 77 MLX4_CMPT_TYPE_CQ = 2, 78 MLX4_CMPT_TYPE_EQ = 3, 79 MLX4_CMPT_NUM_TYPE 80}; 81 82enum { 83 MLX4_CMPT_SHIFT = 24, 84 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 85}; 86 87enum mlx4_mr_state { 88 MLX4_MR_DISABLED = 0, 89 MLX4_MR_EN_HW, 90 MLX4_MR_EN_SW 91}; 92 93#define MLX4_COMM_TIME 10000 94enum { 95 MLX4_COMM_CMD_RESET, 96 MLX4_COMM_CMD_VHCR0, 97 MLX4_COMM_CMD_VHCR1, 98 MLX4_COMM_CMD_VHCR2, 99 MLX4_COMM_CMD_VHCR_EN, 100 MLX4_COMM_CMD_VHCR_POST, 101 MLX4_COMM_CMD_FLR = 254 102}; 103 104/*The flag indicates that the slave should delay the RESET cmd*/ 105#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb 106/*indicates how many retries will be done if we are in the middle of FLR*/ 107#define NUM_OF_RESET_RETRIES 10 108#define SLEEP_TIME_IN_RESET (2 * 1000) 109enum mlx4_resource { 110 RES_QP, 111 RES_CQ, 112 RES_SRQ, 113 RES_XRCD, 114 RES_MPT, 115 RES_MTT, 116 RES_MAC, 117 RES_VLAN, 118 RES_EQ, 119 RES_COUNTER, 120 MLX4_NUM_OF_RESOURCE_TYPE 121}; 122 123enum mlx4_alloc_mode { 124 RES_OP_RESERVE, 125 RES_OP_RESERVE_AND_MAP, 126 RES_OP_MAP_ICM, 127}; 128 129 130/* 131 *Virtual HCR structures. 132 * mlx4_vhcr is the sw representation, in machine endianess 133 * 134 * mlx4_vhcr_cmd is the formalized structure, the one that is passed 135 * to FW to go through communication channel. 136 * It is big endian, and has the same structure as the physical HCR 137 * used by command interface 138 */ 139struct mlx4_vhcr { 140 u64 in_param; 141 u64 out_param; 142 u32 in_modifier; 143 u32 errno; 144 u16 op; 145 u16 token; 146 u8 op_modifier; 147 u8 e_bit; 148}; 149 150struct mlx4_vhcr_cmd { 151 __be64 in_param; 152 __be32 in_modifier; 153 __be64 out_param; 154 __be16 token; 155 u16 reserved; 156 u8 status; 157 u8 flags; 158 __be16 opcode; 159}; 160 161struct mlx4_cmd_info { 162 u16 opcode; 163 bool has_inbox; 164 bool has_outbox; 165 bool out_is_imm; 166 bool encode_slave_id; 167 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 168 struct mlx4_cmd_mailbox *inbox); 169 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 170 struct mlx4_cmd_mailbox *inbox, 171 struct mlx4_cmd_mailbox *outbox, 172 struct mlx4_cmd_info *cmd); 173}; 174 175#ifdef CONFIG_MLX4_DEBUG 176extern int mlx4_debug_level; 177#else /* CONFIG_MLX4_DEBUG */ 178#define mlx4_debug_level (0) 179#endif /* CONFIG_MLX4_DEBUG */ 180 181#define mlx4_dbg(mdev, format, arg...) \ 182do { \ 183 if (mlx4_debug_level) \ 184 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \ 185} while (0) 186 187#define mlx4_err(mdev, format, arg...) \ 188 dev_err(&mdev->pdev->dev, format, ##arg) 189#define mlx4_info(mdev, format, arg...) \ 190 dev_info(&mdev->pdev->dev, format, ##arg) 191#define mlx4_warn(mdev, format, arg...) \ 192 dev_warn(&mdev->pdev->dev, format, ##arg) 193 194extern int mlx4_log_num_mgm_entry_size; 195extern int log_mtts_per_seg; 196 197#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF) 198#define ALL_SLAVES 0xff 199 200struct mlx4_bitmap { 201 u32 last; 202 u32 top; 203 u32 max; 204 u32 reserved_top; 205 u32 mask; 206 u32 avail; 207 spinlock_t lock; 208 unsigned long *table; 209}; 210 211struct mlx4_buddy { 212 unsigned long **bits; 213 unsigned int *num_free; 214 int max_order; 215 spinlock_t lock; 216}; 217 218struct mlx4_icm; 219 220struct mlx4_icm_table { 221 u64 virt; 222 int num_icm; 223 int num_obj; 224 int obj_size; 225 int lowmem; 226 int coherent; 227 struct mutex mutex; 228 struct mlx4_icm **icm; 229}; 230 231/* 232 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. 233 */ 234struct mlx4_mpt_entry { 235 __be32 flags; 236 __be32 qpn; 237 __be32 key; 238 __be32 pd_flags; 239 __be64 start; 240 __be64 length; 241 __be32 lkey; 242 __be32 win_cnt; 243 u8 reserved1[3]; 244 u8 mtt_rep; 245 __be64 mtt_addr; 246 __be32 mtt_sz; 247 __be32 entity_size; 248 __be32 first_byte_offset; 249} __packed; 250 251/* 252 * Must be packed because start is 64 bits but only aligned to 32 bits. 253 */ 254struct mlx4_eq_context { 255 __be32 flags; 256 u16 reserved1[3]; 257 __be16 page_offset; 258 u8 log_eq_size; 259 u8 reserved2[4]; 260 u8 eq_period; 261 u8 reserved3; 262 u8 eq_max_count; 263 u8 reserved4[3]; 264 u8 intr; 265 u8 log_page_size; 266 u8 reserved5[2]; 267 u8 mtt_base_addr_h; 268 __be32 mtt_base_addr_l; 269 u32 reserved6[2]; 270 __be32 consumer_index; 271 __be32 producer_index; 272 u32 reserved7[4]; 273}; 274 275struct mlx4_cq_context { 276 __be32 flags; 277 u16 reserved1[3]; 278 __be16 page_offset; 279 __be32 logsize_usrpage; 280 __be16 cq_period; 281 __be16 cq_max_count; 282 u8 reserved2[3]; 283 u8 comp_eqn; 284 u8 log_page_size; 285 u8 reserved3[2]; 286 u8 mtt_base_addr_h; 287 __be32 mtt_base_addr_l; 288 __be32 last_notified_index; 289 __be32 solicit_producer_index; 290 __be32 consumer_index; 291 __be32 producer_index; 292 u32 reserved4[2]; 293 __be64 db_rec_addr; 294}; 295 296struct mlx4_srq_context { 297 __be32 state_logsize_srqn; 298 u8 logstride; 299 u8 reserved1; 300 __be16 xrcd; 301 __be32 pg_offset_cqn; 302 u32 reserved2; 303 u8 log_page_size; 304 u8 reserved3[2]; 305 u8 mtt_base_addr_h; 306 __be32 mtt_base_addr_l; 307 __be32 pd; 308 __be16 limit_watermark; 309 __be16 wqe_cnt; 310 u16 reserved4; 311 __be16 wqe_counter; 312 u32 reserved5; 313 __be64 db_rec_addr; 314}; 315 316struct mlx4_eqe { 317 u8 reserved1; 318 u8 type; 319 u8 reserved2; 320 u8 subtype; 321 union { 322 u32 raw[6]; 323 struct { 324 __be32 cqn; 325 } __packed comp; 326 struct { 327 u16 reserved1; 328 __be16 token; 329 u32 reserved2; 330 u8 reserved3[3]; 331 u8 status; 332 __be64 out_param; 333 } __packed cmd; 334 struct { 335 __be32 qpn; 336 } __packed qp; 337 struct { 338 __be32 srqn; 339 } __packed srq; 340 struct { 341 __be32 cqn; 342 u32 reserved1; 343 u8 reserved2[3]; 344 u8 syndrome; 345 } __packed cq_err; 346 struct { 347 u32 reserved1[2]; 348 __be32 port; 349 } __packed port_change; 350 struct { 351 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 352 u32 reserved; 353 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 354 } __packed comm_channel_arm; 355 struct { 356 u8 port; 357 u8 reserved[3]; 358 __be64 mac; 359 } __packed mac_update; 360 struct { 361 u8 port; 362 } __packed sw_event; 363 struct { 364 __be32 slave_id; 365 } __packed flr_event; 366 struct { 367 __be16 current_temperature; 368 __be16 warning_threshold; 369 } __packed warming; 370 } event; 371 u8 slave_id; 372 u8 reserved3[2]; 373 u8 owner; 374} __packed; 375 376struct mlx4_eq { 377 struct mlx4_dev *dev; 378 void __iomem *doorbell; 379 int eqn; 380 u32 cons_index; 381 u16 irq; 382 u16 have_irq; 383 int nent; 384 struct mlx4_buf_list *page_list; 385 struct mlx4_mtt mtt; 386}; 387 388struct mlx4_slave_eqe { 389 u8 type; 390 u8 port; 391 u32 param; 392}; 393 394struct mlx4_slave_event_eq_info { 395 int eqn; 396 u16 token; 397}; 398 399struct mlx4_profile { 400 int num_qp; 401 int rdmarc_per_qp; 402 int num_srq; 403 int num_cq; 404 int num_mcg; 405 int num_mpt; 406 int num_mtt; 407}; 408 409struct mlx4_fw { 410 u64 clr_int_base; 411 u64 catas_offset; 412 u64 comm_base; 413 struct mlx4_icm *fw_icm; 414 struct mlx4_icm *aux_icm; 415 u32 catas_size; 416 u16 fw_pages; 417 u8 clr_int_bar; 418 u8 catas_bar; 419 u8 comm_bar; 420}; 421 422struct mlx4_comm { 423 u32 slave_write; 424 u32 slave_read; 425}; 426 427enum { 428 MLX4_MCAST_CONFIG = 0, 429 MLX4_MCAST_DISABLE = 1, 430 MLX4_MCAST_ENABLE = 2, 431}; 432 433#define VLAN_FLTR_SIZE 128 434 435struct mlx4_vlan_fltr { 436 __be32 entry[VLAN_FLTR_SIZE]; 437}; 438 439struct mlx4_mcast_entry { 440 struct list_head list; 441 u64 addr; 442}; 443 444struct mlx4_promisc_qp { 445 struct list_head list; 446 u32 qpn; 447}; 448 449struct mlx4_steer_index { 450 struct list_head list; 451 unsigned int index; 452 struct list_head duplicates; 453}; 454 455#define MLX4_EVENT_TYPES_NUM 64 456 457struct mlx4_slave_state { 458 u8 comm_toggle; 459 u8 last_cmd; 460 u8 init_port_mask; 461 bool active; 462 u8 function; 463 dma_addr_t vhcr_dma; 464 u16 mtu[MLX4_MAX_PORTS + 1]; 465 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 466 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; 467 struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; 468 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; 469 /* event type to eq number lookup */ 470 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; 471 u16 eq_pi; 472 u16 eq_ci; 473 spinlock_t lock; 474 /*initialized via the kzalloc*/ 475 u8 is_slave_going_down; 476 u32 cookie; 477}; 478 479struct slave_list { 480 struct mutex mutex; 481 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; 482}; 483 484struct mlx4_resource_tracker { 485 spinlock_t lock; 486 /* tree for each resources */ 487 struct radix_tree_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; 488 /* num_of_slave's lists, one per slave */ 489 struct slave_list *slave_list; 490}; 491 492#define SLAVE_EVENT_EQ_SIZE 128 493struct mlx4_slave_event_eq { 494 u32 eqn; 495 u32 cons; 496 u32 prod; 497 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; 498}; 499 500struct mlx4_master_qp0_state { 501 int proxy_qp0_active; 502 int qp0_active; 503 int port_active; 504}; 505 506struct mlx4_mfunc_master_ctx { 507 struct mlx4_slave_state *slave_state; 508 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 509 int init_port_ref[MLX4_MAX_PORTS + 1]; 510 u16 max_mtu[MLX4_MAX_PORTS + 1]; 511 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; 512 struct mlx4_resource_tracker res_tracker; 513 struct workqueue_struct *comm_wq; 514 struct work_struct comm_work; 515 struct work_struct slave_event_work; 516 struct work_struct slave_flr_event_work; 517 spinlock_t slave_state_lock; 518 __be32 comm_arm_bit_vector[4]; 519 struct mlx4_eqe cmd_eqe; 520 struct mlx4_slave_event_eq slave_eq; 521 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; 522}; 523 524struct mlx4_mfunc { 525 struct mlx4_comm __iomem *comm; 526 struct mlx4_vhcr_cmd *vhcr; 527 dma_addr_t vhcr_dma; 528 529 struct mlx4_mfunc_master_ctx master; 530}; 531 532struct mlx4_cmd { 533 struct pci_pool *pool; 534 void __iomem *hcr; 535 struct mutex hcr_mutex; 536 struct semaphore poll_sem; 537 struct semaphore event_sem; 538 struct semaphore slave_sem; 539 int max_cmds; 540 spinlock_t context_lock; 541 int free_head; 542 struct mlx4_cmd_context *context; 543 u16 token_mask; 544 u8 use_events; 545 u8 toggle; 546 u8 comm_toggle; 547}; 548 549struct mlx4_uar_table { 550 struct mlx4_bitmap bitmap; 551}; 552 553struct mlx4_mr_table { 554 struct mlx4_bitmap mpt_bitmap; 555 struct mlx4_buddy mtt_buddy; 556 u64 mtt_base; 557 u64 mpt_base; 558 struct mlx4_icm_table mtt_table; 559 struct mlx4_icm_table dmpt_table; 560}; 561 562struct mlx4_cq_table { 563 struct mlx4_bitmap bitmap; 564 spinlock_t lock; 565 struct radix_tree_root tree; 566 struct mlx4_icm_table table; 567 struct mlx4_icm_table cmpt_table; 568}; 569 570struct mlx4_eq_table { 571 struct mlx4_bitmap bitmap; 572 char *irq_names; 573 void __iomem *clr_int; 574 void __iomem **uar_map; 575 u32 clr_mask; 576 struct mlx4_eq *eq; 577 struct mlx4_icm_table table; 578 struct mlx4_icm_table cmpt_table; 579 int have_irq; 580 u8 inta_pin; 581}; 582 583struct mlx4_srq_table { 584 struct mlx4_bitmap bitmap; 585 spinlock_t lock; 586 struct radix_tree_root tree; 587 struct mlx4_icm_table table; 588 struct mlx4_icm_table cmpt_table; 589}; 590 591struct mlx4_qp_table { 592 struct mlx4_bitmap bitmap; 593 u32 rdmarc_base; 594 int rdmarc_shift; 595 spinlock_t lock; 596 struct mlx4_icm_table qp_table; 597 struct mlx4_icm_table auxc_table; 598 struct mlx4_icm_table altc_table; 599 struct mlx4_icm_table rdmarc_table; 600 struct mlx4_icm_table cmpt_table; 601}; 602 603struct mlx4_mcg_table { 604 struct mutex mutex; 605 struct mlx4_bitmap bitmap; 606 struct mlx4_icm_table table; 607}; 608 609struct mlx4_catas_err { 610 u32 __iomem *map; 611 struct timer_list timer; 612 struct list_head list; 613}; 614 615#define MLX4_MAX_MAC_NUM 128 616#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) 617 618struct mlx4_mac_table { 619 __be64 entries[MLX4_MAX_MAC_NUM]; 620 int refs[MLX4_MAX_MAC_NUM]; 621 struct mutex mutex; 622 int total; 623 int max; 624}; 625 626#define MLX4_MAX_VLAN_NUM 128 627#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) 628 629struct mlx4_vlan_table { 630 __be32 entries[MLX4_MAX_VLAN_NUM]; 631 int refs[MLX4_MAX_VLAN_NUM]; 632 struct mutex mutex; 633 int total; 634 int max; 635}; 636 637#define SET_PORT_GEN_ALL_VALID 0x7 638#define SET_PORT_PROMISC_SHIFT 31 639#define SET_PORT_MC_PROMISC_SHIFT 30 640 641enum { 642 MCAST_DIRECT_ONLY = 0, 643 MCAST_DIRECT = 1, 644 MCAST_DEFAULT = 2 645}; 646 647 648struct mlx4_set_port_general_context { 649 u8 reserved[3]; 650 u8 flags; 651 u16 reserved2; 652 __be16 mtu; 653 u8 pptx; 654 u8 pfctx; 655 u16 reserved3; 656 u8 pprx; 657 u8 pfcrx; 658 u16 reserved4; 659}; 660 661struct mlx4_set_port_rqp_calc_context { 662 __be32 base_qpn; 663 u8 rererved; 664 u8 n_mac; 665 u8 n_vlan; 666 u8 n_prio; 667 u8 reserved2[3]; 668 u8 mac_miss; 669 u8 intra_no_vlan; 670 u8 no_vlan; 671 u8 intra_vlan_miss; 672 u8 vlan_miss; 673 u8 reserved3[3]; 674 u8 no_vlan_prio; 675 __be32 promisc; 676 __be32 mcast; 677}; 678 679struct mlx4_mac_entry { 680 u64 mac; 681}; 682 683struct mlx4_port_info { 684 struct mlx4_dev *dev; 685 int port; 686 char dev_name[16]; 687 struct device_attribute port_attr; 688 enum mlx4_port_type tmp_type; 689 char dev_mtu_name[16]; 690 struct device_attribute port_mtu_attr; 691 struct mlx4_mac_table mac_table; 692 struct radix_tree_root mac_tree; 693 struct mlx4_vlan_table vlan_table; 694 int base_qpn; 695}; 696 697struct mlx4_sense { 698 struct mlx4_dev *dev; 699 u8 do_sense_port[MLX4_MAX_PORTS + 1]; 700 u8 sense_allowed[MLX4_MAX_PORTS + 1]; 701 struct delayed_work sense_poll; 702}; 703 704struct mlx4_msix_ctl { 705 u64 pool_bm; 706 spinlock_t pool_lock; 707}; 708 709struct mlx4_steer { 710 struct list_head promisc_qps[MLX4_NUM_STEERS]; 711 struct list_head steer_entries[MLX4_NUM_STEERS]; 712 struct list_head high_prios; 713}; 714 715struct mlx4_priv { 716 struct mlx4_dev dev; 717 718 struct list_head dev_list; 719 struct list_head ctx_list; 720 spinlock_t ctx_lock; 721 722 struct list_head pgdir_list; 723 struct mutex pgdir_mutex; 724 725 struct mlx4_fw fw; 726 struct mlx4_cmd cmd; 727 struct mlx4_mfunc mfunc; 728 729 struct mlx4_bitmap pd_bitmap; 730 struct mlx4_bitmap xrcd_bitmap; 731 struct mlx4_uar_table uar_table; 732 struct mlx4_mr_table mr_table; 733 struct mlx4_cq_table cq_table; 734 struct mlx4_eq_table eq_table; 735 struct mlx4_srq_table srq_table; 736 struct mlx4_qp_table qp_table; 737 struct mlx4_mcg_table mcg_table; 738 struct mlx4_bitmap counters_bitmap; 739 740 struct mlx4_catas_err catas_err; 741 742 void __iomem *clr_base; 743 744 struct mlx4_uar driver_uar; 745 void __iomem *kar; 746 struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; 747 struct mlx4_sense sense; 748 struct mutex port_mutex; 749 struct mlx4_msix_ctl msix_ctl; 750 struct mlx4_steer *steer; 751 struct list_head bf_list; 752 struct mutex bf_mutex; 753 struct io_mapping *bf_mapping; 754 int reserved_mtts; 755}; 756 757static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) 758{ 759 return container_of(dev, struct mlx4_priv, dev); 760} 761 762#define MLX4_SENSE_RANGE (HZ * 3) 763 764extern struct workqueue_struct *mlx4_wq; 765 766u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); 767void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj); 768u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align); 769void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt); 770u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); 771int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, 772 u32 reserved_bot, u32 resetrved_top); 773void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); 774 775int mlx4_reset(struct mlx4_dev *dev); 776 777int mlx4_alloc_eq_table(struct mlx4_dev *dev); 778void mlx4_free_eq_table(struct mlx4_dev *dev); 779 780int mlx4_init_pd_table(struct mlx4_dev *dev); 781int mlx4_init_xrcd_table(struct mlx4_dev *dev); 782int mlx4_init_uar_table(struct mlx4_dev *dev); 783int mlx4_init_mr_table(struct mlx4_dev *dev); 784int mlx4_init_eq_table(struct mlx4_dev *dev); 785int mlx4_init_cq_table(struct mlx4_dev *dev); 786int mlx4_init_qp_table(struct mlx4_dev *dev); 787int mlx4_init_srq_table(struct mlx4_dev *dev); 788int mlx4_init_mcg_table(struct mlx4_dev *dev); 789 790void mlx4_cleanup_pd_table(struct mlx4_dev *dev); 791void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); 792void mlx4_cleanup_uar_table(struct mlx4_dev *dev); 793void mlx4_cleanup_mr_table(struct mlx4_dev *dev); 794void mlx4_cleanup_eq_table(struct mlx4_dev *dev); 795void mlx4_cleanup_cq_table(struct mlx4_dev *dev); 796void mlx4_cleanup_qp_table(struct mlx4_dev *dev); 797void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 798void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 799int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn); 800void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); 801int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); 802void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 803int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); 804void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); 805int __mlx4_mr_reserve(struct mlx4_dev *dev); 806void __mlx4_mr_release(struct mlx4_dev *dev, u32 index); 807int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index); 808void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index); 809u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); 810void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); 811 812int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 813 struct mlx4_vhcr *vhcr, 814 struct mlx4_cmd_mailbox *inbox, 815 struct mlx4_cmd_mailbox *outbox, 816 struct mlx4_cmd_info *cmd); 817int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, 818 struct mlx4_vhcr *vhcr, 819 struct mlx4_cmd_mailbox *inbox, 820 struct mlx4_cmd_mailbox *outbox, 821 struct mlx4_cmd_info *cmd); 822int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 823 struct mlx4_vhcr *vhcr, 824 struct mlx4_cmd_mailbox *inbox, 825 struct mlx4_cmd_mailbox *outbox, 826 struct mlx4_cmd_info *cmd); 827int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 828 struct mlx4_vhcr *vhcr, 829 struct mlx4_cmd_mailbox *inbox, 830 struct mlx4_cmd_mailbox *outbox, 831 struct mlx4_cmd_info *cmd); 832int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 833 struct mlx4_vhcr *vhcr, 834 struct mlx4_cmd_mailbox *inbox, 835 struct mlx4_cmd_mailbox *outbox, 836 struct mlx4_cmd_info *cmd); 837int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 838 struct mlx4_vhcr *vhcr, 839 struct mlx4_cmd_mailbox *inbox, 840 struct mlx4_cmd_mailbox *outbox, 841 struct mlx4_cmd_info *cmd); 842int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 843 struct mlx4_vhcr *vhcr, 844 struct mlx4_cmd_mailbox *inbox, 845 struct mlx4_cmd_mailbox *outbox, 846 struct mlx4_cmd_info *cmd); 847int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 848 int *base); 849void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 850int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 851void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 852int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 853int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 854 int start_index, int npages, u64 *page_list); 855 856void mlx4_start_catas_poll(struct mlx4_dev *dev); 857void mlx4_stop_catas_poll(struct mlx4_dev *dev); 858void mlx4_catas_init(void); 859int mlx4_restart_one(struct pci_dev *pdev); 860int mlx4_register_device(struct mlx4_dev *dev); 861void mlx4_unregister_device(struct mlx4_dev *dev); 862void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port); 863 864struct mlx4_dev_cap; 865struct mlx4_init_hca_param; 866 867u64 mlx4_make_profile(struct mlx4_dev *dev, 868 struct mlx4_profile *request, 869 struct mlx4_dev_cap *dev_cap, 870 struct mlx4_init_hca_param *init_hca); 871void mlx4_master_comm_channel(struct work_struct *work); 872void mlx4_gen_slave_eqe(struct work_struct *work); 873void mlx4_master_handle_slave_flr(struct work_struct *work); 874 875int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 876 struct mlx4_vhcr *vhcr, 877 struct mlx4_cmd_mailbox *inbox, 878 struct mlx4_cmd_mailbox *outbox, 879 struct mlx4_cmd_info *cmd); 880int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 881 struct mlx4_vhcr *vhcr, 882 struct mlx4_cmd_mailbox *inbox, 883 struct mlx4_cmd_mailbox *outbox, 884 struct mlx4_cmd_info *cmd); 885int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 886 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, 887 struct mlx4_cmd_mailbox *outbox, 888 struct mlx4_cmd_info *cmd); 889int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, 890 struct mlx4_vhcr *vhcr, 891 struct mlx4_cmd_mailbox *inbox, 892 struct mlx4_cmd_mailbox *outbox, 893 struct mlx4_cmd_info *cmd); 894int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 895 struct mlx4_vhcr *vhcr, 896 struct mlx4_cmd_mailbox *inbox, 897 struct mlx4_cmd_mailbox *outbox, 898 struct mlx4_cmd_info *cmd); 899int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 900 struct mlx4_vhcr *vhcr, 901 struct mlx4_cmd_mailbox *inbox, 902 struct mlx4_cmd_mailbox *outbox, 903 struct mlx4_cmd_info *cmd); 904int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 905 struct mlx4_vhcr *vhcr, 906 struct mlx4_cmd_mailbox *inbox, 907 struct mlx4_cmd_mailbox *outbox, 908 struct mlx4_cmd_info *cmd); 909int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 910 struct mlx4_vhcr *vhcr, 911 struct mlx4_cmd_mailbox *inbox, 912 struct mlx4_cmd_mailbox *outbox, 913 struct mlx4_cmd_info *cmd); 914int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 915 struct mlx4_vhcr *vhcr, 916 struct mlx4_cmd_mailbox *inbox, 917 struct mlx4_cmd_mailbox *outbox, 918 struct mlx4_cmd_info *cmd); 919int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 920 struct mlx4_vhcr *vhcr, 921 struct mlx4_cmd_mailbox *inbox, 922 struct mlx4_cmd_mailbox *outbox, 923 struct mlx4_cmd_info *cmd); 924int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 925 struct mlx4_vhcr *vhcr, 926 struct mlx4_cmd_mailbox *inbox, 927 struct mlx4_cmd_mailbox *outbox, 928 struct mlx4_cmd_info *cmd); 929int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 930 struct mlx4_vhcr *vhcr, 931 struct mlx4_cmd_mailbox *inbox, 932 struct mlx4_cmd_mailbox *outbox, 933 struct mlx4_cmd_info *cmd); 934int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 935 struct mlx4_vhcr *vhcr, 936 struct mlx4_cmd_mailbox *inbox, 937 struct mlx4_cmd_mailbox *outbox, 938 struct mlx4_cmd_info *cmd); 939int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 940 struct mlx4_vhcr *vhcr, 941 struct mlx4_cmd_mailbox *inbox, 942 struct mlx4_cmd_mailbox *outbox, 943 struct mlx4_cmd_info *cmd); 944int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 945 struct mlx4_vhcr *vhcr, 946 struct mlx4_cmd_mailbox *inbox, 947 struct mlx4_cmd_mailbox *outbox, 948 struct mlx4_cmd_info *cmd); 949int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 950 struct mlx4_vhcr *vhcr, 951 struct mlx4_cmd_mailbox *inbox, 952 struct mlx4_cmd_mailbox *outbox, 953 struct mlx4_cmd_info *cmd); 954int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 955 struct mlx4_vhcr *vhcr, 956 struct mlx4_cmd_mailbox *inbox, 957 struct mlx4_cmd_mailbox *outbox, 958 struct mlx4_cmd_info *cmd); 959int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 960 struct mlx4_vhcr *vhcr, 961 struct mlx4_cmd_mailbox *inbox, 962 struct mlx4_cmd_mailbox *outbox, 963 struct mlx4_cmd_info *cmd); 964 965int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); 966 967int mlx4_cmd_init(struct mlx4_dev *dev); 968void mlx4_cmd_cleanup(struct mlx4_dev *dev); 969int mlx4_multi_func_init(struct mlx4_dev *dev); 970void mlx4_multi_func_cleanup(struct mlx4_dev *dev); 971void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); 972int mlx4_cmd_use_events(struct mlx4_dev *dev); 973void mlx4_cmd_use_polling(struct mlx4_dev *dev); 974 975int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, 976 unsigned long timeout); 977 978void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); 979void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); 980 981void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); 982 983void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); 984 985void mlx4_handle_catas_err(struct mlx4_dev *dev); 986 987int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, 988 enum mlx4_port_type *type); 989void mlx4_do_sense_ports(struct mlx4_dev *dev, 990 enum mlx4_port_type *stype, 991 enum mlx4_port_type *defaults); 992void mlx4_start_sense(struct mlx4_dev *dev); 993void mlx4_stop_sense(struct mlx4_dev *dev); 994void mlx4_sense_init(struct mlx4_dev *dev); 995int mlx4_check_port_params(struct mlx4_dev *dev, 996 enum mlx4_port_type *port_type); 997int mlx4_change_port_types(struct mlx4_dev *dev, 998 enum mlx4_port_type *port_types); 999 1000void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); 1001void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); 1002 1003int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port); 1004/* resource tracker functions*/ 1005int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 1006 enum mlx4_resource resource_type, 1007 int resource_id, int *slave); 1008void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); 1009int mlx4_init_resource_tracker(struct mlx4_dev *dev); 1010 1011void mlx4_free_resource_tracker(struct mlx4_dev *dev); 1012 1013int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, 1014 struct mlx4_vhcr *vhcr, 1015 struct mlx4_cmd_mailbox *inbox, 1016 struct mlx4_cmd_mailbox *outbox, 1017 struct mlx4_cmd_info *cmd); 1018int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1019 struct mlx4_vhcr *vhcr, 1020 struct mlx4_cmd_mailbox *inbox, 1021 struct mlx4_cmd_mailbox *outbox, 1022 struct mlx4_cmd_info *cmd); 1023int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1024 struct mlx4_vhcr *vhcr, 1025 struct mlx4_cmd_mailbox *inbox, 1026 struct mlx4_cmd_mailbox *outbox, 1027 struct mlx4_cmd_info *cmd); 1028int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1029 struct mlx4_vhcr *vhcr, 1030 struct mlx4_cmd_mailbox *inbox, 1031 struct mlx4_cmd_mailbox *outbox, 1032 struct mlx4_cmd_info *cmd); 1033int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); 1034int mlx4_check_ext_port_caps(struct mlx4_dev *dev, u8 port); 1035 1036 1037int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1038 struct mlx4_vhcr *vhcr, 1039 struct mlx4_cmd_mailbox *inbox, 1040 struct mlx4_cmd_mailbox *outbox, 1041 struct mlx4_cmd_info *cmd); 1042 1043int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 1044 struct mlx4_vhcr *vhcr, 1045 struct mlx4_cmd_mailbox *inbox, 1046 struct mlx4_cmd_mailbox *outbox, 1047 struct mlx4_cmd_info *cmd); 1048int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1049 enum mlx4_protocol prot, enum mlx4_steer_type steer); 1050int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1051 int block_mcast_loopback, enum mlx4_protocol prot, 1052 enum mlx4_steer_type steer); 1053int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1054 struct mlx4_vhcr *vhcr, 1055 struct mlx4_cmd_mailbox *inbox, 1056 struct mlx4_cmd_mailbox *outbox, 1057 struct mlx4_cmd_info *cmd); 1058int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1059 struct mlx4_vhcr *vhcr, 1060 struct mlx4_cmd_mailbox *inbox, 1061 struct mlx4_cmd_mailbox *outbox, 1062 struct mlx4_cmd_info *cmd); 1063int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, 1064 int port, void *buf); 1065int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod, 1066 struct mlx4_cmd_mailbox *outbox); 1067int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, 1068 struct mlx4_vhcr *vhcr, 1069 struct mlx4_cmd_mailbox *inbox, 1070 struct mlx4_cmd_mailbox *outbox, 1071 struct mlx4_cmd_info *cmd); 1072int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, 1073 struct mlx4_vhcr *vhcr, 1074 struct mlx4_cmd_mailbox *inbox, 1075 struct mlx4_cmd_mailbox *outbox, 1076 struct mlx4_cmd_info *cmd); 1077int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 1078 struct mlx4_vhcr *vhcr, 1079 struct mlx4_cmd_mailbox *inbox, 1080 struct mlx4_cmd_mailbox *outbox, 1081 struct mlx4_cmd_info *cmd); 1082 1083int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); 1084int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); 1085 1086static inline void set_param_l(u64 *arg, u32 val) 1087{ 1088 *((u32 *)arg) = val; 1089} 1090 1091static inline void set_param_h(u64 *arg, u32 val) 1092{ 1093 *arg = (*arg & 0xffffffff) | ((u64) val << 32); 1094} 1095 1096static inline u32 get_param_l(u64 *arg) 1097{ 1098 return (u32) (*arg & 0xffffffff); 1099} 1100 1101static inline u32 get_param_h(u64 *arg) 1102{ 1103 return (u32)(*arg >> 32); 1104} 1105 1106static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) 1107{ 1108 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; 1109} 1110 1111#define NOT_MASKED_PD_BITS 17 1112 1113#endif /* MLX4_H */ 1114